diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..64b81a8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,28 @@ +# Build and Release Folders +bin-debug/ +bin-release/ +[Oo]bj/ +[Bb]in/ + +# Other files and folders +.settings/ + +# Executables +*.swf +*.air +*.ipa +*.apk +out/ +build/ +.xmake/ +*.o +.sconsign.dblite +__py_cache__/ + +# Project files, i.e. `.project`, `.actionScriptProperties` and `.flexProperties` +# should NOT be excluded as they contain compiler settings and other important +# information for Eclipse / Flash Builder. +/*.map +tools//PLAT/core/ld/ec618_0h00_flash.ld +/PLAT/core/ld/ec618_0h00_flash.ld +tools/ diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..3655eb1 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2019-2022 openLuat & AirM2M + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/PLAT/comdb.txt b/PLAT/comdb.txt new file mode 100644 index 0000000..53dfa70 --- /dev/null +++ b/PLAT/comdb.txt @@ -0,0 +1,8646 @@ +DbVersion +43205453,100 + +BuildInfo +The current data file was built by the Application Ver. 2.2.67.183, Mon Nov 21 22:23:21 2022 + +EnumVals +0,2048,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasMainEntrance_0,P_INFO,swLogPrintf("ICS MEAS of euArfcn %d will be started "); +0,4096,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasMainEntrance_1,P_ERROR,swLogPrintf("Incorrect ICS stage ( %d ) for new euArfcn arranged for ICS MEAS "); +0,6144,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasMainEntrance_2,P_INFO,swLogPrintf("ICS MEAS will be continued with stageChng = %d "); +0,10239,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasFrsContProc_1,P_INFO,swLogPrintf("ICS_STAGE_FRS_MEAS_CONN is continued without TASK_CFG "); +0,12287,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasLrsContProc_1,P_INFO,swLogPrintf("ICS_STAGE_LRS_MEAS_CONN is continued without TASK_CFG "); +0,14335,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasSssContProc_1,P_INFO,swLogPrintf("ICS_STAGE_SSS_MEAS is continued without TASK_CFG "); +0,14592,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasPostProc_1,P_INFO,swLogPrintf("cell delay ( %d ) of TDD intra cell ( PCI = %d ) is out of range "); +0,18431,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasPostProc_2,P_WARNING,swLogPrintf("skip post process of ICS MEAS because ICS_STAGE has been reset "); +0,20479,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasPssCandTimingRefine_1,P_INFO,swLogPrintf("Adjust PSS_POS to next half-frame "); +0,22527,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMeasIntProc_1,P_WARNING,swLogPrintf("ICS_STAGE_LRS_MEAS_CONN failed "); +0,22528,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDelAdjFreqAftMibDecoded_0,P_INFO,swLogPrintf("Delete EARFCN = %d "); +0,24576,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDelAdjFreqAftMibDecoded_1,P_INFO,swLogPrintf("Delete EARFCN = %d "); +0,27136,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyCellDetectedStore_0,P_INFO,swLogPrintf("New Cell ( %d , %d ) detected! cellNum = %d "); +0,30719,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyCellDetectedStore_1,P_WARNING,swLogPrintf("pCellDetected reached PHY_ICS_CELL_REPORTED_NUM! "); +0,30976,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyCellDetectedCheck_0,P_SIG,swLogPrintf("Cell ( %d , %d ) had beed reported , skip this time! "); +0,33024,0,0,PHY_ONLINE,PHY_ICS_MODULE,phyFreqListUpdt4DCXO,P_WARNING,swLogPrintf("DCXO used in extreme H / L temperature !!! , Current Temperature = %d , Cx Reliability = %d "); +0,35584,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsMsgValidityCheck_0,P_ERROR,swLogPrintf("CellSearchReq message check fail! numOfFreq = %d , numOfBand = %d , workMode = %d , phyCellId = %d "); +0,38911,0,0,PHY_ONLINE,PHY_ICS_MODULE,phyIcsHwTaskAdd_0,P_INFO,swLogPrintf("Cancel RSC task when close to Paging occassion! "); +0,40959,0,0,PHY_ONLINE,PHY_ICS_MODULE,phyIcsHwTaskAdd_2,P_WARNING,swLogPrintf("Ics Stage error when add ICS task! "); +0,41729,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_0,P_SIG,swLogPrintf("Start Cell Search : %s , numOfFreq = %d , numOfBand = %d , firstFreq = %d "); +0,43264,0,0,PHY_ONLINE,PHY_ICS_MODULE,IcsMsgProcess_1,P_ERROR,swLogPrintf("Too Many Band requested! numOfBand = %d , Separated BandNum = %d "); +0,45056,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_1,P_SIG,swLogPrintf("Start Fast ICS for EARFCN = %d "); +0,47104,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_2,P_SIG,swLogPrintf("Start Band Scan , EARFCN = %d "); +0,49932,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_7,P_SIG,swLogPrintf("Cell ( %d %d ) Detected! cpType = %s , SNR Level = %s "); +0,51968,0,0,PHY_ONLINE,PHY_ICS_MODULE,FreqScanInScoreList_1,P_INFO,swLogPrintf("Continue Frequency Scan in Score List [ %d ] , Current EARFCN : %d , Score = %d , numOfFreq = %d "); +0,53760,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_4_0,P_INFO,swLogPrintf("Retry preferred EARFCN : %d ( index : %d ) , currFreqIndex = %d "); +0,55552,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_4,P_SIG,swLogPrintf("Skip BandScan from start EARFCN : %d , maxScore = %d "); +0,57600,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_5,P_SIG,swLogPrintf("Start Frequency Scan in Band , Current EARFCN : %d , maxScore = %d "); +0,61439,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_6,P_SIG,swLogPrintf("Frequency Scan in Band Finished!!! "); +0,61440,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsCalcInvSqrtVar_2,P_INFO,swLogPrintf("sumCov < = sumPeakPow in workMode %d , "); +0,63488,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsCalcInvSqrtVar_3,P_INFO,swLogPrintf("wrong : sumCov < = powerPeak0 in workMode %d "); +0,65536,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsCalcInvSqrtVar_1,P_INFO,swLogPrintf("meanNoisePow < = meanNoise^2 in workMode %d "); +0,67840,0,0,PHY_ONLINE,PHY_ICS_MODULE,RscFreqListReSort,P_INFO,swLogPrintf("Start Resort Score List by FRS after RSC , numOfFreq = %d , first EARFCN ( by RSC ) = %d "); +0,70144,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_3_0,P_SIG,swLogPrintf("Start Frequency Scan in Score List , First EARFCN : %d , Score = %d , numOfFreq = %d "); +0,72192,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_3,P_SIG,swLogPrintf("Start Frequency Scan in Score List , First EARFCN : %d , Score = %d , numOfFreq = %d "); +0,75775,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_8,P_SIG,swLogPrintf("ICS High Level Frequency Done! "); +0,77823,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsFlow_9,P_ERROR,swLogPrintf("ICS High Level Frequency Done Report for BPLMN! "); +0,79871,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyIcsWaitTimerExpiredProc_0,P_SIG,swLogPrintf("Delay ICS when icsType is PHY_ICS_TYPE_REDIRECT_DELAY! "); +0,81919,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_0,P_WARNING,swLogPrintf("Unexpected DRX CS Req "); +0,83967,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_10,P_WARNING,swLogPrintf("PLMN Start with PCH task adding in advance ! "); +0,86015,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_11,P_WARNING,swLogPrintf("PLMN Start with PCH timer expired ! "); +0,88063,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_1,P_WARNING,swLogPrintf("PLMN Start signal received and handled when previous one is pending! "); +0,90111,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_2,P_WARNING,swLogPrintf("PLMN Start signal received and pended when previous one is pending! "); +0,92159,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxNextCsReqProcess_0,P_INFO,swLogPrintf("Start DRX Next Cell Search "); +0,94207,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxNextCsReqProcess_1,P_INFO,swLogPrintf("DRX Next Cell Search Pending "); +0,96255,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_3,P_SIG,swLogPrintf("Pending PLMN start after paging cycle! "); +0,98303,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_4,P_ERROR,swLogPrintf("drxNextCsFlag = = 1 when PLMN restarted after paging cycle! "); +0,100351,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_5,P_WARNING,swLogPrintf("PLMN STOP signal received when no PLMN is ongoing! "); +0,102399,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_6,P_SIG,swLogPrintf("PLMN STOP should wait for ICS INT! "); +0,104447,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_7,P_SIG,swLogPrintf("PLMN Stop signal handled! "); +0,106495,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_8,P_WARNING,swLogPrintf("Previous PLMN has not been started when STOPPED! "); +0,108543,0,0,PHY_ONLINE,PHY_ICS_MODULE,PhyDrxCs_9,P_WARNING,swLogPrintf("Pending PLMN start signal need to handle in next paging cycle! "); +0,109056,0,0,PHY_ONLINE,PHY_ICS_MODULE,phyRscScoring_0,P_INFO,swLogPrintf("centerEarfcn = %d , earfcnNum = %d , FeLoss = %d "); +1024,2099456,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_Sr,P_INFO,swLogPrintf("UL HARQ ( SchedulingRequest ) : SR activeTime = 0x%X , srCounter = %d "); +1024,2101760,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyRarTaCmd_0,P_WARNING,swLogPrintf("Invalid TA command received value = %d , counter = %d , currTA = %d "); +1024,2103296,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyRarTaCmd_1,P_WARNING,swLogPrintf("TA command received in RAR with large value ( %d ) ! "); +1024,2107391,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyAnCqiCollisionProcOverPucch1,P_INFO,swLogPrintf("AN_CQI Collision Proc "); +1024,2107392,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyAnRepTimesMaintain1,P_INFO,swLogPrintf("AN Rep Times Maintain , ackNackRepTimes = %d "); +1024,2109952,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxAprdCsiProc_0,P_ERROR,swLogPrintf("AprdCsi arrived later currTime ( hfnSfnSbn = 0x%X , spn = 0x%X ) , transTime = 0x%X "); +1024,2113535,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhySrsFindFirstUlSf_0,P_WARNING,swLogPrintf("The first SF should be UL when Prd > 5 ms "); +1024,2113536,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhySrsUeSpecificParamCheck_0,P_WARNING,swLogPrintf("No Available Sf For Configured SRS Subframe Offset , isPrdSrs = %d "); +1024,2115840,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhySrsFreqResAllocUpPts_0,P_INFO,swLogPrintf("SRS Symbol Flag Changed! , newSymFlag = 0x%x , symFlag = 0x%x "); +1024,2117632,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhySrsReqInfoInform_0,P_WARNING,swLogPrintf("No apSRS Configured , trigSource = %d "); +1024,2120192,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTaCheck_1,P_WARNING,swLogPrintf("Ta is out of range for TDD special subframe. dwPts = %d , ta = %d , init = %d ! "); +1024,2121984,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxHandleDlExtendRev_1,P_WARNING,swLogPrintf("Tx Tasks canceled due to Extended dwpts received. maxOsNum = %d , canceled Task = %d! "); +1024,2123776,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTtiBundingProc_1,P_WARNING,swLogPrintf("firstTxHarqId doesn ' t match schdHarqId ( %d ) "); +1024,2127106,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_Phich0,P_INFO,swLogPrintf("UL HARQ ( PHICH INFO ) : harqId = %d , HI = %s , mcs = %d , prb = %d , tbSizeInBytes = %d , currTxNb = %d "); +1024,2129154,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_Phich1,P_INFO,swLogPrintf("UL HARQ ( PHICH INFO ) : harqId = %d , HI = %s , mcs = %d , prb = %d , tbSizeInBytes = %d , currTxNb = %d "); +1024,2131967,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_DciGrantParse_0,P_WARNING,swLogPrintf("Csi Request but no APR CSI Para Configured "); +1024,2132992,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_DciInfo0,P_INFO,swLogPrintf("UL HARQ ( DCI0 Info ) : harqId = %d , mcs = %d , prb = %d , tbSizeInBytes = %d , transmissionType = %d "); +1024,2135040,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_DciInfo1,P_INFO,swLogPrintf("UL HARQ ( DCI0 Info ) : harqId = %d , mcs = %d , prb = %d , tbSizeInBytes = %d , transmissionType = %d "); +1024,2136832,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyUlHarq_DciInfo2,P_WARNING,swLogPrintf("UL DCI detection invalid!!! crnti = %e , spsrnti = %e , tmprnti = %e , bakcrnti = %e "); +1024,2140159,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxTpuTimer4Cfg_0,P_INFO,swLogPrintf("Stop TX RTN "); +1024,2142207,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxTpuTimer4Cfg_2,P_INFO,swLogPrintf("TX RTN is stopped , no need to stop again! "); +1024,2144255,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxTpuTimer4Cfg_1,P_INFO,swLogPrintf("Start TX RTN "); +1024,2146303,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxTpuTimer4Cfg_3,P_INFO,swLogPrintf("TX RTN is started , no need to start again! "); +1024,2147072,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyTxInfoCreate_0,P_ERROR,swLogPrintf("Tx Related Dynamic Data are not PNULL when IDLE2CONN , PhyDynMemBmpGet ( ) ->bmpVal = 0x%X , gpPhyUlStaticPara = 0x%X , gpPhyTxSchdInfo = 0x%X , gpPhyTxHwParam = 0x%X "); +1024,2148864,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyTxInfoCreate_1,P_ERROR,swLogPrintf("TX dynamic mem allocate fail! gpPhyUlStaticPara = 0x%X , gpPhyTxSchdInfo = 0x%X , gpPhyTxHwParam = 0x%X "); +1024,2151168,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,phyTxInfoRelease,P_ERROR,swLogPrintf("Tx Related Dynamic Data are PNULL when CONN2IDLE , PhyDynMemBmpGet ( ) ->bmpVal = 0x%X , gpPhyUlStaticPara = 0x%X , gpPhyTxSchdInfo = 0x%X , gpPhyTxHwParam = 0x%X "); +1024,2152448,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxScheduleWrapper_0,P_WARNING,swLogPrintf("TxScheduleWrapper re-trigger for hfnSfnSbn = 0x%X "); +1024,2154752,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxScheduleWrapper_1,P_ERROR,swLogPrintf("Miss calling of TxScheduleWrapper for txHfnSfnSbn = 0x%X , missed subframe num = %d "); +1024,2156800,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxScheduler_0,P_WARNING,swLogPrintf("chanMode = %d is cannceled due to large tailZeros = %d! "); +1024,2159616,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxPowerPrint_1,P_INFO,swLogPrintf("type = 0x%x ( Bit3 : SRS , Bit2 : PUCCH , Bit1 : PUSCH , Bit0 : PRACH ) , SrsPower = %d ( dBm ) , PucchPower = %d ( dBm ) , PuschPower = %d ( dBm ) , PrachPower = %d ( dBm ) "); +1024,2161664,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxPowerPrint_0,P_INFO,swLogPrintf("type = 0x%x ( Bit3 : SRS , Bit2 : PUCCH , Bit1 : PUSCH , Bit0 : PRACH ) , SrsPower = %d ( dBm ) , PucchPower = %d ( dBm ) , PuschPower = %d ( dBm ) , PrachPower = %d ( dBm ) "); +1024,2164735,0,0,PHY_ONLINE,PHY_ULPATH_MODULE,PhyTxCancelAll_0,P_INFO,swLogPrintf("PhyTxCancelAll! "); +2048,4196352,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,DcCheckError,P_ERROR,swLogPrintf("DC : max = %d "); +2048,4198400,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,DcCheckWarn,P_WARNING,swLogPrintf("DC : max = %d "); +2048,4200448,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,DcCheckSig,P_SIG,swLogPrintf("DC : max = %d "); +2048,4202496,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,DcCheckInfo,P_INFO,swLogPrintf("DC : max = %d "); +2048,4204544,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,WarnNDetSpurN0,P_WARNING,swLogPrintf("SpurEst : nDetSpur = %d @ PhyRxDFENotchPreCalc ( ) "); +2048,4206592,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,WarnNDetSpurN1,P_WARNING,swLogPrintf("SpurEst : nDetSpur = %d @ PhyRxDFENotchPreCalc ( ) "); +2048,4210687,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,PhyRxDFESpurEstProc_0,P_WARNING,swLogPrintf("skip RxDFE spur est. process "); +2048,4210688,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,PhyRxDFESpurEstProc_1,P_INFO,swLogPrintf("Add RxDFE algorithm para. reconfiguration with startTime of 0x%X "); +2048,4212736,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,WarnNDetSpurS0,P_WARNING,swLogPrintf("SpurEst : nDetSpur = %d @ PhyRxDFESpurEstProc ( ) "); +2048,4214784,0,0,PHY_ONLINE,PHY_RXDFE_MODULE,RcCalibWarn,P_WARNING,swLogPrintf("RC Calib : finalErr = %d / 256 , which is too great. "); +3072,6295551,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeHwConfig_2,P_INFO,swLogPrintf("no CE registers need be configured in TASK CFG INT "); +3072,6297599,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeAxcHoldRelease_1,P_INFO,swLogPrintf("AXC hold is released "); +3072,6299647,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeSpurEstProc_1,P_WARNING,swLogPrintf("skip spurEst process because spurAccuNum is 0 "); +3072,6301695,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeHwResultsRead_1,P_ERROR,swLogPrintf("unexpected axcHold4SwRead with value zero in CEAXC ISR "); +3072,6303743,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeAxcPostEarlyReturnCheck_1,P_WARNING,swLogPrintf("skip CeAxc post process if mac reset process is ongoing "); +3072,6303744,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeAxcPostEarlyReturnCheck_2,P_WARNING,swLogPrintf("skip CeAxc post process because that of previous ISR ( HFNSFNSBN = 0x%X ) has NOT been done "); +3072,6305792,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeAxcPostEarlyReturnCheck_3,P_INFO,swLogPrintf("skip CeAxc post process because that of previous ISR ( HFNSFNSBN = 0x%X ) has just been done "); +3072,6309887,0,0,PHY_ONLINE,PHY_CE_MODULE,PhyCeAxcExtraProc4Cdrx_1,P_INFO,swLogPrintf("extra CEAXC process for CDRX will be triggered "); +4096,8390656,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiSwTrgConfig_1,P_INFO,swLogPrintf("CSI is triggered by SW with configured parameter 0x%X "); +4096,8394751,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiParaInit_1,P_INFO,swLogPrintf("skip CSI reconfiguration "); +4096,8395264,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiContCnfgProc_aprd,P_ERROR,swLogPrintf("Invalid aperiodic CSI in pending list when configuring continuous CSI calculation ( calcTime = 0x%X , ulTime = 0x%X , currTime = 0x%X ) "); +4096,8397312,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiContCnfgProc_prd,P_ERROR,swLogPrintf("Invalid periodic CSI in pending list when configuring continuous CSI calculation ( calcTime = 0x%X , ulTime = 0x%X , currTime = 0x%X ) "); +4096,8400895,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiTypeValidityCheck_0,P_WARNING,swLogPrintf("skip CSI INT during HO MIB process "); +4096,8401152,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiTypeValidityCheck_1,P_INFO,swLogPrintf("unexpected CSI HW results ( SW-%d , HW-%d ) "); +4096,8404991,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiIsr_1,P_INFO,swLogPrintf("txTime of PRD_CSI is from SW "); +4096,8404992,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiCqiFiltOnOffCtrl_1,P_INFO,swLogPrintf("CQI SW filter on-off status changed to %d "); +4096,8407296,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiDci0InfoGet_0,P_ERROR,swLogPrintf("invalid 2 -bit CSI request ( 0x%X ) of subframe set %d in DCI0 "); +4096,8409088,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiDci0InfoGet_3,P_WARNING,swLogPrintf("existed RAR CSI > new DCI0 CSI ( SET%d ) "); +4096,8413183,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiDci0InfoGet_4,P_WARNING,swLogPrintf("existed DCI0 CSI ( SET0 ) > new DCI0 CSI ( SET1 ) "); +4096,8415231,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiDci0InfoGet_5,P_WARNING,swLogPrintf("new DCI0 CSI ( SET0 ) > existed DCI0 CSI ( SET1 ) "); +4096,8417279,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiPeriodicCalcInsert_1,P_INFO,swLogPrintf("transmission time of Inserted periodic CSI conflicted with that of existed aperiodic one "); +4096,8419327,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiPeriodicCalcInsert_2,P_INFO,swLogPrintf("transmission time of Inserted periodic CSI conflicted with RX gap "); +4096,8421375,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRarInfoGet_1,P_WARNING,swLogPrintf("aperiodic CSI request was scheduled in RAR "); +4096,8423423,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRarInfoGet_4,P_WARNING,swLogPrintf("new RAR CSI > existed RAR CSI "); +4096,8423424,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRarInfoGet_5,P_WARNING,swLogPrintf("new RAR CSI > existed DCI0 CSI ( SET%d ) "); +4096,8427519,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRxGapCalcScan_1,P_WARNING,swLogPrintf("too many periodic CSI calculation in the pending list "); +4096,8429567,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRxGapCalcScan_2,P_WARNING,swLogPrintf("too many periodic CSI calculation in RX gap "); +4096,8429568,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRxGapCalcScan_3,P_INFO,swLogPrintf("%d periodic CSI calculation will be executed for RX gap "); +4096,8433663,0,0,PHY_ONLINE,PHY_CSI_MODULE,PhyCsiRxGapCalcScan_4,P_WARNING,swLogPrintf("pending list of periodic CSI calculation is full "); +5120,10487808,0,0,PHY_ONLINE,PHY_DEC_MODULE,PhyDlHarqTypeInit1,P_WARNING,swLogPrintf("L2Buffer not process yet and harqId is %d "); +5120,10490112,0,0,PHY_ONLINE,PHY_DEC_MODULE,PhyDlHarqTypeInit0,P_WARNING,swLogPrintf("dec Isr triggered and task not finished , harqId0 = %d and harqId1 = %d "); +5120,10493951,0,0,PHY_ONLINE,PHY_DEC_MODULE,PhySaveNormalGrant2Harq_SPS,P_VALUE,swLogPrintf("invalid SPS retransmission or false DCI "); +5120,10494464,0,0,PHY_ONLINE,PHY_DEC_MODULE,phyDlHarq_DciInfo,P_INFO,swLogPrintf("DL HARQ ( Ack2Nack ) : harqId = %d , mcs = %d , prb = %d "); +5120,10498047,0,0,PHY_ONLINE,PHY_DEC_MODULE,phyDlHarq_DciInfo1,P_WARNING,swLogPrintf("URS PRBs collide with PBCH or SS , just skip decoding "); +5120,10500095,0,0,PHY_ONLINE,PHY_DEC_MODULE,PhyDecDynamicConfig_OneCB,P_WARNING,swLogPrintf("oneCb codeRate > 94 % "); +5120,10502143,0,0,PHY_ONLINE,PHY_DEC_MODULE,PhyDecDynamicConfig_NormalCB,P_WARNING,swLogPrintf("normal CB codeRate > 94 % "); +5120,10502400,0,0,PHY_ONLINE,PHY_DEC_MODULE,PhyDecApplyL2Buffer,P_ERROR,swLogPrintf("No L2Buffer for DL data , harqId is %d and fail cnt is %d "); +5120,10506239,0,0,PHY_ONLINE,PHY_DEC_MODULE,phyDlHarq_DecInfo_3,P_VALUE,swLogPrintf("SIB1 decode fail! "); +5120,10508287,0,0,PHY_ONLINE,PHY_DEC_MODULE,phyDlHarq_DecInfo_2,P_VALUE,swLogPrintf("SIBX decode fail! "); +5120,10510335,0,0,PHY_ONLINE,PHY_DEC_MODULE,phyDlHarq_DecInfo_1,P_WARNING,swLogPrintf("RAR decode fail! "); +5120,10511648,0,0,PHY_ONLINE,PHY_DEC_MODULE,phyDlHarq_DecInfo,P_INFO,swLogPrintf("DL HARQ ( DEC Info ) : harqId = %d , mcs = %d , prb = %d , retxCnt = %d , tbSizeInBytes = %d , crc = %s "); +6144,12585216,0,0,PHY_ONLINE,PHY_DCH_MODULE,demRegPrint,P_SIG,swLogPrintf("DEM status is 0x%X , 0x%X "); +6144,12589055,0,0,PHY_ONLINE,PHY_DCH_MODULE,PhySaveOneCbGrant2Harq,P_INFO,swLogPrintf("invalid oneCb , discard it "); +7168,14682368,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyTestCaseFor83128,P_WARNING,swLogPrintf("debug for CT case 8.300000 .1.28 with CchEna = %d , DchEna = %d "); +7168,14686207,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyCchBasicInfoGet,P_WARNING,swLogPrintf("ul BW larger than dl BW "); +7168,14688255,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyCchLlrFwlAdjust_1,P_INFO,swLogPrintf("adjust llr FWL of CCH "); +7168,14690303,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyPhichRemoveFwl_0,P_WARNING,swLogPrintf("PHICH0 hw result error! "); +7168,14692351,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyPhichRemoveFwl_1,P_WARNING,swLogPrintf("PHICH1 hw result error! "); +7168,14692608,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyCchTask_0,P_WARNING,swLogPrintf("Received PDCCH order when RA is ongoing! raCause = %d , raStage = %d "); +7168,14696447,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyDciCreditCheck,P_VALUE,swLogPrintf("snr change >6 dB , init credit value "); +7168,14698495,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_HW20,P_VALUE,swLogPrintf("scNcFlag error! "); +7168,14700543,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_HW00,P_WARNING,swLogPrintf("receive grant ( not SI / P ) in CDRX inactive! "); +7168,14700800,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_HW0,P_SIG,swLogPrintf("PDCCH ORDER detected , DCI is [ 0x%X , 0x%X ] "); +7168,14704639,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_SI1,P_INFO,swLogPrintf("SI received and not decode yet1 "); +7168,14706687,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_SI2,P_INFO,swLogPrintf("SI received and not decode yet2 "); +7168,14708735,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_HW1,P_WARNING,swLogPrintf("invalid tempCrnti DL / UL grant "); +7168,14710783,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_RA1,P_INFO,swLogPrintf("RAR received and not decode yet1 "); +7168,14712831,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_RA2,P_INFO,swLogPrintf("RAR received and not decode yet2 "); +7168,14714879,0,0,PHY_ONLINE,PHY_CCH_MODULE,DCI_VALIDATE_RA3,P_WARNING,swLogPrintf("Duplicated RAR Received! "); +7168,14716416,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyDciHwInfoGet,P_VALUE,swLogPrintf("DCI discard Hw info is [ 0 ] : 0x%X , [ 1 ] : 0x%X , [ 2 ] : 0x%X , creditValue = 0x%X , threshold = 0x%X , cbsizeType = %d , cceLvl = %d "); +7168,14718975,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyParseFormat3Info_0,P_ERROR,swLogPrintf("PUCCH TPC index error! "); +7168,14721023,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseSpsActive,P_SIG,swLogPrintf("SPS grant active "); +7168,14723071,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseSpsRelease,P_SIG,swLogPrintf("SPS grant release "); +7168,14725119,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyDciPadingDataCheck0,P_VALUE,swLogPrintf("pading not 0 , discard it "); +7168,14725376,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyDciPadingDataCheck1,P_VALUE,swLogPrintf("pading length < 0 , dciData = 0x%x , padinglength = %d "); +7168,14727424,0,0,PHY_ONLINE,PHY_CCH_MODULE,PHY_CCH_LOG_DCI_PARA_ERR1,P_WARNING,swLogPrintf("Cell parameter mismatch1 , data1 = 0x%X and data2 = 0x%X "); +7168,14731263,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt1ASb,P_WARNING,swLogPrintf("distributed type2 resource PRB too large ( < 50 RB ) "); +7168,14733311,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt1AWb,P_WARNING,swLogPrintf("distributed type2 resource PRB too large ( > = 50 RB ) "); +7168,14735359,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt1BSb,P_WARNING,swLogPrintf("distributed type2 resource PRB too large ( < 50 RB ) "); +7168,14737407,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt1BWb,P_WARNING,swLogPrintf("distributed type2 resource PRB too large ( > = 50 RB ) "); +7168,14739455,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt2,P_WARNING,swLogPrintf("format2 two CW all enable or disable "); +7168,14741503,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt21,P_WARNING,swLogPrintf("pPhyDciParsdInfo->tpmiInfo error "); +7168,14743551,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt2A,P_WARNING,swLogPrintf("format2 two CW all enable or disable "); +7168,14745599,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt2A1,P_WARNING,swLogPrintf("pPhyDciParsdInfo->tpmiInfo error "); +7168,14747647,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt2B,P_WARNING,swLogPrintf("format2 two CW all enable or disable "); +7168,14749695,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt2C,P_WARNING,swLogPrintf("format2 two CW all enable or disable "); +7168,14751743,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyParseOneCbValidation,P_VALUE,swLogPrintf("special subframe "); +7168,14753791,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyParseOneCbValidation1,P_VALUE,swLogPrintf("mbsfn subframe "); +7168,14754048,0,0,PHY_ONLINE,PHY_CCH_MODULE,PHY_CCH_LOG_DCI_PARA_ERR,P_WARNING,swLogPrintf("Cell parameter mismatch , data1 = 0x%X and data2 = 0x%X "); +7168,14757887,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseFmt1AMcs,P_WARNING,swLogPrintf("oneCb grant with format1A too large "); +7168,14759935,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyDlDciValidation_TBSIZE,P_WARNING,swLogPrintf("tbsize too large or false DCI "); +7168,14761983,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseDiscard_2,P_VALUE,swLogPrintf("discard a new grant with RV not 0 "); +7168,14764031,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseDiscard_0,P_VALUE,swLogPrintf("maybe DL grant of newTrans missed or false DCI detected "); +7168,14764032,0,0,PHY_ONLINE,PHY_CCH_MODULE,phyDciParseDiscard_1,P_INFO,swLogPrintf("dci discard dueto 0x%X "); +7168,14768127,0,0,PHY_ONLINE,PHY_CCH_MODULE,PhyGpsDumpTest,P_VALUE,swLogPrintf("start Api Dump test "); +9216,18876672,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAfcNormFactorCalc_1,P_ERROR,swLogPrintf("Unexpected numerator ( %d ) or denominator ( %d ) in AFC normalized factor calculation "); +9216,18880511,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAfcOffsetCalc_1,P_ERROR,swLogPrintf("Incorrect normFactor when calculating freqOffset "); +9216,18882559,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAfcAdjFreqOfstDeterm_1,P_ERROR,swLogPrintf("no valid raw result for determining freqOfstAdj of HST mode "); +9216,18882560,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAtcAdjustProc_0,P_WARNING,swLogPrintf("RxTimingAdjust while TxTiming do not adjust! rxAdjAcc = %d "); +9216,18884608,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAtcPostProc_1,P_WARNING,swLogPrintf("clear previous non-zero ATC adjusted info. ( 0x%X ) "); +9216,18888703,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAtcStatusGetInTaskCfg_11,P_WARNING,swLogPrintf("CE_BIT of ATC is delayed to RX_RESUME after 1 st inter PSS MEAS STEP1 "); +9216,18890751,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAtcStatusGetInTaskCfg_12,P_WARNING,swLogPrintf("CE_BIT of ATC is delayed to SCELL HW tasks in CDRX INACT duration "); +9216,18892799,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAtcStatusGetInTaskCfg_21,P_WARNING,swLogPrintf("timeOfstAdj of sys_RT has NOT been loaded when ICS flow starts to work "); +9216,18894847,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAtcStatusGetInTaskCfg_22,P_WARNING,swLogPrintf("only timeOfstAdj of CE has NOT been taken effect when ICS flow starts to work "); +9216,18896895,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAxcSpdEstDataStore_1,P_WARNING,swLogPrintf("new speed est. data is invalid "); +9216,18896896,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAxcSpdEstDataStore_2,P_WARNING,swLogPrintf("speed est. array overflow ( arrIdx = %d ) "); +9216,18898944,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAxcSpdLvlDeterm_1,P_WARNING,swLogPrintf("data array of speed estimation ( lastEstTime is 0x%X ) is full!!! "); +9216,18901248,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyAxcSpdLvlDeterm_2,P_INFO,swLogPrintf("currSpdLvl = %d , nextSpdLvl = %d "); +9216,18903296,0,0,PHY_ONLINE,PHY_AXC_MODULE,PhyCeSnrLvlSet_1,P_INFO,swLogPrintf("currSnrLvl = %d , nextSnrLvl = %d "); +10240,20973568,0,0,PHY_ONLINE,PHY_RF_MODULE,RfUnitTest_1,P_SIG,swLogPrintf("data : 0x%x "); +10240,20976128,0,0,PHY_ONLINE,PHY_RF_MODULE,RfUnitTest_wr_rd_regs,P_SIG,swLogPrintf("regAddr = 0x%x , WrVal = 0x%x , RdVal = 0x%x "); +10240,20977920,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcRxOnOff1ms,P_SIG,swLogPrintf("freq100KHz = %d , rssi = %d "); +10240,20980736,0,0,PHY_ONLINE,PHY_RF_MODULE,RfRxSemiStaticCfg,P_WARNING,swLogPrintf("freqCfg Miss , scNcInd = %d , scFreqPreCalc = %d , scFreqCfg = %d , ncFreqPreCalc = %d , ncFreqCfg = %d "); +10240,20982272,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSwMipiRegsPrint_1,P_INFO,swLogPrintf("SwSend ECS Reg%d , Addr = 0x%x , Val = 0x%x "); +10240,20984320,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSwMipiRegsPrint_2,P_INFO,swLogPrintf("SwSend ELCS Reg%d , Addr = 0x%x , Val = 0x%x "); +10240,20986368,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSwMipiRegsPrint_3,P_INFO,swLogPrintf("SwSend Reg%d , Addr = 0x%x , Val = 0x%x "); +10240,20988160,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSwMipiRegsPrint_4,P_INFO,swLogPrintf("SwSend Said = 0x%x , regsLenTotal = %d "); +10240,20990976,0,0,PHY_ONLINE,PHY_RF_MODULE,RfCaliTableInit_1,P_VALUE,swLogPrintf("fcVersion1 = 0x%x , fcVersion2 = 0x%x , fcVersion3 = 0x%x , hwInfo1 = 0x%x , hwInfo2 = 0x%x "); +10240,20993792,0,0,PHY_ONLINE,PHY_RF_MODULE,RfCaliTableInit_4,P_SIG,swLogPrintf("Rf Init FreqOfst = %d ( loFreq = %d ) , CBANK = %d ( %d ) , t0 = %d ( C ) , t0Code = %d , 32 KCap = %d ( %d ) "); +10240,20996095,0,0,PHY_ONLINE,PHY_RF_MODULE,RfCaliTableInit_6,P_ERROR,swLogPrintf("Need to do RF Calibration! "); +10240,20996352,0,0,PHY_ONLINE,PHY_RF_MODULE,RfCaliTableInit_2,P_VALUE,swLogPrintf("RxRc = 0x%x , TxRc = 0x%x "); +10240,20999680,0,0,PHY_ONLINE,PHY_RF_MODULE,RfCaliTableInit_3,P_VALUE,swLogPrintf("SarAdcOfstI0 / I1 = 0x%x / 0x%x , SarAdcOfstQ0 / Q1 = 0x%x / 0x%x , SarAdcGainI / Q = 0x%x / 0x%x , SarAdcskew = 0x%x "); +10240,21001472,0,0,PHY_ONLINE,PHY_RF_MODULE,RfCaliTableInit_5,P_SIG,swLogPrintf("Addr = 0x%x , 0x%x , 0x%x , 0x%x , 0x%x , 0x%x "); +10240,21003264,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxTpcCmd,P_INFO,swLogPrintf("Rf TxTpcCmd : txPowrOrg = %d , currTxPowr = %d , tpcDaIdx = %d , paIdx = %d , powerErr = %d "); +10240,21004800,0,0,PHY_ONLINE,PHY_RF_MODULE,RfRxFecParasCalc,P_WARNING,swLogPrintf("RxFront-End Paras Miss , bandPosIdx = 0x%x , oflValid = %d , bandnum = %d "); +10240,21006848,0,0,PHY_ONLINE,PHY_RF_MODULE,RfRxFecParasCalc_1,P_INFO,swLogPrintf("RxPath Config : bandNum = %d , freq100Hz = %d , rxPort = %e "); +10240,21009152,0,0,PHY_ONLINE,PHY_RF_MODULE,RfRxCaliParasCalc_0,P_WARNING,swLogPrintf("LTE Band RxCalibration Paras Miss , bandPosIdx = 0x%x , scValid = %d , fcValid = %d , bandnum = %d "); +10240,21011200,0,0,PHY_ONLINE,PHY_RF_MODULE,RfRxCaliParasCalc_1,P_WARNING,swLogPrintf("WIFI Band RxCalibration Paras Miss , bandPosIdx = 0x%x , scValid = %d , fcValid = %d , bandnum = %d "); +10240,21013504,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxFecParasCalc_1,P_INFO,swLogPrintf("freq100KHz = %d , freq100KHzEnd = %d , tmprtCmpstIdx = %d , cmpVal = %d , cmpVal2 = %d "); +10240,21015040,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxFecParasCalc,P_WARNING,swLogPrintf("TxFront-End Paras Miss , bandPosIdx = 0x%x , oflValid = %d , bandnum = %d "); +10240,21017600,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxFecParasCalc_2,P_INFO,swLogPrintf("TxPath Config : bandNum = %d , freq100Hz = %d , txPort = %e , paOnAdvTime = %d ( unit : 30.720000 cycles ) , paBiasNum = %d "); +10240,21019648,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxCaliParasCalc_3,P_SIG,swLogPrintf("TxIqmResult , freq = %d , band : %d , cmd0 = 0x%x , cmd1 = 0x%x , Index = %d "); +10240,21021184,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxCaliParasCalc_4,P_INFO,swLogPrintf("Band = %d , freqCompTmprt_high = %d , freqCompTmprt_low = %d "); +10240,21022720,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxCaliParasCalc_1,P_WARNING,swLogPrintf("TxTpcTable Miss , bandNum = %d "); +10240,21025792,0,0,PHY_ONLINE,PHY_RF_MODULE,RfTxCaliParasCalc_2,P_WARNING,swLogPrintf("TxCalibration Paras Miss , bandPosIdx1 = 0x%x , bandPosIdx2 = 0x%x , scValid = %d , fcValid = %d , bandNum = %d "); +10240,21027072,0,0,PHY_ONLINE,PHY_RF_MODULE,RfVbatCmpstValUpd,P_SIG,swLogPrintf("Rf Vbad Update : Vbad = %d , voltgCmpVal = %d "); +10240,21030146,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFecLogPrint_1,P_INFO,swLogPrintf("ActCfg : %e %s , delay = %d us , gpioMask = 0x%x , gpioVal = 0x%x 0x%x "); +10240,21031680,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFecLogPrint_4,P_INFO,swLogPrintf("ActCfg : %e ECS Reg%d , Addr = 0x%x , Val = 0x%x "); +10240,21033728,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFecLogPrint_5,P_INFO,swLogPrintf("ActCfg : %e ELCS Reg%d , Addr = 0x%x , Val = 0x%x "); +10240,21035776,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFecLogPrint_3,P_INFO,swLogPrintf("ActCfg : %e Reg%d , Addr = 0x%x , Val = 0x%x "); +10240,21038594,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFecLogPrint_2,P_INFO,swLogPrintf("ActCfg : %e %s , Said = 0x%x , delay = %d us , regsLenTotal = %d %d 0x%x "); +10240,21041151,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFctyCaliStart,P_SIG,swLogPrintf("Rf Calibration Start... "); +10240,21043199,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFctyCaliEnd,P_SIG,swLogPrintf("Rf Calibration End... "); +10240,21044992,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcComInfoCfg,P_VALUE,swLogPrintf("fcVersion1 = %d , fcVersion2 = %d , fcVersion3 = %d , hwInfo1 = %d , hwInfo2 = %d , bandNum = %d , bandList [ 0 ] = %d , rxAgcFelossAdj = %d "); +10240,21045504,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcAfcDataCfg,P_SIG,swLogPrintf("Band = %d , RxFreq = %d "); +10240,21047296,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcAfcStart,P_SIG,swLogPrintf("centFreq = %d "); +10240,21049344,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcRxAgcSeqCfg,P_SIG,swLogPrintf("SeqCount = %d "); +10240,21051648,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcRxIip2CaliRfModemSeqCfg,P_SIG,swLogPrintf("SelfCali-FddIp2 failure : Rxfreq = %d , bandNum = %d "); +10240,21053696,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcGapBeginInt_RxIp2_1,P_SIG,swLogPrintf("RxIp2 Cali BeforCode = 0x%x , Freq100KHz = %d "); +10240,21055744,0,0,PHY_ONLINE,PHY_RF_MODULE,RfFcGapBeginInt_RxIp2_2,P_SIG,swLogPrintf("RxIp2 Cali AfterCode = 0x%x , Freq100KHz = %d "); +10240,21059583,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_1,P_SIG,swLogPrintf("Rf Self-Calibration Start... "); +10240,21059584,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_2,P_SIG,swLogPrintf("step1... ScEventGet = 0x%X "); +10240,21061632,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_3,P_SIG,swLogPrintf("step2... ScEventGet = 0x%X "); +10240,21063680,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_4,P_SIG,swLogPrintf("step3... ScEventGet = 0x%X "); +10240,21065728,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_5,P_SIG,swLogPrintf("step4... ScEventGet = 0x%X "); +10240,21067776,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_6,P_SIG,swLogPrintf("step5... ScEventGet = 0x%X "); +10240,21069824,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_7,P_SIG,swLogPrintf("step6... ScEventGet = 0x%X "); +10240,21071872,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_8,P_SIG,swLogPrintf("step7... ScEventGet = 0x%X "); +10240,21073920,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_9,P_SIG,swLogPrintf("step8... ScEventGet = 0x%X "); +10240,21075968,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_10,P_SIG,swLogPrintf("step9... ScEventGet = 0x%X "); +10240,21078016,0,0,PHY_ONLINE,PHY_RF_MODULE,RfSelfCaliRunning_11,P_SIG,swLogPrintf("Rf Self-Calibration End...Result = 0x%X "); +10240,21080320,0,0,PHY_ONLINE,PHY_RF_MODULE,RfScDcocOneFreqEndInt,P_SIG,swLogPrintf("SelfCali-Dcoc failure : freq = %d , bandNum = %d "); +10240,21082368,0,0,PHY_ONLINE,PHY_RF_MODULE,RfScTxIqmCLRfModemSeqCfg,P_SIG,swLogPrintf("SelfCali-TxCarrierLeakage failure : freq = %d , bandNum = %d "); +10240,21084160,0,0,PHY_ONLINE,PHY_RF_MODULE,RfBandFecParasCalc,P_WARNING,swLogPrintf("band Front-End Paras Miss , bandnum = %d "); +10240,21086976,0,0,PHY_ONLINE,PHY_RF_MODULE,RfBandFecParasCalc_1,P_INFO,swLogPrintf("TxPath Config : bandNum = %d , txPort = %e , paOnAdvTime = %d ( unit : 30.720000 cycles ) , paBiasNum = %d "); +10240,21089024,0,0,PHY_ONLINE,PHY_RF_MODULE,RfNsmRxCwSnrTest,P_SIG,swLogPrintf("Rf RxCwTest , band = %d , freq = %d , bw = %d , flag = %d "); +11264,23071232,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyAtCmdSet,P_SIG,swLogPrintf("Phy AT Cmd Set! moduleValue = %d , data [ 0 ] = %d , data [ 1 ] = %d "); +11264,23074815,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyAtCmdSet_0,P_ERROR,swLogPrintf("Dump parameters error! valid input : data [ 0 ] < 4 , data [ 1 ] < 6 , data [ 2 ] < 20 , data [ 3 ] < 20 "); +11264,23076863,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyAtCmdSet_1,P_ERROR,swLogPrintf("PhyCfg Triggered Assert! "); +11264,23077380,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyMibTask,P_SIG,swLogPrintf("MIB decoded for Cell ( %d , %d ) ! BandWidth = %s "); +11264,23080959,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiDci0InfoGet_1,P_WARNING,swLogPrintf("no valid set for CSI request in DCI0 "); +11264,23083007,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiDci0InfoGet_2,P_WARNING,swLogPrintf("no valid reference subframe for CSI request in DCI0 "); +11264,23085055,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRarInfoGet_1,P_WARNING,swLogPrintf("no valid DL subframe for CSI request in RAR "); +11264,23087103,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRarInfoGet_2,P_WARNING,swLogPrintf("no valid set for CSI request in RAR "); +11264,23089151,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRarInfoGet_3,P_WARNING,swLogPrintf("no valid reference subframe for CSI request in RAR "); +11264,23091199,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDecPreProc_1,P_WARNING,swLogPrintf("no valid set for CSI Subframe config from seq "); +11264,23091456,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyStateTransit,P_ERROR,swLogPrintf("PhyStateTransit Error! current state = %d event = %d "); +11264,23093248,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyFreqOfstAfcAdj_1,P_WARNING,swLogPrintf("freqErrPPM with value of 0x%X overflow "); +11264,23097343,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyNCellTimeOfstUpdt_1,P_WARNING,swLogPrintf("BT_OFST with non-zero value existed "); +11264,23099391,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyTimeOfstUpdtAftAtc_1,P_INFO,swLogPrintf("BT adjustment is disabled in ATC "); +11264,23099392,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyTimeOfstUpdtLeaveConn_1,P_WARNING,swLogPrintf("new HFN value ( %d ) is taking effect when leaving CONN "); +11264,23103487,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMibInfoUpdt_0,P_ERROR,swLogPrintf("dlBandwidth or antPortNum in mib was updated in PHY CONN state "); +11264,23105535,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMibInfoUpdt_1,P_ERROR,swLogPrintf("phich parameters in mib were updated in PHY CONN state "); +11264,23107583,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMibInfoUpdt_2,P_SIG,swLogPrintf("Rx Tx ReSchedule Due to MIB Time Updt in PHY CONN state "); +11264,23107840,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,MultiBandInfo,P_WARNING,swLogPrintf("EARFCN changed by Sib1Config , prev_EARFCN = %d new_EARFCN = %d "); +11264,23109888,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phySib1Updt,P_SIG,swLogPrintf("SIB1 configured! TddUlDlConfig = %d SSP = %d "); +11264,23111936,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyUlCommInfoUpdt,P_ERROR,swLogPrintf("duplexMode mismatch between UL&DL frequency! , dlEuArfcn = %d , ulEuArfcn = %d "); +11264,23115775,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyUlCommInfoUpdt_0,P_INFO,swLogPrintf("Re-Calc PUXCH / SRS parameters when system information updated in connected state "); +11264,23116544,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyHoCommInfoUpdt_0,P_SIG,swLogPrintf("TDD handover , used tdd configuration of original cell! tddConfigPresent = %d , ulDlConfig = %d , specialSbfrmPatterns = %d , tddSbfrmType = 0x%X "); +11264,23118848,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPagingInfoUpdt_0,P_SIG,swLogPrintf("pagingCycle is %d ( ms ) , PFPO = 0x%X , Edrx config : Edrx period is %d ( ms ) , Ptw Length is %d ( ms ) , Ptw StartSfn is %d "); +11264,23121919,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPagingInfoUpdt_1,P_WARNING,swLogPrintf("disable eDRX scheduling because HFN field is absent in SIB1 "); +11264,23122176,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPagingInfoUpdt_2,P_SIG,swLogPrintf("pagingCycle is %d ( ms ) , PFPO = 0x%X "); +11264,23126015,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySpsConfigUpdt_1,P_WARNING,swLogPrintf("SPS C-RNTI is released "); +11264,23128063,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAntInfoDediConfigUpdt_1,P_WARNING,swLogPrintf("antennaInfo of REL-8 and REL-10 is sent by NW together "); +11264,23130111,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAntInfoDediConfigUpdt_2,P_WARNING,swLogPrintf("codebookSubsetRestriction missed by NW for TM4 / 5 / 6 "); +11264,23132159,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAntInfoDediConfigUpdt_3,P_WARNING,swLogPrintf("unexpected codebookSubsetRestriction configuration of TM8 "); +11264,23134207,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAntInfoDediConfigUpdt_4,P_WARNING,swLogPrintf("previous antInfo is REL-8 and new one is REL-10 "); +11264,23136255,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAntInfoDediConfigUpdt_5,P_WARNING,swLogPrintf("unexpected codebookSubsetRestriction configuration of R10 "); +11264,23138303,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCqiRptConfigUpdt_1,P_WARNING,swLogPrintf("cqi-ReportConfig of REL-8 and REL-10 is sent by NW together "); +11264,23140351,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCqiRptConfigUpdt_2,P_WARNING,swLogPrintf("previous cqi-ReportConfig is REL-8 and new one is REL-10 "); +11264,23142399,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCqiRptConfigUpdt_3,P_WARNING,swLogPrintf("illegal aperiodic CSI mode for 1.400000 MHz bandwidth "); +11264,23144447,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCqiRptConfigUpdt_4,P_WARNING,swLogPrintf("illegal periodic CSI mode for 1.400000 MHz bandwidth "); +11264,23146495,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRsNzpOsRePosDerive_1,P_WARNING,swLogPrintf("CSI-RS resourceConfig is illegal for normal subframe "); +11264,23148543,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRsNzpOsRePosDerive_2,P_WARNING,swLogPrintf("CSI-RS resourceConfig is illegal for special subframe "); +11264,23150591,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRsConfigUpdt_1,P_WARNING,swLogPrintf("CSI-RS is configured with 8 ports "); +11264,23152639,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRsConfigUpdt_2,P_WARNING,swLogPrintf("zeroTxPowerCSI_RS2 is configured incorrectly "); +11264,23154687,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCsiRsConfigUpdt_3,P_WARNING,swLogPrintf("TM9 without CSI-RS configuration setup pmi-RI-Report "); +11264,23154944,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPeriodicCqiRiParaMapping_1,P_WARNING,swLogPrintf("I_RI of SET%d is configured with reserved value %d "); +11264,23156992,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPeriodicCqiRiParaMapping_2,P_WARNING,swLogPrintf("I_CQI / PMI of SET%d is configured with reserved value %d "); +11264,23159040,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPeriodicCqiRiParaMapping_3,P_WARNING,swLogPrintf("I_CQI / PMI of SET%d is configured with reserved value %d "); +11264,23162879,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPeriodicCqiRiParaMapping_4,P_WARNING,swLogPrintf("Periodic CQI reporting is disable due to invalid configuration of I_CQI / PMI "); +11264,23164927,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPeriodicCqiRiParaMapping_5,P_WARNING,swLogPrintf("Periodic CQI reporting is disable due to invalid configuration of Npd "); +11264,23166975,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPeriodicCqiRiParaMapping_6,P_WARNING,swLogPrintf("Periodic CQI reporting will be handled by FW , not SEQ "); +11264,23169023,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPuxchDediUpdt_1,P_WARNING,swLogPrintf("pusch_configDecicated of REL-8 and REL-13 is sent by NW together "); +11264,23171071,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPuxchDediUpdt_2,P_WARNING,swLogPrintf("pucch_configDecicated of REL-8 and REL-13 is sent by NW together "); +11264,23173119,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPuxchDediUpdt_3,P_WARNING,swLogPrintf("PUCCH FORMAT3 is Configured!!! "); +11264,23175167,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPuxchDediUpdt_4,P_WARNING,swLogPrintf("PUCCH 1 b Channel Selection is Configured!!! "); +11264,23177215,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyScMeasPatternConfigUpdt_1,P_WARNING,swLogPrintf("duplex mode between serving cell and configured measurement subframe pattern mismatched "); +11264,23179263,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyScMeasPatternConfigUpdt_2,P_WARNING,swLogPrintf("TDD ulDlConfig between serving cell and configured measurement subframe pattern mismatched "); +11264,23181311,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediInfoPostProc_0,P_WARNING,swLogPrintf("post process of dedicated info. updating running in CDRX inactive state "); +11264,23183359,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediInfoPostProc_1,P_WARNING,swLogPrintf("RxResumeTime ( DediCfg ) delayed 1 ms! "); +11264,23185407,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediAbsPatternInfoUpdt_1,P_WARNING,swLogPrintf("csi-MeasSubframeSets-r12 and measSubframePatternPCell-r10 were configured togother "); +11264,23187455,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediAbsPatternInfoUpdt_2,P_WARNING,swLogPrintf("measSubframePatternPCell-r10 is NOT sub-set of csi-MeasSubframeSet1-r10 or csi-MeasSubframeSet2-r10 "); +11264,23189503,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediAbsPatternInfoUpdt_3,P_WARNING,swLogPrintf("measSubframePatternPCell-r10 is configured without valid csi-MeasSubframeSet1-r10 or csi-MeasSubframeSet2-r10 "); +11264,23189763,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediInfoUpdt_1,P_SIG,swLogPrintf("UE downlink transmission mode changed ( %s-->%s ) "); +11264,23192320,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediInfoUpdt_2,P_INFO,swLogPrintf("PhyDediInfoUpdt running time , time1 = 0x%X , time2 = 0x%X , time3 = 0x%X , time4 = 0x%X "); +11264,23194112,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyNextRxTxSbfrmFind,P_ERROR,swLogPrintf("Find next subframe error , startTime = 0x%X , expectSbfrmType = %d , tddSbfrmType = 0x%X "); +11264,23197695,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnApSrsPending_0,P_INFO,swLogPrintf("ApSRS is Pending "); +11264,23197952,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrx2InactiveJudge_0,P_INFO,swLogPrintf("Keep CDRX Active , spsRxTime = 0x%x , spsTxTime = 0x%x "); +11264,23201791,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxStateChange_0,P_INFO,swLogPrintf("SR is sent on PUCCH and is pending "); +11264,23203839,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxStateChange_1,P_INFO,swLogPrintf("CRNTI Grant not Received after RAR For Contention-Free RA "); +11264,23205887,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxStateChange_2,P_INFO,swLogPrintf("HARQ Buffer not empty and Wait for Retrans UL Grant "); +11264,23207935,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxStateChange_3,P_INFO,swLogPrintf("Keep Active Since Short Cycle is too Small "); +11264,23209983,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxStateChange_4,P_INFO,swLogPrintf("Keep Active Since time is Near to DRX Cycle Boundary or SPS Time "); +11264,23209984,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,DrxCmdReq,P_INFO,swLogPrintf("DRX Cmd Req , longDrxCmd = %d "); +11264,23214079,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxTimerExpiredProc_3,P_INFO,swLogPrintf("CDRX Schedule Stopped , Skip timer Expired Proc "); +11264,23216127,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyConnDrxTimerExpiredProc_2,P_INFO,swLogPrintf("Bypass Old Cycle Timer Proc "); +11264,23216896,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiMeasGapCdrxSuspend_0,P_INFO,swLogPrintf("ECGI MEAS GAP CDRX SUSPEND! , measGapProc = %d , schdTime = [ %d , %d , %d ] "); +11264,23220223,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiMeasGapCdrxResume_0,P_INFO,swLogPrintf("ECGI MEAS GAP CDRX RESUME! "); +11264,23222271,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiIcsGapLegalityCheck_0,P_WARNING,swLogPrintf("EMERGENCY GAP Length is not enough "); +11264,23222528,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiIcsPostProc_1,P_INFO,swLogPrintf("cell delay ( %d ) of TDD intra cell ( PCI = %d ) is out of range "); +11264,23224576,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiIntraMibTimeAdjust_0,P_INFO,swLogPrintf("Intra MIB Time Adjust : flag1 = %d , adjBmp = 0x%x "); +11264,23228415,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiSiSchdGapProc_1,P_INFO,swLogPrintf("Mib Receive time delay to next 10 ms "); +11264,23230463,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiSiSchdGapProc_0,P_INFO,swLogPrintf("Set Gap Start End Point When Ecgi Intra Mib "); +11264,23230464,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiSchedule_0,P_INFO,swLogPrintf("ECGI is suspending , suspendBmp = 0x%x "); +11264,23234559,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiReqStart_0,P_WARNING,swLogPrintf("CELL not in Neighbour List during ECGI SIB1 process "); +11264,23236607,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiReqStart_2,P_WARNING,swLogPrintf("ECGI Emergency GAP used! "); +11264,23238655,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiReqStart_1,P_WARNING,swLogPrintf("Valid Gap Not Exist For ECGI "); +11264,23240703,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiIntraMibTimeAdjInCdrxAct2Inact_0,P_INFO,swLogPrintf("Re-Trigger MIB time Update in CDRX ACT2INACT "); +11264,23240960,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiIntraMibTimeAdjInCdrxAct2Inact_1,P_INFO,swLogPrintf("C-RNTI Del Time Re-Adjust in CDRX ACT2INACT , oldDelTime = 0x%x , newDelTime = 0x%x "); +11264,23242752,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiSchdSuspend_0,P_SIG,swLogPrintf("Suspend Bmp Setting Delay , suspendBmp = 0x%x "); +11264,23244800,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiCancelByPendingSig_0,P_WARNING,swLogPrintf("ECGI cancelled by signal pending , waitTime = %d "); +11264,23247360,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiCrntiTimeAdjustByIntraMib_0,P_INFO,swLogPrintf("C-RNTI Time Adjust by Intra ECGI MIB , cRntiTime = %d , ncMibTime = %d , adjTime = %d "); +11264,23250943,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyEcgiCrntiTimeAdjustByIntraMib_1,P_INFO,swLogPrintf("Re-Trigger MIB time Update in CDRX INACT2ACT "); +11264,23251456,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyHwTaskCfgTimerSet,P_ERROR,swLogPrintf("PhyHwTaskCfgTimerSet error! miscTxTaskBitmap = 0x%X , rxTaskAddBitmap = 0x%X , rxTaskDelBitmap = 0x%X "); +11264,23255039,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHwTaskAdd_1,P_WARNING,swLogPrintf("skip adding HW tasks because of ongoing PS RESET process "); +11264,23255296,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,DelCurrRxBitmap,P_WARNING,swLogPrintf("Del Rx Event not existed! rxTaskBitmap = 0x%X , delEvent = %d "); +11264,23259135,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHwTaskProc4MeasGap_1,P_WARNING,swLogPrintf("delay 1 st meas. gap with one period because of confliction b / w meas. gap and auto gap "); +11264,23261183,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMiscEventTaskConfig_1,P_WARNING,swLogPrintf("RX_PAUSE for SIG pending happened when CRNTI has been just removed "); +11264,23263231,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMiscEventTaskConfig_2,P_WARNING,swLogPrintf("RX_RESUME for ECGI pending happened when CRNTI has been just removed "); +11264,23263232,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMiscEventTaskConfig_3,P_ERROR,swLogPrintf("Unexpected hwTask , miscBmp = 0x%X "); +11264,23267327,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxHwTaskConfig_00,P_WARNING,swLogPrintf("rxAddBmp and rxDelBmp overlapped "); +11264,23269375,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxHwTaskConfig_01,P_WARNING,swLogPrintf("rxAddBmp and currRxBmp overlapped "); +11264,23271423,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxHwTaskConfig_02,P_WARNING,swLogPrintf("no valid scheduled bitmap for current RX HW TASK CFG "); +11264,23273471,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxHwTaskConfig_03,P_WARNING,swLogPrintf("skip RxHwTaskConfig because no HW task is scheduled now "); +11264,23274240,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxHwTaskConfig_10,P_INFO,swLogPrintf("RxPause simultaneous with RxAdd / RxDel! miscBmp = 0x%X , rxAddBmp = 0x%X , rxDelBmp = 0x%X , currRxBmp = 0x%X "); +11264,23277567,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxHwTaskConfig_20,P_WARNING,swLogPrintf("Rx HwTask reStart after stopped 1 ms before! "); +11264,23279615,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHwTaskConfig_1,P_WARNING,swLogPrintf("HW task has been cancelled "); +11264,23281663,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHwTaskConfig_2,P_WARNING,swLogPrintf("No HW tasks need be configured "); +11264,23281664,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyHwHalt,P_INFO,swLogPrintf("PhyHwHalt! Reason = %e "); +11264,23285759,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHwTaskAssertResetSchd_1,P_ERROR,swLogPrintf("unexpected PHY ASSERT RESET process "); +11264,23287807,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPchTimerExpiredProc_0,P_INFO,swLogPrintf("Skip PCH Event Add Del Due to MAC Reset for Handover "); +11264,23289855,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPagingConfigReqHandle_1,P_WARNING,swLogPrintf("Get CephyPagingConfigReg in wrong state "); +11264,23289856,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyPchDciDecPostProc_0,P_DEBUG,swLogPrintf("Paging received and reported to PS at 0x%X! "); +11264,23291904,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phySchdInit_ChipId,P_SIG,swLogPrintf("CHIPID = %d ! "); +11264,23293952,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phySchdInit,P_INFO,swLogPrintf("PhySchdInitEvent = %e "); +11264,23296000,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyCerrcInitConfigReport_0,P_ERROR,swLogPrintf("RF calibration table error , bandNum in cali table is : %d "); +11264,23300095,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHandleDeactReq_1,P_WARNING,swLogPrintf("Pending DEACT_REQ because CEAXC post process has been started "); +11264,23302143,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyHandleHandoverReq_1,P_WARNING,swLogPrintf("Cell is not in neighbour list during handover MIB process "); +11264,23304191,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxPauseStartTimeCalc_0,P_WARNING,swLogPrintf("Wait for other pending signal! "); +11264,23304960,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxPauseStartTimeCalc_1,P_WARNING,swLogPrintf("Signal pending overlap with measgap! RxPauseTime = 0x%X , RxResumeTime = 0x%X ; MeasGap : RxPauseTime = 0x%X , RxResumeTime = 0x%X "); +11264,23308287,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySib1ConfigProcess_0,P_SIG,swLogPrintf("SIB1 Config pending! "); +11264,23310335,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyComnCnfgProcess_0,P_SIG,swLogPrintf("CommonConfig pending! "); +11264,23312383,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediConfigProcess_00,P_ERROR,swLogPrintf("buffer of cephyDedicatedConfigReq overflow "); +11264,23314431,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyDediConfigProcess_01,P_WARNING,swLogPrintf("buffer new coming cephyDedicatedConfigReq because last one has NOT been parsed "); +11264,23314688,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyMeasBuffRel_0,P_ERROR,swLogPrintf("PhyMeasBuffRelease ( 0 : MIB , 1 : ICS , 2 : MEAS ) = %d , measBuffInUse = %d , error!!! "); +11264,23316736,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRxGap4SigPendingInCdrxInact_0,P_WARNING,swLogPrintf("%d pending SIG encounter CDRX INACT state with signal pasring bitmap 0x%X "); +11264,23320575,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyTxStopPostProc_0,P_WARNING,swLogPrintf("mac data unready or c-rnti-config later "); +11264,23322623,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAuxAdcCnf_0,P_ERROR,swLogPrintf("invalid internal temperature "); +11264,23322624,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAuxAdcCnf_1,P_INFO,swLogPrintf("Current temperature = %d "); +11264,23324672,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySigParser_0,P_ERROR,swLogPrintf("Received SIG_CEPHY_NEXT_CELL_SEARCH_REQ under wrong PhyState : %e "); +11264,23326720,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySigParser,P_ERROR,swLogPrintf("Not defined signal recevied from PS , sigId = 0x%X "); +11264,23330815,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyAtCmdDataDumpProc,P_WARNING,swLogPrintf("Wait to send dump command in PHY IDLE or CONNECT state! "); +11264,23332863,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyRaStatisCntInc,P_WARNING,swLogPrintf("PhyRaStatisCntInc : Wrong type input! "); +11264,23334656,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyRaStatisInfo_0,P_SIG,swLogPrintf("PhyRaStatisInfo : raSuccNum = %d , accessReqNum = %d , preambleTxNum = %d , rarRecvNum = %d , msg3TxNum = %d , msg4RecvNum = %d , rarTmrExpNum = %d , crTmrExpNum = %d "); +11264,23336959,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyStatisOperReq_0,P_SIG,swLogPrintf("PS Request for start statis info report! "); +11264,23339007,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,phyStatisOperReq_1,P_SIG,swLogPrintf("PS Request for stop statis info report! "); +11264,23339008,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,CephySetMaxTxPowerReq_0,P_SIG,swLogPrintf("PS Request for Max TxPower = %d ! "); +11264,23341056,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,CephySetMaxTxPowerReq_1,P_WARNING,swLogPrintf("PS Request for Max TxPower = %d is invalid!!! "); +11264,23343104,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySpecialCaseInfoUpdt_1,P_INFO,swLogPrintf("Special Case No = 0x%X "); +11264,23347199,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMibStart_0,P_INFO,swLogPrintf("Schedule MIB with PCH task adding in advance "); +11264,23349247,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySib1Start_0,P_INFO,swLogPrintf("Schedule SIB1 with PCH task adding in advance "); +11264,23351295,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySibxStart_1,P_INFO,swLogPrintf("Receiving SYS_INFO_REQ ( SCELL SIBX ) while MEAS_TASK is ongoing "); +11264,23351808,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyScellSysInfoReq_0,P_INFO,swLogPrintf("MIB MODIFY REQ Received , schdTime = 0x%x , timeDiff = 0x%x , mibBoudary = 0x%x "); +11264,23355391,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyNcellSysInfoReq_1,P_WARNING,swLogPrintf("CELL MISS during cell reselection SIB1 process "); +11264,23357439,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySysInfoStop_0,P_SIG,swLogPrintf("PLMN STOP "); +11264,23359487,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySysInfoReport_1,P_WARNING,swLogPrintf("Skip Ncell MIB Reporting in Cell ReSelect "); +11264,23361535,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySysInfoReport_0,P_WARNING,swLogPrintf("Skip Ncell MIB Reporting in ECGI "); +11264,23362048,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySysInfoReport_2,P_WARNING,swLogPrintf("PhySysInfoReport : CRC fail! mibFlag = %d , siReqScell = %d , siReqNcell = %d "); +11264,23365631,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMibMdfPrdTimeDiff,P_WARNING,swLogPrintf("Unxpected Modification Period Coeff in CAT1 mode "); +11264,23367679,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMibDecPostProc_0,P_INFO,swLogPrintf("NC MIB Dec Result Skipped "); +11264,23369727,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySib1DciPostProc_0,P_INFO,swLogPrintf("NC SIB1 Dci Result Skipped "); +11264,23371775,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySib1DecPostProc_0,P_INFO,swLogPrintf("NC SIB1 Dec Result Skipped "); +11264,23372288,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySiRxPauseConflictProc_0,P_INFO,swLogPrintf("Si Rx Pause Conflict Proc : isAddBmp = %d , rxBitmap = 0x%X , CurrBitmap = 0x%X "); +11264,23375871,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhySibxSchdAftPageHwHalt_0,P_INFO,swLogPrintf("SIBx Schedule After Page HwHalt "); +11264,23375872,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,MacTimerExpiredPostProc_0,P_ERROR,swLogPrintf("timeAlignmentTimer expired! , time value = %d "); +11264,23379967,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,MacTimerExpiredPostProc_1,P_INFO,swLogPrintf("SW timer expired without matched expiredTime! "); +11264,23380480,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyMemoryCheck_0,P_SIG,swLogPrintf("PhyMemoryCheck , branchFlag = 0x%X , memAddr = 0x%X , expectContent = 0x%X "); +11264,23383296,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAssert_0,P_ERROR,swLogPrintf("PHY assert! Module = %e , SubID = 0x%X , val1 = 0x%X , val2 = 0x%X , val3 = 0x%X , resetType = %d "); +11264,23386111,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAssert_3,P_WARNING,swLogPrintf("skip PS RESET process because previous one is ongoing "); +11264,23388159,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,PhyAssert_4,P_WARNING,swLogPrintf("start self-recovery for PHY_ASSERT "); +11264,23388416,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,OsaCreateFastSignal_0,P_WARNING,swLogPrintf("runSigNumber = %d , runBigSigNumber = %d "); +11264,23390208,0,0,PHY_ONLINE,PHY_SCHEDULE_MODULE,EC618_CP_VERSION_0,P_WARNING,swLogPrintf("CP version = 0x%X "); +12288,25169919,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacApiInit_0,P_WARNING,swLogPrintf("gpPhyMacRaInfo is not NULL when IDLE2CONN! "); +12288,25171967,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacApiInit_1,P_WARNING,swLogPrintf("gpPhyMacApiCtrlInfo is not NULL when IDLE2CONN! "); +12288,25174015,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacApiInit_2,P_WARNING,swLogPrintf("gpPhyMacRaInfo is NULL when CONN2IDLE! "); +12288,25176063,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacApiInit_3,P_WARNING,swLogPrintf("gpPhyMacApiCtrlInfo is NULL when CONN2IDLE! "); +12288,25176576,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyAllocMacDlMem,P_ERROR,swLogPrintf("pdusize is %d , dlL2BuffBlockAddr is 0x%X , pCurBB is 0x%X "); +12288,25178112,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyAllocMacDlMem1,P_ERROR,swLogPrintf("pCurBB is 0x%X "); +12288,25180416,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyMacSendDlDataInd_0,P_WARNING,swLogPrintf("Discard Received Msg4 PDU : preambleTransCnt = %d DiscardNum = %d! "); +12288,25182208,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyMacSendSrTransMaxInd_0,P_WARNING,swLogPrintf("SR Trans max ind! srCounter = %d "); +12288,25185024,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyMacHandleStartTimerReq_0,P_INFO,swLogPrintf("PhyMacHandleStartTimerReq Received! userId = %d , timerId = %d , timerValue = %d , ulHarqId = %d "); +12288,25186816,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyMacHandleStartTimerReq_1,P_WARNING,swLogPrintf("Wrong TX time! grantTransTime = 0x%X , currTxTime = 0x%X , delayTime = %d "); +12288,25188352,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyMacSRReqProc_0,P_WARNING,swLogPrintf("Received SchedulingRequest when SR is pending! srCounter = %d "); +12288,25190912,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacHandleSRReq_0,P_INFO,swLogPrintf("Received SchedulingRequest when dedicatedConfig to be parsed! parseTime = [ 0x%X~0x%X ] , waitTime = %d ( ms ) "); +12288,25194495,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyMacHandleMacResetReq_1,P_INFO,swLogPrintf("Pending MAC_RESET_REQ because CEAXC post process has been started "); +12288,25195009,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarCrTimerExpireProc_0,P_WARNING,swLogPrintf("raStage = %s is error!!! , rarTimerState = %d , crTimerState = %d "); +12288,25196544,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarCrTimerExpireProc_1,P_SIG,swLogPrintf("RAR Window Timer Expired , preambleTransCnt = %d "); +12288,25198592,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarCrTimerExpireProc_2,P_SIG,swLogPrintf("Contention Resolution Timer Expired , preambleTransCnt = %d "); +12288,25200641,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyRaStageUpdt,P_SIG,swLogPrintf("Random Access : RaStage = %s "); +12288,25203457,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyRaStageUpdt_1,P_WARNING,swLogPrintf("Random Access : RaStage = %s , warningFlag = %d , rarTimerState = %d , crTimerState = %d "); +12288,25204992,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarMacPduParser_3,P_WARNING,swLogPrintf("Discard Received RAR : preambleTransCnt = %d DiscardNum = %d! "); +12288,25207552,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarMacPduParser_0,P_SIG,swLogPrintf("Received RAR ( rapid = %d ) with candidate rapid = %d , ta ( old ) = %d , ta ( new ) = %d "); +12288,25209600,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarMacPduParser_1,P_WARNING,swLogPrintf("Received RAR but Parse Error! rarResType = %d , pdu [ 0 |1|2|3 ] = %X , pdu [ 4 |5|6|7 ] = %X , pdu [ 8 |9|10|11 ] = %X "); +12288,25211392,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyRarMacPduParser_2,P_SIG,swLogPrintf("Received RAR! preambleIndex = %d , timingAdvanceCmd = %d , numOfRapid = %d "); +12288,25212929,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyPrachResourceSelect_1,P_WARNING,swLogPrintf("Number of fRa = 0 under TDD MODE! raStage = %s "); +12288,25217023,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyPreambleProc,P_ERROR,swLogPrintf("Cannot select a PRACH resource ! "); +12288,25217280,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyHandleRandomAccessReq_0,P_WARNING,swLogPrintf("Received RandomAccessReq when RA is ongoing , current RaCause = %d , Request RaCause = %d! "); +12288,25221119,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyHandleRandomAccessReq_1,P_WARNING,swLogPrintf("UL Data RA triggered when SR resource is existed! "); +12288,25223167,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacHandleCrntiConfigReq_0,P_SIG,swLogPrintf("Crnti Configured when raStage is SUCCESS , skipped by PHY! "); +12288,25223168,0,0,PHY_ONLINE,PHY_MAC_MODULE,phyMacHandleCrntiConfigReq_1,P_SIG,swLogPrintf("Crnti Configured ( RA SUCC ) : cRnti = %d "); +12288,25225216,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyTaTaskProc_0,P_WARNING,swLogPrintf("taSpn = %d is out of range !!! "); +12288,25227264,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyTaTaskProc_1,P_WARNING,swLogPrintf("taSpn = %d is out of range !!! "); +12288,25229568,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyDataReq_0,P_ERROR,swLogPrintf("Mac Send TX Data Late! harqID = %d , expected transTime ( HFNSFNSBN ) = 0x%X "); +12288,25231360,0,0,PHY_ONLINE,PHY_MAC_MODULE,PhyTxDataReq_1,P_WARNING,swLogPrintf("data Status = %d is Invalid "); +12288,25233664,0,0,PHY_ONLINE,PHY_MAC_MODULE,macTimerStart,P_ERROR,swLogPrintf("Start a MacTimer with too short length! ( userID<<16 ) |timerID = 0x%x , length = %d "); +12288,25237503,0,0,PHY_ONLINE,PHY_MAC_MODULE,macTimerExpiredIsr,P_WARNING,swLogPrintf("NO Running Timer when SW timer Expired! "); +13312,27265280,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyCeParaReCnfgReq_1,P_INFO,swLogPrintf("Add CE / RxDFE / RxSEQ algorithm para. reconfiguration of trigger source 0x%X HW task with startTime of 0x%X "); +13312,27267072,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyIcsMeasConnCnfgParaGen_1,P_INFO,swLogPrintf("startTime of inter FRS_CONN need be adjusted to 0x%X "); +13312,27269120,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasNCellListMaintain_1,P_INFO,swLogPrintf("add PCI %d into NCELL list because expiredCnt has NOT reached to expired timer "); +13312,27271424,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasInterSchdInfoMaintain_1,P_WARNING,swLogPrintf("number of inter cell is %d , exceed the upper limit %d "); +13312,27273472,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSCellCePostProc_1,P_ERROR,swLogPrintf("unexpected rssiNum ( %d ) or rsrpNum ( %d ) of serving cell "); +13312,27277311,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasFakeNCellRemove_1,P_INFO,swLogPrintf("fake neighCell will be removed after NC_MEAS "); +13312,27279359,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSchdInit_HO,P_WARNING,swLogPrintf("neighCell measurement schdPhase is NOT INIT "); +13312,27281407,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSchdInit_IDLE2CONN,P_WARNING,swLogPrintf("neighCell measurement schdPhase is NOT INIT "); +13312,27283455,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSchdInit_CONN2IDLE,P_WARNING,swLogPrintf("neighCell measurement schdPhase is NOT INIT "); +13312,27285503,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSchdInit_1,P_WARNING,swLogPrintf("wakeup full image from SLEEP2 while MEAS task status is ongoing "); +13312,27287551,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSourceSCellInfoBackup_1,P_INFO,swLogPrintf("Backup valid source cell before cell reselection "); +13312,27289599,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasIdleEventGenerator_1,P_WARNING,swLogPrintf("NCELL MEAS. process of previous DRX is not finished "); +13312,27291647,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasIdleSchedule_1,P_WARNING,swLogPrintf("break out previous unfinished MEAS tasks due to pending measurement commands "); +13312,27293695,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasIdleSchedule_2,P_WARNING,swLogPrintf("neighbor cell meas. scheduler should be only called after PCH in PHY IDLE "); +13312,27295743,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskSchdEnable_1,P_WARNING,swLogPrintf("intra ICS / CRS MEAS is skipped because of suspension "); +13312,27297791,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskSchdEnable_2,P_WARNING,swLogPrintf("inter ICS / CRS MEAS is skipped because of suspension "); +13312,27299839,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskSchdEnable_3,P_WARNING,swLogPrintf("inter ICS / CRS MEAS is skipped because of confliction b / w measGap and RACH "); +13312,27301887,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskSchdEnable_4,P_WARNING,swLogPrintf("inter ICS / CRS MEAS is skipped because of confliction b / w measGap and PCH "); +13312,27303935,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskSchdEnable_5,P_WARNING,swLogPrintf("inter ICS / CRS MEAS is skipped because of confliction b / w measGap and SCELL_SI "); +13312,27305983,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskSchdEnable_6,P_INFO,swLogPrintf("inter ICS / CRS MEAS is skipped because of confliction b / w measGap and CDRX timer "); +13312,27308031,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnTaskReqHandler_1,P_WARNING,swLogPrintf("neighCell MEAS HW task is ongoing when CDRX ACT to INACT "); +13312,27310079,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnEventGenerator_interIcs,P_WARNING,swLogPrintf("ICS MEAS of previous euArfcn has NOT been done "); +13312,27312127,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnNrmlSchedule_1,P_WARNING,swLogPrintf("skip period INT process because modem INT bitmap of CIRQ3 was cleared "); +13312,27314175,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnNrmlSchedule_2,P_INFO,swLogPrintf("skip period INT process if meas. is scheduled with CDRX method during inactive time "); +13312,27314432,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnDrxSchedule_1,P_INFO,swLogPrintf("CDRX cycle changed : %d ( ms ) -->%d ( ms ) "); +13312,27316224,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnSchdAbortPostProc_0,P_ERROR,swLogPrintf("Incorrect bitmap ( 0x%X ) indicated new msg. suspension "); +13312,27318272,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnSchdAbortPostProc_1,P_ERROR,swLogPrintf("Incorrect bitmap ( 0x%X ) indicated ECGI suspension "); +13312,27320576,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnSchdSuspend_1,P_WARNING,swLogPrintf("neighbor cell ( bitmap = 0x%X ) measurements is suspended with source = %d "); +13312,27322624,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnSchdResume_1,P_WARNING,swLogPrintf("neighbor cell ( bitmap = 0x%X ) measurements is resumed with source = %d "); +13312,27326463,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnEarlyReportCheck_intra,P_INFO,swLogPrintf("early reporting of intra cell will be triggered "); +13312,27328511,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnEarlyReportCheck_inter,P_INFO,swLogPrintf("early reporting of inter cell will be triggered "); +13312,27330559,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasRlmProc_0,P_ERROR,swLogPrintf("unexpected accuNum of SNR with value of zero when starting new CDRX cycle "); +13312,27330560,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasRlmProc_1,P_ERROR,swLogPrintf("accuNum ( %d ) of SNR for CDRX overflow "); +13312,27332608,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasRlmAdvSbfrmNumCalc_1,P_INFO,swLogPrintf("advanced subframe number for RLM is %d "); +13312,27334912,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCmdPendingProc_1,P_WARNING,swLogPrintf("%d commands with the same type ( %d ) as new coming one has been already stored "); +13312,27338751,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasIntraCellMeasCmdHandler_1,P_WARNING,swLogPrintf("ignore intra measurement command received during RA procedure "); +13312,27340799,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasInterCellMeasCmdHandler_1,P_WARNING,swLogPrintf("ignore inter measurement command received during RA procedure "); +13312,27340800,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasReqParse_0,P_SIG,swLogPrintf("receiving cell meas request ( bitmap = 0x%X ) "); +13312,27344895,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasReqParse_1,P_WARNING,swLogPrintf("neighbor cell meaurement is started within inappropriate PHY state "); +13312,27346943,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasReqParse_2,P_WARNING,swLogPrintf("intra measurement has already been started "); +13312,27348991,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasReqParse_3,P_WARNING,swLogPrintf("inter measurement with the same configuration has already been started "); +13312,27348992,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasStopReqParse_0,P_SIG,swLogPrintf("receiving cell meas stop request ( bitmap = 0x%X ) "); +13312,27353087,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasStopReqParse_1,P_WARNING,swLogPrintf("intra measurement has already been stopped "); +13312,27355135,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasCellMeasStopReqParse_2,P_WARNING,swLogPrintf("inter measurement with the configured stopped bitmap has been stopped "); +13312,27357183,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasConnMeasGapConfigReqParse_1,P_WARNING,swLogPrintf("configuration of measurement gap is NOT changed "); +13312,27359231,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasRlmInSyncCtrlReqParse_1,P_WARNING,swLogPrintf("Skip SIG_CEPHY_IN_SYNC_CTRL_REQ because schdEntity for CONN is PNULL "); +13312,27359232,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSCellWeakSignalOpt_10,P_VALUE,swLogPrintf("revised RSRP of cephySysInfoInd with value of %d / 16 ( dB ) "); +13312,27363327,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSCellWeakSignalOpt_11,P_INFO,swLogPrintf("skip optimization of weak cell camping in PHY IDLE state because neighbor cell was detected "); +13312,27363328,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSCellWeakSignalOpt_12,P_VALUE,swLogPrintf("revised RSRP of ServCellMeasInd in cephyCellMeasInd with value of %d / 16 ( dB ) "); +13312,27367423,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSCellWeakSignalOpt_13,P_INFO,swLogPrintf("qRxLevMin is invalid or very low "); +13312,27369471,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasSCellWeakSignalOpt_20,P_INFO,swLogPrintf("optimization of weak signal camp on was NOT enabled "); +13312,27371519,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasServCellIndFill_1,P_INFO,swLogPrintf("RSRP / RSSI of serving cell is measured with narrow bandwidth "); +13312,27373567,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasServCellIndFill_2,P_INFO,swLogPrintf("force RSRP / RSRQ reported to RRC to min value because of unreliable serving cell and continuous failure of presync "); +13312,27375615,0,0,PHY_ONLINE,PHY_MEAS_MODULE,PhyMeasServCellReport_1,P_WARNING,swLogPrintf("TA is negative value "); +14336,29364223,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyUpdateBtTimeOffset,P_WARNING,swLogPrintf("BT too large "); +14336,29364480,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyUpdateBtTimeOffset1,P_VALUE,swLogPrintf("update BT HFNSFNSBN = 0x%X , SPN = %d "); +14336,29368319,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyPmuSCCalibrCancelRequest,P_SIG,swLogPrintf("cancel SC calibration! "); +14336,29368320,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyPmuSCCalibrRequest_0,P_SIG,swLogPrintf("Request for SC calibration! trigType = %d "); +14336,29370368,0,0,PHY_ONLINE,PHY_PMU_MODULE,phyPmuSCCalibrResponse,P_SIG,swLogPrintf("Received IPC : A2C_SLOWCLOCK_CALIBR_CNF when slowClockCalibrStatus ( %d ) is not in request type! "); +14336,29374463,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyCpRTWakeupIsr_0,P_INFO,swLogPrintf("CP wakeup by CP RT IRQ! "); +14336,29376511,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyCpSWWakeupIsr_0,P_INFO,swLogPrintf("CP wakeup by SW INT! "); +14336,29377024,0,0,PHY_ONLINE,PHY_PMU_MODULE,phyCpmuConfig_0,P_VALUE,swLogPrintf("CP vote sleep! sleepTime = %d , sleepType = %e , IsScRc32K = %d "); +14336,29379072,0,0,PHY_ONLINE,PHY_PMU_MODULE,phyCpmuConfig_1,P_INFO,swLogPrintf("CP vote sleep! wkupSrc|hwTaskWkupTime = 0x%X , flashUpdtBmp = 0x%X , presyncMode = %d "); +14336,29382655,0,0,PHY_ONLINE,PHY_PMU_MODULE,phyCpmuConfig_2,P_INFO,swLogPrintf("meas exist and MSMB need retention! "); +14336,29384703,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyPmuModeCtrl_00,P_WARNING,swLogPrintf("CP sleep long in Non-CpOff state! "); +14336,29384704,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyWakeFullImage,P_VALUE,swLogPrintf("CP need transfer to full image due to wkupSrc %d "); +14336,29386752,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyGetTimingAdjValue_0,P_VALUE,swLogPrintf("Timing Adj of PreSync is %d "); +14336,29388800,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyGetTimingAdjValue_1,P_VALUE,swLogPrintf("Timing Adj of ATC is %d "); +14336,29392895,0,0,PHY_ONLINE,PHY_PMU_MODULE,PhyCancelDueToATCMD,P_SIG,swLogPrintf("All task canceled due to IPC INT received! "); +15360,31461375,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyDbgAlgoParamPresync,P_SIG,swLogPrintf("enter presync debug mode! "); +15360,31463423,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPresyncTimingAdjXrs,P_WARNING,swLogPrintf("timing offset is too large in sleep0 LRS "); +15360,31463424,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyCpGetSleepSrc,P_VALUE,swLogPrintf("SET sleep SRC to %d ( 0 is 32 K and 1 is 40 K ) "); +15360,31467519,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPreSyncTaskSchd_1,P_SIG,swLogPrintf("sss offline presync try next candidate "); +15360,31469567,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPreSyncTaskSchd_2,P_SIG,swLogPrintf("sss online presync try next candidate "); +15360,31469824,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPreSyncTaskAdd0,P_INFO,swLogPrintf("UE maybe wakup earlier than scheduled time : schedule time is 0x%X and currTime is 0x%X "); +15360,31471616,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPresyncTimingAdjForMib,P_WARNING,swLogPrintf("PRESYNC MIB adjust , need check further and ofst is %d "); +15360,31473664,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyIcsPresyncIntPostProc_AfcAdj1,P_VALUE,swLogPrintf("presync Adjust AFC %d "); +15360,31475968,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyIcsPresyncIntPostProc_AfcAdj2,P_VALUE,swLogPrintf("change AFC value from %d to %d "); +15360,31477760,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyIcsPresyncIntPostProc,P_SIG,swLogPrintf("presync fail and sync flag is %d "); +15360,31480832,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PAPR,P_VALUE,swLogPrintf("accuNum = %d , papr [ 0 \1 \2 \3 ] = %d|%d|%d|%d "); +15360,31481856,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,ICS_STAGE_SSS_OFFLINE_SYNC,P_VALUE,swLogPrintf("NID1 in candidate [ %d ] ! "); +15360,31483904,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPresyncCmdPending0,P_WARNING,swLogPrintf("IPC pending too many cmd , pending number is %d "); +15360,31485952,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPresyncCmdPending,P_INFO,swLogPrintf("IPC pending duto presync , pending number is %d "); +15360,31490047,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPresyncCmdProc_0,P_WARNING,swLogPrintf("presync pending IPC proc nested and skip it "); +15360,31490048,0,0,PHY_ONLINE,PHY_PRESYNC_MODULE,PhyPresyncCmdProc_1,P_INFO,swLogPrintf("process pending IPC , pending number is %d "); +17408,35655679,0,0,PHY_ONLINE,PHY_TMU_MODULE,SeqHwIcsStopRtnTimeAdjust_1,P_WARNING,swLogPrintf("ICS SCHD RTN and ICS STOP RTN overlapped "); +17408,35657727,0,0,PHY_ONLINE,PHY_TMU_MODULE,SeqHwIcsStopRtnTimeAdjust_2,P_INFO,swLogPrintf("ICS SCHD RTN and ICS STOP RTN overlapped "); +18432,37750784,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyDbgAlgoParamMibLlrFwlSet0,P_WARNING,swLogPrintf("AT debug : Set MIB LLR FWL to %d "); +18432,37752832,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyDbgAlgoParamMibLlrFwlSet1,P_WARNING,swLogPrintf("AT debug : Set PHICH LLR FWL to %d "); +18432,37754880,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyDbgAlgoParamMibLlrFwlSet2,P_WARNING,swLogPrintf("AT debug : Set CCH PDCCH FWL to %d "); +18432,37758975,0,0,PHY_ONLINE,PHY_COMM_MODULE,phyMXicDummyIsr,P_ERROR,swLogPrintf("Unexpected MXIC INT happened!!! "); +18432,37761023,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyMXicLogGrpErrSqIsr_0,P_INFO,swLogPrintf("PHY_MXIC_LOGGRP_SQ_ERROR happened! "); +18432,37761024,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyBBDMAIsr_1,P_WARNING,swLogPrintf("BB DMA TimeOut warnings status = %x "); +18432,37763328,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyBBDMAIsr_2,P_INFO,swLogPrintf("BB DMA finish! irqStatus = 0x%X , status0 = 0x%X "); +18432,37766144,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyBBDMAIsr_3,P_SIG,swLogPrintf("PHY Data Dump Done! dump Address = 0x%X , tempData [ 0 ] = 0x%X , tempData [ 1 ] = 0x%X , tempData [ 2 ] = 0x%X , tempData [ 3 ] = 0x%X "); +18432,37767936,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyDMADumpCfg_0,P_ERROR,swLogPrintf("PHY Data Dump Configured Error! dumpMode = %d , sampleRate = %d , numOfTti = %d , skipTti = %d "); +18432,37770752,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyDMADumpCfg_1,P_SIG,swLogPrintf("PHY Data Dump Configured! dump Address = 0x%X , availableMemSize = %d , dumpDataLength = %d , tempData [ 0 ] = 0x%X , tempData [ 1 ] = 0x%X , tempData [ 2 ] = 0x%X , tempData [ 3 ] = 0x%X "); +18432,37771264,0,0,PHY_ONLINE,PHY_COMM_MODULE,PhyDMADumpLostIsr_1,P_WARNING,swLogPrintf("Dump DMA Lost warnings status = %x "); +19456,39847936,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyGraphState_0,P_INFO,swLogPrintf("PhyCommGraphInfo : phyStateId = %d "); +19456,39849984,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyGraphState_1,P_INFO,swLogPrintf("PhyCommGraphInfo : phyStateId = %d "); +19456,39852288,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyCellInfo_0,P_INFO,swLogPrintf("PhyCommGraphInfo : carrierFreq = %d , phyCellId = %d "); +19456,39854080,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyGraphState_2,P_INFO,swLogPrintf("CDRX state change active --> inactive : PhyCommGraphInfo : phyStateId = %d "); +19456,39856128,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyGraphState_3,P_INFO,swLogPrintf("CDRX state change inactive --> active : PhyCommGraphInfo : phyStateId = %d "); +19456,39858688,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyMeaScellInfo_0,P_INFO,swLogPrintf("PhyCommGraphInfo : avgSnr = %d , avgRssi = %d , avgRsrp = %d "); +19456,39860480,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyCellInfo_1,P_INFO,swLogPrintf("PhyCommGraphInfo : carrierFreq = %d , phyCellId = %d "); +19456,39862528,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyCellInfo_2,P_INFO,swLogPrintf("PhyCommGraphInfo : carrierFreq = %d , phyCellId = %d "); +19456,39866112,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyRxStatisInfo_0,P_SIG,swLogPrintf("PhyRxStatisInfo : grantNum = %d , bler = %d% , wbCqi = %d , snr = %d , avgPrb = %d , avgMcs = %d , avgTBS = %d , ack2Nack = %d "); +19456,39868160,0,0,PHY_ONLINE,PHY_GRAPH_MODULE,PhyTxStatisInfo_0,P_SIG,swLogPrintf("PhyTxStatisInfo : grantNum = %d , bler = %d% , avgPrb = %d , avgMcs = %d , avgTBS = %d , ulPower = %d , ta = %d , ack2Dtx|nack2Ack = 0x%X "); +20480,41945344,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXOFTBuffUpdateReq_1,P_SIG,swLogPrintf("PHY request to update DCXO NVM file! , stored temprature = %d , freqPPM = %d "); +20480,41947136,0,0,PHY_ONLINE,PHY_DCXO_MODULE,FreqErrOvfl,P_ERROR,swLogPrintf("gpPhySCellInfo->baseInfo.freqErrPPM = %d ( wl = 17 , fwl = 10 ) overflows "); +20480,41949184,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXOInvalid,P_SIG,swLogPrintf("DCXO ( sync%d ) : curve invalid "); +20480,41952000,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXOAddSmp,P_SIG,swLogPrintf("DCXO ( sync%d ) : add Smp = ( %ddgr , %dppm ) addreason = %d "); +20480,41953280,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXODiscardSmp,P_SIG,swLogPrintf("DCXO ( sync%d ) : discard the current Smp "); +20480,41955844,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXOInitFreqErrGet_0,P_SIG,swLogPrintf("currTempr = %d , initFreqOfst = %d , initFreqType = %s "); +20480,41959423,0,0,PHY_ONLINE,PHY_DCXO_MODULE,PhyDCXOCInfoRst_0,P_WARNING,swLogPrintf("PhyDCXOCInfoRst called! "); +20480,41961471,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXOFTBuffUpdateReq_0,P_ERROR,swLogPrintf("Request to update DCXO NVM before last request has not been confirmed by AP! "); +20480,41963519,0,0,PHY_ONLINE,PHY_DCXO_MODULE,DCXOFTBuffUpdateCnf_0,P_ERROR,swLogPrintf("DCXO NVM update confirm received when request flag has been cleared! "); +20480,41963520,0,0,PHY_ONLINE,PHY_DCXO_MODULE,PhyDCXOFTBufAfcBU,P_WARNING,swLogPrintf("PhyDCXOFTBufPUCheck called! sizeof ( afc ) = %dbyte has changed from 5 words!!! "); +20480,41965568,0,0,PHY_ONLINE,PHY_DCXO_MODULE,PhyDCXOFTBufErase_0,P_WARNING,swLogPrintf("DCXOFTBufErase called! Cause = %d "); +21504,44044287,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyBeaconSyncIsr_0,P_INFO,swLogPrintf("WIFI SYNC isr confirm "); +21504,44046335,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyBeaconSyncIsr_1,P_INFO,swLogPrintf("WIFI SYNC isr abort "); +21504,44048383,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyBeaconSfdMissErrorIsr_0,P_INFO,swLogPrintf("WIFI SYNC isr miss "); +21504,44050431,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyBeaconSyncCmdFifoErrorIsr_0,P_INFO,swLogPrintf("WIFI SYNC cmd Fifo error "); +21504,44052479,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyRakeReset_0,P_INFO,swLogPrintf("WIFI RAKE RESET "); +21504,44054527,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyRakeReset_1,P_INFO,swLogPrintf("WIFI RAKE ABORT "); +21504,44056575,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyRakeSoftDiffDemap_0,P_INFO,swLogPrintf("WIFI RAKE PSDU OK ( Beacon Frame ) . "); +21504,44058623,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyRakeSoftDiffDemap_1,P_INFO,swLogPrintf("WIFI RAKE PSDU OK ( None Beacon Frame ) . "); +21504,44060671,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyRakeSoftDiffDemap_2,P_INFO,swLogPrintf("WIFI RAKE BSSID OK BUT PSDU NOK. "); +21504,44062719,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyRakeTask_0,P_INFO,swLogPrintf("WIFI RAKE SHORT PSDU "); +21504,44064767,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiScanRsltReport_0,P_WARNING,swLogPrintf("Skip WIFI SCAN Result Reporting To RRC in Phy Debug Mode "); +21504,44065280,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiScanReqProcess_0,P_SIG,swLogPrintf("WIFI SCAN REQ : schdEn = %d , maxBssidNum = %d , channelGroupId = %d "); +21504,44068863,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiHwConfig_0,P_INFO,swLogPrintf("WIFI SCAN HW CONFIG "); +21504,44068864,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiRfParaGen_0,P_INFO,swLogPrintf("WIFI SCAN Start , Freq = %d ( MHz ) "); +21504,44072959,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiAbortConfig_0,P_INFO,swLogPrintf("WIFI SCAN Abort Config Give Up "); +21504,44072960,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiAbortPostProc_0,P_SIG,swLogPrintf("WIFI SCAN STOP , Freq = %d ( MHz ) "); +21504,44076288,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiAbortPostProc_1,P_SIG,swLogPrintf("WIFI SCAN BSSID : %x : %x , RSSI : %d.%d , Channel : %d , ssidLen : %d "); +21504,44078848,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiAbortPostProc_2,P_SIG,swLogPrintf("WIFI SCAN SSID : %x-%x-%x-%x-%x-%x-%x-%x "); +21504,44079104,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiAbortPostProc_3,P_SIG,swLogPrintf("WIFI SCAN SSID Length is 0 , ssidExist = %d "); +21504,44083199,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiSchedule_0,P_INFO,swLogPrintf("Time is not enough for WIFI SCAN "); +21504,44085247,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiSchedule_1,P_INFO,swLogPrintf("WIFI SCAN Schedule "); +21504,44085248,0,0,PHY_ONLINE,PHY_WIFI_MODULE,PhyWifiFreqOfstAfcAdj_0,P_INFO,swLogPrintf("WIFI SCAN AFC Adjust , freqEst = %d "); +262144,536875007,0,0,PLAT_AP,SIG_DUMP,DUMP_FULL_SIGNAL,P_INFO,swLogDumpPolling("Sig = > "); +262144,536877055,0,0,PLAT_AP,PS_DUMP,NetMgrLinkUp_8,P_SIG,swLogDump("Net manager , link up , IPV6 PCO DNS addr : "); +262144,536879103,0,0,PLAT_AP,PS_DUMP,NetMgrLinkUp_9,P_ERROR,swLogPrintf("Net manager , link up , get adpt DNS CFG fail "); +263168,538970113,0,0,PLAT_AP,PLA_STRING,slpManApplyPlatVoteHandle_2,P_VALUE,swLogPrintf("%s "); +263168,538972161,0,0,PLAT_AP,PLA_STRING,slpManGivebackPlatVoteHandle_4,P_VALUE,swLogPrintf("%s "); +263168,538974209,0,0,PLAT_AP,PLA_STRING,OsaFopen_1,P_WARNING,swLogPrintf("Can ' t open NVM file , as not support mode : %s "); +263168,538976257,0,0,PLAT_AP,PLA_STRING,build_info,P_SIG,swLogPrintf("%s "); +263168,538978305,0,0,PLAT_AP,PLA_STRING,get_log_version_1,P_ERROR,swLogPrintf("%s "); +263168,538980353,0,0,PLAT_AP,PLA_STRING,StackOverflow,P_ERROR,swLogPrintf("\r \n!!!error!!!..task : %s..stack.over.flow!!! \r \n "); +264192,541071359,0,0,PLAT_AP,PLA_INTERNAL_CMD,EC_READY,P_INFO,swLogPrintf("EC Ready! "); +264192,541067265,0,0,PLAT_AP,PLA_INTERNAL_CMD,get_log_version,P_SIG,swLogPrintf("LOGVERSION : %s "); +264192,541073407,0,0,PLAT_AP,PLA_INTERNAL_CMD,ecDumpHandshakeProc,P_ERROR,swLogPrintf("enter dump handshake mode "); +264192,541075455,0,0,PLAT_AP,PLA_INTERNAL_CMD,ecDumpUsbHandshakeProc,P_ERROR,swLogPrintf("enter USB dump handshake mode "); +265216,543164928,0,0,PLAT_AP,PLA_DRIVER,vTaskStepTick_1,P_VALUE,swLogPrintf("vTaskStepTick-%x , %x , %x "); +265216,543166464,0,0,PLAT_AP,PLA_DRIVER,vTaskStepTick_2,P_VALUE,swLogPrintf("New xTicksToJump = %d "); +265216,543168512,0,0,PLAT_AP,PLA_DRIVER,vTaskStepTick_3,P_VALUE,swLogPrintf("xTicksToJump has error = %d "); +265216,543171072,0,0,PLAT_AP,PLA_DRIVER,vECTaskStepTick_1,P_WARNING,swLogPrintf("vTaskStepTick-%x , %x , %x "); +265216,543172608,0,0,PLAT_AP,PLA_DRIVER,Enter_Active_1,P_VALUE,swLogPrintf("EC618 Active SmallImg-from = %e "); +265216,543176703,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_1,P_VALUE,swLogPrintf("EC Main Branch : AP unschd wakeup "); +265216,543178751,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_2,P_VALUE,swLogPrintf("EC Main Branch : CP sleep before ap wfi "); +265216,543180799,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_3,P_VALUE,swLogPrintf("EC Main Branch : AP receive wakeup pending "); +265216,543182847,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_4,P_VALUE,swLogPrintf("EC Main Branch : AP hib timer is near "); +265216,543184895,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_5,P_VALUE,swLogPrintf("EC Main Branch : Ps need wakeup fullimage "); +265216,543186943,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_6,P_VALUE,swLogPrintf("EC Main Branch : CP sleeped , AP wakeup from wfi "); +265216,543188991,0,0,PLAT_AP,PLA_DRIVER,ecPrintFullImageReason_7,P_VALUE,swLogPrintf("EC Main Branch : AP hib counter wrap "); +265216,543191039,0,0,PLAT_AP,PLA_DRIVER,ec_main_1,P_ERROR,swLogPrintf("sleep should not run to here "); +265216,543191808,0,0,PLAT_AP,PLA_DRIVER,adc_efuse_read,P_INFO,swLogPrintf("adc efuse trim value , code500 : 0x%x , code900 : 0x%x , tcode : 0x%x , t0 : 0x%x "); +265216,543193088,0,0,PLAT_AP,PLA_DRIVER,ec_main_wakeupSrc,P_INFO,swLogPrintf("Wakeup Src Bitmap = 0x%x "); +265216,543195904,0,0,PLAT_AP,PLA_DRIVER,ec_main_0,P_WARNING,swLogPrintf("BC Ld Assert : bcldCfg = 0x%x , wkupCfg = 0x%x , BCWaitStart = %d , BCWaitEnd = %d "); +265216,543197184,0,0,PLAT_AP,PLA_DRIVER,BSP_QSPI_Erase_Safe_1,P_VALUE,swLogPrintf("Erase Safe. primask = %d "); +265216,543199232,0,0,PLAT_AP,PLA_DRIVER,pmuGetMinSleepMode_1,P_VALUE,swLogPrintf("Unable to Sleep because of driver = 0x%x "); +265216,543203327,0,0,PLAT_AP,PLA_DRIVER,PmuHasHibTimertoWakeup_1,P_VALUE,swLogPrintf("Hib Timer nearly trigger , Start AP "); +265216,543203584,0,0,PLAT_AP,PLA_DRIVER,apmuVoteToSleep1State_1,P_VALUE,swLogPrintf("Vote Sleep : apSdkSleep1VoteFlag = 0x%x-%d \n "); +265216,543205632,0,0,PLAT_AP,PLA_DRIVER,apmuVoteToSleep2State_1,P_VALUE,swLogPrintf("Vote Sleep2 : apSdkSleep2VoteFlag = 0x%x-%d \n "); +265216,543207680,0,0,PLAT_AP,PLA_DRIVER,apmuVoteToHibState_1,P_VALUE,swLogPrintf("Vote Hibernate : apSdkHibernateVoteFlag = 0x%x-%d \n "); +265216,543209728,0,0,PLAT_AP,PLA_DRIVER,pmuPreDeepSlpCbRegister_1,P_VALUE,swLogPrintf("Registe pre deepsleep callback = 0x%x , 0x%x "); +265216,543211776,0,0,PLAT_AP,PLA_DRIVER,pmuPostDeepSlpCbRegister_1,P_VALUE,swLogPrintf("Registe post deepsleep callback = 0x%x , 0x%x "); +265216,543215615,0,0,PLAT_AP,PLA_DRIVER,pmuPreDeepSlpCbExcute_1,P_SIG,swLogPrintf("PS DeepSleep Callback Excute "); +265216,543217663,0,0,PLAT_AP,PLA_DRIVER,pmuPostDeepSlpCbExcute_1,P_VALUE,swLogPrintf("Excute PostDeepSlp Callbacks "); +265216,543217664,0,0,PLAT_AP,PLA_DRIVER,pmuSetDeepestSleepMode_1,P_VALUE,swLogPrintf("Deepest sleep mode = %e "); +265216,543219712,0,0,PLAT_AP,PLA_DRIVER,apmuSetUsim1LatchFlag_1,P_VALUE,swLogPrintf("AONIO apmuSetUsim1LatchFlag = %d "); +265216,543221760,0,0,PLAT_AP,PLA_DRIVER,apmuSetAONIOLatchFlag_1,P_VALUE,swLogPrintf("AONIO apmuSetAONIOLatchFlag = %d "); +265216,543224064,0,0,PLAT_AP,PLA_DRIVER,apmuAONIOLatchRelease_1,P_VALUE,swLogPrintf("AONIO Release , usim1Latch = %d , userAonioLatch = %d "); +265216,543226112,0,0,PLAT_AP,PLA_DRIVER,apmuAONIOLatchApply_1,P_VALUE,swLogPrintf("AONIO Need Latch , usim1Latch = %d , userAonioLatch = %d "); +265216,543229951,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_0,P_VALUE,swLogPrintf("Enter ASMB+MSMB mode "); +265216,543231999,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_1,P_VALUE,swLogPrintf("Enter ASMB+MSMB+CSMB mode "); +265216,543232000,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_2,P_VALUE,swLogPrintf("CP State < = CP_STATE_IDLE ( %d ) "); +265216,543236095,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_3,P_VALUE,swLogPrintf("Sleep1 Failed there is pending interrupt "); +265216,543236352,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_4,P_VALUE,swLogPrintf("NVIC ISPR 0x%x ICSR 0x%x \r \n "); +265216,543238912,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_5,P_VALUE,swLogPrintf("XIC0 0x%x XIC1 0x%x XIC2 0x%x XIC3 0x%x \r \n "); +265216,543242239,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_6,P_SIG,swLogPrintf("AP allow to enter hib but enter sleep2 because of cp "); +265216,543244287,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_7,P_VALUE,swLogPrintf("Enter ASMB+CSMB mode "); +265216,543246335,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_8,P_VALUE,swLogPrintf("Enter ASMB mode "); +265216,543248383,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_9,P_VALUE,swLogPrintf("Enter ASMB mode "); +265216,543248384,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_10,P_VALUE,swLogPrintf("CP State < = CP_STATE_CS1 ( %d ) "); +265216,543252479,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_11,P_VALUE,swLogPrintf("Sleep2 Failed there is pending interrupt "); +265216,543252736,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_12,P_VALUE,swLogPrintf("NVIC ISPR 0x%x ICSR 0x%x \r \n "); +265216,543255296,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_13,P_VALUE,swLogPrintf("XIC0 0x%x XIC1 0x%x XIC2 0x%x XIC3 0x%x \r \n "); +265216,543258623,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_14,P_VALUE,swLogPrintf("Enter None Ret mode "); +265216,543258624,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_15,P_VALUE,swLogPrintf("CP State < = CP_STATE_CS2 ( %d ) "); +265216,543262719,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_19,P_SIG,swLogPrintf("Change Fullimage boot flag to hibernate "); +265216,543264767,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_16,P_VALUE,swLogPrintf("Hibernate Failed there is pending interrupt "); +265216,543265024,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_17,P_VALUE,swLogPrintf("NVIC ISPR 0x%x ICSR 0x%x \r \n "); +265216,543267584,0,0,PLAT_AP,PLA_DRIVER,prvEnterLowPowerState_18,P_VALUE,swLogPrintf("XIC0 0x%x XIC1 0x%x XIC2 0x%x XIC3 0x%x \r \n "); +265216,543270400,0,0,PLAT_AP,PLA_DRIVER,apmuPrintBootTimeStamp_0,P_VALUE,swLogPrintf("BootTime Print : Pre Paging SlowCnt = %d , %d , %d , %d , %d , %d , %d "); +265216,543272448,0,0,PLAT_AP,PLA_DRIVER,apmuPrintBootTimeStamp_1,P_VALUE,swLogPrintf("BootTime Print : Post Paging SlowCnt = %d , %d , %d , %d , %d , %d , %d "); +265216,543273216,0,0,PLAT_AP,PLA_DRIVER,apmuPrintBootTimeStamp_2,P_VALUE,swLogPrintf("Last Sc Ratio = %d , slowCnt when ratio change = %d "); +265216,543277055,0,0,PLAT_AP,PLA_DRIVER,atwait_expired_1,P_VALUE,swLogPrintf("Wait AT Timer Expired "); +265216,543277056,0,0,PLAT_AP,PLA_DRIVER,at_wait_start_1,P_VALUE,swLogPrintf("Wait AT Timer Start-%u "); +265216,543281151,0,0,PLAT_AP,PLA_DRIVER,at_wait_start_2,P_VALUE,swLogPrintf("Wait AT Timer New Timer "); +265216,543281152,0,0,PLAT_AP,PLA_DRIVER,at_wait_start_3,P_WARNING,swLogPrintf("Timer Handle Error-0x%x "); +265216,543283200,0,0,PLAT_AP,PLA_DRIVER,pmuUsrAddSlpDelay_0,P_VALUE,swLogPrintf("User Change Sleep Delay-value = %d "); +265216,543285248,0,0,PLAT_AP,PLA_DRIVER,pmuUsrAddSlpDelay_1,P_VALUE,swLogPrintf("User Add Sleep Delay-value = %d "); +265216,543289343,0,0,PLAT_AP,PLA_DRIVER,pmuUsrAddSlpDelay_2,P_VALUE,swLogPrintf("User Create New Sleep Delay "); +265216,543289344,0,0,PLAT_AP,PLA_DRIVER,pmuUsrAddSlpDelay_3,P_WARNING,swLogPrintf("User Add Delay Error-0x%x "); +265216,543291392,0,0,PLAT_AP,PLA_DRIVER,apmuCPStartCheck_1,P_VALUE,swLogPrintf("Time to CP Wakeup = 0x%x ms "); +265216,543295487,0,0,PLAT_AP,PLA_DRIVER,apmuCPStartCheck_2,P_VALUE,swLogPrintf("create modem timer "); +265216,543296000,0,0,PLAT_AP,PLA_DRIVER,apmuIntInit_1,P_VALUE,swLogPrintf("Wakeup SW Sc = %d , BTMsCnt = %d , Current SC = %d "); +265216,543298816,0,0,PLAT_AP,PLA_DRIVER,apmuGetPMUSettings_1,P_VALUE,swLogPrintf("PmuEnMagic = 0x%x , slpdepth = %d , defaultState = %d , voteMask = %d , FullImgReason = %e , minTimeCPWakeup = %d "); +265216,543299584,0,0,PLAT_AP,PLA_DRIVER,apmuGetPMUSettings_2,P_VALUE,swLogPrintf("Full Image transfer Time = %d ms "); +265216,543301632,0,0,PLAT_AP,PLA_DRIVER,pmuRegisterUsrSlpModeCb_1,P_VALUE,swLogPrintf("User Sleep Mode Control Callback = 0x%x "); +265216,543303680,0,0,PLAT_AP,PLA_DRIVER,pmuHasNearHibtimer_2,P_VALUE,swLogPrintf("DeepSlp Timer Can Sleep : Next DeepSleep Timer = %u ms "); +265216,543305728,0,0,PLAT_AP,PLA_DRIVER,pmuHasNearHibtimer_1,P_VALUE,swLogPrintf("DeepSlp Timer Can not Sleep : Near DeepSleep Timer = %u ms "); +265216,543307776,0,0,PLAT_AP,PLA_DRIVER,apmuCalculateCPSlpTimeConsiderCPSlpMode_0,P_VALUE,swLogPrintf("CP need copy measure code = %d "); +265216,543309824,0,0,PLAT_AP,PLA_DRIVER,apmuCalculateCPSlpTimeConsiderCPSlpMode_2,P_VALUE,swLogPrintf("CP need copy measure code = %d "); +265216,543312128,0,0,PLAT_AP,PLA_DRIVER,apmuCalculateCPSlpTimeConsiderCPSlpMode_1,P_VALUE,swLogPrintf("Caculate CP Sleep Time , Old = %u New = %u "); +265216,543313920,0,0,PLAT_AP,PLA_DRIVER,apmuCalculateCPSlpTimeBeforeCPWakeup_2,P_VALUE,swLogPrintf("CP need copy measure code = %d "); +265216,543316224,0,0,PLAT_AP,PLA_DRIVER,apmuCalculateCPSlpTimeBeforeCPWakeup_1,P_VALUE,swLogPrintf("Caculate CP Sleep Time Before CP Start , Old = %u New = %u "); +265216,543318272,0,0,PLAT_AP,PLA_DRIVER,apmuSetSlpLimitTime_1,P_SIG,swLogPrintf("Sleep Limit Time Cfg , enable = %d , LimitTime = %u "); +265216,543322111,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingDeepSlp_8,P_VALUE,swLogPrintf("CP is ready to start "); +265216,543322112,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_0,P_VALUE,swLogPrintf("Paging deepest sleep mode = %d "); +265216,543326207,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_1,P_VALUE,swLogPrintf("Paging deepsleep failed , go to PagingSlp1 "); +265216,543326464,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_LimitTime,P_SIG,swLogPrintf("SleepTime = %u > LimitTime = %u "); +265216,543328512,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_2,P_VALUE,swLogPrintf("CP SleepTime = %u ms AP nearHibTime = %u ms \n "); +265216,543332351,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_3,P_WARNING,swLogPrintf("Flash Write Error , need erase and rewrite again "); +265216,543332352,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_4,P_VALUE,swLogPrintf("Sleep Time to long , change to %u ms "); +265216,543335424,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_5,P_SIG,swLogPrintf("Enter Paging Hibernate %u ms PreSlp = %u ms minTimeL1 = %u Wakeup SC = %u CurrentSC = %u "); +265216,543337472,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_6,P_SIG,swLogPrintf("Enter Paging Sleep2 %u ms PreSlp = %u ms minTimeL1 = %u Wakeup SC = %u CurrentSC = %u "); +265216,543338496,0,0,PLAT_AP,PLA_DRIVER,apmuEnterDeepSlp_7,P_SIG,swLogPrintf("Failed to enter DeepSlp , there is pending interrupt , lowPowerState = %d "); +265216,543342591,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_5,P_VALUE,swLogPrintf("CP is ready to start "); +265216,543344639,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_0,P_SIG,swLogPrintf("Vote change in Paging Sleep1 "); +265216,543344896,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_LimitTime,P_SIG,swLogPrintf("SleepTime = %u > LimitTime = %u "); +265216,543346944,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_1,P_VALUE,swLogPrintf("CP SleepTime = %u ms AP nearHibTime = %u ms \n "); +265216,543348736,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_3,P_VALUE,swLogPrintf("Sleep Time to long , change to %u ms "); +265216,543351808,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_2,P_SIG,swLogPrintf("Enter Paging Sleep1 %u ms PreSlp = %u ms minTimeL1 = %u Wakeup SC = %u CurrentSC = %u "); +265216,543353600,0,0,PLAT_AP,PLA_DRIVER,apmuEnterPagingSlp1_4,P_VALUE,swLogPrintf("EC618 Active Paging Sleep1 @ SwWakeupSc = %u , WakeupSrc Bitmap = 0x%x , SlowCnt after sleep1 Callback = %u , Cur HibCnt = %u "); +265216,543356927,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_01,P_VALUE,swLogPrintf("CP is ready to start "); +265216,543357184,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_LimitTime,P_SIG,swLogPrintf("SleepTime = %u > LimitTime = %u "); +265216,543358976,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_0,P_VALUE,swLogPrintf("sleep time < usb sleep thd ( %d ) "); +265216,543361280,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_1,P_VALUE,swLogPrintf("MinTime is L1 = %u MinTime %u ms \n "); +265216,543363584,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_2,P_VALUE,swLogPrintf("Hibernate Time Not Enough %u , %u ms , flash_write_time = %d \n "); +265216,543367167,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_3,P_VALUE,swLogPrintf("abort sleep , interrupt make a task unblock \n "); +265216,543369215,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_4,P_WARNING,swLogPrintf("Flash Write Error , need erase and rewrite again "); +265216,543369216,0,0,PLAT_AP,PLA_DRIVER,pmuTryHibernate_5,P_VALUE,swLogPrintf("Sleep Time to long , change to %u ms "); +265216,543372288,0,0,PLAT_AP,PLA_DRIVER,Enter_Hibernate,P_SIG,swLogPrintf("Enter Hibernate %u ms PreSlp = %u ms Wakeup SC = %u minTimeL1 = %u , CurrentSC = %u "); +265216,543375359,0,0,PLAT_AP,PLA_DRIVER,Exit_Hibernate,P_SIG,swLogPrintf("Failed to enter hibernate , there is pending interrupt "); +265216,543377407,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_01,P_VALUE,swLogPrintf("CP is ready to start "); +265216,543377664,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_LimitTime,P_SIG,swLogPrintf("SleepTime = %u > LimitTime = %u "); +265216,543379456,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_0,P_VALUE,swLogPrintf("sleep time < usb sleep thd ( %d ) "); +265216,543381760,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_1,P_VALUE,swLogPrintf("MinTime is L1 = %u MinTime %u ms \n "); +265216,543384064,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_2,P_VALUE,swLogPrintf("Sleep2 Time Not Enough , cpWakeupMs = %ums , apWakeup = %ums , flash_write_time = %d \n "); +265216,543387647,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_3,P_SIG,swLogPrintf("abort sleep , interrupt make a task unblock \n "); +265216,543389695,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_4,P_WARNING,swLogPrintf("Flash Write Error , need erase and rewrite again "); +265216,543389696,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep2_5,P_VALUE,swLogPrintf("Sleep Time to long , change to %u ms "); +265216,543392768,0,0,PLAT_AP,PLA_DRIVER,Enter_Sleep2,P_SIG,swLogPrintf("Enter Sleep2 %u ms PreSlp = %u ms Wakeup SC = %u minTimeL1 = %u , CurrentSC = %u "); +265216,543395839,0,0,PLAT_AP,PLA_DRIVER,Exit_Sleep2,P_SIG,swLogPrintf("Failed to enter Sleep2 , there is pending interrupt "); +265216,543397887,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_01,P_VALUE,swLogPrintf("CP is ready to start "); +265216,543399935,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_000,P_WARNING,swLogPrintf("Detect Hib Timer Change , retry DeepSleep "); +265216,543400192,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_LimitTime,P_SIG,swLogPrintf("SleepTime = %d > LimitTime = %d "); +265216,543401984,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_00,P_VALUE,swLogPrintf("sleep time < usb sleep thd ( %d ) "); +265216,543406079,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_0,P_VALUE,swLogPrintf("worth sleep "); +265216,543408127,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_2,P_VALUE,swLogPrintf("task unblock , abort sleep "); +265216,543408128,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_10,P_VALUE,swLogPrintf("Sleep Time to long , change to %u ms "); +265216,543411200,0,0,PLAT_AP,PLA_DRIVER,Enter_Sleep1,P_VALUE,swLogPrintf("Enter Sleep1 : %u ms PreSlp = %u ms Wakeup SC = %u minTimeL1 = %u , Current SC = %u "); +265216,543412992,0,0,PLAT_AP,PLA_DRIVER,Enter_Active_3,P_VALUE,swLogPrintf("EC618 Active Sleep1 @ SwWakeupSc = %u , WakeupSrc Bitmap = 0x%x , SlowCnt after sleep1 Callback = %u , Cur HibCnt = %u "); +265216,543414272,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_81,P_VALUE,swLogPrintf("Sleep1 Wakeup , Time to CP Wakeup = 0x%x ms "); +265216,543418367,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_810,P_VALUE,swLogPrintf("create modem timer "); +265216,543418368,0,0,PLAT_AP,PLA_DRIVER,pmuTrySleep1_91,P_VALUE,swLogPrintf("Sleep1 Failed-%u "); +265216,543422463,0,0,PLAT_AP,PLA_DRIVER,apmuCheckHibTimeNeedUpdate_1,P_SIG,swLogPrintf("Cp PreSync Down , Set BT Precise Flag "); +265216,543422464,0,0,PLAT_AP,PLA_DRIVER,pmuEnterTickless_81,P_SIG,swLogPrintf("Hibernate Failed reason = %u "); +265216,543424512,0,0,PLAT_AP,PLA_DRIVER,pmuEnterTickless_82,P_SIG,swLogPrintf("Sleep2 Failed reason = %u "); +265216,543426560,0,0,PLAT_AP,PLA_DRIVER,pmuEnterTickless_83,P_VALUE,swLogPrintf("Sleep1 result = %u "); +265216,543429120,0,0,PLAT_AP,PLA_DRIVER,apmuCPSwPowerOn_2,P_VALUE,swLogPrintf("CP Power On : cpState = %d , apLLBootFlag = %d , csmbOn = %d "); +265216,543430656,0,0,PLAT_AP,PLA_DRIVER,apmuCPSwPowerOn_3,P_VALUE,swLogPrintf("CP Power On flow cost %d cycles "); +265216,543433216,0,0,PLAT_AP,PLA_DRIVER,apmuCaculateCpSleepMs_0,P_VALUE,swLogPrintf("curr hfnsfnsbn is 0x%X , cp wakeup hfnsfnsbn is 0x%X delta = %d ms "); +265216,543436032,0,0,PLAT_AP,PLA_DRIVER,apmuGetDefaultTimingCfg_1,P_VALUE,swLogPrintf("PmuTiming CodeRunTime , Pre = %d , %d , %d , Post = %d , %d , %d "); +265216,543437568,0,0,PLAT_AP,PLA_DRIVER,apmuGetDefaultTimingCfg_2,P_VALUE,swLogPrintf("PmuTiming FlashWrTime = %d , WorthTime = %d , %d , %d "); +265216,543440128,0,0,PLAT_AP,PLA_DRIVER,apmuSetTimingCfg_1,P_VALUE,swLogPrintf("PmuTiming CodeRunTime , Pre = %d , %d , %d , Post = %d , %d , %d "); +265216,543441664,0,0,PLAT_AP,PLA_DRIVER,apmuSetTimingCfg_2,P_VALUE,swLogPrintf("PmuTiming FlashWrTime = %d , WorthTime = %d , %d , %d "); +265216,543443456,0,0,PLAT_AP,PLA_DRIVER,pmuCheckCodeRunTimeEnd_1,P_ERROR,swLogPrintf("!!!!!!! PMU Run Time Checker %d OverRange , %d>%d !!!!!!!!! "); +265216,543445504,0,0,PLAT_AP,PLA_DRIVER,pmuCheckCodeRunTimeEnd_2,P_VALUE,swLogPrintf("!!!!!!! PMU Run Time Checker %d Too Long , %d<<%d !!!!!!!!! "); +265216,543447040,0,0,PLAT_AP,PLA_DRIVER,timerListAonAdd_0,P_VALUE,swLogPrintf("HibTimer : Aontimer %d add to list "); +265216,543449088,0,0,PLAT_AP,PLA_DRIVER,timerListAonDel_0,P_VALUE,swLogPrintf("HibTimer : Aontimer %d delete from list "); +265216,543451136,0,0,PLAT_AP,PLA_DRIVER,hibTimerAdd_0,P_WARNING,swLogPrintf("HibTimer : TimerList full ID = %d "); +265216,543453184,0,0,PLAT_AP,PLA_DRIVER,hibTimerUsrAdd_0,P_WARNING,swLogPrintf("HibTimer : User TimerList full ID = %d "); +265216,543455488,0,0,PLAT_AP,PLA_DRIVER,hibTimerDelete_0,P_VALUE,swLogPrintf("HibTimer : hibtimer delete success ID = %d index = %d "); +265216,543457280,0,0,PLAT_AP,PLA_DRIVER,hibTimerDelete_1,P_WARNING,swLogPrintf("HibTimer : hibtimer delete failed ID = %d "); +265216,543459584,0,0,PLAT_AP,PLA_DRIVER,hibTimerUsrDelete_0,P_VALUE,swLogPrintf("HibTimer : Usr hibtimer delete success ID = %d index = %d "); +265216,543461376,0,0,PLAT_AP,PLA_DRIVER,hibTimerUsrDelete_1,P_WARNING,swLogPrintf("HibTimer : User hibtimer delete failed ID = %d "); +265216,543464192,0,0,PLAT_AP,PLA_DRIVER,hibTimerCalculateTargetHibCnt_0,P_VALUE,swLogPrintf("HibTimer : Timer ID = %d , Handle = 0x%x , TargetValue = 0x%x , i = %d "); +265216,543466240,0,0,PLAT_AP,PLA_DRIVER,hibTimerCalculateTargetHibCnt_1,P_VALUE,swLogPrintf("HibTimer : User Timer ID = %d , Handle = 0x%x , TargetValue = 0x%x , i = %d "); +265216,543468032,0,0,PLAT_AP,PLA_DRIVER,hibTimerCalculateTargetHibCnt_2,P_VALUE,swLogPrintf("HibTimer : Aon Timer ID = %d , Handle = 0x%x , TargetValue = 0x%x "); +265216,543469824,0,0,PLAT_AP,PLA_DRIVER,hibTimerUsrGetRemainMs_0,P_VALUE,swLogPrintf("HibTimer : User Timer ID = %d , Remain Time = %d ms "); +265216,543471872,0,0,PLAT_AP,PLA_DRIVER,hibTimerUsrGetRemainMs_1,P_VALUE,swLogPrintf("HibTimer : User Timer ID = %d , Remain Time = %d ms "); +265216,543473664,0,0,PLAT_AP,PLA_DRIVER,hibTimerUsrGetRemainMs_2,P_VALUE,swLogPrintf("HibTimer : User Timer not exist , timerId = %d "); +265216,543477759,0,0,PLAT_AP,PLA_DRIVER,hibTimerCheckFlashUpdate_0,P_VALUE,swLogPrintf("HibTimer : DeepSleep Timer Need Update Flash "); +265216,543478016,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_1,P_VALUE,swLogPrintf("HibTimer : Timer Exceed ID = %d , Exceed HibCnt = %d "); +265216,543480064,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_2,P_VALUE,swLogPrintf("HibTimer : Timer In Advance ID = %d , In Advance HibCnt = %d "); +265216,543482368,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_3,P_VALUE,swLogPrintf("HibTimer : Start Timer ID = %d , Remain HibCnt = %d , Remain ms = %d \n "); +265216,543484160,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_4,P_VALUE,swLogPrintf("HibTimer : User Timer Exceed ID = %d , Exceed HibCnt = %d "); +265216,543486208,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_5,P_VALUE,swLogPrintf("HibTimer : User Timer In Advance ID = %d , In Advance HibCnt = %d "); +265216,543488512,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_6,P_VALUE,swLogPrintf("HibTimer : Start User Timer ID = %d , Remain HibCnt = %d , Remain ms = %d \n "); +265216,543490560,0,0,PLAT_AP,PLA_DRIVER,hibTimerWakeupRecreate_7,P_VALUE,swLogPrintf("HibTimer : Aon Timer After Slp , curHibCnt = 0x%x , targetCnt = 0x%x , remainMs = %d "); +265216,543493120,0,0,PLAT_AP,PLA_DRIVER,hibTimerBTCompensate_1,P_SIG,swLogPrintf("HibTimer BT Compensate : Timer ID = %d , remain_ms = %u to %u , CurHibCnt = %u , TarHibCnt = %u "); +265216,543495168,0,0,PLAT_AP,PLA_DRIVER,hibTimerBTCompensate_2,P_SIG,swLogPrintf("User HibTimer BT Compensate : Timer ID = %d , remain_ms = %u to %u , CurHibCnt = %u , TarHibCnt = %u "); +265216,543497216,0,0,PLAT_AP,PLA_DRIVER,hibTimerBTCompensate_3,P_SIG,swLogPrintf("Aon HibTimer BT Compensate : Timer ID = %d , remain_ms = %u to %u , CurHibCnt = %u , TarHibCnt = %u "); +265216,543498496,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_1,P_VALUE,swLogPrintf("HibTimer : Timer Exceed ID = %d , Exceed HibCnt = %d "); +265216,543500544,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_2,P_VALUE,swLogPrintf("HibTimer : Timer In Advance ID = %d , Remain HibCnt = %d "); +265216,543503104,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_3,P_VALUE,swLogPrintf("HibTimer : Check Wakeup Timer Id = %d , %d , Remain HibCnt = %d about %d ms \n "); +265216,543504640,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_4,P_VALUE,swLogPrintf("HibTimer : Timer Nearly trigger , Id = %d remain = %d ms "); +265216,543506688,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_5,P_VALUE,swLogPrintf("HibTimer : sw cnt id = %d , target = %d "); +265216,543508736,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_7,P_VALUE,swLogPrintf("HibTimer : User Timer Exceed ID = %d , Exceed HibCnt = %d "); +265216,543510784,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_8,P_VALUE,swLogPrintf("HibTimer : User Timer In Advance ID = %d , Remain HibCnt = %d "); +265216,543513344,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_9,P_VALUE,swLogPrintf("HibTimer : Check Wakeup Timer User Id = %d , %d , HibCnt = %d about %d ms \n "); +265216,543514880,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_10,P_VALUE,swLogPrintf("HibTimer : User Timer Nearly trigger , Id = %d remain = %d ms "); +265216,543516928,0,0,PLAT_AP,PLA_DRIVER,hibTimerNeedSwitchFullImg_11,P_VALUE,swLogPrintf("HibTimer : Aon Timer %d need wakeup remain = %d ms "); +265216,543518976,0,0,PLAT_AP,PLA_DRIVER,hibTimerGetNearestMs_0,P_VALUE,swLogPrintf("HibTimer : Remain HibCnt = %d , ID = %d "); +265216,543521024,0,0,PLAT_AP,PLA_DRIVER,hibTimerGetNearestMs_1,P_VALUE,swLogPrintf("User HibTimer : Remain HibCnt = %d , ID = %d "); +265216,543523072,0,0,PLAT_AP,PLA_DRIVER,hibTimerGetNearestMs_2,P_VALUE,swLogPrintf("Aon HibTimer : Aon Timer %d , remain %d hibCnt "); +265216,543525376,0,0,PLAT_AP,PLA_DRIVER,apmuSdkFlashWrReq_1,P_VALUE,swLogPrintf("Flash Write Request ID = %d , Write Flag = 0x%x , apFlashWrBm = 0x%x "); +265216,543526912,0,0,PLAT_AP,PLA_DRIVER,apmuSdkFlashBlockBeWr_1,P_WARNING,swLogPrintf("Check whether Flash block need Write , request ID = %d not valid , return FALSE "); +265216,543528960,0,0,PLAT_AP,PLA_DRIVER,apmuTestFlashWrReq_1,P_WARNING,swLogPrintf("Test Flash Wr Flag = 0x%x "); +265216,543531776,0,0,PLAT_AP,PLA_DRIVER,apmuTestPrintFlashFlag_1,P_WARNING,swLogPrintf("Print Flash Wr Flag = 0x%x , Clr Flag = 0x%x APBitmap = 0x%x , CPBitmap = 0x%x "); +265216,543535103,0,0,PLAT_AP,PLA_DRIVER,apmuGetPhyFlashWrReq_0,P_VALUE,swLogPrintf("apmuGetPhyFlashWrReq , cp no need to write flash "); +265216,543535104,0,0,PLAT_AP,PLA_DRIVER,apmuGetPhyFlashWrReq_1,P_VALUE,swLogPrintf("apmuGetPhyFlashWrReq , cpFlashWr_bm = 0x%x "); +265216,543539199,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashRGCntWrite_1,P_ERROR,swLogPrintf("Erase Flash Error!!! "); +265216,543541247,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashRGCntWrite_2,P_ERROR,swLogPrintf("Write Flash Cnt Error!!! "); +265216,543543295,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashRGCntWrite_3,P_ERROR,swLogPrintf("Erase Flash Error in Paging Image!!! "); +265216,543545343,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashRGCntWrite_4,P_ERROR,swLogPrintf("Write Flash Cnt Error in Paging Image!!! "); +265216,543545856,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashRGCntWrite_5,P_VALUE,swLogPrintf("Flash RG Cnt update time1 = %d , time2 = %d , time3 = %d "); +265216,543547904,0,0,PLAT_AP,PLA_DRIVER,pmuRawFlashRGIntegrityCheck_0,P_VALUE,swLogPrintf("Raw Flash Integrity Check Failed , Item = %d BlockNum = %d WriteCnt = 0x%x "); +265216,543550976,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashInitCheck_1,P_VALUE,swLogPrintf("CopyNum = %d Raw Flash PlatPs = 0x%x , 0x%x , 0x%x , 0x%x , Phy = 0x%x , 0x%x "); +265216,543551744,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashInitCheck_2,P_VALUE,swLogPrintf("Invalid Flash Sector , CopyNum = %d , Item = %d "); +265216,543555072,0,0,PLAT_AP,PLA_DRIVER,apmuRawFlashInitCheck_3,P_VALUE,swLogPrintf("CopyNum = %d Raw Flash PlatPs = 0x%x , 0x%x , 0x%x , 0x%x , Phy = 0x%x , 0x%x "); +265216,543555840,0,0,PLAT_AP,PLA_DRIVER,apmuCheckAndEraseFlash_0,P_SIG,swLogPrintf("cpflashWrMap = 0x%x , gSdkFlashOperate.cpFlashWr_bm = 0x%x "); +265216,543558144,0,0,PLAT_AP,PLA_DRIVER,apmuCheckAndEraseFlash_1,P_SIG,swLogPrintf("Start Erase Item = %d , Erase Cnt = %x , Region = %d "); +265216,543561727,0,0,PLAT_AP,PLA_DRIVER,apmuCheckAndEraseFlash_2,P_ERROR,swLogPrintf("Write Flash Cnt Error "); +265216,543563008,0,0,PLAT_AP,PLA_DRIVER,apmuGetCurRegionInfo_0,P_INFO,swLogPrintf("Raw flash Region Info , PlatPs = %d , %d , %d , %d , Phy = %d , %d "); +265216,543565056,0,0,PLAT_AP,PLA_DRIVER,apmuGetCurRegionInfo_1,P_INFO,swLogPrintf("CopyNum = 0 Raw flash Region Info , PlatPs = 0x%x , 0x%x , 0x%x , 0x%x , Phy = 0x%x , 0x%x "); +265216,543567104,0,0,PLAT_AP,PLA_DRIVER,apmuGetCurRegionInfo_2,P_INFO,swLogPrintf("CopyNum = 1 Raw flash Region Info , PlatPs = 0x%x , 0x%x , 0x%x , 0x%x , Phy = 0x%x , 0x%x "); +265216,543569152,0,0,PLAT_AP,PLA_DRIVER,apmuGetCurRegionInfo_3,P_INFO,swLogPrintf("CopyNum = 2 Raw flash Region Info , PlatPs = 0x%x , 0x%x , 0x%x , 0x%x , Phy = 0x%x , 0x%x "); +265216,543571200,0,0,PLAT_AP,PLA_DRIVER,apmuGetCurRegionInfo_4,P_INFO,swLogPrintf("CopyNum = 3 Raw flash Region Info , PlatPs = 0x%x , 0x%x , 0x%x , 0x%x , Phy = 0x%x , 0x%x "); +265216,543571968,0,0,PLAT_AP,PLA_DRIVER,apmuCpFlashBmNeedUpdate_0,P_SIG,swLogPrintf("cpFlashBm Need Update , cpFlashWrBm = 0x%x "); +265216,543576063,0,0,PLAT_AP,PLA_DRIVER,apmuApFlashMemRestore_1,P_VALUE,swLogPrintf("AP Flash Memory Restore "); +265216,543578111,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_0,P_ERROR,swLogPrintf("Raw flash write phy sector error "); +265216,543578112,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_1,P_INFO,swLogPrintf("Raw flash readback phy sector Success , i = %d "); +265216,543580928,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_2,P_ERROR,swLogPrintf("Raw flash readback phy sector Failed , i = %d , j = %d , WriteValue = 0x%x ReadBack = 0x%x "); +265216,543582464,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_3,P_VALUE,swLogPrintf("Raw flash update for phy , cost time = %d cycles , gCPAonMsmbCopyValid = %d "); +265216,543586303,0,0,PLAT_AP,PLA_DRIVER,PmuUpdateFlash_4,P_ERROR,swLogPrintf("Raw flash write platps sector error "); +265216,543586304,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_5,P_INFO,swLogPrintf("Raw flash readback platps sector Success , i = %d "); +265216,543589120,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_6,P_INFO,swLogPrintf("Raw flash readback platps sector Failed , i = %d , j = %d , WriteValue = 0x%x ReadBack = 0x%x "); +265216,543590400,0,0,PLAT_AP,PLA_DRIVER,apmuUpdateFlash_7,P_VALUE,swLogPrintf("Raw flash update for platps , cost time = %d cycles "); +265216,543594495,0,0,PLAT_AP,PLA_DRIVER,apmuRecoverCPPmuMemory_2,P_VALUE,swLogPrintf("CP Never request to write flash "); +265216,543596543,0,0,PLAT_AP,PLA_DRIVER,apmuRecoverCPPmuMemory_0,P_VALUE,swLogPrintf("Recover CP AonMem From MSMB "); +265216,543598591,0,0,PLAT_AP,PLA_DRIVER,apmuRecoverCPPmuMemory_1,P_VALUE,swLogPrintf("Recover CP AonMem From AP Flash "); +265216,543600639,0,0,PLAT_AP,PLA_DRIVER,slpManApplyPlatVoteHandle_0,P_WARNING,swLogPrintf("V-Apy with no name "); +265216,543602687,0,0,PLAT_AP,PLA_DRIVER,slpManApplyPlatVoteHandle_1,P_WARNING,swLogPrintf("V-Apy with invalid name "); +265216,543604735,0,0,PLAT_AP,PLA_DRIVER,slpManApplyPlatVoteHandle_3,P_WARNING,swLogPrintf("V-Apy Vote Handle Full "); +265216,543606783,0,0,PLAT_AP,PLA_DRIVER,slpManApplyPlatVoteHandle_4,P_WARNING,swLogPrintf("V-Apy Unknow ERROR "); +265216,543607040,0,0,PLAT_AP,PLA_DRIVER,slpManGivebackPlatVoteHandle_0,P_WARNING,swLogPrintf("V-Gbk Failed Invalid Handle = 0x%x , handle = %d "); +265216,543609088,0,0,PLAT_AP,PLA_DRIVER,slpManGivebackPlatVoteHandle_1,P_WARNING,swLogPrintf("V-Gbk Failed Sleep1 bitmap not Clear = 0x%x , handle = %d "); +265216,543611136,0,0,PLAT_AP,PLA_DRIVER,slpManGivebackPlatVoteHandle_2,P_WARNING,swLogPrintf("V-Gbk Failed Sleep2 bitmap not Clear = 0x%x , handle = %d "); +265216,543613184,0,0,PLAT_AP,PLA_DRIVER,slpManGivebackPlatVoteHandle_3,P_WARNING,swLogPrintf("V-Gbk Failed hib bitmap not Clear = 0x%x , handle = %d "); +265216,543615488,0,0,PLAT_AP,PLA_DRIVER,slpManPlatVoteDisableSleep_0,P_WARNING,swLogPrintf("Platform Vote Invalid Handle = 0x%x <- %d , status = %d "); +265216,543618048,0,0,PLAT_AP,PLA_DRIVER,slpManPlatVoteDisableSleep_1,P_VALUE,swLogPrintf("Platform Vote Result = 0x%x , 0x%x , 0x%x Handle = 0x%x , Return = %d "); +265216,543619584,0,0,PLAT_AP,PLA_DRIVER,slpManPlatVoteEnableSleep_0,P_WARNING,swLogPrintf("Platform Vote Invalid Handle = 0x%x <- %d , status = %d "); +265216,543622144,0,0,PLAT_AP,PLA_DRIVER,slpManPlatVoteEnableSleep_1,P_VALUE,swLogPrintf("Platform Vote Result = 0x%x , 0x%x , 0x%x Handle = 0x%x , Return = %d "); +265216,543623424,0,0,PLAT_AP,PLA_DRIVER,slpManPlatVoteForceEnableSleep_0,P_WARNING,swLogPrintf("Platform Vote Invalid Handle = 0x x% <- %d , status = %d "); +265216,543626240,0,0,PLAT_AP,PLA_DRIVER,slpManPlatVoteForceEnableSleep_1,P_VALUE,swLogPrintf("Platform Vote Result = 0x%x , 0x%x , 0x%x , Force Sleep Handle = %u , Return = %d "); +265216,543627264,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Expired,P_VALUE,swLogPrintf("User Deep Sleep Timer Expired ID = %d "); +265216,543629312,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_RegisterCb_0,P_ERROR,swLogPrintf("User HibTimer Callback is NULL , TimerID = %d "); +265216,543631616,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_RegisterCb_1,P_VALUE,swLogPrintf("User Register a Deep Sleep Timer Callback = 0x%x to TimerID = %d "); +265216,543633408,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Start_0,P_ERROR,swLogPrintf("User HibTimer timeout = 0 , TimerID = %d "); +265216,543635712,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Start_1,P_SIG,swLogPrintf("User DeepSleep Timer Renew ID = %d , ticks = %d "); +265216,543637760,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Start_2,P_SIG,swLogPrintf("User DeepSleep Timer Change Period ID = %d , ticks = %d "); +265216,543639808,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Start_3,P_SIG,swLogPrintf("Wakeup From User DeepSleep , Timer Restart ID = %d , ticks = %d "); +265216,543641856,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Start_4,P_SIG,swLogPrintf("User DeepSleep Timer New ID = %d , ticks = %d "); +265216,543643648,0,0,PLAT_AP,PLA_DRIVER,HibTimer_Usr_Del_0,P_VALUE,swLogPrintf("Delete DeepSleep Timer of User ID = %d "); +265216,543645952,0,0,PLAT_AP,PLA_DRIVER,slpManGetWakeupSrc_1,P_VALUE,swLogPrintf("slpMan WakeupBm = 0x%x , GetWakeupSrc = %e "); +265216,543647744,0,0,PLAT_AP,PLA_DRIVER,SlowCounter32KFreqSave_1,P_VALUE,swLogPrintf("32 KT Calibration Result = 0x%x "); +265216,543651839,0,0,PLAT_AP,PLA_DRIVER,SlowCounter32KTFreqGet_1,P_VALUE,swLogPrintf("32 K Calibration Result Invalid , use 32768 "); +265216,543651840,0,0,PLAT_AP,PLA_DRIVER,SlowCounter32KFreqReal_1,P_VALUE,swLogPrintf("32 K SlowCounter32KFreqReal = %u "); +265216,543655935,0,0,PLAT_AP,PLA_DRIVER,SlowCounterToSysTick_1,P_ERROR,swLogPrintf("Debug Assert : tmpSystick>0xffffffff "); +265216,543657983,0,0,PLAT_AP,PLA_DRIVER,SlowCounterToMs_1,P_ERROR,swLogPrintf("Debug Assert : tmpSc>0xffffffff "); +265216,543660031,0,0,PLAT_AP,PLA_DRIVER,SysTickToSlowCounter_1,P_ERROR,swLogPrintf("Debug Assert : tmpSc>0xffffffff "); +265216,543661056,0,0,PLAT_AP,PLA_DRIVER,SctErrIsr_e_1,P_ERROR,swLogPrintf("SCT ERROR! ErrStatus.masterErr : %d , ErrStatus.mgrErr : %d , ErrStatus.descErr : %d , RDErrMem : 0x%x , WTErrMem : 0x%x "); +265216,543664127,0,0,PLAT_AP,PLA_DRIVER,SctErrIsr_dump_e_1,P_ERROR,swLogDump("SCT ERROR , SCT_RNDIS_PPP_CFG_REG : "); +265216,543666175,0,0,PLAT_AP,PLA_DRIVER,SctErrIsr_dump_e_2,P_ERROR,swLogDump("SCT ERROR , SCT_COMM_CFG_REG : "); +265216,543668223,0,0,PLAT_AP,PLA_DRIVER,SctErrIsr_dump_e_3,P_ERROR,swLogDump("SCT ERROR , SCT_CHANNELS_CFG_REG : "); +265216,543670271,0,0,PLAT_AP,PLA_DRIVER,SctErrIsr_dump_e_4,P_ERROR,swLogDump("SCT ERROR , SCT_MEM_GUARD_CFG_REG : "); +265216,543672319,0,0,PLAT_AP,PLA_DRIVER,SctErrIsr_dump_e_5,P_ERROR,swLogDump("SCT ERROR , SCT_CHS_STATE_REG : "); +265216,543674367,0,0,PLAT_AP,PLA_DRIVER,uldpUsbClrCmpltFlg_0,P_SIG,swLogPrintf("uldp help to clr xic in usb int context! "); +265216,543674368,0,0,PLAT_AP,PLA_DRIVER,vcom0_earlyinit_finish_1,P_WARNING,swLogPrintf("dlyalloc ret %d "); +265216,543676416,0,0,PLAT_AP,PLA_DRIVER,vcom1_earlyinit_finish_1,P_WARNING,swLogPrintf("dlyalloc ret %d "); +265216,543678464,0,0,PLAT_AP,PLA_DRIVER,vcom2_earlyinit_finish_1,P_WARNING,swLogPrintf("dlyalloc ret %d "); +265216,543680512,0,0,PLAT_AP,PLA_DRIVER,vcom3_earlyinit_finish_1,P_WARNING,swLogPrintf("dlyalloc ret %d "); +265216,543684607,0,0,PLAT_AP,PLA_DRIVER,ecm_func_hostdet_update_1,P_SIG,swLogPrintf("ecm host detect "); +265216,543686655,0,0,PLAT_AP,PLA_DRIVER,usb_ecm_ctrl_xfer_comp_1,P_INFO,swLogPrintf(""); +265216,543686912,0,0,PLAT_AP,PLA_DRIVER,usb_ecm_ext_xfer_1,P_INFO,swLogPrintf("notify tx stat %d , xfer_cur_stat %d "); +265216,543688704,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_func_setup_1,P_DEBUG,swLogPrintf("dtoh , ext buf len %x "); +265216,543690752,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_func_setup_2,P_DEBUG,swLogPrintf("dtoh , int listbuf len %x "); +265216,543692800,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_func_setup_3,P_DEBUG,swLogPrintf("dtoh , intern enbuf len %x "); +265216,543694848,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_func_setup_4,P_DEBUG,swLogPrintf("htod , reqlen %x "); +265216,543696896,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_ep0_dout_stage_comp_1,P_DEBUG,swLogPrintf("MsgType %x "); +265216,543700991,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_ep0_dout_stage_comp_2,P_DEBUG,swLogDump("encap buf data : "); +265216,543703039,0,0,PLAT_AP,PLA_DRIVER,rndis_func_datain_1,P_DEBUG,swLogPrintf("notify xfer comp "); +265216,543705087,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_diep_xfer_cond_1,P_WARNING,swLogPrintf("ext xfer ignored "); +265216,543705088,0,0,PLAT_AP,PLA_DRIVER,rndis_diep_ext_xfer_req_1,P_DEBUG,swLogPrintf("xfer conn stat %d "); +265216,543707136,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_diep_xfer_finish_1,P_DEBUG,swLogPrintf("poll mode detected val %d "); +265216,543711231,0,0,PLAT_AP,PLA_DRIVER,rndis_func_gen_xfer_mux_src_1,P_DEBUG,swLogPrintf("internal encbuf overlap "); +265216,543713279,0,0,PLAT_AP,PLA_DRIVER,rndis_func_gen_xfer_mux_src_2,P_DEBUG,swLogPrintf("exernal encbuf overlap "); +265216,543713536,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_int_encbuf_xfer_1,P_DEBUG,swLogPrintf("notify tx stat %d , xfer_cur_stat %d "); +265216,543715584,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_int_listbuf_xfer_1,P_DEBUG,swLogPrintf("notify tx stat %d , xfer_cur_stat %d "); +265216,543717632,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_ext_xfer_1,P_DEBUG,swLogPrintf("notify tx stat %d , xfer_cur_stat %d "); +265216,543719424,0,0,PLAT_AP,PLA_DRIVER,usb_rndis_auto_next_notify_1,P_DEBUG,swLogPrintf("ext_buf|int_encbuf|int_listbuf 0x%x "); +265216,543721472,0,0,PLAT_AP,PLA_DRIVER,vcom_tplfunc_setup_1,P_WARNING,swLogPrintf("rxtransfer wLength %d "); +265216,543723520,0,0,PLAT_AP,PLA_DRIVER,vcom_tplfunc_try_notify_xfer_1,P_INFO,swLogPrintf("notify tx stat %d "); +265216,543725824,0,0,PLAT_AP,PLA_DRIVER,t_usbd_multi_ep_record_1,P_WARNING,swLogPrintf("ep_idx %d , max_pktsz %d "); +265216,543727616,0,0,PLAT_AP,PLA_DRIVER,t_usbd_multi_ep_record_2,P_WARNING,swLogPrintf("inep mps 8 / 512 [ high / low 16 bits ] map 0x%x "); +265216,543731711,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_1,P_ERROR,swLogPrintf("pfunc_mtd->func_desc_get_cfginfo = = NULL "); +265216,543731712,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_2,P_ERROR,swLogPrintf("cfginfo.epin_num %d "); +265216,543733760,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_3,P_ERROR,swLogPrintf("cfginfo.epout_num %d "); +265216,543736064,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_4,P_ERROR,swLogPrintf("func_elem_idx %d , arr cnt %d "); +265216,543739903,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_5,P_ERROR,swLogPrintf("func_desc_get_clstype "); +265216,543739904,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_6,P_ERROR,swLogPrintf("cls_type %d "); +265216,543742208,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_8_1,P_ERROR,swLogPrintf("loop_idx %d , ep_idx %d "); +265216,543744256,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_8_2,P_ERROR,swLogPrintf("loop_idx %d , ep_idx %d , valid already "); +265216,543746560,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_8_5,P_WARNING,swLogPrintf("ep_idx %d , loop_idx %d , attr %d "); +265216,543748096,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_9_1,P_ERROR,swLogPrintf("ep_idx %d "); +265216,543750400,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_9_2,P_ERROR,swLogPrintf("ep_idx %d , arr_cnt %d "); +265216,543754239,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_9_3,P_ERROR,swLogPrintf("ep mapped already "); +265216,543754752,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_9_6,P_WARNING,swLogPrintf("ep_idx %d , loop_idx %d , attr %d "); +265216,543756288,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_load_locmap_10,P_WARNING,swLogPrintf("func_info_result32 0x%x "); +265216,543758592,0,0,PLAT_AP,PLA_DRIVER,usb_multi_ep0_dout_stage_comp_1,P_ERROR,swLogPrintf("p_usb_func %d , intf_idx %d "); +265216,543760384,0,0,PLAT_AP,PLA_DRIVER,usb_multi_ep0_dout_stage_comp_2,P_ERROR,swLogPrintf("intf_idx %d , bind_flag NULL "); +265216,543762432,0,0,PLAT_AP,PLA_DRIVER,usb_multi_ep0_dout_stage_comp_3,P_ERROR,swLogPrintf("intf_idx %d , pfunc_mtd NULL "); +265216,543764480,0,0,PLAT_AP,PLA_DRIVER,usb_multi_ep0_dout_stage_comp_4,P_ERROR,swLogPrintf("intf_idx %d , func_ep0_dout_stage_comp NULL "); +265216,543766528,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_func_fill_1,P_ERROR,swLogPrintf("p_multidev_load->load_cnt %d error "); +265216,543768832,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_func_fill_2_0,P_ERROR,swLogPrintf("load_idx %d , map_res_idx %d "); +265216,543770880,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_func_fill_2_1,P_ERROR,swLogPrintf("usbd_mutli_func_tbl [ %d ] = = NULL , map_res_idx %d "); +265216,543772928,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_func_fill_3,P_ERROR,swLogPrintf("usbd_mutli_bind_pfn_tbl [ %d ] = = NULL , map_res_idx %d "); +265216,543775234,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_func_fill_4,P_WARNING,swLogPrintf("[ %d ] = %s , type = %d "); +265216,543776768,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_ccinst_fill_1,P_ERROR,swLogPrintf("p_multidev_load->load_cnt %d "); +265216,543778816,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_ccinst_fill_2_1,P_ERROR,swLogPrintf("usbd_mutli_func_tbl [ %d ] = = NULL "); +265216,543781376,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_ccinst_fill_2_2,P_ERROR,swLogPrintf("clstype %d , inst_id , maintp %d , subtp %d , "); +265216,543784959,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_ccinst_fill_3,P_WARNING,swLogPrintf("success "); +265216,543787007,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_custom_filter_fill_1,P_ERROR,swLogPrintf("p_multidev_custom_org = = NULL "); +265216,543787008,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_custom_filter_fill_2,P_WARNING,swLogPrintf("p_dev_name = = NULL , cust_idx %d "); +265216,543789056,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_custom_filter_fill_3,P_WARNING,swLogPrintf("rndis filter , cust_idx %d "); +265216,543791104,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_custom_filter_fill_4,P_WARNING,swLogPrintf("ecm filter , cust_idx %d "); +265216,543793152,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_custom_filter_fill_5,P_WARNING,swLogPrintf("p_multidev_custom_filter->elem_cnt %d "); +265216,543795200,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_update_1,P_ERROR,swLogPrintf("p_multidev_load->load_stat %d "); +265216,543797248,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_update_3,P_ERROR,swLogPrintf("p_multidev_custom_filter->elem_cnt %d "); +265216,543799296,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_update_4_2,P_ERROR,swLogPrintf("elem_update_stat %d "); +265216,543801344,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_update_5,P_ERROR,swLogPrintf("cust_idx %d "); +265216,543803392,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_update_8,P_WARNING,swLogPrintf("finded result 0x%x after filter "); +265216,543805440,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_end_1,P_ERROR,swLogPrintf("fail %d "); +265216,543809535,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_end_2,P_ERROR,swLogPrintf("ccinst fill fail "); +265216,543809536,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_load_end_3,P_ERROR,swLogPrintf("fail %d "); +265216,543811584,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_clstype_fill_1,P_ERROR,swLogPrintf("p_multidev_load->load_cnt %d "); +265216,543813888,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_clstype_fill_2_1,P_ERROR,swLogPrintf("clstype_result32 0x%x , map_res_result32 = 0x%x "); +265216,543815680,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_clstype_fill_2_2,P_ERROR,swLogPrintf("usbd_mutli_bind_pfn_tbl [ %d ] = = NULL "); +265216,543817984,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_clstype_fill_3_1,P_ERROR,swLogPrintf("clstype_result32 0x%x , map_res_result32 = 0x%x "); +265216,543821823,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_clstype_fill_3_2,P_ERROR,swLogPrintf("p_clsdev_base = = NULL "); +265216,543822336,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_clstype_fill_5,P_WARNING,swLogPrintf("map_res_result32 = 0x%x , clstype_result32 0x%x , ulog_cls_entry 0x%x "); +265216,543825919,0,0,PLAT_AP,PLA_DRIVER,usbd_mdev_bind_update_1,P_ERROR,swLogPrintf("clstype fill fail "); +265216,543825920,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_lib_usrcfg_global_init_1,P_ERROR,swLogPrintf("fail loc %d "); +265216,543830015,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_lib_usrcfg_update_bind_1,P_ERROR,swLogPrintf("fail "); +265216,543830784,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_lib_get_func_clstype_1,P_INFO,swLogPrintf("load_stat %x , func_idx %d , cls_type %d , ret%d "); +265216,543834111,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_libcall_cmndesc_1,P_ERROR,swLogPrintf("fail "); +265216,543834112,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_lib_dev_extmsg_1,P_ERROR,swLogPrintf("usbd_mutli_bind_pfn_tbl [ %d ] = = NULL "); +265216,543836416,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_lib_dev_extmsg_2,P_ERROR,swLogPrintf("%d , %d "); +265216,543840255,0,0,PLAT_AP,PLA_DRIVER,usbd_multi_lib_dev_extmsg_3,P_ERROR,swLogPrintf("para error "); +265216,543840512,0,0,PLAT_AP,PLA_DRIVER,ep_cfg_dump_1,P_ERROR,swLogPrintf("ep_idx %d , mps %d "); +265216,543842304,0,0,PLAT_AP,PLA_DRIVER,cfg_fifo_2,P_ERROR,swLogPrintf("totalused %x "); +265216,543844352,0,0,PLAT_AP,PLA_DRIVER,retwkups2_bkfifo_cfg_1,P_ERROR,swLogPrintf("totalused %x "); +265216,543846656,0,0,PLAT_AP,PLA_DRIVER,usbc_ctrl_epin_activate_1,P_WARNING,swLogPrintf("bkup_inep_dpid %x , epx %d "); +265216,543848704,0,0,PLAT_AP,PLA_DRIVER,usbc_ctrl_epout_activate_1,P_WARNING,swLogPrintf("bkup_oep_dpid %x , epx %d "); +265216,543850496,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_hibernate_wkup_intr_00,P_WARNING,swLogPrintf("gintr_status.d32 : %x "); +265216,543852544,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_hibernate_resume_intr_00,P_WARNING,swLogPrintf("gpwrdn : %x "); +265216,543854592,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_hibernate_reset_intr_1,P_WARNING,swLogPrintf("retval : %d "); +265216,543856640,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_hibernate_reset_intr_00,P_WARNING,swLogPrintf("hibwkgpwrdn : %x "); +265216,543858944,0,0,PLAT_AP,PLA_DRIVER,usbc_backup_essregs_1_0,P_WARNING,swLogPrintf("pcgcctl : %x , dcfg 0x%x "); +265216,543860992,0,0,PLAT_AP,PLA_DRIVER,usbc_backup_essregs_1_1,P_WARNING,swLogPrintf("bkup_inep_dpid : %x , bkup_oep_dpid%x "); +265216,543863040,0,0,PLAT_AP,PLA_DRIVER,usbc_restore_ess_regs_1,P_WARNING,swLogPrintf("pcgcctl : %x , dcfg 0x%x "); +265216,543866879,0,0,PLAT_AP,PLA_DRIVER,usbc_restore_wait_restoredone_1,P_WARNING,swLogPrintf("restoredone timeout "); +265216,543867392,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_hibernate_restore_1,P_WARNING,swLogPrintf("pcgcctl 0x%x , dcfg 0x%x , dctl : 0x%x "); +265216,543868928,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_hibernate_resume_intr_1,P_WARNING,swLogPrintf("dev stat : %x "); +265216,543873023,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_suspend_intr_0,P_WARNING,swLogPrintf("noret_hib_suspend already "); +265216,543873280,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_suspend_intr_1,P_WARNING,swLogPrintf("low_power %d , real_suspend : %d "); +265216,543877119,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_susp2hib_0,P_ERROR,swLogPrintf("real_suspend not match "); +265216,543879167,0,0,PLAT_AP,PLA_DRIVER,usbc_proc_susp2hib_1,P_ERROR,swLogPrintf("susp_res_pair_need not match "); +265216,543879168,0,0,PLAT_AP,PLA_DRIVER,usb_trace_step_1,P_WARNING,swLogPrintf("step : %d "); +265216,543881472,0,0,PLAT_AP,PLA_DRIVER,usb_trace_step_2,P_WARNING,swLogPrintf("step : %d , gintsts = 0x%x "); +265216,543884032,0,0,PLAT_AP,PLA_DRIVER,usb_trace_iep_1,P_WARNING,swLogPrintf("or_intsts %x , iepctl %x , iepsz %x , stage_or_txfsts %x "); +265216,543885312,0,0,PLAT_AP,PLA_DRIVER,usb_trace_oep_type_1,P_WARNING,swLogPrintf("iep_or_oep = %d "); +265216,543887872,0,0,PLAT_AP,PLA_DRIVER,usb_trace_oep_1,P_WARNING,swLogPrintf("or_intsts %x , oepctl %x , oepsz %x "); +265216,543889664,0,0,PLAT_AP,PLA_DRIVER,usb_iep_trace_wrtxfifo_1,P_WARNING,swLogPrintf("wr start , epnum %x , txf_sts %x "); +265216,543891968,0,0,PLAT_AP,PLA_DRIVER,usb_iep_trace_wrtxfifo_2,P_WARNING,swLogPrintf("epnum %x , wr len %x , txf_sts %x "); +265216,543895551,0,0,PLAT_AP,PLA_DRIVER,usb_trace_setup_1,P_WARNING,swLogDump("setup data : "); +265216,543895552,0,0,PLAT_AP,PLA_DRIVER,usb_iep0_start_xfer_1,P_WARNING,swLogPrintf("xfer_len_or_size %x "); +265216,543897856,0,0,PLAT_AP,PLA_DRIVER,dataout_handler_1,P_WARNING,swLogPrintf("stg %x , remainlen %x "); +265216,543899648,0,0,PLAT_AP,PLA_DRIVER,usb_uldp_oep0_start_xfer_1,P_WARNING,swLogPrintf("xfer_len %x "); +265216,543903743,0,0,PLAT_AP,PLA_DRIVER,usbd_trace_ep0_setup_breakstage_1,P_WARNING,swLogPrintf(""); +265216,543903744,0,0,PLAT_AP,PLA_DRIVER,usblpw_check_gpwrdn_lnstchg_1,P_WARNING,swLogPrintf("gpwrdn.b.linestate%d "); +265216,543906048,0,0,PLAT_AP,PLA_DRIVER,usblpw_noret_remote_wkup_1,P_SIG,swLogPrintf("pwr state %d , remote_wkup_en %d "); +265216,543907840,0,0,PLAT_AP,PLA_DRIVER,usblpw_noret_remote_wkup_2,P_WARNING,swLogPrintf("dev stat : %x "); +265216,543911935,0,0,PLAT_AP,PLA_DRIVER,usblpw_enable_lpusbwkup_src_1,P_VALUE,swLogPrintf("NVIC_GetPendingIRQ LpusbWakeup_IRQn true "); +265216,543911936,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_normal_0_1,P_VALUE,swLogPrintf("force_cfg_pwr_down %d "); +265216,543913984,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_normal_0_2,P_VALUE,swLogPrintf("force_cfg_pwr_down %d "); +265216,543916032,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_normal_1,P_VALUE,swLogPrintf("cur_pwr_state %d "); +265216,543918080,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_wkmon_0_1,P_VALUE,swLogPrintf("force_cfg_pwr_down 0x%x "); +265216,543920128,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_wkmon_0_2,P_VALUE,swLogPrintf("cur_pwr_state 0x%x "); +265216,543922176,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_wkmon_1,P_VALUE,swLogPrintf("cur_pwr_state 0x%x "); +265216,543924224,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_0_0,P_VALUE,swLogPrintf("ISER %x "); +265216,543926272,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_0_1,P_VALUE,swLogPrintf("force_cfg_pwr_down 0x%x "); +265216,543928320,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_start_proc_0_2,P_VALUE,swLogPrintf("cur_pwr_state 0x%x "); +265216,543930624,0,0,PLAT_AP,PLA_DRIVER,usblpw_enter_abort_proc_wkmon_1,P_VALUE,swLogPrintf("wkmon_ll_enter_ctx %d , wkmon_lpusbwkup_flag %d "); +265216,543932928,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_poll_gpwr_break_1,P_VALUE,swLogPrintf("gpwr_cur %x , gpwr_prev %x , hold cnt %d reset "); +265216,543935232,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_poll_gpwr_break_2,P_VALUE,swLogPrintf("gpwr_cur %x , gpwr_prev %x , hold cnt %d reset , break2_cnt %d "); +265216,543936768,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_poll_gpwr_break_3,P_VALUE,swLogPrintf("break_cnt %x , break2_cnt %x "); +265216,543938816,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_poll_gpwr_match_2,P_VALUE,swLogPrintf("stage %d , detect gpwr ( 0x%x ) timeout "); +265216,543941120,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_poll_gpwr_match_3,P_VALUE,swLogPrintf("detect cnt %x , gpwr_cur %x , detect gpwr ( 0x%x ) "); +265216,543942656,0,0,PLAT_AP,PLA_DRIVER,usblpw_pre_restore_1,P_VALUE,swLogPrintf("detect gpwr 0x%x "); +265216,543944704,0,0,PLAT_AP,PLA_DRIVER,usblpw_pre_restore_2,P_VALUE,swLogPrintf("usblpw_get_cur_pwr_state %d "); +265216,543948799,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_hibslp2_try_stack_rest_1,P_WARNING,swLogPrintf("usblpw_retothwk_stackrest_chk_illegal "); +265216,543950847,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_hibslp2_try_stack_rest_2,P_WARNING,swLogPrintf("usblpw_retothwk_hibslp2_stack_restore fail "); +265216,543952895,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_slp1_try_stack_rest_1,P_WARNING,swLogPrintf("usblpw_retothwk_stackrest_chk_illegal "); +265216,543954943,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_slp1_try_stack_rest_2,P_WARNING,swLogPrintf("usblpw_retwkup_slp1_stack_restore fail "); +265216,543954944,0,0,PLAT_AP,PLA_DRIVER,usblpw_retothwk_wkmon_actv_proc_1,P_WARNING,swLogPrintf("retothwk wkmon stage %d not match "); +265216,543956992,0,0,PLAT_AP,PLA_DRIVER,usb_lpwkup_step_show_1,P_VALUE,swLogPrintf("usb_lpwkup_step 0x%x "); +265216,543961087,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2hib_1,P_VALUE,swLogPrintf("reset "); +265216,543961088,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2hib_4,P_VALUE,swLogPrintf("permit %d "); +265216,543963136,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2hib_3,P_VALUE,swLogPrintf("dlychk %d "); +265216,543965184,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2hib_5,P_VALUE,swLogPrintf("usbc_proc_susp2hib %d "); +265216,543967232,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2hib_6,P_VALUE,swLogPrintf("premit_proc %d "); +265216,543971327,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_1_0,P_WARNING,swLogPrintf("guard none "); +265216,543971328,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_2_1,P_WARNING,swLogPrintf("invalid guard status %d "); +265216,543973376,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_2_2,P_VALUE,swLogPrintf("start %d "); +265216,543975424,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_4,P_VALUE,swLogPrintf("permit %d "); +265216,543977472,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_3,P_VALUE,swLogPrintf("dlychk %d "); +265216,543979520,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_5_1,P_VALUE,swLogPrintf("premit_proc %d "); +265216,543981568,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_5_2,P_VALUE,swLogPrintf("clear unexpect %d "); +265216,543983616,0,0,PLAT_AP,PLA_DRIVER,usblpw_susp2vbustbl_6,P_VALUE,swLogPrintf("unexpected guard state%d "); +265216,543987711,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_pre_recovery_0,P_WARNING,swLogPrintf("Disable LpusbWakeup_IRQn "); +265216,543987968,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_pre_recovery_1,P_VALUE,swLogPrintf("vbus_nvic rec %d , vbus_pad %d "); +265216,543990016,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_locinit_gint_regs,P_WARNING,swLogPrintf("gintsts 0x%x , gintmsk 0x%x "); +265216,543993855,0,0,PLAT_AP,PLA_DRIVER,usblpw_is_retothwks2_slp1_start_2,P_WARNING,swLogPrintf("Disable LpusbWakeup_IRQn "); +265216,543995903,0,0,PLAT_AP,PLA_DRIVER,usblpw_is_retothwks2_slp1_start_3,P_WARNING,swLogPrintf("usblpw_innophy_susp_chk_patch "); +265216,543995904,0,0,PLAT_AP,PLA_DRIVER,usblpw_is_retothwks2_slp1_start_4,P_WARNING,swLogPrintf("reg ctxstat %d unmatch "); +265216,543998208,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_locinit_1,P_VALUE,swLogPrintf("ctx state ( %d ) is not none , vbus_nvic rec %d , wkup hard restore skip "); +265216,544000256,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_locinit_2,P_VALUE,swLogPrintf("prev ctx state ( %d ) before slp1 not success , vbus [ 2 ] or pad [ 1 ] or vbus_nvic_r [ 0 ] 0x%x , wkup hard restore skip "); +265216,544002304,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_locinit_3,P_VALUE,swLogPrintf("vbus_nvic rec %d , vbus_pad %d "); +265216,544006143,0,0,PLAT_AP,PLA_DRIVER,usblpw_sleep1_later_recovery_2,P_ERROR,swLogPrintf("vbus_mode_en and vbus pad nvic enabled , conflict stat "); +265216,544006656,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_locinit_4,P_VALUE,swLogPrintf("hard_rest_warning or case 0x%x , usbslpmsk_en 0x%x , reg_retwkup_ctxstat 0x%x "); +265216,544008960,0,0,PLAT_AP,PLA_DRIVER,usblpw_retwkup_sleep1_locinit_6,P_VALUE,swLogPrintf("pwr state 0x%x , bootstat 0x%x , lastwkup 0x%x , inimod 0x%x "); +265216,544010240,0,0,PLAT_AP,PLA_DRIVER,usblpw_sleep1_later_recovery_nvic,P_VALUE,swLogPrintf("NVIC 0x%x "); +265216,544012800,0,0,PLAT_AP,PLA_DRIVER,usblpw_sleep1_later_recovery_1,P_VALUE,swLogPrintf("pwr state 0x%x , bootstat 0x%x , lastwkup 0x%x "); +265216,544016383,0,0,PLAT_AP,PLA_DRIVER,usbpcd_retwkup_stack_restore_1,P_ERROR,swLogPrintf("early init fail "); +265216,544018431,0,0,PLAT_AP,PLA_DRIVER,usbpcd_retwkup_stack_restore_2,P_ERROR,swLogPrintf("early load fail "); +265216,544020479,0,0,PLAT_AP,PLA_DRIVER,usbpcd_retwkup_stack_restore_3,P_ERROR,swLogPrintf("retwkup restore fail "); +265216,544022527,0,0,PLAT_AP,PLA_DRIVER,usbpcd_init_pre_1,P_WARNING,swLogPrintf("clk ungated "); +265216,544024575,0,0,PLAT_AP,PLA_DRIVER,usbpcd_init_1,P_ERROR,swLogPrintf("early init fail "); +265216,544026623,0,0,PLAT_AP,PLA_DRIVER,usbpcd_init_2,P_ERROR,swLogPrintf("early load fail "); +265216,544028671,0,0,PLAT_AP,PLA_DRIVER,usbpcd_init_3,P_ERROR,swLogPrintf("dev init fail "); +265216,544030719,0,0,PLAT_AP,PLA_DRIVER,usbpcd_proc_sim_cfgreq_1,P_VALUE,swLogPrintf("sim usb init start "); +265216,544030976,0,0,PLAT_AP,PLA_DRIVER,adcProxyVBatCallback_1,P_VALUE,swLogPrintf("raw_result = 0x%x , vbat = 0x%x "); +265216,544033024,0,0,PLAT_AP,PLA_DRIVER,adcProxyThermalCallback_1,P_VALUE,swLogPrintf("rawResult = 0x%x , Thermal = 0x%x "); +265216,544035072,0,0,PLAT_AP,PLA_DRIVER,HibTimer_PS_Start_0,P_SIG,swLogPrintf("DeepSleep Timer Renew ID = %d , ticks = %d "); +265216,544037120,0,0,PLAT_AP,PLA_DRIVER,HibTimer_PS_Start_1,P_SIG,swLogPrintf("DeepSleep Timer Change Period ID = %d , ticks = %d "); +265216,544039168,0,0,PLAT_AP,PLA_DRIVER,HibTimer_PS_Start_2,P_SIG,swLogPrintf("Wakeup From DeepSleep , Timer Restart ID = %d , ticks = %d "); +265216,544041216,0,0,PLAT_AP,PLA_DRIVER,HibTimer_PS_Start_3,P_SIG,swLogPrintf("DeepSleep Timer New ID = %d , ticks = %d "); +265216,544043008,0,0,PLAT_AP,PLA_DRIVER,HibTimer_PS_Del_1,P_SIG,swLogPrintf("DeepSleep Timer Delete ID = %d "); +265216,544047103,0,0,PLAT_AP,PLA_DRIVER,OsaGetFlashValue_1,P_INFO,swLogPrintf("get cclk time value , file not exist , create default one "); +265216,544049151,0,0,PLAT_AP,PLA_DRIVER,OsaGetFlashValue_2,P_INFO,swLogPrintf("get cclk time value , file header error , create default one "); +265216,544051199,0,0,PLAT_AP,PLA_DRIVER,OsaGetFlashValue_3,P_INFO,swLogPrintf("cclk time value file read sucess "); +265216,544053247,0,0,PLAT_AP,PLA_DRIVER,OsaSetFlashValue_1,P_INFO,swLogPrintf("set cclk time value , file not exist , create default one "); +265216,544055295,0,0,PLAT_AP,PLA_DRIVER,OsaSetFlashValue_2,P_INFO,swLogPrintf("cclk time value file write sucess "); +265216,544055811,0,0,PLAT_AP,PLA_DRIVER,assert_func_1,P_ERROR,swLogPrintf("Assert , expr : %s , file : %s , line : %d \r \n "); +265216,544059391,0,0,PLAT_AP,PLA_DRIVER,BSP_LoadPlatConfig_1,P_ERROR,swLogPrintf("Can ' t open ' plat_config ' file , use the defult value "); +265216,544061439,0,0,PLAT_AP,PLA_DRIVER,BSP_LoadPlatConfig_2,P_ERROR,swLogPrintf("Can ' t read ' plat_config ' file header , use the defult value "); +265216,544061440,0,0,PLAT_AP,PLA_DRIVER,BSP_LoadPlatConfig_5,P_ERROR,swLogPrintf("' plat_config ' version : %d not right , use the defult value "); +265216,544064000,0,0,PLAT_AP,PLA_DRIVER,BSP_LoadPlatConfig_3,P_ERROR,swLogPrintf("' plat_config ' version : %d file body size not right : ( %u / %u ) , use the defult value "); +265216,544066048,0,0,PLAT_AP,PLA_DRIVER,BSP_LoadPlatConfig_4,P_ERROR,swLogPrintf("Can ' t read ' plat_config ' version : %d file body , or body not right , ( %u / %u ) , use the defult value "); +265216,544069631,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfig_1,P_ERROR,swLogPrintf("Can ' t open / create ' plat_config ' file , save plat_config failed "); +265216,544071679,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfig_2,P_ERROR,swLogPrintf("Write ' plat_config ' file header failed "); +265216,544073727,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfig_3,P_ERROR,swLogPrintf("Write ' plat_config ' file body failed "); +265216,544075775,0,0,PLAT_AP,PLA_DRIVER,BSP_SetFSAssertCount_0,P_ERROR,swLogPrintf("Erase flash error!!! "); +265216,544077823,0,0,PLAT_AP,PLA_DRIVER,BSP_SetFSAssertCount_1,P_ERROR,swLogPrintf("Update fsAssertCount value error!!! "); +265216,544079871,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfigToRawFlash_1,P_ERROR,swLogPrintf("Erase flash error!!! "); +265216,544081919,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfigToRawFlash_2,P_ERROR,swLogPrintf("Save plat config to raw flash error!!! "); +265216,544083967,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfigToRawFlash_3,P_ERROR,swLogPrintf("Erase flash error!!! "); +265216,544086015,0,0,PLAT_AP,PLA_DRIVER,BSP_SavePlatConfigToRawFlash_4,P_ERROR,swLogPrintf("Save plat config to raw flash error!!! "); +265216,544088063,0,0,PLAT_AP,PLA_DRIVER,BSP_WriteToRawFlash_1,P_ERROR,swLogPrintf("Erase flash error!!! "); +265216,544090111,0,0,PLAT_AP,PLA_DRIVER,BSP_WriteToRawFlash_2,P_ERROR,swLogPrintf("Save plat config to raw flash error!!! "); +265216,544092159,0,0,PLAT_AP,PLA_DRIVER,BSP_WriteToRawFlash_3,P_ERROR,swLogPrintf("Erase flash error!!! "); +265216,544094207,0,0,PLAT_AP,PLA_DRIVER,BSP_WriteToRawFlash_4,P_ERROR,swLogPrintf("Save plat config to raw flash error!!! "); +265216,544094464,0,0,PLAT_AP,PLA_DRIVER,BSP_GET_PLAT_CFG_3,P_WARNING,swLogPrintf("non-identical baud between fs ( %d ) & raw ( %d ) ! "); +265216,544097024,0,0,PLAT_AP,PLA_DRIVER,apmuPeriLpuartPreSleepProcess_1,P_WARNING,swLogPrintf("lpuart status , iir : 0x%x , fcsr : 0x%x , tcr : 0x%x , tsr : 0x%x "); +265216,544099072,0,0,PLAT_AP,PLA_DRIVER,CLOCK_Trace_1,P_WARNING,swLogPrintf("Clock Trace , id = 0x%x isEnable = %d counter = %d , funcPtr = %x "); +265216,544100864,0,0,PLAT_AP,PLA_DRIVER,CLOCK_Trace_2,P_WARNING,swLogPrintf("Clock Trace , id = 0x%x counter = %d may overflow , funcPtr = %x "); +265216,544102656,0,0,PLAT_AP,PLA_DRIVER,CLOCK_clockEnable_1,P_WARNING,swLogPrintf("Clock Enable Failed , id = 0x%x counter = %d "); +265216,544104448,0,0,PLAT_AP,PLA_DRIVER,CLOCK_clockDisable_0,P_WARNING,swLogPrintf("Clock Disable check failed , id = 0x%x "); +265216,544106752,0,0,PLAT_AP,PLA_DRIVER,TIMER_netlightPWM_1,P_SIG,swLogPrintf("Netlight mode = %u Instance = %d "); +265216,544108544,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_init_1,P_WARNING,swLogPrintf("usb_wkup_pad_idx %d "); +265216,544110848,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_1_1,P_WARNING,swLogPrintf("filter reset detect evt %x , vbus %d "); +265216,544112896,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_1_2,P_WARNING,swLogPrintf("filter reset ( to ) evt %x , vbus %d "); +265216,544114944,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_2_1,P_WARNING,swLogPrintf("port filtered unstable evt %x , vbus %d "); +265216,544116992,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_2_2,P_WARNING,swLogPrintf("port vbus filter unstable level vbus last %d , vbus cur = %d "); +265216,544118784,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_2_3,P_WARNING,swLogPrintf("port filtered type2 ( to ) invalid vbus , evt %x , vbus 0 "); +265216,544120832,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_2_4,P_WARNING,swLogPrintf("port filtered type3 ( to ) invalid vbus , evt %x , vbus 1 "); +265216,544123136,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_2_5,P_WARNING,swLogPrintf("port vbus trigger warning , ctx stat not valid %x , vbus %d "); +265216,544125184,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_2_6,P_INFO,swLogPrintf("port vbus trigger , evt %x , vbus %d "); +265216,544129023,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_3_1,P_WARNING,swLogPrintf("BSP_UsbDeInit "); +265216,544131071,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_3_2,P_ERROR,swLogPrintf("BSP_UsbDeInit , ctx stat not match "); +265216,544133119,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_3_3,P_WARNING,swLogPrintf("BSP_UsbInit "); +265216,544135167,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_3_4,P_ERROR,swLogPrintf("BSP_UsbInit , ctx stat not match "); +265216,544135424,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_3_5,P_WARNING,swLogPrintf("port vbus last %d , vbus cur = %d "); +265216,544139263,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_4_1,P_WARNING,swLogPrintf("port stable wait evt change "); +265216,544139264,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_task_4_2,P_WARNING,swLogPrintf("port stable detect evt %x "); +265216,544141312,0,0,PLAT_AP,PLA_DRIVER,usb_portmon_intr_cb_1,P_INFO,swLogPrintf("wkup_val : 0x%x "); +265216,544144128,0,0,PLAT_AP,PLA_DRIVER,usbcustom_multidev_ccinfo_map_1,P_ERROR,swLogPrintf("clstype %d , inst_id %d , maintp %d , subtp %d "); +265216,544146176,0,0,PLAT_AP,PLA_DRIVER,usbcustom_multidev_ccinfo_map_2,P_ERROR,swLogPrintf("clstype %d , inst_id %d , maintp %d , subtp %d "); +265216,544147456,0,0,PLAT_AP,PLA_DRIVER,usbcustom_multidev_cfg_end_1,P_ERROR,swLogPrintf("p_multidev_load->load_cnt %x "); +265216,544150284,0,0,PLAT_AP,PLA_DRIVER,usbcustom_multidevstr_desc_1,P_DEBUG,swLogPrintf("cls_type %d , inst_id 0x%x , name %s , intf string %s "); +265216,544152321,0,0,PLAT_AP,PLA_DRIVER,usbcustom_multidev_cmndesc_1,P_DEBUG,swLogPrintf("name %s , cls = 0x%x , subcls 0x%x , protocol 0x%x "); +265216,544154372,0,0,PLAT_AP,PLA_DRIVER,usbcustom_multidev_ctrl_proc_1,P_DEBUG,swLogPrintf("cls_type = %d , inst_id %d , name %s , req 0x%x "); +265216,544156416,0,0,PLAT_AP,PLA_DRIVER,lpuart_recv_0,P_DEBUG,swLogPrintf("lpuart recv enter , iir : 0x%x , fcsr : 0x%x , tcr : 0x%x , tsr : 0x%x "); +265216,544158464,0,0,PLAT_AP,PLA_DRIVER,lpuart_recv_1,P_DEBUG,swLogPrintf("lpuart recv exit , iir : 0x%x , fcsr : 0x%x , tcr : 0x%x , tsr : 0x%x "); +265216,544160000,0,0,PLAT_AP,PLA_DRIVER,lpuart_wakeup_irq_1,P_SIG,swLogPrintf("LPUART->IIR : 0x%x , LPUART->FCSR : 0x%x "); +265216,544162816,0,0,PLAT_AP,PLA_DRIVER,lpuart_irq_0,P_DEBUG,swLogPrintf("Enter lpuart irq , iir : 0x%x , fcsr : 0x%x , tcr : 0x%x , tsr : 0x%x , rx_cnt : %d , "); +265216,544163840,0,0,PLAT_AP,PLA_DRIVER,lpuart_irq_3,P_DEBUG,swLogPrintf("CPU will transfer : %d "); +265216,544165888,0,0,PLAT_AP,PLA_DRIVER,lpuart_irq_2,P_DEBUG,swLogPrintf("DMA will transfer : %d "); +265216,544167936,0,0,PLAT_AP,PLA_DRIVER,lpuart_irq_4,P_DEBUG,swLogPrintf("Time out , CPU will transfer : %d "); +265216,544170496,0,0,PLAT_AP,PLA_DRIVER,CO_USART_IRQHandler_0,P_DEBUG,swLogPrintf("Enter co_uart irq , isr : 0x%x , fcnr : 0x%x , rx_cnt : %d "); +265216,544172032,0,0,PLAT_AP,PLA_DRIVER,CO_USART_IRQHandler_1,P_DEBUG,swLogPrintf("dma transfer done , cnt : %d "); +265216,544174336,0,0,PLAT_AP,PLA_DRIVER,CO_USART_DmaRxEvent_0,P_DEBUG,swLogPrintf("uart dma rx event , fcnr : %x , cnt : %d "); +265216,544178175,0,0,PLAT_AP,PLA_DRIVER,CO_USART_DmaRxEvent_1,P_DEBUG,swLogPrintf("uart dma rx complete "); +265216,544178688,0,0,PLAT_AP,PLA_DRIVER,USART_IRQHandler_0,P_DEBUG,swLogPrintf("isr : 0x%x , fcnr_reg : 0x%x , rx_cnt : %d "); +265216,544180224,0,0,PLAT_AP,PLA_DRIVER,USART_IRQHandler_1,P_INFO,swLogPrintf("dma transfer done , cnt : %d "); +265216,544182528,0,0,PLAT_AP,PLA_DRIVER,USART_DmaRxEvent_0,P_INFO,swLogPrintf("uart dma rx event , fcnr : %x , cnt : %d "); +265216,544186367,0,0,PLAT_AP,PLA_DRIVER,USART_DmaRxEvent_1,P_INFO,swLogPrintf("uart dma rx complete "); +265216,544188415,0,0,PLAT_AP,PLA_DRIVER,SoftSimInit_0,P_INFO,swLogPrintf("Softsim task has already been created "); +265216,544190463,0,0,PLAT_AP,PLA_DRIVER,SoftSimInit_1,P_INFO,swLogPrintf("Start softsim task "); +265216,544191488,0,0,PLAT_AP,PLA_DRIVER,ALM_exitLowPowerStateRestore_1,P_VALUE,swLogPrintf("Alarm Func Init : %d , %e - %d , %e , %e "); +265216,544194559,0,0,PLAT_AP,PLA_DRIVER,thmHigh_interruptHandler_0,P_WARNING,swLogPrintf("Thm Interrupt Enter : Temperature too high "); +265216,544196607,0,0,PLAT_AP,PLA_DRIVER,thmHigh_interruptHandler_1,P_VALUE,swLogPrintf("Thm Interrupt Enter : Temperature below threshold "); +265216,544198655,0,0,PLAT_AP,PLA_DRIVER,thmHigh_interruptHandler_2,P_VALUE,swLogPrintf("Alarm message send in isr error "); +265216,544200703,0,0,PLAT_AP,PLA_DRIVER,thmHigh_interruptHandler_3,P_VALUE,swLogPrintf("Alarm message queue not ready in isr "); +265216,544202751,0,0,PLAT_AP,PLA_DRIVER,vbatLow_interruptHandler_0,P_WARNING,swLogPrintf("Vbat Interrupt Enter : Bat volatage too low "); +265216,544204799,0,0,PLAT_AP,PLA_DRIVER,vbatLow_interruptHandler_1,P_VALUE,swLogPrintf("Vbat Interrupt Enter : Bat volatage above threshold "); +265216,544206847,0,0,PLAT_AP,PLA_DRIVER,vbatLow_interruptHandler_2,P_VALUE,swLogPrintf("Alarm message send in isr error "); +265216,544208895,0,0,PLAT_AP,PLA_DRIVER,vbatLow_interruptHandler_3,P_VALUE,swLogPrintf("Alarm message queue not ready in isr "); +265216,544209152,0,0,PLAT_AP,PLA_DRIVER,alarmTask_1,P_VALUE,swLogPrintf("alarmTask : type = %d , info = %d "); +265216,544212991,0,0,PLAT_AP,PLA_DRIVER,alarmThreadInit_1,P_VALUE,swLogPrintf("Alarm task queue init error "); +265216,544214016,0,0,PLAT_AP,PLA_DRIVER,alarmFuncInit_1,P_VALUE,swLogPrintf("Alarm Func Init : %d , %e - %d , %e , %e "); +265216,544217087,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtInit_1,P_VALUE,swLogPrintf("Log above print through uart "); +265216,544219135,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtInit_2,P_VALUE,swLogPrintf("Log below print through usb "); +265216,544221183,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtInit_4,P_VALUE,swLogPrintf("Log below print through usb "); +265216,544221184,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtInit_5,P_VALUE,swLogPrintf("USB IRQ usbDevLowLvlEvtInit Process Time = %d "); +265216,544223232,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtDinit_1,P_VALUE,swLogPrintf("USB IRQ usbDevLowLvlEvtDinit Process Time = %d "); +265216,544225280,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtReset_1,P_VALUE,swLogPrintf("USB IRQ usbDevLowLvlEvtReset Process Time = %d "); +265216,544229375,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtSuspend_1,P_VALUE,swLogPrintf("Log above print through usb "); +265216,544231423,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtSuspend_3,P_VALUE,swLogPrintf("Log below print through uart "); +265216,544231424,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtSuspend_4,P_VALUE,swLogPrintf("USB IRQ usbDevLowLvlEvtSuspend Process Time = %d "); +265216,544235519,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtResume_1,P_VALUE,swLogPrintf("Log above print through uart "); +265216,544237567,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtResume_2,P_VALUE,swLogPrintf("Low below print through usb "); +265216,544239615,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtResume_3,P_VALUE,swLogPrintf("Low below print through usb "); +265216,544239616,0,0,PLAT_AP,PLA_DRIVER,usbDevLowLvlEvtResume_4,P_VALUE,swLogPrintf("USB IRQ usbDevLowLvlEvtResume Process Time = %d "); +265216,544242176,0,0,PLAT_AP,PLA_DRIVER,npiLoadNvmConfig_4,P_ERROR,swLogPrintf("Can ' t read ' npiconfig.nvm ' version : %d file body , or body not right , ( %u / %u ) , use the defult value "); +265216,544243712,0,0,PLAT_AP,PLA_DRIVER,npiLoadNvmConfig_5,P_ERROR,swLogPrintf("' npiconfig.nvm ' version : %d not right , use the defult value "); +265216,544246272,0,0,PLAT_AP,PLA_DRIVER,xTimerGenericCommand_1,P_WARNING,swLogPrintf("OsTimer Operation in ISR , msgId = %u , value = %d , pTimer = 0x%x "); +266240,545261568,0,0,PLAT_AP,PLA_HAL,ApmuHandleScCalibrCancel,P_INFO,swLogPrintf("ApmuHandleScCalibration Cancelled! and timer status is %d "); +266240,545265663,0,0,PLAT_AP,PLA_HAL,ApmuScCalibrTimerExpired_0,P_INFO,swLogPrintf("ApmuScCalibrTimerExpired! "); +266240,545267711,0,0,PLAT_AP,PLA_HAL,ApmuHandleScCalibrReq_0,P_INFO,swLogPrintf("ApmuHandleScCalibrReq! "); +266240,545267712,0,0,PLAT_AP,PLA_HAL,SctPmuLowPowerExitCallBack_w_1,P_WARNING,swLogPrintf("SCT , callback should be only called before exit sleep1 , not : %d "); +266240,545269760,0,0,PLAT_AP,PLA_HAL,utfcEpnClear_w_1,P_WARNING,swLogPrintf("UTFC , clear EP : %d , failed !!!! "); +266240,545272064,0,0,PLAT_AP,PLA_HAL,SctAesShaChanlErrIsr_idx_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , AES SHA channel Info : %d / %d "); +266240,545273856,0,0,PLAT_AP,PLA_HAL,SctAesShaChanlErrIsr_idx_w_2,P_WARNING,swLogPrintf("SCT ERROR ISR , AES SHA channel , FIFO idx : %d "); +266240,545277951,0,0,PLAT_AP,PLA_HAL,SctAesShaChanlErrIsr_dump_w_3,P_WARNING,swLogDump("SCT ERROR ISR , AES SHA FIFO DESC DUMP : "); +266240,545279999,0,0,PLAT_AP,PLA_HAL,SctAesShaChanlErrIsr_dump_w_1,P_WARNING,swLogDump("SCT ERROR ISR , AES SHA channel DESC DUMP : "); +266240,545282047,0,0,PLAT_AP,PLA_HAL,SctAesShaInit_w_1,P_WARNING,swLogPrintf("SCT AES / SHA , can ' t create mutex "); +266240,545284095,0,0,PLAT_AP,PLA_HAL,SctAesShaInit_w_2,P_WARNING,swLogPrintf("SCT AES / SHA , can ' t create semaphore "); +266240,545286143,0,0,PLAT_AP,PLA_HAL,SctAesShaPollTrigger_w_1,P_WARNING,swLogPrintf("SCT AES / SHA , polling calc / triger failed "); +266240,545286144,0,0,PLAT_AP,PLA_HAL,SctAesShaOsTrigger_w_1,P_WARNING,swLogPrintf("SCT AES / SHA , wait for semphore failed : %d "); +266240,545288192,0,0,PLAT_AP,PLA_HAL,SctShaSegStart_addr_1,P_WARNING,swLogPrintf("SCT SHA , SHA HDR : 0x%x , can ' t be accessed by SCT "); +266240,545292287,0,0,PLAT_AP,PLA_HAL,SctShaSegStart_w_1,P_WARNING,swLogPrintf("SCT AES / SHA , busy , can ' t be started "); +266240,545294335,0,0,PLAT_AP,PLA_HAL,SctShaSegStart_w_2,P_WARNING,swLogPrintf("SCT SHA , can ' t be called in ISR "); +266240,545296383,0,0,PLAT_AP,PLA_HAL,SctShaSegStart_w_4,P_WARNING,swLogPrintf("SCT SHA , can ' t lock the mutex "); +266240,545296896,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_e_1,P_ERROR,swLogPrintf("SCT SHA , append input not right , shaMode : %d , pInput : %d , inputLen : %d "); +266240,545298432,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_addr_1,P_WARNING,swLogPrintf("SCT SHA , SHA input : 0x%x , can ' t be accessed by SCT "); +266240,545301248,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_w_1,P_WARNING,swLogPrintf("SCT SHA , channel state not right , init : %d , start : %d , shaMode : %d / %d "); +266240,545303296,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_w_2,P_WARNING,swLogPrintf("SCT SHA , channel state not right , init : %d , start : %d , mutexId : %d , semId : %d "); +266240,545304832,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_w_3,P_WARNING,swLogPrintf("SCT SHA , mutex locked by taskId : 0x%x , not curtaskId : 0x%x , ERROR! "); +266240,545308671,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_calc_w_1,P_ERROR,swLogPrintf("SCT SHA , SHA calc failed !!! "); +266240,545310719,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_calc_w_2,P_ERROR,swLogPrintf("SCT SHA , SHA calc backup data failed !!! "); +266240,545312767,0,0,PLAT_AP,PLA_HAL,SctShaAppendSeg_calc_w_3,P_ERROR,swLogPrintf("SCT SHA , SHA calc input data failed !!! "); +266240,545312768,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_addr_1,P_WARNING,swLogPrintf("SCT SHA , SHA output : 0x%x , can ' t be accessed by SCT "); +266240,545315584,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_w_1,P_WARNING,swLogPrintf("SCT SHA , SHA END , channel state not right , init : %d , start : %d , shaMode : %d / %d "); +266240,545317632,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_w_2,P_WARNING,swLogPrintf("SCT SHA , SHA END , channel state not right , init : %d , start : %d , mutexId : %d , semId : %d "); +266240,545319168,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_w_3,P_WARNING,swLogPrintf("SCT SHA , SHA END , mutex locked by taskId : 0x%x , not curtaskId : 0x%x , ERROR! "); +266240,545323007,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_w_4,P_WARNING,swLogPrintf("SCT SHA , SHA END , no input data before , ERROR "); +266240,545325055,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_calc_w_1,P_ERROR,swLogPrintf("SCT SHA , SHA END , SHA calc failed !!! "); +266240,545327103,0,0,PLAT_AP,PLA_HAL,SctShaSegEnd_calc_done_1,P_INFO,swLogPrintf("SCT SHA , SHA END , SHA calc done "); +266240,545327616,0,0,PLAT_AP,PLA_HAL,SctShaCala_w_input_1,P_WARNING,swLogPrintf("SCT SHA , input not right , pInput : 0x%x , inputLen : %d , shaOutput : 0x%x "); +266240,545329408,0,0,PLAT_AP,PLA_HAL,SctShaCala_w_input_2,P_WARNING,swLogPrintf("SCT SHA , input not right , shaHdr : 0x%x , shaHdrByteLen : %d "); +266240,545333247,0,0,PLAT_AP,PLA_HAL,SctShaCala_w_1,P_WARNING,swLogPrintf("SCT AES / SHA , busy , can ' t calc SHA "); +266240,545335295,0,0,PLAT_AP,PLA_HAL,SctShaCala_w_2,P_WARNING,swLogPrintf("SCT SHA , can ' t be called in ISR "); +266240,545337343,0,0,PLAT_AP,PLA_HAL,SctShaCala_w_4,P_WARNING,swLogPrintf("SCT SHA , busy , can ' t lock the mutex "); +266240,545337344,0,0,PLAT_AP,PLA_HAL,SctShaCala_allc_w_1,P_ERROR,swLogPrintf("SCT SHA , can ' t alloc buf in heap , size : %d "); +266240,545341439,0,0,PLAT_AP,PLA_HAL,SctShaCala_calc_w_1,P_ERROR,swLogPrintf("SCT SHA , SHA calc failed !!! "); +266240,545343487,0,0,PLAT_AP,PLA_HAL,SctShaCala_calc_done_1,P_INFO,swLogPrintf("SCT SHA , SHA calc done "); +266240,545345535,0,0,PLAT_AP,PLA_HAL,SctAesCalc_input_w_1,P_WARNING,swLogPrintf("SCT AES , no input !!! "); +266240,545346048,0,0,PLAT_AP,PLA_HAL,SctAesCalc_input_w_2,P_WARNING,swLogPrintf("SCT AES , invalid input , inputByteLen : %d , pInput : 0x%x , pOutput : 0x%x "); +266240,545347584,0,0,PLAT_AP,PLA_HAL,SctAesCalc_input_w_3,P_WARNING,swLogPrintf("SCT AES , invalid input , CK from input , but input CK is NULL , or not 4 bytes aligned : 0x%x "); +266240,545349632,0,0,PLAT_AP,PLA_HAL,SctAesCalc_input_w_4,P_WARNING,swLogPrintf("SCT AES , CBC / CTR mode , invalid input , IV is NULL , or not 4 bytes aligned : 0x%x "); +266240,545353727,0,0,PLAT_AP,PLA_HAL,SctAesCalc_input_w_5,P_WARNING,swLogPrintf("SCT AES , CK from EFUSE , but not support AES_256 , only support AES_128 / AES_192 "); +266240,545355775,0,0,PLAT_AP,PLA_HAL,SctAesCalc_w_1,P_WARNING,swLogPrintf("SCT AES / SHA , busy , can ' t calc AES "); +266240,545357823,0,0,PLAT_AP,PLA_HAL,SctAesCalc_w_2,P_WARNING,swLogPrintf("SCT AES , can ' t be called in ISR "); +266240,545359871,0,0,PLAT_AP,PLA_HAL,SctAesCalc_w_4,P_WARNING,swLogPrintf("SCT AES , busy , can ' t lock the mutex "); +266240,545361919,0,0,PLAT_AP,PLA_HAL,SctAesCalc_calc_w_1,P_ERROR,swLogPrintf("SCT AES , AES calc failed !!! "); +266240,545363967,0,0,PLAT_AP,PLA_HAL,SctAesCalc_calc_done_1,P_INFO,swLogPrintf("SCT AES , AES calc done "); +266240,545363968,0,0,PLAT_AP,PLA_HAL,SctNasChanlIsr_e_1,P_WARNING,swLogPrintf("SCT ISR , NAS channel , ChanState : 0x%x , but no ISR FUNC !!! "); +266240,545366272,0,0,PLAT_AP,PLA_HAL,SctNasChanlErrIsr_idx_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , NAS channel Info : %d / %d "); +266240,545368064,0,0,PLAT_AP,PLA_HAL,SctNasChanlErrIsr_idx_w_2,P_WARNING,swLogPrintf("SCT ERROR ISR , NAS channel , FIFO idx : %d "); +266240,545372159,0,0,PLAT_AP,PLA_HAL,SctNasChanlErrIsr_dump_w_3,P_WARNING,swLogDump("SCT ERROR ISR , NAS FIFO DESC DUMP : "); +266240,545374207,0,0,PLAT_AP,PLA_HAL,SctNasChanlErrIsr_dump_w_1,P_WARNING,swLogDump("SCT ERROR ISR , NAS channel DESC DUMP : "); +266240,545376255,0,0,PLAT_AP,PLA_HAL,SctNasChanlErrIsr_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , no NAS ISR callback !!! "); +266240,545376256,0,0,PLAT_AP,PLA_HAL,SctUpChanlIsr_e_1,P_WARNING,swLogPrintf("SCT ISR , UP channel , ChanState : 0x%x , but no ISR FUNC !!! "); +266240,545378560,0,0,PLAT_AP,PLA_HAL,SctUpChanlErrIsr_idx_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , UP channel Info : %d / %d "); +266240,545380352,0,0,PLAT_AP,PLA_HAL,SctUpChanlErrIsr_idx_w_2,P_WARNING,swLogPrintf("SCT ERROR ISR , UP channel , FIFO idx : %d "); +266240,545384447,0,0,PLAT_AP,PLA_HAL,SctUpChanlErrIsr_dump_w_3,P_WARNING,swLogDump("SCT ERROR ISR , UP FIFO DESC DUMP : "); +266240,545386495,0,0,PLAT_AP,PLA_HAL,SctUpChanlErrIsr_dump_w_1,P_WARNING,swLogDump("SCT ERROR ISR , UP channel DESC DUMP : "); +266240,545388543,0,0,PLAT_AP,PLA_HAL,SctUpChanlErrIsr_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , no UP ISR callback !!! "); +266240,545388544,0,0,PLAT_AP,PLA_HAL,SctNasChanlReset_w_1,P_WARNING,swLogPrintf("SCT NAS channel , can ' t waiting for reset done , chanlState : 0x%x "); +266240,545390592,0,0,PLAT_AP,PLA_HAL,SctUpChanlReset_w_1,P_WARNING,swLogPrintf("SCT UP channel , can ' t waiting for reset done , chanlState : 0x%x "); +266240,545394687,0,0,PLAT_AP,PLA_HAL,SctPppCrcChanlErrIsr_dump_w_1,P_WARNING,swLogDump("SCT ERROR ISR , sctCh2PppCrcCBA DUMP : "); +266240,545394944,0,0,PLAT_AP,PLA_HAL,SctPppCrcChanlErrIsr_idx_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , PPP channel , cfgIdx : %d , doneIdx : %d "); +266240,545398783,0,0,PLAT_AP,PLA_HAL,SctPppCrcChanlErrIsr_dump_w_3,P_WARNING,swLogDump("SCT ERROR ISR , PPP FIFO DESC DUMP : "); +266240,545400831,0,0,PLAT_AP,PLA_HAL,SctPppCrcChanlCheck_w_1,P_WARNING,swLogPrintf("SCT PPP CRC , API can ' t be called in ISR "); +266240,545400832,0,0,PLAT_AP,PLA_HAL,SctPppEscapeStatic_s_1,P_VALUE,swLogPrintf("SCT PPP , escape done , pkgNum : %d "); +266240,545403136,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_w_1,P_WARNING,swLogPrintf("SCT PPP , deescape , invalid input , two bytes 0x7E , validOffset : %d , length : %d "); +266240,545406975,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_7E_w_2,P_WARNING,swLogDump("SCT PPP , deescape error , input : "); +266240,545409023,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_7E_w_3,P_WARNING,swLogDump("SCT PPP , deescape error , only one 7 E , input : "); +266240,545409280,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_w_nopkg_1,P_WARNING,swLogPrintf("SCT PPP , deescape , no valid escaped PKG input , foundPppStart : %d , foundRawPkg : %d "); +266240,545413119,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_w_nopkg_2,P_WARNING,swLogPrintf("SCT PPP , deescape , all input escaped pkg invalid "); +266240,545414400,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_crc_nok,P_WARNING,swLogPrintf("SCT PPP , deescape , pkgIdx : %d / pkgNum : %d , crc not right : 0x%x , 0x%x , 0x%x , 0x%x "); +266240,545415680,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_len_nok,P_WARNING,swLogPrintf("SCT PPP , deescape , pkgIdx : %d / pkgNum : %d , deescape len : %d abnormal , should at least 2 bytes "); +266240,545417216,0,0,PLAT_AP,PLA_HAL,SctPppDeEscapeStatic_s_1,P_VALUE,swLogPrintf("SCT PPP , deescape done , pkgNum : %d "); +266240,545421311,0,0,PLAT_AP,PLA_HAL,SctPppEscapeAccmConfig_w_1,P_WARNING,swLogPrintf("SCT PPP , set ACCM , but SCT PPP Tx is ongoing , pending cur ACCM cfg "); +266240,545422080,0,0,PLAT_AP,PLA_HAL,SctPppEscapeCalcSize_w_1,P_WARNING,swLogPrintf("SCT PPP , calc size , invalid input : : pHead : 0x%x , pOutList : 0x%x , listSize : %d , pRetNext : 0x%x "); +266240,545423616,0,0,PLAT_AP,PLA_HAL,SctPppCrcChanlCheck_full_1,P_ERROR,swLogPrintf("SCT PPP , channel full , can ' t calc PPP len , SCT cfgId : %d , doneIdx : %d , abnormal!!! "); +266240,545425408,0,0,PLAT_AP,PLA_HAL,SctPppEscapeCalcSize_s_1,P_SIG,swLogPrintf("SCT PPP , escape calc size done , pkgNum : %d "); +266240,545427712,0,0,PLAT_AP,PLA_HAL,SctPppEscape_full_1,P_ERROR,swLogPrintf("SCT PPP , channel full , can ' t escape , SCT cfgId : %d , doneIdx : %d , abnormal!!! "); +266240,545429760,0,0,PLAT_AP,PLA_HAL,SctPppDeEscape_full_1,P_ERROR,swLogPrintf("SCT PPP , channel full , can ' t deescape , SCT cfgId : %d , doneIdx : %d , abnormal!!! "); +266240,545431552,0,0,PLAT_AP,PLA_HAL,SctPppTest_e_1,P_ERROR,swLogPrintf("PPP TEST , calc escape size error : %d "); +266240,545433600,0,0,PLAT_AP,PLA_HAL,SctPppTest_e_2,P_ERROR,swLogPrintf("PPP TEST , PKG escape error : %d "); +266240,545435648,0,0,PLAT_AP,PLA_HAL,SctPppTest_e_3,P_ERROR,swLogPrintf("PPP TEST , PKG deescape error : %d "); +266240,545438208,0,0,PLAT_AP,PLA_HAL,SctPppTest_de_1,P_ERROR,swLogPrintf("PPP TEST , PKG deescape crcNok : %d , or len : %d ! = %d , not right "); +266240,545441791,0,0,PLAT_AP,PLA_HAL,SctPppTest_de_dl_1,P_ERROR,swLogDump("PPP TEST , DL PKG : "); +266240,545443839,0,0,PLAT_AP,PLA_HAL,SctPppTest_de_ul_1,P_ERROR,swLogDump("PPP TEST , UL PKG : "); +266240,545443840,0,0,PLAT_AP,PLA_HAL,SctPppTest_s_e_1,P_SIG,swLogPrintf("PPP TEST , escape & descape SUCC , pkgNum : %d "); +266240,545445888,0,0,PLAT_AP,PLA_HAL,SctUsbChanlIsr_timeout_1,P_WARNING,swLogPrintf("SCT USB , timeout warning ISR , current ongoing chain index : %d !!! "); +266240,545449983,0,0,PLAT_AP,PLA_HAL,SctUsbChanlErrIsr_dump_w_1,P_WARNING,swLogDump("SCT ERROR ISR , sctUsbChanlInfo DUMP : "); +266240,545452031,0,0,PLAT_AP,PLA_HAL,SctUsbChanlErrIsr_dump_w_2,P_WARNING,swLogDump("SCT ERROR ISR , sctUsbChainBasicInfoList DUMP : "); +266240,545452544,0,0,PLAT_AP,PLA_HAL,SctUsbChanlErrIsr_idx_w_1,P_WARNING,swLogPrintf("SCT ERROR ISR , USB channel , cfgIdx : %d , doneIdx : %d , procIdx : %d "); +266240,545454080,0,0,PLAT_AP,PLA_HAL,SctUsbChanlErrIsr_idx_w_2,P_WARNING,swLogPrintf("SCT ERROR ISR , USB channel , FIFO idx : %d "); +266240,545458175,0,0,PLAT_AP,PLA_HAL,SctUsbChanlErrIsr_dump_w_3,P_WARNING,swLogDump("SCT ERROR ISR , USB FIFO DESC DUMP : "); +266240,545460223,0,0,PLAT_AP,PLA_HAL,SctUsbChanlErrIsr_dump_desc_w_2,P_WARNING,swLogDump("SCT ERROR ISR , sctCh5UsbTx DESC DUMP : "); +266240,545460224,0,0,PLAT_AP,PLA_HAL,SctUsbFlushEp_w_1,P_WARNING,swLogPrintf("SCT USB , not support to flush EP : %d "); +266240,545462272,0,0,PLAT_AP,PLA_HAL,SctUsbFlushEp_w_2,P_WARNING,swLogPrintf("SCT USB , USB is reseting , don ' t need reflush EP : %d "); +266240,545464320,0,0,PLAT_AP,PLA_HAL,SctUsbProcPppCalcLenChain_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset , can ' t tigger SCT to USB EP : %d "); +266240,545466624,0,0,PLAT_AP,PLA_HAL,SctUsbProcPppToRamChain_s_sent_1,P_VALUE,swLogPrintf("SCT USB , PPP len : %d , sent to USB EP : %d "); +266240,545468416,0,0,PLAT_AP,PLA_HAL,SctUsbProcPppToRamChain_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset , can ' t tigger SCT to USB EP : %d "); +266240,545470976,0,0,PLAT_AP,PLA_HAL,SctUsbDiscardChain_w_1,P_WARNING,swLogPrintf("SCT USB , discard chain index : %d , for EP : %d , xferSize : %d "); +266240,545473280,0,0,PLAT_AP,PLA_HAL,SctUsbDiscardChain_w_2,P_WARNING,swLogPrintf("SCT USB , discard chain index : %d , for EP : %d , PPP step : %d , PPP Orig Size : %d "); +266240,545474816,0,0,PLAT_AP,PLA_HAL,SctUsbDiscardChain_w_3,P_WARNING,swLogPrintf("SCT USB , discard chain index : %d , for EP : %d "); +266240,545478655,0,0,PLAT_AP,PLA_HAL,SctUsbRollbackChain_usbNok_1,P_WARNING,swLogPrintf("SCT USB , USB is NOK , can ' t rollback chain "); +266240,545480703,0,0,PLAT_AP,PLA_HAL,SctUsbRollbackChain_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset , can ' t rollback data to USB EP "); +266240,545480704,0,0,PLAT_AP,PLA_HAL,SctUsbDiscardEpBackupInfo_s_1,P_SIG,swLogPrintf("SCT USB , discard EP : %d all backup Tx info "); +266240,545483776,0,0,PLAT_AP,PLA_HAL,SctUsbEpBackupChain_full_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , backup info full : %d / %d / %d / %d , abnormal , discard all old backup info "); +266240,545485056,0,0,PLAT_AP,PLA_HAL,SctUsbEpStartRetryTimer_s_1,P_SIG,swLogPrintf("SCT USB , EP : %d , start retry timer : %d ms "); +266240,545487360,0,0,PLAT_AP,PLA_HAL,SctUsbEpStartRetryTimer_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , retry timer start failed : %d , discard all backup info , and EP block : %d ms "); +266240,545489408,0,0,PLAT_AP,PLA_HAL,SctUsbEpIsTxFifoEmpty_s_1,P_SIG,swLogPrintf("SCT USB , EP : %d , DIEPTXFI : 0x%x , TxFIFOSize : %d "); +266240,545491456,0,0,PLAT_AP,PLA_HAL,SctUsbEpIsTxFifoEmpty_s_2,P_SIG,swLogPrintf("SCT USB , EP : %d , DTXFSTSI : 0x%x , TxFIFOAvail : %d "); +266240,545493504,0,0,PLAT_AP,PLA_HAL,SctUsbEpIsPreTxDone_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , TxFIFO empty : %d , but UTFC state : %d , seems still not right "); +266240,545495552,0,0,PLAT_AP,PLA_HAL,SctUsbEpIsPreTxDone_s_1,P_SIG,swLogPrintf("SCT USB , EP : %d , still busy , TxFIFO empty : %d , UTFC state : %d "); +266240,545498112,0,0,PLAT_AP,PLA_HAL,SctUsbProcChanlTimeOut_timeout_1,P_WARNING,swLogPrintf("SCT USB , cfgId : %d , doneIdx : %d , procIdx : %d , Tx EP : %d timeout times : %d "); +266240,545499136,0,0,PLAT_AP,PLA_HAL,SctUsbProcChanlTimeOut_mem_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d Tx timeout , but no mem left to backup info "); +266240,545501952,0,0,PLAT_AP,PLA_HAL,SctUsbProcChanlTimeOut_rty_e_1,P_ERROR,swLogPrintf("SCT USB , EP : %d , Tx timeout time : %d > Max : %d , discard backup and block %d ms... "); +266240,545503232,0,0,PLAT_AP,PLA_HAL,SctUsbProcChanlTimeOut_uta_w_1,P_WARNING,swLogPrintf("SCT USB channel , SCT not release UTA : 0x%x "); +266240,545505280,0,0,PLAT_AP,PLA_HAL,SctUsbProcChanlTimeOut_w_1,P_WARNING,swLogPrintf("SCT USB channel , can ' t waiting for reset done , chanlState : 0x%x "); +266240,545507584,0,0,PLAT_AP,PLA_HAL,SctUsbProcChanlTimeOut_ok_1,P_SIG,swLogPrintf("SCT USB , timeout , but EP : %d Tx OK , after try : %d times "); +266240,545509888,0,0,PLAT_AP,PLA_HAL,SctUsbProcSctError_err_1,P_ERROR,swLogPrintf("SCT USB , cfgId : %d , doneIdx : %d , procIdx : %d , SCT ERROR !!!! "); +266240,545512192,0,0,PLAT_AP,PLA_HAL,SctUsbTcpWSProcess_add_ws_1,P_DEBUG,swLogPrintf("SCT USB TCP , DL TCP SYN , ipType : %d , hostPort : %d , rmtPort : %d , ws : %d , try add into list "); +266240,545514240,0,0,PLAT_AP,PLA_HAL,SctUsbTcpWSProcess_disable_ws_1,P_VALUE,swLogPrintf("SCT USB TCP , ipType : %d , hostPort : %d , rmtPort : %d , dlScaled : %d , list full , disable WS option "); +266240,545516032,0,0,PLAT_AP,PLA_HAL,SctUsbTcpWSProcess_no_ws_1,P_DEBUG,swLogPrintf("SCT USB TCP , DL TCP SYN , ipType : %d , hostPort : %d , rmtPort : %d , no WS option , try RM from list "); +266240,545518592,0,0,PLAT_AP,PLA_HAL,SctUsbTcpWSProcess_win_1,P_INFO,swLogPrintf("SCT USB TCP WIN ADPT , hostPort : %d , free ul buffer %u , old win %u , new win %u , scaling value %u "); +266240,545521663,0,0,PLAT_AP,PLA_HAL,SctUsbChanlExitSleepCallback_1,P_INFO,swLogPrintf("SCT USB , wake up from sleep1 , do nothing , wait USB init / reset "); +266240,545521664,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_epck_1,P_WARNING,swLogPrintf("SCT USB , can ' t Tx to EP : %d , not support "); +266240,545523712,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_usbnok_1,P_WARNING,swLogPrintf("SCT USB , USB is NOK now , can ' t Tx to EP : %d "); +266240,545526272,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_full_1,P_WARNING,swLogPrintf("SCT USB , channel full , can ' t Tx anymore , SCT cfgId : %d , doneIdx : %d , procIdx : %d "); +266240,545528064,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_full_2,P_WARNING,swLogPrintf("SCT USB , TX info full , can ' t Tx anymore , TX info list cfgId : %d , procIdx : %d "); +266240,545530112,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_full_3,P_WARNING,swLogPrintf("SCT USB , first pkg size : %d > availSize : %d , can ' t Tx anymore , busy "); +266240,545532672,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_trig_1,P_INFO,swLogPrintf("SCT USB , EP : %d , SCT tigger : %d times , total transfer size : %d , availSize : %d "); +266240,545533952,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset , SCT can ' t send RAW data to USB EP : %d "); +266240,545536000,0,0,PLAT_AP,PLA_HAL,SctUsbTxRawDataStatic_sec_1,P_SIG,swLogPrintf("SCT USB , current transfer size : %d , but still more data , TX retry "); +266240,545538048,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_epck_1,P_WARNING,swLogPrintf("SCT USB , can ' t Tx PPP to EP : %d , not support "); +266240,545540096,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_nok_1,P_WARNING,swLogPrintf("SCT USB , USB is NOK now , can ' t Tx PPP to EP : %d "); +266240,545542656,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_full_1,P_WARNING,swLogPrintf("SCT USB , channel full , can ' t Tx PPP anymore , cfgId : %d , doneIdx : %d , procIdx : %d "); +266240,545544192,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_highwater_1,P_WARNING,swLogPrintf("SCT USB , PPP Tx pending / ongoing len : %d , highwater , return pending "); +266240,545546496,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_full_2,P_WARNING,swLogPrintf("SCT USB , PPP Tx info full , can ' t Tx anymore , TX info list cfgId : %d , procIdx : %d "); +266240,545548288,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset , SCT can ' t send PPP data to USB EP : %d "); +266240,545550336,0,0,PLAT_AP,PLA_HAL,SctUsbTxPppDataStatic_sec_1,P_SIG,swLogPrintf("SCT USB , current PPP escape size : %d , but still more data , TX retry "); +266240,545552384,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_usbnok_1,P_WARNING,swLogPrintf("SCT USB , USB is NOK now , can ' t Tx to EP : %d , discard all backup data "); +266240,545555712,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_full_1,P_WARNING,swLogPrintf("SCT USB , channel busy , sctCfgIdx : %d , sctProcIdx : %d , sctDoneIdx : %d , txInfoCfgIdx : %d , txInfoProcIdx : %d , can ' t Tx EP : %d backup data "); +266240,545557504,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_trig_1,P_SIG,swLogPrintf("SCT USB , EP : %d , Tx backup data , SCT tigger : %d times , cfgIdx : %d , doneIdx : %d , procIdx : %d "); +266240,545558528,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_reset_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset , can ' t Tx backup data to USB EP : %d "); +266240,545560576,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_all_s_1,P_SIG,swLogPrintf("SCT USB , EP : %d , all backup data Tx to channel "); +266240,545562880,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_pend_w_1,P_WARNING,swLogPrintf("SCT USB , can ' t Tx backup pending data to USB EP : %d , failed ret : %d "); +266240,545564672,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxBackupInfo_pend_s_1,P_SIG,swLogPrintf("SCT USB , EP : %d , all backup / pending data Tx to channel , free backup info "); +266240,545566720,0,0,PLAT_AP,PLA_HAL,SctUsbEpTxPendingData_no_mem_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , non mem left for backup info "); +266240,545569024,0,0,PLAT_AP,PLA_HAL,SctUsbTxData_epck_1,P_WARNING,swLogPrintf("SCT USB , Tx MAX EPID : %d , can ' t Tx to EP : %d , discard all Tx data "); +266240,545570816,0,0,PLAT_AP,PLA_HAL,SctUsbTxData_usbnok_1,P_WARNING,swLogPrintf("SCT USB , USB is NOK now , can ' t Tx to EP : %d , discard all Tx data "); +266240,545573376,0,0,PLAT_AP,PLA_HAL,SctUsbTxData_retry_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , retry / pending timer is runing , retryCount : %d , epState : %d , backup Tx data "); +266240,545574912,0,0,PLAT_AP,PLA_HAL,SctUsbTxData_unblocked_1,P_SIG,swLogPrintf("SCT USB , EP : %d , unblock now "); +266240,545577472,0,0,PLAT_AP,PLA_HAL,SctUsbTxData_blocked_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , is blocked untill sysTick : 0x%x , curTick : 0x%x , discard all Tx data "); +266240,545579008,0,0,PLAT_AP,PLA_HAL,SctUsbTxData_cts_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS is not allow , discard all Tx data "); +266240,545581568,0,0,PLAT_AP,PLA_HAL,SctUsbTxDatae_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , bPPP : %d , Tx data , failed ret : %d , discard "); +266240,545583616,0,0,PLAT_AP,PLA_HAL,SctUsbTxDatae_f_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , bPPP : %d , not all tx , ret : %d , need backup "); +266240,545585152,0,0,PLAT_AP,PLA_HAL,SctUsbEpProcRetryTimerExpiry_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , retry / pending time expiry , but no backup info "); +266240,545587200,0,0,PLAT_AP,PLA_HAL,SctUsbEpProcRetryTimerExpiry_w_2,P_WARNING,swLogPrintf("SCT USB , EP : %d , retry / pending time expiry , but time is NULL "); +266240,545589248,0,0,PLAT_AP,PLA_HAL,SctUsbEpProcRetryTimerExpiry_cts_w_2,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS pending time expiry , but CTS still not allow Tx , discard all pending Tx data "); +266240,545591296,0,0,PLAT_AP,PLA_HAL,SctUsbEpProcRetryTimerExpiry_done_1,P_SIG,swLogPrintf("SCT USB , EP : %d , pervious data all Tx , Tx backup data "); +266240,545594112,0,0,PLAT_AP,PLA_HAL,SctUsbEpProcRetryTimerExpiry_rty_e_1,P_ERROR,swLogPrintf("SCT USB , EP : %d , retry timeout , tryCount : %d > Max : %d , discard backup and block %d ms... "); +266240,545595648,0,0,PLAT_AP,PLA_HAL,SctUsbChanlInitConfig_new_1,P_SIG,swLogPrintf("SCT USB , num of Tx ep : %d , epbitmap : 0x%x "); +266240,545599487,0,0,PLAT_AP,PLA_HAL,SctUsbChanlInitConfig_w_1,P_WARNING,swLogPrintf("SCT USB , USB reset / deinit , can ' t config utfcSetZLForSct "); +266240,545599744,0,0,PLAT_AP,PLA_HAL,SctUsbChanlInitConfig_utfc_w_1,P_WARNING,swLogPrintf("SCT USB , Ep : %d , config utfcSetZLForSct , return NOK ( %d ) , USB / UTFC must reset / deinit "); +266240,545601792,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_raw_ok_1,P_SIG,swLogPrintf("SCT USB , EP : %d Tx OK , after try : %d times "); +266240,545603840,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_ppp_ok_1,P_SIG,swLogPrintf("SCT USB , PPP EP : %d Tx OK , after try : %d times "); +266240,545607679,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_accm_p_1,P_SIG,swLogPrintf("SCT USB , PPP escape ACCM config pending , check whether allow to cfg now "); +266240,545608448,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_accm_w_1,P_WARNING,swLogPrintf("SCT USB , PPP pppTxInfoBitmap : 0x%x , but SCT is free : %d / %d / %d "); +266240,545610496,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_accm_w_2,P_WARNING,swLogPrintf("SCT USB , SCT PPP Tx is still busy , pppTxInfoBitmap : 0x%x , %d / %d / %d , pending ACCM config "); +266240,545612288,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_full_1,P_WARNING,swLogPrintf("SCT USB , channel still full , can ' t Tx anymore , cfgId : %d , doneIdx : %d , procIdx : %d "); +266240,545614080,0,0,PLAT_AP,PLA_HAL,SctUsbProcDoneChainInfo_full_2,P_WARNING,swLogPrintf("SCT USB , Tx info list full , can ' t Tx anymore , txCfgId : %d , txProcIdx : %d "); +266240,545617919,0,0,PLAT_AP,PLA_HAL,SctUsbProcUsbEvent_reset_1,P_WARNING,swLogPrintf("SCT USB is RESET , discard all ongoing chain / txInfo "); +266240,545619967,0,0,PLAT_AP,PLA_HAL,SctUsbProcUsbEvent_init_1,P_SIG,swLogPrintf("SCT USB is INIT , OK for SCT "); +266240,545622015,0,0,PLAT_AP,PLA_HAL,SctUsbProcUsbEvent_full_s_1,P_SIG,swLogPrintf("SCT USB full speed version , MPS set to 64 "); +266240,545624063,0,0,PLAT_AP,PLA_HAL,SctUsbProcUsbEvent_high_s_1,P_SIG,swLogPrintf("SCT USB high speed version , MPS set to 512 "); +266240,545624576,0,0,PLAT_AP,PLA_HAL,SctUsbProcEpUnblock_w_1,P_WARNING,swLogPrintf("SCT USB , recv unblock sig , but invalid input / state , EP : %d , backupInfo : 0x%x , epState : %d "); +266240,545626112,0,0,PLAT_AP,PLA_HAL,SctUsbProcEpUnblock_s_1,P_SIG,swLogPrintf("SCT USB , EP : %d , recv unblock sig "); +266240,545628416,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_w_1,P_WARNING,swLogPrintf("SCT USB , invalid EP : %d , CTS bAllow Tx : %d "); +266240,545630208,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_allow_1,P_SIG,swLogPrintf("SCT USB , EP : %d , CTS Allow Tx "); +266240,545632256,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_allow_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS Allow Tx , but no backup / pending info "); +266240,545634560,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_allow_w_2,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS Allow Tx , but epState : %d , seems not right , anyway try Tx pending data "); +266240,545636352,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_allow_w_3,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS Allow Tx , but old data in USB FIFO not Tx , flush USB FIFO anyway "); +266240,545638400,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_not_allow_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS not Allow Tx , pending 10 sec "); +266240,545640448,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_no_mem_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS not allow , but non mem left for backup info "); +266240,545642752,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_tr_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , CTS not allow , epState : %d , retry / pending timer is running , need to stop it , then start CTS pending timer "); +266240,545644800,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_t_1,P_SIG,swLogPrintf("SCT USB , EP : %d , CTS not allow Tx , start pending timer : %d sec "); +266240,545646848,0,0,PLAT_AP,PLA_HAL,SctUsbCtsBeAllowSend_t_w_1,P_WARNING,swLogPrintf("SCT USB , EP : %d , pending timer start failed : %d , discard all backup data "); +266240,545648640,0,0,PLAT_AP,PLA_HAL,SctUsbStateEventInIsr_1,P_SIG,swLogPrintf("SCT USB state change to : %d , ( 0 -DEINT , 1 -INIT , 2 -RESET ) "); +266240,545652735,0,0,PLAT_AP,PLA_HAL,SctUsbStateEventInIsr_reset_1,P_WARNING,swLogPrintf("SCT USB is RESET / Deinit... "); +266240,545652736,0,0,PLAT_AP,PLA_HAL,SctUsbStateEventInIsr_uta_w_1,P_WARNING,swLogPrintf("SCT USB channel , SCT not release UTA : 0x%x "); +266240,545654784,0,0,PLAT_AP,PLA_HAL,SctUsbStateEventInIsr_w_1,P_WARNING,swLogPrintf("SCT USB channel , can ' t waiting for reset done , chanlState : 0x%x "); +266240,545656832,0,0,PLAT_AP,PLA_HAL,ACIpcAlone0Isr_00,P_VALUE,swLogPrintf("IPC0 Msg = 0x%x "); +266240,545658880,0,0,PLAT_AP,PLA_HAL,ACIpcAlone0Isr_1,P_ERROR,swLogPrintf("CP Dump , AP is in ImageType = %d , ( 0 ) AP Paging ( 1 ) AP FullImage "); +266240,545661440,0,0,PLAT_AP,PLA_HAL,ACIpcAlone1Isr_info_1,P_INFO,swLogPrintf("AP RECV IPC ID : 0x%x , msgLen : %d , bFast : %d "); +266240,545662976,0,0,PLAT_AP,PLA_HAL,A2CSendFastIpcMsg_sig_1,P_SIG,swLogPrintf("AP SEND fast IPC ID : 0x%x , to start / wakeup CP... "); +266240,545665280,0,0,PLAT_AP,PLA_HAL,A2CSendIpcMsg_info_1,P_INFO,swLogPrintf("AP SEND IPC ID : 0x%x , msgLen : %d "); +266240,545667072,0,0,PLAT_AP,PLA_HAL,A2CSendIpcMsg_sig_1,P_SIG,swLogPrintf("AP SEND IPC ID : 0x%x , to start / wakeup CP... "); +266240,545669120,0,0,PLAT_AP,PLA_HAL,A2CSendIpcMsg_info_3,P_INFO,swLogPrintf("AP SEND IPC Finish : gA2CNextWriteAddr_ap_rw = 0x%X "); +266240,545671168,0,0,PLAT_AP,PLA_HAL,A2CSendExceptionMsg_1,P_WARNING,swLogExcep("Warning , Last IPC0 Message not pop out , last msg = 0x%x "); +266240,545673216,0,0,PLAT_AP,PLA_HAL,A2CSendExceptionMsg_2,P_WARNING,swLogExcep("AP exception happens , wakeup cp to dead loop msgLen : %d "); +266240,545675520,0,0,PLAT_AP,PLA_HAL,halPhySetDebugCfgInfo_w_1,P_WARNING,swLogPrintf("HAL PHY , phyModId : %d , incorrect paramNum : %d "); +267264,547358720,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonWriteCP_0,P_VALUE,swLogExcep("Write CP Reset Flag = 0x%x "); +267264,547360768,0,0,PLAT_AP,EXCEP_PRINT,cpNVIC_SystemReset_0,P_VALUE,swLogPrintf("CP NVIC Reset , CFG = 0x%x "); +267264,547362816,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonWriteAP_0,P_VALUE,swLogExcep("Write AP Reset Flag = 0x%x "); +267264,547364864,0,0,PLAT_AP,EXCEP_PRINT,ResetStartPorReset_1,P_WARNING,swLogPrintf("Write Por Reset flag to flash = %e "); +267264,547367168,0,0,PLAT_AP,EXCEP_PRINT,ResetStartPorReset_3,P_WARNING,swLogPrintf("Write Por Reset flag failed , reason = %e readback = 0x%x "); +267264,547371007,0,0,PLAT_AP,EXCEP_PRINT,ResetStartPorReset_2,P_WARNING,swLogPrintf("Write Por Reset flag Failed , do por reset directly "); +267264,547371008,0,0,PLAT_AP,EXCEP_PRINT,ResetClrPorResetFlag_0,P_WARNING,swLogPrintf("Flash Por Reset Flag = 0x%x "); +267264,547375103,0,0,PLAT_AP,EXCEP_PRINT,ResetClrPorResetFlag_1,P_WARNING,swLogPrintf("Clear Por Reset Flag failed "); +267264,547375104,0,0,PLAT_AP,EXCEP_PRINT,ResetCheckCpNeedPorReset_1,P_WARNING,swLogPrintf("CP unexpected reset , reset reason = %e "); +267264,547377408,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_0,P_VALUE,swLogPrintf("Reset Value AP = 0x%x , CP = 0x%x "); +267264,547379200,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_21,P_WARNING,swLogPrintf("Reset : SW POR Reset , porReason = %e "); +267264,547383295,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_20,P_WARNING,swLogPrintf("Reset : Fota Reset "); +267264,547385343,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_1,P_WARNING,swLogPrintf("Reset : Aon Watchdog Reset "); +267264,547387391,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_2,P_WARNING,swLogPrintf("AP Reset : Software Active Reset "); +267264,547389439,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_3,P_WARNING,swLogPrintf("AP Reset Trigger in HardFault "); +267264,547391487,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_4,P_WARNING,swLogPrintf("AP Reset Trigger in Assert "); +267264,547393535,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_5,P_WARNING,swLogPrintf("AP Reset Trigger in NMI ( Watch Dog ) "); +267264,547395583,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_6,P_WARNING,swLogPrintf("AP Reset Trigger in Battery Low Int "); +267264,547397631,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_7,P_WARNING,swLogPrintf("AP Reset Trigger in Temperature High Int "); +267264,547397632,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_8,P_VALUE,swLogPrintf("AP Reset Magic = 0x%x "); +267264,547401727,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_9,P_WARNING,swLogPrintf("AP Reset : AP watch dog force reset "); +267264,547403775,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_10,P_WARNING,swLogPrintf("AP Reset : AP lockup reset "); +267264,547405823,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_11,P_VALUE,swLogPrintf("AP Reset : AP Reset Source None "); +267264,547407871,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_12,P_WARNING,swLogPrintf("CP Reset : Software Active Reset "); +267264,547409919,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_13,P_WARNING,swLogPrintf("CP Reset Trigger in HardFault "); +267264,547411967,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_14,P_WARNING,swLogPrintf("CP Reset Trigger in Assert "); +267264,547414015,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_15,P_WARNING,swLogPrintf("CP Reset Trigger in NMI ( Watch Dog ) "); +267264,547414016,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_16,P_VALUE,swLogPrintf("CP Reset Magic = 0x%x "); +267264,547418111,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_17,P_WARNING,swLogPrintf("Reset : CP watch dog force reset "); +267264,547420159,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_18,P_WARNING,swLogPrintf("Reset : CP lockup force reset "); +267264,547422207,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonInit_19,P_VALUE,swLogPrintf("Reset : CP Reset Source None "); +267264,547424255,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_0,P_WARNING,swLogPrintf("CP Reset : Software Active Reset "); +267264,547426303,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_1,P_WARNING,swLogPrintf("CP Reset Trigger in HardFault "); +267264,547428351,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_2,P_WARNING,swLogPrintf("CP Reset Trigger in Assert "); +267264,547430399,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_3,P_WARNING,swLogPrintf("CP Reset Trigger in NMI ( Watch Dog ) "); +267264,547432447,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_4,P_WARNING,swLogPrintf("Reset : CP watch dog force reset "); +267264,547434495,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_5,P_WARNING,swLogPrintf("Reset : CP lockup force reset "); +267264,547436543,0,0,PLAT_AP,EXCEP_PRINT,ResetReasonCpRstCheck_6,P_ERROR,swLogPrintf("Reset : CP Reset Source None "); +267264,547438591,0,0,PLAT_AP,EXCEP_PRINT,check_excep_func_call_1,P_ERROR,swLogExcep("try to parse exception call stack by address compare! "); +267264,547438592,0,0,PLAT_AP,EXCEP_PRINT,check_excep_func_call_2,P_ERROR,swLogExcep("maybe function address @ 0x%x "); +267264,547442687,0,0,PLAT_AP,EXCEP_PRINT,dump_ram_to_flash_0,P_ERROR,swLogExcep("4 M Flash , no flash dump area "); +267264,547444735,0,0,PLAT_AP,EXCEP_PRINT,dump_ram_to_flash_1,P_ERROR,swLogExcep("start dump ram to flash! "); +267264,547446783,0,0,PLAT_AP,EXCEP_PRINT,dump_ram_to_flash_2,P_ERROR,swLogExcep("Finsh dump ram to flash! "); +267264,547448831,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_0,P_ERROR,swLogExcep("RNDIS HALT FAILED "); +267264,547448832,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_1,P_ERROR,swLogExcep("CP Dump , AP help to dump , reason = %e "); +267264,547451136,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_2,P_ERROR,swLogExcep("CP hardFault triggered!!exceptionStore = 0x%x , 0x%x "); +267264,547452929,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_3,P_ERROR,swLogExcep("hardFault in : %s "); +267264,547454976,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_4,P_ERROR,swLogExcep("dump latest %d words stack start "); +267264,547457792,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_5,P_ERROR,swLogExcep("dump stack frame : 0x%x 0x%x 0x%x 0x%x "); +267264,547461119,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_6,P_ERROR,swLogExcep("CP assert triggered!! "); +267264,547461121,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_7,P_ERROR,swLogExcep("Assert INFO : %s "); +267264,547463169,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_8,P_ERROR,swLogExcep("assert in : %s "); +267264,547465216,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_9,P_ERROR,swLogExcep("dump latest %d words stack start "); +267264,547468032,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_10,P_ERROR,swLogExcep("dump stack frame : 0x%x 0x%x 0x%x 0x%x "); +267264,547469312,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_11,P_ERROR,swLogExcep("Current exception action : %d "); +267264,547473407,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_12,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547475455,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_13,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547477503,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_14,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547479551,0,0,PLAT_AP,EXCEP_PRINT,excepCPDump_15,P_ERROR,swLogExcep("cp exception occurs , the system will reset "); +267264,547481599,0,0,PLAT_AP,EXCEP_PRINT,excepCheckFaultType_1,P_ERROR,swLogExcep("hardfault : casued by vector fetch error! "); +267264,547483647,0,0,PLAT_AP,EXCEP_PRINT,excepCheckFaultType_2,P_ERROR,swLogExcep("hardfault : casued by debug event! "); +267264,547485695,0,0,PLAT_AP,EXCEP_PRINT,mmfault_1,P_ERROR,swLogExcep("mem fault : instruction access violatio "); +267264,547487743,0,0,PLAT_AP,EXCEP_PRINT,mmfault_2,P_ERROR,swLogExcep("mem fault : data access violation "); +267264,547489791,0,0,PLAT_AP,EXCEP_PRINT,mmfault_3,P_ERROR,swLogExcep("mem fault : unstacking error "); +267264,547491839,0,0,PLAT_AP,EXCEP_PRINT,mmfault_4,P_ERROR,swLogExcep("mem fault : stacking error "); +267264,547491840,0,0,PLAT_AP,EXCEP_PRINT,mmfault_5,P_ERROR,swLogExcep("memory manage fault address @ 0x%x "); +267264,547495935,0,0,PLAT_AP,EXCEP_PRINT,busfault_1,P_ERROR,swLogExcep("bus fault : instrunction acess error "); +267264,547497983,0,0,PLAT_AP,EXCEP_PRINT,busfault_2,P_ERROR,swLogExcep("bus fault : precise data acess error "); +267264,547500031,0,0,PLAT_AP,EXCEP_PRINT,busfault_3,P_ERROR,swLogExcep("bus fault : imprecise data acess error "); +267264,547502079,0,0,PLAT_AP,EXCEP_PRINT,busfault_4,P_ERROR,swLogExcep("bus fault : unstacking error "); +267264,547504127,0,0,PLAT_AP,EXCEP_PRINT,busfault_5,P_ERROR,swLogExcep("bus fault : stacking error "); +267264,547504128,0,0,PLAT_AP,EXCEP_PRINT,busfault_6,P_ERROR,swLogExcep("bus fault address @ 0x%x "); +267264,547508223,0,0,PLAT_AP,EXCEP_PRINT,usgaefault_1,P_ERROR,swLogExcep("usage fault : try to execute undefined instruction "); +267264,547510271,0,0,PLAT_AP,EXCEP_PRINT,usgaefault_2,P_ERROR,swLogExcep("usage fault : try to switch to wrong state ( ARM ) "); +267264,547512319,0,0,PLAT_AP,EXCEP_PRINT,usgaefault_3,P_ERROR,swLogExcep("usage fault : execute EXC_RETURN error "); +267264,547514367,0,0,PLAT_AP,EXCEP_PRINT,usgaefault_4,P_ERROR,swLogExcep("usage fault : try to execute coprocessor instruction "); +267264,547516415,0,0,PLAT_AP,EXCEP_PRINT,usgaefault_5,P_ERROR,swLogExcep("usage fault : unaligned access "); +267264,547518463,0,0,PLAT_AP,EXCEP_PRINT,usgaefault_6,P_ERROR,swLogExcep("usage fault : divide by zero "); +267264,547520511,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_1,P_ERROR,swLogExcep("dump regs start : "); +267264,547520512,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_2,P_ERROR,swLogExcep("dump reg : r0 : 0x%x ! "); +267264,547522560,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_3,P_ERROR,swLogExcep("dump reg : r1 : 0x%x ! "); +267264,547524608,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_4,P_ERROR,swLogExcep("dump reg : r2 : 0x%x ! "); +267264,547526656,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_5,P_ERROR,swLogExcep("dump reg : r3 : 0x%x ! "); +267264,547528704,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_6,P_ERROR,swLogExcep("dump reg : r4 : 0x%x ! "); +267264,547530752,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_7,P_ERROR,swLogExcep("dump reg : r5 : 0x%x ! "); +267264,547532800,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_8,P_ERROR,swLogExcep("dump reg : r6 : 0x%x ! "); +267264,547534848,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_9,P_ERROR,swLogExcep("dump reg : r7 : 0x%x ! "); +267264,547536896,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_10,P_ERROR,swLogExcep("dump reg : r8 : 0x%x ! "); +267264,547538944,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_11,P_ERROR,swLogExcep("dump reg : r9 : 0x%x ! "); +267264,547540992,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_12,P_ERROR,swLogExcep("dump reg : r10 : 0x%x ! "); +267264,547543040,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_13,P_ERROR,swLogExcep("dump reg : r11 : 0x%x ! "); +267264,547545088,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_14,P_ERROR,swLogExcep("dump reg : r12 : 0x%x ! "); +267264,547547136,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_15,P_ERROR,swLogExcep("dump reg : sp : 0x%x ! "); +267264,547549184,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_16,P_ERROR,swLogExcep("dump reg : msp : 0x%x ! "); +267264,547551232,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_17,P_ERROR,swLogExcep("dump reg : psp : 0x%x ! "); +267264,547553280,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_18,P_ERROR,swLogExcep("dump reg : lr : 0x%x ! "); +267264,547555328,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_19,P_ERROR,swLogExcep("dump reg : exception pc : 0x%x ! "); +267264,547557376,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_20,P_ERROR,swLogExcep("dump reg : psr : 0x%x ! "); +267264,547559424,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_21,P_ERROR,swLogExcep("dump reg : exc_return : 0x%x ! "); +267264,547561472,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_22,P_ERROR,swLogExcep("dump reg BASEPRI : 0x%x ! "); +267264,547563520,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_23,P_ERROR,swLogExcep("dump reg PRIMASK : 0x%x ! "); +267264,547565568,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_24,P_ERROR,swLogExcep("dump reg FAULTMASK : 0x%x ! "); +267264,547567616,0,0,PLAT_AP,EXCEP_PRINT,stack_frame_25,P_ERROR,swLogExcep("dump reg CONTROL : 0x%x ! "); +267264,547569920,0,0,PLAT_AP,EXCEP_PRINT,excepHardFaultHandler_1,P_WARNING,swLogExcep("AP : Min of max free block in histroy : [ %d , %d ) "); +267264,547572224,0,0,PLAT_AP,EXCEP_PRINT,excepHardFaultHandler_2,P_WARNING,swLogExcep("AP : Current max free block size : %d in [ %d , %d ) "); +267264,547573761,0,0,PLAT_AP,EXCEP_PRINT,exception_task0,P_ERROR,swLogExcep("hardfault task : %s "); +267264,547575808,0,0,PLAT_AP,EXCEP_PRINT,hardfault_1,P_ERROR,swLogExcep("Current fault action : %d "); +267264,547579903,0,0,PLAT_AP,EXCEP_PRINT,hardfault_rndis,P_ERROR,swLogExcep("RNDIS HALT FAILED "); +267264,547581951,0,0,PLAT_AP,EXCEP_PRINT,hardfault_enter0,P_ERROR,swLogExcep("AP hard fault triggered!! "); +267264,547581952,0,0,PLAT_AP,EXCEP_PRINT,stack_dump_1,P_ERROR,swLogExcep("dump latest %d words stack start "); +267264,547584768,0,0,PLAT_AP,EXCEP_PRINT,stack_dump_2,P_ERROR,swLogExcep("dump stack frame : 0x%x 0x%x 0x%x 0x%x "); +267264,547586049,0,0,PLAT_AP,EXCEP_PRINT,exception_task,P_ERROR,swLogExcep("hardfault task : %s "); +267264,547590143,0,0,PLAT_AP,EXCEP_PRINT,hardfault_yrcp_0,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547592191,0,0,PLAT_AP,EXCEP_PRINT,hardfault_yrcp_1,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547594239,0,0,PLAT_AP,EXCEP_PRINT,hardfault_yrcp_2,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547596287,0,0,PLAT_AP,EXCEP_PRINT,hardfault_2,P_ERROR,swLogExcep("hardfault occurs , the system will reset "); +267264,547596289,0,0,PLAT_AP,EXCEP_PRINT,unilogAssertInfo_1,P_ERROR,swLogExcep("ASSERT , FUNC : %s "); +267264,547598337,0,0,PLAT_AP,EXCEP_PRINT,unilogAssertInfo_2,P_ERROR,swLogExcep("ASSERT , FILE : %s "); +267264,547601152,0,0,PLAT_AP,EXCEP_PRINT,unilogAssertInfo_3,P_ERROR,swLogExcep("ASSERT line : %d , val is 0x%x , 0x%x , 0x%x "); +267264,547602688,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_001,P_WARNING,swLogExcep("AP : Min of max free block in histroy : [ %d , %d ) "); +267264,547604992,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_002,P_WARNING,swLogExcep("AP : Current max free block size : %d in [ %d , %d ) "); +267264,547606529,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_00,P_ERROR,swLogExcep("Assert INFO : %s "); +267264,547608577,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_01,P_ERROR,swLogExcep("assert in task : %s "); +267264,547610625,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_02,P_ERROR,swLogExcep("assert in : %s "); +267264,547612673,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_03,P_ERROR,swLogExcep("assert in : %s "); +267264,547614720,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_7,P_ERROR,swLogExcep("Current exception action : %d "); +267264,547617280,0,0,PLAT_AP,EXCEP_PRINT,ecAssert_enter_0,P_ERROR,swLogExcep("AP assert triggered!!SP = 0x%x , PSP = 0x%x , MSP = 0x%x "); +267264,547620863,0,0,PLAT_AP,EXCEP_PRINT,assert_rndis,P_ERROR,swLogExcep("RNDIS HALT FAILED "); +267264,547620865,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_0,P_ERROR,swLogExcep("Assert INFO : %s "); +267264,547622912,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_1,P_ERROR,swLogExcep("dump latest %d words stack start "); +267264,547625728,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_2,P_ERROR,swLogExcep("dump stack frame : 0x%x 0x%x 0x%x 0x%x "); +267264,547627009,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_3,P_ERROR,swLogExcep("assert in task : %s "); +267264,547629057,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_4,P_ERROR,swLogExcep("assert in : %s "); +267264,547631105,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_5,P_ERROR,swLogExcep("assert in : %s "); +267264,547635199,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_8,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547637247,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_9,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547639295,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_10,P_ERROR,swLogExcep("...yrcp_init..fail "); +267264,547641343,0,0,PLAT_AP,EXCEP_PRINT,excepEcAssert_11,P_ERROR,swLogExcep("assert occurs , the system will reset "); +267264,547641344,0,0,PLAT_AP,EXCEP_PRINT,LFS_DaemonTaskEntry_e_1,P_ERROR,swLogPrintf("LFS deamon , can ' t proc reqType : %d "); +267264,547643648,0,0,PLAT_AP,EXCEP_PRINT,LFS_Init_0,P_ERROR,swLogPrintf("FS region reformat threshold : %d , Current FS assert count : %d "); +267264,547647487,0,0,PLAT_AP,EXCEP_PRINT,LFS_Init_1,P_ERROR,swLogPrintf("FS region reformat failed!!! "); +268288,549456897,0,0,PLAT_AP,OSA,OsaCheckDebugFalse_e_1,P_ERROR,swLogPrintf("Debug Error , func : %s , line : %d , ( 0x%x , 0x%x , 0x%x ) "); +268288,549458688,0,0,PLAT_AP,OSA,OsaCfgNvmRemoveParam_e_1,P_ERROR,swLogPrintf("OSA CFG NVM , filesize : %d , remove size : %d + %d , can ' t remove paramId : %d , discard whole cfg file "); +268288,549460480,0,0,PLAT_AP,OSA,OsaCfgNvmGetParam_e_1,P_ERROR,swLogPrintf("OSA CFG NVN , can ' t get paramId : %d , file overflow , pCfgParse : 0x%x , pCfgEnd : 0x%x , reset whole config file "); +268288,549462784,0,0,PLAT_AP,OSA,OsaCfgNvmGetNextParam_e_1,P_ERROR,swLogPrintf("OSA CFG NVM , parse file erro , paramId : %d , type : %d , endlen : %d , but filesize only : %d , discard whole cfg file "); +268288,549465088,0,0,PLAT_AP,OSA,OsaCfgNvmAddParam_input_w_1,P_WARNING,swLogPrintf("OSA CFG NVN , can ' t add param , invalid input : paramId : %d , cfgType : %d , len : %d , paramAddr : 0x%x , NVMBody : 0x%x "); +268288,549466624,0,0,PLAT_AP,OSA,OsaCfgNvmAddParam_input_w_2,P_WARNING,swLogPrintf("OSA CFG NVN , cfgType : %d , but size : %d > 2 , can ' t add param : %d "); +268288,549468672,0,0,PLAT_AP,OSA,OsaCfgNvmAddParam_size_w_1,P_ERROR,swLogPrintf("OSA CFG NVN , cfg file size : %d , new added size : %d , already > 4 KB , can ' t add paramId : %d "); +268288,549471232,0,0,PLAT_AP,OSA,OsaCfgNvmUpdateParam_input_w_1,P_WARNING,swLogPrintf("OSA CFG NVN , can ' t update param , invalid input : paramId : %d , cfgType : %d , len : %d , paramAddr : 0x%x , NVMBody : 0x%x "); +268288,549472768,0,0,PLAT_AP,OSA,OsaCfgNvmUpdateParam_input_w_2,P_WARNING,swLogPrintf("OSA CFG NVN , cfgType : %d , but size : %d > 2 , can ' t update param : %d "); +268288,549474304,0,0,PLAT_AP,OSA,OsaCfgNvmUpdateParam_null_1,P_VALUE,swLogPrintf("OSA CFG NVN , paramId : %d , not found in NVM , can ' t update , should add new into NVM "); +268288,549477120,0,0,PLAT_AP,OSA,OsaCfgNvmUpdateParam_replace_e_1,P_ERROR,swLogPrintf("OSA CFG NVM , paramId : %d , type : %d , paramLen not right , new : %d , old : %d "); +268288,549478912,0,0,PLAT_AP,OSA,OsaCfgNvmUpdateParam_replace_e_2,P_ERROR,swLogPrintf("OSA CFG NVM , paramId : %d , type : %d not the same as old : %d "); +268288,549481216,0,0,PLAT_AP,OSA,OsaMemPoolIdAlloc_w_1,P_WARNING,swLogPrintf("OSA POOL MEM , can ' t alloc size : %d > etySize : %d , from poolId : %d , request by : %d "); +268288,549483264,0,0,PLAT_AP,OSA,OsaMemPoolIdAlloc_null_1,P_WARNING,swLogPrintf("OSA POOL MEM , PoolId : %d , allocated Num : %d , no left , can ' t alloc size : %d , request by : %d "); +268288,549484800,0,0,PLAT_AP,OSA,OsaMemPoolAlloc_warning_1,P_WARNING,swLogPrintf("OSA POOL MEM , no pool is suitable for wantedSize : %d , callerId : %d "); +268288,549487105,0,0,PLAT_AP,OSA,OsaNvmDaemonTaskRead_e_2,P_ERROR,swLogPrintf("OSA NVM , file : %s , can ' t read header , readLen : %d , wanted : %d , remove it "); +268288,549489153,0,0,PLAT_AP,OSA,OsaNvmDaemonTaskRead_e_3,P_ERROR,swLogPrintf("OSA NVM , file : %s , invalid file size : %d > %d , not support , remove it "); +268288,549491201,0,0,PLAT_AP,OSA,OsaNvmDaemonTaskRead_e_4,P_ERROR,swLogPrintf("OSA NVM , file : %s , can ' t read body , readLen : %d , wantedSize : %d , remove it "); +268288,549493249,0,0,PLAT_AP,OSA,OsaNvmDaemonTaskWrite_e_1,P_ERROR,swLogPrintf("OSA NVM , file : %s , can ' t write file , wrSize : %d > MAX : %d "); +268288,549495296,0,0,PLAT_AP,OSA,OsaNvmRead_w_1,P_WARNING,swLogPrintf("OSA NVM , read NVM , invalid input , fileName : 0x%x , bodyInfo : 0x%x , bodyInfo.pbuf : 0x%x "); +268288,549497345,0,0,PLAT_AP,OSA,OsaNvmRead_w_2,P_WARNING,swLogPrintf("OSA NVM , file : %s , nameLen : %d > %d , or 0 , invalid , can ' t read file "); +268288,549499137,0,0,PLAT_AP,OSA,OsaNvmRead_lfs_w_1,P_WARNING,swLogPrintf("OSA NVM , can ' t read NVM file : %s , ret : %d "); +268288,549501187,0,0,PLAT_AP,OSA,OsaNvmRead_filename_w_1,P_WARNING,swLogPrintf("OSA NVM , read file : %s , but the filename header is : %s , not valid file , remove file "); +268288,549503745,0,0,PLAT_AP,OSA,OsaNvmRead_cks_w_1,P_WARNING,swLogPrintf("OSA NVM , read file : %s , len : %d , checksum not right , calc : 0x%x , want : 0x%x , remove file "); +268288,549505536,0,0,PLAT_AP,OSA,OsaNvmWrite_input_w_1,P_WARNING,swLogPrintf("OSA NVM , write file , invalid input , fileNameAddr : 0x%x , pData : 0x%x , size : %d , should < 4096 "); +268288,549507585,0,0,PLAT_AP,OSA,OsaNvmWrite_filename_w_1,P_WARNING,swLogPrintf("OSA NVM , file : %s , nameLen : %d > %d , or 0 , invalid , can ' t write file "); +268288,549509377,0,0,PLAT_AP,OSA,OsaNvmWrite_lfs_w_1,P_WARNING,swLogPrintf("OSA NVM , can ' t write NVM file : %s , ret : %d "); +268288,549511168,0,0,PLAT_AP,OSA,OsaHibTimerExpiryCallback_1,P_SIG,swLogPrintf("HIB Timer Expired , ID : %e "); +268288,549513728,0,0,PLAT_AP,OSA,osa_timeSync1,P_INFO,swLogPrintf("new---NITZ , year-mon-day : 0x%x , hour-min-sec-tz : 0x%x , sec from 1970 is 0x%x "); +268288,549515264,0,0,PLAT_AP,OSA,osa_timeSync3,P_INFO,swLogPrintf("SNTP secs since 1970 : 0x%x "); +268288,549517312,0,0,PLAT_AP,OSA,osa_timeSync4,P_INFO,swLogPrintf("curr---ctTimerCurr : 0x%x "); +268288,549519872,0,0,PLAT_AP,OSA,osa_timeSync5,P_INFO,swLogPrintf("update time info to flash utc : 0x%x , ct : 0x%x , zone : 0x%x "); +268288,549522176,0,0,PLAT_AP,OSA,osa_timeSync6,P_INFO,swLogPrintf("update time info to flash again utc : 0x%x , ct : 0x%x , zone : 0x%x , ret = %d "); +268288,549523456,0,0,PLAT_AP,OSA,osa_timeSync7,P_INFO,swLogPrintf("utcSeconds from flash : 0x%x "); +268288,549525504,0,0,PLAT_AP,OSA,osa_timeSync8,P_INFO,swLogPrintf("old---CTtimer : 0x%x "); +268288,549527808,0,0,PLAT_AP,OSA,osa_timeSync9,P_INFO,swLogPrintf("utcRang : 0x%x , ctTimerRang : 0x%x "); +268288,549530112,0,0,PLAT_AP,OSA,osa_timeSync10,P_INFO,swLogPrintf("update time info to flash utc : 0x%x , ct : 0x%x , zone : 0x%x "); +268288,549532416,0,0,PLAT_AP,OSA,osa_timeSync11,P_INFO,swLogPrintf("update time info to flash again utc : 0x%x , ct : 0x%x , zone : 0x%x , ret = %d "); +268288,549534208,0,0,PLAT_AP,OSA,osa_timeSync12,P_INFO,swLogPrintf("update time info to flash utc : 0x%x , ct : 0x%x , zone : 0x%x "); +268288,549536512,0,0,PLAT_AP,OSA,osa_timeSync13,P_INFO,swLogPrintf("update time info to flash again utc : 0x%x , ct : 0x%x , zone : 0x%x , ret = %d "); +268288,549539839,0,0,PLAT_AP,OSA,osa_time9,P_INFO,swLogPrintf("NO time sync triggered , use the default time 2000.100000 .1 "); +268288,549540096,0,0,PLAT_AP,OSA,osa_time10_0,P_INFO,swLogPrintf("read UTC flash maybe err , ctTimerCurr 0x%x , CTtimer 0x%x "); +268288,549542144,0,0,PLAT_AP,OSA,osa_time10,P_INFO,swLogPrintf("read sec flash utc is 0x%x , ct period is 0x%x "); +268288,549545983,0,0,PLAT_AP,OSA,osa_time110,P_INFO,swLogPrintf("use default time seting , senice 2000 "); +268288,549546240,0,0,PLAT_AP,OSA,osa_time12_0,P_INFO,swLogPrintf("read UTC flash maybe err , ctTimerCurr 0x%x , CTtimer 0x%x "); +268288,549548288,0,0,PLAT_AP,OSA,osa_time12,P_INFO,swLogPrintf("read UTC flash utc is 0x%x , ct period is 0x%x "); +268288,549551105,0,0,PLAT_AP,OSA,PsOsCreateTask_1,P_ERROR,swLogPrintf("PS Task : %s , id : %d , create Failed - %u , %u , %u "); +268288,549554175,0,0,PLAT_AP,OSA,CmsTaskAndQCeate_1,P_SIG,swLogPrintf("Create CMS task... "); +268288,549556223,0,0,PLAT_AP,OSA,CmsTaskAndQCeate_w_1,P_WARNING,swLogPrintf("CMS Task already created , not need to create again "); +268288,549556483,0,0,PLAT_AP,OSA,CmsTaskAndQCeate_name_e_1,P_ERROR,swLogPrintf("CMS Task already created , but task name not right : %s , must be : %s "); +268288,549558528,0,0,PLAT_AP,OSA,CmsTaskAndQCeate_pri_e_1,P_ERROR,swLogPrintf("CMS Task already created , but task priority not right : %d , must be : %d "); +268288,549560832,0,0,PLAT_AP,OSA,CmsTaskAndQCeate_task_e_1,P_ERROR,swLogPrintf("CMS Task Create Failed - %u , %u , %u "); +268288,549562880,0,0,PLAT_AP,OSA,CmsTaskAndQCeate_queue_e_1,P_ERROR,swLogPrintf("CMS Task queue Create Failed - %u , %u , %u "); +268288,549564416,0,0,PLAT_AP,OSA,PsInitialiseTasks_1,P_SIG,swLogPrintf("Create PS tasks... , PS tasks created before : %d "); +268288,549566720,0,0,PLAT_AP,OSA,EC_HEAP,P_INFO,swLogPrintf("EC heap size is %d , start addr is 0x%x! "); +268288,549569280,0,0,PLAT_AP,OSA,OSA_ULFC_TIMER,P_SIG,swLogPrintf("UlfcMem ( %d ) : task ( %d / 0x%x ) unset ( %d ) timer event! "); +268288,549571328,0,0,PLAT_AP,OSA,OSA_ULFC_ALLOC,P_SIG,swLogPrintf("UlfcMem ( %d ) : alerting water! usedSize ( %d ) , alertThres ( %d / %d%% ) "); +268288,549573896,0,0,PLAT_AP,OSA,OSA_ULFC_SET_CONF,P_SIG,swLogPrintf("UlfcMem ( %d ) : set task ( %d / 0x%x ) to %s mode ( %d ) , latest ref ( %d ) ! "); +268288,549575424,0,0,PLAT_AP,OSA,OSA_ULFC_UNSET_CONF_1,P_SIG,swLogPrintf("UlfcMem ( %d ) : unset task ( %d / 0x%x ) , latest ref ( %d ) ! "); +268288,549576704,0,0,PLAT_AP,OSA,OSA_ULFC_UNSET_CONF_2,P_SIG,swLogPrintf("UlfcMem ( %d ) : create unset timer! "); +268288,549579778,0,0,PLAT_AP,OSA,OSA_ULFC_EVT_NOTIF,P_SIG,swLogPrintf("UlfcMem ( %d ) : %s water ( %d ) , usedSize ( %d ) , @bmTaskId ( 0x%x ) ! "); +269312,551553024,0,0,PLAT_AP,PMU,ec_main_2,P_VALUE,swLogPrintf("Current BT1MsCnt = %d "); +269312,551555328,0,0,PLAT_AP,PMU,fpgaCaliStart,P_SIG,swLogPrintf("fcStart = %d , scStart = %d "); +269312,551557376,0,0,PLAT_AP,PMU,fpgaCaliStop,P_SIG,swLogPrintf("fcStop = %d , scStop = %d "); +269312,551559168,0,0,PLAT_AP,PMU,fpgaCaliRslt,P_SIG,swLogPrintf("calibration result is %d "); +269312,551561472,0,0,PLAT_AP,PMU,BcLdRslt,P_SIG,swLogPrintf("wakeup : bcValueHigh = 0x%X , bcValueLow = 0x%X "); +269312,551565311,0,0,PLAT_AP,PMU,waitIdle2,P_SIG,swLogPrintf("wait for 10 seconds "); +269312,551567359,0,0,PLAT_AP,PMU,RtcIsr,P_SIG,swLogPrintf("Rtc Isr triggered "); +269312,551568640,0,0,PLAT_AP,PMU,fpgaLatch,P_SIG,swLogPrintf("latch fail fcCnt0 = %d , fcCnt = %d , fcCnt1 = %d , scCnt0 = %d , scCnt = %d , scCnt1 = %d "); +269312,551570688,0,0,PLAT_AP,PMU,fpgaLatch_1,P_SIG,swLogPrintf("latch fail fcCnt0 = %d , fcCnt = %d , fcCnt1 = %d , scCnt0 = %d , scCnt = %d , scCnt1 = %d "); +269312,551571456,0,0,PLAT_AP,PMU,DivTest00,P_SIG,swLogPrintf("Original ratio is %d "); +269312,551573504,0,0,PLAT_AP,PMU,DivTest01,P_SIG,swLogPrintf("new ratio is %d "); +269312,551577599,0,0,PLAT_AP,PMU,waitIdle0,P_SIG,swLogPrintf("wait for 8 seconds "); +269312,551577600,0,0,PLAT_AP,PMU,ratioAfterSleep0,P_SIG,swLogPrintf("ratio after sleep is %d "); +269312,551579648,0,0,PLAT_AP,PMU,DivTest02,P_SIG,swLogPrintf("set divide ratio to original %d "); +269312,551583743,0,0,PLAT_AP,PMU,DivTest03,P_SIG,swLogPrintf("* * * * * * * * * * * * * * * * * * * * * * * * * * * * * Sw divide ratio config done * * * * * * * * * * * * * * * * * * * * * * * * * * "); +269312,551583744,0,0,PLAT_AP,PMU,DivTest10,P_SIG,swLogPrintf("Original ratio is %d "); +269312,551585792,0,0,PLAT_AP,PMU,DivTest11,P_SIG,swLogPrintf("new ratio is %d "); +269312,551589887,0,0,PLAT_AP,PMU,waitIdle1,P_SIG,swLogPrintf("wait for 16 seconds "); +269312,551589888,0,0,PLAT_AP,PMU,ratioAfterSleep1,P_SIG,swLogPrintf("ratio after sleep is %d "); +269312,551593983,0,0,PLAT_AP,PMU,DivTest13,P_SIG,swLogPrintf("* * * * * * * * * * * * * * * * * * * * * * * * * * * * * latch tirgger divide ratio config done * * * * * * * * * * * * * * * * * * * * * * * * * * "); +269312,551594496,0,0,PLAT_AP,PMU,PhyFpgaWakeUpCfg_0,P_SIG,swLogPrintf("currTime : bcValueHigh = 0x%X , bcValueLow = 0x%X and sc is %d "); +269312,551596544,0,0,PLAT_AP,PMU,PhyFpgaWakeUpCfg_1,P_SIG,swLogPrintf("wakeup : bcValueHigh = 0x%X , bcValueLow = 0x%X and sc is %d "); +269312,551600127,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_0,P_SIG,swLogPrintf("Boot From Power On \r \n "); +269312,551600128,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_11,P_SIG,swLogPrintf("curr SC = %d "); +269312,551602432,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_12,P_SIG,swLogPrintf("wakeup : bcValueHigh = 0x%X , bcValueLow = 0x%X "); +269312,551606271,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_2,P_SIG,swLogPrintf("wakeup form sleep1 "); +269312,551608319,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_3,P_SIG,swLogPrintf("undefined \r \n "); +269312,551610367,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_4,P_SIG,swLogPrintf("boot form sleep1 \r \n "); +269312,551612415,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_5,P_SIG,swLogPrintf("boot form sleep2 \r \n "); +269312,551614463,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_51,P_SIG,swLogPrintf("wakeup form sleep2 "); +269312,551616511,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_6,P_SIG,swLogPrintf("boot form hibernate \r \n "); +269312,551616512,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_61,P_SIG,swLogPrintf("hibernate curr SC = %d "); +269312,551618816,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_62,P_SIG,swLogPrintf("hibernate wakeup : bcValueHigh = 0x%X , bcValueLow = 0x%X "); +269312,551622655,0,0,PLAT_AP,PMU,ApFpgaPmuTestMain_7,P_SIG,swLogPrintf("boot form ao \r \n "); +269312,551624703,0,0,PLAT_AP,PMU,apmuStartPowerOff_0,P_SIG,swLogPrintf("Power Off Failed , try again "); +269312,551624960,0,0,PLAT_AP,PMU,apmuGetAPWakeupSrc,P_VALUE,swLogPrintf("APmu : padWakeup = 0x%x , rtcWakeup = 0x%x "); +269312,551628799,0,0,PLAT_AP,PMU,apmuSetWakeupPadCfg_1,P_WARNING,swLogPrintf("apmuSetWakeupPadCfg : Pad Num should < = WAKEUP_PAD_5 "); +269312,551630847,0,0,PLAT_AP,PMU,apmuCPSleepEndIntHandler_2,P_VALUE,swLogPrintf("APMU CpSleepEnd : CP Vote for sleep1 "); +269312,551632895,0,0,PLAT_AP,PMU,apmuCPSleepEndIntHandler_3,P_VALUE,swLogPrintf("APMU CpSleepEnd : CP Vote for sleep2 "); +269312,551634943,0,0,PLAT_AP,PMU,apmuCPSleepEndIntHandler_4,P_VALUE,swLogPrintf("APMU CpSleepEnd : CP Vote for hibernate "); +269312,551636991,0,0,PLAT_AP,PMU,apmuCPSleepEndIntHandler_5,P_VALUE,swLogPrintf("APMU CpSleepEnd : CP Vote for sleep0 "); +269312,551639039,0,0,PLAT_AP,PMU,apmuCPSleepEndIntHandler_1,P_WARNING,swLogPrintf("APMU CpSleepEnd : Unknow sleep type! "); +269312,551641087,0,0,PLAT_AP,PMU,apmuCPWakeupEndIntHandler_1,P_VALUE,swLogPrintf("APMU CpWakeupEnd : CP Wakeup! "); +269312,551643135,0,0,PLAT_AP,PMU,apmuCPAssistReqIntHandler_1,P_VALUE,swLogPrintf("AP : Int Enter->CP Assist Req "); +269312,551645183,0,0,PLAT_AP,PMU,apmuCPRstReqIntHandler_1,P_VALUE,swLogPrintf("AP : Int Enter->CP Reset Req "); +269312,551645440,0,0,PLAT_AP,PMU,apmuNeedFlashErase_0,P_VALUE,swLogPrintf("Need Flash Erase , FlashClrFlag = 0x%x , FlashWrFlag = 0x%x "); +269312,551648000,0,0,PLAT_AP,PMU,apmuCheckLdoBeforeSlp_1,P_VALUE,swLogPrintf("Ldo state , aonio = %d , sim = %d , aio = %d , usbMode = %d "); +269312,551651327,0,0,PLAT_AP,PMU,apmuStartCPTimerExp_0,P_VALUE,swLogPrintf("apmuStartCPTimer Expired "); +269312,551653375,0,0,PLAT_AP,PMU,apmuStartCPTimerExp_1,P_VALUE,swLogPrintf("Still not time to start cp , start modem timer again "); +269312,551655423,0,0,PLAT_AP,PMU,apmuSetCPFastBoot_1,P_WARNING,swLogPrintf("Warning : CP Code in invalid , skip cp fast boot config "); +269312,551655424,0,0,PLAT_AP,PMU,apmuTrgCPPowerOn_0,P_SIG,swLogPrintf("Error : CP is already power on. Last WakeupSrc = 0x%x "); +269312,551659519,0,0,PLAT_AP,PMU,apmuCPSwPowerOn_0,P_VALUE,swLogPrintf("CP is powered off. Start CP Power on flow "); +269312,551659776,0,0,PLAT_AP,PMU,apmuCPSwPowerOn_00,P_VALUE,swLogPrintf("ap share : 0x%x , len : 0x%x "); +269312,551663615,0,0,PLAT_AP,PMU,apmuCPSwPowerOn_1,P_SIG,swLogPrintf("Cp Auto Power On After setting assist boot "); +269312,551665663,0,0,PLAT_AP,PMU,apmuSetCPFastBoot_00,P_WARNING,swLogPrintf("Warning : CP Code in invalid , No code in CP Flash "); +269312,551667711,0,0,PLAT_AP,PMU,funcTestAPSleep1_1,P_SIG,swLogPrintf("funcTestAPSleep1 Test "); +269312,551669759,0,0,PLAT_AP,PMU,funcTestAPSleep1_2,P_SIG,swLogPrintf("Ap go sleep1 "); +269312,551671807,0,0,PLAT_AP,PMU,funcTestAPSleep1_3,P_SIG,swLogPrintf("funcTestAPSleep1 sleep failed "); +269312,551673855,0,0,PLAT_AP,PMU,funcTestAPSleep1_4,P_SIG,swLogPrintf("funcTestAPSleep1 sleep success "); +269312,551675903,0,0,PLAT_AP,PMU,apmuSlpTestExtWakeupSleep2_1,P_SIG,swLogPrintf("SleepDeep Test "); +269312,551676160,0,0,PLAT_AP,PMU,apmuSlpTestExtWakeupSleep2_2,P_SIG,swLogPrintf("DeepSleep Test : bootFlg = %d , slpMode = %d "); +269312,551679999,0,0,PLAT_AP,PMU,apmuSlpTestExtWakeupSleep2_3,P_SIG,swLogPrintf("Deep Sleep failed "); +269312,551682047,0,0,PLAT_AP,PMU,apmuGetBT10MsCnt_1,P_SIG,swLogPrintf("hibCnt Wrap in small image , should go fullimage to write timeoffset "); +269312,551684095,0,0,PLAT_AP,PMU,apmuGetBT10MsCnt_2,P_SIG,swLogPrintf("hibCnt Wrap in full image , should write flash "); +269312,551686143,0,0,PLAT_AP,PMU,ApmuAonRegWR_0,P_INFO,swLogPrintf("ApmuAonRegWR! "); +269312,551688191,0,0,PLAT_AP,PMU,ApmuAonRegRecovery_0,P_SIG,swLogPrintf("ApmuAonRegRecovery! "); +269312,551690239,0,0,PLAT_AP,PMU,ApmuScDivDisable,P_SIG,swLogPrintf("set sc div ratio to 0 by sw! "); +269312,551691264,0,0,PLAT_AP,PMU,ApmuGetSleepLength_0,P_VALUE,swLogPrintf("startSc is %d , wakeupSc is %d , diviRatio is %d , load 0x%X|%d "); +269312,551692544,0,0,PLAT_AP,PMU,ApmuGetSleepLength_1,P_VALUE,swLogPrintf("sleepLength is %d , totalSleepLength is %d ( unit is ms ) "); +269312,551694336,0,0,PLAT_AP,PMU,ApmuWaitBcLdComplete,P_VALUE,swLogPrintf("BcLd triggered and curSc is %d "); +269312,551696384,0,0,PLAT_AP,PMU,ApmuFeedWtdg_1,P_VALUE,swLogPrintf("Feed Aon Watchdog , current sc = %d "); +269312,551699456,0,0,PLAT_AP,PMU,ApmuF2sRatioAtcUpdt_0,P_VALUE,swLogPrintf("old ratio is 0x%X , new one is 0x%X , sleepLength is %d , atcAdj is %d , ApSleepLength = %d ( / 32 ) "); +269312,551700992,0,0,PLAT_AP,PMU,ApmuBfLtchPreProc_0,P_VALUE,swLogPrintf("sleepLength is %d , f2sRatio is 0x%X , scCnt is %d "); +269312,551703808,0,0,PLAT_AP,PMU,ApmuBfLtchPreProc_1,P_VALUE,swLogPrintf("scDiv is %d , scMask is 0x%X , deltaBc 0x%X|%d , btSysTime 0x%X|%d "); +269312,551704832,0,0,PLAT_AP,PMU,ApmuUnschdWakeupProc_1,P_WARNING,swLogPrintf("illegal! scOfstNew2Start is %d , maxSleepLen is %d "); +269312,551706624,0,0,PLAT_AP,PMU,ApmuUnschdWakeupProc_2,P_WARNING,swLogPrintf("bcLd very near or past! scOfstNew2Bcld is %d "); +269312,551709440,0,0,PLAT_AP,PMU,ApmuUnschdWakeupProc_3,P_VALUE,swLogPrintf("currSc is %d , scDiff = %d , bcLd 0x%X|%d "); +269312,551710976,0,0,PLAT_AP,PMU,ApmuUnschdWakeupProc_4,P_WARNING,swLogPrintf("illegal! RTC wakeup missed! currSc is %d , newWakeupSc is %d "); +269312,551713024,0,0,PLAT_AP,PMU,apmuScSyncDoneProc_1,P_VALUE,swLogPrintf("f2s ratio fast clock result start = %d , stop = %d "); +269312,551715584,0,0,PLAT_AP,PMU,apmuScSyncDoneProc,P_SIG,swLogPrintf("SlowClock Calibration Finished! , f2sRatio = 0x%X , fcDiff = %d , scDiff = %d , 32 K freq = %d "); +269312,551717632,0,0,PLAT_AP,PMU,SC_SYNC_REQ_SLEEP_PREPROC_0,P_VALUE,swLogPrintf("startSc is %d , wakeupSc is %d , bcLd 0x%X|%d "); +269312,551719680,0,0,PLAT_AP,PMU,ApmuSniffProc,P_VALUE,swLogPrintf("newRatio is 0x%X , f2sRatio is 0x%X , sleepLength is %d , timingShift is %d "); +269312,551721472,0,0,PLAT_AP,PMU,GetsleepLength,P_VALUE,swLogPrintf("CPSleepLengthTotal is %d , ApSleepLength = %d ( / 32 ) , sleepLengthAdj = %d "); +269312,551725055,0,0,PLAT_AP,PMU,ApmuSleepFailPostProc,P_SIG,swLogPrintf("sleep fail prcoess enter! "); +269312,551725312,0,0,PLAT_AP,PMU,funcTestCPAssistReq_0,P_SIG,swLogPrintf("CPmuStatus = 0x%x , IntCtrl = 0x%x "); +269312,551727360,0,0,PLAT_AP,PMU,funcTestCPAssistReq_1,P_SIG,swLogPrintf("CPmuStatus = 0x%x , IntCtrl = 0x%x "); +269312,551729408,0,0,PLAT_AP,PMU,funcTestCPAssistReq_2,P_SIG,swLogPrintf("CPmuStatus = 0x%x , IntCtrl = 0x%x "); +269312,551731456,0,0,PLAT_AP,PMU,funcTestCPAssistReq_3,P_SIG,swLogPrintf("CPmuStatus = 0x%x , IntCtrl = 0x%x "); +269312,551735295,0,0,PLAT_AP,PMU,funcTestCPAssistReq_4,P_SIG,swLogPrintf("Flush out "); +269312,551735552,0,0,PLAT_AP,PMU,funcTestCPAssistReq_5,P_SIG,swLogPrintf("CPmuStatus = 0x%x , IntCtrl = 0x%x "); +269312,551739391,0,0,PLAT_AP,PMU,apmuPadWakeupTest_00,P_SIG,swLogPrintf("AP Pad Wakeup Test , 6 Pad , pwrkey , charge Negetive , 10 second RTC "); +269312,551739648,0,0,PLAT_AP,PMU,apmuPadWakeupTest_1,P_SIG,swLogPrintf("pad wakeup test-%d , target Sc = %d "); +269312,551743487,0,0,PLAT_AP,PMU,apmuPadWakeupTest_2,P_SIG,swLogPrintf("funcTestPadWakeupTest sleep failed "); +269312,551745535,0,0,PLAT_AP,PMU,funcTestAONDeepSlpLatch_0,P_SIG,swLogPrintf("funcTestAONDeepSlpLatch Test , default set high "); +269312,551747583,0,0,PLAT_AP,PMU,funcTestAONDeepSlpLatch_1,P_SIG,swLogPrintf("Test AON IO Level , Pad can wakeup "); +269312,551749631,0,0,PLAT_AP,PMU,funcTestAONDeepSlpLatch_2,P_SIG,swLogPrintf("funcTestPadWakeupTest sleep failed "); +269312,551751679,0,0,PLAT_AP,PMU,funcTestCacheBypass_0,P_SIG,swLogPrintf("funcTestCacheBypass , do not bypass cache "); +269312,551753727,0,0,PLAT_AP,PMU,funcTestCacheBypass_1,P_SIG,swLogPrintf("funcTestCacheBypass , cache bypass "); +269312,551755775,0,0,PLAT_AP,PMU,funcTestCacheBypass_2,P_SIG,swLogPrintf("funcTestCacheBypass , Recover , do not bypass "); +269312,551757823,0,0,PLAT_AP,PMU,funcTestHardfault_0,P_WARNING,swLogPrintf("funcTestHardfault , trigger a hardfault "); +269312,551757824,0,0,PLAT_AP,PMU,funcTestWatchDog_0,P_WARNING,swLogPrintf("funcTestWatchDog , a while loop at last , rstReason = %d "); +269312,551761919,0,0,PLAT_AP,PMU,funcTestWatchDog_1,P_WARNING,swLogPrintf("should add while loop in nmi handler "); +269312,551762176,0,0,PLAT_AP,PMU,funcTestWatchDog_2,P_WARNING,swLogPrintf("aonreg15 = 0x%x , apTimer = 0x%x , cptimer = 0 "); +269312,551766015,0,0,PLAT_AP,PMU,funcTestForceDeepSlpWithCP_0,P_SIG,swLogPrintf("AP Force deepsleep , if cp allow "); +269312,551768063,0,0,PLAT_AP,PMU,funcTestForceDeepSlpWithCP_1,P_SIG,swLogPrintf("CP do not allow ap deep sleep "); +269312,551770111,0,0,PLAT_AP,PMU,funcTestForceDeepSlpWithCP_2,P_SIG,swLogPrintf("CP allow ap deep sleep "); +269312,551772159,0,0,PLAT_AP,PMU,funcTestForceDeepSlpWithCP_3,P_SIG,swLogPrintf("funcTestForceDeepSlpWithCP sleep failed "); +269312,551774207,0,0,PLAT_AP,PMU,funcTestSysMon_1,P_SIG,swLogPrintf("AP SysMon Test "); +269312,551776255,0,0,PLAT_AP,PMU,funcPllBypass_0,P_SIG,swLogPrintf("funcTestAPSleep1 Test "); +269312,551778303,0,0,PLAT_AP,PMU,funcPllBypass_1,P_ERROR,swLogPrintf("iso clk ref incorrect "); +269312,551780351,0,0,PLAT_AP,PMU,funcPllBypass_2,P_ERROR,swLogPrintf("iso clk pll incorrect "); +269312,551782399,0,0,PLAT_AP,PMU,funcPllBypass_3,P_SIG,swLogPrintf("Ap go sleep1 "); +269312,551784447,0,0,PLAT_AP,PMU,funcPllBypass_12,P_SIG,swLogPrintf("clk Status correct-in mcu mode "); +269312,551786495,0,0,PLAT_AP,PMU,funcPllBypass_13,P_SIG,swLogPrintf("clk Status not correct-in mcu mode "); +269312,551788543,0,0,PLAT_AP,PMU,funcPllBypass_121,P_SIG,swLogPrintf("clk Status correct-in normal mode "); +269312,551790591,0,0,PLAT_AP,PMU,funcPllBypass_131,P_SIG,swLogPrintf("clk Status not correct-in normal mode "); +269312,551792639,0,0,PLAT_AP,PMU,funcPllBypass_4,P_SIG,swLogPrintf("funcTestAPSleep1 sleep failed "); +269312,551794687,0,0,PLAT_AP,PMU,funcPllBypass_5,P_SIG,swLogPrintf("funcTestAPSleep1 sleep success "); +269312,551796735,0,0,PLAT_AP,PMU,funcPllBypass_6,P_VALUE,swLogPrintf("enter mcu mode correct "); +269312,551798783,0,0,PLAT_AP,PMU,funcPllBypass_61,P_ERROR,swLogPrintf("enter mcu mode incorrect "); +269312,551800831,0,0,PLAT_AP,PMU,funcPllBypass_62,P_VALUE,swLogPrintf("wakeup in normal mode correct "); +269312,551802879,0,0,PLAT_AP,PMU,funcPllBypass_63,P_ERROR,swLogPrintf("wakeup in normal mode incorrect "); +269312,551804927,0,0,PLAT_AP,PMU,funcPllBypass_7,P_VALUE,swLogPrintf("enter mcu mode correct "); +269312,551806975,0,0,PLAT_AP,PMU,funcPllBypass_8,P_VALUE,swLogPrintf("ison valid "); +269312,551809023,0,0,PLAT_AP,PMU,funcPllBypass_9,P_VALUE,swLogPrintf("ison invalid "); +269312,551811071,0,0,PLAT_AP,PMU,funcPllBypass_10,P_VALUE,swLogPrintf("pll force on failed "); +269312,551813119,0,0,PLAT_AP,PMU,funcPllBypass_11,P_VALUE,swLogPrintf("pll force on success "); +269312,551815167,0,0,PLAT_AP,PMU,funcPllBypass_14,P_SIG,swLogPrintf("clk Status correct after mcu mode force on pll "); +269312,551817215,0,0,PLAT_AP,PMU,funcPllBypass_15,P_SIG,swLogPrintf("clk Status not correct after mcu mode force on pll "); +269312,551817216,0,0,PLAT_AP,PMU,funcTestDFCTest_0,P_WARNING,swLogPrintf("DeltaTime when not vote = %d "); +269312,551819264,0,0,PLAT_AP,PMU,funcTestDFCTest_1,P_WARNING,swLogPrintf("DeltaTime when not vote = %d "); +269312,551823359,0,0,PLAT_AP,PMU,funcTestDFCTest_2,P_VALUE,swLogPrintf("ap clk change to 26 M "); +269312,551825407,0,0,PLAT_AP,PMU,funcTestDFCTest_3,P_VALUE,swLogPrintf("Err : ap clk not change to 26 M "); +269312,551827455,0,0,PLAT_AP,PMU,funcTestDFCTest_4,P_VALUE,swLogPrintf("cp clk change to 26 M "); +269312,551829503,0,0,PLAT_AP,PMU,funcTestDFCTest_5,P_VALUE,swLogPrintf("Err : cp clk not change to 26 M "); +269312,551831551,0,0,PLAT_AP,PMU,funcTestAonReadWrite_0,P_WARNING,swLogPrintf("funcTestAonReadWrite Read and write "); +269312,551833599,0,0,PLAT_AP,PMU,funcTestAonReadWrite_1,P_WARNING,swLogPrintf("funcTestAonReadWrite Test Failed "); +269312,551835647,0,0,PLAT_AP,PMU,funcTestSlowCnt_3,P_WARNING,swLogPrintf("funcTestSlowCnt Read "); +269312,551835648,0,0,PLAT_AP,PMU,funcTestSlowCnt_0,P_VALUE,swLogPrintf("slow cnt 0 = %d "); +269312,551837696,0,0,PLAT_AP,PMU,funcTestSlowCnt_1,P_VALUE,swLogPrintf("slow cnt 1 = %d "); +269312,551839744,0,0,PLAT_AP,PMU,funcTestSlowCnt_2,P_VALUE,swLogPrintf("slow cnt 2 = %d "); +269312,551843839,0,0,PLAT_AP,PMU,funcTestSlowCnt_4,P_VALUE,swLogPrintf("funcTestSlowCnt Test failed "); +269312,551845887,0,0,PLAT_AP,PMU,funcTestWakeupPinValue_0,P_WARNING,swLogPrintf("Test AP Wakeup Pin Value "); +269312,551845888,0,0,PLAT_AP,PMU,funcTestWakeupPinValue_1,P_SIG,swLogPrintf("PinValue = 0x%x "); +269312,551849983,0,0,PLAT_AP,PMU,funcTestAPCPDapWakeup_0,P_SIG,swLogPrintf("funcTestAPCPDapWakeup Test "); +269312,551852031,0,0,PLAT_AP,PMU,funcTestAPCPDapWakeup_1,P_SIG,swLogPrintf("Error : CP is already power on "); +269312,551854079,0,0,PLAT_AP,PMU,funcTestCPDapWakeup_2,P_SIG,swLogPrintf("CP Dap Wakeup Enable , connect AP Jlink to wakeup cp "); +269312,551856127,0,0,PLAT_AP,PMU,funcTestCPCPDapWakeup_0,P_SIG,swLogPrintf("funcTestCPCPDapWakeup Test "); +269312,551858175,0,0,PLAT_AP,PMU,funcTestCPCPDapWakeup_1,P_SIG,swLogPrintf("Error : CP is already power on "); +269312,551860223,0,0,PLAT_AP,PMU,funcTestCPCPDapWakeup_2,P_SIG,swLogPrintf("CP Dap Wakeup Enable , connect CP Jlink to wakeup cp "); +269312,551860224,0,0,PLAT_AP,PMU,funcTestAPSysReset_1,P_SIG,swLogPrintf("AP Arm Reset Test , rstReason = %d "); +269312,551862272,0,0,PLAT_AP,PMU,funcTestAPSysReset_3,P_SIG,swLogPrintf("Aon Reset Reason = 0x%x "); +269312,551864576,0,0,PLAT_AP,PMU,funcTestAPSysReset_4,P_WARNING,swLogPrintf("aonreg15 = 0x%x , apTimer = 0x%x "); +269312,551868415,0,0,PLAT_AP,PMU,funcTestAPSysReset_2,P_SIG,swLogPrintf("AP Arm Reseting...... "); +269312,551870463,0,0,PLAT_AP,PMU,funcTestBootOnCPFlash_0,P_SIG,swLogPrintf("funcTestBootOnCPFlash Test , CP XIP Init By AP "); +269312,551872511,0,0,PLAT_AP,PMU,funcTestBootOnCPFlash_1,P_SIG,swLogPrintf("Error : CP is already power on "); +269312,551874559,0,0,PLAT_AP,PMU,funcTestBootOnCPFlash_2,P_SIG,swLogPrintf("Wait CP Power On "); +269312,551876607,0,0,PLAT_AP,PMU,funcTestBootOnCPFlash_3,P_SIG,swLogPrintf("CP Power On Finish , connet CP Jlink to comfirm "); +269312,551878655,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_0,P_SIG,swLogPrintf("funcTestBootCPOnCSMB Test , by copy code to csmb and assist boot "); +269312,551880703,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_1,P_SIG,swLogPrintf("Error : CP is already power on "); +269312,551882751,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_2,P_SIG,swLogPrintf("Wait CP Power On "); +269312,551884799,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_3,P_SIG,swLogPrintf("CP Power On Finish "); +269312,551885056,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_4,P_SIG,swLogPrintf("Vector Read Back Error = 0x%x , 0x%x "); +269312,551886848,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_5,P_SIG,swLogPrintf("Code Write Err @ %d "); +269312,551888896,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_6,P_SIG,swLogPrintf("CPmuStatus = 0x%x "); +269312,551892991,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_7,P_SIG,swLogPrintf("Case pass , CP Code Run Success "); +269312,551895039,0,0,PLAT_AP,PMU,funcTestBootCPOnCSMB_8,P_SIG,swLogPrintf("Case funcTestBootCPOnCSMB Fail "); +269312,551897087,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_0,P_SIG,swLogPrintf("funcTestBootCPOnCSMB Test , by copy code to csmb and assist boot "); +269312,551899135,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_1,P_SIG,swLogPrintf("Error : CP is already power on "); +269312,551899392,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_4,P_SIG,swLogPrintf("Vector Read Back Error = 0x%x , 0x%x "); +269312,551901184,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_5,P_SIG,swLogPrintf("Code Write Err @ %d "); +269312,551903232,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_6,P_SIG,swLogPrintf("CPmuStatus = 0x%x "); +269312,551907327,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_7,P_SIG,swLogPrintf("Case pass , CP Code Run Success "); +269312,551909375,0,0,PLAT_AP,PMU,funcTestBootCPOnMSMB_8,P_SIG,swLogPrintf("Case funcTestBootCPOnMSMB Fail "); +269312,551911423,0,0,PLAT_AP,PMU,funcTestCPStatusRead_0,P_SIG,swLogPrintf("funcTestCPStatusRead , CP running to change state , AP read "); +269312,551911424,0,0,PLAT_AP,PMU,funcTestCPStatusRead_1,P_SIG,swLogPrintf("CPmuStatus = 0x%x "); +269312,551913472,0,0,PLAT_AP,PMU,funcTestCPStatusRead_2,P_SIG,swLogPrintf("CPmuStatus = 0x%x "); +269312,551916032,0,0,PLAT_AP,PMU,funcTestCPStatusRead_3,P_SIG,swLogPrintf("0x4d030064 = %x 0x4d030068 = %x 0x4d03006C = %x "); +269312,551918080,0,0,PLAT_AP,PMU,funcTestCPStatusRead_4,P_SIG,swLogPrintf("0x4d030070 = %x 0x4d030074 = %x 0x4d030078 = %x "); +269312,551921663,0,0,PLAT_AP,PMU,funcTestBootCPIPC_0,P_SIG,swLogPrintf("funcTestBootCPIPC , power on cp using ipc "); +269312,551923711,0,0,PLAT_AP,PMU,funcTestBootCPIPC_1,P_SIG,swLogPrintf("Error : CP is already power on "); +269312,551923712,0,0,PLAT_AP,PMU,funcTestBootCPIPC_2,P_SIG,swLogPrintf("CPmuStatus = 0x%x "); +269312,551925760,0,0,PLAT_AP,PMU,funcTestBootCPIPC_3,P_SIG,swLogPrintf("CP Power On Finish , CPmuStatus = 0x%x "); +269312,551927808,0,0,PLAT_AP,PMU,funcTestAonWatchdog_00,P_SIG,swLogPrintf("Aon Reset Reason = 0x%x "); +269312,551930368,0,0,PLAT_AP,PMU,funcTestAonWatchdog_1,P_SIG,swLogPrintf("funcTestAonWatchdog , current = %d , target = %d , changed = %d "); +269312,551931904,0,0,PLAT_AP,PMU,funcTestLockupTest_1,P_SIG,swLogPrintf("funcTestLockupTest , rstReason = %d "); +269312,551934208,0,0,PLAT_AP,PMU,funcTestLockupTest_2,P_WARNING,swLogPrintf("aonreg15 = 0x%x , apTimer = 0x%x , cptimer = 0 "); +269312,551936000,0,0,PLAT_AP,PMU,funcTestSIPCTest_1,P_WARNING,swLogPrintf("AP SIPC Lock Result = %d "); +269312,551938048,0,0,PLAT_AP,PMU,funcTestSIPCTest_3,P_WARNING,swLogPrintf("Ier = 0x%x "); +269312,551942143,0,0,PLAT_AP,PMU,funcTestSIPCTest_2,P_WARNING,swLogPrintf("AP SIPC Release "); +269312,551942400,0,0,PLAT_AP,PMU,CpStatusTask_1,P_SIG,swLogPrintf("CPmuStatus = 0x%x , IntCtrl = 0x%x "); +269312,551946239,0,0,PLAT_AP,PMU,funcTestCPAPBReset_1,P_SIG,swLogPrintf("AP funcTestCPAPBReset "); +269312,551946240,0,0,PLAT_AP,PMU,funcTestCPAPBReset_2,P_SIG,swLogPrintf("Start Wait CP Set Wdt , but not start , wdtReg = 0x%x "); +269312,551948288,0,0,PLAT_AP,PMU,funcTestCPAPBReset_3,P_SIG,swLogPrintf("CP Set Wdt , Reg = 0x%x "); +269312,551952383,0,0,PLAT_AP,PMU,funcTestCPAPBReset_4,P_SIG,swLogPrintf("AP Arm Reseting...... "); +269312,551954431,0,0,PLAT_AP,PMU,RegTimeRead_0,P_VALUE,swLogPrintf("AonReg Read Err "); +269312,551954432,0,0,PLAT_AP,PMU,RegTimeRead_1,P_VALUE,swLogPrintf("AonRegRead 5000 time = 0x%x "); +269312,551956480,0,0,PLAT_AP,PMU,RegTimeRead_2,P_VALUE,swLogPrintf("mpGPRRegRead 5000 time = 0x%x "); +269312,551958528,0,0,PLAT_AP,PMU,RegTimeRead_3,P_VALUE,swLogPrintf("rmiGPRRegRead 5000 time = 0x%x "); +269312,551960576,0,0,PLAT_AP,PMU,RegTimeRead_4,P_VALUE,swLogPrintf("cpWdtRegRead 5000 time = 0x%x "); +269312,551962624,0,0,PLAT_AP,PMU,RegTimeRead_40,P_VALUE,swLogPrintf("apWdtRegRead 5000 time = 0x%x "); +269312,551964672,0,0,PLAT_AP,PMU,RegTimeRead_5,P_VALUE,swLogPrintf("msmbRegRead 5000 time = 0x%x "); +269312,551966720,0,0,PLAT_AP,PMU,RegTimeRead_6,P_VALUE,swLogPrintf("csmbRegRead 5000 time = 0x%x "); +269312,551968768,0,0,PLAT_AP,PMU,RegTimeRead_7,P_VALUE,swLogPrintf("asmbRegRead 5000 time = 0x%x "); +269312,551972863,0,0,PLAT_AP,PMU,funcHWTestSleepMode_1,P_VALUE,swLogPrintf("Start Sleep1 Test...... \r \n "); +269312,551974911,0,0,PLAT_AP,PMU,funcHWTestSleepMode_2,P_VALUE,swLogPrintf("Start Sleep2 With ASMB+CSMB Retention Test...... \r \n "); +269312,551976959,0,0,PLAT_AP,PMU,funcHWTestSleepMode_3,P_VALUE,swLogPrintf("Test Failed : Failed to Enter Sleep2 With ASMB+CSMB Retention \r \n "); +269312,551979007,0,0,PLAT_AP,PMU,funcHWTestSleepMode_4,P_VALUE,swLogPrintf("Start Sleep2 With ASMB Retention Test...... \r \n "); +269312,551981055,0,0,PLAT_AP,PMU,funcHWTestSleepMode_5,P_VALUE,swLogPrintf("Test Failed : Failed to Enter Sleep2 With ASMB Retention. \r \n "); +269312,551983103,0,0,PLAT_AP,PMU,funcHWTestSleepMode_6,P_VALUE,swLogPrintf("Start Sleep2 With ASMB+MSMB Retention Test...... \r \n "); +269312,551985151,0,0,PLAT_AP,PMU,funcHWTestSleepMode_7,P_VALUE,swLogPrintf("Test Failed : Failed to Enter Sleep2 With ASMB+MSMB Retention. \r \n "); +269312,551987199,0,0,PLAT_AP,PMU,funcHWTestSleepMode_8,P_VALUE,swLogPrintf("Start Hibernate with no retention Test...... \r \n "); +269312,551989247,0,0,PLAT_AP,PMU,funcHWTestSleepMode_9,P_VALUE,swLogPrintf("Test Failed : Failed to Enter Hibernate with no retention. \r \n "); +269312,551991295,0,0,PLAT_AP,PMU,funcHWTestSleepMode_10,P_VALUE,swLogPrintf("Start Off Test...... \r \n "); +269312,551993343,0,0,PLAT_AP,PMU,funcHWTestSleepMode_11,P_VALUE,swLogPrintf("Test Failed : Failed to Enter Off State. \r \n "); +269312,551995391,0,0,PLAT_AP,PMU,funcHWTestSleepMode_12,P_VALUE,swLogPrintf("WFI Normal IO On \r \n "); +269312,551997439,0,0,PLAT_AP,PMU,funcHWTestSleepMode_13,P_VALUE,swLogPrintf("WFI Normal IO Off \r \n "); +269312,551999487,0,0,PLAT_AP,PMU,funcHWTestSleepMode_14,P_VALUE,swLogPrintf("WFI 26 M \r \n "); +269312,552001535,0,0,PLAT_AP,PMU,funcHWTestSleepMode_15,P_VALUE,swLogPrintf("WFI Mcu Mode \r \n "); +269312,552001536,0,0,PLAT_AP,PMU,AONIO_ISR_1,P_VALUE,swLogPrintf("AONIO_ISR Enter Counter = %d "); +269312,552005631,0,0,PLAT_AP,PMU,apmuSwitch2McuMode_0,P_SIG,swLogPrintf("Already in mcu mode "); +269312,552007679,0,0,PLAT_AP,PMU,mcuSwitch2CommMode_0,P_SIG,swLogPrintf("Already in comm mode "); +269312,552009727,0,0,PLAT_AP,PMU,mcuModeInit_0,P_SIG,swLogPrintf("Mcu Mode : Switch to Mcu Mode "); +269312,552011775,0,0,PLAT_AP,PMU,mcuModeInit_1,P_SIG,swLogPrintf("Mcu Mode : Switch to Comm Mode "); +269312,552013823,0,0,PLAT_AP,PMU,slpManStartPowerOff_0,P_SIG,swLogPrintf("Power Off Start "); +269312,552014080,0,0,PLAT_AP,PMU,dcxoRestore,P_INFO,swLogPrintf("DCXO restore! temprPreAttach = %d , freqPPMPreAttach = %d "); +269312,552017919,0,0,PLAT_AP,PMU,cmsProcSignal_Utc,P_ERROR,swLogPrintf("SIG_CMS_UTC_TIME_REQ UTC Read Error! "); +269312,552018176,0,0,PLAT_AP,PMU,mainTask_1,P_VALUE,swLogPrintf("APHL BootFlag = %e , APLL BootFlag = %e "); +269312,552020224,0,0,PLAT_AP,PMU,IPC0_Check,P_VALUE,swLogPrintf("XIC0 Latch = 0x%x , NVIC = 0x%x "); +269312,552022016,0,0,PLAT_AP,PMU,usblpw_wkup_or_init_pre_0,P_WARNING,swLogPrintf("ctx stat reg %d "); +269312,552024832,0,0,PLAT_AP,PMU,usblpw_wkup_or_init_0,P_VALUE,swLogPrintf("pwr state 0x%x , bootstat 0x%x , lastwkup 0x%x , othwk stg 0x%x "); +269312,552026880,0,0,PLAT_AP,PMU,usblpw_wkup_or_init_1,P_VALUE,swLogPrintf("pwr state 0x%x , bootstat 0x%x , lastwkup 0x%x , inimod 0x%x "); +269312,552028416,0,0,PLAT_AP,PMU,usblpw_wkup_or_init_2,P_VALUE,swLogPrintf("othwk stg 0x%x , proc_stat 0x%x "); +269312,552030208,0,0,PLAT_AP,PMU,chargeStatusCb_1,P_VALUE,swLogPrintf("Charge Status update = %d "); +269312,552034303,0,0,PLAT_AP,PMU,PwrKey_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pwr key Wakeup "); +269312,552036351,0,0,PLAT_AP,PMU,ChrgPad_WakeupIntHandler_1,P_VALUE,swLogPrintf("charge Wakeup "); +269312,552038399,0,0,PLAT_AP,PMU,Pad0_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pad0 Wakeup "); +269312,552040447,0,0,PLAT_AP,PMU,Pad1_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pad1 Wakeup "); +269312,552042495,0,0,PLAT_AP,PMU,Pad2_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pad2 Wakeup "); +269312,552044543,0,0,PLAT_AP,PMU,Pad3_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pad3 Wakeup "); +269312,552046591,0,0,PLAT_AP,PMU,Pad4_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pad4 Wakeup "); +269312,552048639,0,0,PLAT_AP,PMU,Pad5_WakeupIntHandler_1,P_VALUE,swLogPrintf("Pad5 Wakeup "); +269312,552050687,0,0,PLAT_AP,PMU,apmu2PeriWFITimerExp_0,P_VALUE,swLogPrintf("apmu2PeriWFITimerExp Enter "); +269312,552051200,0,0,PLAT_AP,PMU,apmuPeriStartWFITimer_0,P_ERROR,swLogPrintf("clkRet1 = %d , clkRet2 = %d , CLKFREQ = 0x%x "); +269312,552052736,0,0,PLAT_AP,PMU,apmuPeriStartWFITimer_1,P_VALUE,swLogPrintf("apmuPeriStartWFITimer set to %u ms "); +269312,552055296,0,0,PLAT_AP,PMU,apmuPeriStartCPTimer_0,P_ERROR,swLogPrintf("clkRet1 = %d , clkRet2 = %d , CLKFREQ = 0x%x "); +269312,552056832,0,0,PLAT_AP,PMU,apmuPeriStartCPTimer_1,P_VALUE,swLogPrintf("apmuCreateModemStartTimer set to %u ms "); +269312,552058880,0,0,PLAT_AP,PMU,chargeIntHandler_1,P_VALUE,swLogPrintf("Charger Int Enter , Status Update = %d "); +269312,552060928,0,0,PLAT_AP,PMU,chargeDetectInit_1,P_VALUE,swLogPrintf("Charger Detect Init , Status Update = %d "); +269312,552065023,0,0,PLAT_AP,PMU,pwrKeySendKeyStatus_1,P_VALUE,swLogPrintf("Power Key message send error "); +269312,552067071,0,0,PLAT_AP,PMU,pwrKeySendKeyStatus_2,P_VALUE,swLogPrintf("Power Key queue not ready "); +269312,552069119,0,0,PLAT_AP,PMU,pwrKeySendKeyStatusInIsr_1,P_VALUE,swLogPrintf("Power Key message send in isr error "); +269312,552071167,0,0,PLAT_AP,PMU,pwrKeySendKeyStatusInIsr_2,P_VALUE,swLogPrintf("Power Key queue not ready in isr "); +269312,552073215,0,0,PLAT_AP,PMU,pwrKeyTask_1,P_VALUE,swLogPrintf("Power Key task queue init error "); +269312,552075263,0,0,PLAT_AP,PMU,cmsProcSignal_1,P_VALUE,swLogPrintf("cmsProcSignal CP start ind "); +270336,553650432,0,0,PLAT_AP,CCIO,ADD_DEV_1,P_INFO,swLogPrintf("device ( 0x%x / %d ) is added! "); +270336,553652224,0,0,PLAT_AP,CCIO,DEL_DEV_0,P_INFO,swLogPrintf("device ( 0x%x ) is deleted! "); +270336,553656319,0,0,PLAT_AP,CCIO,DEL_DEV_1,P_SIG,swLogPrintf("no devices in the list! "); +270336,553656320,0,0,PLAT_AP,CCIO,FIND_DEV_1,P_SIG,swLogPrintf("device ( 0x%x ) is not registered! "); +270336,553658368,0,0,PLAT_AP,CCIO,FIND_DEV_2,P_SIG,swLogPrintf("device ( 0x%x ) is not found! "); +270336,553662463,0,0,PLAT_AP,CCIO,FIND_DEV_BY_TYPES_1,P_SIG,swLogPrintf("no device in the list! "); +270336,553662976,0,0,PLAT_AP,CCIO,FIND_DEV_BY_TYPES_2,P_SIG,swLogPrintf("device ( %d / %d / %d ) is not found! "); +270336,553666559,0,0,PLAT_AP,CCIO,ASGN_DEV_BY_TYPES,P_SIG,swLogPrintf("no avail device to be assigned! "); +270336,553666816,0,0,PLAT_AP,CCIO,ASGN_DEV_BY_TYPES_1,P_SIG,swLogPrintf("%d / %d device can be assigned "); +270336,553670655,0,0,PLAT_AP,CCIO,ASGN_DEV_BY_TYPE,P_SIG,swLogPrintf("no avail device to be assigned! "); +270336,553670912,0,0,PLAT_AP,CCIO,ASGN_DEV_BY_TYPE_1,P_INFO,swLogPrintf("%d / %d device can be assigned "); +270336,553674751,0,0,PLAT_AP,CCIO,TRAVERSE_DEV_BY_HT,P_SIG,swLogPrintf("no device in the list! "); +270336,553675520,0,0,PLAT_AP,CCIO,SET_DEV_WORK_STATE,P_SIG,swLogPrintf("device ( 0x%x ) wkState : old ( %d ) --> new ( %d ) , hwAcm ( %d ) ! "); +270336,553676800,0,0,PLAT_AP,CCIO,ADD_ENTITY_1,P_SIG,swLogPrintf("entity has been assigned with devices ( 0x%x ) ? "); +270336,553678848,0,0,PLAT_AP,CCIO,ADD_ENTITY_2,P_SIG,swLogPrintf("warning! a device has already been assigned to entity ( %d ) ? "); +270336,553682943,0,0,PLAT_AP,CCIO,DEL_ENTITY_0,P_SIG,swLogPrintf("no entity in the list! "); +270336,553682944,0,0,PLAT_AP,CCIO,FIND_ENTITY_1,P_SIG,swLogPrintf("warning! no device is assigned to entity ( %d ) ? "); +270336,553687039,0,0,PLAT_AP,CCIO,FIND_ENTITY_BY_TYPES_1,P_SIG,swLogPrintf("no entity in the list! "); +270336,553687296,0,0,PLAT_AP,CCIO,FIND_ENTITY_BY_TYPES_2,P_SIG,swLogPrintf("entity ( %d / %d ) is not found! "); +270336,553689344,0,0,PLAT_AP,CCIO,TRY_ASGN_DEV_0,P_SIG,swLogPrintf("try assign device to entity ( %d / %d ) ... "); +270336,553691136,0,0,PLAT_AP,CCIO,TRY_ASGN_DEV_1,P_INFO,swLogPrintf("succ! device ( 0x%x ) is assigned! "); +270336,553695231,0,0,PLAT_AP,CCIO,TRY_ASGN_DEV_2,P_SIG,swLogPrintf("failed! try again later... "); +270336,553695744,0,0,PLAT_AP,CCIO,RBUF_GET_XBATCH_1,P_WARNING,swLogPrintf("rbuf ( %d ) : RxWinSz ( %d ) < minSz ( %d ) ! wait ulfc event... "); +270336,553699072,0,0,PLAT_AP,CCIO,RBUF_GET_XBATCH_2,P_INFO,swLogPrintf("rbuf ( %d ) : batchCnt ( %d / %d|%d ) @sti ( %d ) , wri ( %d --> %d ) , dummy ( 0x%x ) "); +270336,553700352,0,0,PLAT_AP,CCIO,RBUF_MAPPING_NPT,P_INFO,swLogPrintf("rbuf ( %d ) : xferCnt ( %d ) , range [ %d , %d ] , aligned ( %d ) "); +270336,553701376,0,0,PLAT_AP,CCIO,RBUF_DLVR_XBATCH,P_SIG,swLogPrintf("rbuf ( %d ) : deliver zero bytes? "); +270336,553703936,0,0,PLAT_AP,CCIO,RBUF_HANDLE_FULL_PT_1,P_SIG,swLogPrintf("rbuf ( %d ) : %d bytes @sti ( %d ) shall be flushed? "); +270336,553705728,0,0,PLAT_AP,CCIO,RBUF_HANDLE_FULL_PT_2,P_WARNING,swLogPrintf("rbuf ( %d ) : %d bytes ' valid ' data in the tail? "); +270336,553708288,0,0,PLAT_AP,CCIO,RBUF_IS_LAST_RDI,P_INFO,swLogPrintf("rbuf ( %d ) : vmode ( %d ) free @sti ( %d ) , rdi ( %d ) "); +270336,553710084,0,0,PLAT_AP,CCIO,RBUF_IS_NEXT_NPT_FREE,P_INFO,swLogPrintf("rbuf ( %d ) : next @sti ( %d ) %s free "); +270336,553712640,0,0,PLAT_AP,CCIO,RBUF_ADJUST_PT_RW_ZONE,P_SIG,swLogPrintf("rbuf ( %d ) : adjust xferCnt ( %d --> %d ) , sti ( %d --> %d ) "); +270336,553714688,0,0,PLAT_AP,CCIO,RBUF_ADJUST_NPT_RW_ZONE,P_SIG,swLogPrintf("rbuf ( %d ) : adjust sti ( %d --> %d ) , rdi ( %d --> %d ) "); +270336,553715712,0,0,PLAT_AP,CCIO,RBUF_PT_DEQUEUE,P_INFO,swLogPrintf("rbuf ( %d ) : zero xfer? just free PT pcb node? "); +270336,553718016,0,0,PLAT_AP,CCIO,RBUF_GET,P_SIG,swLogPrintf("%d / %d rbuf node ( s ) have been used! "); +270336,553719808,0,0,PLAT_AP,CCIO,RBUF_UNGET,P_SIG,swLogPrintf("%d rbuf nodes have been used! "); +270336,553722112,0,0,PLAT_AP,CCIO,RBUF_UNGET_ULPCB,P_WARNING,swLogPrintf("rbuf ( %d ) : pcb ( 0x%x ) is a global variable? "); +270336,553723904,0,0,PLAT_AP,CCIO,RBUF_QUEUE_1,P_INFO,swLogPrintf("rbuf ( %d ) : zero batch , all handled before? "); +270336,553725952,0,0,PLAT_AP,CCIO,RBUF_QUEUE_2,P_SIG,swLogPrintf("rbuf ( %d ) : more xbatch on the way? "); +270336,553728768,0,0,PLAT_AP,CCIO,RBUF_QUEUE_3,P_INFO,swLogPrintf("rbuf ( %d ) : next batch @sti ( %d ) / wri ( %d ) / rdi ( %d ) "); +270336,553730560,0,0,PLAT_AP,CCIO,RBUF_DEQUEUE,P_INFO,swLogPrintf("rbuf ( %d ) : rdi up ( %d --> %d ) "); +270336,553732608,0,0,PLAT_AP,CCIO,RBUF_SEL_FLUSH_XFER_0,P_SIG,swLogPrintf("rbuf ( %d ) : flush %d bytes @sti ( %d ) ? "); +270336,553734144,0,0,PLAT_AP,CCIO,RBUF_SEL_FLUSH_XFER_1,P_SIG,swLogPrintf("rbuf ( %d ) : zero batch , all handled before? "); +270336,553736448,0,0,PLAT_AP,CCIO,RBUF_SEL_FLUSH_XFER_2,P_WARNING,swLogPrintf("rbuf ( %d ) : %d bytes ' valid ' data in the tail? "); +270336,553738240,0,0,PLAT_AP,CCIO,RBUF_SEL_FLUSH_XFER_3,P_INFO,swLogPrintf("rbuf ( %d ) : no xfer to be flushed? "); +270336,553740800,0,0,PLAT_AP,CCIO,RBUF_SEL_FLUSH_XFER_4,P_INFO,swLogPrintf("rbuf ( %d ) : next batch @wri ( %d ) / rdi ( %d ) "); +270336,553743104,0,0,PLAT_AP,CCIO,RBUF_START_RECV_XFER,P_SIG,swLogPrintf("rbuf ( %d ) : start batch recv @sti ( %d ) / wri ( %d ) / rdi ( %d ) "); +270336,553745920,0,0,PLAT_AP,CCIO,RBUF_SET_WKSTATE_1,P_SIG,swLogPrintf("rbuf ( %d ) : bmMode ( 0x%x-->0x%x ) , cctSize ( %d-->%d ) , alignVal ( %d-->%d ) ! "); +270336,553746432,0,0,PLAT_AP,CCIO,RBUF_SET_WKSTATE_2,P_WARNING,swLogPrintf("rbuf ( %d ) : set data conf err , device pulled out? "); +270336,553748480,0,0,PLAT_AP,CCIO,TFC_CONV_TO_PID,P_ERROR,swLogPrintf("unknown TFC obj media type ( %d ) ! "); +270336,553751296,0,0,PLAT_AP,CCIO,TFC_CREATE_1,P_INFO,swLogPrintf("device ( 0x%x : %d / %d / %d ) dont need TFC! "); +270336,553752832,0,0,PLAT_AP,CCIO,TFC_CREATE_2,P_SIG,swLogPrintf("TFC Obj ( %d ) already registered in TOIM ( 0x%x ) ! "); +270336,553755392,0,0,PLAT_AP,CCIO,TFC_CREATE_3,P_SIG,swLogPrintf("TFC Pid ( %d : %d / %d , 0x%x ) already created! "); +270336,553756672,0,0,PLAT_AP,CCIO,TFC_DELETE_1,P_SIG,swLogPrintf("TFC Pid ( %d ) already deleted! "); +270336,553758976,0,0,PLAT_AP,CCIO,TFC_DELETE_2,P_SIG,swLogPrintf("TFC Obj ( %d ) not registered in TOIM ( 0x%x ) ! "); +270336,553761792,0,0,PLAT_AP,CCIO,TFC_DELETE_3,P_INFO,swLogPrintf("TFC Pid ( %d : %d / %d ) still refered by others ( 0x%x / %d ) ! "); +270336,553763328,0,0,PLAT_AP,CCIO,CEIO_INPUT_ENT,P_WARNING,swLogPrintf("ecm ( 0x%x ) : state ( %d ) is not connected! discard it ( 0x%p ) ! "); +270336,553764864,0,0,PLAT_AP,CCIO,CEIO_RBUF_INIT,P_INFO,swLogPrintf("rbuf ( 0x%x ) has already inited! "); +270336,553766912,0,0,PLAT_AP,CCIO,ECM_DEV_PWON_0,P_SIG,swLogPrintf("ecm dev ( 0x%x ) power on! "); +270336,553771007,0,0,PLAT_AP,CCIO,ECM_DEV_PWON_1,P_WARNING,swLogPrintf("chentStatusCb is not inited? "); +270336,553771008,0,0,PLAT_AP,CCIO,ECM_DEV_PWOFF_0,P_SIG,swLogPrintf("ecm dev ( 0x%x ) power off! "); +270336,553773056,0,0,PLAT_AP,CCIO,EUTRA_DEV_PWON,P_SIG,swLogPrintf("eutra dev ( 0x%x ) power on! "); +270336,553775104,0,0,PLAT_AP,CCIO,EUTRA_DEV_PWOFF,P_SIG,swLogPrintf("eutra dev ( 0x%x ) power off! "); +270336,553777664,0,0,PLAT_AP,CCIO,CRIO_INPUT_ENT,P_WARNING,swLogPrintf("rndis ( 0x%x ) : state ( %d ) is not connected! discard it ( 0x%p ) ! "); +270336,553779200,0,0,PLAT_AP,CCIO,CRIO_RBUF_INIT,P_INFO,swLogPrintf("rbuf ( 0x%x ) has already inited! "); +270336,553781248,0,0,PLAT_AP,CCIO,RNDIS_DEV_PWON_0,P_SIG,swLogPrintf("rndis dev ( 0x%x ) power on! "); +270336,553785343,0,0,PLAT_AP,CCIO,RNDIS_DEV_PWON_1,P_WARNING,swLogPrintf("chentStatusCb is not inited? "); +270336,553785344,0,0,PLAT_AP,CCIO,RNDIS_DEV_PWOFF_0,P_SIG,swLogPrintf("rndis dev ( 0x%x ) power off! "); +270336,553787392,0,0,PLAT_AP,CCIO,CLEAR_PPP_UL_REMAINS,P_SIG,swLogPrintf("serlEnt ( 0x%x ) : clear ppp pending ulpdu! "); +270336,553789440,0,0,PLAT_AP,CCIO,AT_ENT_INPUT,P_WARNING,swLogPrintf("serlEnt ( 0x%x ) : unblock sct usb ep failure! "); +270336,553791488,0,0,PLAT_AP,CCIO,CLEAR_PPP_DL_REMAINS_1,P_SIG,swLogPrintf("serlEnt ( 0x%x ) : clear ppp outdated dlpdu! "); +270336,553793536,0,0,PLAT_AP,CCIO,CLEAR_PPP_DL_REMAINS_2,P_SIG,swLogPrintf("serlEnt ( 0x%x ) : clear ppp pending dlpdu! "); +270336,553796352,0,0,PLAT_AP,CCIO,PPPENT_INPUT_UNESC,P_WARNING,swLogPrintf("pppEnt ( 0x%x ) : fcs ( 0x%x ) error! drop %d / %d bytes! "); +270336,553798656,0,0,PLAT_AP,CCIO,PPPENT_SCT_INPUT_END_1,P_SIG,swLogPrintf("pppEnt ( %d ) : concat rbuf ( 0x%x / %d , 0x%x / %d ) ! "); +270336,553800192,0,0,PLAT_AP,CCIO,PPPENT_SCT_INPUT_END_2,P_WARNING,swLogPrintf("pppEnt ( %d ) : length ( %d ) overflows! dropping it ( 0x%x ) ! "); +270336,553801984,0,0,PLAT_AP,CCIO,PPPENT_SCT_INPUT_1,P_INFO,swLogPrintf("pppEnt ( %d ) : alloc ( %d ) failure! waiting ulfc evt... "); +270336,553804032,0,0,PLAT_AP,CCIO,PPPENT_SCT_INPUT_2,P_ERROR,swLogPrintf("pppEnt ( %d ) : dropping bad fcs packet ( 0x%x ) ! "); +270336,553806336,0,0,PLAT_AP,CCIO,PPPENT_INPUT_1,P_WARNING,swLogPrintf("pppEnt ( 0x%x ) : disconnected ( %d ) ! discard all ( 0x%p ) ! "); +270336,553807872,0,0,PLAT_AP,CCIO,PPPENT_INPUT_2,P_SIG,swLogPrintf("pppEnt ( 0x%x ) : special pattern ( +++ ) ! "); +270336,553810688,0,0,PLAT_AP,CCIO,PPPENT_OUTPUT_1,P_WARNING,swLogPrintf("pppEnt ( 0x%x ) : sessn ( 0x%x ) is lost or not in data mode ( %d ) ! discard it ( 0x%p ) ... "); +270336,553812224,0,0,PLAT_AP,CCIO,PPPENT_OUTPUT_2,P_WARNING,swLogPrintf("pppEnt ( 0x%x ) : sessn is lost , discard it ( 0x%p ) ... "); +270336,553814272,0,0,PLAT_AP,CCIO,SERL_INPUT_DIAG_ENT,P_WARNING,swLogPrintf("diagEnt ( 0x%x ) : data len ( %d ) overflows! "); +270336,553816064,0,0,PLAT_AP,CCIO,OPAQ_ENT_INPUT,P_WARNING,swLogPrintf("serlEnt ( 0x%x ) : unblock sct usb ep failure! "); +270336,553818368,0,0,PLAT_AP,CCIO,SERL_DEV_PWON_0,P_SIG,swLogPrintf("serv ( %d ) dev ( 0x%x ) power on! "); +270336,553822207,0,0,PLAT_AP,CCIO,SERL_DEV_PWON_1,P_WARNING,swLogPrintf("chentStatusCb is not inited? "); +270336,553822464,0,0,PLAT_AP,CCIO,SERL_DEV_PWOFF_0,P_SIG,swLogPrintf("serv ( %d ) dev ( 0x%x ) power off! "); +270336,553824256,0,0,PLAT_AP,CCIO,SET_PPP_SCT_RRCM,P_SIG,swLogPrintf("ppp latest sct rrcm is : 0x%x "); +270336,553828351,0,0,PLAT_AP,CCIO,INIT_AT_ENTITY,P_SIG,swLogPrintf("at entity has been already inited! "); +270336,553830399,0,0,PLAT_AP,CCIO,INIT_PPP_ENTITY_0,P_SIG,swLogPrintf("ppp entity already exists! "); +270336,553832447,0,0,PLAT_AP,CCIO,INIT_PPP_ENTITY_1,P_SIG,swLogPrintf("fatal error! ppp entity malloc failed! "); +270336,553833216,0,0,PLAT_AP,CCIO,SET_CHAN_MODE,P_INFO,swLogPrintf("serial ( 0x%x / %d ) chanMode : %d --> %d "); +270336,553835008,0,0,PLAT_AP,CCIO,TRY_ADJUST_DLFC_MEM_1,P_INFO,swLogPrintf("serlEnt ( 0x%x ) : ppp start @baud ( %d ) with DlfcMem ( %d ) \n "); +270336,553837056,0,0,PLAT_AP,CCIO,TRY_ADJUST_DLFC_MEM_2,P_SIG,swLogPrintf("serlEnt ( 0x%x ) : adjust Dlfc MemThres ( %d --> %d ) ! \n "); +270336,553839104,0,0,PLAT_AP,CCIO,TRY_RESTORE_DLFC_MEM_1,P_SIG,swLogPrintf("serlEnt ( 0x%x ) : restore Dlfc MemThres ( %d --> %d ) ! \n "); +270336,553840640,0,0,PLAT_AP,CCIO,usbUldpEehInit_1,P_SIG,swLogPrintf("dump outep num %d "); +270336,553842688,0,0,PLAT_AP,CCIO,eehDumpMediaPollingEp0_1,P_INFO,swLogPrintf("eehDumpMediaPollingEp0 : avoid host suspend %d "); +270336,553844736,0,0,PLAT_AP,CCIO,eehDumpMediaPollingRndisHalt_0,P_INFO,swLogPrintf("eehDumpMediaPollingRndisHalt0 : avoid host suspend %d "); +270336,553846784,0,0,PLAT_AP,CCIO,eehDumpMediaPollingRndisHalt_1,P_INFO,swLogPrintf("eehDumpMediaPollingRndisHalt1 : avoid host suspend %d "); +270336,553850879,0,0,PLAT_AP,CCIO,INIT_CUST_TXTASK,P_INFO,swLogPrintf("create cust Tx task... "); +270336,553852927,0,0,PLAT_AP,CCIO,DEINIT_CUST_TXTASK,P_INFO,swLogPrintf("destroy cust Tx task... "); +270336,553852928,0,0,PLAT_AP,CCIO,SENDTO_CUST_TXTASK,P_INFO,swLogPrintf("send msg ( 0x%x ) to cust Tx task... "); +270336,553854976,0,0,PLAT_AP,CCIO,USBD_EXEC_CUST_INSTR_1,P_INFO,swLogPrintf("recv usb cust instr ( 0x%x ) ! "); +270336,553857024,0,0,PLAT_AP,CCIO,USBD_EXEC_CUST_INSTR_2,P_ERROR,swLogPrintf("warning! unknown usb exec cust instr ( 0x%x ) ! "); +270336,553859072,0,0,PLAT_AP,CCIO,UARTD_EXEC_CUST_INSTR_1,P_INFO,swLogPrintf("recv uart cust instr ( 0x%x ) ! "); +270336,553861120,0,0,PLAT_AP,CCIO,UARTD_EXEC_CUST_INSTR_2,P_ERROR,swLogPrintf("warning! unknown uart exec cust instr ( 0x%x ) ! "); +270336,553863168,0,0,PLAT_AP,CCIO,RADIOD_EXEC_CUST_INSTR_1,P_INFO,swLogPrintf("recv radio cust instr ( 0x%x ) ! "); +270336,553865216,0,0,PLAT_AP,CCIO,RADIOD_EXEC_CUST_INSTR_2,P_ERROR,swLogPrintf("warning! unknown radio exec cust instr ( 0x%x ) ! "); +270336,553867264,0,0,PLAT_AP,CCIO,HANDLE_CUST_DEV_STATUS_1,P_INFO,swLogPrintf("handle cust DS ( 0x%x ) ! "); +270336,553869312,0,0,PLAT_AP,CCIO,HANDLE_CUST_DEV_STATUS_2,P_SIG,swLogPrintf("err! unknown cust dsFlags ( 0x%x ) ! "); +270336,553871360,0,0,PLAT_AP,CCIO,HANDLE_CUST_ENT_STATUS_1,P_INFO,swLogPrintf("handle cust ES ( 0x%x ) ! "); +270336,553873408,0,0,PLAT_AP,CCIO,HANDLE_CUST_ENT_STATUS_2,P_SIG,swLogPrintf("err! unknown cust esFlags ( 0x%x ) ! "); +270336,553875456,0,0,PLAT_AP,CCIO,HANDLE_CUST_CHAN_MSG_1,P_INFO,swLogPrintf("handle cust chanMsg ( 0x%x ) ! "); +270336,553878016,0,0,PLAT_AP,CCIO,HANDLE_DEV_ADD_0,P_SIG,swLogPrintf("device ( %d / %d / %d ) is added! "); +270336,553879552,0,0,PLAT_AP,CCIO,HANDLE_DEV_ADD_1,P_ERROR,swLogPrintf("undef device type ( %d ) ! "); +270336,553882368,0,0,PLAT_AP,CCIO,HANDLE_DEV_DEL_0,P_SIG,swLogPrintf("device ( 0x%x : %d / %d / %d ) is deleted! "); +270336,553883904,0,0,PLAT_AP,CCIO,HANDLE_RBUF_FLUSH,P_WARNING,swLogPrintf("device ( 0x%x ) : flush rbuf for flag ( 0x%x ) ... "); +270336,553886208,0,0,PLAT_AP,CCIO,HANDLE_CTS_CHG_1,P_WARNING,swLogPrintf("device ( 0x%x ) : ignore cts ( %d ) by hwType ( %d ) "); +270336,553887744,0,0,PLAT_AP,CCIO,HANDLE_DTR_CHG_2,P_SIG,swLogPrintf("pppEnt ( 0x%x ) : recv dtr @AT&D1 "); +270336,553889792,0,0,PLAT_AP,CCIO,HANDLE_DTR_CHG_3,P_SIG,swLogPrintf("pppEnt ( 0x%x ) : recv dtr @AT&D2 "); +270336,553892352,0,0,PLAT_AP,CCIO,HANDLE_DTR_CHG_4,P_WARNING,swLogPrintf("pppEnt ( 0x%x ) : not in data mode ( %d ) or connected state ( %d ) ! "); +270336,553894144,0,0,PLAT_AP,CCIO,HANDLE_SERL_STATE_1,P_WARNING,swLogPrintf("device ( 0x%x ) : unknown serial state ( %d ) ! "); +270336,553896448,0,0,PLAT_AP,CCIO,HANDLE_AUTO_BAUD_1,P_INFO,swLogPrintf("device ( 0x%x ) detected baud : %d , config : %d "); +270336,553898753,0,0,PLAT_AP,CCIO,SET_ETHER_LAN_MEDIA,P_SIG,swLogPrintf("%s ( %d ) lan state : %d --> %d "); +270336,553902079,0,0,PLAT_AP,CCIO,ETHER_LAN_INIT,P_SIG,swLogPrintf("warining! fast path is not avail! "); +270336,553902593,0,0,PLAT_AP,CCIO,HANDLE_USB_STATE,P_SIG,swLogPrintf("usb is %s ( %d / %d ) for i / o! "); +270336,553906175,0,0,PLAT_AP,CCIO,HANDLE_SCT_TXDONE,P_WARNING,swLogPrintf("warning! sct is still not avail!!! "); +270336,553908223,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_1,P_SIG,swLogPrintf("ppp_sessn_status : Connected! \n "); +270336,553910271,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_8,P_ERROR,swLogPrintf("ppp_sessn_status : Invalid parameter \n "); +270336,553912319,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_9,P_ERROR,swLogPrintf("ppp_sessn_status : Unable to open PPP session \n "); +270336,553914367,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_10,P_ERROR,swLogPrintf("ppp_sessn_status : Invalid I / O device for PPP \n "); +270336,553916415,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_11,P_ERROR,swLogPrintf("ppp_sessn_status : Unable to allocate resources \n "); +270336,553918463,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_12,P_WARNING,swLogPrintf("ppp_sessn_status : User interrupt \n "); +270336,553920511,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_13,P_WARNING,swLogPrintf("ppp_sessn_status : Connection lost \n "); +270336,553922559,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_14,P_ERROR,swLogPrintf("ppp_sessn_status : Failed authentication challenge \n "); +270336,553924607,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_15,P_ERROR,swLogPrintf("ppp_sessn_status : Failed to meet protocol \n "); +270336,553926655,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_16,P_ERROR,swLogPrintf("ppp_sessn_status : Connection timeout \n "); +270336,553928703,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_17,P_ERROR,swLogPrintf("ppp_sessn_status : Idle Timeout \n "); +270336,553930751,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_18,P_ERROR,swLogPrintf("ppp_sessn_status : Max connect time reached \n "); +270336,553932799,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_19,P_ERROR,swLogPrintf("ppp_sessn_status : Loopback detected \n "); +270336,553932800,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_21,P_SIG,swLogPrintf("ppp_sessn_status : act network ( 0x%x ) ... \n "); +270336,553934848,0,0,PLAT_AP,CCIO,NOTIFY_PPP_STATUS_22,P_ERROR,swLogPrintf("ppp_sessn_status : Unknown error code %d \n "); +270336,553938184,0,0,PLAT_AP,CCIO,HANDLE_WAN_NOTIF_1,P_SIG,swLogPrintf("handle wan ( 0x%x , 0x%x ) / %d notif to %s @lanstate ( e%d , p%d ) "); +270336,553939712,0,0,PLAT_AP,CCIO,HANDLE_WAN_NOTIF_2,P_WARNING,swLogPrintf("non-identical wan ( 0x%x , 0x%x ) , local ( 0x%x , 0x%x ) "); +270336,553941760,0,0,PLAT_AP,CCIO,HANDLE_WAN_NOTIF_3,P_WARNING,swLogPrintf("non-identical wan ( 0x%x , 0x%x ) , local ( 0x%x , 0x%x ) "); +270336,553943040,0,0,PLAT_AP,CCIO,HANDLE_PPP_START_4,P_WARNING,swLogPrintf("atCid ( %d ) : ppp sessn is disabled!!! "); +270336,553945088,0,0,PLAT_AP,CCIO,HANDLE_PPP_STOP_1,P_WARNING,swLogPrintf("atCid ( %d ) : ppp sessn is disabled!!! "); +270336,553949183,0,0,PLAT_AP,CCIO,HANDLE_RBUF_EBNA,P_SIG,swLogPrintf("warning! recv rbuf bna message... "); +270336,553951231,0,0,PLAT_AP,CCIO,HANDLE_USB_ESTATUS,P_SIG,swLogPrintf("warning! recv usb status err message... "); +270336,553953279,0,0,PLAT_AP,CCIO,HANDLE_AHB_EADDR,P_SIG,swLogPrintf("warning! recv ahb addr err message... "); +270336,553953280,0,0,PLAT_AP,CCIO,HANDLE_CMSG_0,P_SIG,swLogPrintf("err! unknown msgId ( 0x%x ) ! "); +270336,553955328,0,0,PLAT_AP,CCIO,HANDLE_CMSG_1,P_SIG,swLogPrintf("err! unsupported msgId ( 0x%x ) ! "); +270336,553957376,0,0,PLAT_AP,CCIO,HANDLE_CMSG_2,P_SIG,swLogPrintf("err! unmatched msgId ( 0x%x ) ! "); +270336,553959681,0,0,PLAT_AP,CCIO,HANDLE_CMSG_3,P_INFO,swLogPrintf("handle chan message ( %s : 0x%x ) ... "); +270336,553961473,0,0,PLAT_AP,CCIO,INIT_CHAN_TASK_1,P_SIG,swLogPrintf("create %s task... "); +270336,553963520,0,0,PLAT_AP,CCIO,INIT_CHAN_TASK_2,P_INFO,swLogPrintf("And succ! tid ( 0x%x ) "); +270336,553965568,0,0,PLAT_AP,CCIO,DEINIT_CHAN_TASK_1,P_SIG,swLogPrintf("tid ( 0x%x ) terminated succ! "); +270336,553969663,0,0,PLAT_AP,CCIO,SEND_TO_RXTASK_0,P_WARNING,swLogPrintf("CcioRxTask is not running! "); +270336,553969920,0,0,PLAT_AP,CCIO,SEND_TO_RXTASK_1,P_INFO,swLogPrintf("send message ( 0x%x ) to Rx ( %d ) task! "); +270336,553971713,0,0,PLAT_AP,CCIO,SEND_TO_TXTASK_0,P_WARNING,swLogPrintf("%s is not running yet! "); +270336,553974016,0,0,PLAT_AP,CCIO,SEND_TO_TXTASK_1,P_WARNING,swLogPrintf("discard Tx ( %d ) message ( 0x%x ) ! "); +270336,553976064,0,0,PLAT_AP,CCIO,SEND_TO_TXTASK_2,P_INFO,swLogPrintf("send message ( 0x%x ) to Tx ( %d ) task! "); +270336,553979903,0,0,PLAT_AP,CCIO,CHAN_RX_TASK_1,P_SIG,swLogPrintf("rx msgq ( 1 ) is pending!!! "); +270336,553981951,0,0,PLAT_AP,CCIO,CHAN_RX_TASK_2,P_SIG,swLogPrintf("rx msgq ( 2 ) is pending!!! "); +270336,553982208,0,0,PLAT_AP,CCIO,WAIT_TX_CMPLT,P_INFO,swLogPrintf("device ( 0x%x ) : waiting for txHandle ( %d ) ... "); +270336,553984256,0,0,PLAT_AP,CCIO,SET_TX_CMPLT,P_INFO,swLogPrintf("device ( 0x%x ) : set txHandle ( %d ) done! "); +270336,553986048,0,0,PLAT_AP,CCIO,SET_WAN_ENT,P_INFO,swLogPrintf("set wan entity ( %d ) "); +270336,553988096,0,0,PLAT_AP,CCIO,UNSET_WAN_ENT,P_INFO,swLogPrintf("unset wan entity ( %d ) "); +270336,553990400,0,0,PLAT_AP,CCIO,SET_LAN_ENT_1,P_INFO,swLogPrintf("set lan ( %d ) entity ( 0x%x ) "); +270336,553992448,0,0,PLAT_AP,CCIO,SET_LAN_ENT_2,P_SIG,swLogPrintf("rndisEnt ( %p ) already exists! lanEntType ( 0x%x ) "); +270336,553994496,0,0,PLAT_AP,CCIO,SET_LAN_ENT_3,P_SIG,swLogPrintf("ecmEnt ( %p ) already exists! lanEntType ( 0x%x ) "); +270336,553996544,0,0,PLAT_AP,CCIO,SET_LAN_ENT_4,P_SIG,swLogPrintf("pppEnt ( %p ) already exists! lanEntType ( 0x%x ) "); +270336,553998336,0,0,PLAT_AP,CCIO,UNSET_LAN_ENT_1,P_INFO,swLogPrintf("unset lan ( %d ) entity "); +270336,554000640,0,0,PLAT_AP,CCIO,SET_DIAG_ENT,P_INFO,swLogPrintf("set diagEnt ( 0x%x ) , latest rdcm ( 0x%x ) "); +270336,554002688,0,0,PLAT_AP,CCIO,UNSET_DIAG_ENT,P_INFO,swLogPrintf("unset diagEnt ( 0x%x ) , latest rdcm ( 0x%x ) "); +270336,554004737,0,0,PLAT_AP,CCIO,SET_RXSYNC_FLAG,P_SIG,swLogPrintf("set Rx sync flag : %s ( %d ) "); +270336,554006785,0,0,PLAT_AP,CCIO,GET_RXSYNC_FLAG,P_SIG,swLogPrintf("get Rx sync flag : %s ( %d ) "); +270336,554008576,0,0,PLAT_AP,CCIO,SETUP_CHANS_1,P_SIG,swLogPrintf("err! invalid chanType ( %d ) ! "); +270336,554010624,0,0,PLAT_AP,CCIO,SETUP_CHANS_2,P_INFO,swLogPrintf("set up channel ( %d ) ... "); +270336,554012672,0,0,PLAT_AP,CCIO,PULLDOWN_CHANS_1,P_SIG,swLogPrintf("err! invalid chanType ( %d ) ! "); +270336,554014720,0,0,PLAT_AP,CCIO,PULLDOWN_CHANS_2,P_INFO,swLogPrintf("pull down channel ( %d ) ... "); +270336,554016768,0,0,PLAT_AP,CCIO,HANDLE_DEV_STATUS_1,P_INFO,swLogPrintf("handle DS ( 0x%x ) ! "); +270336,554018816,0,0,PLAT_AP,CCIO,HANDLE_DEV_STATUS_2,P_SIG,swLogPrintf("err! unknown dsFlags ( 0x%x ) ! "); +270336,554020864,0,0,PLAT_AP,CCIO,HANDLE_ENT_STATUS_1,P_INFO,swLogPrintf("handle ES ( 0x%x ) ! "); +270336,554022912,0,0,PLAT_AP,CCIO,HANDLE_ENT_STATUS_2,P_SIG,swLogPrintf("err! unknown esFlags ( 0x%x ) ! "); +270336,554025217,0,0,PLAT_AP,CCIO,IS_ULDP_PPP_AVLB,P_SIG,swLogPrintf("uldp ppp scheme %s avail ( %d ) "); +270336,554027520,0,0,PLAT_AP,CCIO,CHG_PMU_TIMING_CB,P_INFO,swLogPrintf("Slp Urc Report = %d , %d , %d "); +270336,554031103,0,0,PLAT_AP,CCIO,INIT_ETHER_PROVIDER_3,P_SIG,swLogPrintf("ether is disabled! "); +270336,554033151,0,0,PLAT_AP,CCIO,DEINIT_ETHER_PROVIDER_3,P_SIG,swLogPrintf("ether is disabled! "); +270336,554033408,0,0,PLAT_AP,CCIO,INIT_AT_PROVIDER_1,P_WARNING,swLogPrintf("AT provider ( %p / %d ) has already been inited! "); +270336,554037247,0,0,PLAT_AP,CCIO,INIT_AT_PROVIDER_2,P_WARNING,swLogPrintf("warning! no more available AT providers! "); +270336,554037249,0,0,PLAT_AP,CCIO,DEINIT_AT_PROVIDER,P_WARNING,swLogPrintf("%s provider is not inited! "); +270336,554039808,0,0,PLAT_AP,CCIO,INIT_DIAG_PROVIDER_1,P_WARNING,swLogPrintf("unilog [ %d ] provider ( %p / %d ) has already been inited! "); +270336,554041344,0,0,PLAT_AP,CCIO,INIT_DIAG_PROVIDER_2,P_ERROR,swLogPrintf("unilog [ %d ] provider init failure! "); +270336,554043904,0,0,PLAT_AP,CCIO,DEINIT_DIAG_PROVIDER_1,P_WARNING,swLogPrintf("unilog ( %d ) provider ( %p / %d ) is not inited! "); +270336,554045696,0,0,PLAT_AP,CCIO,INIT_OPAQ_PROVIDER_1,P_WARNING,swLogPrintf("opaq provider ( %p / %d ) has already been inited! "); +270336,554049535,0,0,PLAT_AP,CCIO,INIT_OPAQ_PROVIDER_2,P_WARNING,swLogPrintf("warning! no more available opaq providers! "); +270336,554051583,0,0,PLAT_AP,CCIO,INIT_OPAQ_PROVIDER_3,P_ERROR,swLogPrintf("opaq provider init failure! "); +270336,554053631,0,0,PLAT_AP,CCIO,DEINIT_OPAQ_PROVIDER_1,P_WARNING,swLogPrintf("opaq provider is not inited! "); +270336,554053888,0,0,PLAT_AP,CCIO,INIT_EUTRA_PROVIDER_1,P_WARNING,swLogPrintf("eutra provider ( %p / %d ) has already been inited! "); +270336,554057727,0,0,PLAT_AP,CCIO,INIT_EUTRA_PROVIDER_2,P_INFO,swLogPrintf("eutra provider init failure! "); +270336,554057984,0,0,PLAT_AP,CCIO,DEINIT_EUTRA_PROVIDER_1,P_WARNING,swLogPrintf("eutra provider ( %p / %d ) is not inited! "); +270336,554059776,0,0,PLAT_AP,CCIO,RADIOD_EXEC_INSTR_1,P_INFO,swLogPrintf("recv radio instr ( 0x%x ) ! "); +270336,554061824,0,0,PLAT_AP,CCIO,RADIOD_EXEC_INSTR_2,P_ERROR,swLogPrintf("warning! unknown radio exec instr ( %d ) ! "); +270336,554065919,0,0,PLAT_AP,CCIO,RADIOD_OUTPUT,P_INFO,swLogPrintf("send radio data to ps! "); +270336,554065920,0,0,PLAT_AP,CCIO,RADIOD_CREATE_0,P_SIG,swLogPrintf("err! cid ( %d ) overflows! "); +270336,554067968,0,0,PLAT_AP,CCIO,RADIOD_CREATE_1,P_INFO,swLogPrintf("create radio device ( %d ) "); +270336,554070016,0,0,PLAT_AP,CCIO,RADIOD_DESTROY_0,P_SIG,swLogPrintf("err! cid ( %d ) overflows! "); +270336,554072064,0,0,PLAT_AP,CCIO,RADIOD_DESTROY_1,P_INFO,swLogPrintf("destroy radio device ( %d ) "); +270336,554076159,0,0,PLAT_AP,CCIO,RADIOD_NOTIFY_DPC_0,P_SIG,swLogPrintf("warning! radio device is not working! "); +270336,554076928,0,0,PLAT_AP,CCIO,RADIOD_NOTIFY_DPC_2,P_SIG,swLogPrintf("notify fastpath ( 0x%x , 0x%x ) media ( %d ) state ( %d ) "); +270336,554080255,0,0,PLAT_AP,CCIO,RADIOD_NOTIFY_DPC_3,P_SIG,swLogPrintf("err! notify fastpath media state failure! "); +270336,554081032,0,0,PLAT_AP,CCIO,RADIOD_QUERY_WAN_MEDIA,P_INFO,swLogPrintf("fastpath ( 0x%x , 0x%x ) media ( %d ) state is %s! "); +270336,554082304,0,0,PLAT_AP,CCIO,RADIOD_LAN_LINK_CHG,P_ERROR,swLogPrintf("notify change of lan ( %d ) status failure! "); +270336,554084608,0,0,PLAT_AP,CCIO,RADIOD_LAN_LINK_UP,P_ERROR,swLogPrintf("notify lan ( %d / %d ) linkup failure! "); +270336,554086656,0,0,PLAT_AP,CCIO,RADIOD_LAN_LINK_DOWN,P_ERROR,swLogPrintf("notify lan ( %d / %d ) linkdown failure! "); +270336,554089472,0,0,PLAT_AP,CCIO,UARTD_UPDATE_XFER,P_INFO,swLogPrintf("uart ( %d ) : getRxCnt ( %d ) , curRxCnt ( %d ) @wri ( %d --> %d ) "); +270336,554092032,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_1,P_INFO,swLogPrintf("uart ( %d ) : isBusy ( %d ) , wri ( %d ) , rdi ( %d ) , avlbSize ( %d ) , mru ( %d ) , xferCnt ( %d ) "); +270336,554092544,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_2,P_INFO,swLogPrintf("uart ( %d ) : rts flow ctrl released "); +270336,554094592,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_3,P_ERROR,swLogPrintf("uart ( %d ) : enable recv failure!!! "); +270336,554096640,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_4,P_ERROR,swLogPrintf("uart ( %d ) : set new recv failure!!! "); +270336,554098688,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_5,P_ERROR,swLogPrintf("uart ( %d ) : release RTS failure!!! "); +270336,554100736,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_6,P_WARNING,swLogPrintf("uart ( %d ) : rts flow ctrl triggered "); +270336,554102784,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_7,P_ERROR,swLogPrintf("uart ( %d ) : set RTS failure!!! "); +270336,554104832,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_8,P_ERROR,swLogPrintf("uart ( %d ) : disable recv failure!!! "); +270336,554106880,0,0,PLAT_AP,CCIO,UARTD_TRG_NEXT_XFER_9,P_ERROR,swLogPrintf("uart ( %d ) : is busy!!! "); +270336,554109952,0,0,PLAT_AP,CCIO,UARTD_DUMMY_UPDATE,P_SIG,swLogPrintf("uart ( %d ) : wri ( %d --> %d ) , len ( %d ) , xferCnt ( %d ) "); +270336,554111232,0,0,PLAT_AP,CCIO,UARTD_RESET_HW_1,P_WARNING,swLogPrintf("uartd ( %d ) : power off , errno ( %d ) ! "); +270336,554113536,0,0,PLAT_AP,CCIO,UARTD_RESET_HW_2,P_WARNING,swLogPrintf("uartd ( %d ) : power on ( %d ) , errno ( %d ) ! "); +270336,554115840,0,0,PLAT_AP,CCIO,UARTD_RESET_HW_3,P_WARNING,swLogPrintf("uartd ( %d ) : ctrl setting ( %d ) / baud ( %d ) , errno ( %d ) ! "); +270336,554117888,0,0,PLAT_AP,CCIO,UARTD_RESET_HW_4,P_WARNING,swLogPrintf("uartd ( %d ) : next xfer@wri ( %d ) , dummyFreeLen ( %d ) , cfgRecvSize ( %d ) "); +270336,554119680,0,0,PLAT_AP,CCIO,UARTD_GET_RX_CONF,P_INFO,swLogPrintf("uartd ( %d ) : rxWinSize ( %d ) , xferCnt ( %d ) "); +270336,554121216,0,0,PLAT_AP,CCIO,UARTD_SET_STATIC_CONF,P_INFO,swLogPrintf("uartd ( %d ) : pre-rx is running... "); +270336,554123264,0,0,PLAT_AP,CCIO,UARTD_EXEC_INSTR_1,P_INFO,swLogPrintf("recv uart instr ( 0x%x ) ! "); +270336,554125312,0,0,PLAT_AP,CCIO,UARTD_EXEC_INSTR_2,P_ERROR,swLogPrintf("warning! unknown uart exec instr ( 0x%x ) ! "); +270336,554127360,0,0,PLAT_AP,CCIO,UARTD_INPUT_0,P_SIG,swLogPrintf("err! uartIdx ( %d ) overflows! "); +270336,554129664,0,0,PLAT_AP,CCIO,UARTD_INPUT_1,P_ERROR,swLogPrintf("uartd ( %d ) : NOT in working state ( %d ) ! "); +270336,554131712,0,0,PLAT_AP,CCIO,UARTD_INPUT_2,P_SIG,swLogPrintf("uartd ( %d ) : err event ( 0x%x ) "); +270336,554133760,0,0,PLAT_AP,CCIO,UARTD_OUTPUT,P_INFO,swLogPrintf("uartd ( %d ) : %d bytes out "); +270336,554135552,0,0,PLAT_AP,CCIO,UARTD_CREATE_0,P_SIG,swLogPrintf("err! uartIdx ( %d ) overflows! "); +270336,554137600,0,0,PLAT_AP,CCIO,UARTD_CREATE_1,P_INFO,swLogPrintf("create uart device ( %d ) "); +270336,554139648,0,0,PLAT_AP,CCIO,UARTD_CREATE_2,P_WARNING,swLogPrintf("uartd ( %d ) : set pre-rx not ok? "); +270336,554141696,0,0,PLAT_AP,CCIO,UARTD_CREATE_3,P_WARNING,swLogPrintf("uartd ( %d ) : no pre-get rx addr? "); +270336,554143744,0,0,PLAT_AP,CCIO,UARTD_CREATE_4,P_WARNING,swLogPrintf("uartd ( %d ) : chdevStatusCb is null? "); +270336,554145792,0,0,PLAT_AP,CCIO,UARTD_DESTROY_0,P_SIG,swLogPrintf("err! uartIdx ( %d ) overflows! "); +270336,554147840,0,0,PLAT_AP,CCIO,UARTD_DESTROY_1,P_INFO,swLogPrintf("destroy uart device ( %d ) "); +270336,554149888,0,0,PLAT_AP,CCIO,UARTD_DESTROY_2,P_WARNING,swLogPrintf("uartd ( %d ) : chdevStatusCb is null? "); +270336,554151936,0,0,PLAT_AP,CCIO,USBD_NOTIFY_STATE_1,P_SIG,swLogPrintf("usbd : notify isr state ( %d ) ! "); +270336,554156031,0,0,PLAT_AP,CCIO,USBD_NOTIFY_STATE_2,P_WARNING,swLogPrintf("no usb device agent? "); +270336,554156032,0,0,PLAT_AP,CCIO,USBD_DISABLE_RTS,P_SIG,swLogPrintf("usbd ( %d ) : rts flow ctrl triggered! "); +270336,554158080,0,0,PLAT_AP,CCIO,USBD_ENABLE_RTS,P_SIG,swLogPrintf("usbd ( %d ) : rts flow ctrl released! "); +270336,554160896,0,0,PLAT_AP,CCIO,USBD_HAS_OBZP,P_SIG,swLogPrintf("xferCnt ( %d ) , wri ( %d ) , magic ( 0x%x ) , obzp ( %d ) "); +270336,554163712,0,0,PLAT_AP,CCIO,USBD_UPDATE_XFER,P_INFO,swLogPrintf("usbd ( %d ) : xferCnt ( %d / %d / %d ) @wri ( +%d|%d --> %d ) "); +270336,554164992,0,0,PLAT_AP,CCIO,USBD_NEXT_XFER_1,P_INFO,swLogPrintf("usbd ( %d ) : avlbSize ( %d ) < avlbThres ( %d / %d ) ! waiting more... "); +270336,554167552,0,0,PLAT_AP,CCIO,USBD_NEXT_XFER_2,P_INFO,swLogPrintf("usbd ( %d ) : next xfer @N.WR ( +%d|%d ) / N.RD ( %d ) / A.SZ ( %d ) / G.T.E ( %d ) "); +270336,554168832,0,0,PLAT_AP,CCIO,USBD_GET_RX_CONF,P_INFO,swLogPrintf("usbd ( %d ) : rxWinSize ( %d ) , xferCnt ( %d ) "); +270336,554170624,0,0,PLAT_AP,CCIO,USBD_ETH_MEDIA_STATE_1,P_SIG,swLogPrintf("rndis media state ( %d ) ind , errno ( %d ) ! "); +270336,554172672,0,0,PLAT_AP,CCIO,USBD_ETH_MEDIA_STATE_2,P_SIG,swLogPrintf("ecm media state ( %d ) ind , errno ( %d ) ! "); +270336,554174720,0,0,PLAT_AP,CCIO,USBD_ETH_MEDIA_STATE_3,P_ERROR,swLogPrintf("error! eth media ( %d ) state ( %d ) ind timeout ( 10 s ) ! "); +270336,554176768,0,0,PLAT_AP,CCIO,USBD_DCD_STATUS,P_SIG,swLogPrintf("usbd ( %d ) : set serl dcd state ( 0x%x ) ! "); +270336,554178560,0,0,PLAT_AP,CCIO,USBD_RI_DONE,P_SIG,swLogPrintf("usbd ( %d ) : ri done! "); +270336,554181376,0,0,PLAT_AP,CCIO,USBD_RI_STATUS_1,P_SIG,swLogPrintf("usbd ( %d ) : set serl ri state ( %d * %d / %d%% ) "); +270336,554182656,0,0,PLAT_AP,CCIO,USBD_RI_STATUS_2,P_SIG,swLogPrintf("usbd ( %d ) : restore high level "); +270336,554184704,0,0,PLAT_AP,CCIO,USBD_RI_STATUS_3,P_ERROR,swLogPrintf("usbd ( %d ) : create ri timer error! "); +270336,554186752,0,0,PLAT_AP,CCIO,USBD_RI_STATUS_4,P_WARNING,swLogPrintf("usbd ( %d ) : ri cycleCnt > 15 !!! "); +270336,554188800,0,0,PLAT_AP,CCIO,USBD_EXEC_INSTR_1,P_INFO,swLogPrintf("recv usb instr ( 0x%x ) ! "); +270336,554190848,0,0,PLAT_AP,CCIO,USBD_EXEC_INSTR_2,P_ERROR,swLogPrintf("warning! unknown usb exec instr ( 0x%x ) ! "); +270336,554193152,0,0,PLAT_AP,CCIO,USBD_OUTPUT_0,P_WARNING,swLogPrintf("usbd ( %d ) : disabled! discard all dlpdu ( 0x%x ) ... "); +270336,554195200,0,0,PLAT_AP,CCIO,USBD_OUTPUT_3,P_ERROR,swLogPrintf("usbd ( %d ) : sct tx err ( %d ) ! discard all pending dlpdu... "); +270336,554197248,0,0,PLAT_AP,CCIO,USBD_OUTPUT_SIGNAL_1,P_ERROR,swLogPrintf("ifIdx ( %d ) is out of scope [ 0 , %d ) ! "); +270336,554199296,0,0,PLAT_AP,CCIO,USBD_OUTPUT_SIGNAL_2,P_ERROR,swLogPrintf("usbd ( %d ) : output pstn serl state failure ( %d ) ! "); +270336,554201600,0,0,PLAT_AP,CCIO,USBD_CTS_EVT_1,P_INFO,swLogPrintf("usbd ( %d ) : cts state ( %d ) @epNum ( %d ) "); +270336,554203648,0,0,PLAT_AP,CCIO,USBD_CTS_EVT_2,P_SIG,swLogPrintf("usbd ( %d ) : cts state ( %d --> %d ) "); +270336,554205440,0,0,PLAT_AP,CCIO,USBD_DTR_EVT_1,P_INFO,swLogPrintf("usbd ( %d ) : dtr state ( %d ) "); +270336,554207744,0,0,PLAT_AP,CCIO,USBD_DTR_EVT_2,P_SIG,swLogPrintf("usbd ( %d ) : dtr state ( %d --> %d ) "); +270336,554209792,0,0,PLAT_AP,CCIO,USBD_CFG_OUT_XFER_0,P_INFO,swLogPrintf("usbd ( %d ) : cfg xfer , type : %d , size : %d! "); +270336,554211584,0,0,PLAT_AP,CCIO,USBD_CFG_OUT_XFER_1,P_SIG,swLogPrintf("usbd ( %d ) : err! cfg next xfer fail , ret = %d "); +270336,554213376,0,0,PLAT_AP,CCIO,USBD_CREATE_0,P_SIG,swLogPrintf("err! usbIfIdx ( %d ) overflows! "); +270336,554215424,0,0,PLAT_AP,CCIO,USBD_CREATE_1,P_INFO,swLogPrintf("create usb device ( %d ) "); +270336,554217472,0,0,PLAT_AP,CCIO,USBD_CREATE_2,P_SIG,swLogPrintf("usbd ( %d ) : serve as an agent... "); +270336,554219520,0,0,PLAT_AP,CCIO,USBD_DESTROY_0,P_SIG,swLogPrintf("err! usbIfIdx ( %d ) overflows! "); +270336,554221568,0,0,PLAT_AP,CCIO,USBD_DESTROY_1,P_INFO,swLogPrintf("destroy usb device ( %d ) "); +270336,554223616,0,0,PLAT_AP,CCIO,USBD_DESTROY_2,P_SIG,swLogPrintf("usbd ( %d ) : no more serve as an agent... "); +270336,554225664,0,0,PLAT_AP,CCIO,USBD_DESTROY_3,P_SIG,swLogPrintf("usbd ( %d ) : serve as a new agent... "); +270336,554227712,0,0,PLAT_AP,CCIO,USBD_INPUT_0,P_SIG,swLogPrintf("usbd ( %d ) : err! idx overflows! "); +270336,554230272,0,0,PLAT_AP,CCIO,USBD_INPUT_1,P_WARNING,swLogPrintf("usbd ( %d ) : not in working state ( %d ) or not enabled ( %d ) ! "); +270336,554231808,0,0,PLAT_AP,CCIO,USBD_INPUT_2,P_SIG,swLogPrintf("usbd ( %d ) : special pattern ( +++ ) ! "); +270336,554233856,0,0,PLAT_AP,CCIO,USBD_ECM_EVT,P_SIG,swLogPrintf("usb recv ecm event ( 0x%x ) ! "); +270336,554235904,0,0,PLAT_AP,CCIO,USBD_RNDIS_EVT,P_SIG,swLogPrintf("usb recv rndis event ( 0x%x ) ! "); +270336,554238208,0,0,PLAT_AP,CCIO,USBD_SERL_EVT_1,P_INFO,swLogPrintf("usbd ( %d ) : serl request set-line-state ( 0x%x ) ! "); +270336,554240000,0,0,PLAT_AP,CCIO,USBD_SERL_EVT_2,P_ERROR,swLogPrintf("usbd ( %d ) : err! idx overflows! "); +270336,554242304,0,0,PLAT_AP,CCIO,USBD_SCT_TX_DONE_1,P_INFO,swLogPrintf("usb Tx done ( %d ) notif to sct , triggFlag ( %d ) ! "); +270336,554246143,0,0,PLAT_AP,CCIO,USBD_SCT_TX_DONE_2,P_WARNING,swLogPrintf("no usb device agent? "); +270336,554246144,0,0,PLAT_AP,CCIO,USBD_STATE_TO_SCT_1,P_INFO,swLogPrintf("usb state ( %d ) notif to sct! "); +270336,554250239,0,0,PLAT_AP,CCIO,USBD_STATE_TO_SCT_2,P_WARNING,swLogPrintf("no usb device agent? "); +270336,554250240,0,0,PLAT_AP,CCIO,USBD_T_EXPIRY_TO_SCT_1,P_INFO,swLogPrintf("usb timer expiry ( %d ) notif to sct! "); +270336,554254335,0,0,PLAT_AP,CCIO,USBD_T_EXPIRY_TO_SCT_2,P_WARNING,swLogPrintf("no usb device agent? "); +270336,554254336,0,0,PLAT_AP,CCIO,USBD_EP_UNBLOCK_TO_SCT_1,P_INFO,swLogPrintf("usb EP unblock ( %d ) notif to sct! "); +270336,554258431,0,0,PLAT_AP,CCIO,USBD_EP_UNBLOCK_TO_SCT_2,P_WARNING,swLogPrintf("no usb device agent? "); +270336,554259200,0,0,PLAT_AP,CCIO,USBD_TABLE_INIT_0,P_VALUE,swLogPrintf("elem_idx ( %d ) : cls_type ( %d ) , inep ( %d ) , outep ( %d ) ! "); +270336,554261506,0,0,PLAT_AP,CCIO,USBD_TABLE_INIT_1,P_VALUE,swLogPrintf("usbd ( %d ) : %s ( %d ) , inep ( %d ) , outep ( %d ) ! "); +270336,554263808,0,0,PLAT_AP,CCIO,USBD_TABLE_INIT_2,P_VALUE,swLogPrintf("type2If ( %d %d %d %d %d ) , ulgInepNum ( %d ) ! "); +270336,554264576,0,0,PLAT_AP,CCIO,usbDevGetEnumSpd_1,P_VALUE,swLogPrintf("current enum speed is 0x%x! "); +270336,554266624,0,0,PLAT_AP,CCIO,ATCMD_ADD_ENT_1,P_SIG,swLogPrintf("AtCmdEntity ( %d ) is already added to the list!! "); +270336,554268672,0,0,PLAT_AP,CCIO,ATCMD_DEL_ENT_1,P_SIG,swLogPrintf("AtCmdEntity ( %d ) is not found in the list!! "); +270336,554270720,0,0,PLAT_AP,CCIO,ATCMD_GET_ENT_0,P_ERROR,swLogPrintf("atCid ( %d ) : not entity exist! "); +270336,554273024,0,0,PLAT_AP,CCIO,ATCMD_ACTIVATE_CTX,P_SIG,swLogPrintf("serlEnt ( 0x%x ) : atCid ( %d ) is activated! "); +270336,554275072,0,0,PLAT_AP,CCIO,ATCMD_DEACTIVATE_CTX,P_SIG,swLogPrintf("serlEnt ( %d ) : atCid ( %d ) is deactivated! "); +270336,554276864,0,0,PLAT_AP,CCIO,ATCMD_GET_CHANNO_1,P_ERROR,swLogPrintf("atCid ( %d ) : invalid atCid! "); +270336,554278912,0,0,PLAT_AP,CCIO,ATCMD_GET_CHANNO_2,P_ERROR,swLogPrintf("atCid ( %d ) : atCmd entity is unregistered! "); +270336,554281728,0,0,PLAT_AP,CCIO,ATCMD_OUTPUT_DLPDU_EX_1,P_ERROR,swLogPrintf("device ( %d / %d / %d / %d ) does not exist!!! "); +270336,554283776,0,0,PLAT_AP,CCIO,ATCMD_OUTPUT_DLPDU_EX_2,P_ERROR,swLogPrintf("device ( %d / %d / %d / %d ) is not assigned!!! "); +270336,554285057,0,0,PLAT_AP,CCIO,ATCMD_BCAST_OUTPUT,P_SIG,swLogPrintf("urc : bcast ' %s ' out... "); +270336,554287880,0,0,PLAT_AP,CCIO,ATCMD_GET_PEND,P_INFO,swLogPrintf("atCid ( %d / 0x%x ) : %d %s line ( s ) in total... "); +270336,554289664,0,0,PLAT_AP,CCIO,ATCMD_START_PPP_1,P_WARNING,swLogPrintf("atCid ( %d ) : both pdpCid ( %d , %d ) invalid! "); +270336,554291200,0,0,PLAT_AP,CCIO,ATCMD_START_PPP_2,P_WARNING,swLogPrintf("atCid ( %d ) : ppp sessn already running! "); +270336,554293760,0,0,PLAT_AP,CCIO,ATCMD_START_PPP_3,P_WARNING,swLogPrintf("atCid ( %d ) : diff pdpCid ( %d , %d ) ! correct it! "); +270336,554295296,0,0,PLAT_AP,CCIO,ATCMD_STOP_PPP,P_WARNING,swLogPrintf("atCid ( %d ) : no ppp sessn running! maybe deleted... "); +270336,554297344,0,0,PLAT_AP,CCIO,ATCMD_RESUME_PPP,P_WARNING,swLogPrintf("atCid ( %d ) : no ppp sessn running! "); +270336,554299648,0,0,PLAT_AP,CCIO,ATCMD_OUTPUT_DLPDU,P_WARNING,swLogPrintf("atCid ( %d / 0x%x ) : txDelay flag has been set! "); +270336,554301698,0,0,PLAT_AP,CCIO,ATCMD_OUTPUT_2,P_ERROR,swLogPrintf("atCid ( %d ) : discard ' %s ' for unregistration! "); +270336,554303744,0,0,PLAT_AP,CCIO,ATCMD_OUTPUT_3,P_ERROR,swLogPrintf("atCid ( %d ) : dlpdu count ( %d ) overflows!! "); +270336,554305536,0,0,PLAT_AP,CCIO,ATCMD_OUTPUT_4,P_ERROR,swLogPrintf("malloc dlpdu ( %d bytes ) failure! "); +270336,554308608,0,0,PLAT_AP,CCIO,ETH_HAS_OBZP,P_SIG,swLogPrintf("xferCnt ( %d / %d ) , magic ( 0x%x ) , obzp ( %d ) @ulpdu ( 0x%x ) "); +270336,554309889,0,0,PLAT_AP,CCIO,ETH_DATA_INPUT,P_INFO,swLogPrintf("%s ( %d ) ulpdu fast input... "); +270336,554311937,0,0,PLAT_AP,CCIO,ETH_DATA_OUTPUT,P_INFO,swLogPrintf("%s ( %d ) dlpdu output... "); +270336,554313985,0,0,PLAT_AP,CCIO,ETH_DATA_FAST_OUTPUT,P_INFO,swLogPrintf("%s ( %d ) dlpdu fast output... "); +270336,554317823,0,0,PLAT_AP,CCIO,PPP_DATA_OUTPUT_1,P_INFO,swLogPrintf("ppp dlpdu output... "); +270336,554317824,0,0,PLAT_AP,CCIO,PPP_DATA_OUTPUT_2,P_WARNING,swLogPrintf("pppEnt ( 0x%p ) : maybe deleted or not ready , discard... "); +270336,554320128,0,0,PLAT_AP,CCIO,PPP_DATA_FAST_OUTPUT_1,P_WARNING,swLogPrintf("pppEnt ( 0x%p ) : maybe deleted or not ready ( %d ) , discard... "); +270336,554321920,0,0,PLAT_AP,CCIO,PPP_DATA_FAST_OUTPUT_2,P_WARNING,swLogPrintf("pppEnt ( 0x%x ) : txDelay flag has been set! "); +270336,554326015,0,0,PLAT_AP,CCIO,NET_DATA_INPUT,P_INFO,swLogPrintf("ppp ulpdu fast input... "); +270336,554328063,0,0,PLAT_AP,CCIO,NET_DATA_OUTPUT,P_INFO,swLogPrintf("ppp dlpdu output... "); +270336,554330111,0,0,PLAT_AP,CCIO,NET_DATA_FAST_OUTPUT,P_INFO,swLogPrintf("ppp dlpdu fast output... "); +270336,554330112,0,0,PLAT_AP,CCIO,OPAQ_DATA_INPUT,P_INFO,swLogPrintf("chanNo ( %d ) : opaq data input... "); +270336,554332416,0,0,PLAT_AP,CCIO,OPAQ_DATA_OUTPUT,P_INFO,swLogPrintf("chanNo ( %d ) : opaq data ( %d ) output... "); +272384,557845248,0,0,PLAT_AP,ATCMD,atRfTestCmdCnf_2,P_VALUE,swLogPrintf("CmdLen = %d , CmdFlag = %d , rc = %d , chaanId = %d "); +272384,557846529,0,0,PLAT_AP,ATCMD,atRfTestCmdCnf_3,P_SIG,swLogPrintf("Regs : %s "); +272384,557848576,0,0,PLAT_AP,ATCMD,atRfTestCmdCnf_6,P_SIG,swLogPrintf("SarAdc 1 st : 0x%x "); +272384,557850625,0,0,PLAT_AP,ATCMD,atRfTestCmdCnf_4,P_SIG,swLogPrintf("duplexLoss 1 st : %s "); +272384,557854719,0,0,PLAT_AP,ATCMD,atRfTestCmdCnf_5,P_SIG,swLogPrintf("Len = 0 "); +272384,557856767,0,0,PLAT_AP,ATCMD,appTriggerTau_1,P_INFO,swLogPrintf("appTriggerTau "); +272384,557858815,0,0,PLAT_AP,ATCMD,appTriggerTau_2,P_INFO,swLogPrintf("appTriggerTau done "); +272384,557860863,0,0,PLAT_AP,ATCMD,appTriggerRel_1,P_INFO,swLogPrintf("appTriggerRel "); +272384,557862911,0,0,PLAT_AP,ATCMD,appTriggerRel_2,P_INFO,swLogPrintf("appTriggerRel done "); +272384,557864959,0,0,PLAT_AP,ATCMD,appGetWifiScanInfo_info,P_INFO,swLogPrintf("appGetWifiScanInfo api "); +272384,557865472,0,0,PLAT_AP,ATCMD,appGetWifiScanInfo_warn,P_WARNING,swLogPrintf("appGetWifiScanInfo invalid Params , maxTimeOut ( %ld ) should NOT less than round ( %d ) * scanTimeOut ( %d ) * 1000 "); +273408,559941633,0,0,PLAT_AP,ATCMD_PARSER,OperatorStringToNumericPlmn_1,P_WARNING,swLogPrintf("invalid input PLMN : %s "); +273408,559943681,0,0,PLAT_AP,ATCMD_PARSER,OperatorStringToNumericPlmn_2,P_WARNING,swLogPrintf("invalid input PLMN : %s "); +274432,562040831,0,0,PLAT_AP,ATCMD_EXEC,RfAtNstCmdPreHandle_1,P_INFO,swLogPrintf("AT+ECRFNST : crc check error "); +274432,562042879,0,0,PLAT_AP,ATCMD_EXEC,RfAtNstCmdPreHandle_2,P_INFO,swLogPrintf("AT+ECRFNST : data unfinished "); +274432,562042880,0,0,PLAT_AP,ATCMD_EXEC,RfAtNstCmdPreHandle_3,P_INFO,swLogPrintf("AT+ECRFNST : ResumeTrans , tempBlockCounter = %d "); +274432,562045184,0,0,PLAT_AP,ATCMD_EXEC,RfAtTestCmd_1,P_INFO,swLogPrintf("RC32K PTEST : aabbccdd , %x , %x "); +274432,562047488,0,0,PLAT_AP,ATCMD_EXEC,atRfNstRspInd_1,P_INFO,swLogPrintf("AT+ECRFNST : CPReturn cmdid = %d , RetV = %d , dataLen = %d "); +274432,562051071,0,0,PLAT_AP,ATCMD_EXEC,atRfNstRspInd_2,P_INFO,swLogPrintf("AT+ECRFNST : Write selfcal table "); +274432,562053119,0,0,PLAT_AP,ATCMD_EXEC,atRfNstRspInd_5,P_ERROR,swLogPrintf("apNv2Data memory malloc failure. "); +274432,562053120,0,0,PLAT_AP,ATCMD_EXEC,atRfNstRspInd_4,P_INFO,swLogPrintf("Crc Calulate and value = %d "); +274432,562057215,0,0,PLAT_AP,ATCMD_EXEC,atRfNstRspInd_3,P_INFO,swLogPrintf("AT+ECRFNST : Urc end "); +274432,562059263,0,0,PLAT_AP,ATCMD_EXEC,atRfCaliGetThermal,P_ERROR,swLogPrintf("Rf Cali Adc convert timeout "); +274432,562059776,0,0,PLAT_AP,ATCMD_EXEC,atRf32KCapCali_1,P_ERROR,swLogPrintf("32 K cali Failure , scGap = %d , fcGap = %d , rf32kCtune = 0x%X "); +274432,562061824,0,0,PLAT_AP,ATCMD_EXEC,atRf32KCapCali_3,P_SIG,swLogPrintf("32 K cali Success , scGap = %d , fcGap = %d , rf32kCtune = 0x%X "); +274432,562064128,0,0,PLAT_AP,ATCMD_EXEC,atRf32KCapCali_2,P_SIG,swLogPrintf("32 K Cali Step = %d , val1 = %d , val2 = %d , val3 = 0x%X "); +274432,562067455,0,0,PLAT_AP,ATCMD_EXEC,ResumeTrans_1,P_ERROR,swLogPrintf("AT+ECRFNST : TRANSDATABLOCK Index error "); +274432,562067968,0,0,PLAT_AP,ATCMD_EXEC,ResumeTrans_2,P_SIG,swLogPrintf("AT+ECRFNST : Rsp dataBlockCounter = %d , datalen = %d , startPos = %d "); +274432,562071551,0,0,PLAT_AP,ATCMD_EXEC,atRfNstRspDebug_1,P_VALUE,swLogPrintf("NstRspDebug "); +274432,562071808,0,0,PLAT_AP,ATCMD_EXEC,RfOpenApiDcdcVpaCfg_1,P_INFO,swLogPrintf("dcdc vpa Cfg , %x , %x "); +274432,562075647,0,0,PLAT_AP,ATCMD_EXEC,RfOpenApiDcdcVpaRsp_1,P_INFO,swLogPrintf("dcdc vpa Cfg response "); +274432,562075904,0,0,PLAT_AP,ATCMD_EXEC,smsEncodeConcatenatedSms8bit_warn_1,P_WARNING,swLogPrintf("AT CMD , UDH is illegal : maxNum : %d , seqNum : %d "); +274432,562077696,0,0,PLAT_AP,ATCMD_EXEC,smsPduEncodeUDH_warn_1,P_WARNING,swLogPrintf("UDH_IEI : %d is not support "); +274432,562079744,0,0,PLAT_AP,ATCMD_EXEC,smsPduDecodeUDH_warn_1,P_WARNING,swLogPrintf("UDH_IEI : %d is not support "); +274432,562082560,0,0,PLAT_AP,ATCMD_EXEC,smsSendTextSms_1,P_INFO,swLogPrintf("SC address Type : %d , address Length : %d , bcd [ 0 ] : %c , bcd [ 1 ] : %c "); +274432,562083840,0,0,PLAT_AP,ATCMD_EXEC,smsSendSms_warn_1,P_WARNING,swLogPrintf("AT CMD , AT+CMGC does not support TEXT mode : %d "); +276480,566233088,0,0,PLAT_AP,ATCMD_SOCK,TcpipApiSendData_11,P_INFO,swLogPrintf("TcpipApiSendData send packet fail %u "); +276480,566237183,0,0,PLAT_AP,ATCMD_SOCK,TcpipApiCloseConnection_set_close_timeout_1,P_WARNING,swLogPrintf("TcpipApiCloseConnection enable tcp close timeout option fail "); +276480,566237184,0,0,PLAT_AP,ATCMD_SOCK,tcpipApiSendTotalData_4,P_INFO,swLogPrintf("tcpipApiSendTotalData send packet fail %u "); +276480,566239232,0,0,PLAT_AP,ATCMD_SOCK,tcpipApiAckedTotalData_4,P_INFO,swLogPrintf("tcpipApiAckedTotalData send packet fail %u "); +276480,566243327,0,0,PLAT_AP,ATCMD_SOCK,tcpipCheckHibMode_1,P_WARNING,swLogPrintf("tcpipCheckHibMode invalid cms sock mgr context "); +276480,566243584,0,0,PLAT_AP,ATCMD_SOCK,tcpipCheckHibMode_2,P_INFO,swLogPrintf("tcpipCheckHibMode socket id %u status %d , can not enter hib / sleep2 mode "); +276480,566245632,0,0,PLAT_AP,ATCMD_SOCK,tcpipCheckHibMode_3,P_INFO,swLogPrintf("tcpipCheckHibMode socket id %u exist pending UL sequence %ustatus "); +276480,566247424,0,0,PLAT_AP,ATCMD_SOCK,TcpipApiRecoverConnContext_8,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext recreate socket id %d fail "); +276480,566249472,0,0,PLAT_AP,ATCMD_SOCK,AtEcsocRecoverConnContext_bind_fail,P_ERROR,swLogPrintf("AtEcsocRecoverConnContext recreate socket id %d bind fail "); +276480,566251776,0,0,PLAT_AP,ATCMD_SOCK,TcpipApiRecoverConnContext_10,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext recreate socket id %d status %d is invalid "); +277504,568330496,0,0,PLAT_AP,PS_DIAL,psDialGetPlmnCfgByImsi_1,P_WARNING,swLogPrintf("Can ' t find DialPlmnCfg for PLMN : 0x%x , 0x%x "); +277504,568332544,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsBearerActedInd_1,P_WARNING,swLogPrintf("PS DIAL , bearer type : %d not valid , cid : %d "); +277504,568334336,0,0,PLAT_AP,PS_DIAL,psDialProccCmiPsBearerDeActInd_1,P_VALUE,swLogPrintf("PS DIAL , CID : %d , deactivated. "); +277504,568338431,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsConnStatusInd_1,P_INFO,swLogPrintf("PS monitor traffic idle on DRB , trigger TAU... "); +277504,568340479,0,0,PLAT_AP,PS_DIAL,psDialProcCmiDevSilentResetInd_1,P_WARNING,swLogPrintf("PS Silent Reset! "); +277504,568340480,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsReadDynBearerCtxParamCnf_1,P_WARNING,swLogPrintf("CID : %d maybe a non-ip type bearer "); +277504,568344575,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsReadDynBearerCtxParamCnf_2,P_VALUE,swLogPrintf("PS DIAL , BEARER don ' t has valid context , maybe dedicated BR , or not acted "); +277504,568346623,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsReadDynBearerCtxParamCnf_ded_1,P_VALUE,swLogPrintf("PS DIAL , wakeup proc , CGSCONTRDP get all activated dedicated BR "); +277504,568348671,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsReadDedBearerDynCtxParamCnf_tft_1,P_VALUE,swLogPrintf("PS DIAL , wakeup proc , CGTFTRDP get all activated TFT config "); +277504,568350719,0,0,PLAT_AP,PS_DIAL,psDialProcCmiPsTrafficIdleMonitorInd_1,P_INFO,swLogPrintf("PS monitor traffic idle on DRB , tigger RRC local release! "); +277504,568352767,0,0,PLAT_AP,PS_DIAL,psDialProcCmiDevSetPowerStateCnf_1,P_VALUE,swLogPrintf("PS DIAL , wakeup proc , CGCONTRDP get all activated default BR "); +277504,568354815,0,0,PLAT_AP,PS_DIAL,psDailGetCfgDnsByUeImsi_5,P_WARNING,swLogPrintf("psDailGetCfgDnsByUeImsi get plmn dns fail "); +277504,568356863,0,0,PLAT_AP,PS_DIAL,psDailGetCfgDnsByUeImsi_1,P_WARNING,swLogPrintf("psDailGetCfgDnsByUeImsi parse ipv4Dns0 fail "); +277504,568358911,0,0,PLAT_AP,PS_DIAL,psDailGetCfgDnsByUeImsi_2,P_WARNING,swLogPrintf("psDailGetCfgDnsByUeImsi parse ipv4Dns1 fail "); +277504,568360959,0,0,PLAT_AP,PS_DIAL,psDailGetCfgDnsByUeImsi_3,P_WARNING,swLogPrintf("psDailGetCfgDnsByUeImsi parse ipv6Dns0 fail "); +277504,568363007,0,0,PLAT_AP,PS_DIAL,psDailGetCfgDnsByUeImsi_4,P_WARNING,swLogPrintf("psDailGetCfgDnsByUeImsi parse ipv6Dns1 fail "); +277504,568363264,0,0,PLAT_AP,PS_DIAL,psDailGetPlmnPreferBandList_1,P_WARNING,swLogPrintf("Can ' t find DialPlmnCfg for PLMN : 0x%x , 0x%x , can ' t get prefer band "); +277504,568365056,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndBindCid_no_net_0,P_VALUE,swLogPrintf("PS DIAL NET , usbCtrl %d , not enable RNDIS / ECM , not need bind CID "); +277504,568367360,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndBindCid_invalid_cid_1,P_WARNING,swLogPrintf("PS DIAL NET , NETDEVCTL opt : %d , but req bind invalid CID : %d , can ' t bind "); +277504,568369152,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndBindCid_def_1,P_VALUE,swLogPrintf("PS DIAL NET , CID : %d not activated , can ' t bind "); +277504,568371456,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndBindCid_unbind_1,P_VALUE,swLogPrintf("PS DIAL NET , try to bind new CID : %d , but need to unbind old CID : %d "); +277504,568373248,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndActPdp_no_net_0,P_VALUE,swLogPrintf("PS DIAL NET , usbCtrl %d , not enable RNDIS / ECM , not need check / act bound PDP "); +277504,568375552,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndActPdp_invalid_cid_1,P_WARNING,swLogPrintf("PS DIAL NET , NETDEVCTL opt : %d , but bind invalid CID : %d "); +277504,568377344,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndActPdp_ded_2,P_WARNING,swLogPrintf("PS DIAL NET , bind CID : %d not default BR , can ' t act and bind to RNDIS / ECM "); +277504,568379392,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndActPdp_def_1,P_VALUE,swLogPrintf("PS DIAL NET , bind CID : %d , default BR already activated "); +277504,568381440,0,0,PLAT_AP,PS_DIAL,psDialNetCheckAndActPdp_act_1,P_VALUE,swLogPrintf("PS DIAl NET , get CGCONTRDP failed , try to act CID : %d "); +277504,568385535,0,0,PLAT_AP,PS_DIAL,psDialNetDevCtl_none_0,P_VALUE,swLogPrintf("PS DIAL NET , NETDEVCTL no action need , return "); +277504,568385536,0,0,PLAT_AP,PS_DIAL,psDialNetDevCtl_same_0,P_VALUE,swLogPrintf("PS DIAL NET , NETDEVCTL bind CID : %d , already bound before , return "); +277504,568389631,0,0,PLAT_AP,PS_DIAL,psDialNetDevCtl_laninfo_w_0,P_WARNING,swLogPrintf("PS DIAL NET , Get LANStatus failed "); +277504,568391679,0,0,PLAT_AP,PS_DIAL,psDialNetProcApplInd_unbind_1,P_VALUE,swLogPrintf("PS DIAL NET , ETH unbind , check whether need to rebind "); +277504,568391680,0,0,PLAT_AP,PS_DIAL,psDialNetAutoDialCheck_0,P_VALUE,swLogPrintf("PS DIAL NET , cancel Auto Dial Check due to usbCtrl %d "); +277504,568395775,0,0,PLAT_AP,PS_DIAL,psDialNetAutoDialCheck_2,P_VALUE,swLogPrintf("PS DIAl NET , getAllBearersCidsBasicInfo failed , report bind failure "); +277504,568396544,0,0,PLAT_AP,PS_DIAL,psDialNetInit_1,P_VALUE,swLogPrintf("PS DIAL , Ethlan config , ethHostAddr : %u.%u.%u.%u "); +277504,568398592,0,0,PLAT_AP,PS_DIAL,psDialNetInit_2,P_VALUE,swLogPrintf("PS DIAL , Ethlan config , ethLocalAddr : %u.%u.%u.%u "); +277504,568399872,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_s_1,P_INFO,swLogPrintf("PS DIAL ISR , proc CP event : %e "); +277504,568401920,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_w_1,P_WARNING,swLogPrintf("PS DIAL , CMS task already created , forward the CP event : %d , to task "); +277504,568406015,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_paging_1,P_SIG,swLogPrintf("PS DIAL ISR , need wakeup AP & CP , as recv UE paging "); +277504,568408063,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_paging_2,P_WARNING,swLogPrintf("PS DIAL ISR , only need wakeup AP , as recv UE paging "); +277504,568410111,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_serving_1,P_SIG,swLogPrintf("PS DIAL ISR , need wakeup AP & CP , as serving cell measurement "); +277504,568412159,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_serving_2,P_SIG,swLogPrintf("PS DIAL ISR , only need wakeup AP , as serving cell measurement "); +277504,568414207,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_cell_reselect_1,P_SIG,swLogPrintf("PS DIAL ISR , need wakeup AP & CP , as need cell re-selection "); +277504,568416255,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_cell_reselect_2,P_WARNING,swLogPrintf("PS DIAL ISR , only need wakeup AP , as need cell re-selection "); +277504,568418303,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_cell_meas_1,P_SIG,swLogPrintf("PS DIAL ISR , need wakeup AP & CP , as cell measurement event "); +277504,568420351,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_cell_meas_2,P_SIG,swLogPrintf("PS DIAL ISR , only need wakeup AP , as cell measurement event "); +277504,568420352,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingImgEventIsr_err_1,P_ERROR,swLogPrintf("PS DIAL ISR , can ' t proc CP event : %d "); +277504,568424447,0,0,PLAT_AP,PS_DIAL,cmsWakeupCheckPagingEvent_paging_s_1,P_SIG,swLogPrintf("PS DIAL , UE paging event to RRC "); +277504,568426495,0,0,PLAT_AP,PS_DIAL,psDialWakeupCheckPagingEvent_meas_s_1,P_SIG,swLogPrintf("PS DIAL , UE measure event to RRC "); +277504,568428543,0,0,PLAT_AP,PS_DIAL,psDialWakeupCheckPagingEvent_reselect_s_1,P_SIG,swLogPrintf("PS DIAL , UE re-select event to RRC "); +277504,568428544,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingEventIndIsrSig_s_1,P_SIG,swLogPrintf("PS DIAL , PS is ready , forward CP event : %d , to RRC "); +277504,568430592,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingEventIndIsrSig_paging_1,P_SIG,swLogPrintf("PS DIAL , need wakeup PS , as recv UE paging , ret : %d "); +277504,568432640,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingEventIndIsrSig_serving_1,P_SIG,swLogPrintf("PS DIAL , need wakeup PS , as serving cell measurement , ret : %d "); +277504,568434688,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingEventIndIsrSig_cell_reselect_1,P_SIG,swLogPrintf("PS DIAL , need wakeup PS , as need cell re-selection , ret : %d "); +277504,568436736,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingEventIndIsrSig_cell_meas_1,P_SIG,swLogPrintf("PS DIAL , need wakeup PS , as cell measurement event , ret : %d "); +277504,568440831,0,0,PLAT_AP,PS_DIAL,psDialProcCpPagingEventIndIsrSig_not_start_ps_1,P_SIG,swLogPrintf("PS DIAL , proc CP event , not need wake up PS "); +277504,568441088,0,0,PLAT_AP,PS_DIAL,psDialWakeupPs_value_1,P_VALUE,swLogPrintf("PS DIAL recv CMI CNF , SgId : %d , PrimId : %d , netif not recovery , still need pending "); +277504,568444927,0,0,PLAT_AP,PS_DIAL,psDialFirstPowerOn_cfun0_1,P_SIG,swLogPrintf("PS DIAL , CFUN 0 power on , don ' t power on PS... "); +277504,568446975,0,0,PLAT_AP,PS_DIAL,psDialFirstPowerOn_cfun4_1,P_SIG,swLogPrintf("PS DIAL , CFUN 4 power on , power on PS... "); +277504,568446976,0,0,PLAT_AP,PS_DIAL,psDialFirstPowerOn_cfun1_w_1,P_WARNING,swLogPrintf("PS DIAL , unsupported poweron cfun : %d , change to CFUN 1 , power on PS... "); +277504,568451071,0,0,PLAT_AP,PS_DIAL,psDialFirstPowerOn_cfun1_s_1,P_SIG,swLogPrintf("PS DIAL , CFUN 1 power on , power on PS... "); +277504,568453119,0,0,PLAT_AP,PS_DIAL,psDialStartPs_w_1,P_WARNING,swLogPrintf("PS DIAL , PS task is ready , don ' t need to restart "); +277504,568453376,0,0,PLAT_AP,PS_DIAL,psCamCmiReq_start_1,P_SIG,swLogPrintf("PS DIAL , request PS service , sgId : %d , primId : %d , need start PS firstly "); +278528,570427392,0,0,PLAT_AP,PS_STK_BIP,SendSignaltoSimBip_1,P_INFO,swLogPrintf("Send signal ( %x ) to simbip task! "); +278528,570431487,0,0,PLAT_AP,PS_STK_BIP,SimBipLinkUp_1,P_WARNING,swLogPrintf("SIMBIP task has already been created "); +278528,570433535,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcGetDefinedCidListCnf_2,P_WARNING,swLogPrintf("the number of defined cid list is error! "); +278528,570435583,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcSetBearerActStateCnf_0,P_INFO,swLogPrintf("Act bearer successfully "); +278528,570437631,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcSetBearerActStateCnf_1,P_INFO,swLogPrintf("DeAct bearer done "); +278528,570439679,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcSetBearerActStateCnf_2,P_INFO,swLogPrintf("No bip context found "); +278528,570439680,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcReadDynBearerCtxParamCnf_1,P_WARNING,swLogPrintf("Error CID : %d maybe a non-ip type bearer "); +278528,570443775,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcReadDynBearerCtxParamCnf_2,P_WARNING,swLogPrintf("BEARER don ' t has valid context "); +278528,570444032,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcLinkDownRsp_0,P_INFO,swLogPrintf("Disconnect PDN cid %d , bearer type %d "); +278528,570446080,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcLinkDownRsp_1,P_INFO,swLogPrintf("TR for close channel %d , bearer type %d "); +278528,570447872,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcDataAvailReq_0,P_WARNING,swLogPrintf("Ignore Data available by channel state %d is abnormal "); +278528,570450176,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcDataAvailReq_1,P_WARNING,swLogPrintf("Data error! datalength : %d , pData : 0x%x "); +278528,570451968,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcLinkErrorReq_0,P_WARNING,swLogPrintf("link error , channel state %d "); +278528,570454016,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcOpenChannelInd_0,P_WARNING,swLogPrintf("The default NetIf / PDP is ready , create simbip task and set up link for channel %d "); +278528,570458111,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcOpenChannelInd_1,P_WARNING,swLogPrintf("The default NetIf / PDP is not activated! "); +278528,570460159,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcOpenChannelInd_2,P_WARNING,swLogPrintf("Activate BIP PDN , get defined cid list first! "); +278528,570460160,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcOpenChannelInd_3,P_WARNING,swLogPrintf("Unsupport bearer type %x! "); +278528,570464255,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcOpenChannelInd_4,P_WARNING,swLogPrintf("No channel available! "); +278528,570464256,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcSendDataInd_1,P_WARNING,swLogPrintf("The BIP link is not ready , channel state : %x! "); +278528,570466304,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcCmiSimCnf_1,P_WARNING,swLogPrintf("Unexpected CMI CNF : %x , ignore it! "); +278528,570470399,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcCmiPsCnf_1,P_WARNING,swLogPrintf("The NetIf / PDP activated failure! "); +278528,570470400,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcSimBipReqSig_1,P_WARNING,swLogPrintf("Unexpected SIM BIP REQ : %x , ignore it! "); +278528,570472448,0,0,PLAT_AP,PS_STK_BIP,psStkBipProcSimBipRspSig_1,P_WARNING,swLogPrintf("Unexpected SIM BIP RSP : %x , ignore it! "); +278528,570474752,0,0,PLAT_AP,PS_STK_BIP,psStkProcCmiPsBearerDeActInd_1,P_WARNING,swLogPrintf("Bearer context Id %d deactive , channel state %d "); +279552,572526591,0,0,PLAT_AP,CMS,apmuWakeupPsNoneBlock_w_1,P_WARNING,swLogPrintf("CMS , not need send signal to wake up PS , if failed enter sleep2 / HIB "); +279552,572528639,0,0,PLAT_AP,CMS,cmsStartPs_s_1,P_SIG,swLogPrintf("Call CMS SYN API to start PS... "); +279552,572530687,0,0,PLAT_AP,CMS,cmsStartPsNonBlock_s_1,P_SIG,swLogPrintf("Call CMS non-block API to start PS... "); +279552,572530688,0,0,PLAT_AP,CMS,cmsPriSynApiCall_1,P_DEBUG,swLogPrintf("SIG sent pointer : %x "); +279552,572532736,0,0,PLAT_AP,CMS,psDialWakeupPs_1,P_WARNING,swLogPrintf("PS DIAL received sig : 0x%x , while waiting for PS waking up , just enqueue "); +279552,572534784,0,0,PLAT_AP,CMS,psDialFirstPowerPs_1,P_WARNING,swLogPrintf("PS DIAL received sig : 0x%x , during first power cfun , just enqueue "); +279552,572537088,0,0,PLAT_AP,CMS,smsGsmDefaultAlphabet2Ascii_warn_1,P_WARNING,swLogPrintf("PSIL SMS , invalid input pInGsm [ %d ] : 0x%x "); +279552,572539136,0,0,PLAT_AP,CMS,smsAscii2GsmDefaultAlphabet_warn_1,P_WARNING,swLogPrintf("PSIL SMS , output length ( %d ) should not exceed %d "); +279552,572541184,0,0,PLAT_AP,CMS,smsAscii2GsmDefaultAlphabet_warn_2,P_WARNING,swLogPrintf("PSIL SMS , input length ( %d ) should not exceed %d "); +279552,572543232,0,0,PLAT_AP,CMS,smsAscii2GsmDefaultAlphabet_warn_3,P_WARNING,swLogPrintf("PSIL SMS , invalid input pInGsm [ %d ] : 0x%x "); +279552,572545024,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_1,P_WARNING,swLogPrintf("PSIL SMS , invalid UCS2 length : %d "); +279552,572549119,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_2,P_WARNING,swLogPrintf("PSIL SMS , user data header length is 0 "); +279552,572551167,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_3,P_WARNING,swLogPrintf("PSIL SMS , UDH is not supported in DCS 8 BIT "); +279552,572553215,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_4,P_WARNING,swLogPrintf("PSIL SMS , user data header length is 0 "); +279552,572553216,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_5,P_WARNING,swLogPrintf("PSIL SMS , length = %d , user data size should be from 0 to 140 "); +279552,572557311,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_6,P_WARNING,swLogPrintf("PSIL SMS , not valid UCS2 PDU "); +279552,572559359,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_7,P_WARNING,swLogPrintf("PSIL SMS , UDH is not supported in DCS UCS2 "); +279552,572561407,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_8,P_WARNING,swLogPrintf("PSIL SMS , user data header length is 0 "); +279552,572561408,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_9,P_WARNING,swLogPrintf("PSIL SMS , invalid codingScheme = %d "); +279552,572563456,0,0,PLAT_AP,CMS,smsMsgEncodeUserData_warn_10,P_WARNING,swLogPrintf("PSIL SMS , length = %d , user data size should be from 0 to 140 "); +279552,572565760,0,0,PLAT_AP,CMS,smsSubmitText2Pdu_warn_1,P_WARNING,swLogPrintf("PSIL SMS , send Text SMS , length : %d is 0 , or > MAX : %d "); +279552,572567808,0,0,PLAT_AP,CMS,smsSubmitText2Pdu_info_1,P_INFO,swLogPrintf("PSIL SMS , send Text SMS , length : %d , MAX : %d "); +279552,572570368,0,0,PLAT_AP,CMS,smsSubmitText2Pdu_info_2,P_INFO,swLogPrintf("PSIL SMS , Da length : %d , offset : %d , DSC : %d , VPF : %d "); +279552,572572160,0,0,PLAT_AP,CMS,smsSubmitText2Pdu_info_3,P_INFO,swLogPrintf("PSIL SMS , enCode PDU length : %d , offset : %d , DSC : %d "); +279552,572573952,0,0,PLAT_AP,CMS,smsDeliverText2Pdu_warn_1,P_WARNING,swLogPrintf("PSIL SMS , deliver Text SMS , length : %d is 0 , or > MAX : %d "); +279552,572576000,0,0,PLAT_AP,CMS,smsDeliverText2Pdu_info_1,P_INFO,swLogPrintf("PSIL SMS , deliver Text SMS , length : %d , MAX : %d "); +279552,572578304,0,0,PLAT_AP,CMS,smsDeliverText2Pdu_info_2,P_INFO,swLogPrintf("PSIL SMS , Da length : %d , offset : %d , DSC : %d "); +279552,572580352,0,0,PLAT_AP,CMS,smsDeliverText2Pdu_info_3,P_INFO,swLogPrintf("PSIL SMS , enCode PDU length : %d , offset : %d , DSC : %d "); +279552,572582656,0,0,PLAT_AP,CMS,smsSendPduSms_warn_1,P_WARNING,swLogPrintf("PSIL SMS , invalid SC address in input PDU , hex vale : 0x%x , digit Length : %d , lenInHdr : %d , offset : %d "); +279552,572583936,0,0,PLAT_AP,CMS,smsWriteTextSmsToStorage_warn_1,P_WARNING,swLogPrintf("PSIL SMS , smsMsgType %d not supported "); +279552,572585984,0,0,PLAT_AP,CMS,smsWriteTextSmsToStorage_warn_2,P_WARNING,swLogPrintf("PSIL SMS , smsMsgType %d not supported "); +279552,572588032,0,0,PLAT_AP,CMS,smsWriteTextSmsToStorage_warn_3,P_WARNING,swLogPrintf("PSIL SMS , smsMemType %d not supported "); +279552,572590848,0,0,PLAT_AP,CMS,smsWritePduSmsToStorage_warn_1,P_WARNING,swLogPrintf("PSIL SMS , invalid SC address in input PDU , hex vale : 0x%x , digit Length : %d , lenInHdr : %d , offset : %d "); +279552,572592128,0,0,PLAT_AP,CMS,smsWritePduSmsToStorage_warn_2,P_WARNING,swLogPrintf("PSIL SMS , smsRecMsgType %d is not supported "); +279552,572594176,0,0,PLAT_AP,CMS,smsWritePduSmsToStorage_warn_3,P_WARNING,swLogPrintf("PSIL SMS , smsMemType %d not supported "); +279552,572596224,0,0,PLAT_AP,CMS,smsSendStoredSms_warn_1,P_WARNING,swLogPrintf("PSIL SMS , TP-MTI ( %d ) is not SMS-SUBMIT "); +279552,572599040,0,0,PLAT_AP,CMS,smsSrvCenterAddrToText_1,P_INFO,swLogPrintf("SC address Type : %d , Address Len : %d , bcd [ 0 ] : %c , bcd [ 1 ] : %c "); +279552,572600320,0,0,PLAT_AP,CMS,smsSrvCenterAddrToText_2,P_INFO,swLogPrintf("smscBufLen %d is not enouth "); +279552,572602368,0,0,PLAT_AP,CMS,smsSetSrvCenterAddr_warn_1,P_WARNING,swLogPrintf("PSIL SMS , invalid UCS2 length : %d "); +279552,572606463,0,0,PLAT_AP,CMS,smsDeleteSmsStoreRecord_1,P_WARNING,swLogPrintf("PSIL SMS , memory allocate failed when get SMS storage information from NVRAM "); +279552,572608511,0,0,PLAT_AP,CMS,smsDeleteSmsStoreRecord_2,P_WARNING,swLogPrintf("PSIL SMS , read SMS storage memory failure ! "); +279552,572609024,0,0,PLAT_AP,CMS,smsDeleteSmsStoreRecord_3,P_WARNING,swLogPrintf("PSIL SMS , delete fail , input param are invalid , Del_Operat : %d , DEL_Index : %d , Del_Flag : %d "); +279552,572611072,0,0,PLAT_AP,CMS,smsPduDecodeUserData_1,P_INFO,swLogPrintf("userDataLen %d , msgParsed %d , msgBodyLen %d "); +279552,572613124,0,0,PLAT_AP,CMS,smsPduDecodeUserData_2,P_INFO,swLogPrintf("PSIL SMS , codingType : %d , out Length : %d , decodeUserData : %s "); +279552,572614912,0,0,PLAT_AP,CMS,smsGetTPUserDataSize_0,P_INFO,swLogPrintf("PSIL SMS , pTPUDLen : %d , pduDataLen : %d "); +279552,572616960,0,0,PLAT_AP,CMS,smsSubmitTpduLen_0,P_INFO,swLogPrintf("PSIL SMS , offset : %d , tpUserDataLen : %d "); +279552,572619264,0,0,PLAT_AP,CMS,SmsSumbitPduToText_1,P_INFO,swLogPrintf("SmsSubmitPduToText , FO : %d , offset : %d , VPF : %d "); +279552,572621312,0,0,PLAT_AP,CMS,SmsSubmitPduToText_2,P_INFO,swLogPrintf("PSIL SMS , PDU length : %d , offset : %d , VPF : %d "); +279552,572623616,0,0,PLAT_AP,CMS,SmsSubmitPduToText_3,P_INFO,swLogPrintf("PSIL SMS , pduLen : %d , dsc : %d , hdrpresent : %d , offset : %d "); +279552,572625152,0,0,PLAT_AP,CMS,smsDeliverTpduLen_0,P_INFO,swLogPrintf("PSIL SMS , offset : %d , tpUserDataLen : %d "); +279552,572627712,0,0,PLAT_AP,CMS,SmsDeliverPduToText_1,P_INFO,swLogPrintf("PSIL SMS , PDU length : %d , dsc : %d , hdrpresent : %d , offset : %d "); +279552,572628992,0,0,PLAT_AP,CMS,SmsSubmitRptPduToText_1,P_ERROR,swLogPrintf("PSIL SMS , PDU length is wrong : %d "); +279552,572631040,0,0,PLAT_AP,CMS,SmsSubmitRptPduToText_2,P_ERROR,swLogPrintf("PSIL SMS , PDU length is wrong : %d "); +279552,572633088,0,0,PLAT_AP,CMS,smsStateStrToInt_1,P_INFO,swLogPrintf("PSIL SMS , SMS status : %d "); +279552,572635137,0,0,PLAT_AP,CMS,smsStateIntToStr_1,P_INFO,swLogPrintf("PSIL SMS , SMS Status : %s "); +279552,572637700,0,0,PLAT_AP,CMS,smsDecodeCbsData_1,P_INFO,swLogPrintf("PSIL SMS , codingType : %d , out Length : %d , decodeUserData : %s "); +279552,572639490,0,0,PLAT_AP,CMS,smsAsciiToUcs2_1,P_INFO,swLogPrintf("PSIL SMS , iLengh : %d , pAscii : %s "); +279552,572641538,0,0,PLAT_AP,CMS,smsUcs2ToAscii_1,P_INFO,swLogPrintf("PSIL SMS , iLengh : %d , pUcs2 : %s "); +280576,574622720,0,0,PLAT_AP,SIM_BIP,SimBipProcLinkUp_1,P_WARNING,swLogPrintf("Sim bip link up : dest ipv4 addr %u.%u.%u.%u , port %d "); +280576,574625791,0,0,PLAT_AP,SIM_BIP,SimBipProcLinkUp_2,P_WARNING,swLogPrintf("Sim bip link up failed , close socket! "); +280576,574627839,0,0,PLAT_AP,SIM_BIP,SimBipProcLinkUp_3,P_WARNING,swLogPrintf("Sim bip link up failed , connect server error! "); +280576,574628096,0,0,PLAT_AP,SIM_BIP,SimBipProcLinkUp_4,P_WARNING,swLogPrintf("index : %d , socketId : %d , Sim bip link up successed! "); +280576,574631935,0,0,PLAT_AP,SIM_BIP,SimBipProcLinkUp_5,P_WARNING,swLogPrintf("Sim bip link up failed , bind cid error! "); +280576,574631936,0,0,PLAT_AP,SIM_BIP,SimBipProcLinkDown_0,P_WARNING,swLogPrintf("Sim bip close channel ( Id : %x ) ! "); +280576,574634752,0,0,PLAT_AP,SIM_BIP,SimBipProcSendData_001,P_INFO,swLogPrintf("channelId : %d , index : %d , socketId : %d , linkState : %d! "); +280576,574636032,0,0,PLAT_AP,SIM_BIP,SimBipProcSendData_0,P_ERROR,swLogPrintf("Sim bip send data got error code ( %d ) ! "); +280576,574640127,0,0,PLAT_AP,SIM_BIP,SimBipProcSendData_1,P_WARNING,swLogPrintf("Sim bip send data successed! "); +280576,574642175,0,0,PLAT_AP,SIM_BIP,SimBipProcSendData_2,P_WARNING,swLogPrintf("Sim bip send data failed! "); +280576,574642176,0,0,PLAT_AP,SIM_BIP,SimBipProcRecvData_1,P_WARNING,swLogPrintf("Sim bip recvd data got error code ( %d ) ! "); +280576,574644224,0,0,PLAT_AP,SIM_BIP,SimBipProcRecvData_2,P_WARNING,swLogPrintf("Sim bip recvd data ( %d ) bytes! "); +280576,574648319,0,0,PLAT_AP,SIM_BIP,SimBipProcRecvData_3,P_WARNING,swLogPrintf("Sim bip recvd 0 byte data! Continue to receive data... "); +280576,574648320,0,0,PLAT_AP,SIM_BIP,SimBipProcRecvData_4,P_WARNING,swLogPrintf("Sim bip link drop error ( %d ) , send channel status event download! "); +280576,574652415,0,0,PLAT_AP,SIM_BIP,SimBipProcRecvData_5,P_INFO,swLogPrintf("Sim bip select timeout! "); +280576,574654463,0,0,PLAT_AP,SIM_BIP,SimBipTaskEntry_0,P_WARNING,swLogPrintf("SIM BIP task is starting... "); +280576,574656511,0,0,PLAT_AP,SIM_BIP,SimBipTaskEntry_1,P_WARNING,swLogPrintf("All link state of channel is NULL , so exit the sim bip task... "); +280576,574658559,0,0,PLAT_AP,SIM_BIP,SimBipTaskEntry_3,P_WARNING,swLogPrintf("SIM BIP task is exiting... "); +283648,580915199,0,0,PLAT_AP,CMS_PS_IL,phySetPhyInfo_start_1,P_SIG,swLogPrintf("PS PHY IF , set PHY CFG , need start PS firstly "); +283648,580915459,0,0,PLAT_AP,CMS_PS_IL,psParseIpAddrAndMaskFromStr_w_1,P_WARNING,swLogPrintf("PS IF , can ' t decode IP addr and mask from str : %s , parsed : %s "); +283648,580918024,0,0,PLAT_AP,CMS_PS_IL,psParseIpAddrAndMaskFromSt_num_w_1,P_WARNING,swLogPrintf("PS IF , intOffset : %d , addrNum : %d , numVal : %d , can ' t decode IP addr and mask from str : %s "); +283648,580919554,0,0,PLAT_AP,CMS_PS_IL,psParseIpAddrAndMaskFromStr_addrNum_w_1,P_WARNING,swLogPrintf("PS IF , addr num : %d not right , can ' t decode IP addr and mask from str : %s "); +283648,580921860,0,0,PLAT_AP,CMS_PS_IL,psParseIpAddrAndMaskFromStr_mask_w_1,P_WARNING,swLogPrintf("PS IF , ip mask : %d , not right , idx : %d , can ' t decode IP addr and mask from str : %s "); +283648,580923908,0,0,PLAT_AP,CMS_PS_IL,psParsePfPortInfoFromStr_w_1,P_WARNING,swLogPrintf("PS IF , can ' t parse port range : %d , %d from str : %s "); +283648,580925441,0,0,PLAT_AP,CMS_PS_IL,psParseTosMaskFromStr_w_1,P_WARNING,swLogPrintf("PS IF , can ' t parse TOS and mask from str : %s "); +283648,580927746,0,0,PLAT_AP,CMS_PS_IL,psParseTosMaskFromStr_w_2,P_WARNING,swLogPrintf("PS IF , invalid TOS : %d , str : %s "); +283648,580929537,0,0,PLAT_AP,CMS_PS_IL,psParseTosMaskFromStr_w_3,P_WARNING,swLogPrintf("PS IF , can ' t parse TOS from str : %s "); +283648,580931842,0,0,PLAT_AP,CMS_PS_IL,psParseTosMaskFromStr_w_4,P_WARNING,swLogPrintf("PS IF , invalid TOS MASK : %d , str : %s "); +283648,580933633,0,0,PLAT_AP,CMS_PS_IL,psParseTosMaskFromStr_w_5,P_WARNING,swLogPrintf("PS IF , can ' t parse TOS MASK from str : %s "); +284672,583012351,0,0,PLAT_AP,CMS_SOCK_MGR,TcpipApiCloseConnection_set_close_timeout_2,P_INFO,swLogPrintf("TcpipApiCloseConnection enable tcp close timeout option success "); +284672,583012608,0,0,PLAT_AP,CMS_SOCK_MGR,udp_send_dns_resolve_result_len_check_1,P_ERROR,swLogPrintf("cmsSockMgrSendAsyncRequest length %u big than message body len %u "); +285696,585109503,0,0,PLAT_AP,EC_API,apIpcWakeup_0,P_SIG,swLogPrintf("Send IPC Wake up Signal "); +285696,585110016,0,0,PLAT_AP,EC_API,ApFpgaIpcIsr_0,P_SIG,swLogPrintf("msgId = %x , bFastMsg = %x , msgBodyLen = %x "); +285696,585113599,0,0,PLAT_AP,EC_API,ApFpgaIpcIsr_1,P_SIG,swLogPrintf("HandShake REQ Received! "); +285696,585115647,0,0,PLAT_AP,EC_API,ApFpgaIpcAlone0Isr_0,P_SIG,swLogPrintf("Enter FPGA IPC ALONE0 ISR! ISR INFO WRONG "); +285696,585117695,0,0,PLAT_AP,EC_API,ApFpgaIpcAlone0Isr_1,P_SIG,swLogPrintf("Enter FPGA IPC ALONE0 ISR! "); +285696,585119743,0,0,PLAT_AP,EC_API,ApFpgaIpcAlone1Isr_0,P_SIG,swLogPrintf("Enter FPGA IPC ALONE1 ISR! ISR INFO WRONG "); +285696,585121791,0,0,PLAT_AP,EC_API,ApFpgaIpcAlone1Isr_1,P_SIG,swLogPrintf("Enter FPGA IPC ALONE1 ISR! "); +285696,585123839,0,0,PLAT_AP,EC_API,ApFpgaIpcMergeIsr_0,P_SIG,swLogPrintf("Enter FPGA IPC MERGE ISR! ISR INFO WRONG "); +285696,585125887,0,0,PLAT_AP,EC_API,ApFpgaIpcMergeIsr_1,P_SIG,swLogPrintf("Enter FPGA IPC MERGE ISR! "); +285696,585127935,0,0,PLAT_AP,EC_API,ApFpgaSipcIsr_0,P_SIG,swLogPrintf("AP SIPC ISR OK "); +285696,585129983,0,0,PLAT_AP,EC_API,ApFpgaSipcIsr_2,P_SIG,swLogPrintf("AP SIPC RESET OK "); +285696,585132031,0,0,PLAT_AP,EC_API,ApFpgaSipcIsr_3,P_SIG,swLogPrintf("AP SIPC RESET NOK "); +285696,585134079,0,0,PLAT_AP,EC_API,ApFpgaSipcIsr_1,P_SIG,swLogPrintf("AP SIPC ISR NOK "); +285696,585136127,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_0,P_SIG,swLogPrintf("Start IPC FGPA TEST! "); +285696,585138175,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_1,P_SIG,swLogPrintf("C2A_IPC_INIT_REQ RECEIVED "); +285696,585138176,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_2,P_SIG,swLogPrintf("Send Data to CP , caseIndex = %d \n "); +285696,585140736,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_3,P_SIG,swLogPrintf("M = %d , N = %d , X = %d "); +285696,585144319,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_4,P_SIG,swLogPrintf("RECEIVED CP DATA IND ( 1 ) "); +285696,585146367,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_5,P_SIG,swLogPrintf("RECEIVED CP DATA IND ( 2 ) "); +285696,585148415,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_6,P_SIG,swLogPrintf("RECEIVED CP DATA IND ( 3 ) "); +285696,585150463,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_7,P_SIG,swLogPrintf("SIPC Lock by AP "); +285696,585152511,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_8,P_SIG,swLogPrintf("SIPC Release by AP "); +285696,585154559,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_9,P_SIG,swLogPrintf("SIPC Release by CP "); +285696,585156607,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_10,P_SIG,swLogPrintf("SIPC SET INT "); +285696,585156608,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_11,P_SIG,swLogPrintf("Case Pass : caseIndex = %d \n "); +285696,585158656,0,0,PLAT_AP,EC_API,ApFpgaIpcTestMain_12,P_SIG,swLogPrintf("Case Fail : caseIndex = %d \n "); +285696,585160704,0,0,PLAT_AP,EC_API,appPsCmiReqBlockCallback_warn_1,P_WARNING,swLogPrintf("EC API , APP CMI request is busy , can ' t proc new , freeBitmap : 0x%x "); +285696,585163264,0,0,PLAT_AP,EC_API,psBlockProcCmiCnf_warning_1,P_WARNING,swLogPrintf("EC API , blocked psCmiReq , guard timer maybe expiried before , sgId : %d , primId : %d , subHdrId : %d "); +285696,585164800,0,0,PLAT_AP,EC_API,psBlockProcTimerExpiry_warning_1,P_WARNING,swLogPrintf("EC API , block timer expiry , but block info not exist , maybe confirmed before , subHdrId : %d "); +293888,601884928,0,0,PLAT_AP,LWIP_CORE,dns_init_1,P_WARNING,swLogPrintf("dns_init dns_query ( %u ) , dns_answer ( %u ) "); +293888,601888767,0,0,PLAT_AP,LWIP_CORE,dns_init_2,P_INFO,swLogPrintf("dns_init initializing "); +293888,601888768,0,0,PLAT_AP,LWIP_CORE,dns_clear_cache_1,P_INFO,swLogPrintf("dns_clearcache : type %u "); +293888,601890816,0,0,PLAT_AP,LWIP_CORE,dns_clear_cache_2,P_SIG,swLogPrintf("dns_clearcache : invalid type %u "); +293888,601894911,0,0,PLAT_AP,LWIP_CORE,dns_find_adpt_hib_tiny_entry_1,P_INFO,swLogPrintf("dns_find_adpt_hib_tiny_entry "); +293888,601896959,0,0,PLAT_AP,LWIP_CORE,dns_add_cache_entry_1,P_INFO,swLogPrintf("dns_add_cache_entry "); +293888,601899007,0,0,PLAT_AP,LWIP_CORE,dns_add_cache_entry_2,P_INFO,swLogPrintf("dns_add_cache_entry has timeout "); +293888,601899008,0,0,PLAT_AP,LWIP_CORE,dns_add_cache_entry_3,P_INFO,swLogPrintf("active dns entry cache timer %u "); +293888,601903103,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_1,P_INFO,swLogPrintf("dns_entry_retry_timer_handler timeout "); +293888,601905151,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,601905152,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_3,P_WARNING,swLogPrintf("invalid dns entry 0x%x "); +293888,601909247,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_4,P_INFO,swLogPrintf("dns_check_entry : timeout "); +293888,601909248,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_5,P_WARNING,swLogPrintf("dns_send returned error2 : ( %d ) "); +293888,601911552,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_6,P_INFO,swLogPrintf("active dns entry timout %u , entry 0x%x "); +293888,601915391,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_7,P_ERROR,swLogPrintf("unknown dns_table entry retry timeout invalid "); +293888,601915392,0,0,PLAT_AP,LWIP_CORE,dns_entry_retry_timer_handler_8,P_ERROR,swLogPrintf("unknown dns_table entry state %u "); +293888,601919487,0,0,PLAT_AP,LWIP_CORE,dns_entry_cache_timer_handler_1,P_INFO,swLogPrintf("dns_entry_cache_timer_handler timeout "); +293888,601921535,0,0,PLAT_AP,LWIP_CORE,dns_entry_cache_timer_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,601923583,0,0,PLAT_AP,LWIP_CORE,dns_entry_cache_timer_handler_3,P_INFO,swLogPrintf("dns_check_entry : flush "); +293888,601923584,0,0,PLAT_AP,LWIP_CORE,dns_entry_cache_timer_handler_4,P_ERROR,swLogPrintf("unknown dns_table entry state %u "); +293888,601927679,0,0,PLAT_AP,LWIP_CORE,dns_lookup_1,P_INFO,swLogPrintf("dns_lookup found "); +293888,601929727,0,0,PLAT_AP,LWIP_CORE,dns_lookup_timeout_1,P_INFO,swLogPrintf("dns_lookup has timeout "); +293888,601931775,0,0,PLAT_AP,LWIP_CORE,dns_lookup_timeout_2,P_INFO,swLogPrintf("dns_lookup has timeout "); +293888,601931776,0,0,PLAT_AP,LWIP_CORE,dns_send_1,P_INFO,swLogPrintf("dns_send dns_servers %u request "); +293888,601933824,0,0,PLAT_AP,LWIP_CORE,dns_send_2,P_ERROR,swLogPrintf("dns_send dns_servers %u request "); +293888,601936128,0,0,PLAT_AP,LWIP_CORE,dns_send_3,P_INFO,swLogPrintf("sending DNS request ID ( %d ) for name to server ( %d ) "); +293888,601937920,0,0,PLAT_AP,LWIP_CORE,dns_send_4,P_INFO,swLogPrintf("dns_send entry retry timeout %u "); +293888,601939968,0,0,PLAT_AP,LWIP_CORE,dns_send_5,P_INFO,swLogPrintf("dns_send entry retry timeout %u "); +293888,601944063,0,0,PLAT_AP,LWIP_CORE,dns_send_6,P_ERROR,swLogPrintf("dns_send entry retry timeout invalid "); +293888,601946111,0,0,PLAT_AP,LWIP_CORE,dns_call_found_1,P_ERROR,swLogPrintf("invalid ipv6 response "); +293888,601948159,0,0,PLAT_AP,LWIP_CORE,dns_call_found_2,P_ERROR,swLogPrintf("invalid ipv4 response "); +293888,601950207,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_1,P_ERROR,swLogPrintf("array index out of bounds "); +293888,601950208,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_2,P_WARNING,swLogPrintf("dns_send returned error1 : ( %d ) "); +293888,601952512,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_3,P_INFO,swLogPrintf("active dns entry retry timeout %u entry 0x%x "); +293888,601956351,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_4,P_INFO,swLogPrintf("dns_check_entry : timeout "); +293888,601956352,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_5,P_WARNING,swLogPrintf("dns_send returned error2 : ( %d ) "); +293888,601960447,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_6,P_INFO,swLogPrintf("dns_check_entry : flush "); +293888,601962495,0,0,PLAT_AP,LWIP_CORE,dns_check_entry_7,P_ERROR,swLogPrintf("unknown dns_table entry state "); +293888,601964543,0,0,PLAT_AP,LWIP_CORE,dns_clear_entry_1,P_ERROR,swLogPrintf("the name point is null "); +293888,601964544,0,0,PLAT_AP,LWIP_CORE,dns_clear_entry_2,P_INFO,swLogPrintf("dns_clear_entry index %u "); +293888,601968639,0,0,PLAT_AP,LWIP_CORE,dns_clear_all_entry_1,P_INFO,swLogPrintf("dns_clear_all_entry "); +293888,601970687,0,0,PLAT_AP,LWIP_CORE,dns_get_dns_server_info_1,P_WARNING,swLogPrintf("dns_get_dns_server_info invalid "); +293888,601970688,0,0,PLAT_AP,LWIP_CORE,dns_get_dns_server_info_2,P_INFO,swLogPrintf("dns_get_dns_server_info dns server index %u "); +293888,601972736,0,0,PLAT_AP,LWIP_CORE,dns_get_dns_server_info_3,P_INFO,swLogPrintf("dns_get_dns_server_info dns server number %u "); +293888,601976831,0,0,PLAT_AP,LWIP_CORE,dns_disable_all_cache_1,P_INFO,swLogPrintf("dns_disable_all_cache "); +293888,601978879,0,0,PLAT_AP,LWIP_CORE,dns_enable_all_cache_1,P_INFO,swLogPrintf("dns_disable_all_cache "); +293888,601978880,0,0,PLAT_AP,LWIP_CORE,dns_correct_response_1,P_INFO,swLogPrintf("remove dns entry retry timer , entry 0x%x "); +293888,601982975,0,0,PLAT_AP,LWIP_CORE,dns_correct_response_2,P_INFO,swLogPrintf("dns_recv response = "); +293888,601982976,0,0,PLAT_AP,LWIP_CORE,dns_correct_response_3,P_INFO,swLogPrintf("remove dns entry cache timer , entry 0x%x "); +293888,601985024,0,0,PLAT_AP,LWIP_CORE,dns_correct_response_4,P_INFO,swLogPrintf("active dns entry cache timer %u "); +293888,601989119,0,0,PLAT_AP,LWIP_CORE,dns_correct_response_5,P_INFO,swLogPrintf("disable dns entry cache "); +293888,601991167,0,0,PLAT_AP,LWIP_CORE,dns_recv_9,P_INFO,swLogPrintf("dns_recv one packet "); +293888,601993215,0,0,PLAT_AP,LWIP_CORE,dns_recv_1,P_WARNING,swLogPrintf("dns_recv pbuf too small "); +293888,601995263,0,0,PLAT_AP,LWIP_CORE,dns_recv_2,P_INFO,swLogPrintf("dns_recv not a response "); +293888,601997311,0,0,PLAT_AP,LWIP_CORE,dns_recv_3,P_INFO,swLogPrintf("dns_recv response not match to query1 "); +293888,601999359,0,0,PLAT_AP,LWIP_CORE,dns_recv_4,P_INFO,swLogPrintf("dns_recv response not match to query2 "); +293888,602001407,0,0,PLAT_AP,LWIP_CORE,dns_recv_5,P_INFO,swLogPrintf("dns_recv response not match to query3 "); +293888,602003455,0,0,PLAT_AP,LWIP_CORE,dns_recv_6,P_INFO,swLogPrintf("dns_recv error in flags "); +293888,602005503,0,0,PLAT_AP,LWIP_CORE,dns_recv_7,P_INFO,swLogPrintf("dns_recv error in response "); +293888,602007551,0,0,PLAT_AP,LWIP_CORE,dns_recv_8,P_ERROR,swLogPrintf("dns_recv memory error "); +293888,602007552,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_netif_invalid_1,P_ERROR,swLogPrintf("dns_enqueue can not find netif by cid %u "); +293888,602011647,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_1,P_INFO,swLogPrintf("dns_enqueue duplicate request "); +293888,602013695,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_2,P_INFO,swLogPrintf("dns_enqueue DNS entries table is full "); +293888,602015743,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_3,P_INFO,swLogPrintf("dns_enqueue DNS request entries table is full "); +293888,602015744,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_4,P_INFO,swLogPrintf("dns_enqueue use DNS entry ( %u ) "); +293888,602019839,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_5,P_WARNING,swLogPrintf("dns_enqueue failed to allocate a pcb "); +293888,602019840,0,0,PLAT_AP,LWIP_CORE,dns_enqueue_6,P_INFO,swLogPrintf("dns_enqueue use DNS pcb ( %u ) "); +293888,602023935,0,0,PLAT_AP,LWIP_CORE,dns_gethostbyname_addrtype_1,P_WARNING,swLogPrintf("dns_gethostbyname name too long to resolve "); +293888,602024192,0,0,PLAT_AP,LWIP_CORE,inet_cksum_pseudo_base_2,P_INFO,swLogPrintf("inet_chksum_pseudo ( ) pbuf 0x%x chain lwip_chksum ( ) = %x "); +293888,602028031,0,0,PLAT_AP,LWIP_CORE,inet_cksum_pseudo_partial_base_1,P_ERROR,swLogPrintf("delete me "); +293888,602030079,0,0,PLAT_AP,LWIP_CORE,mem_malloc_1,P_ERROR,swLogPrintf("malloc ( ) must return aligned memory "); +293888,602032127,0,0,PLAT_AP,LWIP_CORE,mem_free_1,P_ERROR,swLogPrintf("rmem = = NULL or rmem ! = MEM_ALIGN ( rmem ) "); +293888,602034175,0,0,PLAT_AP,LWIP_CORE,do_memp_malloc_pool_1,P_ERROR,swLogPrintf("memp_malloc : memp properly aligned "); +293888,602036223,0,0,PLAT_AP,LWIP_CORE,do_memp_malloc_pool_2,P_ERROR,swLogPrintf("memp_malloc : out of memory in pool "); +293888,602038271,0,0,PLAT_AP,LWIP_CORE,memp_malloc_pool_1,P_ERROR,swLogPrintf("invalid pool desc "); +293888,602040319,0,0,PLAT_AP,LWIP_CORE,memp_malloc_1,P_ERROR,swLogPrintf("memp_malloc : type < MEMP_MAX "); +293888,602040320,0,0,PLAT_AP,LWIP_CORE,memp_malloc_2,P_ERROR,swLogPrintf("memp_malloc : type %d fail "); +293888,602042624,0,0,PLAT_AP,LWIP_CORE,memp_malloc_3,P_INFO,swLogPrintf("memp_malloc : type %d , address 0x%x success "); +293888,602046463,0,0,PLAT_AP,LWIP_CORE,do_memp_free_pool_1,P_ERROR,swLogPrintf("memp_free : mem properly aligned "); +293888,602048511,0,0,PLAT_AP,LWIP_CORE,do_memp_free_pool_2,P_ERROR,swLogPrintf("memp sanity "); +293888,602050559,0,0,PLAT_AP,LWIP_CORE,memp_free_pool_1,P_ERROR,swLogPrintf("invalid pool desc "); +293888,602052607,0,0,PLAT_AP,LWIP_CORE,memp_free_1,P_ERROR,swLogPrintf("memp_free : type < MEMP_MAX "); +293888,602052864,0,0,PLAT_AP,LWIP_CORE,memp_free_3,P_INFO,swLogPrintf("memp_free : type %d , address 0x%x "); +293888,602054912,0,0,PLAT_AP,LWIP_CORE,memp_free_2,P_INFO,swLogPrintf("memp_free : type %d , address 0x%x success "); +293888,602058751,0,0,PLAT_AP,LWIP_CORE,netif_add_1,P_ERROR,swLogPrintf("No init function given "); +293888,602059520,0,0,PLAT_AP,LWIP_CORE,netif_add_2,P_INFO,swLogPrintf("netif 0x%x added list 0x%x interface %c%u IP "); +293888,602061312,0,0,PLAT_AP,LWIP_CORE,netif_add_3,P_INFO,swLogPrintf("netif 0x%x added list interface %c%u IP complete "); +293888,602063872,0,0,PLAT_AP,LWIP_CORE,netif_remove_1,P_INFO,swLogPrintf("netif_remove : 0x%x removed from list 0x%x netif %c%u , net_type %u "); +293888,602065408,0,0,PLAT_AP,LWIP_CORE,netif_remove_2,P_INFO,swLogPrintf("netif_remove : 0x%x removed from list netif %c%u complete "); +293888,602066944,0,0,PLAT_AP,LWIP_CORE,netif_remove_type_1,P_INFO,swLogPrintf("netif_remove_type : removed netif type : %d "); +293888,602069248,0,0,PLAT_AP,LWIP_CORE,netif_find_1,P_INFO,swLogPrintf("netif_find : found %c%u "); +293888,602071296,0,0,PLAT_AP,LWIP_CORE,netif_find_2,P_INFO,swLogPrintf("netif_find : didn ' t find %c%u "); +293888,602075135,0,0,PLAT_AP,LWIP_CORE,netif_set_arp_reply_mode_1,P_ERROR,swLogPrintf("netif_remove_type : invalid netif point "); +293888,602075136,0,0,PLAT_AP,LWIP_CORE,netif_set_arp_reply_mode_2,P_INFO,swLogPrintf("netif_set_arp_reply_mode : : %d "); +293888,602079231,0,0,PLAT_AP,LWIP_CORE,netif_set_arp_reply_ignore_addr_1,P_ERROR,swLogPrintf("netif_set_arp_reply_ignore_addr : invalid netif point "); +293888,602081279,0,0,PLAT_AP,LWIP_CORE,netif_set_arp_reply_ignore_addr_2,P_INFO,swLogPrintf("netif_set_arp_reply_ignore_addr "); +293888,602081536,0,0,PLAT_AP,LWIP_CORE,netif_enter_oos_1,P_INFO,swLogPrintf("netif_enter_oos : netif enter oos %c%u "); +293888,602083584,0,0,PLAT_AP,LWIP_CORE,netif_exit_oos_1,P_INFO,swLogPrintf("netif_exit_oos : netif exit oos %c%u "); +293888,602087423,0,0,PLAT_AP,LWIP_CORE,netif_enable_timer_active_mask_1,P_ERROR,swLogPrintf("invalid argument "); +293888,602089471,0,0,PLAT_AP,LWIP_CORE,netif_disable_timer_active_mask_1,P_ERROR,swLogPrintf("invalid argument "); +293888,602089728,0,0,PLAT_AP,LWIP_CORE,netif_set_netif_type_1,P_INFO,swLogPrintf("netif_set_netif_type : netif 0x%x set net type %u "); +293888,602093567,0,0,PLAT_AP,LWIP_CORE,netif_find_by_wan_netif_1,P_INFO,swLogPrintf("netif_find_by_wan_netif : didn ' t wan netif "); +293888,602094080,0,0,PLAT_AP,LWIP_CORE,netif_find_by_cid_1,P_INFO,swLogPrintf("netif_find : found %c%u cid %u "); +293888,602095616,0,0,PLAT_AP,LWIP_CORE,netif_find_by_cid_2,P_INFO,swLogPrintf("netif_find : didn ' t find %d "); +293888,602098176,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ip4_cid_1,P_INFO,swLogPrintf("netif_find : found %c%u cid %u "); +293888,602099712,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ip4_cid_2,P_INFO,swLogPrintf("netif_find : didn ' t find %d "); +293888,602101760,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ded_cid_in_w_1,P_INFO,swLogPrintf("netif_find , invalid ded_cid : %d , can ' t found netif "); +293888,602103808,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ded_cid_1,P_INFO,swLogPrintf("netif_find , found netif via ded_cid : %d "); +293888,602105856,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ded_cid_w_1,P_INFO,swLogPrintf("netif_find : didn ' t find ded_cid : %d "); +293888,602108416,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ip6_cid_1,P_INFO,swLogPrintf("netif_find : found %c%u cid %u "); +293888,602109952,0,0,PLAT_AP,LWIP_CORE,netif_find_by_ip6_cid_2,P_INFO,swLogPrintf("netif_find : didn ' t find %d "); +293888,602112000,0,0,PLAT_AP,LWIP_CORE,NetGetLanTypeNetif_1,P_INFO,swLogPrintf("NetGetLanTypeNetif invalid type %u "); +293888,602116095,0,0,PLAT_AP,LWIP_CORE,netif_check_netif_type_1,P_INFO,swLogPrintf("netif_check_netif_type invalid parameter "); +293888,602118143,0,0,PLAT_AP,LWIP_CORE,netif_check_netif_type_is_wan_1,P_INFO,swLogPrintf("netif_check_netif_type invalid parameter "); +293888,602119168,0,0,PLAT_AP,LWIP_CORE,netif_add_ip6_prefix_info_1,P_INFO,swLogPrintf("netif_add_ip6_prefix_info : cid %u , state %u , source %u , life_time %u , active_time %u "); +293888,602122239,0,0,PLAT_AP,LWIP_CORE,netif_add_ip6_prefix_info_timeout_1,P_WARNING,swLogPrintf("netif_add_ip6_prefix_info life_time has timeout "); +293888,602124287,0,0,PLAT_AP,LWIP_CORE,netif_add_ip6_prefix_info_timeout_2,P_WARNING,swLogPrintf("netif_add_ip6_prefix_info life_time has timeout "); +293888,602126335,0,0,PLAT_AP,LWIP_CORE,netif_add_ip6_prefix_info_3,P_WARNING,swLogPrintf("netif_add_ip6_prefix_info malloc fail "); +293888,602126336,0,0,PLAT_AP,LWIP_CORE,netif_remove_ip6_prefix_info_1,P_INFO,swLogPrintf("netif_remove_ip6_prefix_info cid %u "); +293888,602128384,0,0,PLAT_AP,LWIP_CORE,netif_find_ip6_prefix_info_1,P_INFO,swLogPrintf("netif_find_ip6_prefix_info cid %u "); +293888,602132479,0,0,PLAT_AP,LWIP_CORE,netif_set_ipaddr_1,P_INFO,swLogPrintf("netif_set_ipaddr : netif address being changed "); +293888,602133760,0,0,PLAT_AP,LWIP_CORE,netif_set_ipaddr_2,P_INFO,swLogPrintf("netif : IP address of interface %c%u set to %u.%u.%u.%u "); +293888,602135808,0,0,PLAT_AP,LWIP_CORE,netif_set_gw_1,P_INFO,swLogPrintf("netif : GW address of interface %c%u set to %u.%u.%u.%u "); +293888,602137856,0,0,PLAT_AP,LWIP_CORE,netif_set_netmask_1,P_INFO,swLogPrintf("netif : netmask of interface %c%u set to %u.%u.%u.%u "); +293888,602138880,0,0,PLAT_AP,LWIP_CORE,netif_set_default_1,P_INFO,swLogPrintf("netif : setting default interface %c%u "); +293888,602142719,0,0,PLAT_AP,LWIP_CORE,netif_loop_output_1,P_ERROR,swLogPrintf("if first ! = NULL , last must also be ! = NULL "); +293888,602144767,0,0,PLAT_AP,LWIP_CORE,netif_poll_1,P_ERROR,swLogPrintf("bogus pbuf : len ! = tot_len but next = = NULL! "); +293888,602146815,0,0,PLAT_AP,LWIP_CORE,netif_poll_2,P_ERROR,swLogPrintf("netif->loop_cnt_current underflow "); +293888,602148863,0,0,PLAT_AP,LWIP_CORE,netif_poll_3,P_ERROR,swLogPrintf("should not be null since first ! = last! "); +293888,602150911,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_1,P_ERROR,swLogPrintf("addr6 ! = NULL "); +293888,602152959,0,0,PLAT_AP,LWIP_CORE,netif_ip6_prefx_length_set_1,P_ERROR,swLogPrintf("invalid netif "); +293888,602155007,0,0,PLAT_AP,LWIP_CORE,netif_ip6_prefix_length_get_1,P_ERROR,swLogPrintf("invalid netif "); +293888,602157055,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_parts_1,P_ERROR,swLogPrintf("addr6 ! = NULL or invalid index "); +293888,602159103,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_parts_2,P_INFO,swLogPrintf("netif_ip6_addr_set : netif address being changed "); +293888,602159872,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_parts_3,P_INFO,swLogPrintf("netif : IPv6 address %d of interface %c%u set to 0x%x "); +293888,602163199,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_state_1,P_ERROR,swLogPrintf("addr6 ! = NULL or invalid index "); +293888,602165247,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_state_2,P_INFO,swLogPrintf("netif_ip6_addr_set : netif address state being changed "); +293888,602166016,0,0,PLAT_AP,LWIP_CORE,netif_ip6_addr_set_state_3,P_INFO,swLogPrintf("netif : IPv6 address %d of interface %c%u set to 0x%x "); +293888,602167808,0,0,PLAT_AP,LWIP_CORE,pbuf_set_1,P_INFO,swLogPrintf("pbuf_set ( length = %u ) 0x%x type %d "); +293888,602171391,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_2,P_ERROR,swLogPrintf("pbuf_alloc : bad pbuf layer "); +293888,602171648,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_ps_dl_pkg_1,P_ERROR,swLogPrintf("LWIP , can ' t alloc pbuf from DL PKG MEM , layer : %d , size : %d "); +293888,602175487,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_5,P_ERROR,swLogPrintf("pbuf_alloc : pbuf->payload properly aligned "); +293888,602175488,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_6,P_WARNING,swLogPrintf("pbuf_alloc : Could not allocate MEMP_PBUF for PBUF type %d "); +293888,602177536,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_8,P_ERROR,swLogPrintf("LWIP , pbuf_alloc , erroneous type : %d "); +293888,602180096,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_9,P_INFO,swLogPrintf("pbuf_alloc 0x%x , the init ticktype %u , the dataLifeTime %u "); +293888,602182400,0,0,PLAT_AP,LWIP_CORE,pbuf_alloc_10,P_INFO,swLogPrintf("pbuf_alloc ( length = %u ) 0x%x layer ( %d ) type %d "); +293888,602183680,0,0,PLAT_AP,LWIP_CORE,pbuf_alloced_custom_1,P_INFO,swLogPrintf("pbuf_alloced_custom length %u "); +293888,602187775,0,0,PLAT_AP,LWIP_CORE,pbuf_alloced_custom_2,P_ERROR,swLogPrintf("pbuf_alloced_custom : bad pbuf layer "); +293888,602187776,0,0,PLAT_AP,LWIP_CORE,pbuf_alloced_custom_3,P_WARNING,swLogPrintf("pbuf_alloced_custom ( length = %u ) buffer too short "); +293888,602190080,0,0,PLAT_AP,LWIP_CORE,pbuf_realloc_w_1,P_INFO,swLogPrintf("LWIP , can ' t realloc pbuf , new_len : %d > = tot_len : %d "); +293888,602193919,0,0,PLAT_AP,LWIP_CORE,pbuf_realloc_2,P_ERROR,swLogPrintf("grow < max_u16_t "); +293888,602195967,0,0,PLAT_AP,LWIP_CORE,pbuf_realloc_3,P_ERROR,swLogPrintf("pbuf_realloc : q ! = NULL "); +293888,602198015,0,0,PLAT_AP,LWIP_CORE,pbuf_realloc_4,P_ERROR,swLogPrintf("mem_trim returned q = = NULL "); +293888,602200063,0,0,PLAT_AP,LWIP_CORE,pbuf_header_impl_1,P_ERROR,swLogPrintf("p ! = NULL "); +293888,602202111,0,0,PLAT_AP,LWIP_CORE,pbuf_header_impl_2,P_ERROR,swLogPrintf("increment_magnitude < = p->len "); +293888,602202368,0,0,PLAT_AP,LWIP_CORE,pbuf_header_impl_6,P_WARNING,swLogPrintf("pbuf_header : failed as 0x%x < 0x%x ( not enough space for new header size ) "); +293888,602204416,0,0,PLAT_AP,LWIP_CORE,pbuf_header_impl_3,P_WARNING,swLogPrintf("pbuf_header : failed as 0x%x < 0x%x ( not enough space for new header size ) "); +293888,602208255,0,0,PLAT_AP,LWIP_CORE,pbuf_header_impl_4,P_ERROR,swLogPrintf("bad pbuf type "); +293888,602208768,0,0,PLAT_AP,LWIP_CORE,pbuf_header_impl_5,P_INFO,swLogPrintf("pbuf_header : old 0x%x new 0x%x %d "); +293888,602212351,0,0,PLAT_AP,LWIP_CORE,pbuf_free_1,P_ERROR,swLogPrintf("LWIP , pbuf_free , invalid input : p = = NULL "); +293888,602212352,0,0,PLAT_AP,LWIP_CORE,pbuf_free_2,P_INFO,swLogPrintf("LWIP , pbuf_free : 0x%x "); +293888,602216447,0,0,PLAT_AP,LWIP_CORE,pbuf_free_4,P_ERROR,swLogPrintf("pbuf_free : p->ref > 0 "); +293888,602218495,0,0,PLAT_AP,LWIP_CORE,pbuf_free_e_5,P_ERROR,swLogPrintf("LWIP , can ' t free pbuf with type : PBUF_POOL , if PS DL PKG memory used "); +293888,602220543,0,0,PLAT_AP,LWIP_CORE,pbuf_ref_1,P_ERROR,swLogPrintf("pbuf ref overflow "); +293888,602222591,0,0,PLAT_AP,LWIP_CORE,pbuf_cat_1,P_ERROR,swLogPrintf("pbuf_cat invalid argument "); +293888,602224639,0,0,PLAT_AP,LWIP_CORE,pbuf_cat_2,P_ERROR,swLogPrintf("p->tot_len ! = p->len or p->next ! = NULL "); +293888,602224896,0,0,PLAT_AP,LWIP_CORE,pbuf_chain_1,P_INFO,swLogPrintf("pbuf_chain : 0x%x references 0x%x "); +293888,602228735,0,0,PLAT_AP,LWIP_CORE,pbuf_dechain_1,P_ERROR,swLogPrintf("p->tot_len = = p->len + q->tot_len "); +293888,602228736,0,0,PLAT_AP,LWIP_CORE,pbuf_dechain_2,P_INFO,swLogPrintf("pbuf_dechain : unreferencing 0x%x "); +293888,602230784,0,0,PLAT_AP,LWIP_CORE,pbuf_dechain_3,P_INFO,swLogPrintf("pbuf_dechain : deallocated 0x%x ( as it is no longer referenced ) "); +293888,602234879,0,0,PLAT_AP,LWIP_CORE,pbuf_dechain_4,P_ERROR,swLogPrintf("p->tot_len = = p->len "); +293888,602235136,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_1,P_INFO,swLogPrintf("pbuf_copy to 0x%x from 0x%x "); +293888,602238975,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_2,P_ERROR,swLogPrintf("pbuf_copy : target not big enough to hold source "); +293888,602241023,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_3,P_ERROR,swLogPrintf("offset_to > p_to->len or offset_from > p_from->len "); +293888,602243071,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_4,P_ERROR,swLogPrintf("p_to ! = NULL "); +293888,602245119,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_5,P_ERROR,swLogPrintf("pbuf_copy ( ) does not allow packet queues! "); +293888,602247167,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_6,P_ERROR,swLogPrintf("pbuf_copy ( ) does not allow packet queues! "); +293888,602249215,0,0,PLAT_AP,LWIP_CORE,pbuf_copy_partial_1,P_ERROR,swLogPrintf("pbuf_copy_partial : invalid buf or dataptr "); +293888,602251263,0,0,PLAT_AP,LWIP_CORE,updateSequenceBitmap_1,P_ERROR,swLogPrintf("updateSequenceBitmap parameter invalid "); +293888,602253311,0,0,PLAT_AP,LWIP_CORE,getSequenceBitmap_1,P_ERROR,swLogPrintf("getSequenceBitmap parameter invalid "); +293888,602255359,0,0,PLAT_AP,LWIP_CORE,pbuf_split_64k_1,P_ERROR,swLogPrintf("tot_len / len mismatch in last pbuf "); +293888,602257407,0,0,PLAT_AP,LWIP_CORE,pbuf_take_1,P_ERROR,swLogPrintf("pbuf_take : invalid buf or dataptr "); +293888,602259455,0,0,PLAT_AP,LWIP_CORE,pbuf_take_2,P_ERROR,swLogPrintf("pbuf_take : buf not large enough "); +293888,602261503,0,0,PLAT_AP,LWIP_CORE,pbuf_take_3,P_ERROR,swLogPrintf("pbuf_take : invalid pbuf "); +293888,602263551,0,0,PLAT_AP,LWIP_CORE,pbuf_take_4,P_ERROR,swLogPrintf("did not copy all data "); +293888,602265599,0,0,PLAT_AP,LWIP_CORE,pbuf_coalesce_1,P_ERROR,swLogPrintf("pbuf_copy failed "); +293888,602267647,0,0,PLAT_AP,LWIP_CORE,raw_input_1,P_ERROR,swLogPrintf("raw pcb recv callback altered pbuf payload pointer without eating packet "); +293888,602269695,0,0,PLAT_AP,LWIP_CORE,raw_sendto_1,P_INFO,swLogPrintf("raw_sendto "); +293888,602271743,0,0,PLAT_AP,LWIP_CORE,raw_sendto_5,P_WARNING,swLogPrintf("raw_sendto : No route to "); +293888,602273791,0,0,PLAT_AP,LWIP_CORE,raw_sendto_2,P_WARNING,swLogPrintf("raw_sendto : could not allocate header "); +293888,602274048,0,0,PLAT_AP,LWIP_CORE,raw_sendto_3,P_INFO,swLogPrintf("raw_sendto : added header pbuf 0x%x before given pbuf 0x%x "); +293888,602277887,0,0,PLAT_AP,LWIP_CORE,raw_sendto_4,P_ERROR,swLogPrintf("Can ' t restore header we just removed "); +293888,602279935,0,0,PLAT_AP,LWIP_CORE,raw_sendto_7,P_WARNING,swLogPrintf("Checksum must fit into first pbuf "); +293888,602281983,0,0,PLAT_AP,LWIP_CORE,raw_new_1,P_INFO,swLogPrintf("raw_new "); +293888,602281984,0,0,PLAT_AP,LWIP_CORE,raw_netif_enter_oos_state_1,P_INFO,swLogPrintf("raw_netif_enter_oos_state 0x%x "); +293888,602284032,0,0,PLAT_AP,LWIP_CORE,raw_netif_exit_oos_state_1,P_INFO,swLogPrintf("raw_netif_exit_oos_state 0x%x "); +293888,602286592,0,0,PLAT_AP,LWIP_CORE,TCP_REG_1,P_INFO,swLogPrintf("TCP_REG 0x%x local port %d to 0x%x "); +293888,602290175,0,0,PLAT_AP,LWIP_CORE,TCP_REG_2,P_ERROR,swLogPrintf("TCP_REG : tcp_tmp_pcb = = ( npcb ) "); +293888,602292223,0,0,PLAT_AP,LWIP_CORE,TCP_REG_3,P_ERROR,swLogPrintf("TCP_REG : pcb->state = = CLOSED "); +293888,602294271,0,0,PLAT_AP,LWIP_CORE,TCP_REG_4,P_ERROR,swLogPrintf("TCP_REG : npcb->next = = npcb "); +293888,602296319,0,0,PLAT_AP,LWIP_CORE,TCP_REG_5,P_ERROR,swLogPrintf("TCP_REG : tcp_pcbs sane "); +293888,602298367,0,0,PLAT_AP,LWIP_CORE,TCP_RMV_1,P_ERROR,swLogPrintf("TCP_RMV : pcbs = = NULL "); +293888,602298624,0,0,PLAT_AP,LWIP_CORE,TCP_RMV_2,P_INFO,swLogPrintf("TCP_RMV removing 0x%x from 0x%x "); +293888,602302463,0,0,PLAT_AP,LWIP_CORE,TCP_RMV_3,P_ERROR,swLogPrintf("TCP_RMV : tcp_pcbs sane "); +293888,602302464,0,0,PLAT_AP,LWIP_CORE,tcp_add_curr_hib_sleep2_pcb_num_1,P_INFO,swLogPrintf("tcp_add_curr_hib_sleep2_pcb_num %u "); +293888,602304512,0,0,PLAT_AP,LWIP_CORE,tcp_del_curr_hib_sleep2_pcb_num_1,P_INFO,swLogPrintf("tcp_del_curr_hib_sleep2_pcb_num %u "); +293888,602306560,0,0,PLAT_AP,LWIP_CORE,tcp_enable_hib_sleep2_mode_1,P_INFO,swLogPrintf("tcp_enable_hib_sleep2_mode %u "); +293888,602308608,0,0,PLAT_AP,LWIP_CORE,tcp_disable_hib_sleep2_mode_1,P_INFO,swLogPrintf("tcp_disable_hib_sleep2_mode %u "); +293888,602310656,0,0,PLAT_AP,LWIP_CORE,tcp_add_hib_sleep2_context_pcb_1,P_INFO,swLogPrintf("tcp_add_hib_sleep2_context_pcb alloc new tcp_pcb success , sockid %d "); +293888,602314751,0,0,PLAT_AP,LWIP_CORE,tcp_add_hib_sleep2_context_pcb_2,P_ERROR,swLogPrintf("tcp_add_hib_sleep2_context_pcb alloc new tcp_pcb fail "); +293888,602316799,0,0,PLAT_AP,LWIP_CORE,tcp_check_hib_sleep2_pcb_active_1,P_INFO,swLogPrintf("tcp_check_hib_sleep2_pcb_active "); +293888,602316800,0,0,PLAT_AP,LWIP_CORE,tcp_check_hib_sleep2_pcb_active_2,P_INFO,swLogPrintf("tcp_check_hib_sleep2_pcb_active change pcb 0x%x state to enable_active state "); +293888,602320895,0,0,PLAT_AP,LWIP_CORE,tcp_check_hib_sleep2_pcb_deactive_1,P_INFO,swLogPrintf("tcp_check_hib_sleep2_pcb_deactive "); +293888,602320896,0,0,PLAT_AP,LWIP_CORE,tcp_check_hib_sleep2_pcb_deactive_2,P_INFO,swLogPrintf("tcp_check_hib_sleep2_pcb_deactive change pcb 0x%x state to enable_deactive state "); +293888,602324991,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_1,P_ERROR,swLogPrintf("tcp_get_sock_info invalid fd "); +293888,602327039,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_2,P_INFO,swLogPrintf("tcp_get_sock_info find adpat tcp hib pcb "); +293888,602329087,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_3,P_INFO,swLogPrintf("tcp_get_sock_info can not find adpat tcp hib pcb "); +293888,602331135,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_by_pcb_1,P_ERROR,swLogPrintf("tcp_get_sock_info_by_pcb invalid parameter "); +293888,602333183,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_by_pcb_2,P_INFO,swLogPrintf("tcp_get_sock_info_by_pcb find adpat tcppcb "); +293888,602335231,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_by_pcb_3,P_INFO,swLogPrintf("tcp_get_sock_info_by_pcb find adpat tcp hib pcb "); +293888,602337279,0,0,PLAT_AP,LWIP_CORE,tcp_get_sock_info_by_pcb_4,P_INFO,swLogPrintf("tcp_get_sock_info_by_pcb can not find adpat tcp hib pcb "); +293888,602339327,0,0,PLAT_AP,LWIP_CORE,tcp_listen_closed_1,P_ERROR,swLogPrintf("pcb = = NULL or pcb->state ! = LISTEN "); +293888,602341375,0,0,PLAT_AP,LWIP_CORE,tcp_backlog_delayed_1,P_ERROR,swLogPrintf("pcb = = NULL "); +293888,602343423,0,0,PLAT_AP,LWIP_CORE,tcp_backlog_delayed_2,P_ERROR,swLogPrintf("accepts_pending ! = 0 "); +293888,602345471,0,0,PLAT_AP,LWIP_CORE,tcp_backlog_accepted_1,P_ERROR,swLogPrintf("pcb = = NULL "); +293888,602347519,0,0,PLAT_AP,LWIP_CORE,tcp_backlog_accepted_2,P_ERROR,swLogPrintf("accepts_pending ! = 0 "); +293888,602349567,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_5,P_SIG,swLogPrintf("tcp_close_shutdown THE hib / sleep2 tcp context pcb will shutdown "); +293888,602351615,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_1,P_ERROR,swLogPrintf("pcb->flags & TF_RXCLOSED "); +293888,602353663,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_2,P_INFO,swLogPrintf("remove tcp keepalive timer "); +293888,602353664,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_3,P_INFO,swLogPrintf("enable tcp time_wait timer %u "); +293888,602357759,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_4,P_INFO,swLogPrintf("tcp time_wait timer has active "); +293888,602359807,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_1,P_ERROR,swLogPrintf("pcb ! = NULL "); +293888,602361855,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_2,P_INFO,swLogPrintf("remove tcp sync rcv timer "); +293888,602363903,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_3,P_INFO,swLogPrintf("remove tcp keepalive timer "); +293888,602365951,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_4,P_INFO,swLogPrintf("remove tcp delay ack timer "); +293888,602365952,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_5,P_INFO,swLogPrintf("enable tcp last ack timer %u "); +293888,602368000,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_local_abort_time,P_INFO,swLogPrintf("enable tcp close local abort time %u "); +293888,602370048,0,0,PLAT_AP,LWIP_CORE,tcp_close_shutdown_fin_6,P_INFO,swLogPrintf("enable tcp pending fin timer %u "); +293888,602374143,0,0,PLAT_AP,LWIP_CORE,tcp_close_1,P_INFO,swLogPrintf("tcp_close : closing in "); +293888,602376191,0,0,PLAT_AP,LWIP_CORE,tcp_shutdown_1,P_INFO,swLogPrintf("remove tcp refuse data timer "); +293888,602378239,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_12,P_SIG,swLogPrintf("tcp_abandon THE hib / sleep2 tcp context pcb will abandon "); +293888,602380287,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_1,P_ERROR,swLogPrintf("don ' t call tcp_abort / tcp_abandon for listen-pcbs "); +293888,602382335,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_2,P_INFO,swLogPrintf("remove time wait timer "); +293888,602384383,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_3,P_INFO,swLogPrintf("remove tcp keepalive timer "); +293888,602386431,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_4,P_INFO,swLogPrintf("remove tcp syncrcv timer "); +293888,602388479,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_5,P_INFO,swLogPrintf("remove tcp last ack timer "); +293888,602390527,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_6,P_INFO,swLogPrintf("remove tcp FIN_WAIT2 timer "); +293888,602392575,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_tcp_total_retry_time_1,P_INFO,swLogPrintf("remove tcp total retry timer "); +293888,602392576,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_tcp_retry_time_1,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602396671,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_tcp_poll_time_1,P_INFO,swLogPrintf("remove tcp poll timer "); +293888,602398719,0,0,PLAT_AP,LWIP_CORE,tcp_abandon_11,P_INFO,swLogPrintf("tcp_abandon : sending RST "); +293888,602400767,0,0,PLAT_AP,LWIP_CORE,tcp_bind_1,P_ERROR,swLogPrintf("tcp_bind : can only bind in state CLOSED "); +293888,602400768,0,0,PLAT_AP,LWIP_CORE,tcp_bind_2,P_INFO,swLogPrintf("tcp_bind : bind to port %u "); +293888,602404863,0,0,PLAT_AP,LWIP_CORE,tcp_listen_with_backlog_and_err_1,P_ERROR,swLogPrintf("tcp_listen : pcb already connected "); +293888,602406911,0,0,PLAT_AP,LWIP_CORE,tcp_recved_1,P_ERROR,swLogPrintf("don ' t call tcp_recved for listen-pcbs "); +293888,602408959,0,0,PLAT_AP,LWIP_CORE,tcp_recved_2,P_ERROR,swLogPrintf("tcp_recved : len wrapped rcv_wnd "); +293888,602409472,0,0,PLAT_AP,LWIP_CORE,tcp_recved_3,P_INFO,swLogPrintf("tcp_recved : received ( %u ) bytes , wnd ( %u ) %u "); +293888,602413055,0,0,PLAT_AP,LWIP_CORE,tcp_connect_1,P_ERROR,swLogPrintf("tcp_connect : can only connect from state CLOSED "); +293888,602413056,0,0,PLAT_AP,LWIP_CORE,tcp_connect_2,P_INFO,swLogPrintf("tcp_connect to port %u "); +293888,602417151,0,0,PLAT_AP,LWIP_CORE,tcp_connect_3,P_SIG,swLogPrintf("tcp_connect : pcb has connected "); +293888,602419199,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_1,P_INFO,swLogPrintf("tcp_slowtmr : no active pcbs "); +293888,602421247,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_2,P_ERROR,swLogPrintf("tcp_slowtmr : active pcb->state inlavid "); +293888,602423295,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_3,P_INFO,swLogPrintf("tcp_slowtmr : max SYN retries reached "); +293888,602425343,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_4,P_INFO,swLogPrintf("tcp_slowtmr : max DATA retries reached "); +293888,602425600,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_5,P_INFO,swLogPrintf("tcp_slowtmr : rtime %u pcb->rto %u "); +293888,602427648,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_6,P_INFO,swLogPrintf("tcp_slowtmr : cwnd %u ssthresh %u "); +293888,602431487,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_7,P_INFO,swLogPrintf("tcp_slowtmr : removing pcb stuck in FIN-WAIT-2 "); +293888,602433535,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_8,P_INFO,swLogPrintf("tcp_slowtmr : KEEPALIVE timeout. Aborting connection to "); +293888,602435583,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_9,P_INFO,swLogPrintf("tcp_slowtmr : dropping OOSEQ queued data "); +293888,602437631,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_10,P_INFO,swLogPrintf("tcp_slowtmr : removing pcb stuck in SYN-RCVD "); +293888,602439679,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_11,P_INFO,swLogPrintf("tcp_slowtmr : removing pcb stuck in LAST-ACK "); +293888,602441727,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_12,P_ERROR,swLogPrintf("tcp_slowtmr : middle tcp ! = tcp_active_pcbs "); +293888,602443775,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_13,P_ERROR,swLogPrintf("tcp_slowtmr : first pcb = = tcp_active_pcbs "); +293888,602445823,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_14,P_INFO,swLogPrintf("tcp_slowtmr : polling application "); +293888,602447871,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_15,P_ERROR,swLogPrintf("tcp_slowtmr : TIME-WAIT pcb->state = = TIME-WAIT "); +293888,602449919,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_16,P_ERROR,swLogPrintf("tcp_slowtmr : middle tcp ! = tcp_tw_pcbs "); +293888,602451967,0,0,PLAT_AP,LWIP_CORE,tcp_slowtmr_17,P_ERROR,swLogPrintf("tcp_slowtmr : first pcb = = tcp_tw_pcbs "); +293888,602454015,0,0,PLAT_AP,LWIP_CORE,tcp_fasttmr_1,P_INFO,swLogPrintf("tcp_fasttmr : delayed ACK "); +293888,602456063,0,0,PLAT_AP,LWIP_CORE,tcp_fasttmr_2,P_INFO,swLogPrintf("tcp_fasttmr : pending FIN "); +293888,602458111,0,0,PLAT_AP,LWIP_CORE,tcp_enable_timer_active_mask_1,P_ERROR,swLogPrintf("invalid argument "); +293888,602460159,0,0,PLAT_AP,LWIP_CORE,tcp_disable_timer_active_mask_1,P_ERROR,swLogPrintf("invalid argument "); +293888,602460416,0,0,PLAT_AP,LWIP_CORE,tcp_remove_pcb_1,P_INFO,swLogPrintf("tcp_remove_pcb remove pcb 0x%x from list 0x%x "); +293888,602462720,0,0,PLAT_AP,LWIP_CORE,tcp_remove_pcb_2,P_INFO,swLogPrintf("tcp_remove_pcb send error %d event success , err fn 0x%x , err_arg 0x%x "); +293888,602466303,0,0,PLAT_AP,LWIP_CORE,tcp_delay_ack_handler_1,P_INFO,swLogPrintf("tcp_delay_ack_handler timeout "); +293888,602468351,0,0,PLAT_AP,LWIP_CORE,tcp_delay_ack_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602470399,0,0,PLAT_AP,LWIP_CORE,tcp_pending_fin_handler_1,P_INFO,swLogPrintf("tcp_pending_fin_handler timeout "); +293888,602472447,0,0,PLAT_AP,LWIP_CORE,tcp_pending_fin_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602474495,0,0,PLAT_AP,LWIP_CORE,tcp_refused_data_handler_1,P_INFO,swLogPrintf("tcp_refused_data_handler timeout "); +293888,602476543,0,0,PLAT_AP,LWIP_CORE,tcp_refused_data_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602478591,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_1,P_INFO,swLogPrintf("tcp_retry_timeout_handler timeout "); +293888,602480639,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602482687,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_3,P_ERROR,swLogPrintf("tcp_retry_timeout_handler : active pcb->state inlavid "); +293888,602484735,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_4,P_INFO,swLogPrintf("tcp_retry_timeout_handler : max SYN retries reached "); +293888,602486783,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_5,P_INFO,swLogPrintf("tcp_retry_timeout_handler : max DATA retries reached "); +293888,602487040,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_6,P_INFO,swLogPrintf("active tcp retry timer %u , pcb 0x%x "); +293888,602489600,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_7,P_INFO,swLogPrintf("tcp_retry_timeout_handler : pcb->rto %u nrtx %u sa %d sv %d "); +293888,602491136,0,0,PLAT_AP,LWIP_CORE,tcp_retry_timeout_handler_8,P_INFO,swLogPrintf("tcp_retry_timeout_handler : cwnd %u ssthresh %u "); +293888,602494975,0,0,PLAT_AP,LWIP_CORE,tcp_total_retry_timeout_handler_1,P_INFO,swLogPrintf("tcp_total_retry_timeout_handler timeout "); +293888,602497023,0,0,PLAT_AP,LWIP_CORE,tcp_total_retry_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602499071,0,0,PLAT_AP,LWIP_CORE,tcp_total_retry_timeout_handler_3,P_ERROR,swLogPrintf("tcp_total_retry_timeout_handler : active pcb->state inlavid "); +293888,602501119,0,0,PLAT_AP,LWIP_CORE,tcp_fin_wait2_timeout_handler_1,P_INFO,swLogPrintf("tcp_fin_wait2_timeout_handler timeout "); +293888,602503167,0,0,PLAT_AP,LWIP_CORE,tcp_fin_wait2_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602505215,0,0,PLAT_AP,LWIP_CORE,tcp_fin_wait2_timeout_handler_3,P_INFO,swLogPrintf("tcp_fin_wait2_timeout_handler : removing pcb stuck in FIN-WAIT-2 "); +293888,602507263,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_timeout_handler_1,P_INFO,swLogPrintf("tcp_keepalive_timeout_handler timeout "); +293888,602509311,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602511359,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_timeout_handler_3,P_INFO,swLogPrintf("tcp_keepalive_timeout_handler : KEEPALIVE timeout. Aborting connection to "); +293888,602511616,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_timeout_handler_4,P_INFO,swLogPrintf("active tcp keepalive intvl timer %u , send cnt %u "); +293888,602515455,0,0,PLAT_AP,LWIP_CORE,tcp_ooseq_timeout_handler_1,P_INFO,swLogPrintf("tcp_ooseq_timeout_handler timeout "); +293888,602517503,0,0,PLAT_AP,LWIP_CORE,tcp_ooseq_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602519551,0,0,PLAT_AP,LWIP_CORE,tcp_ooseq_timeout_handler_3,P_INFO,swLogPrintf("tcp_ooseq_timeout_handler : dropping OOSEQ queued data "); +293888,602521599,0,0,PLAT_AP,LWIP_CORE,tcp_syncrcv_timeout_handler_1,P_INFO,swLogPrintf("tcp_syncrcv_timeout_handler timeout "); +293888,602523647,0,0,PLAT_AP,LWIP_CORE,tcp_syncrcv_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602525695,0,0,PLAT_AP,LWIP_CORE,tcp_syncrcv_timeout_handler_3,P_INFO,swLogPrintf("tcp_syncrcv_timeout_handler : removing pcb stuck in SYN-RCVD "); +293888,602527743,0,0,PLAT_AP,LWIP_CORE,tcp_lastack_timeout_handler_1,P_INFO,swLogPrintf("tcp_lastack_timeout_handler timeout "); +293888,602529791,0,0,PLAT_AP,LWIP_CORE,tcp_lastack_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602531839,0,0,PLAT_AP,LWIP_CORE,tcp_lastack_timeout_handler_3,P_INFO,swLogPrintf("tcp_lastack_timeout_handler : removing pcb stuck in LAST-ACK "); +293888,602533887,0,0,PLAT_AP,LWIP_CORE,tcp_timewait_timeout_handler_1,P_INFO,swLogPrintf("tcp_timewait_timeout_handler timeout "); +293888,602535935,0,0,PLAT_AP,LWIP_CORE,tcp_timewait_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602537983,0,0,PLAT_AP,LWIP_CORE,tcp_timewait_timeout_handler_3,P_INFO,swLogPrintf("tcp_timewait_timeout_handler : removing pcb in time wait state "); +293888,602540031,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_1,P_INFO,swLogPrintf("tcp_remove_all_timer invalid pcb point "); +293888,602542079,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_12,P_INFO,swLogPrintf("remove tcp total retry timer "); +293888,602542080,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_2,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602546175,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_3,P_INFO,swLogPrintf("remove delay ack timer "); +293888,602548223,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_4,P_INFO,swLogPrintf("remove tcp pending fin timer "); +293888,602550271,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_5,P_INFO,swLogPrintf("remove tcp refuse data timer "); +293888,602552319,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_6,P_INFO,swLogPrintf("remove tcp fin wait2 timer "); +293888,602554367,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_7,P_INFO,swLogPrintf("remove tcp keepalive timer "); +293888,602556415,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_8,P_INFO,swLogPrintf("remove tcp ooseq timer "); +293888,602558463,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_9,P_INFO,swLogPrintf("remove tcp syncrcv timer "); +293888,602560511,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_10,P_INFO,swLogPrintf("remove tcp lastack timer "); +293888,602562559,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_11,P_INFO,swLogPrintf("remove tcp timewait timer "); +293888,602564607,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_13,P_INFO,swLogPrintf("remove tcp poll timer "); +293888,602566655,0,0,PLAT_AP,LWIP_CORE,tcp_remove_all_timer_14,P_INFO,swLogPrintf("remove tcp close local abort timer "); +293888,602568703,0,0,PLAT_AP,LWIP_CORE,tcp_close_local_abort_timeout_handler_1,P_INFO,swLogPrintf("tcp_close_local_abort_timeout_handler timeout "); +293888,602570751,0,0,PLAT_AP,LWIP_CORE,tcp_close_local_abort_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602572799,0,0,PLAT_AP,LWIP_CORE,tcp_close_local_abort_timeout_handler_3,P_ERROR,swLogPrintf("tcp_close_local_abort_timeout_handler : pcb->state inlavid "); +293888,602574847,0,0,PLAT_AP,LWIP_CORE,tcp_close_local_abort_timeout_handler_4,P_INFO,swLogPrintf("remove tcp timewait timer "); +293888,602576895,0,0,PLAT_AP,LWIP_CORE,tcp_poll_timeout_handler_1,P_INFO,swLogPrintf("tcp_poll_timeout_handler timeout "); +293888,602578943,0,0,PLAT_AP,LWIP_CORE,tcp_poll_timeout_handler_2,P_ERROR,swLogPrintf("invalid argument "); +293888,602578944,0,0,PLAT_AP,LWIP_CORE,tcp_poll_timeout_handler_3,P_INFO,swLogPrintf("tcp_poll_timeout_handler poll result %d "); +293888,602583039,0,0,PLAT_AP,LWIP_CORE,tcp_active_poll_timeout_timer_1,P_ERROR,swLogPrintf("invalid argument "); +293888,602585087,0,0,PLAT_AP,LWIP_CORE,tcp_active_poll_timeout_timer_2,P_INFO,swLogPrintf("tcp_active_poll_timeout_timer poll timeout timer has active "); +293888,602585344,0,0,PLAT_AP,LWIP_CORE,tcp_active_poll_timeout_timer_3,P_INFO,swLogPrintf("active tcp poll timeour timer %u seconds , pcb 0x%x "); +293888,602589183,0,0,PLAT_AP,LWIP_CORE,tcp_disable_keepalive_time_1,P_ERROR,swLogPrintf("invalid argument "); +293888,602591231,0,0,PLAT_AP,LWIP_CORE,tcp_disable_keepalive_time_2,P_INFO,swLogPrintf("remove tcp keepalive timer "); +293888,602593279,0,0,PLAT_AP,LWIP_CORE,tcp_send_unack_ul_state_1,P_ERROR,swLogPrintf("tcp_send_unack_ul_state : pcb invalid "); +293888,602595327,0,0,PLAT_AP,LWIP_CORE,tcp_send_unack_ul_state_2,P_ERROR,swLogPrintf("tcp_send_unack_ul_state : the pcb socketid is invalid "); +293888,602595328,0,0,PLAT_AP,LWIP_CORE,tcp_send_unack_ul_state_3,P_INFO,swLogPrintf("tcp_send_unack_ul_state : UL sequence state indicate success , the pcb socket id %u "); +293888,602599423,0,0,PLAT_AP,LWIP_CORE,tcp_set_max_retry_times_1,P_ERROR,swLogPrintf("tcp_set_max_retry_times : pcb invalid "); +293888,602599424,0,0,PLAT_AP,LWIP_CORE,tcp_set_max_retry_times_2,P_ERROR,swLogPrintf("tcp_set_max_retry_times : invalid tcp max retry times %u "); +293888,602603519,0,0,PLAT_AP,LWIP_CORE,tcp_set_max_total_retry_time_1,P_ERROR,swLogPrintf("tcp_set_max_total_retry_time : pcb invalid "); +293888,602603520,0,0,PLAT_AP,LWIP_CORE,tcp_set_max_total_retry_time_2,P_ERROR,swLogPrintf("tcp_set_max_total_retry_time : invalid tcp max total retry time %u "); +293888,602607615,0,0,PLAT_AP,LWIP_CORE,tcp_set_init_retry_time_1,P_ERROR,swLogPrintf("tcp_set_init_retry_time : pcb invalid "); +293888,602607616,0,0,PLAT_AP,LWIP_CORE,tcp_set_init_retry_time_2,P_ERROR,swLogPrintf("tcp_set_init_retry_time : invalid tcp init retry times %u "); +293888,602611711,0,0,PLAT_AP,LWIP_CORE,tcp_ack_1,P_WARNING,swLogPrintf("tcp_ack : pcb invalid "); +293888,602613759,0,0,PLAT_AP,LWIP_CORE,tcp_ack_2,P_INFO,swLogPrintf("tcp delay ack timer has enable "); +293888,602613760,0,0,PLAT_AP,LWIP_CORE,tcp_ack_3,P_INFO,swLogPrintf("enable tcp delay ack timer %u "); +293888,602617855,0,0,PLAT_AP,LWIP_CORE,tcp_ack_now_1,P_WARNING,swLogPrintf("tcp_ack_now : pcb invalid "); +293888,602619903,0,0,PLAT_AP,LWIP_CORE,tcp_ack_now_2,P_INFO,swLogPrintf("tcp delay ack timer has enable , remove it "); +293888,602621951,0,0,PLAT_AP,LWIP_CORE,tcp_process_refused_data_1,P_INFO,swLogPrintf("tcp_input : notify kept packet "); +293888,602623999,0,0,PLAT_AP,LWIP_CORE,tcp_process_refused_data_2,P_INFO,swLogPrintf("tcp_input : drop incoming packets , because pcb is full "); +293888,602624000,0,0,PLAT_AP,LWIP_CORE,tcp_process_refused_data_3,P_INFO,swLogPrintf("enable tcp refse data timer %u "); +293888,602626304,0,0,PLAT_AP,LWIP_CORE,tcp_kill_prio_1,P_INFO,swLogPrintf("tcp_kill_prio : killing oldest PCB 0x%x ( %u ) "); +293888,602630143,0,0,PLAT_AP,LWIP_CORE,tcp_kill_state_1,P_INFO,swLogPrintf("tcp_kill_state invalid state "); +293888,602630656,0,0,PLAT_AP,LWIP_CORE,tcp_kill_state_2,P_INFO,swLogPrintf("tcp_kill_closing : killing oldest %d PCB 0x%x ( %u ) "); +293888,602632448,0,0,PLAT_AP,LWIP_CORE,tcp_kill_timewait_1,P_INFO,swLogPrintf("tcp_kill_timewait : killing oldest TIME-WAIT PCB 0x%x ( %u ) "); +293888,602636287,0,0,PLAT_AP,LWIP_CORE,tcp_alloc_1,P_INFO,swLogPrintf("tcp_alloc : killing off oldest TIME-WAIT connection "); +293888,602638335,0,0,PLAT_AP,LWIP_CORE,tcp_alloc_2,P_INFO,swLogPrintf("tcp_alloc : killing off oldest LAST-ACK connection "); +293888,602640383,0,0,PLAT_AP,LWIP_CORE,tcp_alloc_3,P_INFO,swLogPrintf("tcp_alloc : killing off oldest CLOSING connection "); +293888,602640384,0,0,PLAT_AP,LWIP_CORE,tcp_alloc_4,P_INFO,swLogPrintf("tcp_alloc : killing connection with prio lower than %d "); +293888,602642432,0,0,PLAT_AP,LWIP_CORE,tcp_alloc_5,P_INFO,swLogPrintf("tcp_alloc : current UE packet delay %u "); +293888,602646527,0,0,PLAT_AP,LWIP_CORE,tcp_recv_1,P_ERROR,swLogPrintf("invalid socket state for recv callback "); +293888,602648575,0,0,PLAT_AP,LWIP_CORE,tcp_sent_1,P_ERROR,swLogPrintf("invalid socket state for sent callback "); +293888,602650623,0,0,PLAT_AP,LWIP_CORE,tcp_err_1,P_ERROR,swLogPrintf("invalid socket state for err callback "); +293888,602652671,0,0,PLAT_AP,LWIP_CORE,tcp_poll_1,P_ERROR,swLogPrintf("invalid socket state for poll "); +293888,602654719,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_1,P_INFO,swLogPrintf("tcp_pcb_purge "); +293888,602656767,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_2,P_INFO,swLogPrintf("tcp_pcb_purge : data left on ->refused_data "); +293888,602658815,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_3,P_INFO,swLogPrintf("tcp_pcb_purge : not all data sent "); +293888,602660863,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_4,P_INFO,swLogPrintf("tcp_pcb_purge : data left on ->unacked "); +293888,602662911,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_5,P_INFO,swLogPrintf("tcp_pcb_purge : data left on ->ooseq "); +293888,602664959,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_6,P_INFO,swLogPrintf("remove tcp refuse data timer "); +293888,602667007,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_10,P_INFO,swLogPrintf("remove tcp total retry timer "); +293888,602667008,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_7,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602671103,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_8,P_INFO,swLogPrintf("remove tcp ooseq timer "); +293888,602673151,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_9,P_INFO,swLogPrintf("remove fin wait2 timer "); +293888,602675199,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_last_ack_1,P_INFO,swLogPrintf("remove last ack timer "); +293888,602677247,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_close_local_abort,P_INFO,swLogPrintf("remove close local abort timer "); +293888,602679295,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_close_sync_rcv,P_INFO,swLogPrintf("remove sync rcv timer "); +293888,602681343,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_poll,P_INFO,swLogPrintf("remove tcp poll timer "); +293888,602683391,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_purge_11,P_SIG,swLogPrintf("tcp_pcb_purge THE hib / sleep2 tcp context pcb will shutdown "); +293888,602685439,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_remove_4,P_INFO,swLogPrintf("remove tcp delay ack timer "); +293888,602687487,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_remove_1,P_ERROR,swLogPrintf("unsent or unacked segments leaking "); +293888,602689535,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_remove_2,P_ERROR,swLogPrintf("ooseq segments leaking "); +293888,602691583,0,0,PLAT_AP,LWIP_CORE,tcp_pcb_remove_3,P_ERROR,swLogPrintf("tcp_pcb_remove : tcp_pcbs_sane "); +293888,602691584,0,0,PLAT_AP,LWIP_CORE,tcp_eff_send_mss_impl_1,P_INFO,swLogPrintf("netif_set_ipaddr : aborting TCP pcb 0x%x "); +293888,602693632,0,0,PLAT_AP,LWIP_CORE,tcp_netif_ip_addr_changed_1,P_INFO,swLogPrintf("tcp_netif_ip_addr_changed : aborting TCP hib pcb 0x%x "); +293888,602695680,0,0,PLAT_AP,LWIP_CORE,tcp_netif_enter_oos_state_1,P_INFO,swLogPrintf("tcp pcb 0x%x enter oos state event "); +293888,602697728,0,0,PLAT_AP,LWIP_CORE,tcp_netif_exit_oos_state_1,P_INFO,swLogPrintf("tcp pcb 0x%x exit oos state event "); +293888,602701823,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_1,P_INFO,swLogPrintf("TCP header : "); +293888,602702080,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_2,P_INFO,swLogPrintf("| %u | %u | ( src port , dest port ) "); +293888,602704128,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_3,P_INFO,swLogPrintf("| %u | %u | ( seq no ) ( ack no ) "); +293888,602707712,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_4,P_INFO,swLogPrintf("|%u|%u%u%u%u%u%u|%u| ( seq no ) ( hdrlen flags wnd ) "); +293888,602708224,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_5,P_INFO,swLogPrintf("| %u | %u | ( chksum , urgp ) "); +293888,602710016,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_state_1,P_INFO,swLogPrintf("State : %d "); +293888,602714111,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_1,P_INFO,swLogPrintf("FIN "); +293888,602716159,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_2,P_INFO,swLogPrintf("SYN "); +293888,602718207,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_3,P_INFO,swLogPrintf("RST "); +293888,602720255,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_4,P_INFO,swLogPrintf("PSH "); +293888,602722303,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_5,P_INFO,swLogPrintf("PSH "); +293888,602724351,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_6,P_INFO,swLogPrintf("URG "); +293888,602726399,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_7,P_INFO,swLogPrintf("ECE "); +293888,602728447,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_flags_8,P_INFO,swLogPrintf("CWR "); +293888,602729216,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_pcbs_1,P_INFO,swLogPrintf("Active PCB Local port ( %u ) foreign port ( %u ) snd_nxt ( %u ) rcv_nxt ( %u ) "); +293888,602730496,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_pcbs_2,P_INFO,swLogPrintf("Listen PCB Local port %u "); +293888,602733312,0,0,PLAT_AP,LWIP_CORE,tcp_debug_print_pcbs_3,P_INFO,swLogPrintf("TIME-WAIT PCB Local port ( %u ) foreign port ( %u ) snd_nxt ( %u ) rcv_nxt ( %u ) "); +293888,602736639,0,0,PLAT_AP,LWIP_CORE,tcp_pcbs_sane_1,P_ERROR,swLogPrintf("tcp_pcbs_sane "); +293888,602738687,0,0,PLAT_AP,LWIP_CORE,tcp_pcbs_sane_2,P_ERROR,swLogPrintf("tcp_pcbs_sane : tw pcb->state = = TIME-WAIT "); +293888,602738688,0,0,PLAT_AP,LWIP_CORE,tcp_input_1,P_WARNING,swLogPrintf("tcp_input : short packet ( %u bytes ) discarded "); +293888,602740736,0,0,PLAT_AP,LWIP_CORE,tcp_input_2,P_WARNING,swLogPrintf("tcp_input : packet discarded due to failing checksum 0x%x "); +293888,602742784,0,0,PLAT_AP,LWIP_CORE,tcp_input_3,P_WARNING,swLogPrintf("tcp_input : invalid header length ( %u ) "); +293888,602746879,0,0,PLAT_AP,LWIP_CORE,tcp_input_4,P_ERROR,swLogPrintf("p->next = = NULL "); +293888,602746880,0,0,PLAT_AP,LWIP_CORE,tcp_input_5,P_WARNING,swLogPrintf("tcp_input : options overflow second pbuf ( %u bytes ) "); +293888,602750975,0,0,PLAT_AP,LWIP_CORE,tcp_input_6,P_ERROR,swLogPrintf("p->len ! = 0 or p->tot_len ! = p->next->tot_len "); +293888,602753023,0,0,PLAT_AP,LWIP_CORE,tcp_input_7,P_ERROR,swLogPrintf("tcp_input : active pcb invalid state "); +293888,602755071,0,0,PLAT_AP,LWIP_CORE,tcp_input_8,P_ERROR,swLogPrintf("tcp_input : pcb->next ! = pcb ( before cache ) "); +293888,602757119,0,0,PLAT_AP,LWIP_CORE,tcp_input_9,P_ERROR,swLogPrintf("tcp_input : pcb->next ! = pcb ( after cache ) "); +293888,602759167,0,0,PLAT_AP,LWIP_CORE,tcp_input_10,P_ERROR,swLogPrintf("tcp_input : TIME-WAIT pcb->state = = TIME-WAIT "); +293888,602761215,0,0,PLAT_AP,LWIP_CORE,tcp_input_11,P_INFO,swLogPrintf("tcp_input : packed for TIME_WAITing connection "); +293888,602763263,0,0,PLAT_AP,LWIP_CORE,tcp_input_12,P_INFO,swLogPrintf("tcp_input : packed for LISTENing connection "); +293888,602765311,0,0,PLAT_AP,LWIP_CORE,tcp_input_13,P_INFO,swLogPrintf("tcp_input : flags "); +293888,602767359,0,0,PLAT_AP,LWIP_CORE,tcp_input_20,P_SIG,swLogPrintf("tcp receive rst , THE hib / sleep2 tcp context pcb will shutdown "); +293888,602769407,0,0,PLAT_AP,LWIP_CORE,tcp_input_14,P_ERROR,swLogPrintf("pcb->refused_data = = NULL "); +293888,602771455,0,0,PLAT_AP,LWIP_CORE,tcp_input_15,P_INFO,swLogPrintf("tcp refuse data timer has enable "); +293888,602771456,0,0,PLAT_AP,LWIP_CORE,tcp_input_16,P_INFO,swLogPrintf("enable tcp refuse data timer %u "); +293888,602775551,0,0,PLAT_AP,LWIP_CORE,tcp_input_17,P_WARNING,swLogPrintf("tcp_input : keep incoming packet , because pcb is full "); +293888,602777599,0,0,PLAT_AP,LWIP_CORE,tcp_input_18,P_WARNING,swLogPrintf("tcp_input : no PCB match found , resetting "); +293888,602779647,0,0,PLAT_AP,LWIP_CORE,tcp_input_19,P_WARNING,swLogPrintf("tcp_input : tcp_pcbs_sane ( ) "); +293888,602781695,0,0,PLAT_AP,LWIP_CORE,tcp_listen_input_1,P_INFO,swLogPrintf("tcp_listen_input : ACK in LISTEN , sending reset "); +293888,602781952,0,0,PLAT_AP,LWIP_CORE,tcp_listen_input_2,P_INFO,swLogPrintf("TCP connection request %u -> %u "); +293888,602783744,0,0,PLAT_AP,LWIP_CORE,tcp_listen_input_3,P_INFO,swLogPrintf("tcp_listen_input : listen backlog exceeded for port %u "); +293888,602787839,0,0,PLAT_AP,LWIP_CORE,tcp_listen_input_4,P_WARNING,swLogPrintf("tcp_listen_input : could not allocate PCB "); +293888,602787840,0,0,PLAT_AP,LWIP_CORE,tcp_listen_input_5,P_INFO,swLogPrintf("enable tcp syncrcy timer %u "); +293888,602791935,0,0,PLAT_AP,LWIP_CORE,tcp_timewait_input_1,P_INFO,swLogPrintf("remove tcp time wait timer "); +293888,602791936,0,0,PLAT_AP,LWIP_CORE,tcp_timewait_input_2,P_INFO,swLogPrintf("enable tcp time wait timer %u "); +293888,602793984,0,0,PLAT_AP,LWIP_CORE,tcp_rebuild_seg_ul_sequence_bitmap_1,P_INFO,swLogPrintf("tcp_rebuild_seg_ul_sequence_bitmap disable sequence %d "); +293888,602798079,0,0,PLAT_AP,LWIP_CORE,tcp_process_1,P_INFO,swLogPrintf("tcp_process : Connection RESET "); +293888,602800127,0,0,PLAT_AP,LWIP_CORE,tcp_process_2,P_ERROR,swLogPrintf("tcp_process : pcb->state = = CLOSED "); +293888,602802175,0,0,PLAT_AP,LWIP_CORE,tcp_process_3,P_INFO,swLogPrintf("remove tcp delay ack timer "); +293888,602802432,0,0,PLAT_AP,LWIP_CORE,tcp_process_4,P_INFO,swLogPrintf("tcp_process : unacceptable reset seqno %u rcv_nxt %u "); +293888,602804480,0,0,PLAT_AP,LWIP_CORE,tcp_process_5,P_INFO,swLogPrintf("tcp_process : Connection RESET seqno %u rcv_nxt %u "); +293888,602806784,0,0,PLAT_AP,LWIP_CORE,tcp_process_6,P_INFO,swLogPrintf("SYN-SENT : ackno %u pcb->snd_nxt %u unacked %u "); +293888,602810367,0,0,PLAT_AP,LWIP_CORE,tcp_process_7,P_INFO,swLogPrintf("tcp keepalive timer has active "); +293888,602810368,0,0,PLAT_AP,LWIP_CORE,tcp_process_8,P_INFO,swLogPrintf("enable tcp keepalive timer %u "); +293888,602812672,0,0,PLAT_AP,LWIP_CORE,tcp_process_9,P_INFO,swLogPrintf("tcp_process ( SENT ) : cwnd %u ssthresh %u "); +293888,602816511,0,0,PLAT_AP,LWIP_CORE,tcp_process_10,P_ERROR,swLogPrintf("pcb->snd_queuelen > 0 "); +293888,602816512,0,0,PLAT_AP,LWIP_CORE,tcp_process_11,P_INFO,swLogPrintf("tcp_process : SYN-SENT --queuelen %u "); +293888,602820607,0,0,PLAT_AP,LWIP_CORE,tcp_process_12,P_ERROR,swLogPrintf("no segment to free "); +293888,602820608,0,0,PLAT_AP,LWIP_CORE,tcp_process_13,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602822656,0,0,PLAT_AP,LWIP_CORE,tcp_process_14,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602824960,0,0,PLAT_AP,LWIP_CORE,tcp_process_15,P_INFO,swLogPrintf("enable tcp retry timer %u , pcb 0x%x "); +293888,602828799,0,0,PLAT_AP,LWIP_CORE,tcp_process_43,P_SIG,swLogPrintf("tcp_process THE tcp pcb ( enable hib / sleep2 ) has established "); +293888,602828800,0,0,PLAT_AP,LWIP_CORE,tcp_process_16,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602831104,0,0,PLAT_AP,LWIP_CORE,tcp_process_17,P_INFO,swLogPrintf("enable tcp retry timer %u , pcb 0x%x "); +293888,602834943,0,0,PLAT_AP,LWIP_CORE,tcp_process_18,P_INFO,swLogPrintf("remove tcp syncrcv timer "); +293888,602835200,0,0,PLAT_AP,LWIP_CORE,tcp_process_19,P_INFO,swLogPrintf("TCP connection established %u -> %u "); +293888,602839039,0,0,PLAT_AP,LWIP_CORE,tcp_process_20,P_ERROR,swLogPrintf("pcb->listener->accept ! = NULL "); +293888,602839296,0,0,PLAT_AP,LWIP_CORE,tcp_process_21,P_INFO,swLogPrintf("tcp_process ( SYN_RCVD ) : cwnd %u ssthresh %u "); +293888,602843135,0,0,PLAT_AP,LWIP_CORE,tcp_process_keep_alive_1,P_INFO,swLogPrintf("tcp keepalive timer has active "); +293888,602843136,0,0,PLAT_AP,LWIP_CORE,tcp_process_22,P_INFO,swLogPrintf("enable tcp keepalive timer %u "); +293888,602847231,0,0,PLAT_AP,LWIP_CORE,tcp_process_23,P_INFO,swLogPrintf("remove tcp keepalive timer "); +293888,602847232,0,0,PLAT_AP,LWIP_CORE,tcp_process_24,P_INFO,swLogPrintf("enable tcp ooseq timer %u "); +293888,602851327,0,0,PLAT_AP,LWIP_CORE,tcp_process_25,P_INFO,swLogPrintf("tcp ooseq timer has active "); +293888,602851328,0,0,PLAT_AP,LWIP_CORE,tcp_process_26,P_INFO,swLogPrintf("disable tcp ooseq timer %u "); +293888,602855423,0,0,PLAT_AP,LWIP_CORE,tcp_process_keep_alive_2,P_INFO,swLogPrintf("tcp keepalive timer has active "); +293888,602855424,0,0,PLAT_AP,LWIP_CORE,tcp_process_27,P_INFO,swLogPrintf("enable tcp keepalive timer %u "); +293888,602857728,0,0,PLAT_AP,LWIP_CORE,tcp_process_28,P_INFO,swLogPrintf("TCP connection closed : FIN_WAIT_1 %u -> %u "); +293888,602859520,0,0,PLAT_AP,LWIP_CORE,tcp_process_29,P_INFO,swLogPrintf("enable tcp timewait timeout %u "); +293888,602863615,0,0,PLAT_AP,LWIP_CORE,tcp_process_30,P_WARNING,swLogPrintf("tcp keepalive timer has active "); +293888,602863616,0,0,PLAT_AP,LWIP_CORE,tcp_process_31,P_INFO,swLogPrintf("enable tcp fin wait2 %u "); +293888,602867711,0,0,PLAT_AP,LWIP_CORE,tcp_process_32,P_WARNING,swLogPrintf("tcp FIN WAIT2 timer has active "); +293888,602867968,0,0,PLAT_AP,LWIP_CORE,tcp_process_33,P_INFO,swLogPrintf("TCP connection closed : FIN_WAIT_2 %u -> %u "); +293888,602871807,0,0,PLAT_AP,LWIP_CORE,tcp_process_34,P_INFO,swLogPrintf("remove fin wait2 timer "); +293888,602873855,0,0,PLAT_AP,LWIP_CORE,tcp_process_35,P_WARNING,swLogPrintf("tcp FIN WAIT2 timer has deactive "); +293888,602873856,0,0,PLAT_AP,LWIP_CORE,tcp_process_36,P_INFO,swLogPrintf("enable tcp time wait timer %u "); +293888,602877951,0,0,PLAT_AP,LWIP_CORE,tcp_process_37,P_WARNING,swLogPrintf("tcp TIME WAIT timer has active "); +293888,602878208,0,0,PLAT_AP,LWIP_CORE,tcp_process_38,P_INFO,swLogPrintf("TCP connection closed : CLOSING %u -> %u "); +293888,602880000,0,0,PLAT_AP,LWIP_CORE,tcp_process_39,P_INFO,swLogPrintf("enable tcp time wait timer %u "); +293888,602884095,0,0,PLAT_AP,LWIP_CORE,tcp_process_40,P_WARNING,swLogPrintf("tcp TIME WAIT timer has active "); +293888,602884352,0,0,PLAT_AP,LWIP_CORE,tcp_process_41,P_INFO,swLogPrintf("TCP connection closed : LAST_ACK %u -> %u "); +293888,602888191,0,0,PLAT_AP,LWIP_CORE,tcp_process_42,P_INFO,swLogPrintf("remove tcp last ack timer "); +293888,602890239,0,0,PLAT_AP,LWIP_CORE,tcp_receive_1,P_ERROR,swLogPrintf("tcp_receive : wrong state "); +293888,602890240,0,0,PLAT_AP,LWIP_CORE,tcp_receive_2,P_INFO,swLogPrintf("tcp_receive : window update %u "); +293888,602893312,0,0,PLAT_AP,LWIP_CORE,tcp_receive_3,P_INFO,swLogPrintf("tcp_receive : no window update lastack %u ackno %u wl1 %u seqno %u wl2 %u "); +293888,602894336,0,0,PLAT_AP,LWIP_CORE,tcp_receive_4,P_INFO,swLogPrintf("tcp_receive : slow start cwnd %u "); +293888,602896384,0,0,PLAT_AP,LWIP_CORE,tcp_receive_5,P_INFO,swLogPrintf("tcp_receive : congestion avoidance cwnd %u "); +293888,602898944,0,0,PLAT_AP,LWIP_CORE,tcp_receive_6,P_INFO,swLogPrintf("tcp_receive : ACK for %u , unacked->seqno %u : %u "); +293888,602900736,0,0,PLAT_AP,LWIP_CORE,tcp_receive_7,P_INFO,swLogPrintf("tcp_receive : removing %u : %u from pcb->unacked "); +293888,602902528,0,0,PLAT_AP,LWIP_CORE,tcp_receive_8,P_INFO,swLogPrintf("tcp_receive : queuelen %u "); +293888,602906623,0,0,PLAT_AP,LWIP_CORE,tcp_receive_9,P_ERROR,swLogPrintf("pcb->snd_queuelen > = pbuf_clen ( next->p ) "); +293888,602908671,0,0,PLAT_AP,LWIP_CORE,tcp_receive_38,P_ERROR,swLogPrintf("tcp_receive_37 : UL sequence state indicate fail , the pcb socketid is inavlid "); +293888,602908672,0,0,PLAT_AP,LWIP_CORE,tcp_receive_40,P_INFO,swLogPrintf("tcp_receive_37 : UL sequence state indicate success , the pcb socket id %u "); +293888,602910976,0,0,PLAT_AP,LWIP_CORE,tcp_receive_ul_total_status_1,P_INFO,swLogPrintf("tcp_receive_37 : socket %d , UL total status %u "); +293888,602913024,0,0,PLAT_AP,LWIP_CORE,tcp_receive_ul_total_status_2,P_INFO,swLogPrintf("tcp_receive_37 : socket %d , UL total status %u "); +293888,602914816,0,0,PLAT_AP,LWIP_CORE,tcp_receive_10,P_INFO,swLogPrintf("%u ( after freeing unacked ) "); +293888,602918911,0,0,PLAT_AP,LWIP_CORE,tcp_receive_11,P_ERROR,swLogPrintf("tcp_receive : valid queue length "); +293888,602918912,0,0,PLAT_AP,LWIP_CORE,tcp_receive_12,P_INFO,swLogPrintf("remove tcp retry time , pcb 0x%x "); +293888,602923007,0,0,PLAT_AP,LWIP_CORE,tcp_receive_tcp_total_retry_time1,P_INFO,swLogPrintf("remove tcp total retry timer "); +293888,602923008,0,0,PLAT_AP,LWIP_CORE,tcp_receive_13,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,602925312,0,0,PLAT_AP,LWIP_CORE,tcp_receive_14,P_INFO,swLogPrintf("enable tcp retry timer %u , pcb 0x%x "); +293888,602929151,0,0,PLAT_AP,LWIP_CORE,tcp_receive_tcp_total_retry_time_2,P_INFO,swLogPrintf("remove tcp total retry timer "); +293888,602929152,0,0,PLAT_AP,LWIP_CORE,tcp_receive_tcp_total_retry_time_4,P_INFO,swLogPrintf("enable tcp total retry timer %u "); +293888,602931456,0,0,PLAT_AP,LWIP_CORE,tcp_receive_15,P_ERROR,swLogPrintf("tcp_receive : removing %u : %u from pcb->unsent "); +293888,602933248,0,0,PLAT_AP,LWIP_CORE,tcp_receive_16,P_INFO,swLogPrintf("tcp_receive : queuelen %u "); +293888,602937343,0,0,PLAT_AP,LWIP_CORE,tcp_receive_17,P_ERROR,swLogPrintf("pcb->snd_queuelen > = pbuf_clen ( next->p ) "); +293888,602937344,0,0,PLAT_AP,LWIP_CORE,tcp_receive_18,P_INFO,swLogPrintf("%u ( after freeing unsent ) "); +293888,602941439,0,0,PLAT_AP,LWIP_CORE,tcp_receive_19,P_ERROR,swLogPrintf("tcp_receive : valid queue length "); +293888,602941440,0,0,PLAT_AP,LWIP_CORE,tcp_receive_pool,P_INFO,swLogPrintf("tcp_receive : poll result %u "); +293888,602944000,0,0,PLAT_AP,LWIP_CORE,tcp_receive_20,P_INFO,swLogPrintf("tcp_receive : pcb->rttest %u rtseq %u ackno %u "); +293888,602945792,0,0,PLAT_AP,LWIP_CORE,tcp_receive_21,P_INFO,swLogPrintf("tcp_receive : experienced rtt %u ticks ( %u msec ) "); +293888,602948352,0,0,PLAT_AP,LWIP_CORE,tcp_receive_22,P_INFO,swLogPrintf("tcp_receive : RTO %u ( %u msec ) , sv %d , sa %d "); +293888,602951679,0,0,PLAT_AP,LWIP_CORE,tcp_receive_23,P_ERROR,swLogPrintf("inseg.p ! = NULL or insane offset! "); +293888,602953727,0,0,PLAT_AP,LWIP_CORE,tcp_receive_24,P_ERROR,swLogPrintf("pbuf too short! "); +293888,602955775,0,0,PLAT_AP,LWIP_CORE,tcp_receive_25,P_ERROR,swLogPrintf("pbuf_header failed1 "); +293888,602957823,0,0,PLAT_AP,LWIP_CORE,tcp_receive_26,P_ERROR,swLogPrintf("pbuf_header failed2 "); +293888,602957824,0,0,PLAT_AP,LWIP_CORE,tcp_receive_27,P_INFO,swLogPrintf("tcp_receive : duplicate seqno %u "); +293888,602960384,0,0,PLAT_AP,LWIP_CORE,tcp_receive_28,P_INFO,swLogPrintf("tcp_receive : other end overran receive window seqno %u len %u right edge %u "); +293888,602963967,0,0,PLAT_AP,LWIP_CORE,tcp_receive_29,P_ERROR,swLogPrintf("tcp_receive : segment not trimmed correctly to rcv_wnd "); +293888,602966015,0,0,PLAT_AP,LWIP_CORE,tcp_receive_30,P_INFO,swLogPrintf("tcp_receive : received in-order FIN , binning ooseq queue "); +293888,602968063,0,0,PLAT_AP,LWIP_CORE,tcp_receive_31,P_ERROR,swLogPrintf("tcp_receive : segment not trimmed correctly to ooseq queue "); +293888,602970111,0,0,PLAT_AP,LWIP_CORE,tcp_receive_32,P_ERROR,swLogPrintf("tcp_receive : tcplen > rcv_wnd "); +293888,602972159,0,0,PLAT_AP,LWIP_CORE,tcp_receive_33,P_INFO,swLogPrintf("tcp_receive : received FIN. "); +293888,602974207,0,0,PLAT_AP,LWIP_CORE,tcp_receive_34,P_ERROR,swLogPrintf("tcp_receive : ooseq tcplen > rcv_wnd "); +293888,602976255,0,0,PLAT_AP,LWIP_CORE,tcp_receive_35,P_INFO,swLogPrintf("tcp_receive : dequeued FIN "); +293888,602976768,0,0,PLAT_AP,LWIP_CORE,tcp_receive_36,P_INFO,swLogPrintf("tcp_receive : other end overran receive window seqno %u len %u right edge %u "); +293888,602980351,0,0,PLAT_AP,LWIP_CORE,tcp_receive_37,P_ERROR,swLogPrintf("tcp_receive : segment not trimmed correctly to rcv_wnd "); +293888,602982399,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_1,P_INFO,swLogPrintf("tcp_parseopt : EOL "); +293888,602984447,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_2,P_INFO,swLogPrintf("tcp_parseopt : NOP "); +293888,602986495,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_3,P_INFO,swLogPrintf("tcp_parseopt : MSS "); +293888,602988543,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_4,P_WARNING,swLogPrintf("tcp_parseopt : bad length "); +293888,602990591,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_5,P_INFO,swLogPrintf("tcp_parseopt : WND_SCALE "); +293888,602992639,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_6,P_WARNING,swLogPrintf("tcp_parseopt : bad length2 "); +293888,602994687,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_7,P_ERROR,swLogPrintf("tcp_parseopt : window not at default value "); +293888,602996735,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_10,P_INFO,swLogPrintf("tcp_parseopt : other "); +293888,602998783,0,0,PLAT_AP,LWIP_CORE,tcp_parseopt_11,P_WARNING,swLogPrintf("tcp_parseopt : bad length3 "); +293888,603000831,0,0,PLAT_AP,LWIP_CORE,tcp_output_alloc_header_1,P_ERROR,swLogPrintf("check that first pbuf can hold struct tcp_hdr "); +293888,603002879,0,0,PLAT_AP,LWIP_CORE,tcp_create_segment_1,P_WARNING,swLogPrintf("tcp_create_segment : no memory "); +293888,603004927,0,0,PLAT_AP,LWIP_CORE,tcp_create_segment_2,P_ERROR,swLogPrintf("p->tot_len > = optlen "); +293888,603006975,0,0,PLAT_AP,LWIP_CORE,tcp_create_segment_4,P_WARNING,swLogPrintf("tcp_create_segment : no room for TCP header in pbuf "); +293888,603009023,0,0,PLAT_AP,LWIP_CORE,tcp_pbuf_prealloc_1,P_ERROR,swLogPrintf("need unchained pbuf "); +293888,603011071,0,0,PLAT_AP,LWIP_CORE,tcp_write_checks_1,P_WARNING,swLogPrintf("tcp_write ( ) called in invalid state "); +293888,603011328,0,0,PLAT_AP,LWIP_CORE,tcp_write_checks_2,P_WARNING,swLogPrintf("tcp_write : too much data ( len %u > snd_buf %u ) "); +293888,603013120,0,0,PLAT_AP,LWIP_CORE,tcp_write_checks_3,P_INFO,swLogPrintf("tcp_write : queuelen : %u "); +293888,603015424,0,0,PLAT_AP,LWIP_CORE,tcp_write_checks_4,P_INFO,swLogPrintf("tcp_write : too long queue %u ( max %u ) "); +293888,603019263,0,0,PLAT_AP,LWIP_CORE,tcp_write_checks_5,P_ERROR,swLogPrintf("tcp_write : pbufs on queue = > at least one queue non-empty "); +293888,603021311,0,0,PLAT_AP,LWIP_CORE,tcp_write_checks_6,P_ERROR,swLogPrintf("tcp_write : no pbufs on queue = > both queues empty "); +293888,603022080,0,0,PLAT_AP,LWIP_CORE,tcp_write_1,P_INFO,swLogPrintf("tcp_write ( pcb = 0x%x , data = 0x%x , len = %u , apiflags = %u ) "); +293888,603025407,0,0,PLAT_AP,LWIP_CORE,tcp_write_2,P_ERROR,swLogPrintf("tcp_write : arg = = NULL ( programmer violates API "); +293888,603027455,0,0,PLAT_AP,LWIP_CORE,tcp_write_3,P_ERROR,swLogPrintf("mss_local is too small "); +293888,603029503,0,0,PLAT_AP,LWIP_CORE,tcp_write_4,P_ERROR,swLogPrintf("unsent_oversize mismatch ( pcb vs. last_unsent ) "); +293888,603031551,0,0,PLAT_AP,LWIP_CORE,tcp_write_5,P_ERROR,swLogPrintf("inconsistent oversize vs. space "); +293888,603033599,0,0,PLAT_AP,LWIP_CORE,tcp_write_6,P_ERROR,swLogPrintf("inconsistent oversize vs. len "); +293888,603033600,0,0,PLAT_AP,LWIP_CORE,tcp_write_7,P_INFO,swLogPrintf("tcp_write : could not allocate memory for pbuf copy size %u "); +293888,603037695,0,0,PLAT_AP,LWIP_CORE,tcp_write_8,P_ERROR,swLogPrintf("tcp_write : ROM pbufs cannot be oversized "); +293888,603039743,0,0,PLAT_AP,LWIP_CORE,tcp_write_9,P_WARNING,swLogPrintf("tcp_write : could not allocate memory for zero-copy pbuf "); +293888,603041791,0,0,PLAT_AP,LWIP_CORE,tcp_write_10,P_ERROR,swLogPrintf("unsent_oversize mismatch ( pcb->unsent is NULL ) "); +293888,603041792,0,0,PLAT_AP,LWIP_CORE,tcp_write_11,P_WARNING,swLogPrintf("tcp_write : could not allocate memory for pbuf copy size %u "); +293888,603045887,0,0,PLAT_AP,LWIP_CORE,tcp_write_12,P_ERROR,swLogPrintf("tcp_write : check that first pbuf can hold the complete seglen "); +293888,603047935,0,0,PLAT_AP,LWIP_CORE,tcp_write_13,P_ERROR,swLogPrintf("oversize = = 0 "); +293888,603049983,0,0,PLAT_AP,LWIP_CORE,tcp_write_14,P_WARNING,swLogPrintf("tcp_write : could not allocate memory for zero-copy pbu "); +293888,603052031,0,0,PLAT_AP,LWIP_CORE,tcp_write_15,P_WARNING,swLogPrintf("tcp_write : could not allocate memory for header pbuf "); +293888,603052288,0,0,PLAT_AP,LWIP_CORE,tcp_write_16,P_WARNING,swLogPrintf("tcp_write : queue too long %u ( %d ) "); +293888,603056127,0,0,PLAT_AP,LWIP_CORE,tcp_write_17,P_ERROR,swLogPrintf("prev_seg ! = NULL "); +293888,603056384,0,0,PLAT_AP,LWIP_CORE,tcp_write_18,P_INFO,swLogPrintf("tcp_write : queueing %u : %u "); +293888,603060223,0,0,PLAT_AP,LWIP_CORE,tcp_write_19,P_ERROR,swLogPrintf("last_unsent->oversize_left > = oversize_used "); +293888,603062271,0,0,PLAT_AP,LWIP_CORE,tcp_write_20,P_ERROR,swLogPrintf("tcp_write : cannot concatenate when pcb->unsent is empty "); +293888,603064319,0,0,PLAT_AP,LWIP_CORE,tcp_write_21,P_ERROR,swLogPrintf("tcp_write : extension of reference requires reference "); +293888,603064320,0,0,PLAT_AP,LWIP_CORE,tcp_write_23,P_INFO,swLogPrintf("tcp_write : %u ( after enqueued ) "); +293888,603068415,0,0,PLAT_AP,LWIP_CORE,tcp_write_24,P_ERROR,swLogPrintf("tcp_write : valid queue length "); +293888,603068416,0,0,PLAT_AP,LWIP_CORE,tcp_write_27,P_ERROR,swLogPrintf("tcp_write : UL sequence state indicate fail , because the pcb 0x%x socket id is invalid "); +293888,603070464,0,0,PLAT_AP,LWIP_CORE,tcp_write_28,P_INFO,swLogPrintf("tcp_write : UL sequence state indicate success , the pcb socket id %u "); +293888,603074559,0,0,PLAT_AP,LWIP_CORE,tcp_write_25,P_ERROR,swLogPrintf("tcp_write : valid queue length2 "); +293888,603074560,0,0,PLAT_AP,LWIP_CORE,tcp_write_26,P_INFO,swLogPrintf("tcp_write : %u ( with mem err ) "); +293888,603076608,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_1,P_INFO,swLogPrintf("tcp_enqueue_flags : queuelen : %u "); +293888,603080703,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_2,P_ERROR,swLogPrintf("tcp_enqueue_flags : need either TCP_SYN or TCP_FIN in flags ( programmer violates API ) "); +293888,603080960,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_3,P_INFO,swLogPrintf("tcp_enqueue_flags : too long queue %u ( max %u ) "); +293888,603084799,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_4,P_ERROR,swLogPrintf("tcp_enqueue_flags : check that first pbuf can hold optlen "); +293888,603086847,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_5,P_ERROR,swLogPrintf("tcp_enqueue_flags : seg->tcphdr not aligned or invalid segment length "); +293888,603087360,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_6,P_INFO,swLogPrintf("tcp_enqueue_flags : queueing %u : %u ( 0x%x ) "); +293888,603088896,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_7,P_INFO,swLogPrintf("tcp_enqueue_flags : %u ( after enqueued ) "); +293888,603092991,0,0,PLAT_AP,LWIP_CORE,tcp_enqueue_flags_8,P_ERROR,swLogPrintf("tcp_enqueue_flags : invalid queue length "); +293888,603095039,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_4,P_INFO,swLogPrintf("tcp delay ack timer has enable "); +293888,603095040,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_3,P_INFO,swLogPrintf("enable tcp delay ack timer %u "); +293888,603099135,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_1,P_INFO,swLogPrintf("tcp_output : ( ACK ) could not allocate pbuf "); +293888,603099136,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_2,P_INFO,swLogPrintf("tcp_output : sending ACK for %u "); +293888,603101440,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_port_mapping_1,P_INFO,swLogPrintf("tcp_send_empty_ack : port mapping from %u to %u "); +293888,603105279,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_5,P_INFO,swLogPrintf("tcp delay ack timer has enable "); +293888,603105280,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_6,P_INFO,swLogPrintf("enable tcp delay ack timer %u "); +293888,603109375,0,0,PLAT_AP,LWIP_CORE,tcp_send_empty_ack_7,P_INFO,swLogPrintf("remove tcp delay ack timer "); +293888,603111423,0,0,PLAT_AP,LWIP_CORE,tcp_output_1,P_ERROR,swLogPrintf("don ' t call tcp_output for listen-pcbs "); +293888,603111424,0,0,PLAT_AP,LWIP_CORE,tcp_output_2,P_INFO,swLogPrintf("tcp_output : nothing to send 0x%x "); +293888,603114240,0,0,PLAT_AP,LWIP_CORE,tcp_output_3,P_INFO,swLogPrintf("tcp_output : snd_wnd ( %u ) cwnd ( %u ) wnd ( %u ) seq = = NULL , ack %u "); +293888,603116800,0,0,PLAT_AP,LWIP_CORE,tcp_output_4,P_INFO,swLogPrintf("tcp_output : snd_wnd ( %u ) cwnd ( %u ) wnd ( %u ) effwnd ( %u ) seq ( %u ) , ack %u "); +293888,603119615,0,0,PLAT_AP,LWIP_CORE,tcp_output_5,P_ERROR,swLogPrintf("RST not expected here! "); +293888,603121152,0,0,PLAT_AP,LWIP_CORE,tcp_output_6,P_INFO,swLogPrintf("tcp_output : snd_wnd ( %u ) cwnd ( %u ) wnd ( %u ) effwnd ( %u ) seq ( %u ) , ack %u i ( %u ) "); +293888,603123711,0,0,PLAT_AP,LWIP_CORE,tcp_output_8,P_SIG,swLogPrintf("tcp output fail because of UL suspending , it will retry later when retry time timeout "); +293888,603125759,0,0,PLAT_AP,LWIP_CORE,tcp_output_7,P_INFO,swLogPrintf("remove tcp delay ack timer "); +293888,603126016,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_5,P_INFO,swLogPrintf("enable tcp retry timer %u , pcb 0x%x "); +293888,603129855,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_6,P_WARNING,swLogPrintf("tcp retry timer has active "); +293888,603129856,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_tcp_total_retry_time_1,P_INFO,swLogPrintf("enable tcp total retry timer %u "); +293888,603133951,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_tcp_total_retry_time_2,P_WARNING,swLogPrintf("tcp total retry timer has active "); +293888,603134208,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_8,P_INFO,swLogPrintf("tcp output segment pbuf data ticktype %u , dataLifetime %u "); +293888,603136256,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_1,P_INFO,swLogPrintf("tcp_output_segment : rtseq %u , rttest %u "); +293888,603140095,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_10,P_INFO,swLogPrintf("tcp_output_segment : pcb in SYS_SENT state , discard rttest "); +293888,603140352,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_2,P_INFO,swLogPrintf("tcp_output_segment : %u : %u "); +293888,603142656,0,0,PLAT_AP,LWIP_CORE,tcp_output_segment_port_mapping_1,P_INFO,swLogPrintf("tcp_output_segment : port mapping from %u to %u , cid %u "); +293888,603146239,0,0,PLAT_AP,LWIP_CORE,tcp_rst_1,P_INFO,swLogPrintf("tcp_rst : could not allocate memory for pbuf "); +293888,603148287,0,0,PLAT_AP,LWIP_CORE,tcp_rst_2,P_ERROR,swLogPrintf("check that first pbuf can hold struct tcp_hdr "); +293888,603148800,0,0,PLAT_AP,LWIP_CORE,tcp_rst_port_mapping_1,P_INFO,swLogPrintf("tcp_rst : port mapping from %u to %u , cid %u "); +293888,603150592,0,0,PLAT_AP,LWIP_CORE,tcp_rst_3,P_INFO,swLogPrintf("tcp_rst : seqno %u ackno %u "); +293888,603152896,0,0,PLAT_AP,LWIP_CORE,tcp_rexmit_fast_1,P_INFO,swLogPrintf("tcp_receive : dupacks %u ( %u ) fast retransmit %u "); +293888,603154688,0,0,PLAT_AP,LWIP_CORE,tcp_rexmit_fast_2,P_INFO,swLogPrintf("tcp_receive : The minimum value for ssthresh %u should be min 2 mss %u "); +293888,603156480,0,0,PLAT_AP,LWIP_CORE,tcp_rexmit_fast_3,P_INFO,swLogPrintf("remove tcp retry timer , pcb 0x%x "); +293888,603158784,0,0,PLAT_AP,LWIP_CORE,tcp_rexmit_fast_4,P_INFO,swLogPrintf("enable tcp retry timer %u , pcb 0x%x "); +293888,603162623,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_1,P_INFO,swLogPrintf("tcp_keepalive : sending KEEPALIVE probe to "); +293888,603163136,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_2,P_INFO,swLogPrintf("tcp_keepalive : tcp_ticks %u pcb->tmr %u pcb->keep_cnt_sent %u "); +293888,603166719,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_3,P_WARNING,swLogPrintf("tcp_keepalive : could not allocate memory for pbuf "); +293888,603167232,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_port_mapping_1,P_INFO,swLogPrintf("tcp_keepalive : port mapping from %u to %u , cid %u "); +293888,603169024,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_5,P_INFO,swLogPrintf("tcp_keepalive : pbuf tick type %u , dataLifeTime %u "); +293888,603171328,0,0,PLAT_AP,LWIP_CORE,tcp_keepalive_6,P_INFO,swLogPrintf("tcp_keepalive : seqno %u ackno %u err %d "); +293888,603174911,0,0,PLAT_AP,LWIP_CORE,tcp_zero_window_probe_1,P_INFO,swLogPrintf("tcp_zero_window_probe : sending ZERO WINDOW probe to "); +293888,603175424,0,0,PLAT_AP,LWIP_CORE,tcp_zero_window_probe_2,P_INFO,swLogPrintf("tcp_zero_window_probe : tcp_ticks %u pcb->tmr %u pcb->keep_cnt_sent %u "); +293888,603179007,0,0,PLAT_AP,LWIP_CORE,tcp_zero_window_probe_3,P_WARNING,swLogPrintf("tcp_zero_window_probe : no memory for pbuf "); +293888,603179264,0,0,PLAT_AP,LWIP_CORE,tcp_zero_window_probe_6,P_INFO,swLogPrintf("tcp_zero_window_probe : pbuf ticktype %u , datalifetime %u "); +293888,603181568,0,0,PLAT_AP,LWIP_CORE,tcp_zero_window_probe_7,P_INFO,swLogPrintf("tcp_zero_window_probe : seqno %u ackno %u err %d "); +293888,603185151,0,0,PLAT_AP,LWIP_CORE,sys_timeout_debug_1,P_ERROR,swLogPrintf("sys_timeout : timeout ! = NULL , alloc sys_timeout fail "); +293888,603187199,0,0,PLAT_AP,LWIP_CORE,tcpip_idle_timer_1,P_INFO,swLogPrintf("tcpip idle timer timeout "); +293888,603189247,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_1,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist ipv6 rs retry timer "); +293888,603191295,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_2,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist ipv6 address dad timer "); +293888,603191296,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_3,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp retry timer , arg 0x%x "); +293888,603195391,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_16,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp total retry timer "); +293888,603197439,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_4,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp delay ack timer "); +293888,603199487,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_5,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp pending fin timer "); +293888,603201535,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_6,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp refuse data timer "); +293888,603203583,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_7,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp fin wait2 timer "); +293888,603205631,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_8,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp ooseq timer "); +293888,603207679,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_9,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp syncrcv timer "); +293888,603209727,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_10,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp lastack timer "); +293888,603211775,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_11,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp timewait timer "); +293888,603213823,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_pool_check,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp pool timer "); +293888,603215871,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_keep_alive_check,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist keep alive timer "); +293888,603217919,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_close_local_abort_check,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist tcp close local abort timer "); +293888,603219967,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_12,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist ipv4 frag timer "); +293888,603222015,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_13,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist ipv6 frag timer "); +293888,603224063,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_14,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist DNS retry timer "); +293888,603226111,0,0,PLAT_AP,LWIP_CORE,sys_check_timeouts_for_hib_sleep2_15,P_INFO,swLogPrintf("sys_check_timeouts_for_hib_sleep2 exist idle timer "); +293888,603226112,0,0,PLAT_AP,LWIP_CORE,udp_get_curr_hib_sleep2_pcb_num_1,P_INFO,swLogPrintf("udp_get_curr_hib_sleep2_pcb_num %u "); +293888,603228160,0,0,PLAT_AP,LWIP_CORE,udp_add_curr_hib_sleep2_pcb_num_1,P_INFO,swLogPrintf("udp_add_hib_sleep2_context_pcb %u "); +293888,603230208,0,0,PLAT_AP,LWIP_CORE,udp_del_curr_hib_sleep2_pcb_num_1,P_INFO,swLogPrintf("udp_del_curr_hib_sleep2_pcb_num %u "); +293888,603232256,0,0,PLAT_AP,LWIP_CORE,udp_enable_hib_sleep2_mode_1,P_INFO,swLogPrintf("udp_enable_hib_sleep2_mode %u "); +293888,603236351,0,0,PLAT_AP,LWIP_CORE,udp_disable_hib_sleep2_mode_1,P_INFO,swLogPrintf("udp_disable_hib_sleep2_mode "); +293888,603236352,0,0,PLAT_AP,LWIP_CORE,udp_add_hib_sleep2_context_pcb_1,P_INFO,swLogPrintf("udp_add_hib_sleep2_context_pcb alloc new udp_pcb success , sockid %d "); +293888,603240447,0,0,PLAT_AP,LWIP_CORE,udp_add_hib_sleep2_context_pcb_2,P_ERROR,swLogPrintf("udp_add_hib_sleep2_context_pcb alloc new udp_pcb fail "); +293888,603242495,0,0,PLAT_AP,LWIP_CORE,udp_check_hib_sleep2_pcb_active_1,P_INFO,swLogPrintf("udp_check_hib_sleep2_pcb_active "); +293888,603242496,0,0,PLAT_AP,LWIP_CORE,udp_check_hib_sleep2_pcb_active_2,P_INFO,swLogPrintf("udp_check_hib_sleep2_pcb_active change pcb 0x%x state to enable_active state "); +293888,603246591,0,0,PLAT_AP,LWIP_CORE,udp_check_hib_sleep2_pcb_deactive_1,P_INFO,swLogPrintf("udp_check_hib_sleep2_pcb_deactive "); +293888,603246592,0,0,PLAT_AP,LWIP_CORE,udp_check_hib_sleep2_pcb_deactive_2,P_INFO,swLogPrintf("udp_check_hib_sleep2_pcb_deactive change pcb 0x%x state to enable_deactive state "); +293888,603250687,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_1,P_ERROR,swLogPrintf("udp_get_sock_info invalid fd "); +293888,603252735,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_2,P_INFO,swLogPrintf("udp_get_sock_info find adpat udp hib pcb "); +293888,603254783,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_3,P_INFO,swLogPrintf("udp_get_sock_info can not find adpat udp hib pcb "); +293888,603256831,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_by_pcb_1,P_ERROR,swLogPrintf("udp_get_sock_info_by_pcb invalid parameter "); +293888,603258879,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_by_pcb_2,P_INFO,swLogPrintf("udp_get_sock_info_by_pcb find adpat udp pcb "); +293888,603260927,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_by_pcb_3,P_INFO,swLogPrintf("udp_get_sock_info find adpat udp hib pcb "); +293888,603262975,0,0,PLAT_AP,LWIP_CORE,udp_get_sock_info_by_pcb_4,P_INFO,swLogPrintf("udp_get_sock_info_by_pcb can not find adpat udp pcb "); +293888,603262976,0,0,PLAT_AP,LWIP_CORE,udp_input_1,P_WARNING,swLogPrintf("udp_input : short UDP datagram ( %u bytes ) discarded "); +293888,603265024,0,0,PLAT_AP,LWIP_CORE,udp_input_2,P_INFO,swLogPrintf("udp_input : received datagram of length %u "); +293888,603267328,0,0,PLAT_AP,LWIP_CORE,udp_input_3,P_INFO,swLogPrintf("udp ( %u ) <-- ( %u ) "); +293888,603269376,0,0,PLAT_AP,LWIP_CORE,udp_input_4,P_INFO,swLogPrintf("pcb ( %u ) <-- ( %u ) "); +293888,603273215,0,0,PLAT_AP,LWIP_CORE,udp_input_5,P_INFO,swLogPrintf("udp_input : calculating checksum "); +293888,603275263,0,0,PLAT_AP,LWIP_CORE,udp_input_6,P_ERROR,swLogPrintf("pbuf_header failed "); +293888,603277311,0,0,PLAT_AP,LWIP_CORE,udp_input_7,P_INFO,swLogPrintf("udp_input : not for us "); +293888,603279359,0,0,PLAT_AP,LWIP_CORE,udp_input_8,P_WARNING,swLogPrintf("udp_input : not for us , and not reply icmp unreachable message "); +293888,603281407,0,0,PLAT_AP,LWIP_CORE,udp_input_9,P_WARNING,swLogPrintf("udp_input : UDP ( or UDP Lite ) datagram discarded due to failing checksum "); +293888,603283455,0,0,PLAT_AP,LWIP_CORE,udp_sendto_chksum_2,P_INFO,swLogPrintf("udp_sendto_chksum No route to "); +293888,603285503,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_2,P_INFO,swLogPrintf("udp_send : not yet bound to a port , binding now "); +293888,603287551,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_3,P_WARNING,swLogPrintf("udp_send : forced port bind failed "); +293888,603289599,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_4,P_WARNING,swLogPrintf("udp_send : could not allocate header "); +293888,603289856,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_5,P_INFO,swLogPrintf("udp_send : added header pbuf 0x%x before given pbuf 0x%x "); +293888,603291648,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_6,P_INFO,swLogPrintf("udp_send : added header in given pbuf 0x%x "); +293888,603295743,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_7,P_ERROR,swLogPrintf("check that first pbuf can hold struct udp_hdr "); +293888,603296256,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_port_mapping_1,P_INFO,swLogPrintf("udp_send : port mapping from %u to %u , cid %u "); +293888,603297792,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_8,P_INFO,swLogPrintf("udp_send : sending datagram of length %u "); +293888,603300096,0,0,PLAT_AP,LWIP_CORE,udp_sendto_if_src_chksum_12,P_INFO,swLogPrintf("udp_send : UDP packet checksum %u ip_output_if %u "); +293888,603301888,0,0,PLAT_AP,LWIP_CORE,udp_bind_1,P_INFO,swLogPrintf("udp_bind port = %u "); +293888,603305983,0,0,PLAT_AP,LWIP_CORE,udp_bind_2,P_WARNING,swLogPrintf("udp_bind : out of free UDP ports "); +293888,603305984,0,0,PLAT_AP,LWIP_CORE,udp_bind_3,P_INFO,swLogPrintf("udp_bind : local port %u already bound by another pcb "); +293888,603310079,0,0,PLAT_AP,LWIP_CORE,udp_bind_5,P_INFO,swLogPrintf("udp_bind : add active udp list ) "); +293888,603310080,0,0,PLAT_AP,LWIP_CORE,udp_bind_4,P_INFO,swLogPrintf("udp_bind : bound to port ( %u ) "); +293888,603312128,0,0,PLAT_AP,LWIP_CORE,udp_connect_1,P_INFO,swLogPrintf("udp_connect : connected to port ( %u ) "); +293888,603316223,0,0,PLAT_AP,LWIP_CORE,udp_connect_2,P_INFO,swLogPrintf("udp_bind : add active udp list ) "); +293888,603318271,0,0,PLAT_AP,LWIP_CORE,udp_send_pkg_to_pcb_1,P_ERROR,swLogPrintf("udp_send_pkg_to_pcb : invalid parameter "); +293888,603320319,0,0,PLAT_AP,LWIP_CORE,udp_send_pkg_to_pcb_2,P_ERROR,swLogPrintf("udp_send_pkg_to_pcb : malloc pbuf fail "); +293888,603320576,0,0,PLAT_AP,LWIP_CORE,udp_send_pkg_to_pcb_3,P_ERROR,swLogPrintf("udp_send_pkg_to_pcb : reqeust_body 0x%x fail , len %d "); +293888,603322624,0,0,PLAT_AP,LWIP_CORE,udp_send_pkg_to_pcb_4,P_INFO,swLogPrintf("udp_send_pkg_to_pcb : reqeust_body 0x%x success , len %d "); +293888,603326463,0,0,PLAT_AP,LWIP_CORE,udp_send_pkg_to_pcb_5,P_ERROR,swLogPrintf("udp_send_pkg_to_pcb : the pcb is null "); +293888,603328511,0,0,PLAT_AP,LWIP_CORE,udp_send_ul_state_ind_1,P_ERROR,swLogPrintf("udp_send_ul_state_ind : invalid parameter "); +293888,603328512,0,0,PLAT_AP,LWIP_CORE,udp_send_ul_state_ind_body_len_check_1,P_ERROR,swLogPrintf("udp_send_ul_state_ind : invalid len %u big than &u "); +293888,603332607,0,0,PLAT_AP,LWIP_CORE,udp_send_ul_state_ind_3,P_INFO,swLogPrintf("udp_send_ul_state_ind : no sequence state need indicate "); +293888,603334655,0,0,PLAT_AP,LWIP_CORE,udp_send_dns_resolve_result_1,P_ERROR,swLogPrintf("udp_send_dns_resolve_result : invalid parameter "); +293888,603336703,0,0,PLAT_AP,LWIP_CORE,udp_send_dns_resolve_result_2,P_ERROR,swLogPrintf("udp_send_dns_resolve_result : malloc fail "); +293888,603336704,0,0,PLAT_AP,LWIP_CORE,udp_send_ul_total_length_status_1,P_ERROR,swLogPrintf("udp_send_ul_state_ind : invalid len %u big than &u "); +293888,603338752,0,0,PLAT_AP,LWIP_CORE,udp_netif_enter_oos_state_1,P_INFO,swLogPrintf("udp_netif_enter_oos_state pcb 0x%x "); +293888,603340800,0,0,PLAT_AP,LWIP_CORE,udp_netif_exit_oos_state_1,P_INFO,swLogPrintf("udp_netif_exit_oos_state pcb 0x%x "); +293888,603343104,0,0,PLAT_AP,LWIP_CORE,udp_debug_print_1,P_INFO,swLogPrintf("UDP header : | %u | %u | ( src port , dest port ) "); +293888,603345152,0,0,PLAT_AP,LWIP_CORE,udp_debug_print_2,P_INFO,swLogPrintf("UDP header : | %u | %u | ( len , chksum ) "); +294912,603983871,0,0,PLAT_AP,LWIP_CORE_IP,NetifIp4PkgFwdWanFromLanSrcAddrProcess_1,P_INFO,swLogPrintf("update ip4 src addr "); +294912,603985919,0,0,PLAT_AP,LWIP_CORE_IP,NetifIp4PkgFwdLanFromWanDestAddrProcess_1,P_INFO,swLogPrintf("update ip4 dest addr "); +294912,603985920,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_1,P_INFO,swLogPrintf("icmp_input : short IP header ( %u bytes ) received "); +294912,603987968,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_2,P_INFO,swLogPrintf("icmp_input : short ICMP ( %u bytes ) received "); +294912,603992063,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_3,P_INFO,swLogPrintf("icmp_input : Not echoing to multicast pings "); +294912,603994111,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_4,P_INFO,swLogPrintf("icmp_input : Not echoing to broadcast pings "); +294912,603996159,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_5,P_INFO,swLogPrintf("icmp_input : ping "); +294912,603998207,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_6,P_INFO,swLogPrintf("icmp_input : bad ICMP echo received "); +294912,604000255,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_7,P_WARNING,swLogPrintf("icmp_input : checksum failed for received ICMP echo "); +294912,604002303,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_8,P_WARNING,swLogPrintf("icmp_input : allocating new pbuf failed "); +294912,604004351,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_9,P_ERROR,swLogPrintf("icmp_input : moving r->payload to icmp header failed "); +294912,604006399,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_10,P_WARNING,swLogPrintf("icmp_input : copying to new pbuf failed "); +294912,604008447,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_11,P_ERROR,swLogPrintf("icmp_input : restoring original p->payload failed "); +294912,604010495,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_12,P_WARNING,swLogPrintf("icmp_input : Can ' t move over header in packet "); +294912,604010496,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_13,P_WARNING,swLogPrintf("icmp_input : ip_output_if returned an error : %d "); +294912,604012800,0,0,PLAT_AP,LWIP_CORE_IP,icmp_input_14,P_WARNING,swLogPrintf("icmp_input : ICMP type %u code %u not supported "); +294912,604016639,0,0,PLAT_AP,LWIP_CORE_IP,icmp_send_response_1,P_WARNING,swLogPrintf("icmp_time_exceeded : failed to allocate pbuf for ICMP packet. "); +294912,604018687,0,0,PLAT_AP,LWIP_CORE_IP,icmp_send_response_2,P_ERROR,swLogPrintf("check that first pbuf can hold icmp message "); +294912,604020735,0,0,PLAT_AP,LWIP_CORE_IP,icmp_send_response_3,P_INFO,swLogPrintf("icmp_time_exceeded from "); +294912,604022783,0,0,PLAT_AP,LWIP_CORE_IP,icmp_send_responseto_1,P_WARNING,swLogPrintf("icmp_time_exceeded : failed to allocate pbuf for ICMP packet. "); +294912,604024831,0,0,PLAT_AP,LWIP_CORE_IP,icmp_send_responseto_2,P_ERROR,swLogPrintf("check that first pbuf can hold icmp message "); +294912,604026879,0,0,PLAT_AP,LWIP_CORE_IP,icmp_send_responseto_3,P_INFO,swLogPrintf("icmp_time_exceeded from "); +294912,604027648,0,0,PLAT_AP,LWIP_CORE_IP,ip4_route_1,P_INFO,swLogPrintf("ip4_route : No route to %u.%u.%u.%u "); +294912,604029696,0,0,PLAT_AP,LWIP_CORE_IP,ip4_forwardto_1,P_INFO,swLogPrintf("ip4_forwardto : not forwarding LLA %u.%u.%u.%u "); +294912,604031744,0,0,PLAT_AP,LWIP_CORE_IP,ip4_forwardto_2,P_INFO,swLogPrintf("ip4_forwardto : no forwarding route for %u.%u.%u.%u "); +294912,604033792,0,0,PLAT_AP,LWIP_CORE_IP,ip4_forwardto_3,P_INFO,swLogPrintf("ip4_forwardto : forwarding packet to %u.%u.%u.%u "); +294912,604035328,0,0,PLAT_AP,LWIP_CORE_IP,ip4_forwardto_4,P_WARNING,swLogPrintf("ip4_forwardto : netif mtu %u littler than pkg len %u "); +294912,604039167,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_1,P_INFO,swLogPrintf("ip4_input_adpt_process fwd WAN "); +294912,604039424,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_2,P_INFO,swLogPrintf("ip4_input_adpt_process fwd WAN name %c%u "); +294912,604043263,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_3,P_INFO,swLogPrintf("ip4_input_adpt_process fwd LAN "); +294912,604043520,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_4,P_INFO,swLogPrintf("ip4_input_adpt_process fwd LAN name %c%u "); +294912,604047359,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_5,P_INFO,swLogPrintf("ip4_input_adpt_process fwd ETH LAN "); +294912,604047616,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_6,P_INFO,swLogPrintf("ip4_input_adpt_process fwd LAN name %c%u "); +294912,604051455,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_7,P_INFO,swLogPrintf("ip4_input_adpt_process fwd PPP LAN "); +294912,604051712,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_8,P_INFO,swLogPrintf("ip4_input_adpt_process fwd LAN name %c%u "); +294912,604055551,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_9,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd WAN "); +294912,604055808,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_10,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd WAN name %c%u "); +294912,604059647,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_11,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd LAN "); +294912,604059904,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_12,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd LAN name %c%u "); +294912,604063743,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_13,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd ETH LAN "); +294912,604064000,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_14,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd ETH LAN name %c%u "); +294912,604067839,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_15,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd PPP LAN "); +294912,604068096,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_16,P_INFO,swLogPrintf("ip4_input_adpt_process dns pkg fwd PPP LAN name %c%u "); +294912,604071935,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_17,P_INFO,swLogPrintf("ip4_input_adpt_process fwd LAN and input "); +294912,604072192,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_18,P_INFO,swLogPrintf("ip4_input_adpt_process fwd ETH LAN and input name %c%u "); +294912,604074240,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_19,P_INFO,swLogPrintf("ip4_input_adpt_process fwd PPP LAN and input name %c%u "); +294912,604078079,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_adpt_process_20,P_INFO,swLogPrintf("ip4_input_adpt_process discard "); +294912,604078080,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_1,P_INFO,swLogPrintf("IP packet dropped due to bad version number %u "); +294912,604080128,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_2,P_WARNING,swLogPrintf("ip4_input : short IP header ( %u bytes ) received , IP packet dropped "); +294912,604082432,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_3,P_WARNING,swLogPrintf("IP header ( len %u ) does not fit in first pbuf ( len %u ) , IP packet dropped "); +294912,604084480,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_4,P_WARNING,swLogPrintf("IP ( len %u ) is longer than pbuf ( len %u ) , IP packet dropped "); +294912,604086272,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_5,P_WARNING,swLogPrintf("Checksum ( 0x%x ) failed , IP packet dropped "); +294912,604089344,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_pre_13,P_INFO,swLogPrintf("IP packet is a fragment ( id = 0x%x tot_len = %u len = %u MF = %u offset = %u ) , calling ip4_reass ( ) "); +294912,604091392,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_6,P_INFO,swLogPrintf("ip_input : iphdr->dest 0x%x netif->ip_addr 0x%x ( 0x%x , 0x%x , 0x%x ) "); +294912,604092672,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_7,P_INFO,swLogPrintf("ip4_input : packet accepted on interface %c%u "); +294912,604094464,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_9,P_INFO,swLogPrintf("ip4_input : UDP packet to DHCP client port %u "); +294912,604098559,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_10,P_INFO,swLogPrintf("ip4_input : DHCP packet accepted "); +294912,604100607,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_11,P_WARNING,swLogPrintf("ip4_input : packet source is not valid "); +294912,604102655,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_12,P_INFO,swLogPrintf("ip4_input : packet not for us "); +294912,604102912,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_16,P_INFO,swLogPrintf("ip4_input : p->len %u p->tot_len %u "); +294912,604104704,0,0,PLAT_AP,LWIP_CORE_IP,ip4_input_17,P_INFO,swLogPrintf("Unsupported transport protocol %u "); +294912,604108799,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_if_opt_src_2,P_WARNING,swLogPrintf("ip4_output : not enough room for IP header in pbuf "); +294912,604110847,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_if_opt_src_3,P_ERROR,swLogPrintf("check that first pbuf can hold struct ip_hdr "); +294912,604111360,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_if_opt_src_4,P_INFO,swLogPrintf("ip4_output_if : %c%u %u "); +294912,604114943,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_if_opt_src_5,P_INFO,swLogPrintf("netif_loop_output ( ) "); +294912,604116991,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_if_opt_src_6,P_INFO,swLogPrintf("ip4_output_if : call netif->output ( ) "); +294912,604117248,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_if_opt_src_7,P_INFO,swLogPrintf("ip4_output_if : call netif->output ( ) , ticktype %u , systick %u "); +294912,604119808,0,0,PLAT_AP,LWIP_CORE_IP,ip4_output_1,P_WARNING,swLogPrintf("ip4_output : No route to %u.%u.%u.%u "); +294912,604121856,0,0,PLAT_AP,LWIP_CORE_IP,ip4_debug_print_1,P_INFO,swLogPrintf("IP header : |%u|%u|%u|%u| ( v , hl , tos , len ) "); +294912,604124160,0,0,PLAT_AP,LWIP_CORE_IP,ip4_debug_print_2,P_INFO,swLogPrintf("IP header : |%u|%u%u%u|%u| ( id , flags , offset ) "); +294912,604125696,0,0,PLAT_AP,LWIP_CORE_IP,ip4_debug_print_3,P_INFO,swLogPrintf("IP header : |%u|%u|%u| ( ttl , proto , chksum ) "); +294912,604128000,0,0,PLAT_AP,LWIP_CORE_IP,ip4_debug_print_4,P_INFO,swLogPrintf("IP header : |%u|%u|%u|%u| ( src ) "); +294912,604130048,0,0,PLAT_AP,LWIP_CORE_IP,ip4_debug_print_5,P_INFO,swLogPrintf("IP header : |%u|%u|%u|%u| ( dest ) "); +294912,604131328,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_tmr_1,P_INFO,swLogPrintf("ip_reass_tmr : timer dec %u "); +294912,604135423,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_tmr_2,P_INFO,swLogPrintf("ip_reass_tmr : timer timed out "); +294912,604137471,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_free_complete_datagram_1,P_ERROR,swLogPrintf("ip_reass_free_complete_datagram : prev ! = ipr "); +294912,604139519,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_free_complete_datagram_2,P_ERROR,swLogPrintf("ip_reass_free_complete_datagram : prev->next = = ipr "); +294912,604141567,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_free_complete_datagram_3,P_ERROR,swLogPrintf("ip_reass_free_complete_datagram1 : pbufs_freed + clen < = 0xffff "); +294912,604143615,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_free_complete_datagram_4,P_ERROR,swLogPrintf("ip_reass_free_complete_datagram2 : pbufs_freed + clen < = 0xffff "); +294912,604145663,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_free_complete_datagram_5,P_ERROR,swLogPrintf("ip_reass_free_complete_datagram2 : ip_reass_pbufcount > = clen "); +294912,604147711,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_enqueue_new_datagram_1,P_WARNING,swLogPrintf("Failed to alloc reassdata struct "); +294912,604149759,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_dequeue_datagram_1,P_WARNING,swLogPrintf("sanity check linked list "); +294912,604151807,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_chain_frag_into_datagram_and_validate_1,P_ERROR,swLogPrintf("sizeof ( struct ip_reass_helper ) < = IP_HLEN "); +294912,604153855,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_chain_frag_into_datagram_and_validate_2,P_ERROR,swLogPrintf("check fragments don ' t overlap "); +294912,604155903,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_chain_frag_into_datagram_and_validate_3,P_ERROR,swLogPrintf("no previous fragment , this must be the first fragment "); +294912,604157951,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_chain_frag_into_datagram_and_validate_4,P_ERROR,swLogPrintf("sanity check fail or validate_datagram : next_pbuf! = NULL "); +294912,604159999,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_1,P_WARNING,swLogPrintf("ip4_reass : IP options currently not supported! "); +294912,604160512,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_2,P_INFO,swLogPrintf("ip4_reass : Overflow condition : pbufct = %d , clen = %d , MAX = %d "); +294912,604162048,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_3,P_INFO,swLogPrintf("ip4_reass : matching previous fragment ID = %x "); +294912,604166143,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_overlapp_check_1,P_INFO,swLogPrintf("ip4_reass : invalid reass pkg , drop it "); +294912,604166144,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_4,P_INFO,swLogPrintf("ip4_reass : last fragment seen , total len %u "); +294912,604168192,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_5,P_INFO,swLogPrintf("ip_reass_pbufcount : %d out "); +294912,604172287,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_6,P_INFO,swLogPrintf("ip4_reass : nullreturn "); +294912,604174335,0,0,PLAT_AP,LWIP_CORE_IP,ip_frag_free_pbuf_custom_ref_1,P_ERROR,swLogPrintf("ip_frag_free_pbuf_custom_ref : p ! = NULL "); +294912,604176383,0,0,PLAT_AP,LWIP_CORE_IP,ipfrag_free_pbuf_custom_1,P_ERROR,swLogPrintf("ipfrag_free_pbuf_custom : pcr ! = NULL or pcr = = p "); +294912,604178431,0,0,PLAT_AP,LWIP_CORE_IP,ip4_frag_1,P_ERROR,swLogPrintf("ip4_frag ( ) does not support IP options "); +294912,604180479,0,0,PLAT_AP,LWIP_CORE_IP,ip4_frag_2,P_ERROR,swLogPrintf("ip_frag ( ) : MF already set "); +294912,604182527,0,0,PLAT_AP,LWIP_CORE_IP,ip4_frag_4,P_ERROR,swLogPrintf("this needs a pbuf in one piece!2 "); +294912,604183296,0,0,PLAT_AP,LWIP_CORE_IP,ip4_frag_5,P_INFO,swLogPrintf("the new pbuf bexceptdata %u , dataRai %u , ticktype %u , datalifetime %u "); +294912,604186623,0,0,PLAT_AP,LWIP_CORE_IP,ip_reass_timeout_1,P_INFO,swLogPrintf("ip_reass_timeout : timer timed out "); +294912,604188671,0,0,PLAT_AP,LWIP_CORE_IP,tcpip_ip4_reass_timer_1,P_INFO,swLogPrintf("tcpip_ip4_reass_timer : timeout "); +294912,604188672,0,0,PLAT_AP,LWIP_CORE_IP,tcpip_ip4_reass_timer_2,P_INFO,swLogPrintf("tcpip_ip4_reass_timer : enable ip4_rease_timer %u "); +294912,604192767,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_timer_needed_1,P_INFO,swLogPrintf("ip4_reass_timer_needed "); +294912,604192768,0,0,PLAT_AP,LWIP_CORE_IP,ip4_reass_timer_needed_2,P_INFO,swLogPrintf("ip4_reass_timer_needed active tcpip_ip4_reass_timer %u "); +294912,604196863,0,0,PLAT_AP,LWIP_CORE_IP,icmp6_send_response_1,P_INFO,swLogPrintf("icmp_time_exceeded : failed to allocate pbuf for ICMPv6 packet "); +294912,604198911,0,0,PLAT_AP,LWIP_CORE_IP,icmp6_send_response_2,P_ERROR,swLogPrintf("check that first pbuf can hold icmp 6 message "); +294912,604200959,0,0,PLAT_AP,LWIP_CORE_IP,ip6_forward_1,P_INFO,swLogPrintf("ip6_forward : not forwarding link-local address. "); +294912,604202752,0,0,PLAT_AP,LWIP_CORE_IP,ip6_forward_2,P_INFO,swLogPrintf("ip6_forward : no route for %x : %x : %x : %x : %x : %x : %x : %x "); +294912,604205055,0,0,PLAT_AP,LWIP_CORE_IP,ip6_forward_3,P_INFO,swLogPrintf("ip6_forward : not bouncing packets back on incoming interface. "); +294912,604206848,0,0,PLAT_AP,LWIP_CORE_IP,ip6_forward_4,P_INFO,swLogPrintf("ip6_forward : forwarding packet to%x : %x : %x : %x : %x : %x : %x : %x "); +294912,604207104,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_1,P_INFO,swLogPrintf("IPv6 packet dropped due to bad version number %u "); +294912,604209408,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_2,P_WARNING,swLogPrintf("IPv6 header ( len %u ) does not fit in first pbuf ( len %u ) , IP packet dropped. "); +294912,604211456,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_3,P_WARNING,swLogPrintf("IPv6 ( plen %u ) is longer than pbuf ( len %u ) , IP packet dropped. "); +294912,604213504,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_17,P_INFO,swLogPrintf("ip6_input : p->len %u p->tot_len %u "); +294912,604215552,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_solicited_1,P_SIG,swLogPrintf("ip6_input : solicited packet accepted on interface %c%u "); +294912,604217600,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_4,P_INFO,swLogPrintf("ip6_input : solicited node packet accepted on interface %c%u "); +294912,604219648,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_5,P_INFO,swLogPrintf("ip6_input : packet accepted on interface %c%u "); +294912,604223487,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_6,P_INFO,swLogPrintf("ip6_input : packet with src ANY_ADDRESS dropped "); +294912,604225535,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_7,P_INFO,swLogPrintf("ip6_input : packet not for us "); +294912,604227583,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_8,P_INFO,swLogPrintf("ip6_input : packet with Hop-by-Hop options header "); +294912,604227840,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_9,P_WARNING,swLogPrintf("IPv6 options header ( hlen %u ) does not fit in first pbuf ( len %u ) , IPv6 packet dropped1 "); +294912,604231679,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_10,P_INFO,swLogPrintf("ip6_input : packet with Destination options header "); +294912,604231936,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_11,P_WARNING,swLogPrintf("IPv6 options header ( hlen %u ) does not fit in first pbuf ( len %u ) , IPv6 packet dropped2 "); +294912,604235775,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_12,P_INFO,swLogPrintf("ip6_input : packet with Routing header "); +294912,604236032,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_13,P_WARNING,swLogPrintf("IPv6 options header ( hlen %u ) does not fit in first pbuf ( len %u ) , IPv6 packet dropped3 "); +294912,604239871,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_14,P_INFO,swLogPrintf("ip6_input : packet with Fragment header "); +294912,604240128,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_15,P_WARNING,swLogPrintf("IPv6 options header ( hlen %u ) does not fit in first pbuf ( len %u ) , IPv6 packet dropped4 "); +294912,604241920,0,0,PLAT_AP,LWIP_CORE_IP,ip6_input_18,P_WARNING,swLogPrintf("ip6_input : Unsupported transport protocol %u "); +294912,604246015,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_1,P_WARNING,swLogPrintf("ip6_output_if : No suitable source address for packet "); +294912,604248063,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_src_1,P_WARNING,swLogPrintf("ip6_output_if_src : not enough room for IPv6 header in pbuf "); +294912,604250111,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_src_2,P_ERROR,swLogPrintf("ip6_output_if_src : check that first pbuf can hold struct ip6_hdr "); +294912,604250624,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_src_3,P_INFO,swLogPrintf("ip6_output_if : %c%u %u "); +294912,604254207,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_src_4,P_INFO,swLogPrintf("netif_loop_output ( ) "); +294912,604256255,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_src_5,P_INFO,swLogPrintf("netif->output_ip6 ( ) "); +294912,604256512,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_if_src_6,P_INFO,swLogPrintf("netif->output_ip6 ( ) , ticktype %u , systick %u "); +294912,604260096,0,0,PLAT_AP,LWIP_CORE_IP,ip6_output_1,P_INFO,swLogPrintf("ip6_output : no route for %x : %x : %x : %x : %x : %x : %x : %x "); +294912,604260864,0,0,PLAT_AP,LWIP_CORE_IP,ip6_debug_print_1,P_INFO,swLogPrintf("IPv6 header : |%u|%u|%u| ( ver , class , flow ) "); +294912,604262912,0,0,PLAT_AP,LWIP_CORE_IP,ip6_debug_print_2,P_INFO,swLogPrintf("IPv6 header : |%u|%u|%u| ( plen , nexth , hopl ) "); +294912,604266240,0,0,PLAT_AP,LWIP_CORE_IP,ip6_debug_print_3,P_INFO,swLogPrintf("IPv6 header : src %x : %x : %x : %x : %x : %x : %x : %x "); +294912,604268288,0,0,PLAT_AP,LWIP_CORE_IP,ip6_debug_print_4,P_INFO,swLogPrintf("IPv6 header : dest %x : %x : %x : %x : %x : %x : %x : %x "); +294912,604270591,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_tmr_1,P_ERROR,swLogPrintf("sizeof ( struct ip6_reass_helper ) < = IP6_FRAG_HLEN , set IPV6_FRAG_COPYHEADER to 1 "); +294912,604272639,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_free_complete_datagram_1,P_ERROR,swLogPrintf("ip6_reass_free : moving p->payload to ip6 header failed "); +294912,604274687,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_free_complete_datagram_2,P_ERROR,swLogPrintf("pbufs_freed + clen < = 0xffff 1 "); +294912,604276735,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_free_complete_datagram_3,P_ERROR,swLogPrintf("pbufs_freed + clen < = 0xffff 2 "); +294912,604278783,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_free_complete_datagram_4,P_ERROR,swLogPrintf("ip_reass_pbufcount > = clen "); +294912,604280831,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_2,P_ERROR,swLogPrintf("sizeof ( struct ip6_reass_helper ) < = IP6_FRAG_HLEN , set IPV6_FRAG_COPYHEADER to 1 "); +294912,604282879,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_3,P_ERROR,swLogPrintf("check fragments don ' t overlap "); +294912,604284927,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_4,P_ERROR,swLogPrintf("no previous fragment , this must be the first fragment! "); +294912,604286975,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_7,P_ERROR,swLogPrintf("sanity check linked list "); +294912,604289023,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_8,P_ERROR,swLogPrintf("ip6_reass : moving p->payload to ip6 header failed "); +294912,604291071,0,0,PLAT_AP,LWIP_CORE_IP,ip6_frag_free_pbuf_custom_ref_1,P_ERROR,swLogPrintf("ip6_frag_free_pbuf_custom_ref p ! = NULL "); +294912,604293119,0,0,PLAT_AP,LWIP_CORE_IP,ip6_frag_free_pbuf_custom_1,P_ERROR,swLogPrintf("ip6_frag_free_pbuf_custom p ! = NULL or pcr = = p "); +294912,604295167,0,0,PLAT_AP,LWIP_CORE_IP,ip6_frag_2,P_ERROR,swLogPrintf("ip6_frag this needs a pbuf in one piece!2 "); +294912,604295936,0,0,PLAT_AP,LWIP_CORE_IP,ip6_frag_3,P_INFO,swLogPrintf("the new pbuf bexceptdata %u , dataRai %u , ticktype %u , datalifetime %u "); +294912,604299263,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_timer_needed_1,P_INFO,swLogPrintf("ip6_reass_timer_needed "); +294912,604301311,0,0,PLAT_AP,LWIP_CORE_IP,ip6_reass_timer_needed_2,P_INFO,swLogPrintf("ip6_reass_timer_needed active tcpip_ip6_reass_timer "); +294912,604303359,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_rs_refresh_1,P_INFO,swLogPrintf("remove nd6 rs refresh timer "); +294912,604303360,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_rs_refresh_2,P_INFO,swLogPrintf("nd6 enable rs refresh timer %u "); +294912,604307455,0,0,PLAT_AP,LWIP_CORE_IP,nd6_send_disable_ra_1,P_INFO,swLogPrintf("nd6_send_disable_ra the netif linklocal address is invalid , cancel send disable RA packet "); +294912,604307968,0,0,PLAT_AP,LWIP_CORE_IP,nd6_send_disable_ra_2,P_INFO,swLogPrintf("nd6_send_disable_ra , lladdr_opt_len %u , mtu_opt_len %u , prefix_opt_len %u "); +294912,604311551,0,0,PLAT_AP,LWIP_CORE_IP,nd6_send_ra_1,P_INFO,swLogPrintf("nd6_send_ra the netif linklocal address is invalid , cancel send RA packet "); +294912,604312320,0,0,PLAT_AP,LWIP_CORE_IP,nd6_send_ra_2,P_INFO,swLogPrintf("nd6_send_ra , lladdr_opt_len %u , mtu_opt_len %u , prefix_opt_len %u , rdns_opt_len %u "); +294912,604315647,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_ip6_ra_server_1,P_ERROR,swLogPrintf("invalid parameter "); +294912,604317695,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_ip6_ra_server_2,P_ERROR,swLogPrintf("nd6_enable_ip6_ra_server allocate fail "); +294912,604319743,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_ip6_ra_server_3,P_INFO,swLogPrintf("nd6_enable_ip6_ra_server allocate send un solicitate RA success "); +294912,604321791,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_ip6_ra_server_retrans_timer_check_1,P_INFO,swLogPrintf("nd6_enable_ip6_ra_server close ra server first "); +294912,604323839,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_ip6_ra_server_4,P_ERROR,swLogPrintf("nd6_enable_ip6_ra_server allocate send unsolicitate RA fail "); +294912,604325887,0,0,PLAT_AP,LWIP_CORE_IP,nd6_enable_ip6_ra_server_5,P_INFO,swLogPrintf("nd6_enable_ip6_ra_server allocate disable send un solicitate "); +294912,604327935,0,0,PLAT_AP,LWIP_CORE_IP,nd6_resend_ip6_ra_server_1,P_ERROR,swLogPrintf("invalid parameter "); +294912,604329983,0,0,PLAT_AP,LWIP_CORE_IP,nd6_resend_ip6_ra_server_2,P_WARNING,swLogPrintf("can not find IPV6 RA server data "); +294912,604332031,0,0,PLAT_AP,LWIP_CORE_IP,nd6_resend_ip6_ra_server_3,P_INFO,swLogPrintf("nd6_resend_ip6_ra_server send un solicitate RA success "); +294912,604334079,0,0,PLAT_AP,LWIP_CORE_IP,nd6_resend_ip6_ra_server_retrans_timer_check_1,P_INFO,swLogPrintf("nd6_resend_ip6_ra_server close ra server first "); +294912,604336127,0,0,PLAT_AP,LWIP_CORE_IP,nd6_resend_ip6_ra_server_4,P_ERROR,swLogPrintf("nd6_resend_ip6_ra_server send unsolicitate RA fail "); +294912,604338175,0,0,PLAT_AP,LWIP_CORE_IP,nd6_disable_ip6_ra_server_1,P_ERROR,swLogPrintf("invalid parameter "); +294912,604340223,0,0,PLAT_AP,LWIP_CORE_IP,nd6_disable_ip6_ra_server_2,P_INFO,swLogPrintf("disable ipv6 ra retrans timer "); +294912,604342271,0,0,PLAT_AP,LWIP_CORE_IP,nd6_disable_ip6_ra_server_3,P_INFO,swLogPrintf("nd6_disable_ip6_ra_server allocate send un solicitate RA success "); +294912,604344319,0,0,PLAT_AP,LWIP_CORE_IP,nd6_disable_ip6_ra_server_4,P_ERROR,swLogPrintf("nd6_disable_ip6_ra_server allocate send unsolicitate RA fail "); +294912,604344320,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_NA_retry_timer,P_INFO,swLogPrintf("nd6_input , receive NS packet , disable NS retry timer 0x%x "); +294912,604348415,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_RS_1,P_INFO,swLogPrintf("nd6_input , receive RS packet "); +294912,604350463,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_RS_2,P_WARNING,swLogPrintf("nd6_input , receive RS packet , but not exist ra server data "); +294912,604352511,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_RS_3,P_INFO,swLogPrintf("nd6_input , receive RS packet , send RA success "); +294912,604354559,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_RS_4,P_ERROR,swLogPrintf("nd6_input , receive RS packet , send RA fail "); +294912,604356607,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_13,P_INFO,swLogPrintf("nd6_input , receive RA packet , process it depend on the linklocal address is valid "); +294912,604358655,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_6,P_INFO,swLogPrintf("remove nd6 rs retry timer "); +294912,604360703,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_14,P_INFO,swLogPrintf("nd6_input , receive RA packet , but netif without linklocal address , drop it "); +294912,604362751,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_1,P_INFO,swLogPrintf("remove nd6 default router entry timer "); +294912,604362752,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_2,P_INFO,swLogPrintf("nd6 default router entry timer %u "); +294912,604366847,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_3,P_INFO,swLogPrintf("remove nd6 prefix entry timer "); +294912,604366848,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_4,P_INFO,swLogPrintf("nd6 prefix entry timer %u "); +294912,604369408,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_8,P_INFO,swLogPrintf("p6_prefix_info add / update active_time %u , life_time %u , cid %u "); +294912,604372991,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_12,P_INFO,swLogPrintf("active nd6 address rs refresh timer has active "); +294912,604375039,0,0,PLAT_AP,LWIP_CORE_IP,nd6_input_invalid_prefix_info,P_ERROR,swLogPrintf("nd6_input receive RA with invalid prefix information "); +294912,604375296,0,0,PLAT_AP,LWIP_CORE_IP,nd6_neighbor_cache_process_1,P_INFO,swLogPrintf("nd6_neighbor_cache_process enable nd6 ns 0x%x retry timer %u "); +294912,604379135,0,0,PLAT_AP,LWIP_CORE_IP,nd6_router_entry_timer_handler_1,P_INFO,swLogPrintf("nd6_router_entry_timer_handler timeout "); +294912,604381183,0,0,PLAT_AP,LWIP_CORE_IP,nd6_router_entry_timer_handler_2,P_ERROR,swLogPrintf("nd6_router_entry_timer_handler invalid argument "); +294912,604383231,0,0,PLAT_AP,LWIP_CORE_IP,nd6_prefix_entry_timer_handler_1,P_INFO,swLogPrintf("nd6_prefix_entry_timer_handler timeout "); +294912,604385279,0,0,PLAT_AP,LWIP_CORE_IP,nd6_prefix_entry_timer_handler_2,P_ERROR,swLogPrintf("nd6_prefix_entry_timer_handler invalid argument "); +294912,604387327,0,0,PLAT_AP,LWIP_CORE_IP,nd6_address_dad_timer_handler_1,P_INFO,swLogPrintf("nd6_address_dad_timer_handler timeout "); +294912,604389375,0,0,PLAT_AP,LWIP_CORE_IP,nd6_address_dad_timer_handler_2,P_ERROR,swLogPrintf("nd6_address_dad_timer_handler invalid argument "); +294912,604389376,0,0,PLAT_AP,LWIP_CORE_IP,nd6_address_dad_timer_handler_3,P_INFO,swLogPrintf("nd6 address dad timer %u "); +294912,604393471,0,0,PLAT_AP,LWIP_CORE_IP,nd6_rs_retry_timer_handler_1,P_INFO,swLogPrintf("nd6_rs_retry_timer_handler timeout "); +294912,604395519,0,0,PLAT_AP,LWIP_CORE_IP,nd6_rs_retry_timer_handler_2,P_ERROR,swLogPrintf("nd6_rs_retry_timer_handler invalid argument "); +294912,604395520,0,0,PLAT_AP,LWIP_CORE_IP,nd6_rs_retry_timer_handler_3,P_INFO,swLogPrintf("nd6 rs retry timer %u "); +294912,604399615,0,0,PLAT_AP,LWIP_CORE_IP,nd6_rs_refresh_timer_handler_1,P_INFO,swLogPrintf("nd6_rs_refresh_timer_handler timeout "); +294912,604401663,0,0,PLAT_AP,LWIP_CORE_IP,nd6_rs_refresh_timer_handler_2,P_ERROR,swLogPrintf("nd6_rs_refresh_timer_handler invalid argument "); +294912,604401664,0,0,PLAT_AP,LWIP_CORE_IP,nd6_rs_refresh_timer_handler_3,P_INFO,swLogPrintf("nd6 rs refresh timer %u "); +294912,604405759,0,0,PLAT_AP,LWIP_CORE_IP,nd6_start_rs_process_1,P_ERROR,swLogPrintf("nd6_start_rs_process invalid argument "); +294912,604407807,0,0,PLAT_AP,LWIP_CORE_IP,nd6_start_rs_process_2,P_WARNING,swLogPrintf("nd6 not trigger rs procedure "); +294912,604407808,0,0,PLAT_AP,LWIP_CORE_IP,nd6_start_rs_process_3,P_INFO,swLogPrintf("nd6 rs retry timer %u "); +294912,604411903,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ns_retry_timer_handler_1,P_ERROR,swLogPrintf("nd6_ns_retry_timer_handler invalid argument "); +294912,604411904,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ns_retry_timer_handler_2,P_INFO,swLogPrintf("nd6 ns retry has retry total times %u "); +294912,604414208,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ns_retry_timer_handler_3,P_INFO,swLogPrintf("nd6 ns 0x%x retry timer %u "); +294912,604418047,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ra_retrans_timer_handler_1,P_INFO,swLogPrintf("nd6_ra_retrans_timer_handler timeout "); +294912,604420095,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ra_retrans_timer_handler_2,P_ERROR,swLogPrintf("nd6_ra_retrans_timer_handler invalid argument "); +294912,604422143,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ra_retrans_timer_handler_server_data_check_1,P_ERROR,swLogPrintf("nd6_ra_retrans_timer_handler invalid ra server data "); +294912,604424191,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ra_retrans_timer_handler_3,P_INFO,swLogPrintf("nd6_ra_retrans_timer_handler send unsolicitate RA success "); +294912,604426239,0,0,PLAT_AP,LWIP_CORE_IP,nd6_ra_retrans_timer_handler_4,P_ERROR,swLogPrintf("nd6_ra_retrans_timer_handler send unsolicitat RA fail "); +294912,604428287,0,0,PLAT_AP,LWIP_CORE_IP,nd6_send_rs_1,P_INFO,swLogPrintf("nd6_send_rs the netif linklocal address is invalid , cancel send RS packet "); +294912,604428544,0,0,PLAT_AP,LWIP_CORE_IP,nd6_queue_packet_1,P_INFO,swLogPrintf("ipv6 : queued packet 0x%x on neighbor entry %d "); +294912,604430336,0,0,PLAT_AP,LWIP_CORE_IP,nd6_queue_packet_2,P_INFO,swLogPrintf("ipv6 : could not queue a copy of packet 0x%x ( out of memory "); +294912,604432384,0,0,PLAT_AP,LWIP_CORE_IP,nd6_queue_packet_4,P_INFO,swLogPrintf("ipv6 : 2 could not queue a copy of packet 0x%x ( out of memory "); +294912,604436479,0,0,PLAT_AP,LWIP_CORE_IP,nd6_free_q_1,P_ERROR,swLogPrintf("nd6_free_q : q ! = NULL or q->p ! = NULL "); +294912,604438527,0,0,PLAT_AP,LWIP_CORE_IP,nd6_free_q_2,P_ERROR,swLogPrintf("nd6_free_q : r->p ! = NULL "); +294912,604440575,0,0,PLAT_AP,LWIP_CORE_IP,nd6_cleanup_netif_1,P_INFO,swLogPrintf("remove nd6 rs retry timer "); +294912,604442623,0,0,PLAT_AP,LWIP_CORE_IP,nd6_cleanup_netif_2,P_INFO,swLogPrintf("remove nd6 rs refresh timer "); +294912,604444671,0,0,PLAT_AP,LWIP_CORE_IP,nd6_cleanup_netif_3,P_INFO,swLogPrintf("remove nd6 router entry timer "); +294912,604446719,0,0,PLAT_AP,LWIP_CORE_IP,nd6_cleanup_netif_4,P_INFO,swLogPrintf("remove nd6 address dad timer "); +294912,604448767,0,0,PLAT_AP,LWIP_CORE_IP,nd6_cleanup_netif_5,P_INFO,swLogPrintf("remove nd6 prefix entry timer "); +295936,606081023,0,0,PLAT_AP,LWIP_API,netconn_apimsg_1,P_ERROR,swLogPrintf("netconn_apimsg : SYS new sem fail "); +295936,606083071,0,0,PLAT_AP,LWIP_API,netconn_new_with_proto_and_callback_1,P_ERROR,swLogPrintf("netconn_new_with_proto_and_callback : freeing conn without freeing pcb or conn has no recvmbox "); +295936,606085119,0,0,PLAT_AP,LWIP_API,netconn_new_with_proto_and_callback_2,P_ERROR,swLogPrintf("netconn_new_with_proto_and_callback : conn->acceptmbox shouldn ' t exist "); +295936,606087167,0,0,PLAT_AP,LWIP_API,netconn_getaddr_1,P_ERROR,swLogPrintf("netconn_getaddr : argument invalid "); +295936,606089215,0,0,PLAT_AP,LWIP_API,netconn_bind_1,P_ERROR,swLogPrintf("netconn_bind : invalid conn "); +295936,606091263,0,0,PLAT_AP,LWIP_API,netconn_bind_cid_1,P_ERROR,swLogPrintf("netconn_bind_cid : invalid conn "); +295936,606093311,0,0,PLAT_AP,LWIP_API,netconn_alloca_server_port_1,P_ERROR,swLogPrintf("server_port point : invalid parameter "); +295936,606095359,0,0,PLAT_AP,LWIP_API,netconn_connect_1,P_ERROR,swLogPrintf("netconn_connect : invalid conn "); +295936,606097407,0,0,PLAT_AP,LWIP_API,netconn_disconnect_1,P_ERROR,swLogPrintf("netconn_disconnect : invalid conn "); +295936,606099455,0,0,PLAT_AP,LWIP_API,netconn_listen_with_backlog_1,P_ERROR,swLogPrintf("netconn_listen_with_backlog : invalid conn "); +295936,606101503,0,0,PLAT_AP,LWIP_API,netconn_accept_1,P_ERROR,swLogPrintf("netconn_accept : invalid pointer "); +295936,606103551,0,0,PLAT_AP,LWIP_API,netconn_accept_2,P_ERROR,swLogPrintf("netconn_accept : invalid conn "); +295936,606105599,0,0,PLAT_AP,LWIP_API,netconn_recv_data_1,P_ERROR,swLogPrintf("netconn_recv_data : invalid pointer "); +295936,606107647,0,0,PLAT_AP,LWIP_API,netconn_recv_data_2,P_ERROR,swLogPrintf("netconn_recv_data : invalid conn "); +295936,606109695,0,0,PLAT_AP,LWIP_API,netconn_recv_data_3,P_ERROR,swLogPrintf("netconn_recv_data : invalid recvmbox "); +295936,606111743,0,0,PLAT_AP,LWIP_API,netconn_recv_data_7,P_ERROR,swLogPrintf("netconn_recv_data : netif enter OOS state "); +295936,606113791,0,0,PLAT_AP,LWIP_API,netconn_recv_data_6,P_ERROR,swLogPrintf("netconn_recv_data : netif enter OOS state "); +295936,606115839,0,0,PLAT_AP,LWIP_API,netconn_recv_data_9,P_ERROR,swLogPrintf("netconn_recv_data : tcp rcv buff null "); +295936,606117887,0,0,PLAT_AP,LWIP_API,netconn_recv_data_4,P_ERROR,swLogPrintf("netconn_recv_data : buf = = NULL "); +295936,606119935,0,0,PLAT_AP,LWIP_API,netconn_recv_data_8,P_ERROR,swLogPrintf("netconn_recv_data : netif enter OOS state "); +295936,606120192,0,0,PLAT_AP,LWIP_API,netconn_recv_data_5,P_INFO,swLogPrintf("netconn_recv_data : received 0x%x , len = %u "); +295936,606124031,0,0,PLAT_AP,LWIP_API,netconn_recv_tcp_pbuf_1,P_ERROR,swLogPrintf("netconn_recv_tcp_pbuf : invalid conn "); +295936,606126079,0,0,PLAT_AP,LWIP_API,netconn_recv_1,P_ERROR,swLogPrintf("netconn_recv : invalid pointer "); +295936,606128127,0,0,PLAT_AP,LWIP_API,netconn_recv_2,P_ERROR,swLogPrintf("netconn_recv : invalid conn "); +295936,606130175,0,0,PLAT_AP,LWIP_API,netconn_recv_3,P_ERROR,swLogPrintf("netconn_recv : p = = NULL "); +295936,606132223,0,0,PLAT_AP,LWIP_API,netconn_send_1,P_ERROR,swLogPrintf("netconn_send : invalid conn "); +295936,606132224,0,0,PLAT_AP,LWIP_API,netconn_send_2,P_INFO,swLogPrintf("netconn_send : sending %u bytes "); +295936,606136319,0,0,PLAT_AP,LWIP_API,netconn_write_partly_1,P_ERROR,swLogPrintf("netconn_write_partly : invalid conn "); +295936,606138367,0,0,PLAT_AP,LWIP_API,netconn_write_partly_2,P_ERROR,swLogPrintf("netconn_write_partly : invalid conn->type "); +295936,606140415,0,0,PLAT_AP,LWIP_API,netconn_close_shutdown_1,P_ERROR,swLogPrintf("netconn_close_shutdown : invalid conn "); +295936,606142463,0,0,PLAT_AP,LWIP_API,netconn_gethostbyname_addrtype_1,P_ERROR,swLogPrintf("netconn_gethostbyname : invalid name or addr "); +295936,606144511,0,0,PLAT_AP,LWIP_API,netconn_gethostbyname_addrtype_async_1,P_ERROR,swLogPrintf("netconn_gethostbyname_addrtype_async : invalid name "); +295936,606146559,0,0,PLAT_AP,LWIP_API,netconn_get_default_net_info_1,P_WARNING,swLogPrintf("netconn_get_default_net_info : malloc get net info message fail "); +295936,606146560,0,0,PLAT_AP,LWIP_API,netconn_get_default_net_info_2,P_INFO,swLogPrintf("netconn_get_default_net_info %u "); +295936,606150655,0,0,PLAT_AP,LWIP_API,netconn_get_default_net_info_3,P_WARNING,swLogPrintf("netconn_get_default_net_info get net info fail "); +295936,606152703,0,0,PLAT_AP,LWIP_API,netconn_get_sock_info_1,P_WARNING,swLogPrintf("netconn_get_sock_info : malloc get sock info message fail "); +295936,606154751,0,0,PLAT_AP,LWIP_API,netconn_get_sock_info_2,P_INFO,swLogPrintf("netconn_get_sock_info success "); +295936,606156799,0,0,PLAT_AP,LWIP_API,netconn_get_sock_info_3,P_WARNING,swLogPrintf("netconn_get_sock_info get net info fail "); +295936,606158847,0,0,PLAT_AP,LWIP_API,netconn_get_sock_info_by_pcb_1,P_WARNING,swLogPrintf("netconn_get_sock_info_by_pcb : malloc get sock info message fail "); +295936,606160895,0,0,PLAT_AP,LWIP_API,netconn_get_sock_info_by_pcb_2,P_INFO,swLogPrintf("netconn_get_sock_info_by_pcb success "); +295936,606162943,0,0,PLAT_AP,LWIP_API,netconn_get_sock_info_by_pcb_3,P_WARNING,swLogPrintf("netconn_get_sock_info_by_pcb get net info fail "); +295936,606164991,0,0,PLAT_AP,LWIP_API,netconn_get_hib_sock_id_1,P_WARNING,swLogPrintf("netconn_get_hib_sock_id : malloc get sock info message fail "); +295936,606167039,0,0,PLAT_AP,LWIP_API,netconn_get_hib_sock_id_2,P_INFO,swLogPrintf("netconn_get_hib_sock_id success "); +295936,606169087,0,0,PLAT_AP,LWIP_API,netconn_get_hib_sock_id_3,P_WARNING,swLogPrintf("netconn_get_hib_sock_id get hib sockid fail "); +295936,606171135,0,0,PLAT_AP,LWIP_API,netconn_get_tcp_send_buffer_size_1,P_WARNING,swLogPrintf("netconn_get_tcp_send_buffer_size : malloc get tcp send buffer size message fail "); +295936,606173183,0,0,PLAT_AP,LWIP_API,netconn_get_tcp_send_buffer_size_2,P_INFO,swLogPrintf("netconn_get_tcp_send_buffer_size success "); +295936,606175231,0,0,PLAT_AP,LWIP_API,netconn_get_tcp_send_buffer_size_3,P_WARNING,swLogPrintf("netconn_get_tcp_send_buffer_size get tcp send buffer size fail "); +295936,606177279,0,0,PLAT_AP,LWIP_API,process_oos_tcp_1,P_ERROR,swLogPrintf("process_oos_tcp : conn = = NULL "); +295936,606179327,0,0,PLAT_AP,LWIP_API,recv_udp_1,P_ERROR,swLogPrintf("recv_udp : invalid argument "); +295936,606181375,0,0,PLAT_AP,LWIP_API,recv_udp_2,P_ERROR,swLogPrintf("recv_udp : recv for wrong pcb! "); +295936,606183423,0,0,PLAT_AP,LWIP_API,recv_tcp_1,P_ERROR,swLogPrintf("recv_tcp : invalid argument "); +295936,606185471,0,0,PLAT_AP,LWIP_API,recv_tcp_2,P_ERROR,swLogPrintf("recv_tcp : recv for wrong pcb! "); +295936,606187519,0,0,PLAT_AP,LWIP_API,poll_tcp_1,P_ERROR,swLogPrintf("poll_tcp : conn ! = NULL "); +295936,606189567,0,0,PLAT_AP,LWIP_API,sent_tcp_1,P_ERROR,swLogPrintf("sent_tcp : conn ! = NULL "); +295936,606191615,0,0,PLAT_AP,LWIP_API,err_tcp_1,P_ERROR,swLogPrintf("err_tcp : conn ! = NULL "); +295936,606191872,0,0,PLAT_AP,LWIP_API,err_tcp_state_1,P_INFO,swLogPrintf("err_tcp : state %u , old state %u "); +295936,606195711,0,0,PLAT_AP,LWIP_API,err_tcp_2,P_ERROR,swLogPrintf("err_tcp : conn->current_msg ! = NULL "); +295936,606197759,0,0,PLAT_AP,LWIP_API,err_tcp_3,P_ERROR,swLogPrintf("err_tcp : inavlid op_completed_sem "); +295936,606199807,0,0,PLAT_AP,LWIP_API,err_tcp_info,P_INFO,swLogPrintf("err_tcp : send signal "); +295936,606201855,0,0,PLAT_AP,LWIP_API,err_tcp_4,P_ERROR,swLogPrintf("err_tcp : conn->current_msg ! = NULL 2 "); +295936,606203903,0,0,PLAT_AP,LWIP_API,accept_function_1,P_INFO,swLogPrintf("accept_function : acceptmbox already deleted "); +295936,606203904,0,0,PLAT_AP,LWIP_API,accept_function_2,P_INFO,swLogPrintf("accept_function : newpcb->tate : %d "); +295936,606207999,0,0,PLAT_AP,LWIP_API,netconn_get_socket_id_1,P_ERROR,swLogPrintf("netconn_get_socket_id invalid conn "); +295936,606210047,0,0,PLAT_AP,LWIP_API,pcb_new_1,P_ERROR,swLogPrintf("pcb_new : pcb already allocated "); +295936,606212095,0,0,PLAT_AP,LWIP_API,netconn_alloc_1,P_ERROR,swLogPrintf("netconn_alloc : undefined netconn_type "); +295936,606214143,0,0,PLAT_AP,LWIP_API,netconn_free_1,P_ERROR,swLogPrintf("netconn_free : PCB must be deallocated outside this function "); +295936,606216191,0,0,PLAT_AP,LWIP_API,netconn_free_2,P_ERROR,swLogPrintf("netconn_free : acceptmbox must be deallocated before calling this functionn "); +295936,606218239,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_close_internal_1,P_ERROR,swLogPrintf("lwip_netconn_do_close_internal : conn check fail "); +295936,606218240,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_close_internal_close_local_abort_time_1,P_INFO,swLogPrintf("lwip_netconn_do_close_internal : block close , need wait max time %u "); +295936,606222335,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_close_internal_2,P_ERROR,swLogPrintf("lwip_netconn_do_close_internal : Closing a listen pcb may not fail! "); +295936,606224383,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_close_internal_3,P_ERROR,swLogPrintf("lwip_netconn_do_close_internal : err ! = ERR_OK "); +295936,606226431,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_1,P_ERROR,swLogPrintf("lwip_netconn_do_delconn : netconn state error "); +295936,606228479,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_3,P_ERROR,swLogPrintf("lwip_netconn_do_delconn : blocking connect in progress "); +295936,606230527,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_15,P_INFO,swLogPrintf("lwip_netconn_do_delconn : remove check udp hib pcb "); +295936,606232575,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_16,P_INFO,swLogPrintf("lwip_netconn_do_delconn : remove udp hib pcb "); +295936,606234623,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_17,P_INFO,swLogPrintf("lwip_netconn_do_delconn : reduce udp hib num "); +295936,606236671,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_18,P_INFO,swLogPrintf("lwip_netconn_do_delconn : set the global sequence handler pcb as NULL "); +295936,606238719,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_delconn_4,P_ERROR,swLogPrintf("lwip_netconn_do_delconn : already writing or closing "); +295936,606240767,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_1,P_INFO,swLogPrintf("lwip_netconn_do_bind process hib pcb "); +295936,606242815,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_2,P_INFO,swLogPrintf("lwip_netconn_do_bind udp hib pcb exist "); +295936,606244863,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_3,P_INFO,swLogPrintf("lwip_netconn_do_bind udp hib adapt the udp bind action "); +295936,606245120,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_4,P_WARNING,swLogPrintf("lwip_netconn_do_bind socket id is not adapt , hib pcb %u , this conn %u "); +295936,606248959,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_5,P_INFO,swLogPrintf("lwip_netconn_do_bind hib udp pcb bind success , change hib udp pcb context "); +295936,606251007,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_6,P_ERROR,swLogPrintf("lwip_netconn_do_bind get hib udp pcb fail "); +295936,606251008,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_cid_default,P_WARNING,swLogPrintf("can ' t find netif for CID : %d , try to use default netif "); +295936,606253056,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_bind_cid_1,P_WARNING,swLogPrintf("lwip_netconn_do_bind_cid can not find adapt netif by cid %u "); +295936,606255104,0,0,PLAT_AP,LWIP_API,lwip_netconn_alloc_server_port_1,P_INFO,swLogPrintf("lwip_netconn_alloc_server_port alloc udp server port %d "); +295936,606257152,0,0,PLAT_AP,LWIP_API,lwip_netconn_alloc_server_port_2,P_INFO,swLogPrintf("lwip_netconn_alloc_server_port alloc tcp server port %d "); +295936,606261247,0,0,PLAT_AP,LWIP_API,lwip_netconn_alloc_server_port_3,P_ERROR,swLogPrintf("lwip_netconn_alloc_server_port invalid type "); +295936,606263295,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_net_info_with_cid_1,P_WARNING,swLogPrintf("lwip_netconn_get_net_info_with_cid invalid argument "); +295936,606265343,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_net_info_with_cid_2,P_WARNING,swLogPrintf("lwip_netconn_get_net_info_with_cid can not find any netif "); +295936,606267391,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_1,P_WARNING,swLogPrintf("lwip_netconn_get_sock_info invalid argument "); +295936,606269439,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_2,P_INFO,swLogPrintf("lwip_netconn_get_sock_info get tcp adapt hib pcb fail "); +295936,606271487,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_3,P_INFO,swLogPrintf("lwip_netconn_get_sock_info get udp adapt hib pcb fail "); +295936,606273535,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_4,P_INFO,swLogPrintf("lwip_netconn_get_sock_info get udp adapt hib pcb success "); +295936,606275583,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_5,P_INFO,swLogPrintf("lwip_netconn_get_sock_info get tcp adapt hib pcb success "); +295936,606277631,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_by_pcb_1,P_WARNING,swLogPrintf("lwip_netconn_get_sock_info_by_pcb invalid argument "); +295936,606279679,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_by_pcb_2,P_INFO,swLogPrintf("lwip_netconn_get_sock_info get tcp adapt pcb fail "); +295936,606281727,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_by_pcb_3,P_INFO,swLogPrintf("lwip_netconn_get_sock_info_by_pcb get udp adapt pcb fail "); +295936,606281728,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_sock_info_by_pcb_4,P_INFO,swLogPrintf("lwip_netconn_get_sock_info_by_pcb get adpt pcb fail , type %d "); +295936,606285823,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_hib_sock_id_1,P_WARNING,swLogPrintf("lwip_netconn_get_hib_sock_id invalid argument "); +295936,606287871,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_tcp_send_buffer_size_1,P_WARNING,swLogPrintf("lwip_netconn_get_tcp_send_buffer_size invalid argument "); +295936,606289919,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_tcp_send_buffer_size_2,P_WARNING,swLogPrintf("lwip_netconn_get_tcp_send_buffer_size invalid connection "); +295936,606291967,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_tcp_send_buffer_size_3,P_WARNING,swLogPrintf("lwip_netconn_get_tcp_send_buffer_size the connection is not tcp connection "); +295936,606291968,0,0,PLAT_AP,LWIP_API,lwip_netconn_get_tcp_send_buffer_size_4,P_INFO,swLogPrintf("lwip_netconn_get_tcp_send_buffer_size the tcp connection buffer size %u "); +295936,606296063,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connected_1,P_ERROR,swLogPrintf("lwip_netconn_do_connected : conn->state = = NETCONN_CONNECT "); +295936,606298111,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connected_2,P_ERROR,swLogPrintf("lwip_netconn_do_connected : ( conn->current_msg ! = NULL ) || conn->in_non_blocking_connect "); +295936,606300159,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connected_3,P_ERROR,swLogPrintf("lwip_netconn_do_connected : blocking connect state error "); +295936,606302207,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connected_4,P_INFO,swLogPrintf("lwip_netconn_do_connected : connected success "); +295936,606304255,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_1,P_INFO,swLogPrintf("lwip_netconn_do_connect : udp pcb active "); +295936,606306303,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_2,P_INFO,swLogPrintf("lwip_netconn_do_connect : udp pcb active and remote ip / port change "); +295936,606308351,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_3,P_INFO,swLogPrintf("lwip_netconn_do_connect : udp pcb active and update udp hib pcb list "); +295936,606310399,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_4,P_INFO,swLogPrintf("lwip_netconn_do_connect : udp hib pcb is not NULL "); +295936,606312447,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_5,P_INFO,swLogPrintf("lwip_netconn_do_connect : reuse udp hib pcb "); +295936,606312704,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_13,P_WARNING,swLogPrintf("lwip_netconn_do_connect : socket id is not adapt , hib pcb id %u , this conn id %u "); +295936,606316543,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_6,P_INFO,swLogPrintf("lwip_netconn_do_connect : the hib udp pcb has include in udp active list "); +295936,606318591,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_7,P_INFO,swLogPrintf("lwip_netconn_do_connect : the udp pcb hib / sleep2 is not enable "); +295936,606320639,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_8,P_SIG,swLogPrintf("lwip_netconn_do_connect : tcp connection find adpt hib / sleep2 tcp context "); +295936,606322687,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_9,P_SIG,swLogPrintf("lwip_netconn_do_connect : the hib tcp pcb has include in tcp active list "); +295936,606324735,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_connect_12,P_ERROR,swLogPrintf("lwip_netconn_do_connect : Invalid netconn type "); +295936,606324736,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_send_1,P_WARNING,swLogPrintf("lwip_netconn_do_send : last err is fatal %d "); +295936,606328831,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_send_4,P_WARNING,swLogPrintf("lwip_netconn_do_send : last err is ERR_IF_OOS "); +295936,606330879,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_writemore_1,P_ERROR,swLogPrintf("lwip_netconn_do_writemore : conn check fail "); +295936,606332927,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_writemore_2,P_ERROR,swLogPrintf("lwip_netconn_do_writemore : invalid length "); +295936,606334975,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_write_4,P_WARNING,swLogPrintf("lwip_netconn_do_write : err is ERR_IF_OOS "); +295936,606337023,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_write_1,P_ERROR,swLogPrintf("lwip_netconn_do_write : already writing or closing "); +295936,606339071,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_getaddr_1,P_ERROR,swLogPrintf("lwip_netconn_do_getaddr : invalid netconn_type "); +295936,606341119,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_close_3,P_ERROR,swLogPrintf("lwip_netconn_do_close : already writing or closing "); +295936,606343167,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_dns_found_async_1,P_ERROR,swLogPrintf("lwip_netconn_do_dns_found_async : src_hdr point is null "); +295936,606345215,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_dns_found_async_by_cmsSockMgr_1,P_ERROR,swLogPrintf("lwip_netconn_do_dns_found_async_by_cmsSockMgr : source point is null "); +295936,606347263,0,0,PLAT_AP,LWIP_API,lwip_netconn_do_dns_found_async_by_cmsSockMgr_2,P_INFO,swLogPrintf("lwip_netconn_do_dns_found_async_by_cmsSockMgr : complete "); +295936,606349311,0,0,PLAT_AP,LWIP_API,netbuf_alloc_1,P_ERROR,swLogPrintf("netbuf_alloc : invalid buf "); +295936,606351359,0,0,PLAT_AP,LWIP_API,netbuf_alloc_2,P_ERROR,swLogPrintf("netbuf_alloc : check that first pbuf can hold size "); +295936,606353407,0,0,PLAT_AP,LWIP_API,netbuf_free_1,P_ERROR,swLogPrintf("netbuf_free : invalid buf "); +295936,606355455,0,0,PLAT_AP,LWIP_API,netbuf_ref_1,P_ERROR,swLogPrintf("netbuf_ref : invalid buf "); +295936,606357503,0,0,PLAT_AP,LWIP_API,netbuf_chain_1,P_ERROR,swLogPrintf("netbuf_chain : invalid head or tail "); +295936,606359551,0,0,PLAT_AP,LWIP_API,netbuf_data_1,P_ERROR,swLogPrintf("netbuf_data : invalid argument "); +295936,606361599,0,0,PLAT_AP,LWIP_API,netbuf_next_1,P_ERROR,swLogPrintf("netbuf_next : invalid buff "); +295936,606363647,0,0,PLAT_AP,LWIP_API,netbuf_first_1,P_ERROR,swLogPrintf("netbuf_first : invalid buff "); +295936,606363648,0,0,PLAT_AP,LWIP_API,lwip_gethostbyname_1,P_INFO,swLogPrintf("lwip_gethostbyname failed , err = %d "); +295936,606366464,0,0,PLAT_AP,LWIP_API,lwip_gethostbyname_2,P_INFO,swLogPrintf("lwip_gethostbyname hostent.h_name , hostent.h_aliases ( 0x%x ) , hostent.h_addrtype ( %d ) , hostent.h_length ( %d ) , hostent.h_addr_list ( 0x%x ) "); +295936,606368000,0,0,PLAT_AP,LWIP_API,lwip_gethostbyname_3,P_INFO,swLogPrintf("lwip_gethostbyname hostent.h_addr_list [ %u ] ( 0x%x ) "); +295936,606369792,0,0,PLAT_AP,LWIP_API,lwip_gethostbyname_r_1,P_INFO,swLogPrintf("lwip_gethostbyname_r failed , err = %d "); +295936,606371840,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfo_get_addpt_type_1,P_INFO,swLogPrintf("lwip_getaddrinfo get default net info %u "); +295936,606375935,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfo_1,P_ERROR,swLogPrintf("lwip_getaddrinfo namelen is too long "); +295936,606377983,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfo_2,P_ERROR,swLogPrintf("lwip_getaddrinfo total_size < = NETDB_ELEM_SIZE : please report this "); +295936,606380031,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfo_3,P_ERROR,swLogPrintf("lwip_getaddrinfo wrong sockaddr family "); +295936,606380032,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfowithcid_1,P_INFO,swLogPrintf("lwip_getaddrinfowithcid get cid net info %u "); +295936,606384127,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfowithcid_2,P_ERROR,swLogPrintf("lwip_getaddrinfo namelen is too long "); +295936,606386175,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfowithcid_3,P_ERROR,swLogPrintf("lwip_getaddrinfo total_size < = NETDB_ELEM_SIZE : please report this "); +295936,606388223,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfowithcid_4,P_ERROR,swLogPrintf("lwip_getaddrinfo wrong sockaddr family "); +295936,606388224,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfo_async_1,P_INFO,swLogPrintf("lwip_getaddrinfo_async get cid net info %u "); +295936,606390272,0,0,PLAT_AP,LWIP_API,lwip_getaddrinfo_async_by_cmsSockMgr_1,P_INFO,swLogPrintf("lwip_getaddrinfo_async_by_cmsSockMgr get cid net info %u "); +295936,606392320,0,0,PLAT_AP,LWIP_API,get_socket_1,P_WARNING,swLogPrintf("get_socket ( %d ) : invalid "); +295936,606394368,0,0,PLAT_AP,LWIP_API,get_socket_2,P_WARNING,swLogPrintf("get_socket ( %d ) : not active "); +295936,606396672,0,0,PLAT_AP,LWIP_API,alloc_socket_1,P_INFO,swLogPrintf("alloc_socket get tcp hib sockid %d , udp hib sockid %d success "); +295936,606400511,0,0,PLAT_AP,LWIP_API,alloc_socket_2,P_WARNING,swLogPrintf("alloc_socket get hib sockid fail "); +295936,606400512,0,0,PLAT_AP,LWIP_API,lwip_accept_1,P_INFO,swLogPrintf("lwip_accept ( %d ) "); +295936,606402560,0,0,PLAT_AP,LWIP_API,lwip_accept_2,P_INFO,swLogPrintf("lwip_accept ( %d ) returning EWOULDBLOCK "); +295936,606404864,0,0,PLAT_AP,LWIP_API,lwip_accept_3,P_INFO,swLogPrintf("lwip_accept ( %d ) netconn_acept failed , err = %d "); +295936,606408703,0,0,PLAT_AP,LWIP_API,lwip_accept_4,P_ERROR,swLogPrintf("lwip_accept newconn ! = NULL "); +295936,606410751,0,0,PLAT_AP,LWIP_API,lwip_accept_5,P_ERROR,swLogPrintf("lwip_accept invalid socket index "); +295936,606412799,0,0,PLAT_AP,LWIP_API,lwip_accept_6,P_ERROR,swLogPrintf("lwip_accept newconn->callback = = event_callback "); +295936,606413056,0,0,PLAT_AP,LWIP_API,lwip_accept_7,P_INFO,swLogPrintf("lwip_accept ( %d ) netconn_peer failed , err = %d "); +295936,606416895,0,0,PLAT_AP,LWIP_API,lwip_accept_8,P_ERROR,swLogPrintf("lwip_accept addr valid but addrlen NULL "); +295936,606417408,0,0,PLAT_AP,LWIP_API,lwip_accept_9,P_INFO,swLogPrintf("lwip_accept ( %d ) returning new sock = %d port %d "); +295936,606419200,0,0,PLAT_AP,LWIP_API,lwip_accept_10,P_INFO,swLogPrintf("lwip_accept ( %d ) returning new sock = %d "); +295936,606423039,0,0,PLAT_AP,LWIP_API,lwip_bind_1,P_ERROR,swLogPrintf("lwip_bind : invalid address "); +295936,606423296,0,0,PLAT_AP,LWIP_API,lwip_bind_2,P_INFO,swLogPrintf("lwip_bind ( %d , port = %u ) "); +295936,606425344,0,0,PLAT_AP,LWIP_API,lwip_bind_3,P_WARNING,swLogPrintf("lwip_bind ( %d ) failed , err = %d "); +295936,606427136,0,0,PLAT_AP,LWIP_API,lwip_bind_4,P_INFO,swLogPrintf("lwip_bind ( %d ) succeeded "); +295936,606429440,0,0,PLAT_AP,LWIP_API,lwip_bind_cid_2,P_INFO,swLogPrintf("lwip_bind_cid ( socket %d cid = %u ) "); +295936,606431488,0,0,PLAT_AP,LWIP_API,lwip_bind_cid_3,P_WARNING,swLogPrintf("lwip_bind_cid ( %d ) failed , err = %d "); +295936,606433280,0,0,PLAT_AP,LWIP_API,lwip_bind_cid_4,P_INFO,swLogPrintf("lwip_bind_cid ( %d ) succeeded "); +295936,606435328,0,0,PLAT_AP,LWIP_API,lwip_alloc_server_port_1,P_INFO,swLogPrintf("lwip_alloc_server_port type %u "); +295936,606437376,0,0,PLAT_AP,LWIP_API,lwip_alloc_server_port_2,P_WARNING,swLogPrintf("lwip_alloc_server_port invalid type %u "); +295936,606439680,0,0,PLAT_AP,LWIP_API,lwip_alloc_server_port_3,P_WARNING,swLogPrintf("lwip_alloc_server_port type ( %u ) failed , err = %d "); +295936,606441472,0,0,PLAT_AP,LWIP_API,sock_get_errno_1,P_INFO,swLogPrintf("sock_get_errno ( %d ) "); +295936,606443520,0,0,PLAT_AP,LWIP_API,lwip_close_1,P_INFO,swLogPrintf("lwip_close ( %d ) "); +295936,606447615,0,0,PLAT_AP,LWIP_API,lwip_close_2,P_ERROR,swLogPrintf("lwip_close sock->lastdata = = NULL "); +295936,606447616,0,0,PLAT_AP,LWIP_API,lwip_close_3,P_INFO,swLogPrintf("lwip_close result %d "); +295936,606449664,0,0,PLAT_AP,LWIP_API,lwip_connect_1,P_INFO,swLogPrintf("lwip_connect ( %d , AF_UNSPEC ) "); +295936,606453759,0,0,PLAT_AP,LWIP_API,lwip_connect_2,P_ERROR,swLogPrintf("lwip_connect : invalid address "); +295936,606454016,0,0,PLAT_AP,LWIP_API,lwip_connect_3,P_INFO,swLogPrintf("lwip_connect ( %d , port = %u ) "); +295936,606456064,0,0,PLAT_AP,LWIP_API,lwip_connect_4,P_INFO,swLogPrintf("lwip_connect ( %d ) failed , err = %d "); +295936,606457856,0,0,PLAT_AP,LWIP_API,lwip_connect_5,P_INFO,swLogPrintf("lwip_connect ( %d ) has already connected succeeded "); +295936,606459904,0,0,PLAT_AP,LWIP_API,lwip_connect_6,P_INFO,swLogPrintf("lwip_connect ( %d ) succeeded "); +295936,606462208,0,0,PLAT_AP,LWIP_API,lwip_listen_1,P_INFO,swLogPrintf("lwip_listen ( %d , backlog = %d ) "); +295936,606464256,0,0,PLAT_AP,LWIP_API,lwip_listen_2,P_INFO,swLogPrintf("lwip_listen ( %d ) failed , err = %d "); +295936,606466816,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_1,P_INFO,swLogPrintf("lwip_recvfrom ( %d , 0x%x , %u , 0x%x , .. ) "); +295936,606468096,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_2,P_INFO,swLogPrintf("lwip_recvfrom : top while sock->lastdata = 0x%x "); +295936,606470144,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_3,P_INFO,swLogPrintf("lwip_recvfrom ( %d ) : returning EWOULDBLOCK "); +295936,606472448,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_4,P_INFO,swLogPrintf("lwip_recvfrom netconn_recv err = %d , netbuf = 0x%x "); +295936,606474496,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_5,P_INFO,swLogPrintf("lwip_recvfrom ( %d ) : buf = = NULL , error is %d "); +295936,606478335,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_6,P_ERROR,swLogPrintf("lwip_recvfrom buf ! = NULL "); +295936,606479104,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_7,P_INFO,swLogPrintf("lwip_recvfrom : buflen = %u len = %u off = %d sock->lastoffset = %u "); +295936,606482431,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_8,P_ERROR,swLogPrintf("lwip_recvfrom invalid copylen , len would underflow "); +295936,606482688,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_9,P_INFO,swLogPrintf("lwip_recvfrom : port = %u len = %d "); +295936,606484480,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_10,P_INFO,swLogPrintf("lwip_recvfrom : lastdata now netbuf = 0x%x "); +295936,606486528,0,0,PLAT_AP,LWIP_API,lwip_recvfrom_11,P_INFO,swLogPrintf("lwip_recvfrom : deleting netbuf = 0x%x "); +295936,606489344,0,0,PLAT_AP,LWIP_API,lwip_send_1,P_INFO,swLogPrintf("lwip_send ( %d , data = 0x%x , size = %u , flags = 0x%x ) "); +295936,606491136,0,0,PLAT_AP,LWIP_API,lwip_send_2,P_INFO,swLogPrintf("lwip_send ( %d ) err = %d written = %u ) "); +295936,606494719,0,0,PLAT_AP,LWIP_API,lwip_sendmsg_1,P_ERROR,swLogPrintf("lwip_sendmsg : invalid msghdr "); +295936,606496767,0,0,PLAT_AP,LWIP_API,lwip_sendmsg_2,P_ERROR,swLogPrintf("lwip_sendmsg : invalid msghdr iov "); +295936,606498815,0,0,PLAT_AP,LWIP_API,lwip_sendmsg_3,P_ERROR,swLogPrintf("lwip_sendmsg : invalid msghdr name "); +295936,606500863,0,0,PLAT_AP,LWIP_API,lwip_sendmsg_4,P_ERROR,swLogPrintf("lwip_sendmsg : iov_len < u16_t "); +295936,606502144,0,0,PLAT_AP,LWIP_API,ps_send_1,P_INFO,swLogPrintf("ps_send ( %d , data = 0x%x , size = %u , flags = 0x%x ) , dataRai = %u , exceptdata = %u "); +295936,606503168,0,0,PLAT_AP,LWIP_API,ps_send_2,P_WARNING,swLogPrintf("ps_send invalid dataRai %u or exceptdata %u "); +295936,606505472,0,0,PLAT_AP,LWIP_API,ps_send_3,P_INFO,swLogPrintf("ps_send ( %d ) err = %d written = %u ) "); +295936,606507264,0,0,PLAT_AP,LWIP_API,ps_sendto_1,P_WARNING,swLogPrintf("ps_sendto invalid dataRai %u or exceptdata %u "); +295936,606510848,0,0,PLAT_AP,LWIP_API,ps_sendto_2,P_INFO,swLogPrintf("ps_sendto ( %d , data = 0x%x , size = %u , flags = 0x%x , to addr = 0x%x , tolen = %u , dataRai = %u , exceptdata = %u "); +295936,606513151,0,0,PLAT_AP,LWIP_API,ps_sendto_3,P_ERROR,swLogPrintf("ps_sendto : size must fit in u16_t "); +295936,606515199,0,0,PLAT_AP,LWIP_API,ps_sendto_4,P_ERROR,swLogPrintf("ps_sendto : invalid address "); +295936,606517247,0,0,PLAT_AP,LWIP_API,ps_sendto_5,P_WARNING,swLogPrintf("ps_sendto low-level netif high water "); +295936,606517248,0,0,PLAT_AP,LWIP_API,ps_sendto_6,P_INFO,swLogPrintf("ps_sendto low-level netif high water , current UE packet delay %u "); +295936,606521088,0,0,PLAT_AP,LWIP_API,ps_send_with_ticks_1,P_INFO,swLogPrintf("ps_send ( %d , data = 0x%x , size = %u , flags = 0x%x ) , dataRai = %u , exceptdata = %u , tick type %u , sys tick %u "); +295936,606521600,0,0,PLAT_AP,LWIP_API,ps_send_with_ticks_2,P_WARNING,swLogPrintf("ps_send invalid dataRai %u or exceptdata %u "); +295936,606523904,0,0,PLAT_AP,LWIP_API,ps_send_with_ticks_3,P_INFO,swLogPrintf("ps_send ( %d ) err = %d written = %u ) "); +295936,606525696,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_1,P_WARNING,swLogPrintf("ps_sendto invalid dataRai %u or exceptdata %u "); +295936,606528768,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_2,P_INFO,swLogPrintf("ps_sendto ( %d , data = 0x%x , size = %u , flags = 0x%x , to addr = 0x%x , tolen = %u "); +295936,606530304,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_printf_2,P_INFO,swLogPrintf("ps_sendto ( continue... , dataRai = %u , exceptdata = %u , tick type %u , sys tick %u "); +295936,606533631,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_3,P_ERROR,swLogPrintf("ps_sendto : size must fit in u16_t "); +295936,606535679,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_4,P_ERROR,swLogPrintf("ps_sendto : invalid address "); +295936,606535936,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_5,P_INFO,swLogPrintf("ps_sendto_with_ticks tick type %u , sys tick %u "); +295936,606539775,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_6,P_WARNING,swLogPrintf("ps_sendto low-level netif high water "); +295936,606539776,0,0,PLAT_AP,LWIP_API,ps_sendto_with_ticks_7,P_INFO,swLogPrintf("ps_sendto low-level netif high water , current UE packet delay %u "); +295936,606541824,0,0,PLAT_AP,LWIP_API,lwip_get_tcp_send_buffer_size_1,P_ERROR,swLogPrintf("lwip_get_tcp_send_buffer_size can not find the socket %d "); +295936,606544128,0,0,PLAT_AP,LWIP_API,lwip_get_tcp_send_buffer_size_2,P_INFO,swLogPrintf("lwip_get_tcp_send_buffer_size get the socket %d send buffer size %u "); +295936,606545920,0,0,PLAT_AP,LWIP_API,lwip_get_tcp_send_buffer_size_3,P_ERROR,swLogPrintf("lwip_get_tcp_send_buffer_size get the socket %d send buffer size fail "); +295936,606549248,0,0,PLAT_AP,LWIP_API,lwip_sendto_1,P_INFO,swLogPrintf("lwip_sendto ( %d , data = 0x%x , size = %u , flags = 0x%x , to addr = 0x%x , tolen = %u "); +295936,606552063,0,0,PLAT_AP,LWIP_API,lwip_sendto_2,P_ERROR,swLogPrintf("lwip_sendto : size must fit in u16_t "); +295936,606554111,0,0,PLAT_AP,LWIP_API,lwip_sendto_3,P_ERROR,swLogPrintf("lwip_sendto : invalid address "); +295936,606556159,0,0,PLAT_AP,LWIP_API,lwip_sendto_5,P_WARNING,swLogPrintf("lwip_sendto low-level netif high water "); +295936,606556160,0,0,PLAT_AP,LWIP_API,lwip_sendto_6,P_INFO,swLogPrintf("lwip_sendto low-level netif high water , current UE packet delay %u "); +295936,606558464,0,0,PLAT_AP,LWIP_API,lwip_socket_1,P_INFO,swLogPrintf("lwip_socket ( %d , SOCK_RAW , %d ) = "); +295936,606560512,0,0,PLAT_AP,LWIP_API,lwip_socket_2,P_INFO,swLogPrintf("lwip_socket ( %d , SOCK_DGRAM , %d ) = "); +295936,606562560,0,0,PLAT_AP,LWIP_API,lwip_socket_3,P_INFO,swLogPrintf("lwip_socket ( %d , SOCK_STREAM , %d ) = "); +295936,606564864,0,0,PLAT_AP,LWIP_API,lwip_socket_4,P_INFO,swLogPrintf("lwip_socket ( %d , %d / UNKNOWN , %d ) = -1 "); +295936,606568447,0,0,PLAT_AP,LWIP_API,lwip_socket_5,P_WARNING,swLogPrintf("lwip_socket -1 / ENOBUFS ( could not create netconn ) "); +295936,606568448,0,0,PLAT_AP,LWIP_API,lwip_get_socket_info_by_fd_1,P_INFO,swLogPrintf("lwip_get_socket_info_by_fd get sock %d info fail "); +295936,606570496,0,0,PLAT_AP,LWIP_API,lwip_get_socket_info_by_fd_2,P_INFO,swLogPrintf("lwip_get_socket_info_by_fd get sock %d info by tcp pcb fail "); +295936,606572544,0,0,PLAT_AP,LWIP_API,lwip_get_socket_info_by_fd_3,P_INFO,swLogPrintf("lwip_get_socket_info_by_fd get sock %d info udp by pcb fail "); +295936,606574592,0,0,PLAT_AP,LWIP_API,lwip_get_socket_info_by_fd_4,P_INFO,swLogPrintf("lwip_get_socket_info_by_fd get sock %d info by pcb fail , unsupport type "); +295936,606576640,0,0,PLAT_AP,LWIP_API,lwip_selscan_1,P_INFO,swLogPrintf("lwip_selscan : fd = %d ready for reading "); +295936,606578688,0,0,PLAT_AP,LWIP_API,lwip_selscan_2,P_INFO,swLogPrintf("lwip_selscan : fd = %d ready for writing "); +295936,606580736,0,0,PLAT_AP,LWIP_API,lwip_selscan_3,P_INFO,swLogPrintf("lwip_selscan : fd = %d ready for exception "); +295936,606584831,0,0,PLAT_AP,LWIP_API,lwip_selscan_4,P_ERROR,swLogPrintf("nready > = 0 "); +295936,606586112,0,0,PLAT_AP,LWIP_API,lwip_select_1,P_INFO,swLogPrintf("lwip_select ( %d , 0x%x , 0x%x , 0x%x , tvsec = %u tvusec = %u ) "); +295936,606588927,0,0,PLAT_AP,LWIP_API,lwip_select_2,P_WARNING,swLogPrintf("lwip_select : no timeout , returning 0 "); +295936,606590975,0,0,PLAT_AP,LWIP_API,lwip_select_9,P_ERROR,swLogPrintf("lwip_select : new sys semphore fail "); +295936,606593023,0,0,PLAT_AP,LWIP_API,lwip_select_3,P_ERROR,swLogPrintf("lwip_select : sock->select_waiting > 0 "); +295936,606595071,0,0,PLAT_AP,LWIP_API,lwip_select_4,P_ERROR,swLogPrintf("lwip_select : sock->select_waiting > 0 2 "); +295936,606597119,0,0,PLAT_AP,LWIP_API,lwip_select_5,P_ERROR,swLogPrintf("lwip_select : select_cb.prev = = NULL "); +295936,606599167,0,0,PLAT_AP,LWIP_API,lwip_select_6,P_ERROR,swLogPrintf("lwip_select : select_cb.prev ! = NULL "); +295936,606601215,0,0,PLAT_AP,LWIP_API,lwip_select_7,P_INFO,swLogPrintf("lwip_select : timeout expired "); +295936,606601216,0,0,PLAT_AP,LWIP_API,lwip_select_8,P_INFO,swLogPrintf("lwip_select : nready = %d "); +295936,606605311,0,0,PLAT_AP,LWIP_API,event_callback_1,P_WARNING,swLogPrintf("event_callback unknown event "); +295936,606605568,0,0,PLAT_AP,LWIP_API,lwip_shutdown_1,P_INFO,swLogPrintf("lwip_shutdown ( %d , how = %d ) "); +295936,606607616,0,0,PLAT_AP,LWIP_API,lwip_getaddrname_1,P_INFO,swLogPrintf("lwip_getaddrname ( %d , port = %u ) "); +295936,606611455,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_1,P_ERROR,swLogPrintf("lwip_getsockopt : new sys semphore fail "); +295936,606613503,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_callback_1,P_ERROR,swLogPrintf("lwip_getsockopt_callback arg ! = NULL "); +295936,606613760,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_1,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , SOL_SOCKET , optname = 0x%x , .. ) "); +295936,606615808,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_2,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , SOL_SOCKET , SO_TYPE ) : unrecognized socket type %d "); +295936,606617856,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_3,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , SOL_SOCKET , SO_TYPE ) = %d "); +295936,606619904,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_4,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , SOL_SOCKET , SO_ERROR ) = %d "); +295936,606621952,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_5,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , SOL_SOCKET , UNIMPL : optname = 0x%x , .. ) "); +295936,606624000,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_6,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_IP , IP_TTL ) = %d "); +295936,606626048,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_7,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_IP , IP_TOS ) = %d "); +295936,606628096,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_11,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_IP , UNIMPL : optname = 0x%x , .. ) "); +295936,606629888,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_12,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_TCP , TCP_NODELAY ) "); +295936,606632192,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_13,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPALIVE ) = %d "); +295936,606634240,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_14,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPIDLE ) = %d "); +295936,606636288,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_15,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPINTVL ) = %d "); +295936,606638336,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_16,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPCNT ) = %d "); +295936,606640384,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_17,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_TCP , UNIMPL : optname = 0x%x , .. ) "); +295936,606642432,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_18,P_INFO,swLogPrintf("lwip_getsockopt_impl lwip_getsockopt ( %d , IPPROTO_IPV6 , IPV6_V6ONLY ) = %d "); +295936,606644480,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_19,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_IPV6 , UNIMPL : optname = 0x%x , .. ) "); +295936,606646528,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_23,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_RAW , IPV6_CHECKSUM ) = %d "); +295936,606648576,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_24,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , IPPROTO_RAW , UNIMPL : optname = 0x%x , .. ) "); +295936,606650880,0,0,PLAT_AP,LWIP_API,lwip_getsockopt_impl_25,P_INFO,swLogPrintf("lwip_getsockopt_impl ( %d , level = 0x%x , UNIMPL : optname = 0x%x , .. ) "); +295936,606654463,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_1,P_ERROR,swLogPrintf("lwip_setsockopt : new sys semphore fail "); +295936,606656511,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_callback_1,P_ERROR,swLogPrintf("lwip_setsockopt_callback arg = = NULL "); +295936,606656768,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_1,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , SOL_SOCKET , optname = 0x%x , .. ) "); +295936,606658560,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_keepalive,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , SOL_SOCKET , KEEPALIVE , .. ) "); +295936,606662655,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_20,P_WARNING,swLogPrintf("tcp hib / sleep2 mode connection number limited "); +295936,606664703,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_info_1,P_INFO,swLogPrintf("tcp hib / sleep2 mode connection , tcp hib pcb not connectted "); +295936,606666751,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_warning_1,P_WARNING,swLogPrintf("tcp hib / sleep2 mode connection , tcp hib pcb has exist "); +295936,606668799,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_warning_2,P_WARNING,swLogPrintf("tcp hib / sleep2 mode connection , tcp pcb is invalid "); +295936,606670847,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_21,P_INFO,swLogPrintf("tcp hib / sleep2 mode connection enable "); +295936,606672895,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_22,P_INFO,swLogPrintf("tcp hib / sleep2 mode connection disable "); +295936,606674943,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_23,P_WARNING,swLogPrintf("udp hib / sleep2 mode connection number limited "); +295936,606676991,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_info_2,P_INFO,swLogPrintf("udp hib / sleep2 mode connection , udp hib pcb not bind or connect "); +295936,606679039,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_warning_3,P_WARNING,swLogPrintf("udp hib / sleep2 mode connection , udp hib pcb has exist "); +295936,606681087,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_warning_4,P_WARNING,swLogPrintf("udp hib / sleep2 mode connection , udp pcb is invalid "); +295936,606683135,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_24,P_INFO,swLogPrintf("udp hib / sleep2 mode connection enable "); +295936,606685183,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_25,P_INFO,swLogPrintf("udp hib / sleep2 mode connection disable "); +295936,606687231,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_26,P_INFO,swLogPrintf("set the pcb as squence state handler pcb "); +295936,606689279,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_27,P_WARNING,swLogPrintf("the UL sequence handler socket has set , can not set again "); +295936,606691327,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_28,P_WARNING,swLogPrintf("the udp pcb is invalid "); +295936,606693375,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_29,P_INFO,swLogPrintf("the socket is not UDP socket , can not handle socket sequence state "); +295936,606695423,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_30,P_INFO,swLogPrintf("set squence state handler pcb as NULL "); +295936,606695424,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_init_retry_time_1,P_WARNING,swLogPrintf("tcp_init_retry_time %u fail "); +295936,606699519,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_init_retry_time_2,P_WARNING,swLogPrintf("the tcp pcb is invalid "); +295936,606701567,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_init_retry_time_3,P_ERROR,swLogPrintf("the socket is not TCP socket , can not set tcp init retry time "); +295936,606703615,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_init_retry_time_4,P_ERROR,swLogPrintf("invalid tcp max retry time "); +295936,606703616,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_31,P_WARNING,swLogPrintf("tcp_set_max_retry_times %u fail "); +295936,606707711,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_32,P_WARNING,swLogPrintf("the tcp pcb is invalid "); +295936,606709759,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_33,P_ERROR,swLogPrintf("the socket is not TCP socket , can not set tcp max retry times "); +295936,606711807,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_34,P_ERROR,swLogPrintf("invalid tcp max retry times "); +295936,606711808,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_35,P_WARNING,swLogPrintf("tcp_set_max_total_retry_time %u fail "); +295936,606715903,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_36,P_WARNING,swLogPrintf("the tcp pcb is invalid "); +295936,606717951,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_37,P_ERROR,swLogPrintf("the socket is not TCP socket , can not set tcp max total retry time "); +295936,606719999,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_38,P_ERROR,swLogPrintf("invalid max total retry time "); +295936,606722047,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_tcp_close_local_abort_1,P_WARNING,swLogPrintf("the tcp pcb is invalid "); +295936,606724095,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_tcp_close_local_abort_2,P_ERROR,swLogPrintf("the socket is not TCP socket , can not enable the option "); +295936,606726143,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_tcp_need_report_ul_status_1,P_WARNING,swLogPrintf("the tcp pcb is invalid "); +295936,606728191,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_tcp_need_report_ul_status_2,P_ERROR,swLogPrintf("the socket is not TCP socket , can not enable the option "); +295936,606728448,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_2,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , SOL_SOCKET , UNIMPL : optname = 0x%x , .. ) "); +295936,606730496,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_3,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_IP , IP_TTL , .. ) -> %d "); +295936,606732544,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_4,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_IP , IP_TOS , .. ) -> %d "); +295936,606734592,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_5,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_IP , UNIMPL : optname = 0x%x , .. ) "); +295936,606736384,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_6,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_TCP , TCP_NODELAY ) "); +295936,606738688,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_7,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPALIVE ) -> %u "); +295936,606740736,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_8,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPIDLE ) -> %u "); +295936,606742784,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_9,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPINTVL ) -> %u "); +295936,606744832,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_10,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_TCP , TCP_KEEPCNT ) -> %u "); +295936,606746880,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_11,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_TCP , UNIMPL : optname = 0x%x , .. ) "); +295936,606748928,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_12,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_IPV6 , IPV6_V6ONLY , .. ) -> %d "); +295936,606750976,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_13,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_IPV6 , UNIMPL : optname = 0x%x , .. ) "); +295936,606753024,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_17,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_RAW , IPV6_CHECKSUM , .. ) -> %d "); +295936,606755072,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_18,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , IPPROTO_RAW , UNIMPL : optname = 0x%x , .. ) "); +295936,606757376,0,0,PLAT_AP,LWIP_API,lwip_setsockopt_impl_19,P_INFO,swLogPrintf("lwip_setsockopt_impl ( %d , level = 0x%x , UNIMPL : optname = 0x%x , .. ) "); +295936,606759424,0,0,PLAT_AP,LWIP_API,lwip_ioctl_1,P_INFO,swLogPrintf("lwip_ioctl ( %d , FIONREAD , 0x%x ) = %u "); +295936,606761216,0,0,PLAT_AP,LWIP_API,lwip_ioctl_2,P_INFO,swLogPrintf("lwip_ioctl ( %d , FIONBIO , %d ) "); +295936,606763264,0,0,PLAT_AP,LWIP_API,lwip_ioctl_3,P_INFO,swLogPrintf("lwip_ioctl ( %d , FIOHWODR , %d ) "); +295936,606765568,0,0,PLAT_AP,LWIP_API,lwip_ioctl_4,P_INFO,swLogPrintf("lwip_ioctl ( %d , UNIMPL : 0x%x , 0x%x ) "); +295936,606767616,0,0,PLAT_AP,LWIP_API,lwip_fcntl_1,P_INFO,swLogPrintf("lwip_fcntl ( %d , UNIMPL : %d , %d ) ) "); +295936,606771199,0,0,PLAT_AP,LWIP_API,tcpip_thread_1,P_WARNING,swLogPrintf("tcpip_thread : invalid message : NULL "); +295936,606771200,0,0,PLAT_AP,LWIP_API,tcpip_thread_2,P_INFO,swLogPrintf("tcpip_thread : API message 0x%x "); +295936,606773248,0,0,PLAT_AP,LWIP_API,tcpip_thread_3,P_INFO,swLogPrintf("tcpip_thread : API CALL message 0x%x "); +295936,606775296,0,0,PLAT_AP,LWIP_API,tcpip_thread_5,P_INFO,swLogPrintf("tcpip_thread : PS PACKET 0x%x "); +295936,606777344,0,0,PLAT_AP,LWIP_API,tcpip_thread_pending_input,P_INFO,swLogPrintf("tcpip_thread : PS PACKET 0x%x "); +295936,606779392,0,0,PLAT_AP,LWIP_API,tcpip_thread_11,P_INFO,swLogPrintf("tcpip_thread : LAN PACKET 0x%x "); +295936,606781440,0,0,PLAT_AP,LWIP_API,tcpip_thread_6,P_INFO,swLogPrintf("tcpip_thread : TIMEOUT 0x%x "); +295936,606783488,0,0,PLAT_AP,LWIP_API,tcpip_thread_7,P_INFO,swLogPrintf("tcpip_thread : UNTIMEOUT 0x%x "); +295936,606785536,0,0,PLAT_AP,LWIP_API,tcpip_thread_8,P_INFO,swLogPrintf("tcpip_thread : CALLBACK 0x%x "); +295936,606787584,0,0,PLAT_AP,LWIP_API,tcpip_thread_9,P_INFO,swLogPrintf("tcpip_thread : CALLBACK_STATIC 0x%x "); +295936,606789632,0,0,PLAT_AP,LWIP_API,tcpip_thread_10,P_WARNING,swLogPrintf("tcpip_thread : invalid message %d "); +295936,606793727,0,0,PLAT_AP,LWIP_API,tcpip_inpkt_2,P_ERROR,swLogPrintf("tcpip_inpkt : Invalid mbox "); +295936,606793984,0,0,PLAT_AP,LWIP_API,TcpipPsInpkt_2,P_INFO,swLogPrintf("TcpipPsInpkt2 : %u / 0x%x "); +295936,606797823,0,0,PLAT_AP,LWIP_API,TcpipPsInpkt_3,P_ERROR,swLogPrintf("TcpipPsInpkt : Invalid mbox "); +295936,606797824,0,0,PLAT_AP,LWIP_API,TcpipPsPendingInpkt_2,P_INFO,swLogPrintf("TcpipPsPendingInpkt : %u "); +295936,606801919,0,0,PLAT_AP,LWIP_API,TcpipPsPendingInpkt_3,P_ERROR,swLogPrintf("TcpipPsPendingInpkt : Invalid mbox "); +295936,606802176,0,0,PLAT_AP,LWIP_API,TcpipLanInpkt_2,P_INFO,swLogPrintf("TcpipLanInpkt : %u / 0x%x "); +295936,606806015,0,0,PLAT_AP,LWIP_API,TcpipLanInpkt_3,P_ERROR,swLogPrintf("TcpipLanInpkt : Invalid mbox "); +295936,606808063,0,0,PLAT_AP,LWIP_API,tcpip_callback_with_block_1,P_ERROR,swLogPrintf("tcpip_callback_with_block : Invalid mbox "); +295936,606810111,0,0,PLAT_AP,LWIP_API,tcpip_timeout_1,P_ERROR,swLogPrintf("tcpip_timeout : Invalid mbox "); +295936,606812159,0,0,PLAT_AP,LWIP_API,tcpip_untimeout_1,P_ERROR,swLogPrintf("tcpip_untimeout : Invalid mbox "); +295936,606814207,0,0,PLAT_AP,LWIP_API,tcpip_send_msg_wait_sem_1,P_ERROR,swLogPrintf("tcpip_send_msg_wait_sem : Invalid mbox or semaphore not initialized "); +295936,606816255,0,0,PLAT_AP,LWIP_API,tcpip_api_call_1,P_ERROR,swLogPrintf("tcpip_api_call : Invalid mbox "); +295936,606818303,0,0,PLAT_AP,LWIP_API,tcpip_trycallback_1,P_ERROR,swLogPrintf("tcpip_trycallback : Invalid mbox "); +295936,606820351,0,0,PLAT_AP,LWIP_API,tcpip_init_1,P_ERROR,swLogPrintf("tcpip_init : failed to create tcpip_thread mbox "); +296960,608178175,0,0,PLAT_AP,MAC,CatMacUlBeCancelZeroBSR_highwater_1,P_WARNING,swLogPrintf("CAT MAC UL , UL highwater , cancel BSR 0 "); +296960,608180223,0,0,PLAT_AP,LWIP_OTHER,free_etharp_q_1,P_ERROR,swLogPrintf("free_etharp_q point is invalid "); +296960,608182271,0,0,PLAT_AP,LWIP_OTHER,free_etharp_q_2,P_ERROR,swLogPrintf("free_etharp_q point is invalid "); +296960,608182528,0,0,PLAT_AP,LWIP_OTHER,etharp_free_entry_1,P_INFO,swLogPrintf("etharp_free_entry : freeing entry %u , packet queue 0x%x "); +296960,608184320,0,0,PLAT_AP,LWIP_OTHER,etharp_free_entry_disable_retry_timer_1,P_INFO,swLogPrintf("etharp_free_entry : disable retry timer entry %u "); +296960,608186368,0,0,PLAT_AP,LWIP_OTHER,etharp_free_entry_disable_cahce_timer_1,P_INFO,swLogPrintf("etharp_free_entry : disable cache timer entry %u "); +296960,608190463,0,0,PLAT_AP,LWIP_OTHER,etharp_free_table_1,P_ERROR,swLogPrintf("etharp_free_entry : invalid table point "); +296960,608190464,0,0,PLAT_AP,LWIP_OTHER,etharp_free_table_2,P_INFO,swLogPrintf("etharp_free_entry : freeing entr , packet queue 0x%x "); +296960,608194559,0,0,PLAT_AP,LWIP_OTHER,arp_enable_timer_active_mask_1,P_ERROR,swLogPrintf("invalid argument "); +296960,608196607,0,0,PLAT_AP,LWIP_OTHER,arp_disable_timer_active_mask_1,P_ERROR,swLogPrintf("invalid argument "); +296960,608198655,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_cache_timer_1,P_INFO,swLogPrintf("tcpip_arp_cache_timer timeout "); +296960,608200703,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_cache_timer_2,P_ERROR,swLogPrintf("tcpip_arp_cache_timer arg invliad "); +296960,608202751,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_retry_timer_1,P_INFO,swLogPrintf("tcpip_arp_retry_timer tiemout "); +296960,608204799,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_retry_timer_2,P_ERROR,swLogPrintf("tcpip_arp_retry_timer arg invliad "); +296960,608204800,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_retry_timer_3,P_WARNING,swLogPrintf("tcpip_arp_retry_timer start retry timer %u "); +296960,608206848,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_retry_timer_4,P_WARNING,swLogPrintf("tcpip_arp_retry_timer invliad state %u "); +296960,608210943,0,0,PLAT_AP,LWIP_OTHER,tcpip_arp_retry_timer_5,P_INFO,swLogPrintf("tcpip_arp_retry_timer reach max retry times "); +296960,608210944,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_1,P_INFO,swLogPrintf("etharp_find_entry : found empty entry %u "); +296960,608212992,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_2,P_VALUE,swLogPrintf("state %u "); +296960,608215040,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_3,P_INFO,swLogPrintf("etharp_find_entry : found matching entry %u "); +296960,608219135,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_4,P_INFO,swLogPrintf("etharp_find_entry : no empty entry found and not allowed to recycle "); +296960,608219136,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_5,P_INFO,swLogPrintf("etharp_find_entry : selecting empty entry %u "); +296960,608221184,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_6,P_INFO,swLogPrintf("etharp_find_entry : selecting oldest entry %u "); +296960,608225279,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_7,P_ERROR,swLogPrintf("arp_table [ i ] .q ! = NULL "); +296960,608225280,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_8,P_INFO,swLogPrintf("etharp_find_entry : selecting oldest pending entry %u "); +296960,608227584,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_9,P_INFO,swLogPrintf("etharp_find_entry : selecting oldest pending entry %u , freeing packet queue 0x%x "); +296960,608231423,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_10,P_INFO,swLogPrintf("etharp_find_entry : no empty or recyclable entries found "); +296960,608233471,0,0,PLAT_AP,LWIP_OTHER,etharp_find_entry_11,P_ERROR,swLogPrintf("i > = ARP_TABLE_SIZE "); +296960,608235519,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_entry_1,P_ERROR,swLogPrintf("netif->hwaddr_len = = ETH_HWADDR_LEN "); +296960,608236288,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_entry_2_sub_1,P_INFO,swLogPrintf("etharp_update_arp_entry : ip %u.%u.%u.%u "); +296960,608238848,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_entry_2_sub_2,P_INFO,swLogPrintf("etharp_update_arp_entry : mac %u : %u : %u : %u : %u : %u "); +296960,608241663,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_entry_3,P_ERROR,swLogPrintf("etharp_update_arp_entry : will not add non-unicast IP address to ARP cache "); +296960,608241664,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_entry_4,P_INFO,swLogPrintf("etharp_update_arp_entry : updating stable entry %u "); +296960,608243712,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_disable_retry_timer_1,P_INFO,swLogPrintf("etharp_update_arp_entry : disable retry timer entry %u "); +296960,608245760,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_disable_cahce_timer_1,P_INFO,swLogPrintf("etharp_update_arp_entry : disable old cache timer entry %u "); +296960,608247808,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_enable_cahce_timer_1,P_INFO,swLogPrintf("etharp_update_arp_entry : disable old cache timer entry %u "); +296960,608249856,0,0,PLAT_AP,LWIP_OTHER,etharp_update_arp_disable_retry_timer_static,P_INFO,swLogPrintf("etharp_update_arp_entry : static arp entry %u "); +296960,608252672,0,0,PLAT_AP,LWIP_OTHER,etharp_add_static_entry_11,P_INFO,swLogPrintf("etharp_add_static_entry : %u.%u.%u.%u "); +296960,608255232,0,0,PLAT_AP,LWIP_OTHER,etharp_add_static_entry_12,P_INFO,swLogPrintf("etharp_add_static_entry : %u : %u : %u : %u : %u : %u "); +296960,608256768,0,0,PLAT_AP,LWIP_OTHER,etharp_remove_static_entry_1,P_INFO,swLogPrintf("etharp_remove_static_entry : %u.%u.%u.%u "); +296960,608260095,0,0,PLAT_AP,LWIP_OTHER,etharp_find_addr_1,P_ERROR,swLogPrintf("eth_ret = = NULL || ip_ret = = NULL "); +296960,608262143,0,0,PLAT_AP,LWIP_OTHER,etharp_get_entry_1,P_ERROR,swLogPrintf("ipaddr = = NULL || ipaddr = = NULL || eth_ret = = NUL "); +296960,608264191,0,0,PLAT_AP,LWIP_OTHER,etharp_input_1,P_ERROR,swLogPrintf("netif = = NULL "); +296960,608264704,0,0,PLAT_AP,LWIP_OTHER,etharp_input_2,P_INFO,swLogPrintf("etharp_input : packet dropped , wrong hw type , hwlen , proto , protolen or ethernet type ( %u ^u %u %u ) "); +296960,608268287,0,0,PLAT_AP,LWIP_OTHER,etharp_input_3,P_INFO,swLogPrintf("etharp_input : incoming ARP request "); +296960,608270335,0,0,PLAT_AP,LWIP_OTHER,etharp_input_4,P_INFO,swLogPrintf("etharp_input : we are unconfigured , ARP request ignored "); +296960,608272383,0,0,PLAT_AP,LWIP_OTHER,etharp_input_5,P_INFO,swLogPrintf("etharp_input : ARP request was not for us "); +296960,608274431,0,0,PLAT_AP,LWIP_OTHER,etharp_input_6,P_INFO,swLogPrintf("etharp_input : incoming ARP reply "); +296960,608274432,0,0,PLAT_AP,LWIP_OTHER,etharp_input_7,P_INFO,swLogPrintf("etharp_input : ARP unknown opcode type %u "); +296960,608278527,0,0,PLAT_AP,LWIP_OTHER,etharp_output_to_arp_index_1,P_ERROR,swLogPrintf("arp_table [ arp_idx ] .state < ETHARP_STATE_STABLE "); +296960,608278528,0,0,PLAT_AP,LWIP_OTHER,etharp_output_to_arp_index_enable_retry_timer_1,P_INFO,swLogPrintf("etharp_output_to_arp_index : enable retry timer entry %u "); +296960,608280576,0,0,PLAT_AP,LWIP_OTHER,etharp_output_to_arp_index_enable_retry_timer_2,P_INFO,swLogPrintf("etharp_output_to_arp_index : enable retry timer entry %u "); +296960,608284671,0,0,PLAT_AP,LWIP_OTHER,etharp_output_1,P_ERROR,swLogPrintf("netif = = NULL || q = = NULL || ipaddr = = NULL "); +296960,608286719,0,0,PLAT_AP,LWIP_OTHER,etharp_query_1,P_ERROR,swLogPrintf("etharp_query : will not add non-unicast IP address to ARP cache "); +296960,608288767,0,0,PLAT_AP,LWIP_OTHER,etharp_query_2,P_INFO,swLogPrintf("etharp_query : could not create ARP entry "); +296960,608290815,0,0,PLAT_AP,LWIP_OTHER,etharp_query_3,P_INFO,swLogPrintf("etharp_query : packet dropped "); +296960,608292863,0,0,PLAT_AP,LWIP_OTHER,etharp_query_4,P_ERROR,swLogPrintf("( arp_table [ i ] .state ! = ETHARP_STATE_PENDING ) && ( arp_table [ i ] .state < ETHARP_STATE_STABLE ) L "); +296960,608294911,0,0,PLAT_AP,LWIP_OTHER,etharp_query_5,P_ERROR,swLogPrintf("q = = NULL "); +296960,608296959,0,0,PLAT_AP,LWIP_OTHER,etharp_query_6,P_ERROR,swLogPrintf("no packet queues allowed "); +296960,608297216,0,0,PLAT_AP,LWIP_OTHER,etharp_query_7,P_INFO,swLogPrintf("etharp_query : queued packet 0x%x on ARP entry %u "); +296960,608299008,0,0,PLAT_AP,LWIP_OTHER,etharp_query_8,P_INFO,swLogPrintf("etharp_query : could not queue a copy of PBUF_REF packet 0x%x ( out of memory ) "); +296960,608301312,0,0,PLAT_AP,LWIP_OTHER,etharp_query_10,P_INFO,swLogPrintf("etharp_query : dropped previously queued packe 0x%x for ARP entry %u "); +296960,608305151,0,0,PLAT_AP,LWIP_OTHER,etharp_raw_1,P_ERROR,swLogPrintf("netif = = NULL "); +296960,608307199,0,0,PLAT_AP,LWIP_OTHER,etharp_raw_2,P_ERROR,swLogPrintf("etharp_raw : could not allocate pbuf for ARP request "); +296960,608309247,0,0,PLAT_AP,LWIP_OTHER,etharp_raw_3,P_ERROR,swLogPrintf("check that first pbuf can hold struct etharp_hdr "); +296960,608311295,0,0,PLAT_AP,LWIP_OTHER,etharp_raw_4,P_INFO,swLogPrintf("etharp_raw : sending raw ARP packet "); +296960,608313343,0,0,PLAT_AP,LWIP_OTHER,etharp_raw_5,P_ERROR,swLogPrintf("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp "); +296960,608315391,0,0,PLAT_AP,LWIP_OTHER,etharp_request_1,P_VALUE,swLogPrintf("etharp_request : sending ARP request "); +296960,608316672,0,0,PLAT_AP,LWIP_OTHER,ethernet_input_1_sub_1,P_INFO,swLogPrintf("ethernet_input : dest : %u : %u : %u : %u : %u : %u "); +296960,608318976,0,0,PLAT_AP,LWIP_OTHER,ethernet_input_1_sub_2,P_INFO,swLogPrintf("ethernet_input : src : %u : %u : %u : %u : %u : %u , type %u "); +296960,608319744,0,0,PLAT_AP,LWIP_OTHER,ethernet_input_2,P_INFO,swLogPrintf("ethernet_input : IPv4 packet dropped , too short ( %u %u ) "); +296960,608321792,0,0,PLAT_AP,LWIP_OTHER,ethernet_input_3,P_INFO,swLogPrintf("ethernet_input : ARP response packet dropped , too short ( %u %u ) "); +296960,608323840,0,0,PLAT_AP,LWIP_OTHER,ethernet_input_4,P_INFO,swLogPrintf("ethernet_input : IPv6 packet dropped , too short ( %u %u ) "); +296960,608327679,0,0,PLAT_AP,LWIP_OTHER,ethernet_output_2,P_ERROR,swLogPrintf("netif->hwaddr_len must be 6 for ethernet_output "); +296960,608327680,0,0,PLAT_AP,LWIP_OTHER,ethernet_output_3,P_INFO,swLogPrintf("ethernet_output : sending packet 0x%x "); +296960,608331775,0,0,PLAT_AP,LWIP_OTHER,ethernet_output_4,P_ERROR,swLogPrintf("ethernet_output : could not allocate room for header "); +297984,610273536,0,0,PLAT_AP,RLC,CatRlcAmDecodeDlSnPdu_hw_3,P_WARNING,swLogPrintf("AM DL , L2 DL BM highwater , could only RECV / ACCEPT VRR : %d PDU , discard this SN : %d "); +297984,610275584,0,0,PLAT_AP,RLC,CatRlcAmReEstAssemblePdcpPduFromRlcPdu_1,P_INFO,swLogPrintf("Re-Est AM DL , Cur SN : %d , segNum : 1 , fi : %d ( FNF ) , this PDCP PDU missing the front half , can ' t assemble it , discard this RLC PDU! "); +297984,610277888,0,0,PLAT_AP,RLC,CatRlcAmReEstAssemblePdcpPduFromRlcPdu_2,P_INFO,swLogPrintf("Re-Est AM DL , Cur SN : %d , segNum : %d , fi : %d ( FNF ) , the first PDCP seg missing the front half , can ' t assemble it , skip and continue to assemble other seg! "); +297984,610279424,0,0,PLAT_AP,RLC,CatRlcAmAssembleLcDlSdu_1,P_INFO,swLogPrintf("RLC AM LC : %d , don ' t has valid PDCP PDU , maybe only RLC STATUS report , or RLC PDU has been discarded. "); +297984,610281984,0,0,PLAT_AP,RLC,CatRlcAmDlLcReestablishReq_1,P_INFO,swLogPrintf("Re-Est RLC AM DL , LC : %d , vrr : %d , miss SN : %d , SN is not continuous , discard BackUp PDU! "); +297984,610283776,0,0,PLAT_AP,RLC,CatRlcUmAssemblePdcpPduFromWholeRlcPdu_1,P_INFO,swLogPrintf("UM DL , Cur SN : %d , segNum : 1 , fi : %d ( FNF ) , this PDCP PDU missing the front half , can ' t assemble it , discard this RLC PDU! "); +297984,610286080,0,0,PLAT_AP,RLC,CatRlcUmAssemblePdcpPduFromWholeRlcPdu_2,P_INFO,swLogPrintf("UM DL , Cur SN : %d , segNum : %d , fi : %d ( FNF ) , the first PDCP seg missing the front half , can ' t assemble it , skip and continue to assemble other seg! "); +297984,610287616,0,0,PLAT_AP,RLC,CatRlcUmAssembleLcDlSdu_1,P_INFO,swLogPrintf("RLC UM DL , LC : %d , don ' t has valid PDCP PDU , maybe RLC PDU has been discarded. "); +297984,610290432,0,0,PLAT_AP,RLC,CatRlcUmAssembleLcDlSdu_2,P_INFO,swLogPrintf("RLC UM DL , LC : %d , vrur : %d , fall out of reordering window : [ %d ~ %d ) , update vrur "); +297984,610292224,0,0,PLAT_AP,RLC,CatRlcUmAssembleLcDlSdu_3,P_INFO,swLogPrintf("RLC UM DL , LC : %d , vrur : %d , miss SN : %d , skip this PDU! "); +297984,610293760,0,0,PLAT_AP,RLC,CatRlcUmAssembleLcDlSdu_4,P_INFO,swLogPrintf("RLC UM DL , LC : %d , the backup PDU missing the second half , can ' t assemble it , discard the backup PDU! "); +297984,610296320,0,0,PLAT_AP,RLC,CatRlcUmDlLcReestablishReq_1,P_INFO,swLogPrintf("RLC UM DL , LC : %d , vrur : %d , miss SN : %d , skip this PDU! "); +297984,610297856,0,0,PLAT_AP,RLC,CatRlcUmDlLcReestablishReq_2,P_INFO,swLogPrintf("RLC UM DL , LC : %d , the backup PDU missing the second half , can ' t assemble it , discard the backup PDU! "); +297984,610300416,0,0,PLAT_AP,RLC,CatRlcUmTReorderingTimerExpiry_2,P_INFO,swLogPrintf("UM DL , LC : %d , vrur : %d , miss SN : %d , skip this PDU! "); +297984,610301952,0,0,PLAT_AP,RLC,CatRlcUmTReorderingTimerExpiry_3,P_INFO,swLogPrintf("RLC UM DL , LC : %d , the backup PDU missing the second half , can ' t assemble it , discard the backup PDU! "); +299008,612370944,0,0,PLAT_AP,PDCP,CatPdcpDlDecodeOneStatusReportPdu_fms_1,P_VALUE,swLogPrintf("PDCP DL , LCID : %d , recv status report , fmsCount : 0x%x , nextTxCount : 0x%x "); +299008,612372480,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrProcCeregCnf_1,P_WARNING,swLogPrintf("NM , PS not REG : %d , but not try to search / register to NW "); +299008,612374784,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrProcCeregCnf_2,P_WARNING,swLogPrintf("NM , PS not REG : %d , actCidsBitmap : 0x%x "); +299008,612376576,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrProcCeregInd_1,P_WARNING,swLogPrintf("NM , PS not REG : %d , but not try to search / register to NW "); +299008,612378624,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrGetNetInfoCallback_1,P_SIG,swLogPrintf("NET MGR , NM get net info , state : %u "); +299008,612380928,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_1,P_SIG,swLogPrintf("Net manager link up : CID %d , bind to another CID %d "); +299008,612382976,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_2,P_WARNING,swLogPrintf("Net manager link up fail , invalid ip type : %d , %d "); +299008,612386815,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_3,P_WARNING,swLogPrintf("NM , Test SIM and IPV6 RS is not enabled for TEST SIM , not EST this IPV6 IF "); +299008,612387840,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_4,P_SIG,swLogPrintf("Net manager , link up , CID : %d , IPV4 : %u.%u.%u.%u "); +299008,612390911,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_5,P_SIG,swLogDump("Net manager , link up , full IPV6 addr : "); +299008,612392959,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_ipv6_id_4,P_WARNING,swLogPrintf("NM , Test SIM and IPV6 RS is not enabled for TEST SIM , ignore this IPV6 IF "); +299008,612392960,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_ipv6GetPrefixelay,P_INFO,swLogPrintf("NM , ipv6 get prefix delay %u "); +299008,612397055,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_6,P_SIG,swLogDump("Net manager , link up , IPV6 ID addr : "); +299008,612397824,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkUp_7,P_SIG,swLogPrintf("Net manager , link up , IPV4 PCO DNS : %u.%u.%u.%u "); +299008,612399360,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrDedLinkUp_1,P_SIG,swLogPrintf("NETMANAGER , dedicated BR link up , cid : %d , pcid : %d "); +299008,612401152,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLinkDown_1,P_SIG,swLogPrintf("NETMANAGER link down : cid %d "); +299008,612403200,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLanLinkUp_1,P_SIG,swLogPrintf("NETMANAGER LAN link up : type %u "); +299008,612405248,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLanLinkDown_1,P_SIG,swLogPrintf("NETMANAGER LAN link down : type %u "); +299008,612407552,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLanLinkLayerStatusChange_1,P_SIG,swLogPrintf("NETMANAGER LAN link layer status change : type %u , new status %u "); +299008,612409344,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLanConfig_1,P_SIG,swLogPrintf("NETMANAGER LAN config , ether mode %u "); +299008,612412160,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrLanCtrl_1,P_SIG,swLogPrintf("NETMANAGER LAN control , action %u , type %u , ip4Cid %u , ip6Cid %u "); +299008,612413440,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrQueryLanTcpipDataPathCapability_1,P_INFO,swLogPrintf("NET MGR , lan data path cap type : %u "); +299008,612415488,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrGetLanTcpipDataPathStatus_1,P_INFO,swLogPrintf("NET MGR , lan data path status type : %u "); +299008,612417536,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrGetLanTcpipDataPathHostInfo_1,P_INFO,swLogPrintf("NET MGR , lan data path host info type : %u "); +299008,612419584,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrGetNetInfo_1,P_INFO,swLogPrintf("NET MGR , get ATI netif info , cid : %u "); +299008,612421632,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrGetNetInfoWithoutPsStatusCheck_1,P_INFO,swLogPrintf("NET MGR , get ATI netif info without PS check , cid : %u "); +299008,612423680,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrGetDnsServerInfo_1,P_INFO,swLogPrintf("NETMANAGER get DNS server info : cid %u "); +299008,612425728,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrClearDnsCacheInfo_1,P_INFO,swLogPrintf("NETMANAGER clear DNS cache info : clear all flag %u "); +299008,612427776,0,0,PLAT_AP,TCPIP_NETMGR,NetMgrSetDnsCache_1,P_INFO,swLogPrintf("NETMANAGER Set DNS cache config %u "); +299008,612430592,0,0,PLAT_AP,TCPIP_NETMGR,psDailSetAdptDnsServerInfo_1,P_INFO,swLogPrintf("psdial , NW not config DNS , use default IPv4 DNS ADDR : %u.%u.%u.%u "); +299008,612433919,0,0,PLAT_AP,TCPIP_NETMGR,psDailSetAdptDnsServerInfo_3,P_INFO,swLogPrintf("psdial load ipv4 IMSI DNS "); +299008,612435967,0,0,PLAT_AP,TCPIP_NETMGR,psDailSetAdptDnsServerInfo_4,P_INFO,swLogPrintf("psdial load ipv6 IMSI DNS "); +299008,612435968,0,0,PLAT_AP,TCPIP_NETMGR,psDailSetAdptDnsServerInfo_5,P_WARNING,swLogPrintf("PS DAIL , Get adpt DNS server address failed , bWakeUp %u "); +300032,614467840,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_dest_1,P_WARNING,swLogPrintf("NET DL fast path , one IP DL dest : 0x%lx , not for UE : 0x%lx , discard "); +300032,614469888,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_dest_2,P_WARNING,swLogPrintf("NET DL fast path , one IP DL dest : 0x%lx , not for UE : 0x%lx "); +300032,614471936,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_arpCache_1,P_WARNING,swLogPrintf("NET DL fast path , IPV4 host ARP cache not done , host ARP addr : 0x%lx , host addr : 0x%lx , pkg foward to LWIP "); +300032,614473728,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_frag_1,P_WARNING,swLogPrintf("NET DL fast path , one IP is fragment : 0x%lx , pass to LWIP "); +300032,614476032,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_mtu_1,P_WARNING,swLogPrintf("NET DL fast path , pkg length : %d > LAN MTU : %d , need IP fragment "); +300032,614477824,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_ip_proto_1,P_INFO,swLogPrintf("NET DL fast path , IP protocol is not UDP / TCP : %d , pass to LWIP "); +300032,614480128,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_udp_len_1,P_ERROR,swLogPrintf("NET DL fast path , pkg length : %d < = ( ipHdrLen : %d + udpHdrLen : 8 ) , discard "); +300032,614482176,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_tcp_len_1,P_ERROR,swLogPrintf("NET DL fast path , pkg length : %d < = ( ipHdrLen : %d + tcpHdrLen : 20 ) , discard "); +300032,614486015,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_tcp_mss_1,P_INFO,swLogPrintf("NET DL fast path , TCP SYNC pkt , need MSS check "); +300032,614488063,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp4_dns_relay_1,P_INFO,swLogPrintf("NET DL fast path , RNDIS private IP soltion , dns need relay "); +300032,614488320,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp6Isr_eth_lan_mtu_1,P_WARNING,swLogPrintf("NET DL fast path , pkg length : %d > LAN MTU : %d , need IP segment "); +300032,614490368,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp6Isr_ppp_lan_mtu_1,P_WARNING,swLogPrintf("NET DL fast path , pkg length : %d > LAN MTU : %d , need IP segment "); +300032,614494207,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIp6Isr_fast_fail,P_WARNING,swLogPrintf("NET DL fast path , ipv6 dl fast fail , maybe ndp cache fail "); +300032,614496255,0,0,PLAT_AP,TCPIP_NETADPT,NetFastInsertTcpConnInfo_none_s_1,P_WARNING,swLogPrintf("NET FAST , try add new TCP conn , but list is NULL "); +300032,614497280,0,0,PLAT_AP,TCPIP_NETADPT,NetFastInsertTcpConnInfo_rm_s_1,P_SIG,swLogPrintf("NET FAST , RM oldest tcp conn , ipType : %d , hostPort : %d , rmtPort : %d , curTick : 0x%lx , oldTick : 0x%lx "); +300032,614499072,0,0,PLAT_AP,TCPIP_NETADPT,NetFastPathTcpWSProcess_add_ws,P_DEBUG,swLogPrintf("NET FAST PATH , UL TCP SYN , IpType : %d , hostPort : %d , rmtPort : %d , scaleV : %d , try add into list "); +300032,614501120,0,0,PLAT_AP,TCPIP_NETADPT,NetFastPathTcpWSProcess_disable_ws,P_VALUE,swLogPrintf("NET FAST PATH , UL IpType : %d , hostPort : %d , rmtPort : %d , scaleV : %d , list full , disable WS option "); +300032,614502912,0,0,PLAT_AP,TCPIP_NETADPT,NetFastPathTcpWSProcess_em_ws_1,P_DEBUG,swLogPrintf("NET FAST PATH , UL TCP SYN , IpType : %d , hostPort : %d , rmtPort : %d , no WS option , try to rm from list "); +300032,614505216,0,0,PLAT_AP,TCPIP_NETADPT,NetFastPathTcpWSProcess_1,P_INFO,swLogPrintf("NET FAST PATH TCP WIN ADPT , hostPort : %d , old win %u , new win %u , scaling value %u "); +300032,614506752,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_ip_1,P_WARNING,swLogPrintf("NET UL fast path , can ' t get ipv4 header , or ipver : %d , pkglen : %d , discard "); +300032,614508544,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_wan_ipv4_invalid_1,P_VALUE,swLogPrintf("NET UL fast path , wan ipv4 invalid , ipv4Cid : %d "); +300032,614510592,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_local_1,P_VALUE,swLogPrintf("NET UL fast path , ipv4 dest : 0x%lx , multicast , or to local , local input "); +300032,614514687,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_ip_freg_1,P_WARNING,swLogPrintf("NET UL fast path , ip fregment , need local input "); +300032,614514944,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_mtu_1,P_WARNING,swLogPrintf("NET UL fast path , IP pkg len : %d > WAN MTU : %d , need segment "); +300032,614517248,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_nat_2,P_WARNING,swLogPrintf("NET UL fast path , SRC ipv4 addr : 0x%lx , not host addr : 0x%lx , not UE addr : 0x%lx , fwd to PS for easy "); +300032,614519296,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_udp_1,P_WARNING,swLogPrintf("NET UL fast path , can ' t get UDP header , pkglen : %d , iphdrSize : %d , offset : %d , discard "); +300032,614521344,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_tcp_1,P_WARNING,swLogPrintf("NET UL fast path , can ' t get TCP header , pkglen : %d , iphdrSize : %d , offset : %d , discard "); +300032,614523136,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_mss_1,P_INFO,swLogPrintf("NET UL fast path , TCP SYNC pkt , and LAN MTU : %d > WAN MTU : %d , need MSS check "); +300032,614526975,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_dns_relay_1,P_INFO,swLogPrintf("NET UL fast path , DNS request pkt , Rndis Private Ip solution , need dns relay "); +300032,614526976,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_port_1,P_WARNING,swLogPrintf("NET UL fast path , SRC port : %d , need mapping "); +300032,614531071,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_major_channel_check_1,P_INFO,swLogPrintf("NET UL fast path , lan channel is the secondary , need mapping "); +300032,614531584,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_nat_1,P_WARNING,swLogPrintf("NET UL fast path , SRC ipv4 addr : 0x%lx , not host addr : 0x%lx , not UE addr : 0x%lx , fwd to PS for easy "); +300032,614535167,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp4_ROHC_1,P_WARNING,swLogPrintf("NET UL fast path , ROHC configed , all pass to LWIP "); +300032,614535680,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp6_ip_1,P_WARNING,swLogPrintf("NET UL fast path , can ' t get ipv6 header , or ipver : %d , pkglen : %d , or ip6cid invalid : %d , discard "); +300032,614537216,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp6_wan_ipv6_invalid,P_VALUE,swLogPrintf("NET UL fast path , wan ipv6 invalid , ipv6Cid : %d "); +300032,614540032,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp6_multi_1,P_VALUE,swLogPrintf("NET UL fast path , ipv6 dest : 0x%lx : 0x%lx : 0x%lx : 0x%lx , multicast , local input "); +300032,614542080,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp6_local_1,P_VALUE,swLogPrintf("NET UL fast path , ipv6 dest : 0x%lx : 0x%lx : 0x%lx : 0x%lx , to local "); +300032,614543616,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp6_mtu_1,P_WARNING,swLogPrintf("NET UL fast path , IPv6 pkg len : %d > WAN MTU : %d , need segment "); +300032,614547455,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathRndisIp6_ROHC_1,P_WARNING,swLogPrintf("NET UL fast path , ROHC configed , all pass to LWIP "); +300032,614547968,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_ip_1,P_WARNING,swLogPrintf("NET UL fast path , PPP can ' t get ipv4 header , or ipver : %d , pkglen : %d , or ip4cid invalid : %d , discard "); +300032,614549504,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_ip_wan_ipv4_invalid_1,P_WARNING,swLogPrintf("NET UL fast path , wan ipv4 invalid , ipv4Cid : %d "); +300032,614553599,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_ip_freg_1,P_WARNING,swLogPrintf("NET UL fast path , PPP ip fregment , need local input "); +300032,614553856,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_mtu_1,P_WARNING,swLogPrintf("NET UL fast path , PPP IP pkg len : %d > WAN MTU : %d , need segment "); +300032,614555904,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_udp_1,P_WARNING,swLogPrintf("NET UL fast path , PPP can ' t get UDP header , pkglen : %d , iphdrSize : %d , discard "); +300032,614557952,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_tcp_1,P_WARNING,swLogPrintf("NET UL fast path , PPP can ' t get TCP header , pkglen : %d , iphdrSize : %d , discard "); +300032,614561791,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_windows_adpt_1,P_INFO,swLogPrintf("NET UL fast path , TCP SYNC pkt , need windows adpt "); +300032,614562048,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_mss_1,P_WARNING,swLogPrintf("NET UL fast path , PPP TCP SYNC pkt , and LAN MTU : %d > WAN MTU : %d , need MSS check "); +300032,614563840,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp4_port_1,P_WARNING,swLogPrintf("NET UL fast path , PPP SRC port : %d , need mapping "); +300032,614566400,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp6_ip_1,P_WARNING,swLogPrintf("NET UL fast path , PPP can ' t get ipv6 header , or ipver : %d , pkglen : %d , or ip6cid invalid : %d , discard "); +300032,614567936,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp6_wan_ipv6_invalid_1,P_VALUE,swLogPrintf("NET UL fast path , wan ipv6 invalid , ipv6Cid : %d "); +300032,614570752,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp6_multi_1,P_VALUE,swLogPrintf("NET UL fast path , PPP ipv6 dest : 0x%lx : 0x%lx : 0x%lx : 0x%lx , multicast , local input "); +300032,614572800,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp6_local_1,P_VALUE,swLogPrintf("NET UL fast path , PPP ipv6 dest : 0x%lx : 0x%lx : 0x%lx : 0x%lx , to local "); +300032,614574336,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPathPppIp6_mtu_1,P_WARNING,swLogPrintf("NET UL fast path , PPP IPv6 pkg len : %d > WAN MTU : %d , need segment "); +300032,614576128,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIsr_none_2,P_INFO,swLogPrintf("NET DL fast path , no fast channel info : %d , all DL PDU need to pass to LWIP "); +300032,614578176,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIsr_eth_rohc_3,P_INFO,swLogPrintf("NET DL fast path , cid : %d , rohc enable , all DL PDU need to pass to LWIP "); +300032,614580224,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIsr_PPP_rohc_3,P_INFO,swLogPrintf("NET DL fast path , cid : %d , rohc enable , all DL PDU need to pass to LWIP "); +300032,614582272,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIsr_none_4,P_VALUE,swLogPrintf("NET DL fast path , cid : %d , not bind any lan , pass to LWIP "); +300032,614584320,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlPkgFastPathIsr_ipver_1,P_WARNING,swLogPrintf("NET DL fast path , invalid IpVersion : %d "); +300032,614586880,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_input_w_1,P_WARNING,swLogPrintf("NET UL fast path , invalid input , lanType : %d , pUlHdr : 0x%x , pUlChkInfo : 0x%x , discard UL data "); +300032,614588416,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_RNDIS_w_1,P_WARNING,swLogPrintf("NET UL fast path , ETH input , but LAN is not setup , lanType : %d , discard all UL data "); +300032,614590464,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_ethHdr_1,P_WARNING,swLogPrintf("NET UL fast path , RNDIS , can ' t get ETH header , pkgLen : %d "); +300032,614594559,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_bc_1,P_INFO,swLogPrintf("NET UL fast path , eth pkt dest is broad cast , local input "); +300032,614595840,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_dest_mac_1,P_WARNING,swLogPrintf("NET UL fast path , eth pkt dest : %u : %u : %u : %u : %u : %u is not UE MAC interface , discard "); +300032,614596608,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_eth_type_1,P_VALUE,swLogPrintf("NET UL fast path , other ETH type : %d , local input "); +300032,614598656,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_PPP_w_1,P_WARNING,swLogPrintf("NET UL fast path , PPP input , but LAN is not setup , lanType : %d , discard all UL data "); +300032,614600704,0,0,PLAT_AP,TCPIP_NETADPT,NetifUlPkgFastPath_ppp_ip_ver_1,P_WARNING,swLogPrintf("NET UL fast path , PPP , invalid IP ver : %d , discard "); +300032,614603520,0,0,PLAT_AP,TCPIP_NETADPT,NetFastDelTcpConnInfo_del_s_1,P_SIG,swLogPrintf("NET FAST , RM tcp conn OK : %d , ipType : %d , hostPort : %d , rmtPort : %d "); +300032,614605056,0,0,PLAT_AP,TCPIP_NETADPT,NetGetBindLanNetifByIp4WanNetifAndLanType_1,P_INFO,swLogPrintf("wan neif cid %u is not the same as lan netif cid %u "); +300032,614606848,0,0,PLAT_AP,TCPIP_NETADPT,NetGetBindLanNetifByIp6WanNetifAndLanType_1,P_ERROR,swLogPrintf("wan neif cid %u is not the same as lan netif cid "); +300032,614609664,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4UdpPkgProcess_info,P_INFO,swLogPrintf("netif tcp pkg conn source %u , cid %u , source port %u , dest port %u "); +300032,614611712,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4UdpPkgProcess_1,P_INFO,swLogPrintf("netif udp pkg dest port transfer from %u , to %u , chksum fron %u to %u "); +300032,614615039,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4UdpPkgProcess_checksum_ignore_1,P_INFO,swLogPrintf("netif udp pkg ignor checksum with checksum 0 "); +300032,614615552,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4UdpPkgProcess_info_source_invalid,P_ERROR,swLogPrintf("netif udp pkg source port %u , dest port %u , inlavid conn source %u "); +300032,614617856,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4UdpPkgProcess_2,P_INFO,swLogPrintf("netif udp pkg dest port transfer from %u , to %u , chksum fron %u to %u "); +300032,614621183,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4UdpPkgProcess_checksum_ignore_2,P_INFO,swLogPrintf("netif udp pkg ignor checksum with checksum 0 "); +300032,614621952,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpPkgProcess_info,P_INFO,swLogPrintf("netif tcp pkg conn source %u , cid %u , source port %u , dest port %u "); +300032,614624000,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpPkgProcess_1,P_INFO,swLogPrintf("netif tcp pkg dest port transfer from %u , to %u , chksum fron %u to %u "); +300032,614625792,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpPkgProcess_info_source_invalid,P_ERROR,swLogPrintf("netif udp pkg source port %u , dest port %u , inlavid conn source %u "); +300032,614628096,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpPkgProcess_2,P_INFO,swLogPrintf("netif tcp pkg dest port transfer from %u , to %u , chksum fron %u to %u "); +300032,614631423,0,0,PLAT_AP,TCPIP_NETADPT,NetifIp4PkgFwdWanFromLanSrcAddrProcess_2,P_WARNING,swLogPrintf("dhcp server data is not valid "); +300032,614633471,0,0,PLAT_AP,TCPIP_NETADPT,NetifIp4PkgFwdLanFromWanDestAddrProcess_2,P_WARNING,swLogPrintf("dhcp server data is not valid "); +300032,614635519,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpMssProcess_1,P_INFO,swLogPrintf("tcp sync pkt , check MSS "); +300032,614637567,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpMssProcess_2,P_WARNING,swLogPrintf("tcp sync pkt , invalid MSS option "); +300032,614637824,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpMssProcess_3,P_INFO,swLogPrintf("tcp sync pkt , update MSS from %u to %u "); +300032,614641663,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlIp4TcpMssProcess_4,P_WARNING,swLogPrintf("tcp sync pkt , can not parse MSS option "); +300032,614643711,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlTcpDisableWSOption_2,P_WARNING,swLogPrintf("NET ADPT , tcp sync pkt , invalid windows scale option "); +300032,614644224,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlTcpDisableWSOption_ws_1,P_VALUE,swLogPrintf("NET ADPT , UL syn / syn ack , hostPort : %d , rmtPort : %d , ws : %d , scadisable WS opt "); +300032,614647807,0,0,PLAT_AP,TCPIP_NETADPT,NetifDlTcpDisableWSOption_7,P_INFO,swLogPrintf("NET ADPT , tcp sync pkt , without windows scale option "); +300032,614649855,0,0,PLAT_AP,TCPIP_NETADPT,NetifDnsRelayWanProcess_1,P_INFO,swLogPrintf("dns server relay , trans ip src address "); +300032,614651903,0,0,PLAT_AP,TCPIP_NETADPT,NetifDnsRelayLanProcess_1,P_INFO,swLogPrintf("dns server relay , fresh wan server info "); +300032,614653951,0,0,PLAT_AP,TCPIP_NETADPT,NetifDnsRelayLanProcess_2,P_INFO,swLogPrintf("dns server relay , trans ip dest address "); +300032,614655999,0,0,PLAT_AP,TCPIP_NETADPT,NetifDnsRelayLanProcess_3,P_INFO,swLogPrintf("dns server relay , can not find adpt wan dns server "); +300032,614658047,0,0,PLAT_AP,TCPIP_NETADPT,NetifDnsRelayWanProcess_4,P_INFO,swLogPrintf("dns server relay , trans ip dest address "); +300032,614660095,0,0,PLAT_AP,TCPIP_NETADPT,NetifDnsRelayWanProcess_5,P_WARNING,swLogPrintf("dns server relay , invalid wan dns server "); +300032,614662143,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_fragment_1,P_INFO,swLogPrintf("fragment ip , input "); +300032,614662144,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_1,P_INFO,swLogPrintf("input wan , udp packet dest %u "); +300032,614664192,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_2,P_INFO,swLogPrintf("input wan , tcp packet dest %u "); +300032,614666240,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_3,P_INFO,swLogPrintf("input wan , not udp and tcp packet dest %u "); +300032,614670335,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_4,P_INFO,swLogPrintf("input wan recv loop back or mulicatse pkg , local input "); +300032,614672383,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_5,P_INFO,swLogPrintf("lan recv local pkg , input "); +300032,614674431,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_fragment_2,P_INFO,swLogPrintf("fragment ip , input "); +300032,614674432,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_major_1,P_INFO,swLogPrintf("can not get lan channel major flag , lan type %u "); +300032,614676480,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_6,P_INFO,swLogPrintf("input lan , udp packet dest %u "); +300032,614678784,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_cid_check_1,P_INFO,swLogPrintf("input lan type %u , udp pkg , can not find adpt wan , cid %u "); +300032,614680576,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_7,P_INFO,swLogPrintf("input lan , tcp packet dest %u "); +300032,614682880,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_cid_check_2,P_INFO,swLogPrintf("input lan type %u , tcp pkg , can not find adpt wan , cid %u "); +300032,614684672,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_8,P_INFO,swLogPrintf("input lan , not udp and tcp packet dest %u "); +300032,614686720,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp4InputPkg_9,P_INFO,swLogPrintf("input packet result %u "); +300032,614690815,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp6TcpSyncInputPkg_1,P_INFO,swLogPrintf("netif recv wan pkg , but not ipv6 type "); +300032,614690816,0,0,PLAT_AP,TCPIP_NETADPT,NetifProcessIp6TcpSyncInputPkg_4,P_INFO,swLogPrintf("netif recv wan pkg , invalid lan type %u "); +300032,614692864,0,0,PLAT_AP,TCPIP_NETADPT,NetifLanTcpipInput_1,P_ERROR,swLogPrintf("netif recv lan pkg , but can not find adpt netif , type %u "); +300032,614695424,0,0,PLAT_AP,TCPIP_NETADPT,NetifLanTcpipInput_rohc_only,P_ERROR,swLogPrintf("netif recv lan pkg , need rohc , act : %d , but cid : %d / %d is invalid "); +300032,614696960,0,0,PLAT_AP,TCPIP_NETADPT,NetifLanTcpipInput_2,P_ERROR,swLogPrintf("netif recv lan pkg , but allocate pbuf free , dicard the pkglen : %d "); +300032,614699008,0,0,PLAT_AP,TCPIP_NETADPT,NetifLanTcpipInput_3,P_ERROR,swLogPrintf("NetifLanTcpipInput PPP invalid ip version %u "); +300032,614701056,0,0,PLAT_AP,TCPIP_NETADPT,NetifLanTcpipInput_4,P_ERROR,swLogPrintf("NetifLanTcpipInput invalid lan type %u "); +300032,614703104,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_1,P_WARNING,swLogPrintf("lan type %u channel info is invalid "); +300032,614706176,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_lanchannel_info_1,P_INFO,swLogPrintf("lan channel info type %u , status %u , ip4ActiveCid %u , ip6ActiveCid %u , index %u "); +300032,614707200,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_2,P_INFO,swLogPrintf("channel lan type %u is invalid "); +300032,614709248,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_nettype_1,P_INFO,swLogPrintf("channel lan status %u is invalid "); +300032,614711296,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_3,P_WARNING,swLogPrintf("get lan type %u netif fail "); +300032,614715391,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_4,P_WARNING,swLogPrintf("dhcp server data is not valid "); +300032,614715392,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_nettype_2,P_INFO,swLogPrintf("channel lan status %u is invalid "); +300032,614717440,0,0,PLAT_AP,TCPIP_NETADPT,NetifUpdateFastPathChkInfo_5,P_WARNING,swLogPrintf("get lan type %u netif fail "); +300032,614721535,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetWanInfo_1,P_WARNING,swLogPrintf("NET ADPT , invalid input , can ' t get WAN netif info "); +300032,614723583,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetWanInfo_2,P_WARNING,swLogPrintf("NET ADPT , invalid cid , can ' t get WAN netif info "); +300032,614725631,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetWanInfo_3,P_WARNING,swLogPrintf("NET ADPT , no WAN netif , can ' t get WAN netif info "); +300032,614726400,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_1,P_INFO,swLogPrintf("NetMgrAdptWanIp6Set find ip6 prefix info , source %d , state %d , lifetime %d , active time %d "); +300032,614729727,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_2,P_SIG,swLogPrintf("NetMgrAdptWanIp6Set has find adpt prefix info from hib ip6 context "); +300032,614731775,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_3,P_SIG,swLogPrintf("NetMgrAdptWanIp6Set the hib ip6 prefix liftime has timeout "); +300032,614731776,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_4,P_INFO,swLogPrintf("nd6 prefix entry timer %u "); +300032,614733824,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_5,P_INFO,swLogPrintf("active nd6 address rs refresh timer %u "); +300032,614737919,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_6,P_INFO,swLogPrintf("active nd6 address rs refresh timer has active "); +300032,614739967,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_7,P_SIG,swLogPrintf("new ip6 prefix entry fail "); +300032,614742015,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_8,P_SIG,swLogPrintf("new ip6 prefix entry fail "); +300032,614744063,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanIp6Set_9,P_WARNING,swLogPrintf("NetMgrAdptWanIp6Set invalid ipv6 configuration "); +300032,614746111,0,0,PLAT_AP,TCPIP_NETADPT,PsNetifLinkUp_1,P_WARNING,swLogPrintf("NetMgrAdptWanLinkUp invalid arg "); +300032,614748159,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanLinkUp_1,P_WARNING,swLogPrintf("NetMgrAdptWanLinkUp invalid network type "); +300032,614750207,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanLinkUp_2,P_WARNING,swLogPrintf("NetMgrAdptWanLinkUp netif enter oos "); +300032,614752255,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptInit_1,P_INFO,swLogPrintf("net mgr adpt init success "); +300032,614752512,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanDefaultNetifAutoSet_1,P_INFO,swLogPrintf("NET ADPT auto set , ipv4Cid : %d , ipv6Cid : %d as default netif "); +300032,614754816,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetAtiNetifInfo_type_1,P_WARNING,swLogPrintf("NET ADPT , ipv4Cid : %d , ipv6Cid : %d , netif not default netif , type : %d "); +300032,614756608,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetAtiNetifInfo_invalid_3,P_WARNING,swLogPrintf("NET ADPT , invalid ipv4Cid : %d , ipv6Cid : %d , can ' t get ATI netif info "); +300032,614758400,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_1,P_INFO,swLogPrintf("NetMgrAdptWanRegisterCallback the ipv4 network has been link up cid %u "); +300032,614760448,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_2,P_WARNING,swLogPrintf("NetMgrAdptWanRegisterCallback the ipv6 network has been link up , but ipv4 link with the other cid %u "); +300032,614762496,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_3,P_INFO,swLogPrintf("NetMgrAdptWanRegisterCallback the ipv6 network has been link up cid %u "); +300032,614764544,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_4,P_WARNING,swLogPrintf("NetMgrAdptWanRegisterCallback the ipv4 network has been link up , but ipv6 link with the other cid %u "); +300032,614766592,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_5,P_INFO,swLogPrintf("NetMgrAdptWanRegisterCallback the ipv4&ipv6 network has been link up cid %u "); +300032,614768896,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_6,P_INFO,swLogPrintf("NetMgrAdptWanRegisterCallback the ipv4 network has been link up with cid %u , and ipv6 link up with cid %u "); +300032,614772735,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_7,P_WARNING,swLogPrintf("NetMgrAdptWanRegisterCallback , can not find the bind netif , linkup fail "); +300032,614772736,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanRegisterCallback_8,P_WARNING,swLogPrintf("NetMgrAdptWanRegisterCallback , can not find the bind netif , cid %u "); +300032,614775296,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptDedWanRegisterCallback_in_w_1,P_WARNING,swLogPrintf("NetMgrAdpt , dedicated BR register callback , invalid input , msg : 0x%x , cid : %d , pcid : %d "); +300032,614777088,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptDedWanRegisterCallback_pcid_w_1,P_WARNING,swLogPrintf("NetMgrAdpt , dedicated BR cid : %d register callback , can not find netif via pcid : %d "); +300032,614778880,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanUnregisterCallback_1,P_WARNING,swLogPrintf("NetMgrAdptWanUnregisterCallback invalid cid %u "); +300032,614780928,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanUnregisterCallback_2,P_WARNING,swLogPrintf("NetMgrAdptWanUnregisterCallback can not find the correct netif by cid %u "); +300032,614782976,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetNetInfoCallback_1,P_WARNING,swLogPrintf("NET ADPT , invalid argument , can ' t get ATI netif info for CID : %d "); +300032,614785024,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetNetInfoCallback_2,P_WARNING,swLogPrintf("NET ADPT , can ' t find netif for CID : %d , try to use default netif "); +300032,614787072,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetNetInfoCallback_3,P_WARNING,swLogPrintf("NET ADPT , can not find any netif for cid : %d "); +300032,614789376,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetWanNetInfoCallback_4,P_SIG,swLogPrintf("NET ADPT , reqCid : %d , ATI netif state : %u "); +300032,614791168,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanServiceStateIndCallback_1,P_INFO,swLogPrintf("NetMgrAdptWanServiceStateIndCallback PSIF Inservice %u "); +300032,614795263,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanServiceStateIndCallback_2,P_INFO,swLogPrintf("NetMgrAdptWanServiceStateIndCallback exit all psif oos state "); +300032,614797311,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptWanServiceStateIndCallback_3,P_INFO,swLogPrintf("NetMgrAdptWanServiceStateIndCallback enter all psif oos state "); +300032,614799359,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptClearDnsCacheCallback_1,P_ERROR,swLogPrintf("NetMgrAdptClearDnsCacheCallback invalid name "); +300032,614801407,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptClearAllDnsCacheCallback_1,P_INFO,swLogPrintf("NetMgrAdptClearAllDnsCacheCallback clear all dns cache "); +300032,614803455,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptEnableDnsCacheCallback_1,P_ERROR,swLogPrintf("NetMgrAdptEnableDnsCacheCallback "); +300032,614805503,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptDisaableDnsCacheCallback_1,P_INFO,swLogPrintf("NetMgrAdptDisaableDnsCacheCallback "); +300032,614807551,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptSetDnsServerCallback_1,P_WARNING,swLogPrintf("PS IF , invalid argument "); +300032,614807552,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptSetDnsServerCallback_2,P_WARNING,swLogPrintf("PS IF , can not find any netif for cid : %d "); +300032,614811647,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetDnsServerCallback_1,P_WARNING,swLogPrintf("PS IF , invalid argument "); +300032,614811648,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetDnsServerCallback_2,P_WARNING,swLogPrintf("PS IF , can ' t find netif for CID : %d , try to use default netif "); +300032,614813696,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetDnsServerCallback_3,P_WARNING,swLogPrintf("PS IF , can not find any netif for cid : %d "); +300032,614816000,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptTftConfigCallback_in_w_1,P_WARNING,swLogPrintf("Netadpt , netif TFT config , invalid input msg : 0x%x , cid : %d "); +300032,614817792,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptTftConfigCallback_cid_w_1,P_WARNING,swLogPrintf("Netadpt , netif TFT config , can ' t find netif via cid : %d "); +300032,614821887,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp4Linkup_1,P_WARNING,swLogPrintf("NetMgrAdptLanIp4Linkup , invalid argument "); +300032,614823935,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp4Linkup_2,P_WARNING,swLogPrintf("NetMgrAdptLanIp4Linkup , wan info inavlid "); +300032,614825983,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp4Linkup_dns_relay_1,P_WARNING,swLogPrintf("NetMgrAdptLanIp4Linkup , callocate nds relay server data fail "); +300032,614828031,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp4Linkup_3,P_ERROR,swLogPrintf("NetMgrAdptLanIp4Linkup , start dhcp server fail "); +300032,614830079,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp4Linkup_dns_relay_2,P_WARNING,swLogPrintf("NetMgrAdptLanIp4Linkup , callocate nds relay server data fail "); +300032,614832127,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp6Linkup_1,P_WARNING,swLogPrintf("NetMgrAdptLanIp6Linkup , invalid argument "); +300032,614834175,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp6Linkup_2,P_WARNING,swLogPrintf("NetMgrAdptLanIp6Linkup , enable ipv6 RA server fail "); +300032,614836223,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp6Linkup_3,P_WARNING,swLogPrintf("NetMgrAdptLanIp6Linkup , enable ipv6 RA server fail "); +300032,614838271,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp4LinkDown_1,P_WARNING,swLogPrintf("NetMgrAdptLanIp4LinkDown , invalid argument "); +300032,614840319,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanIp6LinkDown_1,P_WARNING,swLogPrintf("NetMgrAdptLanIp6LinkDown , invalid argument "); +300032,614842367,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanInfo_1,P_WARNING,swLogPrintf("LAN IF , invalid argument "); +300032,614844415,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanInfo_2,P_WARNING,swLogPrintf("LAN IF , hw address length is invalid "); +300032,614846463,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanInfo_3,P_WARNING,swLogPrintf("LAN IF , can not get any WAN info "); +300032,614848511,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanInfo_4,P_WARNING,swLogPrintf("LAN IF , can not get any WAN info "); +300032,614850559,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_1,P_WARNING,swLogPrintf("LAN link up , invalid argument "); +300032,614850560,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_2,P_INFO,swLogPrintf("LAN link up , lan type %u "); +300032,614854655,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_3,P_WARNING,swLogPrintf("LAN link up , can not find lan cfg "); +300032,614856703,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_4,P_WARNING,swLogPrintf("LAN link up , can not find lan channel info "); +300032,614858751,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_5,P_WARNING,swLogPrintf("LAN link up , can not find adpt active wan for none nat mode "); +300032,614858752,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_mem_1,P_WARNING,swLogPrintf("LAN link type %u , can ' t alloc mem for netif "); +300032,614860800,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_6,P_INFO,swLogPrintf("LAN type %u , already link up "); +300032,614864895,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_7,P_ERROR,swLogPrintf("rndis lan IP4 link up false "); +300032,614866943,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_8,P_ERROR,swLogPrintf("rndis lan IP6 link up false "); +300032,614868991,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_9,P_ERROR,swLogPrintf("rndis lan IP4 link up false "); +300032,614871039,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_10,P_ERROR,swLogPrintf("rndis lan IP6 link up false "); +300032,614873087,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_11,P_ERROR,swLogPrintf("rndis lan IP4 link up false "); +300032,614875135,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_12,P_ERROR,swLogPrintf("ppp lan IP4 link up false "); +300032,614877183,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_13,P_ERROR,swLogPrintf("ppp lan IP6 link up false "); +300032,614879231,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_14,P_ERROR,swLogPrintf("ppp lan IP4 link up false "); +300032,614881279,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_15,P_ERROR,swLogPrintf("ppp lan IP6 link up false "); +300032,614883327,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpCallback_16,P_ERROR,swLogPrintf("ppp lan IP4 link up false "); +300032,614885375,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkDownCallback_1,P_WARNING,swLogPrintf("LAN link down , invalid argument "); +300032,614887423,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkDownCallback_3,P_ERROR,swLogPrintf("LAN link down , can not find any LAN netif "); +300032,614889471,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLLStatusChangeCallback_1,P_WARNING,swLogPrintf("LAN link layer status change , invalid argument "); +300032,614891519,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLLStatusChangeCallback_3,P_ERROR,swLogPrintf("LAN link layer status change , can not find any LAN channel info "); +300032,614893567,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLLStatusChangeCallback_4,P_ERROR,swLogPrintf("LAN link layer status change , can not find any LAN netif "); +300032,614895615,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanConfigSetCallback_1,P_WARNING,swLogPrintf("LAN set config , invalid argument "); +300032,614897663,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanConfigSetCallback_2,P_WARNING,swLogPrintf("LAN set config , can not find the global lan config "); +300032,614899711,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanConfigSetCallback_3,P_WARNING,swLogPrintf("LAN set config , can not find free channel "); +300032,614901759,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanConfigSetCallback_4,P_INFO,swLogPrintf("LAN set config , find rndis channel "); +300032,614903807,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptClearDnsRelayWanServerInfo_1,P_WARNING,swLogPrintf("NetMgrAdptClearDnsRelayWanServerInfo get dns relay server data fail "); +300032,614903808,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptClearDnsRelayWanServerInfo_2,P_WARNING,swLogPrintf("NetMgrAdptClearDnsRelayWanServerInfo gan not get the netif by lan net type %u "); +300032,614907903,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBindCheck_1,P_WARNING,swLogPrintf("NetMgrAdptLanBindCheck invalid cid "); +300032,614907904,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBindCheck_2,P_ERROR,swLogPrintf("NetMgrAdptLanBindCheck can not find lan channel cfg , lan type %u "); +300032,614910464,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBindCheck_3,P_WARNING,swLogPrintf("NetMgrAdptLanBindCheck ip4Cid %u ip6Cid %u has bind lan type %u , and also passthrough mode "); +300032,614914047,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_1,P_WARNING,swLogPrintf("NetMgrAdptLanBind invalid cid "); +300032,614916095,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_2,P_WARNING,swLogPrintf("NetMgrAdptLanBind can not get lan cfg "); +300032,614918143,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_3,P_WARNING,swLogPrintf("NetMgrAdptLanBind can not find free channel "); +300032,614918144,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_ip4Cid_check_1,P_WARNING,swLogPrintf("NetMgrAdptLanBind , ip4 cid %u wan is not active and non NAT mode "); +300032,614920192,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_ip6Cid_check_1,P_WARNING,swLogPrintf("NetMgrAdptLanBind , ip6 cid %u wan is not active "); +300032,614924287,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_4,P_INFO,swLogPrintf("NetMgrAdptLanBind , find channel "); +300032,614924288,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_ip4Cid_check_3,P_WARNING,swLogPrintf("NetMgrAdptLanBind , ip4 cid %u wan is not active and non NAT mode "); +300032,614926336,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_ip6Cid_check_4,P_WARNING,swLogPrintf("NetMgrAdptLanBind , ip6 cid %u wan is not active "); +300032,614930431,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_5,P_ERROR,swLogPrintf("NetMgrAdptLanBind lan IP4 link up false "); +300032,614930432,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_6,P_INFO,swLogPrintf("NetMgrAdptLanBind get lan type %d netif fail "); +300032,614934527,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_7,P_INFO,swLogPrintf("NetMgrAdptLanBind get wan info fail "); +300032,614936575,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_8,P_ERROR,swLogPrintf("NetMgrAdptLanBind lan IP6 link up false "); +300032,614936576,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_9,P_INFO,swLogPrintf("NetMgrAdptLanBind get lan type %d netif fail "); +300032,614940671,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_10,P_INFO,swLogPrintf("NetMgrAdptLanBind get wan info fail "); +300032,614940672,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_11,P_INFO,swLogPrintf("NetMgrAdptLanBind lan type %d invalid netType for none nat mode "); +300032,614944767,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_12,P_INFO,swLogPrintf("NetMgrAdptLanBind get wan info fail "); +300032,614946815,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_13,P_ERROR,swLogPrintf("NetMgrAdptLanBind lan IP6 link up false "); +300032,614946816,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_14,P_INFO,swLogPrintf("NetMgrAdptLanBind get lan type %d netif fail "); +300032,614950911,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanBind_15,P_INFO,swLogPrintf("NetMgrAdptLanBind get wan info fail "); +300032,614952959,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanUnbind_1,P_WARNING,swLogPrintf("NetMgrAdptLanUnbind invalid cid "); +300032,614955007,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanUnbind_2,P_WARNING,swLogPrintf("NetMgrAdptLanUnbind can not find lan cfg "); +300032,614957055,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanUnbind_3,P_INFO,swLogPrintf("NetMgrAdptLanUnbind find channel "); +300032,614957056,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanUnbind_4,P_INFO,swLogPrintf("LAN unbind , can not find %d netif "); +300032,614959104,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanUnbind_5,P_INFO,swLogPrintf("LAN unbind , can not find %d netif "); +300032,614961152,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanUnbind_6,P_INFO,swLogPrintf("LAN unbind , can not find %d netif "); +300032,614965247,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanCtrlCallback_1,P_WARNING,swLogPrintf("LAN ctrl , invalid argument "); +300032,614967295,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanCtrlCallback_2,P_WARNING,swLogPrintf("LAN ctrl check fail "); +300032,614967296,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanCtrlCallback_3,P_WARNING,swLogPrintf("LAN ctrl , invalid action %d "); +300032,614971391,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrGetLanDataPathHostIp4Info_1,P_WARNING,swLogPrintf("NetMgrGetLanDataPathHostIp4Info invalid argument "); +300032,614973439,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrGetLanDataPathHostIp4Info_2,P_INFO,swLogPrintf("NetMgrGetLanDataPathHostIp4Info pass through mode , can not find channel info , maybe not bind "); +300032,614973440,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrGetLanDataPathHostIp4Info_3,P_INFO,swLogPrintf("NetMgrGetLanDataPathHostIp4Info pass through mode , can not find wan info , bind ip4 cid %u "); +300032,614977535,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrGetLanDataPathHostIp6Info_1,P_INFO,swLogPrintf("NetMgrGetLanDataPathHostIp6Info invalid argument "); +300032,614979583,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrGetLanDataPathHostIp6Info_2,P_INFO,swLogPrintf("NetMgrGetLanDataPathHostIp6Info pass through mode , can not find channel info , maybe not bind "); +300032,614979584,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrGetLanDataPathHostIp6Info_3,P_INFO,swLogPrintf("NetMgrGetLanDataPathHostIp6Info pass through mode , can not find wan info , bind ip4 cid %u "); +300032,614983679,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanDataPathHostInfoCallback_1,P_WARNING,swLogPrintf("NetMgrAdptGetLanDataPathHostInfoCallback invalid argument "); +300032,614985727,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanDataPathHostInfoCallback_2,P_WARNING,swLogPrintf("NetMgrAdptGetLanDataPathHostInfoCallback can not get lan cfg "); +300032,614985984,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanDataPathHostInfoCallback_3,P_INFO,swLogPrintf("NetMgrAdptGetLanDataPathHostInfoCallback get ip4Cid %u , ip6Cid %u "); +300032,614987776,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanDataPathHostInfoCallback_4,P_INFO,swLogPrintf("NetMgrAdptGetLanDataPathHostInfoCallback get ip4Cid %u "); +300032,614989824,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanDataPathHostInfoCallback_5,P_INFO,swLogPrintf("NetMgrAdptGetLanDataPathHostInfoCallback get ip6Cid %u "); +300032,614993919,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptGetLanDataPathHostInfoCallback_6,P_WARNING,swLogPrintf("NetMgrAdptGetLanDataPathHostInfoCallback get fail "); +300032,614993920,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpdateByWanLinkDown_1,P_WARNING,swLogPrintf("NetMgrAdptLanLinkUpdateByWanLinkDown invalid cid %u "); +300032,614995968,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpdateByWanLinkDown_2,P_WARNING,swLogPrintf("NetMgrAdptLanLinkUpdateByWanLinkDown can not find lan netif cid %u "); +300032,614998016,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpdateByWanLinkDown_3,P_WARNING,swLogPrintf("NetMgrAdptLanLinkUpdateByWanLinkDown can not find lan netif cid %u "); +300032,615000064,0,0,PLAT_AP,TCPIP_NETADPT,NetMgrAdptLanLinkUpdateByWanLinkDown_4,P_WARNING,swLogPrintf("NetMgrAdptLanLinkUpdateByWanLinkDown can not find lan netif cid %u "); +300032,615004159,0,0,PLAT_AP,TCPIP_NETADPT,PsifGetTcpipHibContext_1,P_ERROR,swLogPrintf("PsifGetTcpipHibContext invalid tcpip hib context header point "); +300032,615005184,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreIp6Info_1,P_INFO,swLogPrintf("PsifTcpipStoreIp6Info ip6 prefix %x : %x , life_time %u,active_time %u , cid %u "); +300032,615008255,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreIp6Info_2,P_INFO,swLogPrintf("PsifTcpipStoreIp6Info ip6 prefix info is not invalid "); +300032,615010303,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreIp6Info_3,P_INFO,swLogPrintf("PsifTcpipStoreIp6Info ip6 prefix not exsit "); +300032,615012351,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreTcpContext_1,P_INFO,swLogPrintf("PsifTcpipStoreTcpContext store one tcp context "); +300032,615012352,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreTcpContext_2,P_INFO,swLogPrintf("PsifTcpipStoreTcpContext the tcp context state is not invalid %u "); +300032,615016447,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreTcpContext_3,P_INFO,swLogPrintf("PsifTcpipStoreTcpContext not exist valid tcp context "); +300032,615018495,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreDnsCache_1,P_INFO,swLogPrintf("PsifTcpipStoreDnsCache store one dns cache "); +300032,615020543,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreDnsCache_2,P_INFO,swLogPrintf("PsifTcpipStoreDnsCache not exist valid dns cache "); +300032,615022591,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreUdpContext_1,P_INFO,swLogPrintf("PsifTcpipStoreUdpContext store one udp context "); +300032,615024639,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreUdpContext_2,P_INFO,swLogPrintf("PsifTcpipStoreUdpContext the udp context state is not invalid "); +300032,615026687,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStoreUdpContext_3,P_INFO,swLogPrintf("PsifTcpipStoreUdpContext not exist valid udp context "); +300032,615028735,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStorePortMgrContext_1,P_WARNING,swLogPrintf("PsifTcpipStorePortMgrContext malloc fail "); +300032,615029760,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStorePortMgrContext_2,P_INFO,swLogPrintf("PsifTcpipStorePortMgrContext port mgr context connSource %connType %u , lastUsedTime %u , mappingPort %u , originalPort %u "); +300032,615032831,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipStorePortMgrContext_3,P_INFO,swLogPrintf("PsifTcpipStorePortMgrContext port mgr context not exsit "); +300032,615033856,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverIp6Info_1,P_INFO,swLogPrintf("PsifTcpipRecoverIp6Info ip6 prefix %x : %x , life_time %u,active_time %u , cid %u "); +300032,615036927,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverTcpContext_1,P_INFO,swLogPrintf("PsifTcpipRecoverTcpContext tcp context success "); +300032,615038975,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverTcpContext_2,P_INFO,swLogPrintf("PsifTcpipRecoverTcpContext tcp context fail "); +300032,615041023,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverDnsCache_1,P_INFO,swLogPrintf("PsifTcpipRecoverDnsCache dns cache "); +300032,615043071,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverUdpContext_1,P_INFO,swLogPrintf("PsifTcpipRecoverUdpContext udp context success "); +300032,615045119,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverUdpContext_2,P_INFO,swLogPrintf("PsifTcpipRecoverUdpContext udp context fail "); +300032,615046144,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipRecoverPortMgrContext_1,P_INFO,swLogPrintf("PsifTcpipRecoverPortMgrContext context connType %u , connSource %originalPort %u , mappingPort %u , lastUsedTime %u "); +300032,615049215,0,0,PLAT_AP,TCPIP_NETADPT,PsifRecoverContextFromHibCallback_1,P_INFO,swLogPrintf("PsifRecoverContextFromHibCallback recover ip6info "); +300032,615051263,0,0,PLAT_AP,TCPIP_NETADPT,PsifRecoverContextFromHibCallback_2,P_INFO,swLogPrintf("PsifRecoverContextFromHibCallback recover tcp context "); +300032,615053311,0,0,PLAT_AP,TCPIP_NETADPT,PsifRecoverContextFromHibCallback_3,P_INFO,swLogPrintf("PsifRecoverContextFromHibCallback recover dns cache "); +300032,615055359,0,0,PLAT_AP,TCPIP_NETADPT,PsifRecoverContextFromHibCallback_4,P_INFO,swLogPrintf("PsifRecoverContextFromHibCallback recover udp context "); +300032,615057407,0,0,PLAT_AP,TCPIP_NETADPT,PsifRecoverContextFromHibCallback_5,P_INFO,swLogPrintf("PsifRecoverContextFromHibCallback recover port mgr context "); +300032,615059455,0,0,PLAT_AP,TCPIP_NETADPT,PsifIsTcpipAllowEnterHIB_1,P_INFO,swLogPrintf("TCPIP EXIST any pending data , not allow enter hib / sleep2 mode "); +300032,615059456,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipEnterHibCallback_1,P_SIG,swLogPrintf("PsifTcpipEnterHibCallback state %u "); +300032,615063551,0,0,PLAT_AP,TCPIP_NETADPT,PisfCheckTcpipHibContextNeedChang_1,P_INFO,swLogPrintf("LWIP hib context changed "); +300032,615065599,0,0,PLAT_AP,TCPIP_NETADPT,PsifRequestRecoverContextFromHib_1,P_SIG,swLogPrintf("PsifRequestRecoverContextFromHib "); +300032,615067647,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipHibModeInit_1,P_INFO,swLogPrintf("TCPIP HIB mode init "); +300032,615067648,0,0,PLAT_AP,TCPIP_NETADPT,EthifLowLevelOutput_if_link_type_check_1,P_WARNING,swLogPrintf("ETH if link type %u is invalid "); +300032,615071743,0,0,PLAT_AP,TCPIP_NETADPT,EthifLowLevelOutput_if_down,P_WARNING,swLogPrintf("ETH if is not link up "); +300032,615072000,0,0,PLAT_AP,TCPIP_NETADPT,EthifLowLevelOutput_1,P_WARNING,swLogPrintf("UL pkg Len : %d > MTU : %d , ignore this pkg "); +300032,615074048,0,0,PLAT_AP,TCPIP_NETADPT,RndisifLowLevelOutput_2,P_VALUE,swLogPrintf("ETH IF type %u , UE -> Host , len : %u "); +300032,615077887,0,0,PLAT_AP,TCPIP_NETADPT,RndisIfRecvUlPkg_1,P_ERROR,swLogPrintf("RndisIfRecvUlPkg fail "); +300032,615077888,0,0,PLAT_AP,TCPIP_NETADPT,LanifSendNetifInfo_1,P_VALUE,swLogPrintf("LanifSendNetifInfo invalid lan type %d "); +300032,615080192,0,0,PLAT_AP,TCPIP_NETADPT,LanifSendNetifInfo_info_1,P_VALUE,swLogPrintf("LanifSendNetifInfo lan type %d , cause %d "); +300032,615082240,0,0,PLAT_AP,TCPIP_NETADPT,LanifSendNetifInfo_2,P_VALUE,swLogPrintf("LanifSendNetifInfo lan %d invalid netType %d , maybe nat mode "); +300032,615084032,0,0,PLAT_AP,TCPIP_NETADPT,LanifSendNetifInfo_3,P_VALUE,swLogPrintf("LanifSendNetifInfo lan %d status deactive "); +300032,615086080,0,0,PLAT_AP,TCPIP_NETADPT,LanifSendNetifInfo_4,P_VALUE,swLogPrintf("LanifSendNetifInfo lan %d can not find channel info "); +300032,615088128,0,0,PLAT_AP,TCPIP_NETADPT,LanifSendNetifInfo_5,P_VALUE,swLogPrintf("LanifSendNetifInfo lan %d , invalid cause "); +300032,615092223,0,0,PLAT_AP,TCPIP_NETADPT,PppifLowLevelOutput_if_down,P_WARNING,swLogPrintf("PPP if is not link up "); +300032,615092480,0,0,PLAT_AP,TCPIP_NETADPT,PppifUlOutput_1,P_WARNING,swLogPrintf("UL pkg Len : %d > MTU : %d , ignore this pkg "); +300032,615096319,0,0,PLAT_AP,TCPIP_NETADPT,PppIfRecvUlPkg_1,P_ERROR,swLogPrintf("PppIfRecvUlPkg fail "); +300032,615096576,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlOutput_4,P_WARNING,swLogPrintf("PS IF %c%u is OOS state "); +300032,615098880,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlOutput_1,P_WARNING,swLogPrintf("CID : %d , UL pkg Len : %d > MTU : %d , ignore this pkg "); +300032,615102463,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlOutput_2,P_WARNING,swLogPrintf("PS UL highwater , busy "); +300032,615103232,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlOutput_3,P_INFO,swLogPrintf("PS UL PDU , esmRai : %u , bExceptData : %u , ticktype : %u ( 0 -NO / 1 -DISCARD / 2 -START ) , systick : %u "); +300032,615104512,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpDlIpInput_1,P_ERROR,swLogPrintf("PsifTcpIpDlIpInput invalid ip version %u "); +300032,615106560,0,0,PLAT_AP,TCPIP_NETADPT,PsifDlPkgFastPath_3,P_VALUE,swLogPrintf("PSIF DL fast path , cid : %d not bind a lan "); +300032,615108608,0,0,PLAT_AP,TCPIP_NETADPT,PsifDlPkgFastPath_4,P_WARNING,swLogPrintf("PSIF DL fast path , invalid IpVersion : %d "); +300032,615110912,0,0,PLAT_AP,TCPIP_NETADPT,PsifDlPkgFastPath_5,P_WARNING,swLogPrintf("PSIF DL fast path , can not find correct netif via cid : %u , pdu 0x%x "); +300032,615114751,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcDecompOnePkg_arg_a,P_WARNING,swLogPrintf("PsifTcpIpRohcDecompOnePkg invalid parameter "); +300032,615116799,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcDecompOnePkg_1,P_WARNING,swLogPrintf("ROHC decompress pkg failed "); +300032,615118847,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcDecompOnePkg_2,P_WARNING,swLogDump("ROHC DL recv comped pkg : "); +300032,615119616,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcDecompOnePkg_3,P_INFO,swLogPrintf("ROHC decomp SUCC , decomp header len : %u , pkg payload offset : %u , pkg payload len : %u , feedback len : %u "); +300032,615120896,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcDecompOnePkg_4,P_INFO,swLogPrintf("Test loopback decompressed raw pkg , pkg len : %d "); +300032,615123200,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcInput_1,P_VALUE,swLogPrintf("PSIF , CID : %d , DL ROHC feedback packet , len : %d "); +300032,615125248,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcInput_2,P_WARNING,swLogPrintf("PSIF , CID : %d , pRohcComp : 0x%lx , DL ROHC feedback packet , decomp failed "); +300032,615127296,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpIpRohcInput_3,P_VALUE,swLogPrintf("PSIF , CID : %d , DL PKG need to ignore ROHC decomp , pkg len : %d "); +300032,615129344,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipDlInput_1,P_WARNING,swLogPrintf("Can not find correct netif , cid %u , pdu 0x%x "); +300032,615131136,0,0,PLAT_AP,TCPIP_NETADPT,PsSuspendIndCallback_1,P_INFO,swLogPrintf("PsGetNetInfoCallback is suspend : %u "); +300032,615133184,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_1,P_WARNING,swLogPrintf("CID : %d , configed ROHC , but not ROCH COMP channel "); +300032,615137279,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_2,P_INFO,swLogDump("ROHC , PKG before compress : "); +300032,615137280,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_3,P_WARNING,swLogPrintf("CID : %d , configed ROHC , no more memory allo from compressed header "); +300032,615139328,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_4,P_WARNING,swLogPrintf("CID : %d , ROHC compress PKG fail , UL pkg send fail "); +300032,615142400,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_5,P_WARNING,swLogPrintf("CID : %d , ROHC compress PKG , RAW PKG len : %d , compressed offset : %d , payload size : %d , compressed header size : %d "); +300032,615143424,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_6,P_WARNING,swLogPrintf("CID : %d , ROHC compress output is not right , discard this UL pkg "); +300032,615146240,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_7,P_INFO,swLogPrintf("PS UL new pdu esmRai %u , bexceptdata %u , ticktype %u , systick %u "); +300032,615148032,0,0,PLAT_AP,TCPIP_NETADPT,PsifUlRohcOutput_8,P_INFO,swLogPrintf("PS UL rohc process fail , cid %u , pdu list hdr 0x%x , total len %u "); +300032,615149824,0,0,PLAT_AP,TCPIP_NETADPT,PsifAllocUlPkgMem_1,P_WARNING,swLogPrintf("PS IF UL PKG high water : %u , can ' t alloc this new len : %d "); +300032,615151616,0,0,PLAT_AP,TCPIP_NETADPT,PsifAllocUlPkgMem_2,P_INFO,swLogPrintf("PsifAllocUlPkgMem alloc success , address 0x%x "); +300032,615153664,0,0,PLAT_AP,TCPIP_NETADPT,PsifFreeUlPkgMem_1,P_INFO,swLogPrintf("PsifFreeUlPkgMem free address 0x%x "); +300032,615155968,0,0,PLAT_AP,TCPIP_NETADPT,PsNetifSyncRohcChannel_1,P_INFO,swLogPrintf("PsNetifSyncRohcChannel sync netif 0x%x with cid %u rohc channel "); +300032,615157760,0,0,PLAT_AP,TCPIP_NETADPT,PsifSuspendInd_1,P_SIG,swLogPrintf("PSIF , suspend ( 1 ) / resume ( 0 ) : %u LWIP "); +300032,615159808,0,0,PLAT_AP,TCPIP_NETADPT,PsifSuspendInd_2,P_WARNING,swLogPrintf("PSIF , suspend ( 1 ) / resume ( 0 ) : %u , LWIP FAIL "); +300032,615162624,0,0,PLAT_AP,TCPIP_NETADPT,PsifNetifTftConfig_cid_w_1,P_ERROR,swLogPrintf("PSIF , netif TFT cfg , pfNum : %d , idx : %x , cid : %d ! = %d "); +300032,615163904,0,0,PLAT_AP,TCPIP_NETADPT,PsifAllocDlRamBlockMem_1,P_WARNING,swLogPrintf("ps dl ram alloc high water , %u "); +300032,615165952,0,0,PLAT_AP,TCPIP_NETADPT,PsifAllocDlRamBlockMem_2,P_WARNING,swLogPrintf("ps dl ram alloc FAIL , %u "); +300032,615168256,0,0,PLAT_AP,TCPIP_NETADPT,PsifAllocDlRamBlockMem_3,P_INFO,swLogPrintf("ps dl ram alloc 0x%x success , data len %u "); +300032,615172095,0,0,PLAT_AP,TCPIP_NETADPT,PsifTcpipDlHighWaterChkInput_1,P_INFO,swLogPrintf("PS DL BUFFER high water "); +300032,615174143,0,0,PLAT_AP,TCPIP_NETADPT,PsifFreeDlRamBlockMem_1,P_WARNING,swLogPrintf("ps dl ram free , invalid pbuf "); +300032,615174144,0,0,PLAT_AP,TCPIP_NETADPT,PsifFreeDlRamBlockMem_2,P_WARNING,swLogPrintf("ps dl ram free , invalid dl data header point , 0x%x "); +300032,615176448,0,0,PLAT_AP,TCPIP_NETADPT,PsifSendNetifInfoInd_down_1,P_VALUE,swLogPrintf("Netif linkdown , ipv4Cid : %d , ipv6Cid : %d "); +300032,615178496,0,0,PLAT_AP,TCPIP_NETADPT,PsifSendNetifInfoInd_ipv4_down_1,P_VALUE,swLogPrintf("Netif only ipv4 linkdown , ipv4Cid : %d , ipv6Cid : %d "); +300032,615180288,0,0,PLAT_AP,TCPIP_NETADPT,PsifSendNetifInfoInd_ipv4_down_2,P_WARNING,swLogPrintf("Netif only ipv4 linkdown , but no ipv6 exist , iptype : %d "); +300032,615182592,0,0,PLAT_AP,TCPIP_NETADPT,PsifSendNetifInfoInd_ipv6_down_1,P_VALUE,swLogPrintf("Netif only ipv6 linkdown , ipv4Cid : %d , ipv6Cid : %d "); +300032,615184384,0,0,PLAT_AP,TCPIP_NETADPT,PsifSendNetifInfoInd_ipv6_down_2,P_WARNING,swLogPrintf("Netif only ipv6 linkdown , but no ipv4 exist , iptype : %d "); +300032,615186944,0,0,PLAT_AP,TCPIP_NETADPT,PsifSendNetifInfoInd_notify_1,P_SIG,swLogPrintf("Netif change cause : %e , net status : %e , ipType %e "); +300032,615188480,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrAllocateMappingTable_1,P_INFO,swLogPrintf("PortMgrAllocateMappingTable allocate tcpip port mgr table 0x%x "); +300032,615191552,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrFreeMappingTable_1,P_INFO,swLogPrintf("PortMgrAllocateMappingTable free tcpip port mgr table 0x%x , conn source %u , original port %u , mapping port %u , cid %u "); +300032,615192576,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrMappingTableHighWaterProcess_1,P_INFO,swLogPrintf("PortMgrMappingTableHighWaterProcess context num %u "); +300032,615195648,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrGetMappingTableByOriginalPort_1,P_INFO,swLogPrintf("PortMgrGetMappingTableByOriginalPort get tcpip port mgr table 0x%x , source %u , original port %u , mapping port %u , cid %u "); +300032,615197696,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrGetMappingTableByOriginalPort_2,P_INFO,swLogPrintf("PortMgrGetMappingTableByOriginalPort get tcpip port mgr table 0x%x , source %u , original port %u , mapping port %u , cid %u "); +300032,615199744,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrGetMappingTableByMappingPort_1,P_INFO,swLogPrintf("PortMgrGetMappingTableByMappingPort get tcpip port mgr table 0x%x , source %u , original port %u , mapping port %u , cid %u "); +300032,615201792,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrGetMappingTableByMappingPort_2,P_INFO,swLogPrintf("PortMgrGetMappingTableByMappingPort get tcpip port mgr table 0x%x , source %u , original port %u , mapping port %u , cid %u "); +300032,615203840,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrUlProcess_1,P_INFO,swLogPrintf("PortMgrUlProcess add new tcpip port mgr table 0x%x , source %u , original port %u , mapping port %u , cid %u "); +300032,615206911,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrUlProcess_2,P_INFO,swLogPrintf("PortMgrUlProcess allocate mapping table fail "); +300032,615208959,0,0,PLAT_AP,TCPIP_NETADPT,PortMgrUlProcess_3,P_INFO,swLogPrintf("PortMgrUlProcess get new mapping port fail "); +300032,615208960,0,0,PLAT_AP,TCPIP_NETADPT,dns_enqueue_cid_1,P_WARNING,swLogPrintf("can ' t find netif for CID : %d , try to use default netif "); +300032,615213055,0,0,PLAT_AP,TCPIP_NETADPT,nd6_input_ipv6_ra_server_1,P_WARNING,swLogPrintf("enable ipv6 RA server fail "); +300032,615215103,0,0,PLAT_AP,TCPIP_NETADPT,nd6_input_ipv6_ra_server_2,P_WARNING,swLogPrintf("enable ipv6 RA server fail "); +302080,618663935,0,0,PLAT_AP,TCPIP_APP,AppGetAddrInfoAsync_1,P_ERROR,swLogPrintf("get dns fail , invalid arg "); +302080,618665983,0,0,PLAT_AP,TCPIP_APP,AppGetAddrInfoAsync_3,P_ERROR,swLogPrintf("get dns fail "); +303104,620761087,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsScanOptions_1,P_ERROR,swLogPrintf("bad packet , malformed option field "); +303104,620761088,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsAddBinaryOption_1,P_ERROR,swLogPrintf("option 0x%x did not fit into the packet "); +303104,620763136,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsAddSimpleOption_1,P_ERROR,swLogPrintf("can ' t add option 0x%x "); +303104,620767231,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendOffer_1,P_ERROR,swLogPrintf("create pbuf fail "); +303104,620769279,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendOffer_2,P_INFO,swLogPrintf("sending OFFER "); +303104,620771327,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendNak_1,P_ERROR,swLogPrintf("create pbuf fail "); +303104,620773375,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendNak_2,P_INFO,swLogPrintf("sending NAK "); +303104,620775423,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendAck_1,P_ERROR,swLogPrintf("create pbuf fail "); +303104,620777471,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendAck_2,P_INFO,swLogPrintf("sending ACK "); +303104,620779519,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendInform_1,P_ERROR,swLogPrintf("create pbuf fail "); +303104,620781567,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsSendInform_2,P_INFO,swLogPrintf("sending NAK "); +303104,620783615,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_1,P_WARNING,swLogPrintf("DhcpdRecv netif or pbuf point is invalid "); +303104,620785663,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_2,P_ERROR,swLogPrintf("DhcpdRecv netif server data is invalid "); +303104,620787711,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_3,P_WARNING,swLogPrintf("DhcpdRecv pbuf copy fail "); +303104,620789759,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_4,P_WARNING,swLogPrintf("DhcpdRecv pbuf allocate fail "); +303104,620791807,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_5,P_ERROR,swLogPrintf("DhcpdRecv MAC length ! = 6 ignoring packet "); +303104,620793855,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_6,P_WARNING,swLogPrintf("DhcpdRecv not a REQUEST ignoring packet "); +303104,620795903,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_7,P_WARNING,swLogPrintf("DhcpdRecv no or bad message type option ignoring packet "); +303104,620797951,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_8,P_WARNING,swLogPrintf("DhcpdRecv server ID doesn ' t match ignoring packet "); +303104,620799999,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_9,P_INFO,swLogPrintf("DhcpdRecv DISCOVER "); +303104,620802047,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_10,P_INFO,swLogPrintf("DhcpdRecv REQUEST "); +303104,620804095,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_11,P_INFO,swLogPrintf("no requested IP and no ciaddr ignore "); +303104,620806143,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_12,P_INFO,swLogPrintf("DhcpdRecv DECLINE "); +303104,620808191,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_13,P_INFO,swLogPrintf("DhcpdRecv DECLINE the lease ip "); +303104,620810239,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_14,P_INFO,swLogPrintf("DhcpdRecv RELEASE "); +303104,620812287,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_15,P_INFO,swLogPrintf("DhcpdRecv RELEASE the lease ip "); +303104,620814335,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_16,P_INFO,swLogPrintf("DhcpdRecv INFORM "); +303104,620814336,0,0,PLAT_AP,TCPIP_DHCPD,DhcpsRecv_17,P_INFO,swLogPrintf("DhcpdRecv %u "); +303104,620818431,0,0,PLAT_AP,TCPIP_DHCPD,dhcpd_setup_1,P_ERROR,swLogPrintf("allocate dhcp server pcb fail "); +303104,620820479,0,0,PLAT_AP,TCPIP_DHCPD,dhcpd_setup_2,P_WARNING,swLogPrintf("dhcp server pcb has already setup "); +303104,620822527,0,0,PLAT_AP,TCPIP_DHCPD,DhcpStart_1,P_ERROR,swLogPrintf("allocate dhcp server pcb fail "); +303104,620824575,0,0,PLAT_AP,TCPIP_DHCPD,DhcpStart_2,P_INFO,swLogPrintf("dhcpd_start ( ) : mallocing new DHCP server "); +303104,620826623,0,0,PLAT_AP,TCPIP_DHCPD,DhcpStart_3,P_ERROR,swLogPrintf("dhcpd server allocate fail "); +303104,620828671,0,0,PLAT_AP,TCPIP_DHCPD,DhcpdStop_1,P_ERROR,swLogPrintf("DhcpdStop netif point is invalid "); +303104,620828928,0,0,PLAT_AP,TCPIP_DHCPD,DhcpdStop_2,P_INFO,swLogPrintf("dhcp server stop success netif %c%u "); +304128,622858239,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_1,P_INFO,swLogPrintf("TcpipConnectionCreates invalid param "); +304128,622860287,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_2,P_INFO,swLogPrintf("TcpipConnectionCreates invalid param "); +304128,622862335,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_3,P_INFO,swLogPrintf("TcpipConnectionCreates invalid param "); +304128,622864383,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_4,P_INFO,swLogPrintf("TcpipConnectionCreates local address invalid "); +304128,622866431,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_5,P_INFO,swLogPrintf("TcpipConnectionCreates destAddr invalid "); +304128,622868479,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_6,P_INFO,swLogPrintf("TcpipConnectionCreates protocol invalid "); +304128,622870527,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_7,P_INFO,swLogPrintf("TcpipConnectionCreates send request fail "); +304128,622872575,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_8,P_INFO,swLogPrintf("TcpipConnectionCreates send request timeout "); +304128,622872832,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_9,P_INFO,swLogPrintf("TcpipConnectionCreates recv response success , result %d , cause %d "); +304128,622876671,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionCreate_10,P_INFO,swLogPrintf("TcpipConnectionCreates recv invalid response "); +304128,622878719,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_1,P_INFO,swLogPrintf("TcpipConnectionSend invalid param "); +304128,622880767,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_2,P_INFO,swLogPrintf("TcpipConnectionSend invalid param "); +304128,622882815,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_3,P_INFO,swLogPrintf("TcpipConnectionSend invalid param "); +304128,622884863,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_4,P_INFO,swLogPrintf("TcpipConnectionSend send request fail "); +304128,622886911,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_5,P_INFO,swLogPrintf("TcpipConnectionSend send request timeout "); +304128,622887168,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_6,P_INFO,swLogPrintf("TcpipConnectionSend recv response success , result %d , cause %d "); +304128,622891007,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionSend_7,P_INFO,swLogPrintf("TcpipConnectionSend recv invalid response "); +304128,622893055,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_1,P_INFO,swLogPrintf("TcpipConnectionClose invalid param "); +304128,622895103,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_2,P_INFO,swLogPrintf("TcpipConnectionClose invalid param "); +304128,622897151,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_3,P_INFO,swLogPrintf("TcpipConnectionClose invalid param "); +304128,622899199,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_4,P_INFO,swLogPrintf("TcpipConnectionClose send request fail "); +304128,622901247,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_5,P_INFO,swLogPrintf("TcpipConnectionClose send request timeout "); +304128,622901504,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_6,P_INFO,swLogPrintf("TcpipConnectionClose recv response success , result %d , cause %d "); +304128,622905343,0,0,PLAT_AP,TCPIP_SDK_API,TcpipConnectionClose_7,P_INFO,swLogPrintf("TcpipConnectionClose recv invalid response "); +304128,622907391,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_1,P_INFO,swLogPrintf("TcpipGetTotalSendLen invalid param "); +304128,622909439,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_2,P_INFO,swLogPrintf("TcpipGetTotalSendLen invalid param "); +304128,622911487,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_3,P_INFO,swLogPrintf("TcpipGetTotalSendLen invalid param "); +304128,622913535,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_4,P_INFO,swLogPrintf("TcpipGetTotalSendLen send request fail "); +304128,622915583,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_5,P_INFO,swLogPrintf("TcpipGetTotalSendLen send request timeout "); +304128,622915840,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_6,P_INFO,swLogPrintf("TcpipGetTotalSendLen recv response success , result %d , result %u "); +304128,622919679,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalSendLen_7,P_INFO,swLogPrintf("TcpipGetTotalSendLen recv invalid response "); +304128,622921727,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_1,P_INFO,swLogPrintf("TcpipGetTotalAckedLen invalid param "); +304128,622923775,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_2,P_INFO,swLogPrintf("TcpipGetTotalAckedLen invalid param "); +304128,622925823,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_3,P_INFO,swLogPrintf("TcpipGetTotalAckedLen invalid param "); +304128,622927871,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_4,P_INFO,swLogPrintf("TcpipGetTotalAckedLen send request fail "); +304128,622929919,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_5,P_INFO,swLogPrintf("TcpipGetTotalAckedLen send request timeout "); +304128,622930176,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_6,P_INFO,swLogPrintf("TcpipGetTotalAckedLen recv response success , result %d , result %u "); +304128,622934015,0,0,PLAT_AP,TCPIP_SDK_API,TcpipGetTotalAckedLen_7,P_INFO,swLogPrintf("TcpipGetTotalAckedLen recv invalid response "); +304128,622936063,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendResponse_1,P_ERROR,swLogPrintf("TcpipApiSendResponse invalid parameter "); +304128,622938111,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendResponse_2,P_ERROR,swLogPrintf("TcpipApiCreateConnection atskt is full "); +304128,622940159,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendResponse_3,P_INFO,swLogPrintf("send response to socket handler success "); +304128,622942207,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendResponse_4,P_ERROR,swLogPrintf("send response to socket handler fail "); +304128,622944255,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_1,P_ERROR,swLogPrintf("TcpipApiCreateConnection invalid param "); +304128,622946303,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_2,P_ERROR,swLogPrintf("TcpipApiCreateConnection invalid param "); +304128,622948351,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_3,P_ERROR,swLogPrintf("TcpipApiCreateConnection atskt is full "); +304128,622950399,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_4,P_ERROR,swLogPrintf("TcpipApiCreateConnection invalid address info "); +304128,622950400,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_5,P_ERROR,swLogPrintf("TcpipApiCreateConnection invalid type %d "); +304128,622954495,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_6,P_ERROR,swLogPrintf("TcpipApiCreateConnection create socket fail "); +304128,622956543,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_ul_total_status_1,P_WARNING,swLogPrintf("TcpipApiCreateConnection enable ul total status option fail "); +304128,622958591,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_7,P_ERROR,swLogPrintf("TcpipApiCreateConnection create socket fail "); +304128,622960639,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_8,P_INFO,swLogPrintf("TcpipApiCreateConnection connect success "); +304128,622961152,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_9,P_ERROR,swLogPrintf("TcpipApiCreateConnection request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,622962944,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_10,P_INFO,swLogPrintf("TcpipApiCreateConnection connect is oning , fd %d , current tick %u "); +304128,622966783,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_11,P_ERROR,swLogPrintf("TcpipApiCreateConnection connect fail "); +304128,622967296,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCreateConnection_12,P_ERROR,swLogPrintf("TcpipApiCreateConnection request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,622970879,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_2,P_ERROR,swLogPrintf("TcpipApiSendData request point is null "); +304128,622972927,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_1,P_ERROR,swLogPrintf("TcpipApiSendData invalid param "); +304128,622974975,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_3,P_INFO,swLogPrintf("TcpipApiSendData can not get the socketatcmd "); +304128,622974976,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_4,P_ERROR,swLogPrintf("TcpipApiSendData the seq socket %d is not skapi socket "); +304128,622977024,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_5,P_ERROR,swLogPrintf("TcpipApiSendData the seq socket %d is not connected "); +304128,622979328,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_6,P_WARNING,swLogPrintf("TcpipApiSendData the socket %d sequence %u is reusing "); +304128,622981376,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_7,P_INFO,swLogPrintf("TcpipApiSendData send packet success %u , send total len %u "); +304128,622983680,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_8,P_ERROR,swLogPrintf("TcpipApiSendData request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,622987263,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_9,P_ERROR,swLogPrintf("TcpipApiSendData send fail "); +304128,622989311,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_10,P_ERROR,swLogPrintf("TcpipApiSendData invalid sendLen param "); +304128,622989824,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSendData_12,P_ERROR,swLogPrintf("TcpipApiSendData request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,622993407,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_1,P_ERROR,swLogPrintf("TcpipApiCloseConnection invalid param "); +304128,622995455,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_2,P_ERROR,swLogPrintf("TcpipApiCloseConnection request point is null "); +304128,622997503,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_3,P_INFO,swLogPrintf("TcpipApiCloseConnection can not get the socketatcmd "); +304128,622997504,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_4,P_ERROR,swLogPrintf("TcpipApiCloseConnection socket %d is not ecsoc "); +304128,623001599,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_5,P_INFO,swLogPrintf("TcpipApiCloseConnection close socket success "); +304128,623002112,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_6,P_ERROR,swLogPrintf("TcpipApiCloseConnection request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,623004160,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiCloseConnection_7,P_ERROR,swLogPrintf("AtecSocketHandleConnectReq request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,623007743,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiSendTotalData_1,P_ERROR,swLogPrintf("tcpipApiSendTotalData request point is null "); +304128,623009791,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiSendTotalData_2,P_ERROR,swLogPrintf("tcpipApiSendTotalData invalid param "); +304128,623011839,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiSendTotalData_3,P_INFO,swLogPrintf("tcpipApiSendTotalData can not get the socketatcmd "); +304128,623012352,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiSendTotalData_5,P_ERROR,swLogPrintf("tcpipApiSendTotalData request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,623015935,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiAckedTotalData_1,P_ERROR,swLogPrintf("tcpipApiAckedTotalData request point is null "); +304128,623017983,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiAckedTotalData_2,P_ERROR,swLogPrintf("tcpipApiAckedTotalData invalid param "); +304128,623020031,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiAckedTotalData_3,P_INFO,swLogPrintf("tcpipApiAckedTotalData can not get the socketatcmd "); +304128,623020544,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiAckedTotalData_5,P_ERROR,swLogPrintf("tcpipApiAckedTotalData request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,623024127,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiProessReq_1,P_ERROR,swLogPrintf("TcpipApiProessReq invalid param "); +304128,623026175,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiProessReq_2,P_ERROR,swLogPrintf("TcpipApiProessReq invalid param "); +304128,623026688,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiProessReq_3,P_INFO,swLogPrintf("read tcpipApiReqFd success , req_id %d , reqbody 0x%x , sourcePort %d "); +304128,623028224,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiProessReq_4,P_WARNING,swLogPrintf("process tcpipApi reqeust fail , invalid reqId %d "); +304128,623030272,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiProessReq_5,P_WARNING,swLogPrintf("read tcpipApi fail , source %u check fail "); +304128,623034367,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiStatusEventProcess_1,P_ERROR,swLogPrintf("TcpipApiStatusEventProcess invalid param "); +304128,623034880,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiStatusEventProcess_3,P_ERROR,swLogPrintf("TcpipApiStatusEventProcess request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,623036928,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiStatusEventProcess_4,P_ERROR,swLogPrintf("TcpipApiStatusEventProcess request has timeout , can not send response , reqticks %u , timeout %u , now %u "); +304128,623040511,0,0,PLAT_AP,TCPIP_SDK_API,TcpipDlEventProcess_1,P_ERROR,swLogPrintf("TcpipDlEventProcess callback is invalid "); +304128,623042559,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiSockErrorEventProcess_1,P_ERROR,swLogPrintf("TcpipApiSockErrorEventProcess callback is invalid "); +304128,623044607,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiUlStatusEventProcess_1,P_ERROR,swLogPrintf("TcpipApiUlStatusEventProcess callback is invalid "); +304128,623044864,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiUlStatusEventProcess_2,P_WARNING,swLogPrintf("TcpipApiUlStatusEventProcess the socket %d , sequence %d status invalid "); +304128,623046912,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiUlStatusEventProcess_3,P_WARNING,swLogPrintf("TcpipApiUlStatusEventProcess the socket %d , sequence %d status invalid "); +304128,623048960,0,0,PLAT_AP,TCPIP_SDK_API,tcpipApiUlTotalStatusEventProcess_1,P_INFO,swLogPrintf("tcpipApiUlTotalStatusEventProcess the socket %d , ul total ack len %u "); +304128,623051008,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiEventCallback_1,P_INFO,swLogPrintf("TcpipApiEventCallback socketid %d , event %d "); +304128,623054847,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiStoreConnHibContext_1,P_WARNING,swLogPrintf("TcpipApiStoreConnHibContext context is invalid "); +304128,623055104,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiStoreConnHibContext_2,P_WARNING,swLogPrintf("TcpipApiStoreConnHibContext private hib context len %d bit than %d "); +304128,623058943,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiStoreConnHibContext_3,P_WARNING,swLogPrintf("TcpipApiStoreConnHibContext private context is invalid "); +304128,623060991,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_1,P_WARNING,swLogPrintf("TcpipApiRecoverConnContext context is invalid "); +304128,623061248,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_2,P_WARNING,swLogPrintf("TcpipApiRecoverConnContext private hib context len %d bit than %d "); +304128,623065087,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_3,P_WARNING,swLogPrintf("TcpipApiRecoverConnContext private hib context is invalid "); +304128,623067135,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_4,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext atskt is full "); +304128,623067136,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_5,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext rebuild socket id %d fail "); +304128,623069184,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_6,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext rebuild socket id %d success , but status is not valid "); +304128,623071232,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_7,P_INFO,swLogPrintf("TcpipApiRecoverConnContext rebuild socket id %d success "); +304128,623073280,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_91,P_INFO,swLogPrintf("TcpipApiRecoverConnContext rebuild socket id %d success "); +304128,623075328,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_92,P_INFO,swLogPrintf("TcpipApiRecoverConnContext rebuild socket id %d success "); +304128,623077632,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_11,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext hib socket id %d status %dis invalid "); +304128,623079424,0,0,PLAT_AP,TCPIP_SDK_API,TcpipApiRecoverConnContext_12,P_ERROR,swLogPrintf("TcpipApiRecoverConnContext rebuild socket id %d is invalid "); +305152,624955391,0,0,PLAT_AP,TCPIP_PKG_DUMP,tcpip_ps_ul,P_VALUE,swLogDump("PS UL : "); +305152,624957439,0,0,PLAT_AP,TCPIP_PKG_DUMP,tcpip_ppp_ul,P_VALUE,swLogDump("PPP UL : "); +305152,624959487,0,0,PLAT_AP,TCPIP_PKG_DUMP,tcpip_rndis_ul,P_VALUE,swLogDump("RNDIS UL : "); +305152,624961535,0,0,PLAT_AP,TCPIP_PKG_DUMP,tcpip_ps_dl,P_VALUE,swLogDump("PS DL : "); +305152,624963583,0,0,PLAT_AP,TCPIP_PKG_DUMP,tcpip_ppp_dl,P_VALUE,swLogDump("PPP DL : "); +305152,624965631,0,0,PLAT_AP,TCPIP_PKG_DUMP,tcpip_rndis_dl,P_VALUE,swLogDump("RNDIS DL : "); +306176,627051264,0,0,PLAT_AP,ROHC,RohcCreateRohcChannel_1,P_INFO,swLogPrintf("RohcCreateRohcChannel , cid %u , profile 0x%x , maxcid %u , onlyuplink %u "); +306176,627052544,0,0,PLAT_AP,ROHC,RohcCreateRohcChannel_2,P_WARNING,swLogPrintf("RohcCreateRohcChannel alloc msg buffer fail , cid %u "); +306176,627054592,0,0,PLAT_AP,ROHC,RohcCreateRohcChannel_3,P_WARNING,swLogPrintf("RohcCreateRohcChannel tcpip_callback_with_block fail , cid %u "); +306176,627056640,0,0,PLAT_AP,ROHC,RohcDestroyRohcChannel_1,P_INFO,swLogPrintf("RohcDestroyRohcChannel cid %u "); +306176,627058688,0,0,PLAT_AP,ROHC,RohcDestroyRohcChannel_2,P_WARNING,swLogPrintf("RohcDestroyRohcChannel alloc msg buffer fail , cid %u "); +306176,627060736,0,0,PLAT_AP,ROHC,RohcDestroyRohcChannel_3,P_WARNING,swLogPrintf("RohcDestroyRohcChannel tcpip_callback_with_block fail , cid %u "); +306176,627062784,0,0,PLAT_AP,ROHC,RohcRestRohcChannel_1,P_INFO,swLogPrintf("RohcCreateRohcChannel cid %u "); +306176,627064832,0,0,PLAT_AP,ROHC,RohcRestRohcChannel_2,P_WARNING,swLogPrintf("RohcCreateRohcChannel alloc msg buffer fail , cid %u "); +306176,627066880,0,0,PLAT_AP,ROHC,RohcResetRohcChannel_3,P_WARNING,swLogPrintf("PsifResetRohcCallback tcpip_callback_with_block fail , cid %u "); +306176,627069184,0,0,PLAT_AP,ROHC,RohcReCompDataPdu_1,P_INFO,swLogPrintf("RohcReCompDataPdu cid %u , pdu 0x%x "); +306176,627071232,0,0,PLAT_AP,ROHC,RohcReCompDataPdu_2,P_WARNING,swLogPrintf("RohcReCompDataPdu alloc msg buffer fail , cid %u , pdu 0x%x "); +306176,627073024,0,0,PLAT_AP,ROHC,RohcReCompDataPdu_3,P_WARNING,swLogPrintf("RohcReCompDataPdu tcpip_callback_with_block fail , cid %u "); +313344,641732607,0,0,PLAT_AP,LFS,lfs_bd_flush_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641734655,0,0,PLAT_AP,LFS,lfs_dir_getread_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641734912,0,0,PLAT_AP,LFS,lfs_dir_fetchmatch_0,P_ERROR,swLogPrintf("Corrupted dir pair at %x %x "); +313344,641738751,0,0,PLAT_AP,LFS,lfs_dir_commitcrc_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641740799,0,0,PLAT_AP,LFS,lfs_dir_compact_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641742847,0,0,PLAT_AP,LFS,lfs_dir_compact_1,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641744895,0,0,PLAT_AP,LFS,lfs_dir_compact_2,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641746943,0,0,PLAT_AP,LFS,lfs_dir_compact_3,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641748991,0,0,PLAT_AP,LFS,lfs_dir_compact_4,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641751039,0,0,PLAT_AP,LFS,lfs_dir_compact_5,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641753087,0,0,PLAT_AP,LFS,lfs_ctz_extend_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641755135,0,0,PLAT_AP,LFS,lfs_ctz_extend_1,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641757183,0,0,PLAT_AP,LFS,lfs_ctz_extend_2,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641759231,0,0,PLAT_AP,LFS,lfs_file_opencfg,P_WARNING,swLogPrintf("Can ' t malloc for name field "); +313344,641761279,0,0,PLAT_AP,LFS,lfs_file_relocate_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641763327,0,0,PLAT_AP,LFS,lfs_file_relocate_1,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641765375,0,0,PLAT_AP,LFS,lfs_file_flush_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641767423,0,0,PLAT_AP,LFS,lfs_file_write_0,P_WARNING,swLogPrintf("LFS corrupt detect! "); +313344,641767680,0,0,PLAT_AP,LFS,LFS_Reply_0,P_INFO,swLogPrintf("LFS reply , ret : %d , threadId : %x "); +313344,641769728,0,0,PLAT_AP,LFS,LFS_daemonTaskEntry,P_INFO,swLogPrintf("LFS Daemon task recv a request , type : %d , threadId : %x "); +313344,641771521,0,0,PLAT_AP,LFS,fs_remove,P_DEBUG,swLogPrintf("LFS remove , path : %s "); +313344,641773827,0,0,PLAT_AP,LFS,fs_rename,P_DEBUG,swLogPrintf("LFS rename , old path : %s , new path : %s "); +313344,641775617,0,0,PLAT_AP,LFS,fs_file_open,P_DEBUG,swLogPrintf("LFS file open , path : %s "); +313344,641777665,0,0,PLAT_AP,LFS,fs_file_close,P_DEBUG,swLogPrintf("LFS file close , file name : %s "); +313344,641779713,0,0,PLAT_AP,LFS,fs_file_read,P_DEBUG,swLogPrintf("LFS file read , file name : %s "); +313344,641781761,0,0,PLAT_AP,LFS,fs_file_write,P_DEBUG,swLogPrintf("LFS file write , file name : %s "); +313344,641783809,0,0,PLAT_AP,LFS,fs_file_seek,P_DEBUG,swLogPrintf("LFS file seek , file name : %s "); +313344,641785857,0,0,PLAT_AP,LFS,fs_file_sync,P_DEBUG,swLogPrintf("LFS file sync , file name : %s "); +313344,641787905,0,0,PLAT_AP,LFS,fs_file_truncate,P_DEBUG,swLogPrintf("LFS file truncate , file name : %s "); +313344,641789953,0,0,PLAT_AP,LFS,fs_file_rewind,P_DEBUG,swLogPrintf("LFS file rewind , file name : %s "); +314368,643829759,0,0,PLAT_AP,CEMM,ProcessServiceReject_1,P_WARNING,swLogPrintf("SERVICE REJECT without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643831807,0,0,PLAT_AP,CEMM,ProcessAttachReject_1,P_WARNING,swLogPrintf("ATTACH REJECT without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643833855,0,0,PLAT_AP,CEMM,ProcessAttachReject_2,P_WARNING,swLogPrintf("ATTACH REJECT without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643835903,0,0,PLAT_AP,CEMM,MtDetachRequest_1,P_WARNING,swLogPrintf("MT DETACH without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643837951,0,0,PLAT_AP,CEMM,MtDetachRequest_2,P_WARNING,swLogPrintf("MT DETACH without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643839999,0,0,PLAT_AP,CEMM,ProcessTauchReject_1,P_WARNING,swLogPrintf("TAU REJECT without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643842047,0,0,PLAT_AP,CEMM,ProcessTauchReject_2,P_WARNING,swLogPrintf("TAU REJECT without integrity protection , store the current TAI in the list of ' forbidden tracking areas for roaming ' ! "); +314368,643844095,0,0,PLAT_AP,CEMM,CemmEsmUnitDataRequestMsg_7,P_INFO,swLogPrintf("ESM DATA TRANSPORT message is blocked by T3440 , pending it. "); +316416,648022272,0,0,PLAT_AP,SMS,SearchForTIValue_1,P_VALUE,swLogPrintf("Can ' t found matched TI value %d , TI flag %d "); +316416,648026111,0,0,PLAT_AP,SMS,CesmscmFindEntity_1,P_WARNING,swLogPrintf("Can ' t find free TI value! "); +316416,648026112,0,0,PLAT_AP,SSL,sslListFind_1,P_INFO,swLogPrintf("find the cxtId : %d "); +316416,648028161,0,0,PLAT_AP,SSL,loadFile2Buff_0,P_INFO,swLogPrintf("fail to open such file : %s "); +316416,648030209,0,0,PLAT_AP,SSL,loadFile2Buff_1,P_INFO,swLogPrintf("file : %s "); +316416,648032256,0,0,PLAT_AP,SSL,loadFile2Buff_0_1,P_INFO,swLogPrintf("filesize = %x "); +316416,648034304,0,0,PLAT_AP,SSL,loadFile2Buff_2,P_INFO,swLogPrintf("filesize = %d "); +316416,648038399,0,0,PLAT_AP,SSL,loadFile2Buff_0_2,P_INFO,swLogPrintf("read failed "); +316416,648040447,0,0,PLAT_AP,SSL,sslRestoreSession_0_1,P_INFO,swLogPrintf("can ' t open NVM : ' ssi.nvm ' "); +316416,648042495,0,0,PLAT_AP,SSL,sslRestoreSession_0_2,P_INFO,swLogPrintf("can ' t read header , restore session fail "); +316416,648042496,0,0,PLAT_AP,SSL,sslRestoreSession_1,P_INFO,swLogPrintf("read sslSessionCxt , malloc it = 0x%x "); +316416,648046591,0,0,PLAT_AP,SSL,sslRestoreSession_0_3,P_INFO,swLogPrintf("can ' t read body "); +316416,648048639,0,0,PLAT_AP,SSL,sslSaveSession_0_1,P_INFO,swLogPrintf("can ' t open / create NVM : ssi.nvm , save NVM failed "); +316416,648050687,0,0,PLAT_AP,SSL,sslSaveSession_0_2,P_INFO,swLogPrintf("ssi.nvm , write the file header failed "); +316416,648052735,0,0,PLAT_AP,SSL,sslSaveSession_0_3,P_INFO,swLogPrintf("ssi.nvm , write the file body failed "); +316416,648054783,0,0,PLAT_AP,SSL,sslSaveSession_1,P_INFO,swLogPrintf("ssi.nvm save success "); +317440,650121215,0,0,PLAT_AP,PLA_MIDWARE,mwAonSockInfoChanged_s_1,P_SIG,swLogPrintf("MW AON , socket AON info changed "); +317440,650123263,0,0,PLAT_AP,PLA_MIDWARE,mwAonPsDialInfoChanged_s_1,P_SIG,swLogPrintf("MW AON , PS DIAL AON info changed "); +317440,650125311,0,0,PLAT_AP,PLA_MIDWARE,mwAonSetDefaultAonDnsCfgAndSave_1,P_ERROR,swLogPrintf("MW AON , can not find adpt dns aon "); +317440,650125312,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgAccessLock_e_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t lock the mutex , retErr : %d "); +317440,650127360,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgAccessUnLock_e_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t unlock the mutex , retErr : %d "); +317440,650129408,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmParseParamValue_id_w_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t parse paramId : %d "); +317440,650131712,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmParseParamValue_unkown_param_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t parse paramID : %d , type : %d , ignore it "); +317440,650133505,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmRead_w_1,P_WARNING,swLogPrintf("MW NVM CFG , NVM file : %s , can ' t read , using default value "); +317440,650135809,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmRead_s_1,P_SIG,swLogPrintf("MW NVM CFG , NVM file : %s , read OK , bodySize : %d "); +317440,650137600,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmRead_parse_e_1,P_ERROR,swLogPrintf("MW CFG NVM , get next parameter err : %d "); +317440,650139904,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmRead_rm_w_1,P_WARNING,swLogPrintf("MW CFG NVM , can ' t parse paramId : %d , type : %d , remove this param "); +317440,650143743,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmRead_parse_e_2,P_WARNING,swLogPrintf("MW CFG NVM , parse file error , all param reset to default , and delete NVM file "); +317440,650145791,0,0,PLAT_AP,PLA_MIDWARE,mwCfgNvmRead_rm_w_2,P_WARNING,swLogPrintf("MW CFG NVM , some param removed , need write back to flash "); +317440,650146560,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveParam_input_e_1,P_ERROR,swLogPrintf("MW CFG NVM , save param , input error , paramId : %d , cfgTpe : %d , paramLen : %d , pParamValue : 0x%x "); +317440,650148096,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveParam_input_e_2,P_ERROR,swLogPrintf("MW CFG NVM , save param , input error , paramId : %d , cfgTpe : TV , but paramLen : %d > 2 "); +317440,650150144,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveParam_input_e_3,P_ERROR,swLogPrintf("MW CFG NVM , save param , input error , paramId : %d , cfgTpe : TLV , but paramLen : %d < = 2 "); +317440,650151937,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveParam_read_w_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t read NVM file : %s "); +317440,650154240,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveParam_update_w_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t update / add paramId : %d into NVM buf , retErr : %d "); +317440,650156288,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveParam_write_w_1,P_WARNING,swLogPrintf("MW NVM CFG , can ' t write paramId : %d into NVM file , retErr : %d "); +317440,650160127,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgInit_e_1,P_ERROR,swLogPrintf("MW NVM CFG , can ' t create mutex "); +317440,650160128,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSaveAtChanConfig_e_1,P_ERROR,swLogPrintf("MW NVM CFG , invalid AT chanId : %d , can ' t update AtChanCfg into NVM "); +317440,650162944,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgGetCsmpConfig_1,P_INFO,swLogPrintf("MW NVM CFG , Read CSMP param from NVM , FO : %d , VP : %d , PID : %d , DCS : %d "); +317440,650164736,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgGetCpmsConfig_1,P_INFO,swLogPrintf("MW NVM CFG , Read CPMS param , mem1 : %d , mem2 : %d , mem3 : %d "); +317440,650166784,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgGetCscaConfig_1,P_INFO,swLogPrintf("MW NVM CFG , Read CSCA param , SC address present : %d , Type : %d , Address Len : %d "); +317440,650169344,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgGetCnmiConfig_1,P_INFO,swLogPrintf("MW NVM CFG , Read CNMI param from NVM , mode : %d , mt : %d , bm : %d , ds : %d , bfr : %d "); +317440,650170368,0,0,PLAT_AP,PLA_MIDWARE,mwNvmCfgSetAndSavePowerOnCfun_e_1,P_ERROR,swLogPrintf("MW NVM CFG , invalid power on CFUN : %d , can ' t set "); +317440,650172417,0,0,PLAT_AP,PLA_MIDWARE,mwNvmInfoRead_w_1,P_WARNING,swLogPrintf("MW NVM INFO , NVM file : %s , can ' t read , using default value "); +317440,650175489,0,0,PLAT_AP,PLA_MIDWARE,mwNvmInfoRead_w_2,P_WARNING,swLogPrintf("MW NVM INFO , NVM file : %s , file size not right : %d / %d , or version not right : %d / %d , using default value "); +317440,650178559,0,0,PLAT_AP,PLA_MIDWARE,mwNvmInfoGetPhyDebugAtCmdInfo_w_1,P_WARNING,swLogPrintf("MW NVM INFO , can ' t get PHY debug AT info , as NVM not read "); +317440,650179072,0,0,PLAT_AP,PLA_MIDWARE,mwNvmInfoSetPhyDebugAtCmdInfo_w_1,P_WARNING,swLogPrintf("MW NVM INFO , PHY AY debug info size : %d > bufSize : %d , only could write : %d into NVM "); +317440,650182655,0,0,PLAT_AP,PLA_MIDWARE,mwNvmInfoSetPhyDebugAtCmdInfo_w_2,P_WARNING,swLogPrintf("MW NVM INFO , can ' t set PHY debug AT info , as NVM not read "); +317440,650182657,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsRead_1,P_DEBUG,swLogPrintf("MW NVM SMS , NVM file : %s , can ' t read , using default value "); +317440,650185729,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsRead_2,P_DEBUG,swLogPrintf("MW NVM INFO , NVM file : %s , file size not right : %d / %d , or version not right : %d / %d , using default value "); +317440,650186752,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsGetRecByIndex_1,P_WARNING,swLogPrintf("MW NVM SMS , input invalid index : %d , can ' t get SMS record from NVM "); +317440,650190847,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsGetRecByIndex_2,P_WARNING,swLogPrintf("MW NVM SMS , No memory to get SMS storage information from NVRAM "); +317440,650192895,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsGetRecByIndex_3,P_WARNING,swLogPrintf("MW NVM SMS , Read SMS Storage memory failure! "); +317440,650193152,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsGetRecByIndex_4,P_WARNING,swLogPrintf("MW NVM SMS , index : %d , stored number : %d , there is no SMS message. "); +317440,650194944,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsUpdateAndSaveRecByIndex_1,P_WARNING,swLogPrintf("MW NVM SMS , input invalid index : %d , can ' t update SMS record "); +317440,650199039,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsUpdateAndSaveRecByIndex_2,P_WARNING,swLogPrintf("MW NVM SMS , memory allocate fail when saveing SMS to NVRAM! "); +317440,650201087,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsUpdateAndSaveRecByIndex_3,P_WARNING,swLogPrintf("MW NVM SMS , read SMS Storage memory fail! "); +317440,650201344,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsUpdateAndSaveRecByIndex_4,P_WARNING,swLogPrintf("MW NVM SMS , index : %d , stored number : %d , the specificed stored SMS message record is NULL. "); +317440,650203136,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsUpdateAndSaveRecByIndex_5,P_INFO,swLogPrintf("MW NVM SMS , Updated SMS Record with the index ( %d ) Done and Saved to NVRAM "); +317440,650207231,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsAddAndSaveRec_1,P_WARNING,swLogPrintf("MW NVM SMS , No memory to get SMS storage information from NVRAM "); +317440,650209279,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsAddAndSaveRec_2,P_WARNING,swLogPrintf("MW NVM SMS , Read SMS Storage memory failure , try again ! "); +317440,650211327,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsAddAndSaveRec_3,P_WARNING,swLogPrintf("MW NVM SMS , Read SMS Storage memory failure ! "); +317440,650213375,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsAddAndSaveRec_4,P_WARNING,swLogPrintf("MW NVM SMS , SMS Record Box is full , can ' t add SMS record to NVM "); +317440,650215423,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsAddAndSaveRec_5,P_WARNING,swLogPrintf("MW NVM SMS , SMS Record Box is full , can ' t add SMS record to NVM "); +317440,650215680,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsAddAndSaveRec_6,P_INFO,swLogPrintf("MW NVM SMS , added SMS success , index : %d , stored Counter : %d "); +317440,650217472,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByIndex_1,P_WARNING,swLogPrintf("MW NVM SMS , input invalid index : %d , can ' t delete SMS record from NVM "); +317440,650221567,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByIndex_2,P_WARNING,swLogPrintf("MW NVM SMS , memory allocate failed when get SMS storage information from NVRAM "); +317440,650223615,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByIndex_3,P_WARNING,swLogPrintf("MW NVM SMS , read SMS Storage memory failure ! "); +317440,650223616,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByIndex_4,P_INFO,swLogPrintf("MW NVM SMS , the specificed index : %d SMS record has been Deleted! "); +317440,650225920,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByIndex_5,P_INFO,swLogPrintf("MW NVM SMS , deleted SMS specified index ( %d ) success , SMS stored number : %d "); +317440,650227712,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelRecByStatus_1,P_WARNING,swLogPrintf("MW NVM SMS , input invalid Status : %d , can ' t delete SMS records from NVM "); +317440,650229760,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelRecByStatus_2,P_INFO,swLogPrintf("MW NVM SMS , No need to Deleted : %d , SMS records list is NULL "); +317440,650232064,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelRecByStatus_3,P_INFO,swLogPrintf("MW NVM SMS , Deleted the specified Status SMS done , delete Statu : %d success , remaining SMS number : %d "); +317440,650233856,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByStatus_1,P_WARNING,swLogPrintf("MW NVM SMS , input invalid Status : %d , can ' t delete SMS records from NVM "); +317440,650237951,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByStatus_2,P_WARNING,swLogPrintf("MW NVM SMS , No memory to get SMS storage information from NVRAM "); +317440,650239999,0,0,PLAT_AP,PLA_MIDWARE,mwNvmSmsDelAndSaveRecByStatus_3,P_WARNING,swLogPrintf("MW NVM SMS , Read SMS Storage memory failure ! "); +317440,650242047,0,0,PLAT_AP,PLA_MIDWARE,npiLoadNvmConfig_1,P_ERROR,swLogPrintf("Can ' t open NVM : ' npiconfig.nvm ' , use the defult value "); +317440,650244095,0,0,PLAT_AP,PLA_MIDWARE,npiLoadNvmConfig_2,P_ERROR,swLogPrintf("NPI NVM : ' npiconfig.nvm ' , can ' t read header , use the defult value "); +317440,650244608,0,0,PLAT_AP,PLA_MIDWARE,npiLoadNvmConfig_3,P_ERROR,swLogPrintf("' npiconfig.nvm ' version : %d file body size not right : ( %u / %u ) , use the defult value "); +317440,650248191,0,0,PLAT_AP,PLA_MIDWARE,npiSaveNvmConfig_1,P_ERROR,swLogPrintf("NPI NVM , can ' t open / create NVM : ' npiconfig.nvm ' , save NVM failed "); +317440,650250239,0,0,PLAT_AP,PLA_MIDWARE,npiSaveNvmConfig_2,P_ERROR,swLogPrintf("NPI NVM : ' npiconfig.nvm ' , write the file header failed "); +317440,650252287,0,0,PLAT_AP,PLA_MIDWARE,npiSaveNvmConfig_3,P_ERROR,swLogPrintf("NPI NVM : ' npiconfig.nvm ' , write the file body failed "); +318464,652216320,0,0,PLAT_AP,PLA_APP,CpStatusTask_0,P_VALUE,swLogPrintf("AP : Test task loop-%d "); +318464,652218368,0,0,PLAT_AP,PLA_APP,funcTestGetPinValue_0,P_VALUE,swLogPrintf("WakeupPinValue = %d "); +318464,652222463,0,0,PLAT_AP,PLA_APP,appInit_0,P_VALUE,swLogPrintf("AP : CP Power Off "); +318464,652224511,0,0,PLAT_AP,PLA_APP,appInit_1,P_VALUE,swLogPrintf("AP : CP Power On "); +318464,652226559,0,0,PLAT_AP,PLA_APP,funcTestAPAonReadTimeTest_1,P_VALUE,swLogPrintf("AP : End aon Read Time Test "); +318464,652226816,0,0,PLAT_AP,PLA_APP,hibTimerGlobalCntGet6P25HZ_0,P_VALUE,swLogPrintf("HibTimer : CurHibCnt = %d , HibCntStore = %d "); +318464,652228864,0,0,PLAT_AP,PLA_APP,hibTimerGlobalCntGet6P25HZ_1,P_VALUE,swLogPrintf("HibTimer : Offset = %d , Global Cnt Value = %d "); +318464,652231168,0,0,PLAT_AP,NAS_PLMN,CcmPsCheckAutoSaveDataCounterTimerWakeUpFromDeepSleep_2,P_INFO,swLogPrintf("CCM PS , currHibSC is %d , ExpiredHibSC is %d , Wakeup from deep sleep , Re-Start CCM_PS_AUTO_SAVE_DATA_COUNTER_PERIOD_TIMER with remain seconds : %d "); +318464,652234751,0,0,PLAT_AP,NAS_PLMN,CePlmnCurPlmnSearchDone_5,P_WARNING,swLogPrintf("PLMN , no valid PLMN found , since PLMN is currently blocked "); +318464,652236799,0,0,PLAT_AP,NAS_PLMN,CePlmnDelPhyCellId_1,P_VALUE,swLogPrintf("CE PLMN , cell locked , can ' t delete the PHY cell id "); +318464,652238847,0,0,PLAT_AP,NAS_PLMN,CePlmnDelPhyCellId_2,P_VALUE,swLogPrintf("CE PLMN , delete the PHY cell id "); +318464,652240895,0,0,PLAT_AP,PLA_APP,enter_NMI_handler,P_ERROR,swLogPrintf("WDT timeout!!! Enter NMI Handler!!! "); +318464,652241408,0,0,PLAT_AP,PLA_APP,appSetPinOperationSync_1,P_INFO,swLogPrintf("PIN oper mode %d , pinStrLen %d , newPinStrLen %d "); +323584,662702080,0,0,PLAT_AP,UICC,DecodeSms_1,P_INFO,swLogPrintf("invalid sms status %d , set as free space "); +323584,662704128,0,0,PLAT_AP,UICC,ReadPreferLanguage_1,P_INFO,swLogPrintf("Reset command status : %d as ok. "); +323584,662708223,0,0,PLAT_AP,UICC,UsatProcSendSmRsp_0,P_WARNING,swLogPrintf("ME problem is absent "); +323584,662708480,0,0,PLAT_AP,UICC,UsatProcSendSmRsp_1,P_WARNING,swLogPrintf("abnormal result smsProblemPresent %d smsProblem 0x%x "); +323584,662710272,0,0,PLAT_AP,UICC,UsatProcTimerExpiration_0,P_INFO,swLogPrintf("Check if busy statusWords %x "); +325632,666896384,0,0,PLAT_AP,FOTA,FOTA_INIT_CHKSUM,P_WARNING,swLogPrintf("chksum : unsupported algo ( %d ) ! \n "); +325632,666898432,0,0,PLAT_AP,FOTA,FOTA_CALC_CHKSUM,P_WARNING,swLogPrintf("chksum : unsupported algo ( %d ) ! \n "); +325632,666900736,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_0,P_WARNING,swLogPrintf("clr : invalid zoneId ( %d ) ! max ( %d ) \n "); +325632,666902784,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_1,P_WARNING,swLogPrintf("clr : no fota zone ( %d ) ! bmZoneId ( 0x%x ) \n "); +325632,666904832,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_2,P_WARNING,swLogPrintf("clr zone ( %d ) : offset ( %d ) should be aligned by 4 K! \n "); +325632,666907136,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_3,P_WARNING,swLogPrintf("clr zone ( %d ) : len ( %d ) overflowed! set it with max ( %d ) ! \n "); +325632,666909184,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_4,P_ERROR,swLogPrintf("clr zone ( %d ) : invalid offset ( %d ) ! max ( %d ) \n "); +325632,666911232,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_5,P_ERROR,swLogPrintf("clr zone ( %d ) : error! curr / erase Len ( 0x%x / 0x%x ) invalid! \n "); +325632,666913280,0,0,PLAT_AP,FOTA,FOTA_NVM_CLEAR_6,P_ERROR,swLogPrintf("clr zone ( %d ) : error! currAddr ( 0x%x ) , errno ( %d ) \n "); +325632,666915072,0,0,PLAT_AP,FOTA,FOTA_NVM_WRITE_1,P_WARNING,swLogPrintf("wr : invalid zoneId ( %d ) ! max ( %d ) \n "); +325632,666917120,0,0,PLAT_AP,FOTA,FOTA_NVM_WRITE_2,P_WARNING,swLogPrintf("wr : no fota zone ( %d ) ! bmZoneId ( 0x%x ) \n "); +325632,666919424,0,0,PLAT_AP,FOTA,FOTA_NVM_WRITE_3,P_WARNING,swLogPrintf("wr zone ( %d ) : len ( %d ) overflowed! set it with max ( %d ) ! \n "); +325632,666921472,0,0,PLAT_AP,FOTA,FOTA_NVM_WRITE_4,P_ERROR,swLogPrintf("wr zone ( %d ) : invalid offset ( %d ) ! max ( %d ) \n "); +325632,666923264,0,0,PLAT_AP,FOTA,FOTA_NVM_READ_1,P_WARNING,swLogPrintf("rd : invalid zoneId ( %d ) ! max ( %d ) \n "); +325632,666925312,0,0,PLAT_AP,FOTA,FOTA_NVM_READ_2,P_WARNING,swLogPrintf("rd : no fota zone ( %d ) ! bmZoneId ( 0x%x ) \n "); +325632,666927616,0,0,PLAT_AP,FOTA,FOTA_NVM_READ_3,P_WARNING,swLogPrintf("rd zone ( %d ) : len ( %d ) overflowed! set it with max ( %d ) ! \n "); +325632,666929664,0,0,PLAT_AP,FOTA,FOTA_NVM_READ_4,P_ERROR,swLogPrintf("rd zone ( %d ) : invalid offset ( %d ) ! max ( %d ) \n "); +325632,666933247,0,0,PLAT_AP,FOTA,FOTA_NVM_SET_DFU_0,P_WARNING,swLogPrintf("set DFU : null result ptr! \n "); +325632,666935295,0,0,PLAT_AP,FOTA,FOTA_NVM_SET_DFU_1,P_ERROR,swLogPrintf("set DFU : clear bkup zone failure! \n "); +325632,666935553,0,0,PLAT_AP,FOTA,FOTA_NVM_SET_DFU_2,P_WARNING,swLogPrintf("set DFU : ' %s ' , errno ( %d ) ! \n "); +325632,666939391,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_DFU_0,P_WARNING,swLogPrintf("get DFU : null result ptr! \n "); +325632,666941439,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_DFU_1,P_ERROR,swLogPrintf("get DFU : read bkup zone failure! \n "); +325632,666943487,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_DFU_2,P_INFO,swLogPrintf("get DFU : ' success ' \n "); +325632,666945535,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_DFU_3,P_INFO,swLogPrintf("get DFU : ' failure ' \n "); +325632,666947583,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_DFU_4,P_INFO,swLogPrintf("get DFU : ' no result ' \n "); +325632,666947840,0,0,PLAT_AP,FOTA,FOTA_CHK_DELTA_1,P_SIG,swLogPrintf("delta : not a par! pmagic ( %x%x ) \n "); +325632,666951679,0,0,PLAT_AP,FOTA,FOTA_CHK_DELTA_2,P_ERROR,swLogPrintf("delta : parh non-sha padding cs calc fail! \n "); +325632,666953727,0,0,PLAT_AP,FOTA,FOTA_CHK_DELTA_3,P_ERROR,swLogPrintf("delta : par-pl cs calc fail! \n "); +325632,666955775,0,0,PLAT_AP,FOTA,FOTA_CHK_DELTA_4,P_WARNING,swLogPrintf("delta : unmatched par cs! calc & set as follows : \n "); +325632,666955776,0,0,PLAT_AP,FOTA,FOTA_IS_IDENTICAL_1,P_ERROR,swLogPrintf("image ( %d ) : fw chksum calc fail! \n "); +325632,666957824,0,0,PLAT_AP,FOTA,FOTA_IS_IDENTICAL_2,P_WARNING,swLogPrintf("image ( %d ) : non-identical fw cs! calc & set as follows : \n "); +325632,666959872,0,0,PLAT_AP,FOTA,FOTA_IS_IDENTICAL_3,P_INFO,swLogPrintf("image ( %d ) : base is identical! \n "); +325632,666962176,0,0,PLAT_AP,FOTA,FOTA_CHK_IMAGE_1,P_SIG,swLogPrintf("image : not a * .par! pmagic ( %x%x ) \n "); +325632,666964224,0,0,PLAT_AP,FOTA,FOTA_CHK_IMAGE_2,P_SIG,swLogPrintf("image : * .par len ( %d ) err , maxsize ( %d ) \n "); +325632,666966272,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_SZ_1,P_WARNING,swLogPrintf("get size : invalid zoneId ( %d ) ! max ( %d ) \n "); +325632,666968320,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_SZ_2,P_WARNING,swLogPrintf("get size : no fota zone ( %d ) ! bmZoneId ( 0x%x ) \n "); +325632,666970368,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_HNDL_1,P_WARNING,swLogPrintf("get handle : invalid zoneId ( %d ) ! max ( %d ) \n "); +325632,666972416,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_HNDL_2,P_WARNING,swLogPrintf("get handle : no fota zone ( %d ) ! bmZoneId ( 0x%x ) \n "); +325632,666974464,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_XTRAS_1,P_WARNING,swLogPrintf("get xtras : invalid zoneId ( %d ) ! max ( %d ) \n "); +325632,666976512,0,0,PLAT_AP,FOTA,FOTA_NVM_GET_XTRAS_2,P_WARNING,swLogPrintf("get xtras : no fota zone ( %d ) ! bmZoneId ( 0x%x ) \n "); +325632,666978304,0,0,PLAT_AP,FOTA,FOTA_CONVTO_ZONEID,P_WARNING,swLogPrintf("undef fwAttr ( %d ) ! \n "); +325632,666980352,0,0,PLAT_AP,FOTA,FOTA_CONVTO_FWATTR,P_WARNING,swLogPrintf("invalid zoneId ( %d ) ! \n "); +325632,666982400,0,0,PLAT_AP,FOTA,FOTA_CHKSUM_FLASH_1,P_WARNING,swLogPrintf("error! non-last data , not aligned by %d bytes! \n "); +325632,666984448,0,0,PLAT_AP,FOTA,FOTA_CHKSUM_FLASH_2,P_ERROR,swLogPrintf("sha256sum : alloc buffer ( %d ) failure! \n "); +325632,666986496,0,0,PLAT_AP,FOTA,FOTA_CHKSUM_FLASH_3,P_WARNING,swLogPrintf("zid ( %d ) flash read failure! \n "); +325632,666988544,0,0,PLAT_AP,FOTA,FOTA_CHKSUM_FLASH_4,P_ERROR,swLogPrintf("zid ( %d ) flash cs-calc fail! \n "); +325632,666990592,0,0,PLAT_AP,FOTA,FOTA_DUMP_OCTETS_1,P_INFO,swLogPrintf("total length ( %d ) : \n "); +325632,666993156,0,0,PLAT_AP,FOTA,FOTA_DUMP_OCTETS_2,P_INFO,swLogPrintf("[ %d / %d ] %s \n "); +325632,666995204,0,0,PLAT_AP,FOTA,FOTA_DUMP_OCTETS_3,P_INFO,swLogPrintf("[ %d / %d ] %s \n "); +334848,685772799,0,0,PLAT_AP,CCM_REG,CcmRegProcCemmrNwServiceStatusIndSig_2,P_SIG,swLogPrintf("CCM REG , UE is OUT OF SERVICE "); +336896,689965312,0,0,PLAT_AP,CCM_PS,CcmPsCheckAutoSaveDataCounterTimerWakeUpFromDeepSleep_1,P_INFO,swLogPrintf("CCM PS , currHibSC is %d , ExpiredHibSC is %d , CCM_PS_AUTO_SAVE_DATA_COUNTER_PERIOD_TIMER had expired under deep sleep , need to save into nvm! "); +337920,692064255,0,0,PLAT_AP,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_7,P_WARNING,swLogPrintf("CCM SMS , CcmSmsGetUserDatafromPdu return wrong "); +337920,692064256,0,0,PLAT_AP,CCM_SMS,CcmSmsPduDecodeUDH_warn_1,P_WARNING,swLogPrintf("UDH_IEI : %d is not support "); +337920,692066560,0,0,PLAT_AP,CCM_SMS,CcmSmsCheckMoreMsgSend_1,P_INFO,swLogPrintf("enable TEMP_MORE_MESSAGE_SEND for concatenated SMS , seqNum : %d , maxNum : %d "); +337920,692068608,0,0,PLAT_AP,CCM_SMS,CcmSmsCheckMoreMsgSend_2,P_INFO,swLogPrintf("disable TEMP_MORE_MESSAGE_SEND for concatenated SMS , seqNum : %d , maxNum : %d "); +345088,706744319,0,0,PLAT_AP,CAM_DEV,CacDevGetWifiScanCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_SET_WIFISCAN_REQ ' pending , when process the WifiScan CNF "); +345088,706746367,0,0,PLAT_AP,CAM_DEV,CamDevGetWifiScanCfgCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_WIFISCAN_REQ ' pending , when process the WifiScan Cfg CNF "); +349184,715130880,0,0,PLAT_AP,CAM_SMS,CamSmsCmiSetCscbSettingReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support cscb setting : %d "); +349184,715134975,0,0,PLAT_AP,CAM_SMS,CamSmsCmiSetCscbSettingReqFunc_2,P_WARNING,swLogPrintf("CAM SMS , fail to update the CSCB setting to NVM "); +349184,715137023,0,0,PLAT_AP,CAM_SMS,CamSmsGetCscbSettingCnf_1,P_WARNING,swLogPrintf("CAM SMS , no ' CmiSmsGetCscbSettingReq ' pending , when process the get CscbSetting CNF "); +394240,807405569,0,0,PLAT_CP,PLA_STRING,StackOverflow,P_ERROR,swLogPrintf("\r \n!!!error!!!..task : %s..stack.over.flow!!! \r \n "); +396288,811601919,0,0,PLAT_CP,PLA_DRIVER,ShareInfoGetCpAdcValue_0,P_ERROR,swLogPrintf("Request Read AuxADC when result is invalid! "); +396288,811602176,0,0,PLAT_CP,PLA_DRIVER,CLOCK_clockEnable_1,P_WARNING,swLogPrintf("Clock Enable Failed , id = 0x%x counter = %d "); +396288,811603968,0,0,PLAT_CP,PLA_DRIVER,CLOCK_clockDisable_0,P_WARNING,swLogPrintf("Clock Disable check failed , id = 0x%x "); +396288,811606272,0,0,PLAT_CP,PLA_DRIVER,cpmuTryCPSleep_3,P_VALUE,swLogPrintf("XIC0 0x%x XIC1 0x%x \r \n "); +396288,811608064,0,0,PLAT_CP,PLA_DRIVER,cpmuTranslatePhyInitState_6,P_WARNING,swLogPrintf("Phy Init State Error : wakeupBm = 0x%x "); +396288,811610880,0,0,PLAT_CP,PLA_DRIVER,CAIpcAlone1Isr_1,P_INFO,swLogPrintf("CP RECV IPC ID : 0x%x , msgLen : %d , bFast : %d , gA2CReadAddr_cp_rw = 0x%X "); +396288,811612160,0,0,PLAT_CP,PLA_DRIVER,C2ASendAonIpcMsg_1,P_WARNING,swLogExcep("Warning , Last IPC0 Message not pop out , last msg = 0x%x "); +396288,811616255,0,0,PLAT_CP,PLA_DRIVER,C2ASendAonIpcMsg_2,P_WARNING,swLogExcep("Warning , CP write IPC0 fail "); +396288,811616256,0,0,PLAT_CP,PLA_DRIVER,WaitC2AIpcCnf_0,P_INFO,swLogPrintf("MSG ( id : 0x%X ) send to AP in paging image , wait for response! "); +396288,811618304,0,0,PLAT_CP,PLA_DRIVER,WaitC2AIpcCnf_1,P_INFO,swLogPrintf("MSG response ( id : 0x%X ) received from AP in paging image! "); +396288,811620352,0,0,PLAT_CP,PLA_DRIVER,WaitC2AIpcCnf_2,P_INFO,swLogPrintf("wait in while loop! and msg in aon is 0x%X "); +396288,811622915,0,0,PLAT_CP,PLA_DRIVER,assert_func_1,P_ERROR,swLogPrintf("Assert , expr : %s , file : %s , line : %d \r \n "); +398336,815796223,0,0,PLAT_CP,EXCEP_PRINT,check_excep_func_call_1,P_ERROR,swLogExcep("try to parse exception call stack by address compare! "); +398336,815796224,0,0,PLAT_CP,EXCEP_PRINT,check_excep_func_call_2,P_ERROR,swLogExcep("maybe function address @ 0x%x "); +398336,815800319,0,0,PLAT_CP,EXCEP_PRINT,excepCheckFaultType_1,P_ERROR,swLogExcep("hardfault : casued by vector fetch error! "); +398336,815802367,0,0,PLAT_CP,EXCEP_PRINT,excepCheckFaultType_2,P_ERROR,swLogExcep("hardfault : casued by debug event! "); +398336,815804415,0,0,PLAT_CP,EXCEP_PRINT,mmfault_1,P_ERROR,swLogExcep("mem fault : instruction access violatio "); +398336,815806463,0,0,PLAT_CP,EXCEP_PRINT,mmfault_2,P_ERROR,swLogExcep("mem fault : data access violation "); +398336,815808511,0,0,PLAT_CP,EXCEP_PRINT,mmfault_3,P_ERROR,swLogExcep("mem fault : unstacking error "); +398336,815810559,0,0,PLAT_CP,EXCEP_PRINT,mmfault_4,P_ERROR,swLogExcep("mem fault : stacking error "); +398336,815810560,0,0,PLAT_CP,EXCEP_PRINT,mmfault_5,P_ERROR,swLogExcep("memory manage fault address @ 0x%x "); +398336,815814655,0,0,PLAT_CP,EXCEP_PRINT,busfault_1,P_ERROR,swLogExcep("bus fault : instrunction acess error "); +398336,815816703,0,0,PLAT_CP,EXCEP_PRINT,busfault_2,P_ERROR,swLogExcep("bus fault : precise data acess error "); +398336,815818751,0,0,PLAT_CP,EXCEP_PRINT,busfault_3,P_ERROR,swLogExcep("bus fault : imprecise data acess error "); +398336,815820799,0,0,PLAT_CP,EXCEP_PRINT,busfault_4,P_ERROR,swLogExcep("bus fault : unstacking error "); +398336,815822847,0,0,PLAT_CP,EXCEP_PRINT,busfault_5,P_ERROR,swLogExcep("bus fault : stacking error "); +398336,815822848,0,0,PLAT_CP,EXCEP_PRINT,busfault_6,P_ERROR,swLogExcep("bus fault address @ 0x%x "); +398336,815826943,0,0,PLAT_CP,EXCEP_PRINT,usgaefault_1,P_ERROR,swLogExcep("usage fault : try to execute undefined instruction "); +398336,815828991,0,0,PLAT_CP,EXCEP_PRINT,usgaefault_2,P_ERROR,swLogExcep("usage fault : try to switch to wrong state ( ARM ) "); +398336,815831039,0,0,PLAT_CP,EXCEP_PRINT,usgaefault_3,P_ERROR,swLogExcep("usage fault : execute EXC_RETURN error "); +398336,815833087,0,0,PLAT_CP,EXCEP_PRINT,usgaefault_4,P_ERROR,swLogExcep("usage fault : try to execute coprocessor instruction "); +398336,815835135,0,0,PLAT_CP,EXCEP_PRINT,usgaefault_5,P_ERROR,swLogExcep("usage fault : unaligned access "); +398336,815837183,0,0,PLAT_CP,EXCEP_PRINT,usgaefault_6,P_ERROR,swLogExcep("usage fault : divide by zero "); +398336,815839231,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_1,P_ERROR,swLogExcep("dump regs start : "); +398336,815839232,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_2,P_ERROR,swLogExcep("dump reg : r0 : 0x%x ! "); +398336,815841280,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_3,P_ERROR,swLogExcep("dump reg : r1 : 0x%x ! "); +398336,815843328,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_4,P_ERROR,swLogExcep("dump reg : r2 : 0x%x ! "); +398336,815845376,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_5,P_ERROR,swLogExcep("dump reg : r3 : 0x%x ! "); +398336,815847424,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_6,P_ERROR,swLogExcep("dump reg : r4 : 0x%x ! "); +398336,815849472,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_7,P_ERROR,swLogExcep("dump reg : r5 : 0x%x ! "); +398336,815851520,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_8,P_ERROR,swLogExcep("dump reg : r6 : 0x%x ! "); +398336,815853568,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_9,P_ERROR,swLogExcep("dump reg : r7 : 0x%x ! "); +398336,815855616,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_10,P_ERROR,swLogExcep("dump reg : r8 : 0x%x ! "); +398336,815857664,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_11,P_ERROR,swLogExcep("dump reg : r9 : 0x%x ! "); +398336,815859712,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_12,P_ERROR,swLogExcep("dump reg : r10 : 0x%x ! "); +398336,815861760,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_13,P_ERROR,swLogExcep("dump reg : r11 : 0x%x ! "); +398336,815863808,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_14,P_ERROR,swLogExcep("dump reg : r12 : 0x%x ! "); +398336,815865856,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_15,P_ERROR,swLogExcep("dump reg : sp : 0x%x ! "); +398336,815867904,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_16,P_ERROR,swLogExcep("dump reg : msp : 0x%x ! "); +398336,815869952,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_17,P_ERROR,swLogExcep("dump reg : psp : 0x%x ! "); +398336,815872000,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_18,P_ERROR,swLogExcep("dump reg : lr : 0x%x ! "); +398336,815874048,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_19,P_ERROR,swLogExcep("dump reg : exception pc : 0x%x ! "); +398336,815876096,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_20,P_ERROR,swLogExcep("dump reg : psr : 0x%x ! "); +398336,815878144,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_21,P_ERROR,swLogExcep("dump reg : exc_return : 0x%x ! "); +398336,815880192,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_22,P_ERROR,swLogExcep("dump reg BASEPRI : 0x%x ! "); +398336,815882240,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_23,P_ERROR,swLogExcep("dump reg PRIMASK : 0x%x ! "); +398336,815884288,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_24,P_ERROR,swLogExcep("dump reg FAULTMASK : 0x%x ! "); +398336,815886336,0,0,PLAT_CP,EXCEP_PRINT,stack_frame_25,P_ERROR,swLogExcep("dump reg CONTROL : 0x%x ! "); +398336,815890431,0,0,PLAT_CP,EXCEP_PRINT,hardfault_enter1,P_ERROR,swLogExcep("CP hard fault triggered!! "); +398336,815890688,0,0,PLAT_CP,EXCEP_PRINT,excepHardFaultHandler_3,P_WARNING,swLogExcep("CP : Min of max free block in histroy : [ %d , %d ) "); +398336,815892992,0,0,PLAT_CP,EXCEP_PRINT,excepHardFaultHandler_4,P_WARNING,swLogExcep("CP : Current max free block size : %d in [ %d , %d ) "); +398336,815894529,0,0,PLAT_CP,EXCEP_PRINT,exception_task,P_ERROR,swLogExcep("hardfault task : %s "); +398336,815896577,0,0,PLAT_CP,EXCEP_PRINT,unilogAssertInfo_1,P_ERROR,swLogExcep("ASSERT , FUNC : %s "); +398336,815898625,0,0,PLAT_CP,EXCEP_PRINT,unilogAssertInfo_2,P_ERROR,swLogExcep("ASSERT , FILE : %s "); +398336,815901440,0,0,PLAT_CP,EXCEP_PRINT,unilogAssertInfo_3,P_ERROR,swLogExcep("ASSERT line : %d , val is 0x%x , 0x%x , 0x%x "); +398336,815903232,0,0,PLAT_CP,EXCEP_PRINT,ecAssert_CP_0,P_ERROR,swLogExcep("CP assert triggered!!SP = 0x%x , PSP = 0x%x , MSP = 0x%x "); +398336,815904769,0,0,PLAT_CP,EXCEP_PRINT,ecAssert_CP_1,P_ERROR,swLogExcep("Assert INFO : %s "); +398336,815907072,0,0,PLAT_CP,EXCEP_PRINT,ecAssert_CP_001,P_WARNING,swLogExcep("CP : Min of max free block in histroy : [ %d , %d ) "); +398336,815909376,0,0,PLAT_CP,EXCEP_PRINT,ecAssert_CP_002,P_WARNING,swLogExcep("CP : Current max free block size : %d in [ %d , %d ) "); +398336,815910913,0,0,PLAT_CP,EXCEP_PRINT,ecAssert_CP_2,P_ERROR,swLogExcep("assert in : %s "); +399360,817892353,0,0,PLAT_CP,OSA,OsaCheckDebugFalse_e_1,P_ERROR,swLogPrintf("Debug Error , func : %s , line : %d , ( 0x%x , 0x%x , 0x%x ) "); +400384,819988736,0,0,PLAT_CP,PMU,cpmuSaveWakeupSrc_4,P_VALUE,swLogPrintf("CPmu : Recover Wakeup_type from Hw = 0x%x , bootFlag = %d "); +400384,819992575,0,0,PLAT_CP,PMU,cpmuHasIPCInt_1,P_VALUE,swLogPrintf("CP has IPC1 Int Pending in SmallImg "); +400384,819994623,0,0,PLAT_CP,PMU,cpmuTryCPSleep_1,P_VALUE,swLogPrintf("CP : Go DeepSleep "); +400384,819994880,0,0,PLAT_CP,PMU,cpmuTryCPSleep_2,P_WARNING,swLogPrintf("CP : Sleep Failed , NVIC ISPR 0x%x ICSR 0x%x \r \n "); +400384,819996928,0,0,PLAT_CP,PMU,cpmuInit1,P_INFO,swLogPrintf("cp share : 0x%x , len : 0x%x \r \n "); +400384,819998720,0,0,PLAT_CP,PMU,excepCPEnterLoop_1,P_ERROR,swLogExcep("AP Dump , CP enter exception loop , reason = %e "); +400384,820000768,0,0,PLAT_CP,PMU,testTask_1,P_VALUE,swLogPrintf("CP : Test task loop-%d "); +400384,820002816,0,0,PLAT_CP,PMU,cp_main_01,P_WARNING,swLogPrintf("CP found unexpected reset , Reset Src = 0x%x "); +400384,820005376,0,0,PLAT_CP,PMU,cp_main_1,P_VALUE,swLogPrintf("CP Wakeup Bitmap ( 0 : sw 1 : rt ; 2 : bc 3 -5 : ipc ) = 0x%x , CP Actual Sleep State = %e , Pending ipc1 = %d "); +400384,820007424,0,0,PLAT_CP,PMU,cp_main_2,P_VALUE,swLogPrintf("CP Power On IPC NVIC Status , ipc0 = %d , ipc1 = %d , CurSc = %d "); +400384,820011007,0,0,PLAT_CP,PMU,cp_main_3,P_INFO,swLogPrintf("Cp Sleep in paging Img "); +400384,820011776,0,0,PLAT_CP,PMU,cp_main_4,P_SIG,swLogPrintf("CP : Transfer to FullImage , ipc1 Int = %d , IPCPending = ( %d , %d ) , cp Need FullImage = %d "); +449536,920653823,0,0,PLAT_CP,PLA_APP,enter_NMI_handler,P_ERROR,swLogPrintf("WDT timeout!!! Enter NMI Handler!!! "); +524288,1073745919,0,0,PS1,PS_DUMP,CerrcCheckIfBandSupported_list,P_INFO,swLogDump("Supported Band List : "); +524288,1073747967,0,0,PS1,PS_DUMP,CerrcUpdateSimInfo_imsi,P_INFO,swLogDump("IMSI : "); +524288,1073750015,0,0,PS1,PS_DUMP,CerrcPrintBcchDlSchMsg_SIB2_else,P_INFO,swLogDump("SIB2 : "); +524288,1073752063,0,0,PS1,PS_DUMP,CerrcPrintBcchDlSchMsg_SIB3_else,P_INFO,swLogDump("SIB3 : "); +524288,1073754111,0,0,PS1,PS_DUMP,CerrcPrintBcchDlSchMsg_SIB4_else,P_INFO,swLogDump("SIB4 : "); +524288,1073756159,0,0,PS1,PS_DUMP,CerrcPrintBcchDlSchMsg_SIB5_else,P_INFO,swLogDump("SIB5 : "); +524288,1073758207,0,0,PS1,PS_DUMP,CerrcPrintBcchDlSchMsg_SIB14_else,P_INFO,swLogDump("SIB14 : "); +524288,1073760255,0,0,PS1,PS_DUMP,CerrcPrintBcchDlSchMsg_SIB16_else,P_INFO,swLogDump("SIB16 : "); +524288,1073762303,0,0,PS1,PS_DUMP,CerrcDeriveKeNB_Kasme,P_INFO,swLogDump("Kasme ( 256 -bit ) : "); +524288,1073764351,0,0,PS1,PS_DUMP,CerrcDeriveKeNB_ulCount,P_INFO,swLogDump("NAS UL COUNT ( 32 -bit ) : "); +524288,1073766399,0,0,PS1,PS_DUMP,CerrcDeriveKeNB_KeNB,P_INFO,swLogDump("KeNB ( 256 -bit ) : "); +524288,1073768447,0,0,PS1,PS_DUMP,CerrcDeriveAsKey_asKey,P_INFO,swLogDump("AS Key ( 128 -bit ) : "); +524288,1073770495,0,0,PS1,PS_DUMP,CerrcSyncNH_KeNBInit,P_INFO,swLogDump("KeNBInitial ( 256 -bit ) : "); +524288,1073772543,0,0,PS1,PS_DUMP,CerrcSyncNH_preNH,P_INFO,swLogDump("Previous NH ( 256 -bit ) : "); +524288,1073774591,0,0,PS1,PS_DUMP,CerrcSyncNH_string,P_INFO,swLogDump("Input String : "); +524288,1073776639,0,0,PS1,PS_DUMP,CerrcSyncNH_syncNH,P_INFO,swLogDump("The sync NH ( 256 -bit ) : "); +524288,1073778687,0,0,PS1,PS_DUMP,CerrcDeriveNewKeNB_input,P_INFO,swLogDump("The input Key ( 256 -bit ) : "); +524288,1073780735,0,0,PS1,PS_DUMP,CerrcDeriveNewKeNB_string,P_INFO,swLogDump("The input String : "); +524288,1073782783,0,0,PS1,PS_DUMP,CerrcDeriveNewKeNB_output,P_INFO,swLogDump("The output KeNB * ( 256 -bit ) : "); +524288,1073784831,0,0,PS1,PS_DUMP,CerrcCalcXmacI_data,P_INFO,swLogDump("The input data : "); +524288,1073786879,0,0,PS1,PS_DUMP,CerrcCalcXmacI_key,P_INFO,swLogDump("The KRRCint ( 128 -bit ) : "); +524288,1073788927,0,0,PS1,PS_DUMP,CerrcCalcXmacI_xMacIArray,P_INFO,swLogDump("The xMacIArray ( 32 -bit ) : "); +524288,1073790975,0,0,PS1,PS_DUMP,CerrcDlPduSoftEeaThenEia_input,P_INFO,swLogDump("The input data : "); +524288,1073793023,0,0,PS1,PS_DUMP,CerrcDlPduSoftEeaThenEia_output,P_INFO,swLogDump("The output data : "); +524288,1073795071,0,0,PS1,PS_DUMP,CamSimCmiSimRestrictedAccessReqFunc_0,P_VALUE,swLogDump("CmiSimRestrictedAccessReq : "); +524288,1073797119,0,0,PS1,PS_DUMP,CamSimCmiSimGenLogicalChAccessReqFunc_0,P_VALUE,swLogDump("CmiSimGenLogicalChannelAccessReq : "); +524288,1073799167,0,0,PS1,PS_DUMP,CamSimCmiSimGenLogicalChAccessCnfFunc_2,P_VALUE,swLogDump("CmiSimGenLogicalChannelAccessCnf : "); +524288,1073801215,0,0,PS1,PS_DUMP,RandomizeDownlinkEmmMessage_2,P_INFO,swLogDumpPolling("Original DL PDU is : "); +524288,1073803263,0,0,PS1,PS_DUMP,RandomizeDownlinkEmmMessage_4,P_INFO,swLogDumpPolling("Random value is : "); +524288,1073805311,0,0,PS1,PS_DUMP,RandomizeDownlinkEmmMessage_5,P_INFO,swLogDumpPolling("Randomized DL PDU is : "); +524288,1073807359,0,0,PS1,PS_DUMP,NasMessageSecurityCheck_8,P_INFO,swLogDump("decypered data content is : "); +524288,1073809407,0,0,PS1,PS_DUMP,NasMessageSecurityCheck_9,P_INFO,swLogDump("data content is : "); +524288,1073811455,0,0,PS1,PS_DUMP,NasMessageSecurityCheck_10,P_INFO,swLogDump("nasEncKey is : "); +524288,1073813503,0,0,PS1,PS_DUMP,NasMessageSecurityCheck_11,P_INFO,swLogDump("nasIntKey is : "); +524288,1073815551,0,0,PS1,PS_DUMP,NasMessageSecurityCheck_12,P_INFO,swLogDump("DL NAS COUNT is : "); +524288,1073817599,0,0,PS1,PS_DUMP,CemmIsNeedIngoreDlEmmMsg_4,P_INFO,swLogDump("Last Dl Emm Msg Hash Value : "); +524288,1073819647,0,0,PS1,PS_DUMP,CemmIsNeedIngoreDlEmmMsg_5,P_INFO,swLogDump("Current Dl Emm Msg Hash Value : "); +524288,1073821695,0,0,PS1,PS_DUMP,CemmNasMsgInd_5,P_INFO,swLogDumpPolling("cerrcNasMsgInd PDU is : "); +524288,1073823743,0,0,PS1,PS_DUMP,CemmNasMsgInd_7,P_INFO,swLogDumpPolling("NAS DL PDU : "); +524288,1073825791,0,0,PS1,PS_DUMP,CemmSimReady_2,P_INFO,swLogDumpPolling("EFepsloci GUTI is : "); +524288,1073827839,0,0,PS1,PS_DUMP,CesmGetFullIpv6AddrFromNetif_1,P_VALUE,swLogDump("CESM , EPS FULL IPV6 ADDR : "); +524288,1073829887,0,0,PS1,PS_DUMP,CeSmcmProcessMoEstReqData_4,P_INFO,swLogDumpPolling("SMCM send SMS pdu to EMM : "); +524288,1073831935,0,0,PS1,PS_DUMP,CeSmcmSendEmmSmsUnitDataReq_5,P_INFO,swLogPrintf("SMCM SEND CP DATA / ACK / ERROR TO CEMM : "); +524288,1073833983,0,0,PS1,PS_DUMP,SmcmSendSmcmDataIndToSmrl_1,P_INFO,swLogDumpPolling("SMCM send CP DATA / ACK / ERROR to SMRL : "); +524288,1073836031,0,0,PS1,PS_DUMP,SmcmSendSmcmEstIndFromEmmData_1,P_INFO,swLogPrintf("SMCM send MT CP-DATA to SMRL : "); +524288,1073838079,0,0,PS1,PS_DUMP,CemmSmrlSendDataIndtoSmtl_1,P_INFO,swLogPrintf("SMRL SEND MT SMS PDU TO SMTL : "); +524288,1073840127,0,0,PS1,PS_DUMP,CemmSmstlProcCemmSmsSendMessageSig_1,P_INFO,swLogPrintf("SMTL SEND SMS PDU : "); +524288,1073842175,0,0,PS1,PS_DUMP,CemmSmstlProcCemmSmsCommandReqSig_1,P_INFO,swLogPrintf("SMTL SEND SMS PDU : "); +524288,1073844223,0,0,PS1,PS_DUMP,CemmSmstlProcCemmSmsSendSMMASig_1,P_INFO,swLogPrintf("SMTL SEND SMMA "); +524288,1073846271,0,0,PS1,PS_DUMP,UiccCtrlStart3GSession_acl_dump,P_VALUE,swLogDump("CemmsimAppReadyInd pAclRawData : "); +524288,1073848319,0,0,PS1,PS_DUMP,HandleUiccCtrlRecoveryState_iccid1,P_VALUE,swLogDump("current UICC iccid : "); +524288,1073850367,0,0,PS1,PS_DUMP,HandleUiccCtrlRecoveryState_iccid2,P_VALUE,swLogDump("saved tinyCtx iccid : "); +524288,1073852415,0,0,PS1,PS_DUMP,HandleUiccCtrlRecoveryState_imsi1,P_VALUE,swLogDump("current UICC imsi : "); +524288,1073854463,0,0,PS1,PS_DUMP,HandleUiccCtrlRecoveryState_imsi2,P_VALUE,swLogDump("saved tinyCtx imsi : "); +524288,1073856511,0,0,PS1,PS_DUMP,HandleUiccCtrlRecoveryState_epsloci1,P_VALUE,swLogDump("current UICC Epsloci : "); +524288,1073858559,0,0,PS1,PS_DUMP,HandleUiccCtrlRecoveryState_epsloci2,P_VALUE,swLogDump("saved tinyCtx EpsLoci : "); +524288,1073860607,0,0,PS1,PS_DUMP,UsatEncSmsPpDownload_0,P_VALUE,swLogDump("SMS user data : "); +524288,1073862655,0,0,PS1,PS_DUMP,UiccDecodeATRContent_1,P_VALUE,swLogDump("ATR content : "); +524288,1073864703,0,0,PS1,PS_DUMP,UiccPPSProcedure_1,P_VALUE,swLogDump("PPS response : "); +524288,1073866751,0,0,PS1,PS_DUMP,UiccDllDelProcedureByteInRxBuffer_1,P_VALUE,swLogDump("R-TPDU ( del ) : "); +524288,1073868799,0,0,PS1,PS_DUMP,UiccDllSendHandler_2,P_VALUE,swLogDump("C-TPDU : "); +524288,1073870847,0,0,PS1,PS_DUMP,UiccDllSendHandler_3,P_VALUE,swLogDump("C-TPDU : "); +524288,1073872895,0,0,PS1,PS_DUMP,UiccDllSendHandler_4,P_VALUE,swLogDump("PPS request : "); +524288,1073874943,0,0,PS1,PS_DUMP,UiccDllSendHandler_dump,P_VALUE,swLogDump("C-TPDU : "); +524288,1073876991,0,0,PS1,PS_DUMP,UiccTransLayerHandleCmdCase12_softsim_1,P_VALUE,swLogDump("C-TPDU : "); +524288,1073879039,0,0,PS1,PS_DUMP,UiccTransLayerHandleCmdCase12_1,P_VALUE,swLogDump("R-TPDU : "); +524288,1073881087,0,0,PS1,PS_DUMP,UiccTransLayerHandleCmdCase34_softsim_1,P_VALUE,swLogDump("C-TPDU : "); +524288,1073883135,0,0,PS1,PS_DUMP,UiccTransLayerHandleCmdCase34_1,P_VALUE,swLogDump("R-TPDU : "); +524288,1073885183,0,0,PS1,PS_DUMP,UiccTransLayerHandleCmdCase34_softsim_2,P_VALUE,swLogDump("C-TPDU : "); +524288,1073887231,0,0,PS1,PS_DUMP,UiccTransLayerHandleCmdCase34_4,P_VALUE,swLogDump("R-TPDU : "); +524288,1073889279,0,0,PS1,PS_DUMP,UiccPmuDeepSlpEnterCallBack_2,P_INFO,swLogDump("STATUS command response : "); +524288,1073891327,0,0,PS1,PS_DUMP,UiccPmuDeepSlpEnterCallBack_3,P_INFO,swLogDump("STATUS command response : "); +524288,1073893375,0,0,PS1,PS_DUMP,UiccPmuDeepSlpEnterCallBack_4,P_INFO,swLogDump("Select USIM AID ( termiante ) response : "); +524288,1073895423,0,0,PS1,PS_DUMP,UiccPmuDeepSlpEnterCallBack_5,P_INFO,swLogDump("Select USIM AID ( termiante ) response : "); +524288,1073897471,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_1,P_INFO,swLogDump("cmd apdu : "); +524288,1073899519,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_2,P_INFO,swLogDump("response apdu : "); +524288,1073901567,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_3,P_INFO,swLogDump("cmd apdu : "); +524288,1073903615,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_4,P_INFO,swLogDump("response apdu : "); +524288,1073905663,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_5,P_INFO,swLogDump("cmd apdu : "); +524288,1073907711,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_6,P_INFO,swLogDump("response apdu : "); +524288,1073909759,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_7,P_INFO,swLogDump("cmd apdu : "); +524288,1073911807,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_8,P_INFO,swLogDump("response apdu : "); +524288,1073913855,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_9,P_INFO,swLogDump("cmd apdu : "); +524288,1073915903,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_10,P_INFO,swLogDump("response apdu : "); +524288,1073917951,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_11,P_INFO,swLogDump("cmd apdu : "); +524288,1073919999,0,0,PS1,PS_DUMP,UiccVerifyOtherSimAccessCase_12,P_INFO,swLogDump("response apdu : "); +524288,1073922047,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_1,P_INFO,swLogDump("cmd apdu : "); +524288,1073924095,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_2,P_INFO,swLogDump("response apdu : "); +524288,1073926143,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_3,P_INFO,swLogDump("cmd apdu : "); +524288,1073928191,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_4,P_INFO,swLogDump("response apdu : "); +524288,1073930239,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_5,P_INFO,swLogDump("cmd apdu : "); +524288,1073932287,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_6,P_INFO,swLogDump("response apdu : "); +524288,1073934335,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_7,P_INFO,swLogDump("cmd apdu : "); +524288,1073936383,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_8,P_INFO,swLogDump("response apdu : "); +524288,1073938431,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_9,P_INFO,swLogDump("cmd apdu : "); +524288,1073940479,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_10,P_INFO,swLogDump("response apdu : "); +524288,1073942527,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_11,P_INFO,swLogDump("cmd apdu : "); +524288,1073944575,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_12,P_INFO,swLogDump("response apdu : "); +524288,1073946623,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_13,P_INFO,swLogDump("cmd apdu : "); +524288,1073948671,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_14,P_INFO,swLogDump("response apdu : "); +524288,1073950719,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_15,P_INFO,swLogDump("cmd apdu : "); +524288,1073952767,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_16,P_INFO,swLogDump("response apdu : "); +524288,1073954815,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_17,P_INFO,swLogDump("cmd apdu : "); +524288,1073956863,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_18,P_INFO,swLogDump("response apdu : "); +524288,1073958911,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_19,P_INFO,swLogDump("cmd apdu : "); +524288,1073960959,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_20,P_INFO,swLogDump("response apdu : "); +524288,1073963007,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_21,P_INFO,swLogDump("cmd apdu : "); +524288,1073965055,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_22,P_INFO,swLogDump("response apdu : "); +524288,1073967103,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_23,P_INFO,swLogDump("cmd apdu : "); +524288,1073969151,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_24,P_INFO,swLogDump("response apdu : "); +524288,1073971199,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_25,P_INFO,swLogDump("cmd apdu : "); +524288,1073973247,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_26,P_INFO,swLogDump("response apdu : "); +524288,1073975295,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_27,P_INFO,swLogDump("cmd apdu : "); +524288,1073977343,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_28,P_INFO,swLogDump("response apdu : "); +524288,1073979391,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_29,P_INFO,swLogDump("cmd apdu : "); +524288,1073981439,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_30,P_INFO,swLogDump("response apdu : "); +524288,1073983487,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_31,P_INFO,swLogDump("cmd apdu : "); +524288,1073985535,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_32,P_INFO,swLogDump("response apdu : "); +524288,1073987583,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_33,P_INFO,swLogDump("cmd apdu : "); +524288,1073989631,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_34,P_INFO,swLogDump("response apdu : "); +524288,1073991679,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_35,P_INFO,swLogDump("cmd apdu : "); +524288,1073993727,0,0,PS1,PS_DUMP,UiccVerifyUsimAppInitCase_36,P_INFO,swLogDump("response apdu : "); +524288,1073995775,0,0,PS1,PS_DUMP,CatMacDlProcCephyDlDataIndSig_dump_discard,P_INFO,swLogDump("DISCARD MAC DL PDU : "); +524288,1073997823,0,0,PS1,PS_DUMP,CatMacDlProcCephyDlDataIndSig_dump_1,P_INFO,swLogDump("MAC DL PDU : "); +524288,1073999871,0,0,PS1,PS_DUMP,CatMacDlProcCephyDlDataIndSig_dump_2,P_INFO,swLogDump("DISCARD MAC DL PDU : "); +524288,1074001919,0,0,PS1,PS_DUMP,CatMacUlSegPduCheck_1,P_INFO,swLogDump("MAC UL PDU : "); +524288,1074003967,0,0,PS1,PS_DUMP,CerrcBootCheckPagingUeIdentity_wrongImsi,P_INFO,swLogDump("Mismatch UE IMSI : "); +524288,1074006015,0,0,PS1,PS_DUMP,CerrcBootUpDueToPaging_data,P_VALUE,swLogDump("Normal Paging : "); +532480,1090523135,0,0,PS1,LTE_RRC_BCCH_BCH_DUMP,EcommDumpErrcMessage_MIB,P_SIG,swLogDumpPolling("MIB "); +533504,1092620287,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB2,P_SIG,swLogDumpPolling("SIB2 "); +533504,1092622335,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB3,P_SIG,swLogDumpPolling("SIB3 "); +533504,1092624383,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB4,P_SIG,swLogDumpPolling("SIB4 "); +533504,1092626431,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB5,P_SIG,swLogDumpPolling("SIB5 "); +533504,1092628479,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB14,P_SIG,swLogDumpPolling("SIB14 -- EAB parameters "); +533504,1092630527,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB16,P_SIG,swLogDumpPolling("SIB16 -- GPS time and UTC "); +533504,1092632575,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB10,P_SIG,swLogDumpPolling("SIB10 -- ETWS primary notification "); +533504,1092634623,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB11,P_SIG,swLogDumpPolling("SIB11 -- ETWS secondary notification "); +533504,1092636671,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB12,P_SIG,swLogDumpPolling("SIB12 -- CMAS notification "); +533504,1092638719,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB6,P_SIG,swLogDumpPolling("SIB6 -- UTRA cell re-selection information "); +533504,1092640767,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB7,P_SIG,swLogDumpPolling("SIB7 -- GERAN cell re-selection information "); +533504,1092642815,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB8,P_SIG,swLogDumpPolling("SIB8 -- CDMA2000 cell re-selection information "); +533504,1092644863,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB9,P_SIG,swLogDumpPolling("SIB9 -- home eNB name "); +533504,1092646911,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB13,P_SIG,swLogDumpPolling("SIB13 "); +533504,1092648959,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB15,P_SIG,swLogDumpPolling("SIB15 "); +533504,1092651007,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB17,P_SIG,swLogDumpPolling("SIB17 "); +533504,1092653055,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB18,P_SIG,swLogDumpPolling("SIB18 "); +533504,1092655103,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB19,P_SIG,swLogDumpPolling("SIB19 "); +533504,1092657151,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB20,P_SIG,swLogDumpPolling("SIB20 "); +533504,1092659199,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB21,P_SIG,swLogDumpPolling("SIB21 "); +533504,1092661247,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SI,P_SIG,swLogDumpPolling("Unsupported BCCH_Message "); +533504,1092663295,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_SIB1,P_SIG,swLogDumpPolling("SIB1 "); +533504,1092665343,0,0,PS1,LTE_RRC_BCCH_DL_SCH_DUMP,EcommDumpErrcMessage_Bcch,P_SIG,swLogDumpPolling("Invalid BCCH_Message "); +535552,1096814591,0,0,PS1,LTE_RRC_DL_CCCH_DUMP,EcommDumpErrcMessage_Reest,P_SIG,swLogDumpPolling("RrcConnectionReestablishment "); +535552,1096816639,0,0,PS1,LTE_RRC_DL_CCCH_DUMP,EcommDumpErrcMessage_ReestRej,P_SIG,swLogDumpPolling("RrcConnectionReestablishmentReject "); +535552,1096818687,0,0,PS1,LTE_RRC_DL_CCCH_DUMP,EcommDumpErrcMessage_ConnRej,P_SIG,swLogDumpPolling("RrcConnectionReject "); +535552,1096820735,0,0,PS1,LTE_RRC_DL_CCCH_DUMP,EcommDumpErrcMessage_Setup,P_SIG,swLogDumpPolling("RrcConnectionSetup "); +535552,1096822783,0,0,PS1,LTE_RRC_DL_CCCH_DUMP,EcommDumpErrcMessage_DlCcch,P_SIG,swLogDumpPolling("Invalid DL_CCCH_Message "); +536576,1098911743,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_DlTrans,P_SIG,swLogDumpPolling("DlInformationTransfer "); +536576,1098913791,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_Recfg,P_SIG,swLogDumpPolling("RrcConnectionReconfiguration "); +536576,1098915839,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_Rel,P_SIG,swLogDumpPolling("RrcConnectionRelease "); +536576,1098917887,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_SMC,P_SIG,swLogDumpPolling("SecurityModeCommand "); +536576,1098919935,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_Cap,P_SIG,swLogDumpPolling("UeCapabilityEnquiry "); +536576,1098921983,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_Count,P_SIG,swLogDumpPolling("CounterCheck "); +536576,1098924031,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_Rsm,P_SIG,swLogDumpPolling("RrcConnectionResume "); +536576,1098926079,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_UeInfo,P_SIG,swLogDumpPolling("UeInformationRequest "); +536576,1098928127,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_LogMeas,P_SIG,swLogDumpPolling("LoggedMeasurementConfiguration "); +536576,1098930175,0,0,PS1,LTE_RRC_DL_DCCH_DUMP,EcommDumpErrcMessage_DlDcch,P_SIG,swLogDumpPolling("Unsupported DL_DCCH_Message "); +537600,1101008895,0,0,PS1,LTE_RRC_DL_PCCH_DUMP,EcommDumpErrcMessage_Paging,P_VALUE,swLogDumpPolling("Paging "); +537600,1101010943,0,0,PS1,LTE_RRC_DL_PCCH_DUMP,EcommDumpErrcMessage_PagingSig,P_SIG,swLogDumpPolling("Paging "); +539648,1105203199,0,0,PS1,LTE_RRC_UL_CCCH_DUMP,EcommDumpErrcMessage_ReestReq,P_SIG,swLogDumpPolling("RrcConnectionReestablishmentRequest "); +539648,1105205247,0,0,PS1,LTE_RRC_UL_CCCH_DUMP,EcommDumpErrcMessage_ConnReq,P_SIG,swLogDumpPolling("RrcConnectionRequest "); +539648,1105207295,0,0,PS1,LTE_RRC_UL_CCCH_DUMP,EcommDumpErrcMessage_UlCcch,P_SIG,swLogDumpPolling("Invalid UL_CCCH_Message "); +539648,1105209343,0,0,PS1,LTE_RRC_UL_CCCH_DUMP,EcommDumpErrcMessage_RsmReq,P_SIG,swLogDumpPolling("RrcConnectionResumeRequest "); +539648,1105211391,0,0,PS1,LTE_RRC_UL_CCCH_DUMP,EcommDumpErrcMessage_UlCcch2,P_SIG,swLogDumpPolling("Invalid UL_CCCH_Message "); +539648,1105213439,0,0,PS1,LTE_RRC_UL_CCCH_DUMP,EcommDumpErrcMessage_UlCcch1,P_SIG,swLogDumpPolling("Invalid UL_CCCH_Message "); +540672,1107300351,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_MR,P_SIG,swLogDumpPolling("MeasurementReport "); +540672,1107302399,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_RecfgComp,P_SIG,swLogDumpPolling("RrcConnectionReconfigurationComplete "); +540672,1107304447,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_ReestComp,P_SIG,swLogDumpPolling("RrcConnectionReestablishmentComplete "); +540672,1107306495,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_SetupComp,P_SIG,swLogDumpPolling("RrcConnectionSetupComplete "); +540672,1107308543,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_SMComp,P_SIG,swLogDumpPolling("SecurityModeComplete "); +540672,1107310591,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_SMF,P_SIG,swLogDumpPolling("SecurityModeFailure "); +540672,1107312639,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_Cap,P_SIG,swLogDumpPolling("UeCapabilityInformation "); +540672,1107314687,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_UlTrans,P_SIG,swLogDumpPolling("UlInformationTransfer "); +540672,1107316735,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_CountRsp,P_SIG,swLogDumpPolling("CounterCheckResponse "); +540672,1107318783,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_UeInfoRsp,P_SIG,swLogDumpPolling("UeInformationResponse "); +540672,1107320831,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_ProInd,P_SIG,swLogDumpPolling("ProximityIndication "); +540672,1107322879,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_Rstd,P_SIG,swLogDumpPolling("InterFreqRSTDMeasurementIndication "); +540672,1107324927,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_UlDcch,P_SIG,swLogDumpPolling("Unsupported UL_DCCH_Message "); +540672,1107326975,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_RsmComp,P_SIG,swLogDumpPolling("RrcConnectionResumeComplete "); +540672,1107329023,0,0,PS1,LTE_RRC_UL_DCCH_DUMP,EcommDumpErrcMessage_UlDcch2,P_SIG,swLogDumpPolling("Unsupported UL_DCCH_Message "); +541696,1109397503,0,0,PS1,LTE_RRC_VAR_MEASCONFIG_DUMP,EcommDumpErrcMessage_VarMeasConfig,P_VALUE,swLogDumpPolling("VarMeasConfig "); +543744,1113591807,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_1,P_SIG,swLogDumpPolling("Sending ATTACH_REQUEST : "); +543744,1113593855,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_2,P_SIG,swLogDumpPolling("Receiving ATTACH_ACCEPT : "); +543744,1113595903,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_3,P_SIG,swLogDumpPolling("Sending ATTACH_COMPLETE : "); +543744,1113597951,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_4,P_SIG,swLogDumpPolling("Receiving ATTACH_REJECT : "); +543744,1113599999,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_5,P_SIG,swLogDumpPolling("Sending DETACH_REQUEST : "); +543744,1113602047,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_6,P_SIG,swLogDumpPolling("Receiving DETACH_REQUEST : "); +543744,1113604095,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_7,P_SIG,swLogDumpPolling("Sending DETACH_ACCEPT : "); +543744,1113606143,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_8,P_SIG,swLogDumpPolling("Receiving DETACH_ACCEPT : "); +543744,1113608191,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_9,P_SIG,swLogDumpPolling("Sending TA_UPDATE_REQUEST : "); +543744,1113610239,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_10,P_SIG,swLogDumpPolling("Receiving TA_UPDATE_ACCEPT : "); +543744,1113612287,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_11,P_SIG,swLogDumpPolling("Sending TA_UPDATE_COMPLETE : "); +543744,1113614335,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_12,P_SIG,swLogDumpPolling("Receiving TA_UPDATE_REJECT : "); +543744,1113616383,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_13,P_SIG,swLogDumpPolling("Sending EXTENDED_SERVICE_REQUEST : "); +543744,1113618431,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_14,P_SIG,swLogDumpPolling("Sending CONTROL_PLANE_SERVICE_REQUEST : "); +543744,1113620479,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_15,P_SIG,swLogDumpPolling("Receiving SERVICE_REJECT : "); +543744,1113622527,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_16,P_SIG,swLogDumpPolling("Receiving SERVICE_ACCEPT : "); +543744,1113624575,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_17,P_SIG,swLogDumpPolling("Receiving GUTI_REALLOC_COMMAND : "); +543744,1113626623,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_18,P_SIG,swLogDumpPolling("Sending GUTI_REALLOC_COMPLETE : "); +543744,1113628671,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_19,P_SIG,swLogDumpPolling("Receiving AUTHENTICATION_REQUEST : "); +543744,1113630719,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_20,P_SIG,swLogDumpPolling("Sending AUTHENTICATION_RESPONSE : "); +543744,1113632767,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_21,P_SIG,swLogDumpPolling("Receiving AUTHENTICATION_REJECT : "); +543744,1113634815,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_22,P_SIG,swLogDumpPolling("Sending AUTHENTICATION_FAILURE : "); +543744,1113636863,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_23,P_SIG,swLogDumpPolling("Receiving IDENTITY_REQUEST : "); +543744,1113638911,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_24,P_SIG,swLogDumpPolling("Sending IDENTITY_RESPONSE : "); +543744,1113640959,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_25,P_SIG,swLogDumpPolling("Receiving SECURITY_MODE_COMMAND : "); +543744,1113643007,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_26,P_SIG,swLogDumpPolling("Sending SECURITY_MODE_COMPLETE : "); +543744,1113645055,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_27,P_SIG,swLogDumpPolling("Sending SECURITY_MODE_REJECT : "); +543744,1113647103,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_28,P_SIG,swLogDumpPolling("Sending EMM_STATUS : "); +543744,1113649151,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_29,P_SIG,swLogDumpPolling("Receiving EMM_STATUS : "); +543744,1113651199,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_30,P_SIG,swLogDumpPolling("Receiving EMM_INFORMATION : "); +543744,1113653247,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_31,P_SIG,swLogDumpPolling("Receiving DOWNLINK_NAS_TRANSPORT : "); +543744,1113655295,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_32,P_SIG,swLogDumpPolling("Sending UPLINK_NAS_TRANSPORT : "); +543744,1113657343,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_33,P_SIG,swLogDumpPolling("Receiving DOWNLINK_GENERIC_NAS_TRANSPORT : "); +543744,1113659391,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_34,P_SIG,swLogDumpPolling("Sending UPLINK_GENERIC_NAS_TRANSPORT : "); +543744,1113661439,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEmmMessageType_35,P_SIG,swLogDumpPolling("Sending SERVICE_REQUEST : "); +543744,1113663487,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_1,P_SIG,swLogDumpPolling("Receiving ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_REQUEST : "); +543744,1113665535,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_2,P_SIG,swLogDumpPolling("Sending ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_ACCEPT : "); +543744,1113667583,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_3,P_SIG,swLogDumpPolling("Sending ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_REJECT : "); +543744,1113669631,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_4,P_SIG,swLogDumpPolling("Receiving ACTIVATE_DEDICATED_EPS_BEARER_CONTEXT_REQUEST : "); +543744,1113671679,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_5,P_SIG,swLogDumpPolling("Sending ACTIVATE_DEDICATED_EPS_BEARER_CONTEXT_ACCEPT : "); +543744,1113673727,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_6,P_SIG,swLogDumpPolling("Sending ACTIVATE_DEDICATED_EPS_BEARER_CONTEXT_REJECT : "); +543744,1113675775,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_7,P_SIG,swLogDumpPolling("Receiving MODIFY_EPS_BEARER_CONTEXT_REQUEST : "); +543744,1113677823,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_8,P_SIG,swLogDumpPolling("Sending MODIFY_EPS_BEARER_CONTEXT_ACCEPT : "); +543744,1113679871,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_9,P_SIG,swLogDumpPolling("Sending MODIFY_EPS_BEARER_CONTEXT_REJECT : "); +543744,1113681919,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_10,P_SIG,swLogDumpPolling("Receiving DEACTIVATE_EPS_BEARER_CONTEXT_REQUEST : "); +543744,1113683967,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_11,P_SIG,swLogDumpPolling("Sending DEACTIVATE_EPS_BEARER_CONTEXT_ACCEPT : "); +543744,1113686015,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_12,P_SIG,swLogDumpPolling("Sending PDN_CONNECTIVITY_REQUEST : "); +543744,1113688063,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_13,P_SIG,swLogDumpPolling("Receiving PDN_CONNECTIVITY_REJECT : "); +543744,1113690111,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_14,P_SIG,swLogDumpPolling("Sending PDN_DISCONNECT_REQUEST : "); +543744,1113692159,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_15,P_SIG,swLogDumpPolling("Receiving PDN_DISCONNECT_REJECT : "); +543744,1113694207,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_16,P_SIG,swLogDumpPolling("Sending BEARER_RESOURCE_ALLOCATION_REQUEST : "); +543744,1113696255,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_17,P_SIG,swLogDumpPolling("Receiving BEARER_RESOURCE_ALLOCATION_REJECT : "); +543744,1113698303,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_18,P_SIG,swLogDumpPolling("Sending BEARER_RESOURCE_MODIFICATION_REQUEST : "); +543744,1113700351,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_19,P_SIG,swLogDumpPolling("Receiving BEARER_RESOURCE_MODIFICATION_REJECT : "); +543744,1113702399,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_20,P_SIG,swLogDumpPolling("Receiving ESM_INFORMATION_REQUEST : "); +543744,1113704447,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_21,P_SIG,swLogDumpPolling("Sending ESM_INFORMATION_RESPONSE : "); +543744,1113706495,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_22,P_SIG,swLogDumpPolling("Receiving ESM_NOTIFICATION : "); +543744,1113708543,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_23,P_SIG,swLogDumpPolling("Sending ESM_DUMMY_MESSAGE : "); +543744,1113710591,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_24,P_SIG,swLogDumpPolling("Receiving ESM_DUMMY_MESSAGE : "); +543744,1113712639,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_25,P_SIG,swLogDumpPolling("Sending ESM_STATUS : "); +543744,1113714687,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_26,P_SIG,swLogDumpPolling("Receiving ESM_STATUS : "); +543744,1113716735,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_27,P_SIG,swLogDumpPolling("Sending REMOTE_UE_REPORT : "); +543744,1113718783,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_28,P_SIG,swLogDumpPolling("Receiving REMOTE_UE_REPORT_RESPONSE : "); +543744,1113720831,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_29,P_SIG,swLogDumpPolling("Sending ESM_DATA_TRANSPORT : "); +543744,1113722879,0,0,PS1,EPS_PLAIN_DUMP,EcnbDumpEsmMessageType_30,P_SIG,swLogDumpPolling("Receiving ESM_DATA_TRANSPORT : "); +543744,1113724927,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_2,P_SIG,swLogDumpPolling("Receiving CLOSE_UE_TEST_LOOP "); +543744,1113726975,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_4,P_SIG,swLogDumpPolling("Sending CLOSE_UE_TEST_LOOP_COMPLETE "); +543744,1113729023,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_6,P_SIG,swLogDumpPolling("Receiving OPEN_UE_TEST_LOOP "); +543744,1113731071,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_8,P_SIG,swLogDumpPolling("Sending OPEN_UE_TEST_LOOP_COMPLETE "); +543744,1113733119,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_10,P_SIG,swLogDumpPolling("Receiving ACTIVATE_TEST_MODE "); +543744,1113735167,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_12,P_SIG,swLogDumpPolling("Sending ACTIVATE_TEST_MODE_COMPLETE "); +543744,1113737215,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_14,P_SIG,swLogDumpPolling("Receiving DEACTIVATE_TEST_MODE "); +543744,1113739263,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_16,P_SIG,swLogDumpPolling("Sending DEACTIVATE_TEST_MODE_COMPLETE "); +543744,1113741311,0,0,PS1,EPS_PLAIN_DUMP,EcnbTraceTcMessageType_18,P_SIG,swLogDumpPolling("Receiving RESET_UE_POSITIONING_STORED_INFORMATION "); +555008,1136658944,0,0,PS1,PS,PsNvmRead_1,P_WARNING,swLogPrintf("PS NVM , NVM file : %d , file size ( %d ) ! = input buffer size ( %d ) , can ' t read NVM "); +555008,1136660481,0,0,PS1,PS,PsNvmRead_osa_w_1,P_WARNING,swLogPrintf("PS NVM , NVM file : %s , can ' t read , using default value "); +555008,1136663041,0,0,PS1,PS,PsNvmRead_ver_w_1,P_WARNING,swLogPrintf("PS NVM , read NVM file : %s , version in NVM : %d , but curVersion : %d , reset to default value "); +555008,1136665345,0,0,PS1,PS,PsNvmRead_size_w_1,P_WARNING,swLogPrintf("PS NVM , read NVM file : %s , read pBuf : 0x%x , readSize : %d , wantedSize : %d , reset to default value "); +555008,1136667136,0,0,PS1,PS,PsNvmWrite_1,P_ERROR,swLogPrintf("PS NVM , NVM file ID : %d , file size ( %d ) ! = input buffer size ( %d ) , can ' t write NVM "); +555008,1136668929,0,0,PS1,PS,PsNvmSave_1,P_SIG,swLogPrintf("PS NVM , File : %s , id : %d , need to write back to flash "); +555008,1136670976,0,0,PS1,PS,HmacSha256Sct_key_w_1,P_WARNING,swLogPrintf("PS , SHA256 calc HMAC key failed : %d , inputLen : %d "); +555008,1136673024,0,0,PS1,PS,HmacSha256Sct_calc_w_1,P_WARNING,swLogPrintf("PS , HMAX SHA 256 SCT calc failed : %d , inputLen : %d "); +555008,1136675072,0,0,PS1,PS,HmacSha256Sct_calc_w_2,P_WARNING,swLogPrintf("PS , HMAX SHA 256 SCT final calc failed : %d , inputLen : %d "); +555008,1136678911,0,0,PS1,PS,HmacSha256_sct_w_1,P_WARNING,swLogPrintf("PS , can ' t calc HMAC by SCT , try calc by software "); +555008,1136678912,0,0,PS1,PS,PsTftRouteUlPkg_ipver_w_1,P_WARNING,swLogPrintf("PS , invalid ipVer : %d , when check TFT "); +555008,1136681216,0,0,PS1,PS,PsTftRouteUlPkg_ipv4_w_1,P_WARNING,swLogPrintf("PS , pkg length : %d < ipv4 hdr length : %d , maybe segment "); +555008,1136683264,0,0,PS1,PS,PsTftRouteUlPkg_ipv6_w_1,P_WARNING,swLogPrintf("PS , pkg length : %d < ipv6 hdr length : %d , maybe segment "); +555008,1136685568,0,0,PS1,PS,PsTftRouteUlPkg_ip_udp_w_1,P_WARNING,swLogPrintf("PS , pkg length : %d < ip hdr length : %d + udp hdr length : %d , maybe segment "); +555008,1136687616,0,0,PS1,PS,PsTftRouteUlPkg_ip_tcp_w_1,P_WARNING,swLogPrintf("PS , pkg length : %d < ip hdr length : %d + tcp hdr length : %d , maybe segment "); +555008,1136689664,0,0,PS1,PS,PsTftRouteUlPkg_ip_esp_w_1,P_WARNING,swLogPrintf("PS , pkg length : %d < ip hdr length : %d + esp hdr length : %d , maybe segment "); +555008,1136691456,0,0,PS1,PS,PsTftRouteUlPkg_debug_1,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , dir : %d , not for UL "); +555008,1136693504,0,0,PS1,PS,PsTftRouteUlPkg_debug_2,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remote ipv4 , but pkg not IPv4 type : %d "); +555008,1136696320,0,0,PS1,PS,PsTftRouteUlPkg_debug_3,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remote i : %d ipv4 : %d , mask : %d , but pkg ipv4 daddr : %d "); +555008,1136697856,0,0,PS1,PS,PsTftRouteUlPkg_debug_4,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remote iptype : %d , but current pkg not ipv6 : %d "); +555008,1136700416,0,0,PS1,PS,PsTftRouteUlPkg_debug_5,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remote i : %d ipv6 : %d , mask : %d , but pkg ipv6 daddr : %d "); +555008,1136702464,0,0,PS1,PS,PsTftRouteUlPkg_debug_6,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remote i : %d ipv6 : %d , prefixmask : %d , but pkg ipv6 daddr : %d "); +555008,1136704000,0,0,PS1,PS,PsTftRouteUlPkg_debug_7,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , protId : %d , pkg protId : %d "); +555008,1136706304,0,0,PS1,PS,PsTftRouteUlPkg_debug_7_1,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , ipv4 tc : 0x%x , mask : 0x%x , pkg tc : 0x%x "); +555008,1136708352,0,0,PS1,PS,PsTftRouteUlPkg_debug_8,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , ipv6 tc : 0x%x , mask : 0x%x , pkg tc : 0x%x "); +555008,1136710144,0,0,PS1,PS,PsTftRouteUlPkg_debug_9,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , ipv6 FL : 0x%lx , pkg FL : 0x%lx "); +555008,1136712448,0,0,PS1,PS,PsTftRouteUlPkg_debug_10,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , localport : 0x%lx , 0x%lx , UDP pkg sport : 0x%lx "); +555008,1136714496,0,0,PS1,PS,PsTftRouteUlPkg_debug_11,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , localport : 0x%lx , 0x%lx , TCP pkg sport : 0x%lx "); +555008,1136716288,0,0,PS1,PS,PsTftRouteUlPkg_debug_12,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , localport : 0x%lx , 0x%lx , but not UDP / TCP "); +555008,1136718592,0,0,PS1,PS,PsTftRouteUlPkg_debug_13,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remoteport : 0x%lx , 0x%lx , UDP pkg dport : 0x%lx "); +555008,1136720640,0,0,PS1,PS,PsTftRouteUlPkg_debug_14,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remoteport : 0x%lx , 0x%lx , TCP pkg dport : 0x%lx "); +555008,1136722432,0,0,PS1,PS,PsTftRouteUlPkg_debug_15,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , remoteport : 0x%lx , 0x%lx , but not UDP / TCP "); +555008,1136724480,0,0,PS1,PS,PsTftRouteUlPkg_debug_16,P_DEBUG,swLogPrintf("PS , TFT filter evID : %d , ESP SPI : 0x%lx , PKG SPI : 0x%lx "); +555008,1136726016,0,0,PS1,PS,PsTftRouteUlPkg_ip_sec_w_1,P_WARNING,swLogPrintf("PS , TFT IP sec needed , but not support IP Proto : %d "); +555008,1136728064,0,0,PS1,PS,PsTftRouteUlPkg_match_1,P_INFO,swLogPrintf("PS , TFT packet filter matched , UL to CID : %d "); +555008,1136730112,0,0,PS1,PS,PsTftRouteUlPkg_ipv4_def_1,P_INFO,swLogPrintf("PS , no TFT matched , UL to default IPv4 CID : %d "); +555008,1136732160,0,0,PS1,PS,PsTftRouteUlPkg_ipv6_def_1,P_INFO,swLogPrintf("PS , no TFT matched , UL to default IPv6 CID : %d "); +555008,1136736255,0,0,PS1,PS,PsTftRouteUlPkg_discard_1,P_WARNING,swLogPrintf("PS , no TFT matched , and default bearer has TFT , can ' t send this PDU "); +555008,1136736256,0,0,PS1,PS,PsTftRouteUlPkg_ipv6_def_2,P_WARNING,swLogPrintf("PS , no TFT matched , and default bearer has TFT , for safe , UL to default IPv6 CID : %d "); +555008,1136738304,0,0,PS1,PS,PsTftRouteUlPkg_ipv4_def_2,P_WARNING,swLogPrintf("PS , no TFT matched , and default bearer has TFT , for safe , UL to default IPv4 CID : %d "); +555008,1136741120,0,0,PS1,PS,PsUlDataBeOutDate_1,P_WARNING,swLogPrintf("PS , UL PDU out of date , tickType : %d , curtick : 0x%lx , endtick : 0x%lx , bMustDiscard : %d "); +555008,1136744447,0,0,PS1,PS,PsClearUlPendingPduList_1,P_WARNING,swLogPrintf("PS , discard one UL PKG , as out of date "); +555008,1136744960,0,0,PS1,PS,PsClearUlPendingPduList_2,P_WARNING,swLogPrintf("PS , UL only could pending ( %d ) pkg , or ( %d ) bytes , discard one old pkg with len : %d "); +555008,1136746496,0,0,PS1,PS,PsDlPkgAlloc_1,P_WARNING,swLogPrintf("PS DL MEM , want size : %d > MAX ( PS_DL_PKG_MEM_DATA_MAX_SIZE ) , ERROR ! "); +555008,1136748544,0,0,PS1,PS,PsDlPkgAlloc_high_w_1,P_WARNING,swLogPrintf("PS DL MEM , = = = high water : %d = = = "); +555008,1136750848,0,0,PS1,PS,PsDlPkgAlloc_w_2,P_WARNING,swLogPrintf("PS DL MEM , no mem allocated for size : %d , bShort : %d "); +555008,1136752896,0,0,PS1,PS,PsSlp2Malloc_w_1,P_WARNING,swLogPrintf("PS SLP2 HEAP , no memory left , want : %d , left : %d "); +555008,1136754944,0,0,PS1,PS,PsTinyVarAddrInit_lwip_1,P_VALUE,swLogPrintf("TCPIP tiny RAM , used : %d , MAX : %d "); +555008,1136756992,0,0,PS1,PS,PsTinyVarAddrInit_rrc_1,P_VALUE,swLogPrintf("RRC tiny RAM , used : %d , MAX : %d "); +555008,1136759040,0,0,PS1,PS,PsTinyVarAddrInit_ps2_1,P_VALUE,swLogPrintf("PS tiny RAM 2 , used : %d , MAX : %d "); +555008,1136761088,0,0,PS1,PS,PsL1BootVarAddrInit_1,P_VALUE,swLogPrintf("RRC Boot tiny RAM , used : %d , MAX : %d "); +555008,1136763136,0,0,PS1,PS,PsSleep2VarAddrInit_1,P_VALUE,swLogPrintf("RRC Sleep2 RAM , used : %d , MAX : %d "); +555008,1136765184,0,0,PS1,PS,PsL1TinyVarAddrInit_rrc_1,P_VALUE,swLogPrintf("RRCL1 tiny RAM , used : %d , MAX : %d "); +555008,1136767233,0,0,PS1,PS,PsCfgReadUeConfig_w_1,P_WARNING,swLogPrintf("PS NVM CFG , NVM file : %s , can ' t read , retId : %d , using default value "); +555008,1136769281,0,0,PS1,PS,PsCfgReadUeConfig_s_1,P_SIG,swLogPrintf("PS NVM CFG , NVM file : %s , read OK , bodySize : %d "); +556032,1138757631,0,0,PS1,PS_SIG_DUMP,DUMP_SIG_HEADER,P_INFO,swLogDumpPolling("Sig = > "); +556032,1138757888,0,0,PS1,PS_SIG_DUMP,PsRamLogSigDump_1,P_INFO,swLogPrintf("Signal : 0x%lx , is not large : %d > 512 , can ' t dump to RAM log "); +556032,1138761727,0,0,PS1,PS_SIG_DUMP,DUMP_FULL_SIGNAL,P_INFO,swLogDumpPolling("Sig = > "); +557056,1140854783,0,0,PS1,PS_INTER_MSG,DUMP_INTERNAL_MSG,P_INFO,swLogDumpPolling("Msg = > "); +558080,1142950144,0,0,PS1,UP,CatUpProcCephyTimerExpiryIndSig_1,P_VALUE,swLogPrintf("Timer expiry , userId : %d , timerId : 0x%x "); +558080,1142953983,0,0,PS1,UP,CatUpProcCcmSetTrafficIdleMonitorReqSig_1,P_DEBUG,swLogPrintf("Disable traffic idle monitor feature , stop trafficIdleMonitorTimerId. "); +558080,1142955009,0,0,PS1,UP,CatCheck_asset,P_ERROR,swLogPrintf("UP assert , func : %s , line : %d , v1 : 0x%x , v2 : 0x%x , v3 : 0x%x "); +558080,1142958079,0,0,PS1,UP,CeUpTaskEntry_1,P_VALUE,swLogPrintf("UP no RACH , and no LC , could enter HIB state "); +558080,1142960127,0,0,PS1,UP,CeUpTaskEntry_2,P_VALUE,swLogPrintf("UP no RACH , and no LC , could enter SLEEP2 state "); +558080,1142962175,0,0,PS1,UP,CeUpTaskEntry_3,P_VALUE,swLogPrintf("UP cannot enter HIB state "); +558080,1142964223,0,0,PS1,UP,CeUpTaskEntry_4,P_VALUE,swLogPrintf("UP cannot enter SLEEP2 state "); +559104,1145047296,0,0,PS1,MAC,CatMacProcMacMainConfigReqSig_phr_setup,P_INFO,swLogPrintf("CAT MAC , PHR or Extend PHR had been setup / modify : %d , %d "); +559104,1145049344,0,0,PS1,MAC,CatMacProcMacMainConfigReqSig_phr_release,P_INFO,swLogPrintf("CAT MAC , PHR and Extend PHR had been release / invalid : %d , %d "); +559104,1145051392,0,0,PS1,MAC,CatMacProcMacMainConfigReqSig_1,P_INFO,swLogPrintf("CAT MAC , LC SR Prohibit Timer not changed : %d , %d "); +559104,1145053184,0,0,PS1,MAC,CatMacProcMacMainConfigReqSig_2,P_INFO,swLogPrintf("CAT MAC , LC SR Prohibit Timer setup / modify to : %d "); +559104,1145055232,0,0,PS1,MAC,CatMacProcMacMainConfigReqSig_3,P_INFO,swLogPrintf("CAT MAC , LC SR Prohibit Timer release / invalid : %d "); +559104,1145057792,0,0,PS1,MAC,CatMacLcConfigReq_1,P_SIG,swLogPrintf("LC : %d ; priority is changed from %d to %d "); +559104,1145059328,0,0,PS1,MAC,CatMacProcMacResetReqSig_1,P_VALUE,swLogPrintf("CAT MAC RESET , cause : %d "); +559104,1145061632,0,0,PS1,MAC,CatMacProcMacResetCnfSig_1,P_WARNING,swLogPrintf("The lastest mac reset cause : %e , now rcv reset cause : %e , ignore this sig! "); +559104,1145063936,0,0,PS1,MAC,CatMacPhyUlGrantInd_1,P_WARNING,swLogPrintf("CAT MAC , too many UL grant pending , insert index : %d , proc index : %d , just drop grant size : %d "); +559104,1145065472,0,0,PS1,MAC,CatMacDlDecodeMacCeAndSdu_1,P_INFO,swLogPrintf("RCV TA CMD , TA VALUE : %d "); +559104,1145067520,0,0,PS1,MAC,CatMacDlDecodeMacCeAndSdu_2,P_INFO,swLogPrintf("RCV DRX CMD , DRX TYPE : %d "); +559104,1145069568,0,0,PS1,MAC,CatMacDlProcCephyDlDataIndSig_crc_error,P_INFO,swLogPrintf("MAC DL , harqId : %d , crc check error , DISCARD MAC DL PDU! "); +559104,1145071872,0,0,PS1,MAC,CatMacDlProcCephyDlDataIndSig_len_error,P_WARNING,swLogPrintf("MAC DL , harqId : %d , PDU length : %d , check error , discard it!!! "); +559104,1145073664,0,0,PS1,MAC,CatMacDlProcCephyDlDataIndSig_1,P_VALUE,swLogPrintf("DL CCCH PDU , Len : %d "); +559104,1145075968,0,0,PS1,MAC,CatMacDlProcCephyDlDataIndSig_unexpect_ccch_msg,P_WARNING,swLogPrintf("Ra Status is %d , discard this unexpect Dl CCCH Msg with len : %d "); +559104,1145078272,0,0,PS1,MAC,CatMacDlProcCephyDlDataIndSig_2,P_VALUE,swLogPrintf("MAC DL , harqId : %d , one DL RLC PDU , LCID : %d , Len : %d "); +559104,1145079808,0,0,PS1,MAC,CatMacDlProcCephyDlDataIndSig_3,P_WARNING,swLogPrintf("Too many : %d padding MAC PDU ..... "); +559104,1145083903,0,0,PS1,MAC,CatMacRaRandomAccessSucc_1,P_SIG,swLogPrintf("PRACH SUCC "); +559104,1145083904,0,0,PS1,MAC,CatMacRaProcPdcchOrderIndSig_1,P_WARNING,swLogPrintf("Another RACH is ongoing : %d ; ignore this PDCCH ORDER RA "); +559104,1145085952,0,0,PS1,MAC,CatMacRaProcPreambleTransMaxIndSig_1,P_WARNING,swLogPrintf("PRACH MAX Times : %d "); +559104,1145090047,0,0,PS1,MAC,CatMacRaProcRecvRARIndSig_1,P_INFO,swLogPrintf("RAR received ; RA is not CR based ; RA succ... "); +559104,1145092095,0,0,PS1,MAC,CatMacRaProcRecvRARIndSig_2,P_WARNING,swLogPrintf("non-contention based , and grantSize is 0 ! "); +559104,1145094143,0,0,PS1,MAC,CatMacRaProcRachCancelIndSig_1,P_WARNING,swLogPrintf("RACH cannceled by PHY "); +559104,1145094144,0,0,PS1,MAC,CatMacRaRachReq_1,P_SIG,swLogPrintf("Trigger PRACH , cause : %d , CCCH ( 0 ) / PDCCH_ORDER ( 1 ) / HAND_OVER ( 2 ) / UL_DATA ( 3 ) "); +559104,1145096192,0,0,PS1,MAC,CatMacRaCRFailRetryRach_1,P_WARNING,swLogPrintf("RACH CR Failed : %d need to retry RACH "); +559104,1145098240,0,0,PS1,MAC,CatMacUlBeCancelZeroBSR_1,P_INFO,swLogPrintf("CAT MAC UL , Rai Activation is %d , and zero BSR could be sent "); +559104,1145102335,0,0,PS1,MAC,CatMacUlSendSchedulingRequestSig_SR_1,P_INFO,swLogPrintf("MAC UL , scheduling request "); +559104,1145102848,0,0,PS1,MAC,CatMacUlOneLcScheduling_Cut_Bsr,P_VALUE,swLogPrintf("MAC UL , LCID : %d , should Cut Long BSR to Short , grant : %d , BSR grant : %d "); +559104,1145104896,0,0,PS1,MAC,CatMacUlOneLcScheduling_1,P_VALUE,swLogPrintf("MAC UL , LCID : %d , should BSR Cancel , grant : %d , BSR grant : %d "); +559104,1145106944,0,0,PS1,MAC,CatMacUlOneLcScheduling_2,P_VALUE,swLogPrintf("UL LCID : %d , assign grant : %d , total grant : %d "); +559104,1145108480,0,0,PS1,MAC,CatMacUlLcScheduling_1,P_WARNING,swLogPrintf("LC : %d ; is suspened "); +559104,1145110528,0,0,PS1,MAC,CatMacUlLcScheduling_3,P_WARNING,swLogPrintf("LC : %d ; is suspened "); +559104,1145112576,0,0,PS1,MAC,CatMacUlLcScheduling_2,P_WARNING,swLogPrintf("LC : %d ; is suspened "); +559104,1145114880,0,0,PS1,MAC,CatMacUlReConstructCrntiMsg3DataWithDiffGrant_1,P_WARNING,swLogPrintf("Retx msg3 with crnti , grantsize become bigger ( %d -> %d ) , for simplicity , just re-assemble mac hdr! "); +559104,1145116928,0,0,PS1,MAC,CatMacUlReConstructCrntiMsg3DataWithDiffGrant_2,P_WARNING,swLogPrintf("Retx msg3 with crnti , grantsize become smaller ( %d -> %d ) , for simplicity , just re-assemble mac hdr! "); +559104,1145118720,0,0,PS1,MAC,CatMacUlLcDataBecomeAvaiable_suspend,P_ERROR,swLogPrintf("LC : %d is suspend , should not send this data to MAC! "); +559104,1145120768,0,0,PS1,MAC,CatMacUlLcDataBecomeAvaiable_1,P_VALUE,swLogPrintf("BSR had been triggered , no need to trigger BSR on LC : %d again "); +559104,1145122816,0,0,PS1,MAC,CatMacUlLcDataBecomeAvaiable_2,P_WARNING,swLogPrintf("TA expiry , LC : %d , UL data trigger RACH... "); +559104,1145124864,0,0,PS1,MAC,CatMacUlLcDataBecomeAvaiable_3,P_WARNING,swLogPrintf("LC : %d , disable SR triggering for logicalChannelSR-Mask is True! "); +559104,1145127424,0,0,PS1,MAC,CatMacUlProcRetxBsrTimerExpiry_1,P_INFO,swLogPrintf("pendingSr : %d , raStatus : %d , raCause : %d , Another Sr or Rach procedure is ongoing , nothing to do! "); +559104,1145131007,0,0,PS1,MAC,CatMacUlProcPeriodPHRTimerExpiry_1,P_INFO,swLogPrintf("PeriodicPHR-Timer expires , PHR Trigger! "); +559104,1145133055,0,0,PS1,MAC,CatMacUlProcProhibitPHRTimerExpiry_1,P_SIG,swLogPrintf("PHR Trigger! "); +559104,1145133056,0,0,PS1,MAC,CatUpResumeSuspendAllLcExceptSrb1_1,P_VALUE,swLogPrintf("bSuspend : %d , Resume ( 0 ) or Suspend ( 1 ) All Lc Except Srb1 "); +560128,1147144448,0,0,PS1,RLC,CatRlcAmLcSetupConfig_1,P_SIG,swLogPrintf("RLC AM , LCID : %d , pollPdu too large : 0x%x , cut to : 64 "); +560128,1147146496,0,0,PS1,RLC,CatRlcAmLcSetupConfig_2,P_SIG,swLogPrintf("RLC AM , LCID : %d , pollByte too large : 0x%x , cut to : 100 kB "); +560128,1147148288,0,0,PS1,RLC,CatRlcAmLcModifyConfig_1,P_WARNING,swLogPrintf("LC : %d , Some Rlc parameters can ' t be modified , Please Check it! "); +560128,1147150848,0,0,PS1,RLC,CatRlcAmLcModifyConfig_pollPdu,P_WARNING,swLogPrintf("LC : %d , pollPdu has been modified from 0x%x to 0x%x! "); +560128,1147152640,0,0,PS1,RLC,CatRlcAmLcModifyConfig_2,P_SIG,swLogPrintf("RLC AM , LCID : %d , pollPdu too large : 0x%x , cut to : 64 "); +560128,1147154944,0,0,PS1,RLC,CatRlcAmLcModifyConfig_pollByte,P_SIG,swLogPrintf("LC : %d , pollByte has been modified from 0x%x to 0x%x! "); +560128,1147156736,0,0,PS1,RLC,CatRlcAmLcSetupConfig_3,P_SIG,swLogPrintf("RLC AM , LCID : %d , pollByte too large : 0x%x , cut to : 100 kB "); +560128,1147159040,0,0,PS1,RLC,CatRlcAmLcModifyConfig_tPollRetransmit,P_SIG,swLogPrintf("LC : %d , tPollRetransmit has been modified from %d to %d! "); +560128,1147161088,0,0,PS1,RLC,CatRlcAmLcModifyConfig_tReordering,P_SIG,swLogPrintf("LC : %d , tReordering has been modified from %d to %d! "); +560128,1147163136,0,0,PS1,RLC,CatRlcAmLcModifyConfig_tStatusProhibit,P_SIG,swLogPrintf("LC : %d , tStatusProhibit has been modified from %d to %d! "); +560128,1147164672,0,0,PS1,RLC,CatRlcUmBiDirLcModifyConfig_1,P_WARNING,swLogPrintf("LC : %d , Some Rlc parameters can ' t be modified , Please Check it! "); +560128,1147167232,0,0,PS1,RLC,CatRlcUmBiDirLcModifyConfig_tReordering,P_WARNING,swLogPrintf("LC : %d , tReordering has been modified from %d to %d! "); +560128,1147168768,0,0,PS1,RLC,CatRlcUmUniDirDlLcModifyConfig_1,P_WARNING,swLogPrintf("LC : %d , Some Rlc parameters can ' t be modified , Please Check it! "); +560128,1147171328,0,0,PS1,RLC,CatRlcUmUniDirDlLcModifyConfig_tReordering,P_WARNING,swLogPrintf("LC : %d , tReordering has been modified from %d to %d! "); +560128,1147173120,0,0,PS1,RLC,CatRlcLcConfigReq_0,P_ERROR,swLogPrintf("CAT RLC , rlc mode : %d can ' t config for SRB : %d , pls check! "); +560128,1147174912,0,0,PS1,RLC,CatRlcLcConfigReq_1,P_SIG,swLogPrintf("LC : %d , Nw Modify Rlc Configuration! "); +560128,1147176960,0,0,PS1,RLC,CatRlcLcConfigReq_2,P_WARNING,swLogPrintf("LC : %d , should not modify Rlc mode , Please Check it! "); +560128,1147179264,0,0,PS1,RLC,CatRlcLcConfigReq_3,P_WARNING,swLogPrintf("LC : %d , Rlc Mode : %d , not support modify Rlc parameters , Please Check it! "); +560128,1147183103,0,0,PS1,RLC,CatRlcAllLcReleaseInd_1,P_WARNING,swLogPrintf("ALL LC released ; but CONN_REL_ACKED_TIMER still running ; stop it "); +560128,1147185151,0,0,PS1,RLC,CatRlcAllLcReleaseInd_2,P_WARNING,swLogPrintf("ALL LC released ; but CONN_REL_ACK_SENT_TIMER still running ; stop it "); +560128,1147187199,0,0,PS1,RLC,CatRlcAllLcReleaseInd_3,P_VALUE,swLogPrintf("RLC aLL LC released "); +560128,1147187200,0,0,PS1,RLC,CatRlcProcDlRlcPduInd_1,P_ERROR,swLogPrintf("RLC UM LC : %d , only config ul mode , can ' t receive dl data , discard it!!! "); +560128,1147191295,0,0,PS1,RLC,CatRlcProcGrantInd_1,P_VALUE,swLogPrintf("RLC STATUS RPT for RrcConnectionRelease sent in this grant "); +560128,1147191808,0,0,PS1,RLC,CatRlcProcTimerExpiry_0,P_ERROR,swLogPrintf("AM RLC timer : 0x%x expiry ; LCID : %d ; timer Id : %d ; can ' t find the LC context , maybe released by nw "); +560128,1147193856,0,0,PS1,RLC,CatRlcProcTimerExpiry_1,P_ERROR,swLogPrintf("AM RLC timer : 0x%x expiry ; LCID : %d ; timer Id : %d ; can ' t find the LC context "); +560128,1147195904,0,0,PS1,RLC,CatRlcProcTimerExpiry_2,P_ERROR,swLogPrintf("UM RLC timer : 0x%x expiry ; LCID : %d ; timer Id : %d ; can ' t find the LC context "); +560128,1147197440,0,0,PS1,RLC,CatRlcProcConnectReleaseAckReqSig_1,P_INFO,swLogPrintf("LCID : %d , still has UL STATUS pending , start the release ack timer "); +560128,1147199488,0,0,PS1,RLC,CatRlcProcConnectReleaseAckReqSig_2,P_INFO,swLogPrintf("LCID : %d , CONN REL ACK STATUS PDU sent , waiting for UL HARQ transmit ind "); +560128,1147203583,0,0,PS1,RLC,CatRlcOperaAfterUlGrant_1,P_VALUE,swLogPrintf("RRC RELEASE has been ACKed "); +560128,1147203840,0,0,PS1,RLC,CatRlcProcPdcpStatusReport_e_1,P_ERROR,swLogPrintf("RLC , lcid : %d , is not AM mode : %d , can ' t proc PDCP status report "); +560128,1147205632,0,0,PS1,RLC,CatRlcAmAllocDlPduInfoMem_1,P_ERROR,swLogPrintf("AM UL , no pool mem for RLC DL PDU block , more than : %d , need to abort connection "); +560128,1147207680,0,0,PS1,RLC,CatRlcAmAllocDlSegInfoMem_1,P_ERROR,swLogPrintf("AM UL , no pool mem for RLC DL SEG block , more than : %d , need to abort connection "); +560128,1147210240,0,0,PS1,RLC,CatRlcAmDiscardDlPdu_1,P_WARNING,swLogPrintf("LC : %d , DL AM PDU SN : %d , pBit : %d , need to discard "); +560128,1147213823,0,0,PS1,RLC,CatRlcAmDiscardDlPdu_2,P_WARNING,swLogPrintf("DL AM , discard PDU , and status report need "); +560128,1147213824,0,0,PS1,RLC,CatRlcAmDecodeDlStatusPdu_1,P_WARNING,swLogPrintf("AM DL , status PDU length too short : %d , invalid PDU "); +560128,1147216128,0,0,PS1,RLC,CatRlcAmDecodeDlStatusPdu_ackSn,P_INFO,swLogPrintf("AM DL , LC : %d , RECV STATUS REPORT , ACK SN : %d "); +560128,1147218688,0,0,PS1,RLC,CatRlcAmDecodeDlStatusPdu_invalid_ackSn,P_ERROR,swLogPrintf("AM , LC : %d , received a invalid ackSn : %d , not in range : VTA : %d ~ VTMS : %d "); +560128,1147220480,0,0,PS1,RLC,CatRlcAmDecodeDlStatusPdu_4,P_WARNING,swLogPrintf("AM DL , LC : %d , E1 : 1 , but total PDU len : %d < required : %d / 8 "); +560128,1147222528,0,0,PS1,RLC,CatRlcAmDecodeDlStatusPdu_5,P_WARNING,swLogPrintf("AM DL , LC : %d , E2 : 1 , but total PDU len : %d < required : %d / 8 "); +560128,1147225088,0,0,PS1,RLC,CatRlcAmDecodeDlStatusPdu_6,P_INFO,swLogPrintf("AM DL , LC : %d , RECV STATUS REPORT , ACK SN : %d , NACK SN : %d , soStart : %d , soEnd : %d "); +560128,1147226112,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_error_LI_0,P_ERROR,swLogPrintf("CAT RLC , AM DL , The LI value should not be 0 , segIndex : %d "); +560128,1147228416,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_odd_w_1,P_WARNING,swLogPrintf("CAT RLC , AM DL , invalid ODD LI header , leftLen : %d , pduLen : %d "); +560128,1147230208,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_error_LI_1,P_ERROR,swLogPrintf("CAT RLC , AM DL , The LI value should not be 0 , segIndex : %d "); +560128,1147232512,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_even_w_1,P_WARNING,swLogPrintf("CAT RLC , AM DL , invalid EVEN LI header , leftLen : %d , pduLen : %d "); +560128,1147236351,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_even_3,P_INFO,swLogPrintf("CAT RLC , AM DL , EVEN LI headers , no more LI left "); +560128,1147238399,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_odd_4,P_INFO,swLogPrintf("CAT RLC , AM DL , ODD LI headers , no more LI left "); +560128,1147238400,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_error_LI_2,P_ERROR,swLogPrintf("CAT RLC , AM DL , The LI value should not be 0 , segIndex : %d "); +560128,1147240704,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_extli_1,P_WARNING,swLogPrintf("CAT RLC , AM DL , extended LI , leftLen : %d , pduLen : %d "); +560128,1147244543,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_extli_2,P_INFO,swLogPrintf("CAT RLC , AM DL , extended LI , no more LI left "); +560128,1147244800,0,0,PS1,RLC,CatRlcAmDecodeLiHeader_w_1,P_WARNING,swLogPrintf("CAT RLC , AM DL , invalid LI header , left Len : %d , or too much LI headers : %d "); +560128,1147248639,0,0,PS1,RLC,CatRlcAmDecodeDlWholePdu_li_w_1,P_WARNING,swLogPrintf("CAT RLC , AM DL , invalid LI header field "); +560128,1147249408,0,0,PS1,RLC,CatRlcAmMergeContSegPdu_w_1,P_WARNING,swLogPrintf("RLC AM DL , curSeg soStart : %d , soEnd : %d is last , but a nextSeg soStart : %d , soEnd : %d still followed , discard next seg "); +560128,1147252735,0,0,PS1,RLC,CatRlcAmParseUsefulPartFromSegPduData_mem_1,P_WARNING,swLogPrintf("AM DL , no pool mem left , to store : CatRlcAmDlSegList "); +560128,1147252992,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_1,P_WARNING,swLogPrintf("AM DL , this RLC SEG data partly reported to PDCP , and new SEG data all received before , parseSoEnd : %d , oldSoEnd : %d "); +560128,1147256831,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_2,P_WARNING,swLogPrintf("AM DL , NW IS WRONG , the discard SEG is the last SEG "); +560128,1147257088,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_part_w_1,P_WARNING,swLogPrintf("AM DL , decode seg part failed : %d , curPduAddIdx : %d "); +560128,1147259648,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_done_1,P_INFO,swLogPrintf("AM DL , new RLC SEG PDU : soStart ( %d ) ~ soEnd ( %d ) , all insert before OLD SEG : soStart ( %d ) ~ soEnd ( %d ) "); +560128,1147261696,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_dup_1,P_WARNING,swLogPrintf("AM DL , new RECV SEG , soStart : %d - soEnd : %d , already RECV before , OLD SoStart : %d - soEnd : %d "); +560128,1147265023,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_dup_w_1,P_WARNING,swLogPrintf("AM DL , NW IS WRONG , all SEG RECV before , but not the LSF "); +560128,1147265280,0,0,PS1,RLC,CatRlcAmDecodeSegPduDataPart_part_w_2,P_WARNING,swLogPrintf("AM DL , decode last seg part failed : %d , curPduAddIdx : %d "); +560128,1147267072,0,0,PS1,RLC,CatRlcAmDecodeDlSegPdu_li_1,P_WARNING,swLogPrintf("AM DL , SEG PDU , SN : %d , invalid LI header field "); +560128,1147269888,0,0,PS1,RLC,CatRlcAmDecodeDlSegPdu_data_e_1,P_WARNING,swLogPrintf("AM DL , REG PDU data part decode failed : %d , sn : %d , soStart : %d , soEnd : %d "); +560128,1147271680,0,0,PS1,RLC,CatRlcAmDecodeDlSegPdu_2,P_WARNING,swLogPrintf("AM DL , REG PDU useless , maybe all received before , sn : %d , soStart : %d , soEnd : %d "); +560128,1147273216,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_w_1,P_WARNING,swLogPrintf("AM DL , recv a invalid RLC PDU with size : %d < CAT_RLC_AM_MIN_PDU_LEN ( 3 ) "); +560128,1147275264,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_w_2,P_WARNING,swLogPrintf("AM DL , extSn , recv a invalid RLC PDU with size : %d < CAT_RLC_AM_16_SN_MIN_PDU_LEN ( 4 ) "); +560128,1147277824,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_size_w_1,P_WARNING,swLogPrintf("AM DL , recv a invalid RLC SEG PDU SN : %d , size : %d < CAT_RLC_AM_MIN_SEG_PDU_LEN ( %d ) "); +560128,1147279872,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_w_3,P_WARNING,swLogPrintf("AM DL , recv a SN : %d PDU , fall out of window : [ %d ~ %d ) "); +560128,1147281920,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_buf_w_1,P_WARNING,swLogPrintf("AM DL , SRB , recv a SN : %d PDU , fall out of buf : [ %d ~ %d ) "); +560128,1147283968,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_buf_w_2,P_WARNING,swLogPrintf("AM DL , DRB , recv a SN : %d PDU , fall out of buf : [ %d ~ %d ) "); +560128,1147285504,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_recv_w_1,P_WARNING,swLogPrintf("AM DL , whole SN ( %d ) PDU already recv before , discard current one "); +560128,1147287552,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_recv_w_2,P_WARNING,swLogPrintf("AM DL , part of SN ( %d ) SEG already report to PDCP , while RECV a whole RLC PDU here "); +560128,1147289856,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_whole_1,P_INFO,swLogPrintf("AM DL , LCID : %d , RECV WHOLE PDU SN : %d "); +560128,1147291904,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_dec_w_1,P_WARNING,swLogPrintf("AM DL , SN ( %d ) PDU decode error , errId : %d , discard it "); +560128,1147293696,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_dec_e_1,P_ERROR,swLogPrintf("AM DL , VRR = SN ( %d ) , but no memory left , need to abort connection "); +560128,1147296256,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_seg_1,P_INFO,swLogPrintf("AM DL , LCID : %d , RECV SEG PDU SN : %d , SO : %d "); +560128,1147298048,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_dec_seg_w_1,P_WARNING,swLogPrintf("AM DL , SN ( %d ) seg PDU decode error , errId : %d , discard it "); +560128,1147299840,0,0,PS1,RLC,CatRlcAmDecodeDlSnPdu_dec_seg_e_1,P_ERROR,swLogPrintf("AM DL , VRR = SN ( %d ) , seg PDU , but no memory left , need to abort connection "); +560128,1147302656,0,0,PS1,RLC,CatRlcAmDlDiscardAllPdu_w_1,P_WARNING,swLogPrintf("RLC AM DL , LCID : %d , discard DL PDU SN : %d > VRH : %d , VRR : %d "); +560128,1147304960,0,0,PS1,RLC,CatRlcAmAssembleLcDlSdu_reorder_1,P_WARNING,swLogPrintf("RLC AM DL , LCID : %d , VRH : %d > VRR : %d , set VRX : %d , start T_Reordering : %d "); +560128,1147306496,0,0,PS1,RLC,CatRlcAmAssembleLcDlSdu_reordering_2,P_WARNING,swLogPrintf("RLC AM DL , LCID : %d , VRH : %d > VRR : %d "); +560128,1147308544,0,0,PS1,RLC,CatRlcAmAssembleLcDlSdu_reordering_3,P_WARNING,swLogPrintf("AM LC : %d , VRH : %d > VRR : %d , trigger the status report "); +560128,1147310848,0,0,PS1,RLC,CatRlcAmAssembleLcDlSdu_pbit_1,P_INFO,swLogPrintf("AM LC : %d , P bit set , and CUR SN : %d < VRMS : %d , or > = VRMR : %d , trigger the status report "); +560128,1147312896,0,0,PS1,RLC,CatRlcAmDlLcReestablishReq_w_1,P_WARNING,swLogPrintf("RLC AM DL , LCID : %d , Re-Est DL PDU SN : %d > VRH : %d , VRR : %d "); +560128,1147314176,0,0,PS1,RLC,CatRlcAmTReorderingTimerExpiry_err,P_WARNING,swLogPrintf("AM LC : %d , t-Reordering is not running , ignore it! "); +560128,1147316992,0,0,PS1,RLC,CatRlcAmTReorderingTimerExpiry_1,P_WARNING,swLogPrintf("AM LC : %d , SRB , vrx : %d , fall out of buf : [ %d ~ %d ) , just set vrms to vrx "); +560128,1147319040,0,0,PS1,RLC,CatRlcAmTReorderingTimerExpiry_2,P_WARNING,swLogPrintf("AM LC : %d , DRB , vrx : %d , fall out of buf : [ %d ~ %d ) , just set vrms to vrx "); +560128,1147321344,0,0,PS1,RLC,CatRlcAmTReorderingTimerExpiry_3,P_WARNING,swLogPrintf("AM LC : %d , set VRX : %d , VRH : %d > VRMS : %d , start T_Reording : %d "); +560128,1147322880,0,0,PS1,RLC,CatRlcAmTReorderingTimerExpiry_4,P_WARNING,swLogPrintf("AM LC : %d , t-Reordering expiry , VRH : %d > VRR : %d , trigger the status report "); +560128,1147324416,0,0,PS1,RLC,CatRlcAmAllocUlPduBlockMem_1,P_ERROR,swLogPrintf("AM UL , no pool mem for RLC UL PDU block , more than : %d , need to abort connection "); +560128,1147326464,0,0,PS1,RLC,CatRlcAmCheckSetPBit_1,P_INFO,swLogPrintf("AM UL , LC : %d , no UL data pending , set ' P ' bit "); +560128,1147329280,0,0,PS1,RLC,CatRlcAmCheckSetPBit_2,P_INFO,swLogPrintf("AM UL , LC : %d , VTS out of window , vts : %d , vta : %d , vtms : %d , set ' P ' bit "); +560128,1147330560,0,0,PS1,RLC,CatRlcAmCheckSetPBit_3,P_INFO,swLogPrintf("AM UL , LC : %d , t-PollRetransmit timer expired before , set ' P ' bit "); +560128,1147333120,0,0,PS1,RLC,CatRlcAmCheckSetPBit_4,P_INFO,swLogPrintf("AM UL , LC : %d , pduWithoutPoll : %d > = pollPdu : %d , set ' P ' bit "); +560128,1147335168,0,0,PS1,RLC,CatRlcAmCheckSetPBit_5,P_INFO,swLogPrintf("AM UL , LC : %d , byteWithoutPoll : %d > = pollByte : %d , set ' P ' bit "); +560128,1147336960,0,0,PS1,RLC,CatRlcAmCheckSetPBit_6,P_INFO,swLogPrintf("AM UL , LC : %d , L2B high water , and UL RLC / PDCP only pending : %d , set ' P ' bit "); +560128,1147339776,0,0,PS1,RLC,CatRlcAmMergeNackSo_2,P_WARNING,swLogPrintf("AM PDU SN : %d , insert nack so : [ %d - %d ] before old so : [ %d - %d ] "); +560128,1147342336,0,0,PS1,RLC,CatRlcAmMergeNackSo_3,P_WARNING,swLogPrintf("AM PDU SN : %d , lots if nack sostart / soend ; need to merge from : [ %d - %d ] + [ %d - %d ] -> [ %d - %d ] "); +560128,1147344384,0,0,PS1,RLC,CatRlcAmMergeNackSo_4,P_INFO,swLogPrintf("AM PDU SN : %d , NACK SO merge from : [ %d - %d ] + [ %d - %d ] -> [ %d - %d ] "); +560128,1147346432,0,0,PS1,RLC,CatRlcAmMergeNackSo_5,P_INFO,swLogPrintf("AM PDU SN : %d ; NACK SO merge from : [ %d - %d ] + [ %d - %d ] -> [ %d - %d ] "); +560128,1147348480,0,0,PS1,RLC,CatRlcAmMergeNackSo_6,P_INFO,swLogPrintf("AM PDU SN : %d , NACK SO merge from : [ %d , %d ] + [ %d , %d ] -> [ %d , %d ] "); +560128,1147350528,0,0,PS1,RLC,CatRlcAmMergeNackSo_7,P_INFO,swLogPrintf("AM PDU SN : %d , NACK SO merge from : [ %d , %d ] + [ %d , %d ] -> [ %d , %d ] "); +560128,1147352576,0,0,PS1,RLC,CatRlcAmMergeNackSo_8,P_INFO,swLogPrintf("AM PDU SN : %d , NACK SO merge from : [ %d , %d ] + [ %d , %d ] -> [ %d , %d ] "); +560128,1147354624,0,0,PS1,RLC,CatRlcAmMergeNackSo_9,P_INFO,swLogPrintf("AM PDU SN : %d , NACK SO merge from : [ %d , %d ] + [ %d , %d ] -> [ %d , %d ] "); +560128,1147356672,0,0,PS1,RLC,CatRlcAmMergeNackSo_10,P_WARNING,swLogPrintf("AM PDU SN : %d , lots if nack sostart / soend , need to merge from : [ %d , %d ] + [ %d , %d ] -> [ %d , %d ] "); +560128,1147358208,0,0,PS1,RLC,CatRlcAmMergeNackSo_11,P_WARNING,swLogPrintf("AM PDU SN : %d , insert the NACK SO : [ %d , %d ] after old : [ %d , %d ] "); +560128,1147360768,0,0,PS1,RLC,CatRlcAmMergeNackSo_12,P_INFO,swLogPrintf("AM PDU SN : %d , NACK SO merge from : [ %d , %d ] + [ %d , %d ] -> [ %d , %d ] "); +560128,1147362048,0,0,PS1,RLC,CatRlcAmMergeNackSo_13,P_INFO,swLogPrintf("AM PDU SN : %d , merge NACK SO : [ %d , %d ] , all datalenght : %d , all PDU need to retx "); +560128,1147363584,0,0,PS1,RLC,CatRlcAmInsertPduIntoRetxList_1,P_WARNING,swLogPrintf("AM UL , LC : %d , SN : %d is exist in retx buffer , can ' t insert again! "); +560128,1147365376,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_1,P_INFO,swLogPrintf("AM UL , LC : %d , no UL RLC SDU left "); +560128,1147368192,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_2,P_WARNING,swLogPrintf("AM UL , LC : %d , SN window stalling , VTA : %d , VTS : %d , VTMS : %d "); +560128,1147369728,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_3,P_VALUE,swLogPrintf("AM UL , UL ExtSn : %d , left grant size : %d is not enough for a new RLC PDU "); +560128,1147371776,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_4,P_WARNING,swLogPrintf("AM UL , LC : %d , too much RLC PDU ( %d ) construct this time "); +560128,1147374336,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_buf_w_1,P_WARNING,swLogPrintf("AM DL , SRB LCID : %d , new PDU SN : %d , fall out of buf : [ %d ~ %d ) "); +560128,1147376384,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_buf_w_2,P_WARNING,swLogPrintf("AM DL , DRB LCID : %d , new PDU SN : %d , fall out of buf : [ %d ~ %d ) "); +560128,1147377920,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_buf_w_3,P_WARNING,swLogPrintf("AM DL , LCID : %d , No PDU info mem for new PDU SN : %d , not construct "); +560128,1147380480,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_5,P_INFO,swLogPrintf("AM UL , LC : %d , no more grant , PDU total grant : %d , pduDataLen : %d , preHdrLen : %d "); +560128,1147382272,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_6,P_WARNING,swLogPrintf("AM UL , LC : %d , RLC header too long : %d > memSize : %d "); +560128,1147384064,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_7,P_INFO,swLogPrintf("AM UL , LC : %d , UL RLC SDU all sent , no more pending , this PDU datalen : %d "); +560128,1147386368,0,0,PS1,RLC,CatRlcAmUlAssembleNewPdu_8,P_INFO,swLogPrintf("AM UL , LC : %d , New RLC PDU SN : %d , P Bit : %d "); +560128,1147387904,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_tStatusProhibit,P_INFO,swLogPrintf("AM UL , LC : %d , t-StatusProhibit is running , can ' t send Status Report! "); +560128,1147390208,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_1,P_WARNING,swLogPrintf("RLC AM , LC : %d , not enough grant : %d , to ASSEM status PDU "); +560128,1147392256,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_extSn_1,P_WARNING,swLogPrintf("RLC AM , LC : %d , extSN , not enough grant : %d , to ASSEM status PDU "); +560128,1147394816,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_2,P_WARNING,swLogPrintf("AM UL , not enought grant : %d , for LC : %d Status PDU , NACK_SN : %d , bitOffset : %d "); +560128,1147396864,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_3,P_WARNING,swLogPrintf("AM UL , not enought STATUS PDU buffer size : %d , for LC : %d Status PDU , NACK_SN : %d , bitOffset : %d "); +560128,1147398400,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_4,P_WARNING,swLogPrintf("AM UL , LC : %d , UL STATUS NACK : %d "); +560128,1147401472,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_6,P_WARNING,swLogPrintf("AM UL , not enought grant : %d , for LC : %d Status PDU , NACK_SN : %d , soStart : %d , soEnd : %d , bitOffset : %d "); +560128,1147402240,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_7,P_WARNING,swLogPrintf("AM UL , a soStart / soEnd exist for some NACK_SN : %d , set the pre soEnd to : 0x7FFF / 0xFFFF "); +560128,1147405568,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_8,P_WARNING,swLogPrintf("AM UL , not enought STATUS PDU buffer size : %d , for LC : %d Status PDU , NACK_SN : %d , soStart : %d , soEnd : %d , bitOffset : %d "); +560128,1147406336,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_9,P_WARNING,swLogPrintf("AM UL , a soStart / soEnd exist for some NACK_SN : %d , set the pre soEnd to : 0x7FFF / 0xFFFF "); +560128,1147409152,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_10,P_WARNING,swLogPrintf("AM UL , LC : %d , UL STATUS NACK : %d , soStart : %d , soEnd : %d "); +560128,1147410688,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_16,P_VALUE,swLogPrintf("AM UL , LC : %d , UL STATUS ACK SN : %d "); +560128,1147412736,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_17,P_WARNING,swLogPrintf("AM UL , LC : %d , not enough grant to send STATUS PDU , grant left : %d , need to continue to send STATUS PDU in next grant "); +560128,1147414784,0,0,PS1,RLC,CatRlcAmUlAssembleStatusPdu_18,P_INFO,swLogPrintf("AM LC : %d , Status reporting has been triggered , start T_StatusProhibit : %d ms "); +560128,1147417344,0,0,PS1,RLC,CatRlcAmUlAssembleOneSegPdu_1,P_INFO,swLogPrintf("AM UL , LC : %d , no more grant for more SEG SDU , SEG total grant : %d , segDataLen : %d , reqHdrSize : %d "); +560128,1147418880,0,0,PS1,RLC,CatRlcAmUlAssembleOneSegPdu_2,P_WARNING,swLogPrintf("AM UL , LC : %d , SEG PDU RLC header too long : %d "); +560128,1147420928,0,0,PS1,RLC,CatRlcAmUlRetxSegRlcPdu_w_1,P_WARNING,swLogPrintf("AM UL , LC : %d , already construct : %d segment PDU in current HARQ , can ' t any more "); +560128,1147422976,0,0,PS1,RLC,CatRlcAmUlRetxSegRlcPdu_1,P_WARNING,swLogPrintf("AM UL , LC : %d , already construct : %d MAC SDU , can ' t any more "); +560128,1147425280,0,0,PS1,RLC,CatRlcAmUlRetxSegRlcPdu_2,P_WARNING,swLogPrintf("AM UL , LC : %d , RE-SEG , no more grant ( %d ) reserved for MAC LC Header length ( %d ) "); +560128,1147427072,0,0,PS1,RLC,CatRlcAmUlRetxSegRlcPdu_3,P_WARNING,swLogPrintf("AM UL , LC : %d , RE-SEG , no more grant ( %d ) for a new seg PDU "); +560128,1147428864,0,0,PS1,RLC,CatRlcAmUlAssembleRetxPdu_1,P_INFO,swLogPrintf("AM UL , LC : %d , no RETX RLC PDU "); +560128,1147431168,0,0,PS1,RLC,CatRlcAmUlAssembleRetxPdu_2,P_WARNING,swLogPrintf("AM UL , LC : %d , too much RLC PDU ( %d ) construct this time , can ' t construct any more "); +560128,1147433472,0,0,PS1,RLC,CatRlcAmUlAssembleRetxPdu_3,P_WARNING,swLogPrintf("AM UL , LC : %d , no more grant ( %d ) reserved for MAC LC Header length ( %d ) "); +560128,1147435264,0,0,PS1,RLC,CatRlcAmUlAssembleRetxPdu_4,P_WARNING,swLogPrintf("AM UL , LC : %d , no more grant ( %d ) left for SEG PDU "); +560128,1147437312,0,0,PS1,RLC,CatRlcAmUlEstimateAllRetxPduGrant_1,P_WARNING,swLogPrintf("Estimate the UL grant for LC : %d , SN : %d need to SEG , todo in future "); +560128,1147439872,0,0,PS1,RLC,CatRlcAmUlRecvAckSn_1,P_WARNING,swLogPrintf("AM , LC : %d , received a invalid ackSn : %d , not in range : VTA : %d ~ VTS : %d "); +560128,1147442432,0,0,PS1,RLC,CatRlcAmUlRecvNackList_1,P_WARNING,swLogPrintf("AM , LC : %d , recv a invalid nackSn : %d , SO : [ %d - %d ] , not in range : VTA : %d ~ VTS : %d "); +560128,1147443968,0,0,PS1,RLC,CatRlcAmUlRecvNackList_2,P_WARNING,swLogPrintf("AM , LC : %d , recv a invalid nackSn : %d , not in range : VTA : %d ~ VTS : %d "); +560128,1147446528,0,0,PS1,RLC,CatRlcAmUlRecvNackList_invaid_sn_1,P_WARNING,swLogPrintf("AM , LC : %d , recv a invalid nackSn : %d , SO : [ %d - %d ] , VTA : %d ~ VTS : %d , but UL PDU not available , maybe ACKed before "); +560128,1147448064,0,0,PS1,RLC,CatRlcAmUlRecvNackList_invaid_sn_2,P_WARNING,swLogPrintf("AM , LC : %d , recv a invalid nackSn : %d , VTA : %d ~ VTS : %d , but UL PDU not available , maybe ACKed before "); +560128,1147449344,0,0,PS1,RLC,CeRlcAmEstimateStatusPduLen_1,P_WARNING,swLogPrintf("LC : %d , status report is not need "); +560128,1147451392,0,0,PS1,RLC,CeRlcAmEstimateStatusPduLen_2,P_INFO,swLogPrintf("LC : %d , t-StatusProhibit is running , no need to calc status report len "); +560128,1147453440,0,0,PS1,RLC,CatRlcAmTriggerStatusReport_highwater_1,P_WARNING,swLogPrintf("RLC AM LC : %d , t-StatusProhibit is running , but DL L2B highwater , trigger STATUS report at once "); +560128,1147455488,0,0,PS1,RLC,CatRlcAmTriggerStatusReport_prohibit_1,P_VALUE,swLogPrintf("RLC AM LC : %d , t-StatusProhibit is running , delay STATUS report "); +560128,1147457536,0,0,PS1,RLC,CatRlcAmTriggerStatusReport_1,P_VALUE,swLogPrintf("RLC AM LC : %d , AM trigger STATUS report "); +560128,1147459584,0,0,PS1,RLC,CatRlcAmTPollRetxTimerExpiry_1,P_INFO,swLogPrintf("AM UL , LC : %d , no more new PDU or retx PDU pending "); +560128,1147462400,0,0,PS1,RLC,CatRlcAmTPollRetxTimerExpiry_2,P_INFO,swLogPrintf("AM UL , LC : %d , VTS out of window , vts : %d , vta : %d , vtms : %d "); +560128,1147464448,0,0,PS1,RLC,CatRlcAmTPollRetxTimerExpiry_buf_w_1,P_WARNING,swLogPrintf("AM UL , SRB LCID : %d , VTS is %d , fall out of buf : [ %d ~ %d ) "); +560128,1147466496,0,0,PS1,RLC,CatRlcAmTPollRetxTimerExpiry_buf_w_2,P_WARNING,swLogPrintf("AM UL , DRB LCID : %d , VTS is %d , fall out of buf : [ %d ~ %d ) "); +560128,1147467776,0,0,PS1,RLC,CatRlcAmTPollRetxTimerExpiry_3,P_VALUE,swLogPrintf("AM UL , LC : %d , put last PDU into retx buffer "); +560128,1147470080,0,0,PS1,RLC,CatRlcAmTPollRetxTimerExpiry_4,P_VALUE,swLogPrintf("AM UL , LC : %d , VT (S ) -1 has been acked , put the SN : %d into retx buffer "); +560128,1147472640,0,0,PS1,RLC,CatRlcAmUlCheckPdcpDiscardTimer_1_1,P_WARNING,swLogPrintf("LCID : %d , PDCP PDU count : %d , discard timer expiry , curTick : 0x%x , discardEndTick : 0x%x , need to discard it "); +560128,1147473920,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_e_1,P_ERROR,swLogPrintf("RLC AM , LCID : %d , is for SRB , can ' t proc PDCP status report "); +560128,1147476224,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_p_1,P_SIG,swLogPrintf("RLC AM , proc PDCP status report , FMS : %d , bitmapSize : %d "); +560128,1147478272,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_p_2,P_SIG,swLogPrintf("RLC AM , continue to proc PDCP status report , FMS : %d , bitmapSize : %d "); +560128,1147482111,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_dump_1,P_SIG,swLogDump("RLC AM , proc PDCP status report bitmap : "); +560128,1147484159,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_dump_2,P_SIG,swLogDump("RLC AM , continue to proc PDCP status report bitmap : "); +560128,1147484416,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_discard_1,P_SIG,swLogPrintf("RLC AM , PDCP count : %d < fmsCount : %d , need to discard "); +560128,1147486208,0,0,PS1,RLC,CatRlcAmProcPdcpStatusReport_discard_2,P_SIG,swLogPrintf("RLC AM , PDCP count : %d , status report bitmap value 1 , try to discard from RLC SDU list "); +560128,1147488256,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_error_LI_0,P_ERROR,swLogPrintf("CAT RLC , UM DL , The LI value should not be 0 , segIndex : %d "); +560128,1147490560,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_odd_w_1,P_WARNING,swLogPrintf("CAT RLC , UM DL , invalid ODD LI header , leftLen : %d , pduLen : %d "); +560128,1147492352,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_error_LI_1,P_ERROR,swLogPrintf("CAT RLC , UM DL , The LI value should not be 0 , segIndex : %d "); +560128,1147494656,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_even_w_1,P_WARNING,swLogPrintf("CAT RLC , UM DL , invalid EVEN LI header , leftLen : %d , pduLen : %d "); +560128,1147498495,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_even_3,P_INFO,swLogPrintf("CAT RLC , DL , EVEN LI headers , no more LI left "); +560128,1147500543,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_odd_4,P_INFO,swLogPrintf("CAT RLC , UM DL , ODD LI headers , no more LI left "); +560128,1147500800,0,0,PS1,RLC,CatRlcUmDecodeLiHeader_w_1,P_WARNING,swLogPrintf("CAT RLC , UM DL , invalid LI header , left Len : %d , or too much LI headers : %d "); +560128,1147504639,0,0,PS1,RLC,CatRlcUmDecodeDlWholePdu_li_w_1,P_WARNING,swLogPrintf("CAT RLC , UM DL , invalid LI header field "); +560128,1147504640,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_w_1,P_WARNING,swLogPrintf("UM DL , SN SIZE 5 , recv a invalid RLC PDU with size : %d < CAT_RLC_UM_5_SN_MIN_PDU_LEN ( 2 ) "); +560128,1147506688,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_w_2,P_WARNING,swLogPrintf("UM DL , SN SIZE 10 , recv a invalid RLC PDU with size : %d < CAT_RLC_UM_10_SN_MIN_PDU_LEN ( 3 ) "); +560128,1147509248,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_w_3,P_WARNING,swLogPrintf("UM DL , recv a SN : %d PDU , VR ( UH ) -UM_Window_Size : %d < = SN < VR ( UR ) : %d , diacard it! "); +560128,1147511296,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_buf_w_1,P_WARNING,swLogPrintf("UM DL , DRB ( SN 10 Bits ) , recv a SN : %d PDU , fall out of buf : [ %d ~ %d ) , diacard it! "); +560128,1147513344,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_recv_w_1,P_WARNING,swLogPrintf("UM DL , VR ( UR ) : %d < SN : %d < VR ( UH ) %d , and the whole SN PDU already recv before , discard it! "); +560128,1147515136,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_whole_1,P_INFO,swLogPrintf("UM DL , LCID : %d , RECV WHOLE PDU SN : %d "); +560128,1147517184,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_dec_w_1,P_WARNING,swLogPrintf("UM DL , SN ( %d ) PDU decode error , errId : %d , discard it! "); +560128,1147518976,0,0,PS1,RLC,CatRlcUmDecodeDlSnPdu_dec_e_1,P_ERROR,swLogPrintf("UM DL , VR ( UR ) = SN ( %d ) , but no memory left , need to abort connection "); +560128,1147521536,0,0,PS1,RLC,CatRlcUmAssembleLcDlSdu_reordering_1,P_WARNING,swLogPrintf("RLC UM DL , LCID : %d , VRUH : %d > VRUR : %d "); +560128,1147524096,0,0,PS1,RLC,CatRlcUmAssembleLcDlSdu_reorder_2,P_WARNING,swLogPrintf("RLC UM DL , LCID : %d , VRUH : %d > VRUR : %d , set VRUX : %d , start T_Reordering : %d "); +560128,1147525120,0,0,PS1,RLC,CatRlcUmTReorderingTimerExpiry_err,P_WARNING,swLogPrintf("UM LC : %d , t-Reordering is not running , ignore it! "); +560128,1147527936,0,0,PS1,RLC,CatRlcUmTReorderingTimerExpiry_1,P_WARNING,swLogPrintf("UM DL , LC : %d , ( SN 10 Bits ) , vrux : %d , fall out of buf : [ %d ~ %d ) , just set vrur to vrux "); +560128,1147530240,0,0,PS1,RLC,CatRlcUmTReorderingTimerExpiry_4,P_WARNING,swLogPrintf("UM DL , LC : %d , set VRUX : %d , VRUH : %d > VRUR : %d , start T_Reording : %d "); +560128,1147531264,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_1,P_INFO,swLogPrintf("UM UL , LC : %d , no UL RLC SDU left "); +560128,1147533568,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_2,P_VALUE,swLogPrintf("UM UL , UL SN size : %d , left grant size : %d is not enough for a new RLC PDU "); +560128,1147535616,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_3,P_WARNING,swLogPrintf("UM UL , LC : %d , too much RLC PDU ( %d ) construct this time "); +560128,1147538176,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_4,P_INFO,swLogPrintf("UM UL , LC : %d , no more grant , PDU total grant : %d , pduDataLen : %d , preHdrLen : %d "); +560128,1147539968,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_5,P_WARNING,swLogPrintf("UM UL , LC : %d , RLC header too long : %d > hdrMemSize : %d "); +560128,1147541760,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_6,P_INFO,swLogPrintf("UM UL , LC : %d , UL RLC SDU all sent , no more pending , this PDU datalen : %d "); +560128,1147544064,0,0,PS1,RLC,CatRlcUmUlAssembleNewPdu_7,P_INFO,swLogPrintf("UM UL , LC : %d , New RLC PDU SN : %d , harqId : %d "); +560128,1147546368,0,0,PS1,RLC,CatRlcUmUlCheckPdcpDiscardTimer_1_1,P_WARNING,swLogPrintf("LCID : %d , PDCP PDU count : %d , discard timer expiry , curTick : %d , discardEndTick : %d , need to discard it "); +561152,1149241344,0,0,PS1,PDCP,CatPdcpDrbLcSetupConfig_1,P_SIG,swLogPrintf("LCID : %d , is configed ROHC "); +561152,1149243648,0,0,PS1,PDCP,CatPdcpDrbLcSetupConfig_2,P_SIG,swLogPrintf("LCID : %d , Extend pdcp discard timer from %d ms to 20000 ms for FT "); +561152,1149245696,0,0,PS1,PDCP,CatPdcpLcResumeSuspendReq_e_1,P_ERROR,swLogPrintf("CAT PDCP , can ' t suspend / resume : %d , LCID : %d , not PDCP context "); +561152,1149249535,0,0,PS1,PDCP,CatPdcpAllLcReleaseInd_1,P_VALUE,swLogPrintf("PDCP , all LC are released "); +561152,1149251583,0,0,PS1,PDCP,CatPdcpDlPduSoftEeaThenEia_2,P_WARNING,swLogPrintf("PDCP DL PDU , SOFT EEA the EIA FAIL , key not configed !!!! "); +561152,1149253376,0,0,PS1,PDCP,CatPdcpDlPduSoftEeaThenEia_3,P_WARNING,swLogPrintf("PDCP DL PDU , soft EEA the EIA FAIL , orig MACI : 0x%x 0x%x 0x%x 0x%x , CALC MACI : 0x%x 0x%x 0x%x 0x%x "); +561152,1149253632,0,0,PS1,PDCP,CatPdcpIsUlHighWater_high_1,P_VALUE,swLogPrintf("CAT PDCP , UL highwater , pendingLen : %d "); +561152,1149257727,0,0,PS1,PDCP,CatPdcpPmuDeepSlpEnterCallBack_s_1,P_SIG,swLogPrintf("CAT PDCP , only TPT statis need write to flash , can ' t enter HIB , change to SLP2 "); +561152,1149259775,0,0,PS1,PDCP,CatPdcpPmuDeepSlpEnterCallBack_s_2,P_SIG,swLogPrintf("CAT PDCP , tiny flash need to write , update TPT statis by the way , and vote to HIB "); +561152,1149259776,0,0,PS1,PDCP,CatPdcpProcCounterCheckReqSig_1,P_ERROR,swLogPrintf("CAT PDCP , nwDrbCountMsbNum : %d , exceeds the max num , pls check it! "); +561152,1149262080,0,0,PS1,PDCP,CatPdcpDlIsStoreDlSdu_s_1,P_SIG,swLogPrintf("CAT PDCP , AM LCID : %d , SN : %d , need to store in local "); +561152,1149263872,0,0,PS1,PDCP,CatPdcpDlDeliverStoredSduBeforeCurCount_1,P_WARNING,swLogPrintf("PDCP DL : CurCount ( %d ) just the same as stored one , just discard the stored one "); +561152,1149266176,0,0,PS1,PDCP,CatPdcpDlDeliverStoredSduAfterCurCount_1,P_WARNING,swLogPrintf("PDCP DL : store PDCP SDU count ( %d ) < = ( preCount ( %d ) + 1 ) , just discard the stored one "); +561152,1149268736,0,0,PS1,PDCP,CatPdcpDlDecodeDrbUmPduHeader_invalid_1,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , SN : %d , PDU should bCont , but pNext : 0x%x , dCont : %d "); +561152,1149270528,0,0,PS1,PDCP,CatPdcpDlDecodeDrbUmPduHeader_invalid_2,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , SN 12 bits , PDU should bCont , but pNext : 0x%x , dCont : %d "); +561152,1149272832,0,0,PS1,PDCP,CatPdcpDlDecodeDrbUmPduHeader_invalid_3,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , SN : %d , only header part no data part , pNext : 0x%x , dCont : %d , discard "); +561152,1149274624,0,0,PS1,PDCP,CatPdcpDlDecodeDrbAmPduHeader_invalid_1,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , PDCP header not complete , pNext : 0x%x , dCont : %d , discard "); +561152,1149276672,0,0,PS1,PDCP,CatPdcpDlDecodeDrbAmPduHeader_invalid_2,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , 18 bit SN , PDCP header not complete , pNext : 0x%x , dCont : %d , discard "); +561152,1149278976,0,0,PS1,PDCP,CatPdcpDlDecodeDrbAmPduHeader_invalid_3,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , curSN : %d , no data part , pNext : 0x%x , dCont : %d , discard "); +561152,1149280768,0,0,PS1,PDCP,CatPdcpDlDecodeDrbAmPduHeader_1,P_WARNING,swLogPrintf("PDCP LCID : %d , recv PDCP SN : %d , Last_Submitted_PDCP_RX_SN : %d , out of win , need to discard "); +561152,1149282304,0,0,PS1,PDCP,CatPdcpDlDecodeOneSrbPdu_e_1,P_ERROR,swLogPrintf("CAT PDCP , LCID : %d , DL PDCP SEG bContinue , but next seg is NULL "); +561152,1149284608,0,0,PS1,PDCP,CatPdcpDlDecodeOneSrbPdu_e_2,P_ERROR,swLogPrintf("CAT PDCP , SRB LCID : %d , invalid DL PDCP PDU length : %d , discard it "); +561152,1149286400,0,0,PS1,PDCP,CatPdcpDlDecodeOneDrbPduData_e_1,P_ERROR,swLogPrintf("CAT PDCP , LCID : %d , DL PDCP SEG bContinue , but next seg is NULL "); +561152,1149289472,0,0,PS1,PDCP,CatPdcpDlDecodeOneDrbPduData_storeMax_1,P_WARNING,swLogPrintf("CAT PDCP , DRB LCID : %d , DL PKG len store too much : %d > = %d , can ' t store more , discard curCount : %d , len : %d "); +561152,1149290752,0,0,PS1,PDCP,CatPdcpDlDecodeOneDrbPduData_e_2,P_ERROR,swLogPrintf("CAT PDCP , DRB LCID : %d , invalid DL PDCP SDU length : %d , discard it "); +561152,1149292800,0,0,PS1,PDCP,CatPdcpDlDecodeOneDrbPduData_2,P_WARNING,swLogPrintf("PDCP LCID : %d , store DL PDU , count : %d "); +561152,1149294848,0,0,PS1,PDCP,CatPdcpDlDecodeOneDrbPduData_3,P_WARNING,swLogPrintf("PDCP LCID : %d , store DL PDU , count : %d , but need ROHC decompression "); +561152,1149297408,0,0,PS1,PDCP,CatPdcpDlDecodeOneStatusReportPdu_discard_1,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , recv status report , but is not AM : %d , or isSrb : %d , or isSuspend : %d , discard it "); +561152,1149299200,0,0,PS1,PDCP,CatPdcpDlDecodeOneStatusReportPdu_invalid_1,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , status report , pNext : 0x%x , dCont : %d , discard "); +561152,1149301504,0,0,PS1,PDCP,CatPdcpDlDecodeOneStatusReportPdu_invalid_2,P_ERROR,swLogPrintf("PDCP DL , LCID : %d , snBitNum : %d , status report not complete , pNext : 0x%x , dCont : %d , discard "); +561152,1149302784,0,0,PS1,PDCP,CatPdcpDlDecodeOneControlPdu_ctrl_w_1,P_WARNING,swLogPrintf("CAT PDCP , recv unknow PDCP control PDU , type : %d , discard it "); +561152,1149306879,0,0,PS1,PDCP,CatPdcpDlDecodeOneControlPdu_dump,P_WARNING,swLogDump("Unknown PDCP DL PDU : "); +561152,1149306880,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_highwater_1,P_WARNING,swLogPrintf("PDCP LCID : %d , DL PKG memory highwater , discard all PKG during RE-EST "); +561152,1149308928,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_highwater_2,P_WARNING,swLogPrintf("PDCP LCID : %d , DL PKG memory highwater , backup PDCP PDU "); +561152,1149310976,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_sctopen_2,P_WARNING,swLogPrintf("PDCP LCID : %d , can ' t open SCT , discard DL PDU "); +561152,1149313024,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_highwater_3,P_WARNING,swLogPrintf("PDCP LCID : %d , DL PKG memory highwater , backup left PDCP PDU "); +561152,1149315584,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_reorder_s_1,P_SIG,swLogPrintf("PDCP , AM LCID : %d , curCount : %d , after re-est , update lastSubmittedCount to : %d "); +561152,1149317632,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_reorder_s_2,P_SIG,swLogPrintf("PDCP , AM LCID : %d , curSn : %d , during re-est , reorder , don ' t update lastSubmittedPdcpRxSn : %d "); +561152,1149319168,0,0,PS1,PDCP,CatPdcpDlProcUpPduInd_abnormal_1,P_WARNING,swLogPrintf("PDCP LCID : %d , recv DL PDU , but can ' t need to config SCT "); +561152,1149321216,0,0,PS1,PDCP,CatPdcpDlEiaFailRollbackVars_1,P_WARNING,swLogPrintf("PDCP LCID : %d , DL EIA failed , need to rollback some variables "); +561152,1149323264,0,0,PS1,PDCP,CatPdcpDlReEstProcPduInd_1,P_WARNING,swLogPrintf("SRB LCID : %d , RLC should not pass the DL PDCP PDU to PDCP during re-est procedure "); +561152,1149325312,0,0,PS1,PDCP,CatPdcpDlLcReestablishReq_um_w_1,P_WARNING,swLogPrintf("CAT PDCP , UM LCID : %d , backup DL SDU must discard "); +561152,1149327360,0,0,PS1,PDCP,CatPdcpDlLcReestablishReq_am_w_1,P_WARNING,swLogPrintf("CAT PDCP , AM LCID : %d , backup DL SDU must discard "); +561152,1149331455,0,0,PS1,PDCP,CatPdcpDlProcDlPkgContinueReqSig_e_1,P_ERROR,swLogPrintf("CAT PDCP DL , PS DL PKG continue request , but still high water !!! "); +561152,1149331456,0,0,PS1,PDCP,CatPdcpDlProcDlPkgContinueReqSig_w_1,P_WARNING,swLogPrintf("CAT PDCP DL , DL PKG memory highwater again , can ' t proc LCID : %d DL backup PDU , keep backup "); +561152,1149333760,0,0,PS1,PDCP,CatPdcpUlDrbPendingLenAdd_high_1,P_WARNING,swLogPrintf("CAT PDCP , UL become highwater , pendingLen : %d , new add : %d "); +561152,1149335552,0,0,PS1,PDCP,CatPdcpUlDrbPendingLenSub_high_1,P_WARNING,swLogPrintf("CAT PDCP , UL become not highwater , pendingLen : %d "); +561152,1149337856,0,0,PS1,PDCP,CatPdcpUlEia0ConfigL2CForCpDataReq_1,P_WARNING,swLogPrintf("SRB LCID : %d , config EEA : %d , but EIA0 "); +561152,1149340416,0,0,PS1,PDCP,CatPdcpUlSetPdcpPduInfoForUpData_1,P_VALUE,swLogPrintf("PDCP LCID : %u , set this UL PDU discard tick to : %u , as PDCP config discardTick : %u > PKG discardTick : %u "); +561152,1149341696,0,0,PS1,PDCP,CatPdcpUlSRBCpDataReq_1,P_ERROR,swLogPrintf("Can ' t find PDCP context for LCID : %d , can ' t send UL data "); +561152,1149343744,0,0,PS1,PDCP,CatPdcpUlSRBCpDataReq_2,P_ERROR,swLogPrintf("PDCP LCID : %d , but can ' t open SCT , can ' t send UL data "); +561152,1149346048,0,0,PS1,PDCP,CatPdcpUlConsAndCfgOnePduForUpData_0,P_VALUE,swLogPrintf("PDCP LCID : %d , UL ROHC feedback PKG , total LEN : %d "); +561152,1149348352,0,0,PS1,PDCP,CatPdcpUlConsAndCfgOnePduForUpData_1,P_WARNING,swLogPrintf("LCID : %d , Can ' t send PDCP SDU with len : %d = = 0 or > %d "); +561152,1149350144,0,0,PS1,PDCP,CatPdcpUlConsAndCfgOnePduForUpData_2,P_WARNING,swLogPrintf("LCID : %d , Can ' t alloc L2B buffer for UL PDCP PDU , len : %d "); +561152,1149353983,0,0,PS1,PDCP,CatPdcpUlSendUpDataReq_1,P_ERROR,swLogPrintf("SCT exhaust , can ' t OPEN for UL UP data "); +561152,1149356031,0,0,PS1,PDCP,CatPdcpUlSendUpDataReq_2,P_WARNING,swLogPrintf("Can ' t construct / config PDCP PDU for UL UP data "); +561152,1149358079,0,0,PS1,PDCP,CatPdcpUlSendUpDataReq_3,P_WARNING,swLogPrintf("One UL UP PKG construct error , continue to process the previous UL PKG "); +561152,1149360127,0,0,PS1,PDCP,CatPdcpUlPdcpPduToRlc_e_1,P_ERROR,swLogPrintf("SCT exhaust , can ' t OPEN for UL PDCP PDU to RLC "); +561152,1149360384,0,0,PS1,PDCP,CatPdcpUlConsOneRawPduForUpData_fb_0,P_VALUE,swLogPrintf("PDCP LCID : %d , UL ROHC feedback PKG , total LEN : %d "); +561152,1149362688,0,0,PS1,PDCP,CatPdcpUlConsOneRawPduForUpData_len_1,P_WARNING,swLogPrintf("LCID : %d , Can ' t construct RAW PDCP PDU with len : %d = = 0 or > %d "); +561152,1149364480,0,0,PS1,PDCP,CatPdcpUlConsOneRawPduForUpData_no_bm_2,P_WARNING,swLogPrintf("LCID : %d , Can ' t alloc L2B buffer for UL RAW PDCP PDU , len : %d "); +561152,1149368319,0,0,PS1,PDCP,CatPdcpUlUpDataToPdcp_e_1,P_ERROR,swLogPrintf("SCT exhaust , can ' t OPEN for UL UP data to PDCP "); +561152,1149369600,0,0,PS1,PDCP,CatPdcpUlCtrlSendUpData_opt_5,P_VALUE,swLogPrintf("CAT PDCP , RLC CTRL , UL BM high : %d , pending UL PKG , shortPending : %d , normalPending : %d , shortSentLen : %d , shorPdcpLen : %d , normalPdcpLen : %d "); +561152,1149371648,0,0,PS1,PDCP,CatPdcpUlCtrlSendUpData_opt_7,P_DEBUG,swLogPrintf("CAT PDCP , RLC CTRL , UL BM size : %d , pending UL PKG , shortPending : %d , normalPending : %d , shortSentLen : %d , shorPdcpLen : %d , normalPdcpLen : %d "); +561152,1149374463,0,0,PS1,PDCP,CatPdcpUlRetxAmDrbPdu_open_e_1,P_ERROR,swLogPrintf("SCT exhaust , can ' t OPEN for DRB AM retx data "); +561152,1149374464,0,0,PS1,PDCP,CatPdcpUlRetxAmDrbPdu_discard_1,P_INFO,swLogPrintf("CAT PDCP , DRB AM retx , LCID : %d , one PDCP PDU out of date , not need to retx "); +561152,1149376512,0,0,PS1,PDCP,CatPdcpUlRetxAmDrbPdu_discard_2,P_INFO,swLogPrintf("CAT PDCP , DRB AM retx , LCID : %d , control PDU don ' t need to retx "); +561152,1149379072,0,0,PS1,PDCP,CatPdcpUlRetxAmDrbPdu_discard_3,P_WARNING,swLogPrintf("CAT PDCP , DRB AM retx , LCID : %d , PDCP PDU length : %d < = PDCP header length : %d , useless , discard "); +561152,1149380608,0,0,PS1,PDCP,CatPdcpUlRetxAmDrbPdu_cancel_1,P_WARNING,swLogPrintf("CAT PDCP , LCID : %d , no valid PDU need re-tx "); +561152,1149383168,0,0,PS1,PDCP,CatPdcpUlProcCpDataReqSig_1,P_VALUE,swLogPrintf("SRB LCID : %d , UL data , total len : %d , contain nas len : %d "); +561152,1149384704,0,0,PS1,PDCP,CatPdcpUlUpDataReq_1,P_WARNING,swLogPrintf("Can ' t find the PDCP context for LCID : %d "); +561152,1149386752,0,0,PS1,PDCP,CatPdcpUlUpDataReq_2,P_WARNING,swLogPrintf("PDCP LCID : %d is not DRB , can ' t send UL UP Data "); +561152,1149389056,0,0,PS1,PDCP,CatPdcpUlUpDataReq_3,P_WARNING,swLogPrintf("PDCP LCID : %d is suspended , can ' t send UL PDU , pending LEN : %d "); +561152,1149391104,0,0,PS1,PDCP,CatPdcpUlUpDataReqSort_1,P_WARNING,swLogPrintf("Can ' t find the PDCP context for LCID : %d , or not DRB : %d , can ' t send UL UP Data "); +561152,1149393408,0,0,PS1,PDCP,CatPdcpUlUpDataReqSort_pendig_1,P_WARNING,swLogPrintf("PDCP LCID : %d is suspended , can ' t send UL PDU , pending LEN : %d , shortLen : %d "); +561152,1149395456,0,0,PS1,PDCP,CatPdcpUlTransSuccInd_1,P_VALUE,swLogPrintf("PDCP LCID : %u , RRC PDU ID : %u , UL sent SUCC , cost : %u "); +561152,1149397248,0,0,PS1,PDCP,CatPdcpUlTransSuccInd_2,P_VALUE,swLogPrintf("PDCP LCID : %u , RRC PDU ID : %u , UL sent SUCC "); +561152,1149399296,0,0,PS1,PDCP,CatPdcpUlTransSuccInd_3,P_VALUE,swLogPrintf("PDCP LCID : %u , RRC PDU : %u , UL sent SUCC "); +561152,1149401344,0,0,PS1,PDCP,CatPdcpUlTransFailInd_1,P_VALUE,swLogPrintf("PDCP LCID : %d , UL RRC PDU ID : %d , sent failed "); +561152,1149403136,0,0,PS1,PDCP,CatPdcpUlTransFailInd_e_1,P_ERROR,swLogPrintf("CAT PDCP , LCID : %d , can ' t find the context "); +561152,1149405184,0,0,PS1,PDCP,CatPdcpUlTransFailInd_w_1,P_WARNING,swLogPrintf("CAT PDCP , AM LCID : %d , is configed ROHC , not support re-tx UL PDU "); +561152,1149407232,0,0,PS1,PDCP,CatPdcpUlTransFailInd_3,P_VALUE,swLogPrintf("PDCP_SDU Trans Failed : lcid %d "); +561152,1149409280,0,0,PS1,PDCP,CatPdcpUlLcResumeReq_am_retx_1,P_SIG,swLogPrintf("CAT PDCP , DRB AM , LCID : %d , PDU retx "); +561152,1149411584,0,0,PS1,PDCP,CatPdcpUlLcResumeReq_um_retx_1,P_WARNING,swLogPrintf("CAT PDCP , DRB be UM : %d , LCID : %d , should no retx PDU "); +561152,1149413632,0,0,PS1,PDCP,CatPdcpUlSendStatusReport_buf_1,P_WARNING,swLogPrintf("LCID : %d , Can ' t alloc L2B buffer for UL status report , len : %d "); +561152,1149416448,0,0,PS1,PDCP,CatPdcpUlSendStatusReport_buf_w_1,P_WARNING,swLogPrintf("PDCP UL status report , LCID : %d , buf size not enough , pduMaxBitSize : %d , recvSn : %d , bitmapSn : %d , fms : %d "); +561152,1149419519,0,0,PS1,PDCP,CatPdcpUlSendStatusReport_status_rpt_dump,P_VALUE,swLogDump("PDCP UL , send status report : "); +561152,1149419776,0,0,PS1,PDCP,CatPdcpUlAddPendingPdcpPdu_1,P_WARNING,swLogPrintf("CAT PDCP , no PDCP CTX for LCID : %d , or not DRB : %d , can ' t pending UL PDCP PDU "); +562176,1151338752,0,0,PS1,BM,CatUpCheckFreeBuffBlock_ul_1,P_WARNING,swLogPrintf("CAT UP BM , cancel UL highwater : %d , totalNum : %d "); +562176,1151340800,0,0,PS1,BM,CatUpCheckFreeBuffBlock_dl_1,P_WARNING,swLogPrintf("CAT UP BM , cancel DL highwater : %d , totalNum : %d "); +562176,1151344128,0,0,PS1,BM,CatUpBmFreeAll_1,P_ERROR,swLogPrintf("CAT UP BM , Pls check DL BB , pStart is 0x%x , phyNotUsed is %d , freeLen is %d , alloPhyNum is %d , freePhyNum is %d , allocRlcSegNum is %d , freeRlcSegNum is %d "); +562176,1151345408,0,0,PS1,BM,CatUpBmFreeAll_2,P_ERROR,swLogPrintf("CAT UP BM , Pls check UL BB , pStart is 0x%x , freeLen is %d , alloNum is %d , freeNum is %d "); +562176,1151346688,0,0,PS1,BM,CatUpBmIsL2UlHighWater_w_1,P_VALUE,swLogPrintf("= = = = L2B UL higher water ( used : %d ) = = = = "); +562176,1151349248,0,0,PS1,BM,CatUpBmIsL2UlLimited_e_1,P_ERROR,swLogPrintf("= = = = L2B UL limited ( used : %d , limited : %d , DL lack : %d ) = = = = "); +562176,1151350784,0,0,PS1,BM,CatUpBmIsL2DlHighWater_w_1,P_WARNING,swLogPrintf("= = = = L2B DL higher water ( used : %d ) = = = = "); +562176,1151353088,0,0,PS1,BM,CatUpBmAllocPdcpUlMem_w_1,P_WARNING,swLogPrintf("CAT UP BM , no free BB left , alloDlBBNum : %d , alloUlBBNum : %d "); +562176,1151354880,0,0,PS1,BM,CatUpBmAllocPdcpUlMem_w_2,P_WARNING,swLogPrintf("CAT UP BM , alloUlBBNum : %d , UL high water "); +562176,1151357184,0,0,PS1,BM,CatUpBmFreeMacDlMem_dl_1,P_WARNING,swLogPrintf("CAT UP BM , DL highwater : %d , totalNum : %d "); +562176,1151359232,0,0,PS1,BM,CatUpBmFreeMacDlMem_dl_2,P_WARNING,swLogPrintf("CAT UP BM , NO UP BB left , lackDlBBNum : %d , alloDlBBNum : %d "); +562176,1151361024,0,0,PS1,BM,CatUpBmGetFreeULMemSize_w_1,P_VALUE,swLogPrintf("= = = = L2B UL higher water ( used : %d ) , free mem return 0 = = = = "); +563200,1153437695,0,0,PS1,DR,CesmCheckSendPdnConReqByAclApn_dump_1,P_WARNING,swLogDump("CESM , parse APN : "); +563200,1153437696,0,0,PS1,DR,CedrUlRateCtrlBAllow_1,P_WARNING,swLogPrintf("EpsId : %d , PLMN Rate Ctrl timer is running , not allow to send new PDU "); +563200,1153439744,0,0,PS1,DR,CedrUlRateCtrlBAllow_2,P_WARNING,swLogPrintf("EpsId : %d , APN Rate Ctrl timer is running , not allow to send new PDU "); +563200,1153441792,0,0,PS1,DR,CedrUlRateCtrlBAllow_3,P_WARNING,swLogPrintf("EpsId : %d , APN Rate Ctrl timer is running , but exception data is allow to send "); +563200,1153443840,0,0,PS1,DR,CedrUlRateCtrlBAllow_4,P_WARNING,swLogPrintf("EpsId : %d , APN Except Rate Ctrl timer is not running , exception data is allow to send "); +563200,1153445888,0,0,PS1,DR,CedrUlApnExceptRateCtrlAllowPduNum_1,P_WARNING,swLogPrintf("EpsId : %d , PLMN Rate Ctrl timer is running , UL exception data not allowed "); +563200,1153447936,0,0,PS1,DR,CedrUlApnExceptRateCtrlAllowPduNum_2,P_WARNING,swLogPrintf("EpsId : %d , APN RATE CTRL , but UL exception data allowed "); +563200,1153450240,0,0,PS1,DR,CedrUlApnExceptRateCtrlAllowPduNum_3,P_WARNING,swLogPrintf("EpsId : %d , APN exception Rate Ctrl timer is running , not allow exception data , pending NUM : %d "); +563200,1153452544,0,0,PS1,DR,CedrUlApnExceptRateCtrlAllowPduNum_4,P_SIG,swLogPrintf("EpsId : %d , Exception Rate Ctrl , reqExceptPduNum : %d , allowExceptPduNum : %d "); +563200,1153454336,0,0,PS1,DR,CedrUlApnPlmnRateCtrlAllowPduNum_1,P_WARNING,swLogPrintf("EpsId : %d , PLMN Rate Ctrl timer is running , pending UL PDU NUM : %d "); +563200,1153456384,0,0,PS1,DR,CedrUlApnPlmnRateCtrlAllowPduNum_3,P_WARNING,swLogPrintf("EpsId : %d , APN Rate Ctrl timer is running , pending UL PDU NUM : %d "); +563200,1153458688,0,0,PS1,DR,CedrUlApnPlmnRateCtrlAllowPduNum_end_1,P_WARNING,swLogPrintf("EpsId : %d , APN / PLMN Rate Ctrl reqPduNum : %d , but only allowPduNum : %d "); +563200,1153460224,0,0,PS1,DR,CedrProcDrTestLoopModeADataReq_1,P_WARNING,swLogPrintf("TEST LOOP MODE A , no EPS bearer info for EPSID : %d , free loopback data "); +563200,1153463040,0,0,PS1,DR,CedrProcDrTestLoopModeADataReq_2,P_WARNING,swLogPrintf("TEST LOOP MODE A , EPSID : %d , is CP ONLY ( %d ) , or DRB not exist ( %d ) , or suspended ( %d ) , free loopback data "); +563200,1153464320,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_1,P_WARNING,swLogPrintf("TEST LOOP MODE B , no EPS bearer info for EPSID : %d , free loopback data "); +563200,1153467136,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_2,P_WARNING,swLogPrintf("TEST LOOP MODE B , EPSID : %d , is CP ONLY ( %d ) , or DRB not exist ( %d ) , or suspended ( %d ) , free loopback data "); +563200,1153468416,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_3,P_VALUE,swLogPrintf("TEST LOOP MODE B ; tDelay : %d > 0 ; need to buffer loopback data "); +563200,1153470720,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_nobr_e_2,P_ERROR,swLogPrintf("CE DR , dedicated BR : %d , can ' t find linked default BR : %d , can ' t check TFT "); +563200,1153472768,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_nobr_e_3,P_ERROR,swLogPrintf("CE DR , TFT route data to CID : %d , but can ' t find BR , using current BR with CID : %d "); +563200,1153476607,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_4,P_WARNING,swLogPrintf("CE DR , TEST LOOP MODE B , does not match any TFT filter , discard all UL data "); +563200,1153478655,0,0,PS1,DR,CedrProcDrTestLoopModeBDataReq_dump_1,P_WARNING,swLogDump("CE DR , discard loop data : "); +563200,1153480703,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_1,P_VALUE,swLogPrintf("TEST LOOP MODE G ; but repNum is 0 ; don ' t loopback "); +563200,1153480704,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_3,P_WARNING,swLogPrintf("TEST LOOP MODE G ; no EPS bearer info for EPSID : %d ; free loopback data "); +563200,1153482752,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_2_1,P_INFO,swLogPrintf("TEST LOOP MODE G , MTU size : %d configed "); +563200,1153486847,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_2,P_WARNING,swLogPrintf("TEST LOOP MODE G ; loopback to CESM ; but ESM is suspended ; just free all PDU "); +563200,1153486848,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_4,P_VALUE,swLogPrintf("TEST LOOP MODE G ; tDelay : %d > 0 ; need to buffer loopback data "); +563200,1153489408,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_5,P_VALUE,swLogPrintf("CE DR , EpsId : %d , UL PKG RATE CTRL , reqNum : %d , allowedNum : %d "); +563200,1153490944,0,0,PS1,DR,CedrProcDrTestLoopModeGDataReq_not_sup_1,P_ERROR,swLogPrintf("CE DR , loop mode G , epsId : %d , not support loop data to SRB2 , free all loopback data "); +563200,1153495039,0,0,PS1,DR,CedrProcDrTestLoopModeHDataReq_1,P_VALUE,swLogPrintf("TEST LOOP MODE H , but repNum is 0 , don ' t loopback "); +563200,1153495040,0,0,PS1,DR,CedrProcDrTestLoopModeHDataReq_2,P_VALUE,swLogPrintf("TEST LOOP MODE H , tDelay ( %d ) > 0 , need to buffer SMS loopback data "); +563200,1153499135,0,0,PS1,DR,CedrProcDrTestLoopModeHDataReq_not_sup_1,P_ERROR,swLogPrintf("CE DR , loop mode H , not support loop SMS data to SRB2 , free all loopback data "); +563200,1153501183,0,0,PS1,DR,CedrProcDrTestLoopModeIDataReq_1,P_WARNING,swLogPrintf("TEST LOOP MODE I , loopback to CESM , but ESM is suspended , just free all PDU "); +563200,1153501184,0,0,PS1,DR,CedrProcDrTestLoopModeIDataReq_2,P_WARNING,swLogPrintf("TEST LOOP MODE I , no EPS bearer info for EPSID : %d , free loopback data "); +563200,1153505279,0,0,PS1,DR,CedrProcDrTestLoopModeIDataReq_3,P_WARNING,swLogPrintf("CE DR , TEST LOOP MODE I , does not match any TFT filter , discard all UL data "); +563200,1153505280,0,0,PS1,DR,CedrProcDrTestLoopModeIDataReq_not_sup_1,P_ERROR,swLogPrintf("CE DR , loop mode I , epsId : %d , not support loop CP data "); +563200,1153507584,0,0,PS1,DR,CedrUlRateCtrlSendPendingData_1,P_VALUE,swLogPrintf("CEDR , epsId : %d , allow to send UL PDU viaCp ( 1 ) / viaUp ( 0 ) : %d "); +563200,1153509376,0,0,PS1,DR,CedrFreeBearer_1,P_VALUE,swLogPrintf("CEDR , EPSID : %d , free bearer context "); +563200,1153511936,0,0,PS1,DR,CedrCheckAndTriggerProcForUlPdu_1,P_VALUE,swLogPrintf("CEDR , EPSID : %d , RAB reest proc : %d , or transUpPending : %d , can ' t send any UL PDU via CP "); +563200,1153513472,0,0,PS1,DR,CedrCheckAndTriggerProcForUlPdu_2,P_VALUE,swLogPrintf("CEDR , EPSID : %d , is suspended , but this UL PKG is exception data , pass to ESM "); +563200,1153515520,0,0,PS1,DR,CedrCheckAndTriggerProcForUlPdu_3,P_VALUE,swLogPrintf("CEDR , EPSID : %d , is suspended , can ' t send any UL PDU via CP "); +563200,1153518080,0,0,PS1,DR,CedrCheckAndTriggerProcForUlPdu_4,P_VALUE,swLogPrintf("CEDR , EPSID : %d , data VIA DRB , but DRB not setup , DrbId : %d , or drbSuspend : %d , pending "); +563200,1153520384,0,0,PS1,DR,CedrCheckAndTriggerProcForUlPdu_5,P_VALUE,swLogPrintf("CEDR , EPSID : %d , data VIA DRB , bearerSuspend : %d , anyDrbEst : %d , rabEstProc : %d , can ' t send SIG_CEMM_DR_REESTABLISH_REQ "); +563200,1153521664,0,0,PS1,DR,CedrSendUlPendingData_no_1,P_SIG,swLogPrintf("CE DR , epsId : %d , no UL pending PDU "); +563200,1153523712,0,0,PS1,DR,CedrSendUlPendingData_loopback_1,P_WARNING,swLogPrintf("CEDR , epsId : %d , send UL pending PDU , but LOOPBACK delay timer is running , not allow "); +563200,1153525760,0,0,PS1,DR,CedrSendUlPendingData_reest_delay_1,P_WARNING,swLogPrintf("CEDR , epsId : %d , send UL pending PDU , but RAB re-est delay timer is running , not allow "); +563200,1153527808,0,0,PS1,DR,CedrSendUlPendingData_1,P_WARNING,swLogPrintf("CEDR , epsId : %d , send UL pending PDU , but RATE CTRL not allow "); +563200,1153529856,0,0,PS1,DR,CedrSendUlPendingData_ratectrl_2,P_WARNING,swLogPrintf("CEDR , epsId : %d , send UL pending PDU , only except data allow , but no except data "); +563200,1153531904,0,0,PS1,DR,CedrSendUlPendingData_2,P_VALUE,swLogPrintf("CEDR , epsId : %d , send UL pending PDU , but BEARER STATE is not OK "); +563200,1153533952,0,0,PS1,DR,CedrSendUlPendingData_3,P_WARNING,swLogPrintf("CEDR , epsId : %d , pending UL pkg need to RE-ROHC "); +563200,1153538047,0,0,PS1,DR,CedrProcLoopbackTDelayTimerExpiry_1,P_WARNING,swLogPrintf("CE_UP_GOS_TEST_LOOPBACK_DELAY_TIMER expiry ; but no valid CloseTestModeInfo "); +563200,1153538048,0,0,PS1,DR,CedrProcLoopbackTDelayTimerExpiry_2,P_WARNING,swLogPrintf("TEST LOOP mode : %d ; not support TDelay timer "); +563200,1153540096,0,0,PS1,DR,CedrProcUlDataReqSig_1,P_WARNING,swLogPrintf("CID : %d , no bearer context , maybe freed "); +563200,1153542144,0,0,PS1,DR,CedrProcDrTestLoopDataReqSig_1,P_WARNING,swLogPrintf("Not support Test loop back mode : %d "); +563200,1153544448,0,0,PS1,DR,CedrProcDrPsDataPlaneTransReqSig_1,P_WARNING,swLogPrintf("CEDR , UE support OPT type : %d , NW support OPT type : %d , data can ' t trans to UP "); +563200,1153546496,0,0,PS1,DR,CedrProcDrPsDataPlaneTransReqSig_2,P_WARNING,swLogPrintf("CEDR , transfer to UP , but bearerSuspend : %d , or RAB re-est is ongoing : %d , pending "); +563200,1153550335,0,0,PS1,DR,CedrProcDrPsDataPlaneTransReqSig_3,P_WARNING,swLogPrintf("CEDR , not support UP -> CP now "); +563200,1153550336,0,0,PS1,DR,CedrProcDrPdcpDlNonIpDataIndIsrSig_1,P_ERROR,swLogPrintf("EPS ID : %d , no such bearer info , can ' t FWD NON IP pkg "); +563200,1153552384,0,0,PS1,DR,CedrSetNetifFastChkInfo_ppp_1,P_SIG,swLogPrintf("CEDR , BR : %d , set PPP fast check info "); +563200,1153554432,0,0,PS1,DR,CedrSetNetifFastChkInfo_eth_1,P_SIG,swLogPrintf("CEDR , BR : %d , set ETH fast check info "); +563200,1153556480,0,0,PS1,DR,CedrProcDrSetNetifInfoReqSig_cid_w_1,P_WARNING,swLogPrintf("CE DR , set eth fast path for v4v6Cid : %d , but can ' t find BR "); +563200,1153558528,0,0,PS1,DR,CedrProcDrSetNetifInfoReqSig_v4cid_w_1,P_WARNING,swLogPrintf("CE DR , set eth fast path for v4Cid : %d , but can ' t find BR "); +563200,1153560576,0,0,PS1,DR,CedrProcDrSetNetifInfoReqSig_v6cid_w_1,P_WARNING,swLogPrintf("CE DR , set eth fast path for v6Cid : %d , but can ' t find BR "); +563200,1153562624,0,0,PS1,DR,CedrProcDrSetNetifInfoReqSig_ppp_cid_w_1,P_WARNING,swLogPrintf("CE DR , set PPP fast path for v4v6Cid : %d , but can ' t find BR "); +563200,1153564672,0,0,PS1,DR,CedrProcDrSetNetifInfoReqSig_ppp_v4cid_w_1,P_WARNING,swLogPrintf("CE DR , set PPP fast path for v4Cid : %d , but can ' t find BR "); +563200,1153566720,0,0,PS1,DR,CedrProcDrSetNetifInfoReqSig_ppp_v6cid_w_1,P_WARNING,swLogPrintf("CE DR , set PPP fast path for v6Cid : %d , but can ' t find BR "); +563200,1153568768,0,0,PS1,DR,CedrAnySuspendULPendingData_1,P_VALUE,swLogPrintf("CE DR , EPSID : %d , has UL pending data , but APN RATE CTRL "); +563200,1153570816,0,0,PS1,DR,CedrAnySuspendULPendingData_2,P_VALUE,swLogPrintf("CE DR , EPSID : %d , has UL pending data , but PLMN RATE CTRL "); +563200,1153572864,0,0,PS1,DR,CedrStartRabReestDelayTimer_s_1,P_SIG,swLogPrintf("CE DR , start RabReestDelayTimer with seconds : %d "); +563200,1153574912,0,0,PS1,DR,CedrStartRabReestDelayTimer_w_1,P_WARNING,swLogPrintf("CE DR , RabReestDelayTimer is already started , rabEstProc : %d , not need to restart "); +563200,1153579007,0,0,PS1,DR,CedrProcRabReestDelayTimerExpiry_info_1,P_INFO,swLogPrintf("CE DR , RabReestDelayTimer expiry "); +563200,1153579008,0,0,PS1,DR,CedrProcRabReestDelayTimerExpiry_w_1,P_WARNING,swLogPrintf("CE DR , RAB re-est proc : %d , not right "); +563200,1153583103,0,0,PS1,DR,CedrProcRabReestDelayTimerExpiry_trans_up_1,P_SIG,swLogPrintf("CE DR , CP->UP , trigger RAB re-est "); +563200,1153583360,0,0,PS1,DR,CedrAllocDlCpDataMem_1,P_VALUE,swLogPrintf("EPS : %d , configed ROHC , alloc DL pkg buf size : %d "); +563200,1153585408,0,0,PS1,DR,CedrDlCtrlPlaneDataInd_3,P_VALUE,swLogPrintf("CID : %d , RECV DL IP PKG , Len : %d "); +563200,1153587200,0,0,PS1,DR,CedrDlCtrlPlaneDataInd_4,P_WARNING,swLogPrintf("CID : %d , TCPIP RECV DL IP PKG ; FAIL "); +563200,1153589504,0,0,PS1,DR,CedrDlCtrlPlaneDataInd_5,P_VALUE,swLogPrintf("CID : %d , RECV DL NON IP PKG , Len : %d "); +563200,1153591296,0,0,PS1,DR,CedrDlUserPlaneDataIndIsr_1,P_ERROR,swLogPrintf("EPS ID : %d , no such bearer info , can ' t FWD this UP DL pkg "); +563200,1153593856,0,0,PS1,DR,CedrDlUserPlaneDataIndIsr_2,P_VALUE,swLogPrintf("CID : %d , RECV DL IP PKG via UP , pkgNum : %d , totalLen : %d "); +563200,1153595392,0,0,PS1,DR,CedrUlPkgListDataReq_1,P_WARNING,swLogPrintf("No EPS bearer found for CID : %d , free all UL pkgs "); +563200,1153597440,0,0,PS1,DR,CedrUlPkgListDataReq_2,P_VALUE,swLogPrintf("EpsId : %d , need to do Rate Ctrl , or TFT , just FWD to CEDR "); +563200,1153600000,0,0,PS1,DR,CedrUlPkgListDataReq_3,P_VALUE,swLogPrintf("EpsId : %d , via CP , but bearer suspend : %d , or RAB re-est proc : %d , just FWD UL data to CEDR "); +563200,1153601536,0,0,PS1,DR,CedrUlPkgListDataReqSort_no_br_1,P_WARNING,swLogPrintf("No EPS bearer found for CID : %d , free all UL pkgs "); +563200,1153603584,0,0,PS1,DR,CedrUlPkgListDataReqSort_2,P_VALUE,swLogPrintf("EpsId : %d , need to do Rate Ctrl , or TFT , just FWD to CEDR "); +563200,1153606144,0,0,PS1,DR,CedrUlPkgListDataReqSort_3,P_VALUE,swLogPrintf("EpsId : %d , via CP , but bearer suspend : %d , or RAB re-est proc : %d , just FWD UL data to CEDR "); +563200,1153607936,0,0,PS1,DR,CedrUlPkgListDataReqFromLwip_1,P_VALUE,swLogPrintf("CID : %d , SEND UL IP PKG list , total Len : %d "); +563200,1153610240,0,0,PS1,DR,CedrUlPkgListDataReqSortFromFast_1,P_VALUE,swLogPrintf("CID : %d , UL fast path SEND UL IP PKG list , shortTotalLen : %d , longTotalLen : %d "); +563200,1153611776,0,0,PS1,DR,CedrOneUlPkgDataReq_1,P_ERROR,swLogPrintf("No EPS bearer found for CID : %d , free this one UL pkg "); +563200,1153613824,0,0,PS1,DR,CedrOneUlPkgDataReq_2,P_ERROR,swLogPrintf("CID : %d , UL data request via CP , but bearer is via UP , failed "); +563200,1153616128,0,0,PS1,DR,CedrOneUlPkgDataReq_3,P_VALUE,swLogPrintf("CID : %d , SEND UL ONE PKG , Len : %d "); +563200,1153617920,0,0,PS1,DR,CedrUpdateTftPacketFilterlist_nobr_e_1,P_ERROR,swLogPrintf("CE DR , CID : %d , can ' t find pBr , can ' t update TFT "); +563200,1153620224,0,0,PS1,DR,CedrUpdateTftPacketFilterlist_nobr_e_2,P_ERROR,swLogPrintf("CE DR , dedicated BR : %d , can ' t find linked default BR : %d , can ' t update TFT "); +563200,1153622016,0,0,PS1,DR,CedrProcBearerActivateIndSig_1,P_VALUE,swLogPrintf("EpsId : %d , is NON-IP type "); +563200,1153624320,0,0,PS1,DR,CedrProcBearerActivateIndSig_linked_1,P_ERROR,swLogPrintf("CE DR , EpsId : %d , is dedicated bearer , but linked EPS ID : %d , is not right "); +563200,1153626368,0,0,PS1,DR,CedrProcBearerActivateIndSig_linked_2,P_ERROR,swLogPrintf("CE DR , EpsId : %d , is dedicated bearer , but linked EPS ID : %d , can ' t find the entity "); +563200,1153628672,0,0,PS1,DR,CedrProcBearerActivateIndSig_2,P_WARNING,swLogPrintf("EpsId : %d , config ApnRateCtrl , but time unit is %d , maxUlRate is %d , cancel ApnRateCtrl! "); +563200,1153630464,0,0,PS1,DR,CedrProcBearerActivateIndSig_3,P_WARNING,swLogPrintf("EpsId : %d , config ApnExceptRateCtrl , but time unit ( %d ) is UNRESTRICTED "); +563200,1153632256,0,0,PS1,DR,CedrProcBearerActivateIndSig_4,P_VALUE,swLogPrintf("EpsId : %d , configed ROHC "); +563200,1153634816,0,0,PS1,DR,CedrProcBearerModifyIndSig_1,P_WARNING,swLogPrintf("EpsId : %d , modify ApnRateCtrl , but time unit is %d , maxUlRate is %d , cancel ApnRateCtrl! "); +563200,1153636608,0,0,PS1,DR,CedrProcBearerDeactivateIndSig_1,P_WARNING,swLogPrintf("EPSID : %d , deactived , but DRB : %d is not released , pending free the bearer "); +563200,1153638656,0,0,PS1,DR,CedrProcBearerResumeIndSig_suspend,P_INFO,swLogPrintf("CE DR , bearer is not suspended , with rrcRelAndSuspend is %d , anyDrbEst is %d "); +563200,1153642495,0,0,PS1,DR,CedrProcBearerResumeIndSig_s_1,P_SIG,swLogPrintf("CE DR , RAB re-est wait for resume , try check still any UL PDU pending "); +563200,1153644543,0,0,PS1,DR,CedrProcBearerResumeIndSig_w_1,P_WARNING,swLogPrintf("CE DR , BR resume , but RAB need re-est later , retry re-est after delay timer "); +563200,1153646591,0,0,PS1,DR,CedrProcBearerResumeIndSig_s_up_1,P_SIG,swLogPrintf("CE DR , BR resume , CP->UP is pending , trigger RAB re-est "); +563200,1153648639,0,0,PS1,DR,CedrProcDrReestablishRspSig_w_2,P_WARNING,swLogPrintf("CE DR , RAB re-est succ , but DRB not setup , abnormal , start a delay retry timer "); +563200,1153648896,0,0,PS1,DR,CedrProcDrReestablishRspSig_w_1,P_WARNING,swLogPrintf("CE DR , DRB ested : %d , or rabEstProc succ : %d , but CemmDrReestablishRsp not succ , not right "); +563200,1153650944,0,0,PS1,DR,CedrProcDrReestablishRspSig_trans_up_w_1,P_WARNING,swLogPrintf("CE DR , Rab re-est failed , cause : %d , already try : %d times , tansfer to UP failed "); +563200,1153652736,0,0,PS1,DR,CedrProcDrReestablishRspSig_retry_discard_1,P_WARNING,swLogPrintf("CE DR , RAB re-est more times : %d , still failed , free all pending UL data "); +563200,1153654784,0,0,PS1,DR,CedrProcDrReestablishRspSig_retry_discard_2,P_WARNING,swLogPrintf("CE DR , free all EpsId : %d , pending data "); +563200,1153658879,0,0,PS1,DR,CedrProcDrReestablishRspSig_delay_1,P_SIG,swLogPrintf("CE DR , Rab re-est failed , need start a dealy timer "); +563200,1153660927,0,0,PS1,DR,CedrProcDrReestablishRspSig_wait_resume_1,P_SIG,swLogPrintf("CE DR , Rab re-est failed , need wait for resume "); +563200,1153662975,0,0,PS1,DR,CedrProcDrReestablishRspSig_wait_resume_2,P_WARNING,swLogPrintf("CE DR , Rab re-est failed , need wait for resume , but bearer not suspended in DR , here start a a retry timer "); +563200,1153662976,0,0,PS1,DR,CedrProcDrReestablishRspSig_unknown_1,P_WARNING,swLogPrintf("CE DR , Rab re-est failed , with unknown cause : %d , start a dealy timer "); +563200,1153665024,0,0,PS1,DR,CedrDrbSetupReq_S_1,P_SIG,swLogPrintf("CE DR , RAB re-est wait for resume , or retry later : %d , but DRB setup , change to EST SUCC "); +563200,1153667328,0,0,PS1,DR,CedrDrbSetupReq_1,P_VALUE,swLogPrintf("CE DR , EPSID : %d , DRB : %d , configed ROHC "); +563200,1153669632,0,0,PS1,DR,CedrDrbConfigReq_1,P_VALUE,swLogPrintf("DR , DRBID : %d , EPSID : %d , LCID : %d , config not changed "); +563200,1153671424,0,0,PS1,DR,CedrDrbReestablishReq_1,P_VALUE,swLogPrintf("CE DR , epsId : %d , DRB : %d , RRC re-establishment , need to reset ROHC "); +565248,1157629952,0,0,PS1,CERRC,CerrcUpdateReleaseVersion_errRel,P_ERROR,swLogPrintf("Unsupport Release Version ( %d ) ! ! "); +565248,1157632256,0,0,PS1,CERRC,CerrcUpdateReleaseVersion_rel,P_INFO,swLogPrintf("Modify Release Version from %e to %e! "); +565248,1157634048,0,0,PS1,CERRC,CerrcUpdateUeCategory_Cat1,P_ERROR,swLogPrintf("Unsupport Category ( %d ) ! ! "); +565248,1157636608,0,0,PS1,CERRC,CerrcUpdateUeCategory_Cat,P_INFO,swLogPrintf("Modify UE Category from %e to %e , asRelease is %e! "); +565248,1157638912,0,0,PS1,CERRC,CerrcFillIntraNcellDBIntoStatusCnf_d1,P_INFO,swLogPrintf("QENG Intra phyCellId = %d , rsrp = %d , rsrq = %d , srxlev = %d "); +565248,1157640960,0,0,PS1,CERRC,CerrcFillInterNcellDBIntoStatusCnf_d1,P_INFO,swLogPrintf("QENG InterFreq = %ld , phyCellId = %d , rsrp = %d , rsrq = %d "); +565248,1157643008,0,0,PS1,CERRC,CerrcFillSib5InterFreqIntoStatusCnf_d1,P_INFO,swLogPrintf("QENG InterFreq = %ld , phyCellId = %d , rsrp = %d , rsrq = %d "); +565248,1157644288,0,0,PS1,CERRC,CerrcHandleCerrcCcmSetParamReq_meas,P_WARNING,swLogPrintf("Modify disableNCellMeas to ( %d ) ! ! "); +565248,1157646336,0,0,PS1,CERRC,CerrcHandleCerrcCcmSetParamReq_abc,P_WARNING,swLogPrintf("Modify enableABCheck to ( %d ) ! ! "); +565248,1157648384,0,0,PS1,CERRC,CerrcHandleCerrcCcmSetParamReq_weakCell,P_WARNING,swLogPrintf("Modify weakCellOpt to ( %d ) ! ! "); +565248,1157650432,0,0,PS1,CERRC,CerrcHandleCerrcCcmSetParamReq_qRxLevMin,P_WARNING,swLogPrintf("Modify qRxLevMinWeakCell to ( %d ) ! ! "); +565248,1157652480,0,0,PS1,CERRC,CerrcHandleCerrcCcmSetParamReq_reselToWeakNcellOpt,P_WARNING,swLogPrintf("Modify reselToWeakNcellOpt to ( %d ) ! ! "); +565248,1157654528,0,0,PS1,CERRC,CerrcHandleCerrcCcmSetParamReq_DeltaP,P_WARNING,swLogPrintf("The relaxMonitorDeltaP ( %d ) is out of range , set it to MAX value 15 ! "); +565248,1157656576,0,0,PS1,CERRC,CerrcHandleCcmEventStatisReq_1,P_VALUE,swLogPrintf("Unexpected set parameter type : %e "); +565248,1157658624,0,0,PS1,CERRC,CerrcGetBandIndexFromDlEarfcn_invalid,P_INFO,swLogPrintf("EARFCN ( %d ) is not belonging to any band !! "); +565248,1157660672,0,0,PS1,CERRC,CerrcGetBandIndexFromBand_invalid,P_INFO,swLogPrintf("BAND ( %d ) is not supported !! "); +565248,1157662720,0,0,PS1,CERRC,CerrcGetBandFromDlEarfcn_invalid,P_INFO,swLogPrintf("EARFCN ( %d ) is not belonging to any supported RF band !! "); +565248,1157664768,0,0,PS1,CERRC,CerrcCheckIfBandSupported_false,P_INFO,swLogPrintf("Band ( %d ) is not supported !! "); +565248,1157667072,0,0,PS1,CERRC,CerrcCheckIfDlEarfcnSupportedByMFBI_true,P_INFO,swLogPrintf("EARFCN ( %d ) is supported by multi-Bands ( %d ) !! "); +565248,1157669120,0,0,PS1,CERRC,CerrcAddIntraFreqCellToDB_info1,P_INFO,swLogPrintf("INTRA FREQ CELL ( %d , %d ) has existed in intra neighcell DB , update its value. "); +565248,1157671168,0,0,PS1,CERRC,CerrcAddIntraFreqCellToDB_info2,P_INFO,swLogPrintf("Add INTRA FREQ CELL ( %d , %d ) into intra neighcell DB. "); +565248,1157673216,0,0,PS1,CERRC,CerrcAddIntraFreqCellToDB_info3,P_INFO,swLogPrintf("Remove the oldest cell and add INTRA FREQ CELL ( %d , %d ) into intra neighcell DB. "); +565248,1157675264,0,0,PS1,CERRC,CerrcAddInterFreqCellToDB_info1,P_INFO,swLogPrintf("INTER FREQ CELL ( %d , %d ) has existed in inter neighcell DB , update its value. "); +565248,1157677312,0,0,PS1,CERRC,CerrcAddInterFreqCellToDB_info2,P_INFO,swLogPrintf("Add INTER FREQ CELL ( %d , %d ) into inter neighcell DB. "); +565248,1157679360,0,0,PS1,CERRC,CerrcAddInterFreqCellToDB_info3,P_INFO,swLogPrintf("Remove the oldest cell and add INTER FREQ CELL ( %d , %d ) into inter neighcell DB. "); +565248,1157681664,0,0,PS1,CERRC,CerrcRefreshIntraCellsInDB_del,P_INFO,swLogPrintf("Cell ( %d , %d ) has expired %d ms , remove it from intra neighcell DB. "); +565248,1157683712,0,0,PS1,CERRC,CerrcRefreshInterCellsInDB_del,P_INFO,swLogPrintf("Cell ( %d , %d ) has expired %d ms , remove it from inter neighcell DB. "); +565248,1157685504,0,0,PS1,CERRC,CerrcRemoveInvalidSib1Info_del,P_INFO,swLogPrintf("Cell ( %d , %d ) has expired 24 hours , remove it from history SIB1 info DB "); +565248,1157689343,0,0,PS1,CERRC,CerrcCreateCellReselContext_exist,P_WARNING,swLogPrintf("CerrcCellReselectionContext already exists! "); +565248,1157689600,0,0,PS1,CERRC,CerrcStoreReselSourceCell_add,P_INFO,swLogPrintf("Add new source cell ( %d , %d ) "); +565248,1157691648,0,0,PS1,CERRC,CerrcStoreReselSourceCell_rmv,P_INFO,swLogPrintf("Remove Cell ( %d , %d ) in reselection source cell list due to expiry 20 mins "); +565248,1157693952,0,0,PS1,CERRC,CerrcStoreReselSourceCell_update,P_INFO,swLogPrintf("Cell ( %d , %d ) is in the reselection source cell list , numOfCell ( %d ) "); +565248,1157696000,0,0,PS1,CERRC,CerrcStoreReselSourceCell_add2,P_INFO,swLogPrintf("Add new source cell ( %d , %d ) , numOfCell ( %d ) "); +565248,1157699583,0,0,PS1,CERRC,CerrcStoreReselSourceCell_full,P_WARNING,swLogPrintf("The reselection source cell array is full! "); +565248,1157699840,0,0,PS1,CERRC,CerrcCheckIfInSourceCellList_rmv,P_INFO,swLogPrintf("Remove Cell ( %d , %d ) in reselection source cell list due to expiry 20 mins "); +565248,1157702144,0,0,PS1,CERRC,CerrcCheckIfInSourceCellList_true,P_INFO,swLogPrintf("Cell ( %d , %d ) is in the reselection source cell list , numOfCell ( %d ) "); +565248,1157703936,0,0,PS1,CERRC,CerrcProcessReselEvaluation_exit,P_INFO,swLogPrintf("Reselection evaluation is NOT avaliable due to measOngoing ( %d ) or cellLockedMode : %e "); +565248,1157706240,0,0,PS1,CERRC,CerrcProcessReselEvaluation_worseTargetCell,P_SIG,swLogPrintf("Target Cell ( %d , %d ) RSRP is worse than serving cell ( %d ) dbm , NOT reselect to it. "); +565248,1157708800,0,0,PS1,CERRC,CerrcCalcServCellEvalTime_time,P_INFO,swLogPrintf("coverageType %e , drxCycleInMs %d ms , eDrxCycle %d s , nservTimeLength %d ms , escapeTimeLength %d s! "); +565248,1157709824,0,0,PS1,CERRC,CerrcCalcServCellEvalTime_gcf,P_INFO,swLogPrintf("Shorten the escapeTimeLength to %d s for GCF test! "); +565248,1157713919,0,0,PS1,CERRC,CerrcProcessServCellMeasInd_ptwInd,P_WARNING,swLogPrintf("ptwInd sent by L1 is changed under non-eDRX "); +565248,1157713920,0,0,PS1,CERRC,CerrcUpdateCriterionSTime_fail,P_INFO,swLogPrintf("CriterionS starts to be not fulfilled , criterionSTime ( %d ) "); +565248,1157715968,0,0,PS1,CERRC,CerrcProcessIfSCriterionFail_start,P_INFO,swLogPrintf("unsuitableStartTime ( %d ) is started!!! "); +565248,1157720063,0,0,PS1,CERRC,CerrcProcessIfSCriterionFail_stop,P_INFO,swLogPrintf("CriterionS is fulfilled again , stop serving cell unsuitable timer !!! "); +565248,1157720832,0,0,PS1,CERRC,CerrcStoreServCellMeasInd_info,P_INFO,swLogPrintf("Serving Cell RSRP ( %d ) / RSRQ ( %d ) , after L3 filter RSRP ( %d ) / RSRQ ( %d ) "); +565248,1157723904,0,0,PS1,CERRC,CerrcStoreServCellMeasInd_end,P_VALUE,swLogPrintf("Serving CELL ( %d , %d ) : Srxlev ( %d ) , sQual ( %d ) , rank ( %d ) , qRxLevMin ( %d ) , qOffsetTemp ( %d ) , qHyst ( %d ) "); +565248,1157724928,0,0,PS1,CERRC,CerrcProcessIntraCellMeasInd_intra,P_SIG,swLogPrintf("INTRA FREQ CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1157726208,0,0,PS1,CERRC,CerrcProcessInterCellMeasInd_intra,P_WARNING,swLogPrintf("Received intra frequency ( %d ) in inter meas , skip it ! "); +565248,1157729024,0,0,PS1,CERRC,CerrcProcessInterCellMeasInd_inter,P_SIG,swLogPrintf("INTER FREQ CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1157730304,0,0,PS1,CERRC,CerrcProcessInterCellMeasInd_err,P_WARNING,swLogPrintf("Cannot find Inter frequency ( %d ) in DB , skip it ! "); +565248,1157733376,0,0,PS1,CERRC,CerrcProcessServCellMeasInd_conn,P_SIG,swLogPrintf("CONNECTED : SERV CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) , SNR ( %d ) "); +565248,1157735424,0,0,PS1,CERRC,CerrcProcessServCellMeasInd_idle,P_SIG,swLogPrintf("IDLE : SERV CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) , SNR ( %d ) "); +565248,1157738495,0,0,PS1,CERRC,CerrcProcessServCellMeasInd_deact,P_WARNING,swLogPrintf("Received ServCellMeasInd in CERRC_DEACTIVATED! "); +565248,1157738752,0,0,PS1,CERRC,CerrcProcessCellReselSib1_s,P_INFO,swLogPrintf("Reselect Target Cell is not suitable due to criterionS fail : Srxlev ( %d ) , Squal ( %d ) : "); +565248,1157741312,0,0,PS1,CERRC,CerrcProcessCellReselNcellSysInfoInd_mismatch,P_INFO,swLogPrintf("Cell mismatch! Target Cell ( %d , %d ) but receive Cell ( %d , %d ) BCH , just ignore it! "); +565248,1157743872,0,0,PS1,CERRC,CerrcProcessCellReselectCnf_servCell,P_WARNING,swLogPrintf("CELL RESELECTION from CELL ( %d , %d ) to CELL ( %d , %d ) , TAC ( 0x%X ) -> TAC ( 0x%X ) "); +565248,1157746687,0,0,PS1,CERRC,CerrcProcessCellReselectCnf_else,P_WARNING,swLogPrintf("CephyReselectCnf : Should never enter this branch ! "); +565248,1157746944,0,0,PS1,CERRC,CerrcStartCellReselFailureRestore_bar,P_INFO,swLogPrintf("cell reselection back to source cell , barredByPlmn is %d , barredByTa is %d "); +565248,1157749248,0,0,PS1,CERRC,CerrcStartCellReselFailureRestore_entry,P_INFO,swLogPrintf("forceReselection : %d , triggerSource : %d , CellReselState : %d "); +565248,1157752831,0,0,PS1,CERRC,CerrcStartCellReselFailureRestore_error,P_ERROR,swLogPrintf("Incorrect trigger source of cell reselection "); +565248,1157753088,0,0,PS1,CERRC,CerrcHandleCephyStartRelectionInd_else,P_WARNING,swLogPrintf("Received CephyStartRelectionInd in wrong RrcState %e , CsrState %e "); +565248,1157754880,0,0,PS1,CERRC,CerrcResetFoundCellList_else,P_WARNING,swLogPrintf("Incorrect CsrState %e "); +565248,1157758975,0,0,PS1,CERRC,CerrcHandlePendingActReq_1,P_INFO,swLogPrintf("Handle pending CerrcActReq. "); +565248,1157758976,0,0,PS1,CERRC,CerrcHandleCerrcActReq_invalid,P_WARNING,swLogPrintf("Received CerrcActReq with requestedPLMNValid ( %d ) or no band / freq ! "); +565248,1157761280,0,0,PS1,CERRC,CerrcHandleCerrcActReq_state,P_WARNING,swLogPrintf("Received CerrcActReq in wrong RrcState %e , or RccState %e ! "); +565248,1157763328,0,0,PS1,CERRC,CerrcHandleCerrcActReq_freqBand,P_WARNING,swLogPrintf("Received CerrcActReq with no valid numOfFreq ( %d ) and numOfBand ( %d ) ! "); +565248,1157765120,0,0,PS1,CERRC,CerrcHandleCerrcActReq_phyCellId,P_WARNING,swLogPrintf("Received CerrcActReq with no numOfFreq but valid phyCellId ( %d ) ! "); +565248,1157769215,0,0,PS1,CERRC,CerrcHandleCerrcActReq_buff1,P_INFO,swLogPrintf("Receive CerrcActReq while waiting for ecphyDeactCnf , buffer it "); +565248,1157771263,0,0,PS1,CERRC,CerrcHandleCerrcActReq_buff2,P_INFO,swLogPrintf("Receive CerrcActReq during cell selection or cell reselection , need to deact L1 first "); +565248,1157773311,0,0,PS1,CERRC,CerrcHandleCerrcActReq_err,P_ERROR,swLogPrintf("Receive CerrcActReq during NORMAL FG PLMN , but not waiting for MM response ! "); +565248,1157775359,0,0,PS1,CERRC,CerrcHandleCerrcActReq_buff3,P_INFO,swLogPrintf("Receive CerrcActReq during FG PLMN , need to deact L1 first "); +565248,1157775616,0,0,PS1,CERRC,CerrcHandleCerrcActReq_freqLock,P_WARNING,swLogPrintf("CerrcActReq : Invalid freq lock info with numOfFreq ( %d ) , numOfBand ( %d ) "); +565248,1157777408,0,0,PS1,CERRC,CerrcFillOosFreqList_lock,P_INFO,swLogPrintf("Only locked frequency ( %d ) in CerrcActInd "); +565248,1157780224,0,0,PS1,CERRC,CerrcFillOosFreqList_freq,P_INFO,swLogPrintf("CerrcFillOosFreqList : numOfFreq ( %d ) , freq [ 0 ] = %d , freq [ 1 ] = %d , freq [ 2 ] = %d "); +565248,1157783551,0,0,PS1,CERRC,CerrcFillOosFreqList_else,P_INFO,swLogPrintf("No oosFreqList in CerrcActInd , due to not performed AS cell search. "); +565248,1157783552,0,0,PS1,CERRC,CerrcSendCerrcActCnf_status,P_INFO,swLogPrintf("CerrcActCnf : actStatus %e "); +565248,1157785600,0,0,PS1,CERRC,CerrcSendCerrcActInd_status,P_INFO,swLogPrintf("CerrcActInd : actStatus = %e "); +565248,1157789695,0,0,PS1,CERRC,CerrcStoreInterFreqInCellSearchContext_else,P_WARNING,swLogPrintf("CerrcCellSearchContext has not been created !! "); +565248,1157791743,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_no,P_INFO,swLogPrintf("No valid last camped cell info. "); +565248,1157792512,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_cell,P_INFO,swLogPrintf("Fail to directly camp after SIB1 due to last CELL ( %d , %d ) , Current CELL ( %d , %d ) "); +565248,1157794048,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_tag,P_INFO,swLogPrintf("Fail to directly camp after SIB1 due to sysInfoValueTag change from ( %d ) to ( %d ) "); +565248,1157796096,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_numSi,P_INFO,swLogPrintf("Fail to directly camp after SIB1 due to siSchdNumInfo change from ( %d ) to ( %d ) "); +565248,1157798144,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_SiList,P_INFO,swLogPrintf("Fail to directly camp after SIB1 due to sysInfoValueTagSIList change from ( 0x%x ) to ( 0x%x ) "); +565248,1157800192,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_bitmap,P_INFO,swLogPrintf("Fail to directly camp after SIB1 due to last siValidBitmap ( 0x%x ) ! = new requiredBitmap ( 0x%x ) "); +565248,1157801984,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_24h,P_INFO,swLogPrintf("Fail to directly camp after SIB1 due to exceed 24 hours , siUpdateTime ( %d ) "); +565248,1157806079,0,0,PS1,CERRC,CerrcCheckIfCampDirectlyAfterSib1_true,P_INFO,swLogPrintf("Camp directly according to last camped cell info , do not request SIB2 and other SIBs ! "); +565248,1157806336,0,0,PS1,CERRC,CerrcStartSuitableCellCamp_servCell,P_WARNING,swLogPrintf("CELL SELECTION to CELL ( %d , %d ) "); +565248,1157810175,0,0,PS1,CERRC,CerrcCheckIfCampDirectly_phy,P_INFO,swLogPrintf("Cannot camp directly when leaving CONNECTED , due to PHY reset. "); +565248,1157812223,0,0,PS1,CERRC,CerrcCheckIfCampDirectly_bar,P_INFO,swLogPrintf("Cannot camp directly when leaving CONNECTED , due to cell barred. "); +565248,1157814271,0,0,PS1,CERRC,CerrcCheckIfCampDirectly_si,P_INFO,swLogPrintf("Cannot camp directly when leaving CONNECTED , due to SI modification. "); +565248,1157816319,0,0,PS1,CERRC,CerrcCheckIfCampDirectly_suitable,P_INFO,swLogPrintf("Cannot camp directly when leaving CONNECTED , due to cell is NOT suitable. "); +565248,1157816832,0,0,PS1,CERRC,CerrcCheckIfCampDirectly_criterionS,P_INFO,swLogPrintf("Cannot camp directly when leaving CONNECTED , due to criterionS fail , Srxlev ( %d ) , Squal ( %d ) or missing SIB1 / 2 siValidBitmap ( 0x%x ) "); +565248,1157818368,0,0,PS1,CERRC,CerrcSendCephyCellSearchReq_lock,P_WARNING,swLogPrintf("Start locked frequency cell search , mode %e "); +565248,1157821696,0,0,PS1,CERRC,CerrcHandleCephyCellSearchCnf_cell,P_SIG,swLogPrintf("CELL FOUND : cellDetected ( %d ) , highLevelDone ( %d ) , CELL ( %d , %d ) , RSRP ( %d ) , RSRQ ( %d ) "); +565248,1157824511,0,0,PS1,CERRC,CerrcHandleCephyCellSearchCnf_ret,P_INFO,swLogPrintf("Receive CephyCellSearchCnf while waiting for CephyDeactCnf "); +565248,1157824512,0,0,PS1,CERRC,CerrcHandleCephyCellSearchCnf_csr,P_WARNING,swLogPrintf("Received CephyCellSearchCnf in wrong CsrState %e "); +565248,1157826560,0,0,PS1,CERRC,CerrcHandleCephyCellSearchCnf_rcc,P_WARNING,swLogPrintf("Received CephyCellSearchCnf in wrong RccState %e "); +565248,1157828608,0,0,PS1,CERRC,CerrcHandleCephyCellSearchCnf_rrc,P_WARNING,swLogPrintf("Received CephyCellSearchCnf in wrong RrcState %e "); +565248,1157830656,0,0,PS1,CERRC,CerrcStartLeaveConnCellSearch_redirect,P_SIG,swLogPrintf("Redirect to EARFCN ( %d ) "); +565248,1157832704,0,0,PS1,CERRC,CerrcProcessCellSearchNoCellFound_ics,P_INFO,swLogPrintf("No cell found with icsType %e ! "); +565248,1157836032,0,0,PS1,CERRC,CerrcProcessReestSearchNoCellFound_suppBand,P_INFO,swLogPrintf("Total support numOfBand ( %d ) , band [ 0 ] = %d , band [ 1 ] = %d , band [ 2 ] = %d , band [ 3 ] = %d , band [ 4 ] = %d "); +565248,1157837568,0,0,PS1,CERRC,CerrcProcessReestSearchNoCellFound_band,P_SIG,swLogPrintf("%d th round of band search during RRC re-establishment , numOfBand ( %d ) , band [ 0 ] = %d , band [ 1 ] = %d "); +565248,1157839616,0,0,PS1,CERRC,CerrcUpdateGuti_gummei,P_INFO,swLogPrintf("gutiElemType is GUTI_GUMMEI , MMEC ( 0x%x ) , MMEGI ( 0x%x ) , MCC ( 0x%x ) , MNC ( 0x%x ) "); +565248,1157841152,0,0,PS1,CERRC,CerrcUpdateGuti_stmsi,P_INFO,swLogPrintf("gutiElemType is GUTI_STMSI , MMEC ( 0x%x ) , mTMSI ( 0x%x ) "); +565248,1157844991,0,0,PS1,CERRC,CerrcUpdateGuti_invalid,P_INFO,swLogPrintf("gutiElemType is GUTI_INVALID "); +565248,1157844992,0,0,PS1,CERRC,CerrcUpdateSimInfo_ac,P_SIG,swLogPrintf("UE accessClass is 0x%X , AC15|AC14|AC13...AC2|AC1|AC0 "); +565248,1157849087,0,0,PS1,CERRC,CerrcUpdateSimInfo_len0,P_WARNING,swLogPrintf("simInfoPresent is TRUE , but lengthOfImsi is 0 ! "); +565248,1157849088,0,0,PS1,CERRC,CerrcUpdateNasExtDrxConfigNB_invalid,P_ERROR,swLogPrintf("Invalid eDrx cycle : %d "); +565248,1157851392,0,0,PS1,CERRC,CerrcUpdateNasExtDrxConfigNB_end,P_INFO,swLogPrintf("Setup eDRX , eDrxCycle ( %d ) , ptwLength ( %d ) "); +565248,1157853184,0,0,PS1,CERRC,CerrcUpdateNasExtDrxConfig_invalid,P_ERROR,swLogPrintf("Invalid eDrx cycle : %d "); +565248,1157855488,0,0,PS1,CERRC,CerrcUpdateNasExtDrxConfig_end,P_INFO,swLogPrintf("Setup eDRX , eDrxCycle ( %d ) , ptwLength ( %d ) "); +565248,1157859327,0,0,PS1,CERRC,CerrcReleaseExtDrxConfig_end,P_INFO,swLogPrintf("Release eDRX configuration ! "); +565248,1157860352,0,0,PS1,CERRC,CerrcHandleCerrcNasInfoUpdateReq_plmn,P_INFO,swLogPrintf("Update requestedPlmn from ( %X-%X ) to ( %X-%X ) , current requestedPlmnValid ( %d ) "); +565248,1157861632,0,0,PS1,CERRC,CerrcHandleCerrcSelectedPlmnInd_update,P_WARNING,swLogPrintf("Update selectedPlmnIdx from ( %d ) to ( %d ) ! "); +565248,1157863680,0,0,PS1,CERRC,CerrcHandleCerrcSelectedPlmnInd_err,P_WARNING,swLogPrintf("NAS selected PLMN ( %X-%X ) is NOT included in CerrcActCnf / CerrcActInd! "); +565248,1157867519,0,0,PS1,CERRC,CerrcCreateSourceCell_exist,P_WARNING,swLogPrintf("SourceCell already exists! "); +565248,1157867776,0,0,PS1,CERRC,CerrcStoreLastCampCellInfo_fail,P_ERROR,swLogPrintf("Fail to store last camp cell info due to CsrState %e , siValidBitmap ( 0x%x ) "); +565248,1157869568,0,0,PS1,CERRC,CerrcEscapeServingCell_entry,P_INFO,swLogPrintf("Escape current serving cell , needReselEval ( %d ) ! "); +565248,1157871616,0,0,PS1,CERRC,CerrcCalcExtendDrxCycle_invalid,P_ERROR,swLogPrintf("Invalid eDrx cycle : %d "); +565248,1157873664,0,0,PS1,CERRC,CerrcCheckIfRepeatedCell_else,P_WARNING,swLogPrintf("Received CephyCellSearchCnf in wrong CsrState %e "); +565248,1157875712,0,0,PS1,CERRC,CerrcCheckIfRepeatedCell_num,P_WARNING,swLogPrintf("Already found more than %d cells ! "); +565248,1157878016,0,0,PS1,CERRC,CerrcCheckIfRepeatedCell_repeated,P_INFO,swLogPrintf("PHY already reported this cell ( %d , %d ) "); +565248,1157879808,0,0,PS1,CERRC,CerrcAddCellToFoundCellList_else,P_INFO,swLogPrintf("No need to record this cell in foundCellList , CsrState %e "); +565248,1157881856,0,0,PS1,CERRC,CerrcAddCellToFoundCellList_num,P_WARNING,swLogPrintf("Already found more than %d cells ! "); +565248,1157884160,0,0,PS1,CERRC,CerrcAddCellToFoundCellList_repeated,P_WARNING,swLogPrintf("Already record this cell ( %d , %d ) "); +565248,1157885952,0,0,PS1,CERRC,CerrcUpdateTSearchDaltaP_default2,P_WARNING,swLogPrintf("Wrong DRX cycle length %d is configured. "); +565248,1157888512,0,0,PS1,CERRC,CerrcUpdateTSearchDaltaP_value,P_INFO,swLogPrintf("eDrxPresent ( %d ) , eDRXAllowed ( %d ) , tSearchDeltaP %d seconds. "); +565248,1157890560,0,0,PS1,CERRC,CerrcUpdateHibMeasRsrpThreshold_end,P_WARNING,swLogPrintf("Update hibernate wake up rmRsrpThreshold ( %d ) to ( %d ) , nRsrpThreshold ( %d ) . "); +565248,1157892864,0,0,PS1,CERRC,CerrcCheckIfRMCriterionFulfilled_false,P_VALUE,swLogPrintf("s-SearchDeltaP ( %d ) , bRMCriterionFulfilled ( %d ) , bIntraMeasRmEnable ( %d ) , bInterMeasRmEnable ( %d ) "); +565248,1157894656,0,0,PS1,CERRC,CerrcUpdateSrxlevRef_entry,P_VALUE,swLogPrintf("Current Srxlev ( %d ) , previous SrxlevRef ( %d ) , bRMCriterionFulfilled ( %d ) "); +565248,1157896192,0,0,PS1,CERRC,CerrcUpdateSrxlevRef_update,P_VALUE,swLogPrintf("Update SrxlevRef to current Srxlev ( %d ) "); +565248,1157899008,0,0,PS1,CERRC,CerrcUpdateCriterionRMTime_succ,P_VALUE,swLogPrintf("Update relaxed monitoring SUCCESS time : s-SearchDeltaP ( %d ) , Srxlev ( %d ) , SrxlevRef ( %d ) , rMCriterionSuccTime ( %d ) "); +565248,1157901056,0,0,PS1,CERRC,CerrcUpdateCriterionRMTime_fail,P_VALUE,swLogPrintf("Update relaxed monitoring FAIL time : s-SearchDeltaP ( %d ) , Srxlev ( %d ) , SrxlevRef ( %d ) , rMCriterionFailTime ( %d ) "); +565248,1157902848,0,0,PS1,CERRC,CerrcCalcSCriterion_end,P_INFO,swLogPrintf("Pcompensation ( %d ) , Qoffsetauthorization ( %d ) , Qoffsettemp ( %d ) "); +565248,1157906431,0,0,PS1,CERRC,CerrcUpdateIntraInterMeasThreshold_sDeltaP,P_INFO,swLogPrintf("sSearchDeltaP is 0 due to no SIB3! "); +565248,1157906688,0,0,PS1,CERRC,CerrcUpdateIntraInterMeasThreshold_disNcell,P_WARNING,swLogPrintf("bCellLocked ( %d ) or bDisableNCellMeas ( %d ) , only care about CriterionS "); +565248,1157909504,0,0,PS1,CERRC,CerrcUpdateIntraInterMeasThreshold_rsrp,P_WARNING,swLogPrintf("IDLE Meas Threshold : Intra-Threshold ( %d ) , Inter-Threshold ( %d ) , sIntraSearchP ( %d ) , sNonIntraSearchP ( %d ) , nRsrpThreshold ( %d ) "); +565248,1157911552,0,0,PS1,CERRC,CerrcUpdateIntraInterMeasThreshold_rsrq,P_WARNING,swLogPrintf("IDLE Meas RSRQ Threshold : Intra-Threshold ( %d ) , Inter-Threshold ( %d ) , sIntraSearchQ ( %d ) , sNonIntraSearchQ ( %d ) , nRsrqThreshold ( %d ) "); +565248,1157914623,0,0,PS1,CERRC,CerrcUpdateIntraInterMeasThreshold_qQualMin,P_WARNING,swLogPrintf("qQualMin is absent in SIB1 ! Hence , RSRQ is NOT taken into account for any threshold ! "); +565248,1157916671,0,0,PS1,CERRC,CerrcSendCephyCellMeasReq_inter,P_ERROR,swLogPrintf("interFreqMeasBitmap is not set correctly! "); +565248,1157918719,0,0,PS1,CERRC,CerrcSendCephyCellMeasStopReq_inter,P_ERROR,swLogPrintf("interFreqMeasBitmap is not set correctly! "); +565248,1157919232,0,0,PS1,CERRC,CerrcCheckCellReserved4OperatorUse_rsvdAc11_15,P_INFO,swLogPrintf("PLMN ( %X-%X ) is ' reserved ' for operator use , and UE ' s accessClass ( 0x%x ) , which is assigned to 11 or 15 but NOT in their HPLMN / EHPLMN "); +565248,1157921280,0,0,PS1,CERRC,CerrcCheckCellReserved4OperatorUse_rsvd,P_INFO,swLogPrintf("PLMN ( %X-%X ) is ' reserved ' for operator use , and UE ' s accessClass ( 0x%x ) , which is NOT assigned to Access Class 11 or 15 "); +565248,1157923584,0,0,PS1,CERRC,CerrcGetPlmnIndex_plmn,P_INFO,swLogPrintf("PLMN ( %X-%X ) is not EPLMN or HPLMN of the Requested PLMN ( %X-%X ) . "); +565248,1157926911,0,0,PS1,CERRC,CerrcGetPlmnIndex_noPlmn,P_WARNING,swLogPrintf("No valid requestedPLMN "); +565248,1157927424,0,0,PS1,CERRC,CerrcGetTaStatus_forbidden,P_INFO,swLogPrintf("CerrcGetTaStatus : FORBIDDEN_TA_FOR_ROAMING , PLMN ( %X-%X ) , TAC ( %X ) "); +565248,1157929472,0,0,PS1,CERRC,CerrcGetTaStatus_block,P_INFO,swLogPrintf("CerrcGetTaStatus : BLOCKED_TA , PLMN ( %X-%X ) , TAC ( %X ) "); +565248,1157931776,0,0,PS1,CERRC,CerrcGetTaStatus_not,P_INFO,swLogPrintf("CerrcGetTaStatus : NOT_FORBIDDEN_TA! PLMN ( %X-%X ) , TAC ( %X ) , TA type %e "); +565248,1157933056,0,0,PS1,CERRC,CerrcGetCellAccessInfoFromSib1_index,P_INFO,swLogPrintf("Get accessInfo from cellAccessRelatedInfoList-r14 [ %d ] "); +565248,1157935104,0,0,PS1,CERRC,CerrcGetCellAccessInfoFromStoredSib1_index,P_INFO,swLogPrintf("Get accessInfo from cellAccessRelatedInfoList-r14 [ %d ] "); +565248,1157937152,0,0,PS1,CERRC,CerrcGetCellBarStatusFromSib1_fbi,P_INFO,swLogPrintf("Cell is barred due to freqBandIndicator ( %d ) not supported ! "); +565248,1157941247,0,0,PS1,CERRC,CerrcGetCellBarStatusFromSib1_reserved,P_INFO,swLogPrintf("Cell is barred due to all PLMN in SIB1 is ' resverd ' for operator and no valid AC11 / AC15! "); +565248,1157943295,0,0,PS1,CERRC,CerrcGetCellBarStatusFromSib1_bar,P_INFO,swLogPrintf("Cell is barred due to SIB1->cellBarred is TRUE! "); +565248,1157944320,0,0,PS1,CERRC,CerrcGetCellStatusFromSib1_status,P_SIG,swLogPrintf("CELL ( %d , %d ) , cellStatus %e , selectedPlmnIdx ( %d ) , band ( %d ) "); +565248,1157945600,0,0,PS1,CERRC,CerrcCheckCampAvailable_s,P_INFO,swLogPrintf("Cell is not suitable due to criterionS fail : Srxlev ( %d ) , Squal ( %d ) : "); +565248,1157947392,0,0,PS1,CERRC,CerrcCheckIfDetectedCellSatisfiedCriterionS_weakCell,P_INFO,swLogPrintf("AT+ECCFG = ' QRxLevMin ' ( %d ) "); +565248,1157949696,0,0,PS1,CERRC,CerrcWeakCellCampOpt_delta,P_INFO,swLogPrintf("deltaRsrp ( %d ) , deltaRsrq ( %d ) "); +565248,1157951488,0,0,PS1,CERRC,CerrcWeakCellCampOpt_weakCell,P_INFO,swLogPrintf("AT+ECCFG = ' QRxLevMin ' ( %d ) "); +565248,1157954304,0,0,PS1,CERRC,CerrcRemoveTimeoutBarredCell_rmv,P_INFO,swLogPrintf("Unbarred Cell ( %d , %d ) due to timeout , barCause ( %d ) , barTimeLength ( %d ) in seconds "); +565248,1157956352,0,0,PS1,CERRC,CerrcAddCellToBarredList_notUpdate,P_INFO,swLogPrintf("Cell ( %d , %d ) has already existed in barredList due to cause %e , barTimeLength ( %d ) , do not update it. "); +565248,1157958400,0,0,PS1,CERRC,CerrcAddCellToBarredList_entry,P_INFO,swLogPrintf("Add new barred cell ( %d , %d ) due to cause %e , barTimeLength ( %d ) in seconds "); +565248,1157961727,0,0,PS1,CERRC,CerrcAddCellToBarredList_full,P_WARNING,swLogPrintf("The barred cell array is full! "); +565248,1157962496,0,0,PS1,CERRC,CerrcAddOverlappedCellToBarredList_entry,P_INFO,swLogPrintf("Barred the overlapped cell ( %d , %d ) due to cause %e , barTimeLength ( %d ) in seconds "); +565248,1157964800,0,0,PS1,CERRC,CerrcCheckIfCellBarred_true,P_INFO,swLogPrintf("Cell ( %d , %d ) is barred due to cause %e , barStartTime ( %d ) , currentTime ( %d ) "); +565248,1157966080,0,0,PS1,CERRC,CerrcRecordAndRmvLocalBarredCells_full,P_INFO,swLogPrintf("freqList [ ] is full , numOfFreq ( %d ) > = maxNumOfFreq ( %d ) "); +565248,1157968384,0,0,PS1,CERRC,CerrcRecordAndRmvLocalBarredCells_rmv,P_INFO,swLogPrintf("Unbarred Cell ( %d , %d ) due to no other cell was found , barCause ( %d ) "); +565248,1157970688,0,0,PS1,CERRC,CerrcUnbarredCellWithCause_rmv,P_INFO,swLogPrintf("Unbarred Cell ( %d , %d ) with barCause ( %d ) before barTimeLength ( %d ) expired "); +565248,1157972736,0,0,PS1,CERRC,CerrcUnbarredCellWithSpecificCell_rmv,P_INFO,swLogPrintf("Unbarred Specific Cell ( %d , %d ) with barCause ( %d ) before barTimeLength ( %d ) expired "); +565248,1157974784,0,0,PS1,CERRC,CerrcActivateCellQoffsetTemp_entry,P_INFO,swLogPrintf("Apply cell ( %d , %d ) QoffsetTemp ( %d ) for %d seconds "); +565248,1157978111,0,0,PS1,CERRC,CerrcActivateCellQoffsetTemp_full,P_WARNING,swLogPrintf("The cell QoffsetTemp array is full! "); +565248,1157978368,0,0,PS1,CERRC,CerrcAddCellToVisitedCellList_exist,P_INFO,swLogPrintf("Cell ( %d , %d ) is already in the visited cell list "); +565248,1157980928,0,0,PS1,CERRC,CerrcAddCellToVisitedCellList_old,P_INFO,swLogPrintf("Remove oldest Cell ( %d , %d ) , PLMN ( %X-%X ) in the visited cell list "); +565248,1157982464,0,0,PS1,CERRC,CerrcAddCellToVisitedCellList_add,P_INFO,swLogPrintf("Add Cell ( %d , %d ) in the visited cell list "); +565248,1157986303,0,0,PS1,CERRC,CerrcAddCellToVisitedCellList_full,P_WARNING,swLogPrintf("The visited cell array is full ! "); +565248,1157986560,0,0,PS1,CERRC,CerrcCheckIfCellInVisitedCellList_true,P_INFO,swLogPrintf("Cell ( %d , %d ) is found in visited cell list "); +565248,1157990399,0,0,PS1,CERRC,CerrcDetectMobilityState_high,P_INFO,swLogPrintf("Enter High-mobility state! "); +565248,1157992447,0,0,PS1,CERRC,CerrcDetectMobilityState_medium,P_INFO,swLogPrintf("Enter Medium-mobility state! "); +565248,1157994495,0,0,PS1,CERRC,CerrcDetectMobilityState_normal,P_INFO,swLogPrintf("Enter Normal-mobility state! "); +565248,1157994496,0,0,PS1,CERRC,CerrcInMobilityState_conn,P_INFO,swLogPrintf("UE is in mobility state %e in RRC_CONNECTED state. "); +565248,1157996544,0,0,PS1,CERRC,CerrcInMobilityState_idle,P_INFO,swLogPrintf("UE is in mobility state %e in RRC_IDLE state. "); +565248,1158000639,0,0,PS1,CERRC,CerrcAddFreqToDeprioritisationList_full,P_WARNING,swLogPrintf("Already received 8 deprioritisationReq for different frequency! "); +565248,1158000896,0,0,PS1,CERRC,CerrcClearEscapeCellFromList_info,P_INFO,swLogPrintf("Delete carrierFreq ( %d ) , phyCellId ( %d ) from escapeCellList. "); +565248,1158002944,0,0,PS1,CERRC,CerrcRemoveTimeoutEscapeCell_info,P_INFO,swLogPrintf("Remove carrierFreq ( %d ) , phyCellId ( %d ) from escapeCellList for over time. "); +565248,1158004992,0,0,PS1,CERRC,CerrcAddCelIntoEscapeCellList_info1,P_INFO,swLogPrintf("Move the escape cell ( %d , %d ) into BarredCellList. "); +565248,1158007296,0,0,PS1,CERRC,CerrcAddCelIntoEscapeCellList_info2,P_INFO,swLogPrintf("Update the escape cell ( %d , %d ) startTime and pos ( %d ) . "); +565248,1158009344,0,0,PS1,CERRC,CerrcAddCelIntoEscapeCellList_info3,P_INFO,swLogPrintf("Replace escapeCellList oldest one with the escape cell ( %d , %d ) , pos ( %d ) . "); +565248,1158011392,0,0,PS1,CERRC,CerrcAddCelIntoEscapeCellList_info4,P_INFO,swLogPrintf("Add the escape cell ( %d , %d ) into EscapeCellList , pos ( %d ) . "); +565248,1158013184,0,0,PS1,CERRC,CerrcHandlePhyEscapeCell_entry,P_INFO,swLogPrintf("Handle new escape cell ( %d , %d ) "); +565248,1158015232,0,0,PS1,CERRC,CerrcHandlePhyEscapeCell_info1,P_INFO,swLogPrintf("Add new escape cell ( %d , %d ) into EscapeCellList. "); +565248,1158017280,0,0,PS1,CERRC,CerrcHandlePhyEscapeCell_info2,P_INFO,swLogPrintf("The escape cell ( %d , %d ) just inserted into EscapeCellList , ingore it. "); +565248,1158021119,0,0,PS1,CERRC,CerrcCreateDeactProcContext_exist,P_WARNING,swLogPrintf("CerrcDeactProcContext already exists! "); +565248,1158023167,0,0,PS1,CERRC,CerrcHandlePendingDeactReq_1,P_INFO,swLogPrintf("Handle pending CerrcDeactReq. "); +565248,1158023168,0,0,PS1,CERRC,CerrcResetSleep2ContextToDeact_meas,P_INFO,swLogPrintf("CERRC Intra / Inter meas is ongoing ! measAction ( 0x%X ) "); +565248,1158025472,0,0,PS1,CERRC,CerrcResetSleep2ContextToDeact_MDT,P_INFO,swLogPrintf("VarLogMeasConfig ( %d ) or VarLogMeasReport ( %d ) exists ! "); +565248,1158029311,0,0,PS1,CERRC,CerrcStoreInterFreqInDeactContext_else,P_WARNING,swLogPrintf("CerrcDeactProcContext has not been created !! "); +565248,1158029312,0,0,PS1,CERRC,CerrcDeactiveProcess_cause,P_INFO,swLogPrintf("CerrcDeactiveProcess : cause %e "); +565248,1158031360,0,0,PS1,CERRC,CerrcHandleCerrcDeactReq_cause,P_INFO,swLogPrintf("CerrcDeactReq : cause %e "); +565248,1158035455,0,0,PS1,CERRC,CerrcHandleCerrcDeactReq_idle,P_INFO,swLogPrintf("Received CerrcDeactReq in CERRC_IDLE ! "); +565248,1158035456,0,0,PS1,CERRC,CerrcHandleCerrcDeactReq_rccState,P_WARNING,swLogPrintf("Received CerrcDeactReq while RccState is %e ! "); +565248,1158039551,0,0,PS1,CERRC,CerrcHandleCerrcDeactReq_conn,P_INFO,swLogPrintf("Received CerrcDeactReq in CERRC_CONNECTED ! "); +565248,1158041599,0,0,PS1,CERRC,CerrcHandleCerrcDeactReq_state,P_ERROR,swLogPrintf("Received CerrcDeactReq in CERRC_INVALID_STATE ! "); +565248,1158042368,0,0,PS1,CERRC,CerrcSendCerrcDeactCnf_end,P_INFO,swLogPrintf("CerrcDeactCnf : numOfFreq ( %d ) , freq [ 0 ] = %d , freq [ 1 ] = %d , freq [ 2 ] = %d "); +565248,1158043648,0,0,PS1,CERRC,CerrcSendCephyDeactReq_cause,P_INFO,swLogPrintf("CephyDeactReq : cause %e "); +565248,1158045696,0,0,PS1,CERRC,CerrcHandleCephyDeactCnf_state,P_WARNING,swLogPrintf("Receive CephyDeactCnf in wrong RrcState %e! "); +565248,1158047744,0,0,PS1,CERRC,CerrcHandleCephyResetInd_idle,P_INFO,swLogPrintf("Received CephyResetInd in RRC_IDLE , while RccState is %e ! "); +565248,1158051839,0,0,PS1,CERRC,CerrcHandleCephyResetInd_conn,P_INFO,swLogPrintf("Received CephyResetInd in CERRC_CONNECTED ! "); +565248,1158051840,0,0,PS1,CERRC,CerrcHandleCephyResetInd_macReset,P_WARNING,swLogPrintf("Received CephyResetInd in CERRC_CONNECTED ! RccState %e "); +565248,1158055935,0,0,PS1,CERRC,CerrcHandleCephyResetInd_deact,P_INFO,swLogPrintf("Received CephyResetInd in CERRC_DEACTIVATED ! "); +565248,1158057983,0,0,PS1,CERRC,CerrcHandleCephyResetInd_state,P_ERROR,swLogPrintf("Received CephyResetInd in CERRC_INVALID_STATE ! "); +565248,1158060031,0,0,PS1,CERRC,CerrcCreateAssistedLocateContext_exist,P_WARNING,swLogPrintf("pAssistedLocContext already exists! "); +565248,1158062079,0,0,PS1,CERRC,CerrcCreateAssistedLocateContext_err1,P_ERROR,swLogPrintf("CerrcCcmBasicCellListInfoReq ( BCINFO ) : reqMaxCellNum is 0 ! "); +565248,1158062080,0,0,PS1,CERRC,CerrcCreateAssistedLocateContext_err2,P_ERROR,swLogPrintf("CerrcCcmBasicCellListInfoReq ( BCINFO ) : reqMaxCellNum is %d ! "); +565248,1158066175,0,0,PS1,CERRC,CerrcCreateWifiScanContext_exist,P_WARNING,swLogPrintf("pWifiScanContext already exists! "); +565248,1158068223,0,0,PS1,CERRC,CerrcHandlePendingWifiScanReq_1,P_INFO,swLogPrintf("Handle pending CerrcWiFiScanReq. "); +565248,1158070271,0,0,PS1,CERRC,CerrcFillSCellBasicInfo_sib1,P_ERROR,swLogPrintf("No serving cell ' s SIB1 available !! "); +565248,1158071040,0,0,PS1,CERRC,CerrcStoreNCellInAssistedLocContext_add,P_INFO,swLogPrintf("Add NCELL ( %d , %d ) in context , RSRP ( %d ) , total numOfNcell ( %d ) "); +565248,1158072832,0,0,PS1,CERRC,CerrcStoreNCellInAssistedLocContext_ignore,P_INFO,swLogPrintf("Ingore NCELL ( %d , %d ) due to RSRP ( %d ) is too low and the NCELL list is full! "); +565248,1158074880,0,0,PS1,CERRC,CerrcRefreshNCellInAssistedLocContext_remove,P_INFO,swLogPrintf("Remove inter-freq NCELL ( %d , %d ) in context , new total numOfNcell ( %d ) "); +565248,1158077184,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_lockcell,P_INFO,swLogPrintf("Cell locked but sCellInfo.earfcn ( %d ) , sCellInfo.cellId ( %d ) is different from locked cell earfcn ( %d ) , cellId ( %d ) "); +565248,1158078720,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_lockfreq,P_INFO,swLogPrintf("freq locked but sCellInfo.earfcn ( %d ) is different from locked cell earfcn ( %d ) "); +565248,1158081024,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_ncell,P_INFO,swLogPrintf("CerrcCcmBasicCellListInfoCnf : sCellPresent ( %d ) , pAssistedLocContext->numOfNcell ( %d ) , pBasicCellListInfoCnf->nCellNum ( %d ) "); +565248,1158082816,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_scell1,P_INFO,swLogPrintf("CerrcCcmBasicCellListInfoCnf : only current SCELL ( %d , %d ) "); +565248,1158084864,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_scell2,P_INFO,swLogPrintf("CerrcCcmBasicCellListInfoCnf : only source SCELL ( %d , %d ) "); +565248,1158088703,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_scell3,P_ERROR,swLogPrintf("Serving cell should be exist !! "); +565248,1158090751,0,0,PS1,CERRC,CerrcSendCerrcCcmBasicCellListInfoCnf_null,P_INFO,swLogPrintf("CerrcCcmBasicCellListInfoCnf : Neither SCELL nor NCELL is included !! "); +565248,1158091520,0,0,PS1,CERRC,CerrcHandleCerrcCcmBasicCellListInfoReq_deact,P_WARNING,swLogPrintf("Not under PSM state ( %d ) , or waiting for CephyDeactCnf , or there is no valid freq or band , lastCampCellCarrierFreq = %d , storedBandNum = %d , bSearchBand = %d ! "); +565248,1158093056,0,0,PS1,CERRC,CerrcSendCerrcCcmAbortBasicCellListInfoCnf_ncell,P_INFO,swLogPrintf("CerrcCcmAbortBasicCellListInfoCnf : sCellPresent ( %d ) , nCellNum ( %d ) "); +565248,1158095104,0,0,PS1,CERRC,CerrcSendCerrcCcmAbortBasicCellListInfoCnf_scell1,P_INFO,swLogPrintf("CerrcCcmAbortBasicCellListInfoCnf : only current SCELL ( %d , %d ) "); +565248,1158098943,0,0,PS1,CERRC,CerrcSendCerrcCcmAbortBasicCellListInfoCnf_scell2,P_ERROR,swLogPrintf("Serving cell should be exist !! "); +565248,1158100991,0,0,PS1,CERRC,CerrcSendCerrcCcmAbortBasicCellListInfoCnf_null,P_INFO,swLogPrintf("CerrcCcmAbortBasicCellListInfoCnf : Neither SCELL nor NCELL is included !! "); +565248,1158103039,0,0,PS1,CERRC,CerrcSendCephyBasicCellInfoReq_freq,P_ERROR,swLogPrintf("No last camped cell info when enter PSM ! "); +565248,1158104064,0,0,PS1,CERRC,CerrcSendCephyBasicCellInfoReq_psm,P_INFO,swLogPrintf("CephyBasicCellInfoReq : numOfFreq ( %d ) , freqList [ 0 ] ( %d ) , numOfBand ( %d ) , bandList [ 0 ] ( %d ) , bandList [ 1 ] ( %d ) "); +565248,1158105344,0,0,PS1,CERRC,CerrcSendCephyBasicCellInfoReq_intra,P_INFO,swLogPrintf("CephyBasicCellInfoReq : intra-freq ( %d ) , total numOfFreq ( %d ) "); +565248,1158107392,0,0,PS1,CERRC,CerrcHandleCephyBasicCellInfoCnf_interFreq,P_INFO,swLogPrintf("CephyBasicCellInfoCnf : found interFreq ( %d ) , intraFreq ( %d ) ! "); +565248,1158111231,0,0,PS1,CERRC,CerrcHandleCephyBasicCellInfoCnf_nocell,P_INFO,swLogPrintf("CephyBasicCellInfoCnf : no cell found ! "); +565248,1158111488,0,0,PS1,CERRC,CerrcHandleCephyBasicCellInfoCnf_stop,P_INFO,swLogPrintf("CephyBasicCellInfoCnf : cellDetected ( %d ) or reported inter-freq ( %d ) NCELL ! "); +565248,1158113280,0,0,PS1,CERRC,CerrcHandleCephyBasicCellInfoCnf_act,P_ERROR,swLogPrintf("Received CephyBasicCellInfoCnf in wrong ActStatus ( %d ) ! "); +565248,1158117375,0,0,PS1,CERRC,CerrcHandleCephyBasicCellInfoCnf_else,P_ERROR,swLogPrintf("Received unexpected CephyBasicCellInfoCnf in CONNECTED state ! "); +565248,1158119423,0,0,PS1,CERRC,CerrcHandleCephyWiFiScanCnf_null,P_INFO,swLogPrintf("CerrcWifiScanContext is NULL "); +565248,1158120192,0,0,PS1,CERRC,CerrcHandleCephyWiFiScanCnf_end,P_INFO,swLogPrintf("Finish WiFi scan procedure due to numOfBssid ( %d ) > = reqBssidNum ( %d ) or phyScanRound ( %d ) > = maxRoundNum ( %d ) ! "); +565248,1158121984,0,0,PS1,CERRC,CerrcHandleCerrcWiFiScanReq_check1,P_WARNING,swLogPrintf("Receive CerrcWiFiScanReq in RrcState %e , or RccState %e , or PendingConnReq ( %d ) "); +565248,1158123520,0,0,PS1,CERRC,CerrcHandleCerrcWiFiScanReq_check2,P_WARNING,swLogPrintf("Receive CerrcWiFiScanReq during PLMN search , or PendingPlmnSearchReq ( %d ) "); +565248,1158125824,0,0,PS1,CERRC,CerrcHandleCerrcWiFiScanReq_buff1,P_INFO,swLogPrintf("Receive CerrcWiFiScanReq in CsrState %e or siRcvingBitmap ( 0x%X ) , buffer it "); +565248,1158129663,0,0,PS1,CERRC,CerrcHandleCerrcWiFiScanReq_buff2,P_INFO,swLogPrintf("Receive CerrcWiFiScanReq while waiting for ecphyDeactCnf , buffer it "); +565248,1158131711,0,0,PS1,CERRC,CerrcPmuVote_deactHib,P_INFO,swLogPrintf("CERRC vote to enter HIB state in CERRC_DEACTIVATED ! "); +565248,1158131968,0,0,PS1,CERRC,CerrcPmuVote_deactSlp2,P_INFO,swLogPrintf("CERRC vote to enter SLEEP2 state in CERRC_DEACTIVATED ! bConfigPresent ( %d ) , logMeasInfoListLength ( %d ) "); +565248,1158134272,0,0,PS1,CERRC,CerrcPmuVote_idle,P_VALUE,swLogPrintf("CERRC current measAction ( 0x%x ) , bConfigPresent ( %d ) , logMeasInfoListLength ( %d ) "); +565248,1158137855,0,0,PS1,CERRC,CerrcPmuVote_idleHib,P_INFO,swLogPrintf("CERRC vote to enter HIB state in CERRC_IDLE ! "); +565248,1158139903,0,0,PS1,CERRC,CerrcPmuVote_idleSlp2,P_INFO,swLogPrintf("CERRC vote to enter SLEEP2 state in CERRC_IDLE ! "); +565248,1158139904,0,0,PS1,CERRC,CerrcPmuDeepSlpEnterCallBack_entry,P_VALUE,swLogPrintf("Cerrc Enter Deep Sleep , the lowPowerState is %d "); +565248,1158143999,0,0,PS1,CERRC,CerrcPmuDeepSlpEnterCallBack_deact,P_INFO,swLogPrintf("Do nothing if enter Deep Sleep in CERRC_DEACTIVATED state ! "); +565248,1158144000,0,0,PS1,CERRC,CerrcPmuDeepSlpEnterCallBack_else,P_WARNING,swLogPrintf("CERRC deep sleep call back in wrong APSleepState ( %d ) ! "); +565248,1158148095,0,0,PS1,CERRC,CerrcRestoreWhenWakeUp_hib,P_INFO,swLogPrintf("CERRC wake up from HIBERNATE ! "); +565248,1158150143,0,0,PS1,CERRC,CerrcRestoreWhenWakeUp_sleep2,P_INFO,swLogPrintf("CERRC wake up from SLEEP2 ! "); +565248,1158151168,0,0,PS1,CERRC,CerrcRestoreWhenWakeUp_state,P_INFO,swLogPrintf("CerrcRestoreWhenWakeUp : RrcState %e , CampOnState %e , CsrState %e , ActStatus %e , RccState %e "); +565248,1158154239,0,0,PS1,CERRC,CerrcInit_entry,P_INFO,swLogPrintf("Initialize CERRC task global variables when power on ! "); +565248,1158154240,0,0,PS1,CERRC,CerrcMain_sig,P_WARNING,swLogPrintf("Unknown CERRC SIG : 0x%X "); +565248,1158156800,0,0,PS1,CERRC,CerrcCheckIfRplmnInPlmnList_end,P_INFO,swLogPrintf("RPLMN ( %X-%X ) is not included in the plmnList ( numOfPlmn = %d ) "); +565248,1158159104,0,0,PS1,CERRC,CerrcCheckIfAsn1PlmnInPlmnList_false,P_INFO,swLogPrintf("The Cell ( PLMN ( %X-%X ) ) is NOT part of the AreaConfiguration : PLMN ( %X-%X ) "); +565248,1158160384,0,0,PS1,CERRC,CerrcFillMdtScellRsrpResult_err,P_ERROR,swLogPrintf("Invalid PCell RSRP ( %d ) ! "); +565248,1158162432,0,0,PS1,CERRC,CerrcFillMdtScellRsrqResult_err,P_ERROR,swLogPrintf("Invalid PCell RSRQ ( %d ) ! "); +565248,1158164992,0,0,PS1,CERRC,CerrcStoreRachInfo_entry,P_INFO,swLogPrintf("CemacRAInd : numberOfPreamblesSent ( %d ) , contentionDetected ( %d ) , maxTxPowerReached ( %d ) "); +565248,1158168575,0,0,PS1,CERRC,CerrcStoreRachInfo_rccEst,P_WARNING,swLogPrintf("RachInfo is NOT stored due to incorrect RccState ( CONN_EST ) ! "); +565248,1158168576,0,0,PS1,CERRC,CerrcEncodeRLF_Report_r9_size,P_ERROR,swLogPrintf("Need to extend memory reserved for RLF-Report to ( %d ) ! "); +565248,1158170624,0,0,PS1,CERRC,CerrcDecodeRLF_Report_r9_dec,P_ERROR,swLogPrintf("RLF_Report decode error : %d "); +565248,1158172672,0,0,PS1,CERRC,CerrcEncodeRLF_Report_v9e0_size,P_ERROR,swLogPrintf("Need to extend memory reserved for RLF-Report-v9e0 to ( %d ) ! "); +565248,1158174720,0,0,PS1,CERRC,CerrcDecodeRLF_Report_v9e0_dec,P_ERROR,swLogPrintf("RLF_Report_v9e0 decode error : %d "); +565248,1158178815,0,0,PS1,CERRC,CerrcFillRlfReportT304Expiry_else,P_ERROR,swLogPrintf("T304 expiry but no stored RLF-Report info ! "); +565248,1158178816,0,0,PS1,CERRC,CerrcFillRlfReportRlf_rlfCause,P_ERROR,swLogPrintf("Invalid rlf-Cause %e ! "); +565248,1158182911,0,0,PS1,CERRC,CerrcFillReestCellIdInRlfReport_else,P_INFO,swLogPrintf("Re-establishment was NOT initiated due to radio link failure or handover failure "); +565248,1158184959,0,0,PS1,CERRC,CerrcGetRlfReportAvailable_noRplmn,P_WARNING,swLogPrintf("NO valid RPLMN ! "); +565248,1158185216,0,0,PS1,CERRC,CerrcGetRlfReportAvailable_else,P_INFO,swLogPrintf("the RPLMN ( %X-%X ) is NOT included in plmn-IdentityList stored in VarRLF-Report ! "); +565248,1158189055,0,0,PS1,CERRC,CerrcGetRlfReportAvailable_noPlmn,P_WARNING,swLogPrintf("NOT getting any PLMN from EMM ! "); +565248,1158189056,0,0,PS1,CERRC,CerrcEncodeVarLogMeasConfig_r12_size,P_ERROR,swLogPrintf("Need to extend memory reserved for VarLogMeasConfig to ( %d ) ! "); +565248,1158191104,0,0,PS1,CERRC,CerrcDecodeVarLogMeasConfig_r12_dec,P_ERROR,swLogPrintf("VarLogMeasConfig_r12 decode error : %d "); +565248,1158193152,0,0,PS1,CERRC,CerrcEncodeLogMeasList_r10_size,P_WARNING,swLogPrintf("Memory reserved for LogMeasInfoList is full ( %d ) ! Stop T330 and release VarLogMeasConfig "); +565248,1158195200,0,0,PS1,CERRC,CerrcDecodeLogMeasInfoList_r10_dec,P_ERROR,swLogPrintf("LogMeasInfoList_r10 decode error : %d "); +565248,1158197504,0,0,PS1,CERRC,CerrcCellIsPartOfAreaConfig_CGI,P_INFO,swLogPrintf("The Cell ( cellIdentity = %d ) is NOT part of the AreaConfiguration : cellIdentity ( %d ) "); +565248,1158199552,0,0,PS1,CERRC,CerrcCellIsPartOfAreaConfig_TAC,P_INFO,swLogPrintf("The Cell ( TAC = %d ) is NOT part of the AreaConfiguration : TAC ( %d ) "); +565248,1158203391,0,0,PS1,CERRC,CerrcPerformMeasurementsLogging_config,P_WARNING,swLogPrintf("VarLogMeasConfig has been released ! "); +565248,1158205439,0,0,PS1,CERRC,CerrcPerformMeasurementsLogging_T330,P_WARNING,swLogPrintf("T330 is NOT running ! "); +565248,1158207487,0,0,PS1,CERRC,CerrcPerformMeasurementsLogging_add,P_SIG,swLogPrintf("Adding a logged measurement entry in VarLogMeasReport ! "); +565248,1158209535,0,0,PS1,CERRC,CerrcGetLogMeasAvailable_unSupport,P_INFO,swLogPrintf("Not support LoggedMeasurementsIdle ! "); +565248,1158211583,0,0,PS1,CERRC,CerrcGetLogMeasAvailable_noRplmn,P_WARNING,swLogPrintf("NO valid RPLMN ! "); +565248,1158211840,0,0,PS1,CERRC,CerrcGetLogMeasAvailable_else,P_INFO,swLogPrintf("the RPLMN ( %X-%X ) is NOT included in plmn-IdentityList stored in VarLogMeasReport ! "); +565248,1158213632,0,0,PS1,CERRC,CerrcEncodeConnEstFailReport_r11_size,P_ERROR,swLogPrintf("Need to extend memory reserved for ConnEstFailReport-r11 to ( %d ) ! "); +565248,1158215680,0,0,PS1,CERRC,CerrcDecodeConnEstFailReport_r11_dec,P_ERROR,swLogPrintf("ConnEstFailReport_r11 decode error : %d "); +565248,1158219775,0,0,PS1,CERRC,CerrcGetConnEstFailInfoAvailable_noRplmn,P_WARNING,swLogPrintf("NO valid RPLMN ! "); +565248,1158220544,0,0,PS1,CERRC,CerrcGetConnEstFailInfoAvailable_else,P_INFO,swLogPrintf("the RPLMN ( %X-%X ) is NOT equal to plmn-Identity ( %X-%X ) stored in VarConnEstFailReport ! "); +565248,1158223871,0,0,PS1,CERRC,CerrcHandleLoggedMeasurementConfiguration_unSupport,P_WARNING,swLogPrintf("Ignore this LoggedMeasurementConfiguration due to not support LoggedMeasurementsIdle ! "); +565248,1158225919,0,0,PS1,CERRC,CerrcHandleLoggedMeasurementConfiguration_noRplmn,P_WARNING,swLogPrintf("NO valid RPLMN ! Ignore this LoggedMeasurementConfiguration ! "); +565248,1158226176,0,0,PS1,CERRC,CerrcHandleLoggedMeasurementConfiguration_plmnList,P_INFO,swLogPrintf("Set plmn-IdentityList in VarLogMeasReport to include the RPLMN ( %X-%X ) ! "); +565248,1158230015,0,0,PS1,CERRC,CerrcCreateConnMeasContext_exist,P_INFO,swLogPrintf("CerrcConnMeasContext already exists! \n "); +565248,1158230272,0,0,PS1,CERRC,CerrcAddCellToMeasReportingEntryInVarMeasReportList_info,P_INFO,swLogPrintf("Add measId ( %d ) phyCellId ( %d ) into varMeasReportList "); +565248,1158232064,0,0,PS1,CERRC,CerrcAddCellToMeasReportingEntryInVarMeasReportList_error,P_ERROR,swLogPrintf("Cell Num of cellsTriggered exceed MAX , Ingore phyCellId ( %d ) "); +565248,1158234112,0,0,PS1,CERRC,CerrcRmvMeasReportingEntryInVarMeasReportList_info1,P_INFO,swLogPrintf("rmv measReportingEntry measId ( %d ) from VarMeasReport "); +565248,1158236160,0,0,PS1,CERRC,CerrcRmvMeasReportingEntryInVarMeasReportList_info2,P_INFO,swLogPrintf("rmv measReportingEntry measId ( %d ) from VarMeasReport "); +565248,1158238464,0,0,PS1,CERRC,CerrcRmvCellFromMeasReportingEntryInVarMeasReportList_reportLeave,P_INFO,swLogPrintf("measId ( %d ) , phyCellId ( %d ) statify A3-reportLeave "); +565248,1158240512,0,0,PS1,CERRC,CerrcJudgeCellExistInVarMeasReportList_info,P_INFO,swLogPrintf("measId ( %d ) phyCellId ( %d ) already exist in VarMeasReport "); +565248,1158244351,0,0,PS1,CERRC,CerrcReconfigMeasObjectInVarMeasConfig_not_support_measCycleSCell,P_WARNING,swLogPrintf("NW config measCycleSCell! "); +565248,1158246399,0,0,PS1,CERRC,CerrcReconfigMeasObjectInVarMeasConfig_not_support_measDS,P_WARNING,swLogPrintf("NW config measDS! "); +565248,1158248447,0,0,PS1,CERRC,CerrcReconfigMeasObjectInVarMeasConfig_not_support_rmtc,P_WARNING,swLogPrintf("NW config rmtc! "); +565248,1158250495,0,0,PS1,CERRC,CerrcReconfigMeasObjectInVarMeasConfig_not_support_tx_ResourcePool,P_WARNING,swLogPrintf("NW config tx_ResourcePool! "); +565248,1158252543,0,0,PS1,CERRC,CerrcReconfigMeasObjectInVarMeasConfig_not_support_fembms_MixedCarrier,P_WARNING,swLogPrintf("NW config fembms_MixedCarrier! "); +565248,1158254591,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_reportStrongestCSI_RS,P_WARNING,swLogPrintf("NW config reportStrongestCSI_RSs! "); +565248,1158256639,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_reportCRS_Meas,P_WARNING,swLogPrintf("NW config reportCRS_Meas! "); +565248,1158258687,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_triggerQuantityCSI_RS,P_WARNING,swLogPrintf("NW config triggerQuantityCSI_RS! "); +565248,1158260735,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_reportSSTD_Meas,P_WARNING,swLogPrintf("NW config reportSSTD_Meas! "); +565248,1158262783,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_rs_sinr_Config,P_WARNING,swLogPrintf("NW config rs_sinr_Config! "); +565248,1158264831,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_measRSSI_ReportConfig,P_WARNING,swLogPrintf("NW config measRSSI_ReportConfig! "); +565248,1158266879,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_ul_DelayConfig,P_WARNING,swLogPrintf("NW config ul_DelayConfig! "); +565248,1158268927,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_ue_RxTxTimeDiffPeriodicalTDD,P_WARNING,swLogPrintf("NW config ue_RxTxTimeDiffPeriodicalTDD! "); +565248,1158270975,0,0,PS1,CERRC,CerrcPrintNotSupportReportConfig_not_support_purpose_v1430,P_WARNING,swLogPrintf("NW config purpose_v1430! "); +565248,1158273023,0,0,PS1,CERRC,CerrcAddModMeasObjectInVarMeasConfig_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158275071,0,0,PS1,CERRC,CerrcAddModMeasObjectExtR13InVarMeasConfig_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158277119,0,0,PS1,CERRC,CerrcGetMeasObjectIdByCarrierFreq_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158279167,0,0,PS1,CERRC,CerrcGetMeasObjectIdAndMeasIdInfoByCarrierFreq_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158281215,0,0,PS1,CERRC,CerrcGetMeasObjectIdR13ByCarrierFreq_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158283263,0,0,PS1,CERRC,CerrcGetMeasObjectIdAndMeasIdInfoR13ByCarrierFreq_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158285311,0,0,PS1,CERRC,CerrcGetCarrierFreqByMeasObjectId_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158287359,0,0,PS1,CERRC,CerrcGetCarrierFreqAndMeasObjectInfoByMeasObjectId_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158289407,0,0,PS1,CERRC,CerrcGetCarrierFreqByMeasObjectIdR13_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158291455,0,0,PS1,CERRC,CerrcGetCarrierFreqAndMeasObjectInfoR13ByMeasObjectId_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158293503,0,0,PS1,CERRC,CerrcGetReportConfigInfoByReportConfigId_error_type,P_ERROR,swLogPrintf("only support EUTRAN! "); +565248,1158294272,0,0,PS1,CERRC,CerrcUpdateQuantityConfigInVarMeasConfig_not_change,P_VALUE,swLogPrintf("NW configured quantityConfig is the same with quantityConfig saved in varMeasConfig , filterCoefficientRSRPPresent = %d , filterCoefficientRSRP = %d , filterCoefficientRSRQPresent = %d , filterCoefficientRSRQ = %d "); +565248,1158297599,0,0,PS1,CERRC,CerrcProcessQuantityConfig_not_support,P_ERROR,swLogPrintf("NW config non EUTRAN quantityConfig "); +565248,1158297600,0,0,PS1,CERRC,CerrcUpdateMeasIdWithSelfCheck_rmv1,P_WARNING,swLogPrintf("Remove MeasId ( %d ) due to its associated measObject or reportConfig NOT configured. "); +565248,1158299648,0,0,PS1,CERRC,CerrcUpdateMeasIdWithSelfCheck_rmv2,P_WARNING,swLogPrintf("Remove MeasId ( %d ) due to its associated measObject or reportConfig NOT configured. "); +565248,1158301952,0,0,PS1,CERRC,CerrcHandlePeriodMeasReportTimerExpiry_not_support,P_ERROR,swLogPrintf("preRegistrationInfoHRPDPresent = %d , measScaleFactor_r12Present = %d "); +565248,1158305791,0,0,PS1,CERRC,CerrcHandleMeasConfig_info,P_INFO,swLogPrintf("Start scell s-Measure procedure. "); +565248,1158306048,0,0,PS1,CERRC,CerrcGetCellTimeToTrigger_info,P_INFO,swLogPrintf("phyCellId ( %d ) , timeToTrigger ( %d ) "); +565248,1158307840,0,0,PS1,CERRC,CerrcFillRsrpInMeasResultPCell_err,P_ERROR,swLogPrintf("Invalid PCell RSRP ( %d ) ! "); +565248,1158309888,0,0,PS1,CERRC,CerrcFillRsrqInMeasResultPCell_err,P_ERROR,swLogPrintf("Invalid PCell RSRQ ( %d ) ! "); +565248,1158311936,0,0,PS1,CERRC,CerrcFillRsrpInMeasResultEutra_err,P_ERROR,swLogPrintf("Invalid neighbor cell RSRP ( %d ) ! "); +565248,1158313984,0,0,PS1,CERRC,CerrcFillRsrqInMeasResultEutra_err,P_ERROR,swLogPrintf("Invalid neighbor cell RSRQ ( %d ) ! "); +565248,1158318079,0,0,PS1,CERRC,CerrcFillLocationInfoInMeasResult_warn,P_INFO,swLogPrintf("No Valid LocationInfo could be used , not fill locationInfo in MeasResult IE. "); +565248,1158318080,0,0,PS1,CERRC,CerrcFillLocationInfoInMeasResult_info,P_INFO,swLogPrintf("Current LocationInfo Type is %e "); +565248,1158322175,0,0,PS1,CERRC,CerrcFillLocationInfoInMeasResult_fill1,P_INFO,swLogPrintf("Fill LocationInfo into MeasResult IE. "); +565248,1158324223,0,0,PS1,CERRC,CerrcFillLocationInfoInMeasResult_fill2,P_INFO,swLogPrintf("Fill horizontalVelocity_r10 into MeasResult IE. "); +565248,1158326271,0,0,PS1,CERRC,CerrcFillLocationInfoInMeasResult_fill3,P_INFO,swLogPrintf("Fill gnss_TOD_msec_r10 into MeasResult IE. "); +565248,1158328319,0,0,PS1,CERRC,CerrcFillMeasResults_warn,P_WARNING,swLogPrintf("NW expect LocationInfo Report , but UE not support it. "); +565248,1158329088,0,0,PS1,CERRC,CerrcPrintMeasResult_info,P_INFO,swLogPrintf("MeasResult measId = %d , PCellRsrp = %d , PCellRsrq = %d , NCellPresent = %d "); +565248,1158330880,0,0,PS1,CERRC,CerrcPrintMeasResult_ncell_info,P_INFO,swLogPrintf("NCellId = %d , NCellRsrp = %d , NCellRsrq = %d "); +565248,1158332672,0,0,PS1,CERRC,CerrcPostProcOfSendingPeriodMeasReport_rmv,P_INFO,swLogPrintf("Periodical MeasReport numberOfReportsSent ( %d ) , reportAmount ( %d ) , rmv reportEntry and measId. "); +565248,1158334976,0,0,PS1,CERRC,CerrcIsNeedProcessEventForThisCell_reportNum,P_INFO,swLogPrintf("MeasId ( %d ) Event A%d MR sent times equal to ReportAmount ( %d ) "); +565248,1158337024,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA1_rsrp,P_INFO,swLogPrintf("Ms ( %d ) , Hys ( %d ) , ThreshP ( %d ) "); +565248,1158339072,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA1_rsrq,P_INFO,swLogPrintf("Ms ( %d ) , Hys ( %d ) , ThreshQ ( %d ) "); +565248,1158340864,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA1_wrong,P_ERROR,swLogPrintf("TriggerQuantity ( %d ) , A1_Threshold_Tag ( %d ) "); +565248,1158343168,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA2_rsrp,P_INFO,swLogPrintf("Ms ( %d ) , Hys ( %d ) , ThreshP ( %d ) "); +565248,1158345216,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA2_rsrq,P_INFO,swLogPrintf("Ms ( %d ) , Hys ( %d ) , ThreshQ ( %d ) "); +565248,1158347008,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA2_wrong,P_ERROR,swLogPrintf("TriggerQuantity ( %d ) , A2_Threshold_Tag ( %d ) "); +565248,1158349312,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA3_cell,P_INFO,swLogPrintf("Evaluate phyCellId ( %d ) , rsrp ( %d ) , rsrq ( %d ) "); +565248,1158352640,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA3_rsrp,P_INFO,swLogPrintf("Mn ( %d ) , Ofn ( %d ) , Ocn ( %d ) , Hys ( %d ) , Mp ( %d ) , Ofp ( %d ) , Ocp ( %d ) , Off ( %d ) "); +565248,1158354688,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA3_rsrq,P_INFO,swLogPrintf("Mn ( %d ) , Ofn ( %d ) , Ocn ( %d ) , Hys ( %d ) , Mp ( %d ) , Ofp ( %d ) , Ocp ( %d ) , Off ( %d ) "); +565248,1158355456,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA4_cell,P_INFO,swLogPrintf("Evaluate phyCellId ( %d ) , rsrp ( %d ) , rsrq ( %d ) "); +565248,1158358016,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA4_rsrp,P_INFO,swLogPrintf("Mn ( %d ) , Ofn ( %d ) , Ocn ( %d ) , Hys ( %d ) , ThreshP ( %d ) "); +565248,1158360064,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA4_rsrq,P_INFO,swLogPrintf("Mn ( %d ) , Ofn ( %d ) , Ocn ( %d ) , Hys ( %d ) , ThreshQ ( %d ) "); +565248,1158361344,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA4_wrong,P_ERROR,swLogPrintf("TriggerQuantity ( %d ) , A4_Threshold_Tag ( %d ) "); +565248,1158363648,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA5_cell,P_INFO,swLogPrintf("Evaluate phyCellId ( %d ) , rsrp ( %d ) , rsrq ( %d ) "); +565248,1158366720,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA5_rsrp,P_INFO,swLogPrintf("Mp ( %d ) , Hys ( %d ) , Thresh1 ( %d ) , Mn ( %d ) , Ofn ( %d ) , Ocn ( %d ) , Thresh2 ( %d ) "); +565248,1158368768,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA5_rsrq,P_INFO,swLogPrintf("Mp ( %d ) , Hys ( %d ) , Thresh1 ( %d ) , Mn ( %d ) , Ofn ( %d ) , Ocn ( %d ) , Thresh2 ( %d ) "); +565248,1158369792,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventA5_wrong,P_ERROR,swLogPrintf("TriggerQuantity ( %d ) , A5_Threshold1_Tag ( %d ) , A5_Threshold2_Tag ( %d ) "); +565248,1158371840,0,0,PS1,CERRC,CerrcJudgeIfStatisfyEventTriggerCond_info,P_INFO,swLogPrintf("Event ( A%d ) , Entering ( %d ) , Leaving ( %d ) "); +565248,1158373888,0,0,PS1,CERRC,CerrcAddCellMeasReportLeavingEntry_info2,P_INFO,swLogPrintf("Add measId ( %d ) phyCellId ( %d ) into MeasReportLeavingEntry , cellTimeToTrigger = %d "); +565248,1158375936,0,0,PS1,CERRC,CerrcProcessCellReportInfoLeavingEntry_rmv,P_INFO,swLogPrintf("measId = %d , phyCellId = %d has statisfied leavingConditon ( %d ms ) , remove it from varMeasReport. "); +565248,1158377984,0,0,PS1,CERRC,CerrcProcessEventMeasReport_info,P_INFO,swLogPrintf("measId ( %d ) , reportOnLeaveCellBitmap ( %d ) , measReportFlag ( %d ) "); +565248,1158380032,0,0,PS1,CERRC,CerrcProcessPeriodMeasReport_inter,P_INFO,swLogPrintf("PeriodMeasReport phyCellId ( %d ) , rsrp ( %d ) , rsrq ( %d ) "); +565248,1158382080,0,0,PS1,CERRC,CerrcProcessPeriodMeasReport_inra,P_INFO,swLogPrintf("PeriodMeasReport phyCellId ( %d ) , rsrp ( %d ) , rsrq ( %d ) "); +565248,1158384640,0,0,PS1,CERRC,CerrcProcessMeasResultForEachMeasId_info,P_INFO,swLogPrintf("CarrierFreq ( %ld ) , measId ( %d ) , measObjId ( %d ) , reportConfigId ( %d ) , triggerType ( %d ) ( 0 -Event , 1 -Periodical ) "); +565248,1158385664,0,0,PS1,CERRC,CerrcProcessMeasResultForEachMeasId_periodOngoing,P_INFO,swLogPrintf("Periodical Timer ( measId = %d ) is running , delay the process until timer expired. "); +565248,1158387968,0,0,PS1,CERRC,CerrcProcessMeasResultForEachMeasId_wrong_event,P_ERROR,swLogPrintf("NOT Supported TriggerType ( %d ) , EventType ( %d ) "); +565248,1158391807,0,0,PS1,CERRC,CerrcProcessConnectedMeasResult_empty_config,P_WARNING,swLogPrintf("No available VarMeasConfig , ingore this MeasResult. "); +565248,1158392064,0,0,PS1,CERRC,CerrcStartT321Timer_info,P_INFO,swLogPrintf("T321 timer length = %d , measId = %d. "); +565248,1158395903,0,0,PS1,CERRC,CerrcStartReportCGI_T321_running,P_ERROR,swLogPrintf("T321 is running! "); +565248,1158397184,0,0,PS1,CERRC,CerrcRecodeSib1CellInfo_update,P_INFO,swLogPrintf("Update existed SIB1 info : CELL ( %d , %d ) , PLMN ( %x-%x ) , TAC ( 0x%X ) , total numOfCell ( %d ) "); +565248,1158399232,0,0,PS1,CERRC,CerrcRecodeSib1CellInfo_new,P_INFO,swLogPrintf("Add SIB1 info : CELL ( %d , %d ) , PLMN ( %x-%x ) , TAC ( 0x%X ) , total numOfCell ( %d ) "); +565248,1158401280,0,0,PS1,CERRC,CerrcRecodeSib1CellInfo_rmv,P_INFO,swLogPrintf("Remove the oldest cell : CELL ( %d , %d ) , PLMN ( %x-%x ) , TAC ( 0x%X ) , total numOfCell ( %d ) "); +565248,1158403328,0,0,PS1,CERRC,CerrcRecodeSib1CellInfo_replace,P_INFO,swLogPrintf("Remove the oldest cell and Add SIB1 info : CELL ( %d , %d ) , PLMN ( %x-%x ) , TAC ( 0x%X ) , total numOfCell ( %d ) "); +565248,1158404864,0,0,PS1,CERRC,CerrcProcessReportCGI_NcellSysInfoInd_info,P_INFO,swLogPrintf("measId = %d , measObjectId = %d , ReportCGIPresent = %d , phyCellId = %d "); +565248,1158406656,0,0,PS1,CERRC,CerrcProcessReportCGI_NcellSysInfoInd_crc,P_WARNING,swLogPrintf("Ncell ( %d , %d ) SIB1 decode or CRC ( %d ) fail in RRC_CONNECTED state "); +565248,1158408192,0,0,PS1,CERRC,CerrcHandleT321Expiry_wrong_state,P_ERROR,swLogPrintf("rrcState %e "); +565248,1158411008,0,0,PS1,CERRC,CerrcAddServingCellToIntraFreqDB_addScell,P_INFO,swLogPrintf("INTRA FREQ SCELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1158414335,0,0,PS1,CERRC,CerrcDeleteCellsInVarMeasReportList_wrong_num,P_ERROR,swLogPrintf("VarMeasReport exceed the max num "); +565248,1158414336,0,0,PS1,CERRC,CerrcDeleteCellsInVarMeasReportList_info,P_INFO,swLogPrintf("rmv measId ( %d ) from VarMeasReport "); +565248,1158416384,0,0,PS1,CERRC,CerrcUpdateInterFreqCarrierFreqList_wrong_num,P_ERROR,swLogPrintf("no spare place to add carrierFreq ( %d ) to database "); +565248,1158418432,0,0,PS1,CERRC,CerrcHandleMeasReportTimerExpiry_wrong_measId,P_WARNING,swLogPrintf("MeasTimer ( %d ) not exists , ingore this time expriy. "); +565248,1158420992,0,0,PS1,CERRC,CerrcHandleMeasReportTimerExpiry_unMatched_freqIndex,P_WARNING,swLogPrintf("UnMatched carrierFreq ( %d ) measId ( %d ) measObjectId ( %d ) , UE will send MR only with scell. "); +565248,1158423296,0,0,PS1,CERRC,CerrcHandleMeasReportTimerExpiry_info,P_INFO,swLogPrintf("MeasId ( %d ) Timer expiry , measObjectId = %d , TriggerType = %d , carrierFreq = %d "); +565248,1158424576,0,0,PS1,CERRC,CerrcHandleMeasReportTimerExpiry_notTrigger,P_INFO,swLogPrintf("MeasmentReport ( measId = %d ) just sent , ingore this time expiry. "); +565248,1158426880,0,0,PS1,CERRC,CerrcHandleMeasReportTimerExpiry_wrong_event,P_ERROR,swLogPrintf("CerrcHandlePeriodMeasReportTimerExpiry : measId = %d , triggerType = %d "); +565248,1158428928,0,0,PS1,CERRC,CerrcHandlePeriodMeasReportTimerExpiry_wrong_state,P_ERROR,swLogPrintf("rrcState = %d , measId = %d "); +565248,1158430976,0,0,PS1,CERRC,CerrcUpdateIntraInterFreqDataBase_notSupport,P_INFO,swLogPrintf("MeasObjectId ( %d ) DlEarfcn ( %d ) is Not Supported ! "); +565248,1158434815,0,0,PS1,CERRC,CerrcUpdateIntraInterFreqDataBase_info0,P_WARNING,swLogPrintf("Change InterFreqEnableFlag to FALSE for validMeasGapFlag is FALSE. "); +565248,1158435328,0,0,PS1,CERRC,CerrcUpdateIntraInterFreqDataBase_info1,P_VALUE,swLogPrintf("ConnMeas IntraFreqEnableFlag = %d , InterFreqEnableFlag = %d , numOfCurInterFreq = %d "); +565248,1158437120,0,0,PS1,CERRC,CerrcUpdateIntraInterFreqDataBase_info2,P_VALUE,swLogPrintf("ConnMeas curInterFreqCarrier [ %d ] = %d "); +565248,1158439168,0,0,PS1,CERRC,CerrcUpdateIntraInterFreqDataBase_info3,P_VALUE,swLogPrintf("ConnMeas Updated NcellDB interFreq [ %d ] .carrierFreq = %d "); +565248,1158440960,0,0,PS1,CERRC,CerrcFillSubframePatternConfigNeigh_wrong_cell_num,P_ERROR,swLogPrintf("neighbor cell num exceed max num , carrierFreq = %d. "); +565248,1158443008,0,0,PS1,CERRC,CerrcFillCephyMeasConfigReq_wrong_blackcell_num,P_ERROR,swLogPrintf("black cell num exceed max num , carrierFreq = %d. "); +565248,1158445056,0,0,PS1,CERRC,CerrcFillCephyMeasConfigReqByMeasObject_intrafreq,P_ERROR,swLogPrintf("NW not config measObject for LTE serving frequency ( %d ) . "); +565248,1158449151,0,0,PS1,CERRC,CerrcHandleActionUponHandoverOrReest_warn,P_WARNING,swLogPrintf("NW not config measObject ( serving ) , no need swap sourceCell with targetCell measObject. "); +565248,1158449664,0,0,PS1,CERRC,CerrcPrintBcchBchMsg_MIB,P_SIG,swLogPrintf("CELL ( %d , %d ) , MIB , len ( %d ) "); +565248,1158451712,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB2,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB2 , len ( %d ) "); +565248,1158453760,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB3,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB3 , len ( %d ) "); +565248,1158455808,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB4,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB4 , len ( %d ) "); +565248,1158457856,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB5,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB5 , len ( %d ) "); +565248,1158459904,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB14,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB14 , len ( %d ) "); +565248,1158461952,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB16,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB16 , len ( %d ) "); +565248,1158464000,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB10,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB10 , len ( %d ) "); +565248,1158466048,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB11,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB11 , len ( %d ) "); +565248,1158468096,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB12,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB12 , len ( %d ) "); +565248,1158470144,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB6,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB6 , len ( %d ) "); +565248,1158472192,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB7,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB7 , len ( %d ) "); +565248,1158474240,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB8,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB8 , len ( %d ) "); +565248,1158476288,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB9,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB9 , len ( %d ) "); +565248,1158478336,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB13,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB13 , len ( %d ) "); +565248,1158480384,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB15,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB15 , len ( %d ) "); +565248,1158482432,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB17,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB17 , len ( %d ) "); +565248,1158484480,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB18,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB18 , len ( %d ) "); +565248,1158486528,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB19,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB19 , len ( %d ) "); +565248,1158488576,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB20,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB20 , len ( %d ) "); +565248,1158490624,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB21,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB21 , len ( %d ) "); +565248,1158492160,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_errSI,P_ERROR,swLogPrintf("Unsupported BCCH_Message SI type %d! "); +565248,1158494720,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_SIB1,P_SIG,swLogPrintf("CELL ( %ld , %d ) , SIB1 , len ( %d ) "); +565248,1158496256,0,0,PS1,CERRC,CerrcPrintBcchDlSchMsg_tag,P_ERROR,swLogPrintf("Invalid BCCH_Message type %d! "); +565248,1158498304,0,0,PS1,CERRC,CerrcPrintDlCcchMsg_Reest,P_INFO,swLogPrintf("RrcConnectionReestablishment , len ( %d ) "); +565248,1158500352,0,0,PS1,CERRC,CerrcPrintDlCcchMsg_ReestRej,P_INFO,swLogPrintf("RrcConnectionReestablishmentReject , len ( %d ) "); +565248,1158502400,0,0,PS1,CERRC,CerrcPrintDlCcchMsg_ConnRej,P_INFO,swLogPrintf("RrcConnectionReject , len ( %d ) "); +565248,1158504448,0,0,PS1,CERRC,CerrcPrintDlCcchMsg_Setup,P_INFO,swLogPrintf("RrcConnectionSetup , len ( %d ) "); +565248,1158506496,0,0,PS1,CERRC,CerrcPrintDlCcchMsg_tag,P_ERROR,swLogPrintf("Invalid DL_CCCH_Message type %d! "); +565248,1158508544,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_DlTrans,P_SIG,swLogPrintf("DlInformationTransfer , len ( %d ) "); +565248,1158510592,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_Recfg,P_INFO,swLogPrintf("RrcConnectionReconfiguration , len ( %d ) "); +565248,1158512640,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_Rel,P_INFO,swLogPrintf("RrcConnectionRelease , len ( %d ) "); +565248,1158514688,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_SMC,P_INFO,swLogPrintf("SecurityModeCommand , len ( %d ) "); +565248,1158516736,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_Cap,P_INFO,swLogPrintf("UeCapabilityEnquiry , len ( %d ) "); +565248,1158518784,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_Count,P_INFO,swLogPrintf("CounterCheck , len ( %d ) "); +565248,1158520832,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_Rsm,P_INFO,swLogPrintf("RrcConnectionResume , len ( %d ) "); +565248,1158522880,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_UeInfo,P_INFO,swLogPrintf("UeInformationRequest , len ( %d ) "); +565248,1158524928,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_LogMeas,P_INFO,swLogPrintf("LoggedMeasurementConfiguration , len ( %d ) "); +565248,1158526976,0,0,PS1,CERRC,CerrcPrintDlDcchMsg_tag,P_ERROR,swLogPrintf("Unsupported DL_DCCH_Message type %d! "); +565248,1158529024,0,0,PS1,CERRC,CerrcPrintPcchMsg_Paging,P_VALUE,swLogPrintf("Paging , normal paging , len ( %d ) "); +565248,1158531072,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_Reest,P_INFO,swLogPrintf("RrcConnectionReestablishmentRequest , len ( %d ) "); +565248,1158533120,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_ConnReq,P_INFO,swLogPrintf("RrcConnectionRequest , len ( %d ) "); +565248,1158535168,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_tag1,P_ERROR,swLogPrintf("Invalid UL_CCCH_Message type %d! "); +565248,1158537216,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_RsmReq,P_INFO,swLogPrintf("RrcConnectionResumeRequest , len ( %d ) "); +565248,1158539264,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_tag2,P_ERROR,swLogPrintf("Invalid UL_CCCH_Message type %d! "); +565248,1158543359,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_err,P_ERROR,swLogPrintf("Invalid UL_CCCH_Message type! "); +565248,1158543360,0,0,PS1,CERRC,CerrcPrintUlCcchMsg_msg5,P_INFO,swLogPrintf("Msg5 len = %d "); +565248,1158545408,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_Mr,P_INFO,swLogPrintf("MeasurementReport , len ( %d ) "); +565248,1158547456,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_RecfgComp,P_INFO,swLogPrintf("RrcConnectionReconfigurationComplete , len ( %d ) "); +565248,1158549504,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_ReestComp,P_INFO,swLogPrintf("RrcConnectionReestablishmentComplete , len ( %d ) "); +565248,1158551552,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_SetupComp,P_INFO,swLogPrintf("RrcConnectionSetupComplete , len ( %d ) "); +565248,1158554112,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_SetupComp1,P_INFO,swLogPrintf("rrcPduBitLength ( %d ) , nasPduBitLength ( %d ) , nasPduBitPosition ( %d ) "); +565248,1158555648,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_SMC,P_INFO,swLogPrintf("SecurityModeComplete , len ( %d ) "); +565248,1158557696,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_SMF,P_INFO,swLogPrintf("SecurityModeFailure , len ( %d ) "); +565248,1158559744,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_Cap,P_INFO,swLogPrintf("UeCapabilityInformation , len ( %d ) "); +565248,1158561792,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_UlTrans,P_SIG,swLogPrintf("UlInformationTransfer , len ( %d ) "); +565248,1158564352,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_UlTrans1,P_INFO,swLogPrintf("rrcPduBitLength ( %d ) , nasPduBitLength ( %d ) , nasPduBitPosition ( %d ) "); +565248,1158565888,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_CountRsp,P_INFO,swLogPrintf("CounterCheckResponse , len ( %d ) "); +565248,1158567936,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_UeInfoRsp,P_INFO,swLogPrintf("UeInformationResponse , len ( %d ) "); +565248,1158569984,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_ProInd,P_INFO,swLogPrintf("ProximityIndication , len ( %d ) "); +565248,1158572032,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_Rstd,P_INFO,swLogPrintf("InterFreqRSTDMeasurementIndication , len ( %d ) "); +565248,1158574080,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_tag1,P_ERROR,swLogPrintf("Unsupported UL_DCCH_Message type %d! "); +565248,1158576128,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_RsmComp,P_INFO,swLogPrintf("RrcConnectionResumeComplete , len ( %d ) "); +565248,1158578688,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_RsmComp1,P_INFO,swLogPrintf("rrcPduBitLength ( %d ) , nasPduBitLength ( %d ) , nasPduBitPosition ( %d ) "); +565248,1158580224,0,0,PS1,CERRC,CerrcPrintUlDcchMsg_tag2,P_ERROR,swLogPrintf("Unsupported UL_DCCH_Message type %d! "); +565248,1158582272,0,0,PS1,CERRC,CerrcPrintVarMeasConfig,P_SIG,swLogPrintf("VarMeasConfig len ( %d ) "); +565248,1158584320,0,0,PS1,CERRC,CerrcDecodeBcchBchMsg_err,P_ERROR,swLogPrintf("MIB decode error : %d "); +565248,1158586368,0,0,PS1,CERRC,CerrcDecodeBcchDlSchMsg_err,P_ERROR,swLogPrintf("SIB decode error : %d "); +565248,1158588416,0,0,PS1,CERRC,CerrcDecodePCCHMsg_err,P_ERROR,swLogPrintf("PCCH decode error : %d "); +565248,1158590464,0,0,PS1,CERRC,CerrcDecodeDlCcchMsg_err,P_ERROR,swLogPrintf("DL CCCH decode error : %d "); +565248,1158592512,0,0,PS1,CERRC,CerrcDecodeDlDcchMsg_err,P_ERROR,swLogPrintf("DL DCCH decode error : %d "); +565248,1158594560,0,0,PS1,CERRC,CerrcDecodeVarMeasConfig_err,P_ERROR,swLogPrintf("VarMeasConfig decode error : %d \n "); +565248,1158596864,0,0,PS1,CERRC,CerrcSendCerrcPageInfoIndToNAS_end,P_SIG,swLogPrintf("CerrcPageInfoInd : type %e , cnDomain %e "); +565248,1158600703,0,0,PS1,CERRC,CerrcHandlePagingRecordList_cs,P_INFO,swLogPrintf("This is for CS domain , ignore it ! "); +565248,1158600704,0,0,PS1,CERRC,CerrcHandlePagingRecordList_tag,P_WARNING,swLogPrintf("pPaging->ue_Identity.tag is wrong : %d "); +565248,1158604799,0,0,PS1,CERRC,CerrcHandlePagingRecordList_mismatch,P_INFO,swLogPrintf("This Paging is not for this UE! PagingRecordList mismatch! "); +565248,1158606847,0,0,PS1,CERRC,CerrcHandlePagingRecordList_noList,P_INFO,swLogPrintf("There is no PagingRecordList in this Paging message "); +565248,1158608895,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_state,P_WARNING,swLogPrintf("Receive CephyPagingInd in Deactive / HIB / SLEEP2 state! "); +565248,1158610943,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_csrstate,P_WARNING,swLogPrintf("Receive CephyPagingInd in CELL_SELECTION state! "); +565248,1158610944,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_tag,P_WARNING,swLogPrintf("Not supported pPcchMsg->tag ( %d ) in Paging ! "); +565248,1158612992,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_DI,P_ERROR,swLogPrintf("Cat1 does NOT support Direct Indication Information! pagingType ( %d ) "); +565248,1158615808,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_etws_cmas,P_SIG,swLogPrintf("Paging : RrcState ( %e ) , Paging Type ( %d ) , etwsIndication ( %d ) , cmasIndication ( %d ) "); +565248,1158617600,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_eab,P_SIG,swLogPrintf("Paging : RrcState ( %e ) , Paging Type ( %d ) , eabParamModification ( %d ) "); +565248,1158619904,0,0,PS1,CERRC,CerrcHandleCephyPagingInd_SIupdate,P_SIG,swLogPrintf("Paging : RrcState ( %e ) , Paging Type ( %d ) , sysInfoModi ( %d ) , eDrxSysInfoModi ( %d ) "); +565248,1158623231,0,0,PS1,CERRC,CerrcCreatePlmnSearchContext_exist,P_WARNING,swLogPrintf("CerrcPlmnSearchContext already exists! "); +565248,1158625279,0,0,PS1,CERRC,CerrcCreatePlmnSearchContext_err,P_ERROR,swLogPrintf("CerrcPlmnSearchReq ( BCINFO ) : reqMaxCellNum is 0 ! "); +565248,1158627327,0,0,PS1,CERRC,CerrcHandlePendingPlmnSearchReq_1,P_INFO,swLogPrintf("Handle pending CerrcPlmnSearchReq. "); +565248,1158627584,0,0,PS1,CERRC,CerrcFillInfoToBcInfoList_scell,P_INFO,swLogPrintf("Set the first found cell ( %d , %d ) as serving cell. "); +565248,1158629632,0,0,PS1,CERRC,CerrcFillServingCellInfoToBcInfoList_plmn,P_WARNING,swLogPrintf("AT+BCINFO = 1 , the requestedPlmn ( %X-%X ) is not belonging to serving cell ' s PLMN ! "); +565248,1158631680,0,0,PS1,CERRC,CerrcFillNeighCellInfoToBcInfoList_exists,P_INFO,swLogPrintf("Ncell ( %d , %d ) already exists in BcInfoList ! "); +565248,1158633728,0,0,PS1,CERRC,CerrcPickUpBestNcellWithoutSib1_sib1Full,P_INFO,swLogPrintf("CerrcPickUpBestNcellWithoutSib1 : Already request %d Ncell SIB1 , exceed max SIB1 number ( %d ) , abort SIB1 reception "); +565248,1158635520,0,0,PS1,CERRC,CerrcPickUpBestNcellWithoutSib1_full,P_INFO,swLogPrintf("CerrcPickUpBestNcellWithoutSib1 : All top %d Ncells already have SIB1 , do not need to perform SIB1 reception "); +565248,1158639615,0,0,PS1,CERRC,CerrcProcessPlmnNoSib1_else,P_ERROR,swLogPrintf("Wrong PLMN search state! "); +565248,1158639872,0,0,PS1,CERRC,CerrcProcessPlmnSib1_S,P_INFO,swLogPrintf("CerrcProcessPlmnSib1 :S criterion is NOT satisfied , Srvlev ( %d ) , Squal ( %d ) "); +565248,1158641664,0,0,PS1,CERRC,CerrcProcessPlmnNcellSysInfoInd_else,P_ERROR,swLogPrintf("Wrong NCELL BCH type %e , just ingore! "); +565248,1158645759,0,0,PS1,CERRC,CerrcProcessPlmnSearchNoCellFound_else,P_ERROR,swLogPrintf("Wrong PLMN search state! "); +565248,1158647807,0,0,PS1,CERRC,CerrcHandleCephyDrxCellSearchCnf_bg,P_WARNING,swLogPrintf("Receive CephyDrxCellSearchCnf outside BG PLMN procedure ! "); +565248,1158647808,0,0,PS1,CERRC,CerrcHandleCephyDrxCellSearchCnf_state,P_WARNING,swLogPrintf("Receive CephyDrxCellSearchCnf in wrong RrcState %e! "); +565248,1158649856,0,0,PS1,CERRC,CerrcSendCephyDrxCellSearchReq_lock,P_WARNING,swLogPrintf("Start locked frequency ( %d ) cell search. "); +565248,1158653184,0,0,PS1,CERRC,CerrcSendCerrcPlmnSearchCnf_plmn,P_VALUE,swLogPrintf("CerrcPlmnSearchCnf : numOfPlmn ( %d ) , the %d PLMN ( %X-%X ) , TAC ( %X ) , isPlmnRequested ( %d ) "); +565248,1158655232,0,0,PS1,CERRC,CerrcSendCerrcPlmnSearchCnf_bcinfo,P_VALUE,swLogPrintf("CerrcPlmnSearchCnf ( BCINFO ) : numOfCell ( %d ) , the %d CELL ( %d , %d ) , RSRP ( %d ) , isServingCell ( %d ) "); +565248,1158657280,0,0,PS1,CERRC,CerrcSendCerrcPlmnSearchInd_plmn,P_VALUE,swLogPrintf("CerrcPlmnSearch ] Ind : numOfPlmn ( %d ) , the %d PLMN ( %X-%X ) , TAC ( %X ) , isPlmnRequested ( %d ) "); +565248,1158658048,0,0,PS1,CERRC,CerrcPreProcessOfPlmnSearchReq_wrong1,P_WARNING,swLogPrintf("Receive invalid CerrcPlmnSearchReq : requestedPlmn is FALSE , but type %e is NOT Manual or BcInfo ! "); +565248,1158660352,0,0,PS1,CERRC,CerrcPreProcessOfPlmnSearchReq_wrong2,P_WARNING,swLogPrintf("Receive CerrcPlmnSearchReq in wrong state : RrcState %e , RccState %e ! "); +565248,1158662912,0,0,PS1,CERRC,CerrcPreProcessOfPlmnSearchReq_only1cell,P_INFO,swLogPrintf("Receive CerrcPlmnSearchReq ( BCINFO ) : CellLocked ( %d ) , reqMaxBCCellNum ( %d ) , RccState %e , pending ConnReq ( %d ) "); +565248,1158664960,0,0,PS1,CERRC,CerrcPreProcessOfPlmnSearchReq_noNcellReq,P_INFO,swLogPrintf("Receive CerrcPlmnSearchReq ( BCINFO ) in state RccState %e , waitSiUpdate ( %d ) , siRcvingBitmap ( 0x%x ) , T321 ( %d ) ! "); +565248,1158666496,0,0,PS1,CERRC,CerrcPreProcessOfPlmnSearchReq_wrong3,P_WARNING,swLogPrintf("Receive CerrcPlmnSearchReq with no valid numOfFreq ( %d ) and numOfBand ( %d ) ! "); +565248,1158668288,0,0,PS1,CERRC,CerrcPreProcessOfPlmnSearchReq_wrong4,P_WARNING,swLogPrintf("Receive CerrcPlmnSearchReq with no numOfFreq but valid phyCellId ( %d ) ! "); +565248,1158672383,0,0,PS1,CERRC,CerrcIsPlmnSearchReqBuffered_buff1,P_INFO,swLogPrintf("Receive CerrcPlmnSearchReq while waiting for ecphyDeactCnf , buffer it "); +565248,1158672896,0,0,PS1,CERRC,CerrcIsPlmnSearchReqBuffered_buff2,P_INFO,swLogPrintf("Receive CerrcPlmnSearchReq in CsrState %e , siRcvingBitmap ( 0x%x ) , searchType %e , buffer it "); +565248,1158676479,0,0,PS1,CERRC,CerrcIsPlmnSearchReqBuffered_buff3,P_INFO,swLogPrintf("Receive CerrcPlmnSearchReq with NORMAL type , need to deact L1 first "); +565248,1158676736,0,0,PS1,CERRC,CerrcStartPlmnSearch_freqLock,P_WARNING,swLogPrintf("CerrcPlmnSearchReq : Invalid freq lock info with numOfFreq ( %d ) , numOfBand ( %d ) "); +565248,1158679552,0,0,PS1,CERRC,CerrcStartPlmnSearch_entry,P_INFO,swLogPrintf("CerrcPlmnSearchReq : SearchType %e , requestedPlmnValid ( %d ) , PLMN ( %X-%X ) , bCellLock ( %d ) "); +565248,1158682623,0,0,PS1,CERRC,CerrcStartPlmnSearch_state,P_ERROR,swLogPrintf("Cannot handle CerrcPlmnSearchReq due to wrong state! "); +565248,1158684671,0,0,PS1,CERRC,CerrcHandleCerrcNextPlmnSearchReq_else,P_ERROR,swLogPrintf("Received CerrcNextPlmnSearchReq in wrong state! "); +565248,1158685952,0,0,PS1,CERRC,CerrcSendCerrcAbortPlmnSearchCnf_plmn,P_VALUE,swLogPrintf("CerrcAbortPlmnSearchCnf : numOfPlmn ( %d ) , the %d PLMN ( %X-%X ) , TAC ( %X ) , isPlmnRequested ( %d ) "); +565248,1158688000,0,0,PS1,CERRC,CerrcSendCerrcAbortPlmnSearchCnf_bcinfo,P_VALUE,swLogPrintf("CerrcAbortPlmnSearchCnf ( BCINFO ) : numOfCell ( %d ) , the %d CELL ( %d , %d ) , RSRP ( %d ) , isServingCell ( %d ) "); +565248,1158690815,0,0,PS1,CERRC,CerrcAbortPlmnSearchDueToActReq_else,P_ERROR,swLogPrintf("Abort PLMN search due to CerrcActReq in wrong state! "); +565248,1158692863,0,0,PS1,CERRC,CerrcAbortPlmnSearch_else,P_ERROR,swLogPrintf("Abort PLMN search in wrong state! "); +565248,1158694911,0,0,PS1,CERRC,CerrcCreateConnContext_exist,P_WARNING,swLogPrintf("CerrcConnContext already exists! "); +565248,1158695168,0,0,PS1,CERRC,CerrcReleaseConnContext_freeArray,P_INFO,swLogPrintf("Free OsaIeMemInfo->pBufHdr ( 0x%X ) , numOfIeMemInfoForPhy ( %d ) "); +565248,1158699007,0,0,PS1,CERRC,CerrcUpdateUpRbConfigType_err,P_ERROR,swLogPrintf("Ask to resume a already resumed RB ! "); +565248,1158701055,0,0,PS1,CERRC,CerrcSendCeupConfigReqToUpReleaseAllRBs_err,P_ERROR,swLogPrintf("No valid CerrcConnContext ! "); +565248,1158703103,0,0,PS1,CERRC,CerrcSendCeupConfigReqToUpReleaseSuspendedAllRBs_err,P_ERROR,swLogPrintf("No valid CerrcConnSuspendContext ! "); +565248,1158703616,0,0,PS1,CERRC,CerrcSendResumeCemacMacMainConfigReqToUP_wrongType,P_INFO,swLogPrintf("logicChProTimerType %e , connSuspendContext_logicChProTimerType %e , raiActivation = %d "); +565248,1158707199,0,0,PS1,CERRC,CerrcSendResumeCemacMacMainConfigReqToUP_noSuspendContext,P_ERROR,swLogPrintf("No valid CerrcConnSuspendContext ! "); +565248,1158707200,0,0,PS1,CERRC,CerrcSendReleaseCemacMacMainConfigReqToUP_wrongType,P_INFO,swLogPrintf("connSuspendContext_logicChProTimerType %e "); +565248,1158711295,0,0,PS1,CERRC,CerrcSendReleaseCemacMacMainConfigReqToUP_noSuspendContext,P_ERROR,swLogPrintf("No valid CerrcConnSuspendContext ! "); +565248,1158711296,0,0,PS1,CERRC,CerrcSendCemacResetReqToUP_cause,P_SIG,swLogPrintf("MAC RESET , cause %e "); +565248,1158713600,0,0,PS1,CERRC,CerrcHandleCemacResetCnf_cause,P_INFO,swLogPrintf("CemacResetCnf cause is %e , CerrcGetRrcState is %e "); +565248,1158715392,0,0,PS1,CERRC,CerrcHandleCemacResetCnf_state,P_WARNING,swLogPrintf("Receive CemacResetCnf in wrong RccState %e. "); +565248,1158719487,0,0,PS1,CERRC,CerrcHandleCemacResetCnf_idle,P_WARNING,swLogPrintf("Receive CemacResetCnf in wrong IDLE state "); +565248,1158719744,0,0,PS1,CERRC,CerrcHandleRadioLinkFailure_state,P_WARNING,swLogPrintf("Cannot handle RLF in RrcState %e , RccState %e ! "); +565248,1158723583,0,0,PS1,CERRC,CerrcHandleCemacRandomAccessInd_state,P_WARNING,swLogPrintf("Received CemacRAInd in wrong RrcState ! "); +565248,1158723584,0,0,PS1,CERRC,CerrcHandleCephySyncStatusInd_unsync,P_SIG,swLogPrintf("Received %d times Out-Of-Sync! "); +565248,1158727679,0,0,PS1,CERRC,CerrcHandleCephySyncStatusInd_inSync,P_WARNING,swLogPrintf("In-Sync report should be enabled ! "); +565248,1158727936,0,0,PS1,CERRC,CerrcHandleCephySyncStatusInd_else,P_WARNING,swLogPrintf("Received CephySyncStatusInd in wrong RrcState %e , RccState %e! "); +565248,1158730240,0,0,PS1,CERRC,CerrcHandleCephyConnStatisInfoInd_Meas,P_SIG,swLogPrintf("DL MEAS STATIS INFO : RSRP ( %d / 100 ) , RSRQ ( %d / 100 ) , SNR ( %d / 100 ) "); +565248,1158732032,0,0,PS1,CERRC,CerrcHandleCephyConnStatisInfoInd_DlTpT,P_SIG,swLogPrintf("DL TpT STATIS INFO : MCS Index ( %d / 100 ) , BLER ( %d / 10000 ) "); +565248,1158734080,0,0,PS1,CERRC,CerrcHandleCephyConnStatisInfoInd_UlTpT,P_SIG,swLogPrintf("UL TpT STATIS INFO : MCS Index ( %d / 100 ) , BLER ( %d / 10000 ) "); +565248,1158735872,0,0,PS1,CERRC,CerrcHandleCerrcNasMsgReq_suspend,P_WARNING,swLogPrintf("Received CerrcNasMsgReq in wrong RccState %e after sending NasUlMsgSuspendInd ! "); +565248,1158737920,0,0,PS1,CERRC,CerrcHandleCerrcNasMsgReq_rccState,P_ERROR,swLogPrintf("Received CerrcNasMsgReq in wrong RccState %e , just ignore it ! "); +565248,1158739968,0,0,PS1,CERRC,CerrcHandleCerrcNasMsgReq_state,P_WARNING,swLogPrintf("Received CerrcNasMsgReq in wrong RrcState %e , just ignore it ! "); +565248,1158742272,0,0,PS1,CERRC,CerrcSetDedicatedInfoNAS_err,P_ERROR,swLogPrintf("nasMessageLength = %d , pNasMessage = 0x%lx "); +565248,1158746111,0,0,PS1,CERRC,CerrcFillPdcpParameters_else,P_WARNING,swLogPrintf("ROHC shoule ALWAYS be supported for eMTC / Cat1! "); +565248,1158746112,0,0,PS1,CERRC,CerrcFillUeCapabilityEutraContainer_rel,P_WARNING,swLogPrintf("Unsupported AS release version %e ! "); +565248,1158748160,0,0,PS1,CERRC,CerrcFillUeCapabilityEutraContainer_category,P_WARNING,swLogPrintf("Unsupported ueCategory %e , cast it to Category-Cat1 type. "); +565248,1158750208,0,0,PS1,CERRC,CerrcHandleDlInformationTransfer_else,P_INFO,swLogPrintf("Unsupported dedicatedInfoType ( %d ) in DlInformationTransfer , CDMA2000_1XRTT ( 1 ) , CDMA2000_HRPD ( 2 ) ! "); +565248,1158752256,0,0,PS1,CERRC,CerrcHandleCecpDataInd_dlInfo,P_ERROR,swLogPrintf("Invalid DlInformationTransfer , RccState %e "); +565248,1158754304,0,0,PS1,CERRC,CerrcHandleCecpDataInd_recfg,P_ERROR,swLogPrintf("Invalid RrcConnectionReconfiguration , RccState %e "); +565248,1158756352,0,0,PS1,CERRC,CerrcHandleCecpDataInd_rel,P_ERROR,swLogPrintf("Invalid RrcConnectionRelease , RccState %e "); +565248,1158758400,0,0,PS1,CERRC,CerrcHandleCecpDataInd_smc,P_ERROR,swLogPrintf("Invalid SecurityModeCommand , RccState %e "); +565248,1158760448,0,0,PS1,CERRC,CerrcHandleCecpDataInd_cap,P_ERROR,swLogPrintf("Invalid UeCapabilityEnquiry , RccState %e "); +565248,1158762496,0,0,PS1,CERRC,CerrcHandleCecpDataInd_count,P_ERROR,swLogPrintf("Invalid CounterCheck , RccState %e "); +565248,1158764544,0,0,PS1,CERRC,CerrcHandleCecpDataInd_rsm,P_ERROR,swLogPrintf("Invalid RrcConnectionResume , RccState %e "); +565248,1158766592,0,0,PS1,CERRC,CerrcHandleCecpDataInd_ueInfo,P_ERROR,swLogPrintf("Invalid UeInformationRequest , RccState %e "); +565248,1158768640,0,0,PS1,CERRC,CerrcHandleCecpDataInd_loggMeas,P_ERROR,swLogPrintf("Invalid LoggedMeasurementConfiguration , RccState %e "); +565248,1158772735,0,0,PS1,CERRC,CerrcHandleCecpDataInd_unSupp,P_ERROR,swLogPrintf("Unsupported DL_DCCH_MessageType_messageClassExtension_str "); +565248,1158774783,0,0,PS1,CERRC,CerrcHandleCecpDataCnf_return,P_INFO,swLogPrintf("No ulInfoTransBitmap exists in ERRC , ignore this CecpDataCnf ! "); +565248,1158775040,0,0,PS1,CERRC,CerrcHandleCecpDataCnf_entry,P_INFO,swLogPrintf("CecpDataCnf : failPduNum ( %d ) , succPduNum ( %d ) "); +565248,1158778879,0,0,PS1,CERRC,CerrcCreateConnEstContext_exist,P_WARNING,swLogPrintf("ConnEstContext already exists! "); +565248,1158780927,0,0,PS1,CERRC,CerrcHandlePendingConnOrResumeReq_1,P_INFO,swLogPrintf("Handle pending CerrcConnReq / CerrcResumeReq. "); +565248,1158781952,0,0,PS1,CERRC,CerrcCountRrcConnEstInfo_info,P_INFO,swLogPrintf("gEventStatisMode ( %d ) , nvmRrcEstSuccNum ( %d ) , nvmRrcEstFailNum ( %d ) , rrcEstSuccNum ( %d ) , rrcEstFailNum ( %d ) "); +565248,1158782976,0,0,PS1,CERRC,CerrcAccessBarringCheck_t302,P_INFO,swLogPrintf("Access is barred due to T302 or Tbarring ( %d ) is running ! "); +565248,1158785280,0,0,PS1,CERRC,CerrcAccessBarringCheck_notBar,P_INFO,swLogPrintf("Access is not barred : valid accessClass11~15 ( 0x%x ) , acBarringForSpecialAC ( 0x%x ) "); +565248,1158787584,0,0,PS1,CERRC,CerrcAccessBarringCheck_factor1,P_INFO,swLogPrintf("Access is not barred due to rand ( %d ) < acBarringFactor ( %d ) ! GCF ( %d ) "); +565248,1158789376,0,0,PS1,CERRC,CerrcAccessBarringCheck_factor2,P_INFO,swLogPrintf("Access is barred due to rand ( %d ) > = acBarringFactor ( %d ) ! "); +565248,1158793215,0,0,PS1,CERRC,CerrcAccessBarringCheck_else,P_INFO,swLogPrintf("Access is not barred due to no ' AC barring parameter ' in SIB2 "); +565248,1158793984,0,0,PS1,CERRC,CerrcAccessBarringCheckEAB_check,P_INFO,swLogPrintf("EAB check : plmnType ( %d ) , abCategory ( %d ) , accessClass0~9 ( 0x%x ) , abBarringBitmap ( 0x%x ) "); +565248,1158797311,0,0,PS1,CERRC,CerrcAccessBarringCheckEAB_bar,P_INFO,swLogPrintf("EAB access is barred "); +565248,1158799359,0,0,PS1,CERRC,CerrcAccessBarringCheckEAB_else,P_INFO,swLogPrintf("EAB access is not barred "); +565248,1158801407,0,0,PS1,CERRC,CerrcAccessBarringCheckEAB_sib14,P_INFO,swLogPrintf("EAB access is not barred due to no EAB parameters "); +565248,1158803455,0,0,PS1,CERRC,CerrcAccessBarringCheckACDC_t302,P_INFO,swLogPrintf("ACDC access is barred due to T302 is running ! "); +565248,1158803712,0,0,PS1,CERRC,CerrcAccessBarringCheckACDC_factor1,P_INFO,swLogPrintf("ACDC access is not barred due to rand ( %d ) < acBarringFactor ( %d ) ! "); +565248,1158805760,0,0,PS1,CERRC,CerrcAccessBarringCheckACDC_factor2,P_INFO,swLogPrintf("ACDC access is barred due to rand ( %d ) > = acBarringFactor ( %d ) ! "); +565248,1158809599,0,0,PS1,CERRC,CerrcAccessBarringCheckACDC_else,P_INFO,swLogPrintf("ACDC access is not barred due to no ' ACDC barring parameter ' in SIB2 "); +565248,1158810624,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_AC,P_INFO,swLogPrintf("CerrcAccessBarringCheckNB : PLMN ( %x-%x ) , plmnType ( %d ) , USIM ( AC15~AC0 ) accessClass ( 0x%x ) , abConfigPresent ( %d ) "); +565248,1158812416,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_check,P_INFO,swLogPrintf("Access Barring check : plmnType ( %d ) , abCategory ( %d ) , accessClass0~9 ( 0x%x ) , abBarringBitmap ( 0x%x ) "); +565248,1158815743,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_excp,P_INFO,swLogPrintf("Access is not barred : establishmentCause is mo-ExceptionData and abBarringForExceptionData is FALSE "); +565248,1158816000,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_notBar,P_INFO,swLogPrintf("Access is not barred : valid accessClass11~15 ( 0x%x ) , abBarringForSpecialAC ( 0x%x ) "); +565248,1158818048,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_bar,P_INFO,swLogPrintf("Access is barred : valid accessClass11~15 ( 0x%x ) , abBarringForSpecialAC ( 0x%x ) "); +565248,1158820608,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_cat,P_INFO,swLogPrintf("Access is not barred , plmnType ( %d ) , abCategory ( %d ) , accessClass ( 0x%x ) , abBarringBitmap ( 0x%x ) "); +565248,1158823935,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_abConfig,P_INFO,swLogPrintf("Access is not barred due to abConfig is absent in SIB14-NB "); +565248,1158823936,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_abEnable,P_INFO,swLogPrintf("Access is not barred , abEnabled ( %d ) or SIB14-NB is not scheduled "); +565248,1158828031,0,0,PS1,CERRC,CerrcAccessBarringCheckNB_mt,P_INFO,swLogPrintf("Access is not barred due to MT access "); +565248,1158830079,0,0,PS1,CERRC,CerrcIsAccessAllowed_t302,P_INFO,swLogPrintf("MT Access is barred due to T302 is running ! "); +565248,1158830592,0,0,PS1,CERRC,CerrcIsAccessAllowed_emgerCheck,P_INFO,swLogPrintf("AC check for emergency calls : : valid accessClass11~15 ( 0x%x ) , acBarringForMOData ( %d ) , acBarringForSpecialAC ( 0x%x ) "); +565248,1158832128,0,0,PS1,CERRC,CerrcGetAbortCause_resumeAbort,P_ERROR,swLogPrintf("accessBarReason %e is wrong "); +565248,1158834176,0,0,PS1,CERRC,CerrcGetAbortCause_establishAbort,P_ERROR,swLogPrintf("accessBarReason %e is wrong "); +565248,1158838271,0,0,PS1,CERRC,CerrcCheckIfSib14IsNeededBeforeRce_sib14,P_WARNING,swLogPrintf("SIB14 is not scheduled by NW in SIB1. "); +565248,1158838784,0,0,PS1,CERRC,CerrcPreProcessOfConnOrResumeReq_state,P_INFO,swLogPrintf("CerrcConnReq / CerrcResumeReq : RrcState %e , ActStatus %e , RccState %e "); +565248,1158840832,0,0,PS1,CERRC,CerrcPreProcessOfConnOrResumeReq_tai,P_INFO,swLogPrintf("CerrcConnReq / CerrcResumeReq : PLMN ( %x-%x ) , TAC ( 0x%x ) "); +565248,1158842880,0,0,PS1,CERRC,CerrcSendCerrcConnCnfToNAS_end,P_INFO,swLogPrintf("Send CerrcConnCnf , estStatus %e , extendedWaitTimePresent ( %d ) , extendedWaitTime ( %d s ) "); +565248,1158844928,0,0,PS1,CERRC,CerrcSendCerrcResumeCnfToNAS_end,P_INFO,swLogPrintf("Send CerrcResumeCnf , resumeStatus %e , rrcSuspendIndication ( %d ) , extendedWaitTime ( %d s ) "); +565248,1158847232,0,0,PS1,CERRC,CerrcHandleCerrcConnReq_entry,P_INFO,swLogPrintf("Receive CerrcConnReq , EstCause %e , callType %e , plmnType %e , upCIoT ( %d ) "); +565248,1158849280,0,0,PS1,CERRC,CerrcHandleCerrcResumeReq_entry,P_INFO,swLogPrintf("Receive CerrcResumeReq , EstCause %e , callType %e , plmnType %e , upCIoT ( %d ) "); +565248,1158852607,0,0,PS1,CERRC,CerrcHandleCemacRandomAccessIndInIdle_T300,P_ERROR,swLogPrintf("Received CemacRAInd when T300 is not running ! "); +565248,1158852608,0,0,PS1,CERRC,CerrcCovertEstablishmentCause_rsm,P_ERROR,swLogPrintf("Received unsupported ResumeCause %e from EMM ! "); +565248,1158854656,0,0,PS1,CERRC,CerrcCovertEstablishmentCause_est,P_ERROR,swLogPrintf("Received unsupported EstablishmentCause %e from EMM ! "); +565248,1158856704,0,0,PS1,CERRC,CerrcHandleRrcConnectionSetup_rceType,P_ERROR,swLogPrintf("Received RrcConnectionSetup in wrong RceType %e ! "); +565248,1158860799,0,0,PS1,CERRC,CerrcHandleRrcConnectionSetup_T300,P_ERROR,swLogPrintf("Received RrcConnectionSetup while T300 is not running ! "); +565248,1158862847,0,0,PS1,CERRC,CerrcHandleRrcConnectionResume_T300,P_ERROR,swLogPrintf("Received RrcConnectionResume while T300 is not running! "); +565248,1158864895,0,0,PS1,CERRC,CerrcHandleRrcConnectionReject_T300,P_ERROR,swLogPrintf("Received RrcConnectionReject while T300 is not running ! "); +565248,1158866943,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_state1,P_WARNING,swLogPrintf("Receive CemacCcchDataInd in Deactive / HIB / SLEEP2 state! "); +565248,1158866944,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_reest1,P_ERROR,swLogPrintf("Invalid RrcConnectionReestablishment , RccState %e "); +565248,1158868992,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_reestRej1,P_ERROR,swLogPrintf("Invalid RrcConnectionReestablishmentReject , RccState %e "); +565248,1158871040,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_connRej1,P_ERROR,swLogPrintf("Invalid RrcConnectionReject , RccState %e "); +565248,1158873088,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_setup1,P_ERROR,swLogPrintf("Invalid RrcConnectionSetup , RccState %e "); +565248,1158875136,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_err1,P_ERROR,swLogPrintf("Unsupported DL_CCCH_MessageType_c1 tag ( %d ) ! "); +565248,1158879231,0,0,PS1,CERRC,CerrcHandleCemacCcchDataInd_unSupp1,P_ERROR,swLogPrintf("Unsupported T_DL_CCCH_MessageType_messageClassExtension "); +565248,1158881279,0,0,PS1,CERRC,CerrcCreateConnReleaseContext_exist,P_INFO,swLogPrintf("CerrcConnReleaseContext already exists! "); +565248,1158881280,0,0,PS1,CERRC,CerrcSendCerrcReleaseCnfToNAS_cause,P_INFO,swLogPrintf("CerrcReleaseCnf : cause = %e "); +565248,1158883328,0,0,PS1,CERRC,CerrcSendCerrcReleaseIndToNAS_cause,P_INFO,swLogPrintf("CerrcReleaseInd : cause = %e "); +565248,1158887423,0,0,PS1,CERRC,CerrcHandleCerrcReleaseReq_ingore,P_INFO,swLogPrintf("Received CerrcReleaseReq while RCC_CONN_REL , ignore it! "); +565248,1158887424,0,0,PS1,CERRC,CerrcHandleDataInactivityTimerExpiry_RccState,P_INFO,swLogPrintf("Received DataInactivityTimerExpiry in wrong RccState %e , ignore it! "); +565248,1158889472,0,0,PS1,CERRC,CerrcHandleDataInactivityTimerExpiry_idle,P_WARNING,swLogPrintf("Received DataInactivityTimerExpiry in wrong RrcState %e! "); +565248,1158891520,0,0,PS1,CERRC,CerrcHandleUpAbortInd_RccState,P_INFO,swLogPrintf("Received CerrcHandleUpAbortInd in wrong RccState %e , ignore it! "); +565248,1158893568,0,0,PS1,CERRC,CerrcHandleUpAbortInd_idle,P_WARNING,swLogPrintf("Received CerrcHandleUpAbortInd in wrong RrcState %e! "); +565248,1158897663,0,0,PS1,CERRC,CerrcHandleRrcConnectionRelease_csfb,P_WARNING,swLogPrintf("Receive RrcConnectionRelease indicates CSFB but we do NOT support ! "); +565248,1158899711,0,0,PS1,CERRC,CerrcHandleRrcConnectionRelease_suspend,P_WARNING,swLogPrintf("Receive RrcConnectionRelease indicates suspend but not including resumeIdentity ! "); +565248,1158901759,0,0,PS1,CERRC,CerrcCreateConnReEstContext_exist,P_WARNING,swLogPrintf("CerrcConnReEstContext already exists! "); +565248,1158901760,0,0,PS1,CERRC,CerrcUpdateDataInactivityTimerFromNvm_nvm,P_INFO,swLogPrintf("set the DataInactivityTimer according to NVM ( %d ) ! "); +565248,1158904320,0,0,PS1,CERRC,CerrcCheckDrbToAddModList_check2,P_WARNING,swLogPrintf("New DRB , rlc_ConfigPresent ( %d ) , logicalChannelIdentityPresent ( %d ) and logicalChannelConfigPresent ( %d ) should present ! "); +565248,1158905856,0,0,PS1,CERRC,CerrcCheckSrbToAddModList_check1,P_WARNING,swLogPrintf("Setup a New SRB , srb_Identity ( %d ) , not SRB2 ! "); +565248,1158908416,0,0,PS1,CERRC,CerrcCheckSrbToAddModList_check2,P_WARNING,swLogPrintf("New SRB , srb_Identity ( %d ) , rlc_ConfigPresent ( %d ) , logicalChannelConfigPresent ( %d ) should present ! "); +565248,1158911999,0,0,PS1,CERRC,CerrcSetDedicatedPhysicalConfig_error,P_ERROR,swLogPrintf("No valid decode memory address pBufHdr for CephyDedicatedConfigReq ! "); +565248,1158912256,0,0,PS1,CERRC,CerrcUpdateSrbInfo_initial,P_INFO,swLogPrintf("Inital set SRB ( %d ) update-type as %e. "); +565248,1158914304,0,0,PS1,CERRC,CerrcRevertSrbDrbsConfig_info1,P_INFO,swLogPrintf("Revert SRB [ %d ] from Backup-Context due Handover Fail , type %e. "); +565248,1158916352,0,0,PS1,CERRC,CerrcRevertSrbDrbsConfig_info2,P_INFO,swLogPrintf("Revert DRB [ %d ] from Backup-Context due Handover Fail , type %e. "); +565248,1158918656,0,0,PS1,CERRC,CerrcStoreDecodeMemoryForPhy_rec,P_WARNING,swLogPrintf("This decode memory OsaIeMemInfo->pBufHdr ( 0x%X ) is already exists! index ( %d ) , numOfIeMemInfoForPhy ( %d ) "); +565248,1158920448,0,0,PS1,CERRC,CerrcStoreDecodeMemoryForPhy_full,P_WARNING,swLogPrintf("numOfIeMemInfoForPhy ( %d ) exceeds MAX limitation ( %d ) , something wrong in PHY "); +565248,1158922752,0,0,PS1,CERRC,CerrcStoreDecodeMemoryForPhy_save,P_INFO,swLogPrintf("Store decode memory OsaIeMemInfo->pBufHdr ( 0x%X ) , numOfIeMemInfoForPhy ( %d ) , index ( %d ) "); +565248,1158924288,0,0,PS1,CERRC,CerrcStoreDecodeMemoryForPhy_err,P_ERROR,swLogPrintf("Should not come here! numOfIeMemInfoForPhy ( %d ) "); +565248,1158926848,0,0,PS1,CERRC,CerrcFindDecMemForPhy_find,P_INFO,swLogPrintf("OsaIeMemInfo->pBufHdr ( 0x%X ) exists in array! numOfIeMemInfoForPhy ( %d ) , needClear ( %d ) "); +565248,1158930431,0,0,PS1,CERRC,CerrcSendCephyResetInd_send,P_WARNING,swLogPrintf("CERRC triggers CephyResetInd "); +565248,1158932479,0,0,PS1,CERRC,CerrcHandleCephyFreeCfgMemInd_HO,P_INFO,swLogPrintf("Received CephyFreeCfgMemInd but cannot free ieMemInfo since this decode memory is using by handover context! "); +565248,1158932736,0,0,PS1,CERRC,CerrcHandleCephyFreeCfgMemInd_free,P_INFO,swLogPrintf("Received CephyFreeCfgMemInd and free the OsaIeMemInfo->pBufHdr ( 0x%X ) , numOfIeMemInfoForPhy ( %d ) "); +565248,1158934784,0,0,PS1,CERRC,CerrcHandleCephyFreeCfgMemInd_ignore,P_WARNING,swLogPrintf("Ignore this CephyFreeCfgMemInd! Cannot find pBufHdr ( 0x%X ) in ERRC stored array , numOfIeMemInfoForPhy ( %d ) "); +565248,1158936832,0,0,PS1,CERRC,CerrcHandleCephyFreeCfgMemInd_state,P_WARNING,swLogPrintf("Ignore this CephyFreeCfgMemInd! CerrcGetConnContext ( 0x%X ) , pBufHdr ( 0x%X ) "); +565248,1158940671,0,0,PS1,CERRC,CerrcCreateHandoverContext_exist,P_WARNING,swLogPrintf("CerrcHandoverContext already exists! "); +565248,1158942719,0,0,PS1,CERRC,CerrcUpdateHandoverContext_warn,P_WARNING,swLogPrintf("MobilityControlInfo include rachSkipr14. "); +565248,1158944767,0,0,PS1,CERRC,CerrcHandleSysInfoBlockType1DuringHO_err,P_ERROR,swLogPrintf("HandoverContext not exist! "); +565248,1158946815,0,0,PS1,CERRC,CerrcHandleSecurityActionDuringHO_warn,P_WARNING,swLogPrintf("Not support HO Security interRAT type! "); +565248,1158947072,0,0,PS1,CERRC,CerrcHandleCephyHandoverCnf_HO,P_WARNING,swLogPrintf("HANDOVER to CELL ( %d , %d ) "); +565248,1158948864,0,0,PS1,CERRC,CerrcHandleCephyHandoverCnf_else,P_WARNING,swLogPrintf("Received CephyHandoverCnf in wrong RccState %e ! "); +565248,1158952959,0,0,PS1,CERRC,CerrcHandleHandoverAfterRandomAccessInd_T304,P_WARNING,swLogPrintf("Received CemacRAInd->ERROR while T304 is NOT running ! "); +565248,1158955007,0,0,PS1,CERRC,CerrcHandleReestablishmentAfterRandomAccessInd_T301,P_WARNING,swLogPrintf("Received CemacRAInd->ERROR while T301 is NOT running ! "); +565248,1158957055,0,0,PS1,CERRC,CerrcSendRrcConnectionReconfigurationComplete_notSupport,P_ERROR,swLogPrintf("UE not support CA! "); +565248,1158957056,0,0,PS1,CERRC,CerrcSendRRCConnectionReestablishmentRequest_err,P_ERROR,swLogPrintf("Unsupported reestblishementCause %d ! "); +565248,1158959104,0,0,PS1,CERRC,CerrcDeriveAsKey_algId,P_INFO,swLogPrintf("KeyType %e "); +565248,1158961664,0,0,PS1,CERRC,CerrcSyncNH_HCC,P_INFO,swLogPrintf("currentHopChainingCount ( %d ) , nextHopChainingCount ( %d ) , bInitialNH ( %d ) "); +565248,1158963200,0,0,PS1,CERRC,CerrcCheckSMCIntegrityProtection_count,P_INFO,swLogPrintf("The correct NAS UL COUNT is 0x%x "); +565248,1158965760,0,0,PS1,CERRC,CerrcCalcXmacI_input,P_INFO,swLogPrintf("EIA %e , dlCount ( %d ) , bearer ( %d ) "); +565248,1158967296,0,0,PS1,CERRC,CerrcCalcXmacI_xmacI,P_INFO,swLogPrintf("xMacI ( 0x%x ) "); +565248,1158969600,0,0,PS1,CERRC,CerrcCheckIfIntegrityProtectionPassed_fail,P_INFO,swLogPrintf("xMacI ( %x ) , macI ( %x ) "); +565248,1158971392,0,0,PS1,CERRC,CerrcStoreSib2SiRawData_store,P_INFO,swLogPrintf("Store the SIB2 SI data since it contains other SIBx , sibTypeMapBitmap ( 0x%x ) "); +565248,1158973696,0,0,PS1,CERRC,CerrcReleaseSib2SiRawData_free,P_INFO,swLogPrintf("Clear the stored SIB2 SI data of Cell ( %d , %d ) "); +565248,1158977535,0,0,PS1,CERRC,CerrcProcessSibxInSameSiWithSib2_dec,P_INFO,swLogPrintf("Decode and apply the stored SIB2 SI "); +565248,1158978304,0,0,PS1,CERRC,CerrcProcessSibxInSameSiWithSib2_cell,P_ERROR,swLogPrintf("Discard the stored SIB2 SI of Cell ( %d , %d ) , since current Cell ( %d , %d ) "); +565248,1158979840,0,0,PS1,CERRC,CerrcProcessSibxInSameSiWithSib2_else,P_INFO,swLogPrintf("No SIBx in the SIB2 SI need to be processed , siMissingBitmap ( 0x%x ) , siRequiredBitmap ( 0x%x ) "); +565248,1158983679,0,0,PS1,CERRC,CerrcSendCephyInterFreqConfigReq_freq,P_WARNING,swLogPrintf("There is no supported inter-freq in SIB5 ! "); +565248,1158985727,0,0,PS1,CERRC,CerrcSendCephyInterFreqConfigReq_ext,P_ERROR,swLogPrintf("We need to extend MAX inter-Freq number ! "); +565248,1158985984,0,0,PS1,CERRC,CerrcSendCephyInterFreqConfigReq_info,P_INFO,swLogPrintf("InterFreqConfigReq [ %d ] = %d "); +565248,1158987776,0,0,PS1,CERRC,CerrcCopySib2Data_ase,P_WARNING,swLogPrintf("Need to extend additionalSpectrumEmission ( %d ) ! "); +565248,1158991871,0,0,PS1,CERRC,CerrcCopySib3Data_sDeltaP,P_INFO,swLogPrintf("s_SearchDeltaP_r14 is present in SIB3! "); +565248,1158993919,0,0,PS1,CERRC,CerrcCopySib3Data_sDeltaPNvm,P_INFO,swLogPrintf("sSearchDeltaP is set according to NVM! "); +565248,1158995967,0,0,PS1,CERRC,CerrcCopySib3Data_sDeltaPZero,P_INFO,swLogPrintf("sSearchDeltaP is set to 0 ! "); +565248,1158996224,0,0,PS1,CERRC,CerrcCopySib5Data_newEarfcn,P_INFO,swLogPrintf("convert to EARFCN ( %d ) according to selectedBand ( %d ) !! "); +565248,1158998016,0,0,PS1,CERRC,CerrcCopySib5Data_intra,P_WARNING,swLogPrintf("Skip the intra-freq EARFCN ( %d ) in SIB5 !! "); +565248,1159002111,0,0,PS1,CERRC,CerrcCopySib5Data_ext,P_ERROR,swLogPrintf("We need to extend MAX inter-Freq number ! "); +565248,1159002368,0,0,PS1,CERRC,CerrcCopySib5Data_newEarfcnExt,P_INFO,swLogPrintf("convert to EARFCN ( %d ) according to selectedBand ( %d ) !! "); +565248,1159004160,0,0,PS1,CERRC,CerrcCopySib5Data_intraExt,P_WARNING,swLogPrintf("Skip the intra-freq EARFCN ( %d ) in SIB5 !! "); +565248,1159006976,0,0,PS1,CERRC,CerrcCheckIfAlreadyReAssembled_info,P_INFO,swLogPrintf("value pair messageIdentifier ( %d ) , serialNumber ( %d ) is the same as the last assembled value pair messageIdentifier ( %d ) , serialNumber ( %d ) "); +565248,1159008256,0,0,PS1,CERRC,CerrcCopySib11Data_hasRecv,P_INFO,swLogPrintf("The warningMessageSegmentNumber ( %d ) has already buffered , ingore it. "); +565248,1159010304,0,0,PS1,CERRC,CerrcReceivedAllSegsForOneCmasWarningMessage_recvAll,P_INFO,swLogPrintf("CMAS Warning Msg ( %d ) has received completed. "); +565248,1159014399,0,0,PS1,CERRC,CerrcSib1Decode_else,P_WARNING,swLogPrintf("Received SIB1 in unexpected state! "); +565248,1159014400,0,0,PS1,CERRC,CerrcHandleSiStoredTimerExpiry_est,P_INFO,swLogPrintf("SI 3 H timer expired in RccState %e , pending until return IDLE! "); +565248,1159018495,0,0,PS1,CERRC,CerrcHandleSiStoredTimerExpiry_bg,P_INFO,swLogPrintf("SI 3 H timer expired during BG PLMN , abort PLMN first! "); +565248,1159020543,0,0,PS1,CERRC,CerrcHandleSiStoredTimerExpiry_resel,P_INFO,swLogPrintf("SI 3 H timer expired during reselection , pending until reselection finished! "); +565248,1159022591,0,0,PS1,CERRC,CerrcHandleSiStoredTimerExpiry_conn,P_INFO,swLogPrintf("SI 3 H timer expired in CERRC connected state , pending until return IDLE! "); +565248,1159024639,0,0,PS1,CERRC,CerrcHandleSiStoredTimerExpiry_deact,P_WARNING,swLogPrintf("SI 3 H timer expired in CERRC deactive state! "); +565248,1159024640,0,0,PS1,CERRC,CerrcCheckIfStoredSiOutDated_expriy,P_SIG,swLogPrintf("SI 3 H timer expired , last updating time is %d "); +565248,1159028735,0,0,PS1,CERRC,CerrcHandleCephyWaitBoundaryInd_err,P_ERROR,swLogPrintf("ERRC is not waiting for BCCH boundary !! "); +565248,1159030783,0,0,PS1,CERRC,CerrcHandleCephyWaitBoundaryInd_else,P_ERROR,swLogPrintf("Received CephyWaitBoundaryInd with timeLen 0 ms !! "); +565248,1159031040,0,0,PS1,CERRC,CerrcProcessMibAfterLeavingConnectedState_siMod,P_INFO,swLogPrintf("Perform cell search after leaving connected state , due to sysInfoValueTag is changed from ( %d ) to ( %d ) ! "); +565248,1159032832,0,0,PS1,CERRC,CerrcProcessMibAfterLeavingConnectedState_crc,P_INFO,swLogPrintf("MIB fail during SI update after leaving connected state , MIB crcResult is %d ! "); +565248,1159034880,0,0,PS1,CERRC,CerrcProcessSiUpdtMib_crc,P_INFO,swLogPrintf("MIB fail during SI update , MIB crcResult is %d ! "); +565248,1159037184,0,0,PS1,CERRC,CerrcRequestSibsProc_noSib,P_INFO,swLogPrintf("No SIB is requested : siRequiredBitmap ( 0x%X ) , siValidBitmap ( 0x%X ) "); +565248,1159039232,0,0,PS1,CERRC,CerrcRequestCertainSibsProc_noSib,P_INFO,swLogPrintf("No SIB is requested : siRequiredBitmap ( 0x%X ) , siValidBitmap ( 0x%X ) "); +565248,1159043071,0,0,PS1,CERRC,CerrcProcessMibInIdle_else,P_ERROR,swLogPrintf("Received MIB in wrong PLMN search state! "); +565248,1159043072,0,0,PS1,CERRC,CerrcProcessMibInConn_state,P_WARNING,swLogPrintf("Receive CephySysInfoInd in wrong RccState %e! "); +565248,1159045120,0,0,PS1,CERRC,CerrcProcessSibsInConn_csrState,P_WARNING,swLogPrintf("Receive CephySysInfoInd in wrong CsrState %e! "); +565248,1159047168,0,0,PS1,CERRC,CerrcProcessSibsInConn_state,P_WARNING,swLogPrintf("Receive CephySysInfoInd in wrong RccState %e! "); +565248,1159049984,0,0,PS1,CERRC,CerrcHandleCephySysInfoInd_entry,P_INFO,swLogPrintf("Cell ( %d , %d ) , crcResult ( %d ) , type %e "); +565248,1159053311,0,0,PS1,CERRC,CerrcHandleCephySysInfoInd_ret,P_INFO,swLogPrintf("Receive CephySysInfoInd while waiting for CephyDeactCnf "); +565248,1159053312,0,0,PS1,CERRC,CerrcHandleCephySysInfoInd_state,P_WARNING,swLogPrintf("Receive CephySysInfoInd in wrong RrcState %e! "); +565248,1159056128,0,0,PS1,CERRC,CerrcHandleCephyNcellSysInfoInd_entry,P_INFO,swLogPrintf("Cell ( %d , %d ) , crcResult ( %d ) , type %e "); +565248,1159057664,0,0,PS1,CERRC,CerrcHandleCephyNcellSysInfoInd_state,P_WARNING,swLogPrintf("Receive CephyNcellSysInfoInd in wrong RrcState %e or RccState %e! "); +565248,1159059456,0,0,PS1,CERRC,CerrcHandleT300Expiry_rccState,P_WARNING,swLogPrintf("T300 Expiry in wrong RccState %e ! "); +565248,1159061504,0,0,PS1,CERRC,CerrcHandleT301Expiry_rccState,P_WARNING,swLogPrintf("T301 expiry in wrong RccState %e ! "); +565248,1159063552,0,0,PS1,CERRC,CerrcHandleT311Expiry_rccState,P_WARNING,swLogPrintf("T311 expiry in wrong RccState %e ! "); +565248,1159065600,0,0,PS1,CERRC,CerrcHandleT304Expiry_rccState,P_WARNING,swLogPrintf("T304 expiry in wrong RccState %e ! "); +565248,1159069695,0,0,PS1,CERRC,CerrcHandleBcchModExpiry_err,P_ERROR,swLogPrintf("ERRC is not waiting for BCCH boundary !! "); +565248,1159069696,0,0,PS1,CERRC,CerrcHandleCellSearchGuardTimerExpiry_csrState,P_WARNING,swLogPrintf("CellSearchGuardTimerExpiry in wrong CsrState %e ! "); +565248,1159071744,0,0,PS1,CERRC,CerrcHandleCellSearchGuardTimerExpiry_rccState,P_WARNING,swLogPrintf("CellSearchGuardTimerExpiry in wrong RccState %e ! "); +565248,1159073792,0,0,PS1,CERRC,CerrcHandleCellSearchGuardTimerExpiry_rrcState,P_WARNING,swLogPrintf("CellSearchGuardTimerExpiry in wrong RrcState %e ! "); +565248,1159075840,0,0,PS1,CERRC,CerrcHandleCampingGuardTimerExpiry_csrState,P_WARNING,swLogPrintf("CampingGuardTimerExpiry in wrong CsrState %e ! "); +565248,1159078144,0,0,PS1,CERRC,CerrcHandleCampingGuardTimerExpiry_rccState,P_WARNING,swLogPrintf("CampingGuardTimerExpiry in wrong RrcState %e , RccState %e ! "); +565248,1159079936,0,0,PS1,CERRC,CerrcHandleReceivingSib14GuardTimerExpiry_rccState,P_WARNING,swLogPrintf("SIB14 guard timer expiry in wrong RccState %e ! "); +565248,1159084031,0,0,PS1,CERRC,CerrcHandleMibUpdateGuardTimerExpiry_entry,P_WARNING,swLogPrintf("MIB guard timer expiry !! "); +565248,1159086079,0,0,PS1,CERRC,CerrcHandleMibUpdateGuardTimerExpiry_else,P_WARNING,swLogPrintf("MIB guard timer expiry unexpected !! "); +565248,1159086592,0,0,PS1,CERRC,CerrcDebugForTimer_timer,P_ERROR,swLogPrintf("GosTimerIsRunning ( 0x%x ) = %d ! IS_IRQ_MODE ( %d ) "); +565248,1159088384,0,0,PS1,CERRC,CerrcDebugForTimer_timerNull,P_ERROR,swLogPrintf("Cannot find timer %e in ERRC timer list ! pTimerList ( %x ) "); +565248,1159090432,0,0,PS1,CERRC,CerrcIsTimerRunning_T300,P_ERROR,swLogPrintf("ERRC T300 running status ( %d ) , Gos T300 running status ( %d ) "); +565248,1159092480,0,0,PS1,CERRC,CerrcStartTimer_Id,P_INFO,swLogPrintf("CerrcStartTimer : timerId %e , timerPeriod = %d ms "); +565248,1159094272,0,0,PS1,CERRC,CerrcStartTimer_timerId,P_INFO,swLogPrintf("Add timerId allocated by OS : osTimerId_t = 0x%x "); +565248,1159096320,0,0,PS1,CERRC,CerrcStartTimer_fail,P_ERROR,swLogPrintf("Start timer fail : osStatus_t ( %d ) "); +565248,1159098624,0,0,PS1,CERRC,CerrcStopTimerIfRunning_stop,P_INFO,swLogPrintf("CerrcStopTimer : timerId %e , osTimerId_t = 0x%x "); +565248,1159100416,0,0,PS1,CERRC,CerrcHandleTimerExpiry_start,P_WARNING,swLogPrintf("timerId %e has not started : "); +565248,1159102976,0,0,PS1,CERRC,CerrcHandleTimerExpiry_Id,P_INFO,swLogPrintf("CerrcHandleTimerExpiry : timerId %e , osTimerId_t = 0x%x , timerPeriod = %d ms "); +565248,1159106559,0,0,PS1,CERRC,CerrcHandleTimerExpiry_deact_cnf,P_ERROR,swLogPrintf("CERRC_T_DEACT_CNF_GUARD Timer expiry , please foward it to PHY. "); +565248,1159108607,0,0,PS1,CERRC,CerrcHandleTimerExpiry_mac_reset_cnf,P_ERROR,swLogPrintf("CERRC_T_MAC_RESET_CNF_GUARD Timer expiry , please foward it to PHY. "); +565248,1159108608,0,0,PS1,CERRC,CerrcHandleTimerExpiry_errCat1,P_ERROR,swLogPrintf("timerId is invalid : %d "); +565248,1159110912,0,0,PS1,CERRC,CerrcStartHibTimer_Id,P_INFO,swLogPrintf("CerrcStartHibTimer : hibTimerId %e , timerPeriod = %d ms "); +565248,1159112704,0,0,PS1,CERRC,CerrcStopHibTimerIfRunning_stop,P_INFO,swLogPrintf("CerrcHibStopTimer : hibTimerId %e "); +565248,1159114752,0,0,PS1,CERRC,CerrcHandleHibTimerExpiry_err,P_VALUE,swLogPrintf("Unexpected hibTimerId : %d "); +565248,1159116800,0,0,PS1,CERRC,CerrcRsrpMapping_err,P_ERROR,swLogPrintf("Invalid rsrp ( %d ) ! "); +565248,1159118848,0,0,PS1,CERRC,CerrcRsrqMapping_err,P_ERROR,swLogPrintf("Invalid rsrq ( %d ) ! "); +565248,1159120896,0,0,PS1,CERRC,CerrcNRsrpMapping_err,P_ERROR,swLogPrintf("Invalid rsrp ( %d ) ! "); +565248,1159123200,0,0,PS1,CERRC,CerrcNRsrqMapping_err,P_ERROR,swLogPrintf("Invalid rsrq ( %d ) , rsrqMapping ( %d ) ! "); +565248,1159124992,0,0,PS1,CERRC,CerrcGetRfBandHalfDuplex_err,P_ERROR,swLogPrintf("Cannot find Band ( %d ) in UE support RfBandList ! "); +565248,1159129087,0,0,PS1,CERRC,CerrcBootCheckPagingUeIdentity_csDomain,P_INFO,swLogPrintf("This PagingRecord is for CS domain , ignore it! "); +565248,1159129344,0,0,PS1,CERRC,CerrcBootCheckPagingUeIdentity_wrongStmsi,P_INFO,swLogPrintf("Mismatch s-TMSI , UE MMEC ( 0x%x ) , mTMSI ( 0x%x ) "); +565248,1159133183,0,0,PS1,CERRC,CerrcBootCheckPagingUeIdentity_stmsi,P_INFO,swLogPrintf("Paging for s-TMSI but sTMSIPresent is FALSE "); +565248,1159135231,0,0,PS1,CERRC,CerrcBootCheckPagingUeIdentity_imsi,P_INFO,swLogPrintf("Paging for IMSI but bIMSIPresent is FALSE "); +565248,1159135232,0,0,PS1,CERRC,CerrcBootCheckPagingUeIdentity_tag,P_WARNING,swLogPrintf("Invalid pPagingRecord->tag ( %d ) ! "); +565248,1159139327,0,0,PS1,CERRC,CerrcBootCheckPagingUeIdentity_mismatch,P_INFO,swLogPrintf("This PagingRecord is not for this UE! PagingRecord mismatch! "); +565248,1159141375,0,0,PS1,CERRC,CerrcBootDecodeSkipUnsupportedExtension_else,P_WARNING,swLogPrintf("Invalid lengh of extension ! "); +565248,1159142656,0,0,PS1,CERRC,CerrcBootUpDueToPaging_wakeup,P_SIG,swLogPrintf("Wake up due to Paging ! UeId ( %d ) , SI ( %d ) , SI_eDRX ( %d ) , ETWS ( %d ) , CMAS ( %d ) , EAB ( %d ) "); +565248,1159145471,0,0,PS1,CERRC,CerrcBootUpDueToPaging_decInvalid,P_INFO,swLogPrintf("This Paging has nothing to do with us ! "); +565248,1159147519,0,0,PS1,CERRC,CerrcBootUpDueToPaging_decErr,P_WARNING,swLogPrintf("The paging info cannot be decoded correctly ! "); +565248,1159147520,0,0,PS1,CERRC,CerrcBootUpDueToPaging_pagingType,P_WARNING,swLogPrintf("Unsupported pagingType ( %d ) "); +565248,1159149824,0,0,PS1,CERRC,CerrcBootUpDueToLowMeas_slp2,P_SIG,swLogPrintf("SLEEP2 : SERV CELL : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1159151872,0,0,PS1,CERRC,CerrcBootUpDueToLowMeas_hib,P_SIG,swLogPrintf("HIBERNATE : SERV CELL : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1159154432,0,0,PS1,CERRC,CerrcBootUpDueToLowMeas_rmTrue,P_SIG,swLogPrintf("CERRC HIB : Wake up due to RSRP ( %d ) < = rmRsrpThreshold ( %d ) || RSRQ ( %d ) < = nRsrqThreshold ( %d ) "); +565248,1159155968,0,0,PS1,CERRC,CerrcBootUpDueToLowMeas_update,P_SIG,swLogPrintf("CERRC HIB : Wake up due to need to update rmRsrpThreshold to ( %d ) , sSearchDeltaP ( %d ) "); +565248,1159158528,0,0,PS1,CERRC,CerrcBootUpDueToLowMeas_true,P_SIG,swLogPrintf("CERRC HIB : Wake up due to RSRP ( %d ) < = nRsrpThreshold ( %d ) || RSRQ ( %d ) < = nRsrqThreshold ( %d ) "); +565248,1159161855,0,0,PS1,CERRC,CerrcLeaveSleep2DueToReselection_HIB,P_INFO,swLogPrintf("CERRC vote to enter HIB , but enter SLEEP2 instead! "); +565248,1159162624,0,0,PS1,CERRC,CerrcLeaveSleep2DueToReselection_serv,P_SIG,swLogPrintf("SLEEP2 : SERV CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1159165951,0,0,PS1,CERRC,CerrcLeaveSleep2DueToReselection_reselect,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to CELL RESELECTION ! "); +565248,1159167999,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_criS,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to CriterionS is not fulfilled ! "); +565248,1159169024,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_entry,P_VALUE,swLogPrintf("CERRC SLEEP2 : s-SearchDeltaP ( %d ) , Srxlev ( %d ) , SrxlevRef ( %d ) , bRMCriterionFulfilled ( %d ) , higherPriorityBitmap ( 0x%X ) "); +565248,1159172095,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_stopIntra,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to STOP intra-meas ! "); +565248,1159174143,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_startIntra,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to START intra-meas ! "); +565248,1159176191,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_startInter,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to START inter-meas ! "); +565248,1159176448,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_lowerInter,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to MODIFY lower priority inter-meas ! bLowerPriorityNeeded ( %d ) , bLowerPriorityOngoing ( %d ) "); +565248,1159180287,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_stopInter,P_SIG,swLogPrintf("CERRC SLEEP2 : Wake up due to STOP inter-meas ! "); +565248,1159182335,0,0,PS1,CERRC,CerrcLeaveSleep2DueToServMeas_stay,P_INFO,swLogPrintf("Stay in SLEEP2 state ! "); +565248,1159182592,0,0,PS1,CERRC,CerrcAddIdleIntraFreqCellToDB_info1,P_INFO,swLogPrintf("INTRA FREQ CELL ( %d , %d ) has existed in intra neighcell DB , update its value. "); +565248,1159184640,0,0,PS1,CERRC,CerrcAddIdleIntraFreqCellToDB_info2,P_INFO,swLogPrintf("Add INTRA FREQ CELL ( %d , %d ) into intra neighcell DB. "); +565248,1159186688,0,0,PS1,CERRC,CerrcAddIdleIntraFreqCellToDB_info3,P_INFO,swLogPrintf("Remove the oldest cell and add INTRA FREQ CELL ( %d , %d ) into intra neighcell DB. "); +565248,1159188736,0,0,PS1,CERRC,CerrcAddIdleInterFreqCellToDB_info1,P_INFO,swLogPrintf("INTER FREQ CELL ( %d , %d ) has existed in inter neighcell DB , update its value. "); +565248,1159190784,0,0,PS1,CERRC,CerrcAddIdleInterFreqCellToDB_info2,P_INFO,swLogPrintf("Add INTER FREQ CELL ( %d , %d ) into inter neighcell DB. "); +565248,1159192832,0,0,PS1,CERRC,CerrcAddIdleInterFreqCellToDB_info3,P_INFO,swLogPrintf("Remove the oldest cell and add INTER FREQ CELL ( %d , %d ) into inter neighcell DB. "); +565248,1159195136,0,0,PS1,CERRC,CerrcRefreshIdleIntraCellsInDB_del,P_INFO,swLogPrintf("Cell ( %d , %d ) has NOT been detected over %d ms , remove it from intra neighcell DB. "); +565248,1159197184,0,0,PS1,CERRC,CerrcRefreshIdleInterCellsInDB_del,P_INFO,swLogPrintf("Cell ( %d , %d ) has NOT been detected over %d ms , remove it from inter neighcell DB. "); +565248,1159199488,0,0,PS1,CERRC,CerrcProcessIdleIntraCellMeasInd_intra,P_SIG,swLogPrintf("INTRA FREQ CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1159200768,0,0,PS1,CERRC,CerrcProcessIdleInterCellMeasInd_intra,P_WARNING,swLogPrintf("Received intra frequency ( %d ) in inter meas , skip it ! "); +565248,1159203584,0,0,PS1,CERRC,CerrcProcessIdleInterCellMeasInd_inter,P_SIG,swLogPrintf("INTER FREQ CELL ( %d , %d ) : RSRP ( %d ) , RSRQ ( %d ) "); +565248,1159204864,0,0,PS1,CERRC,CerrcProcessIdleInterCellMeasInd_err,P_WARNING,swLogPrintf("Cannot find Inter frequency ( %d ) in DB , skip it ! "); +565248,1159208704,0,0,PS1,CERRC,CerrcStoreIdleServCellMeasInd_end,P_VALUE,swLogPrintf("Serving CELL ( %d , %d ) : Srxlev ( %d ) , sQual ( %d ) , rank ( %d ) , qRxLevMin ( %d ) , qOffsetTemp ( %d ) , qHyst ( %d ) "); +565248,1159211007,0,0,PS1,CERRC,CerrcIsWaitForSiUpdate_SiWating,P_INFO,swLogPrintf("Don ' t start reselect evaluate while SI update is ongoing. "); +565248,1159212800,0,0,PS1,CERRC,CerrcCalcIntraCellRank_rank,P_VALUE,swLogPrintf("Intra CELL ( %d , %d ) : Srxlev ( %d ) , sQual ( %d ) , rank ( %d ) , qRxLevMin ( %d ) , qOffset ( %d ) , qOffsetTemp ( %d ) "); +565248,1159214848,0,0,PS1,CERRC,CerrcCalcInterCellRank_rank,P_VALUE,swLogPrintf("Inter CELL ( %d , %d ) : Srxlev ( %d ) , sQual ( %d ) , rank ( %d ) , qRxLevMin ( %d ) , qOffset ( %d ) , qOffsetTemp ( %d ) "); +565248,1159215616,0,0,PS1,CERRC,CerrcSkipReselFreq_intra,P_INFO,swLogPrintf("Skip intra-freq due to : numOfCell ( %d ) , top cell rankValid ( %d ) , barredByBestRank ( %d ) "); +565248,1159218176,0,0,PS1,CERRC,CerrcSkipReselFreq_inter,P_INFO,swLogPrintf("Skip inter-freq ( %d ) due to : numOfCell ( %d ) , top cell rankValid ( %d ) , barredByBestRank ( %d ) , freqLock ( %d ) "); +565248,1159219968,0,0,PS1,CERRC,CerrcEvalReselCriterionHigherPriority_rsrq,P_INFO,swLogPrintf("CELL ( %d , %d ) NOT fulfills reselection criteria : Squal ( %d ) > threshXHighQ ( %d ) "); +565248,1159222016,0,0,PS1,CERRC,CerrcEvalReselCriterionHigherPriority_rsrp,P_INFO,swLogPrintf("CELL ( %d , %d ) NOT fulfills reselection criteria : Srxlev ( %d ) > threshXHigh ( %d ) "); +565248,1159224576,0,0,PS1,CERRC,CerrcEvalReselCriterionLowerPriority_rsrq,P_INFO,swLogPrintf("CELL ( %d , %d ) NOT fulfills reselection criteria : serving Squal ( %d ) < threshServingLowQ ( %d ) && neighbor Squal ( %d ) > threshXLowQ ( %d ) "); +565248,1159226624,0,0,PS1,CERRC,CerrcEvalReselCriterionLowerPriority_rsrp,P_INFO,swLogPrintf("CELL ( %d , %d ) NOT fulfills reselection criteria : serving Srxlev ( %d ) < threshServingLow ( %d ) && neighbor Srxlev ( %d ) > threshXLow ( %d ) "); +565248,1159227648,0,0,PS1,CERRC,CerrcEvalReselCriterion_startT0,P_INFO,swLogPrintf("CELL ( %d , %d ) fulfills reselection criteria , reselect to it immediately as Treselection is 0 . "); +565248,1159229952,0,0,PS1,CERRC,CerrcEvalReselCriterion_reselectTime,P_INFO,swLogPrintf("CELL ( %d , %d ) already fulfills reselection criteria over Treselection ( %d ) seconds. "); +565248,1159232000,0,0,PS1,CERRC,CerrcEvalReselCriterion_startT,P_INFO,swLogPrintf("CELL ( %d , %d ) fulfills reselection criteria , but still need Treselection ( %d ) seconds to continue evaluate it. "); +565248,1159234048,0,0,PS1,CERRC,CerrcGetHighestRankedCell_end,P_INFO,swLogPrintf("Highest ranked CELL ( %d , %d ) , rank ( %d ) "); +565248,1159237631,0,0,PS1,CERRC,CerrcRemoveInvalidBestRankBar_intra,P_INFO,swLogPrintf("Intra-freq barredByBestRank flag is set as FALSE ! "); +565248,1159237632,0,0,PS1,CERRC,CerrcRemoveInvalidBestRankBar_inter,P_INFO,swLogPrintf("Inter-freq ( %d ) barredByBestRank flag is set as FALSE ! "); +565248,1159240192,0,0,PS1,CERRC,CerrcUpdateFreqBarredByBestRank_intra,P_INFO,swLogPrintf("Intra-freq barredByBestRank flag set as TRUE due to highest ranked intra-CELL ( %d ) : barredByPlmn ( %d ) , barredByTa ( %d ) "); +565248,1159242496,0,0,PS1,CERRC,CerrcUpdateFreqBarredByBestRank_inter,P_INFO,swLogPrintf("Inter-freq ( %d ) barredByBestRank flag set as TRUE due to highest ranked inter-CELL ( %d ) : barredByPlmn ( %d ) , barredByTa ( %d ) "); +565248,1159243776,0,0,PS1,CERRC,CerrcUpdateFreqBarredByBestRank_else,P_INFO,swLogPrintf("CampOnState %e "); +565248,1159246336,0,0,PS1,CERRC,CerrcCheckIfReselectNeeded_intra,P_INFO,swLogPrintf("CampOnState %e , barredByPlmn ( %d ) , barredByTa ( %d ) "); +565248,1159248384,0,0,PS1,CERRC,CerrcCheckIfReselectNeeded_inter,P_INFO,swLogPrintf("CampOnState %e , barredByPlmn ( %d ) , barredByTa ( %d ) "); +565248,1159251967,0,0,PS1,CERRC,CerrcCheckIfReselectNeeded_else,P_INFO,swLogPrintf("Reselect is not needed due to camping less than 1 second. "); +565248,1159252224,0,0,PS1,CERRC,CerrcCheckIfReselectNeeded_pingpong,P_SIG,swLogPrintf("Cell ( %d , %d ) will trigger pingpong reselection , NOT reselect to it. "); +565248,1159254272,0,0,PS1,CERRC,CerrcCheckIfReselectNeeded_need,P_INFO,swLogPrintf("Start to reselect to Cell ( %d , %d ) . "); +565248,1159256576,0,0,PS1,CERRC,CerrcSleep2ReselEvaluation_worseTargetCell,P_SIG,swLogPrintf("Target Cell ( %d , %d ) RSRP is worse than serving cell ( %d ) dbm , NOT reselect to it. "); +575488,1178601472,0,0,PS1,NAS,CemmSetNasEventOperReq_1,P_VALUE,swLogPrintf("Unexpected set parameter type : %d "); +575488,1178603779,0,0,PS1,NAS,CemmProcGetRplmnNameReq_1,P_VALUE,swLogPrintf("Full name from NITZ : %s , Short Name : %s "); +575488,1178605568,0,0,PS1,NAS,CemmTrrigerRrcReleaseReq_1,P_INFO,swLogPrintf("If there is emmSpecificProcedure : %d "); +575488,1178607616,0,0,PS1,NAS,CeNasBePendingSignal_1,P_WARNING,swLogPrintf("CE NAS , can ' t process signal : 0x%x , as CE NAS not woken up from deep sleep , pending it "); +575488,1178609664,0,0,PS1,NAS,CeNasStartTimer_1,P_INFO,swLogPrintf("Start NAS timer period is %d MS "); +575488,1178613759,0,0,PS1,NAS,CeNasStartTimer_2,P_WARNING,swLogPrintf("Timer is already started! "); +575488,1178613761,0,0,PS1,NAS,CeNasStopTimer_1,P_INFO,swLogPrintf("EMM timer %s stop "); +575488,1178615809,0,0,PS1,NAS,CeNasStopTimer_2,P_INFO,swLogPrintf("SMS timer %s stop "); +575488,1178617857,0,0,PS1,NAS,CeNasStopHibTimer_1,P_INFO,swLogPrintf("NAS Hibernate timer %s stop "); +575488,1178619904,0,0,PS1,NAS,CeNasTimerExpiry_1,P_VALUE,swLogPrintf("Unexpected timerEnum : %d "); +575488,1178621952,0,0,PS1,NAS,CeNasHibTimerExpiry_1,P_VALUE,swLogPrintf("Unexpected hibTimerId : %d "); +575488,1178626047,0,0,PS1,NAS,CeNasTaskEntry_2,P_VALUE,swLogPrintf("CENAS vote to enter HIB state "); +575488,1178628095,0,0,PS1,NAS,CeNasTaskEntry_3,P_VALUE,swLogPrintf("CENAS vote to enter SLEEP2 state "); +575488,1178630143,0,0,PS1,NAS,CeNasTaskEntry_not_hib_1,P_VALUE,swLogPrintf("CENAS cannot enter HIB state "); +575488,1178632191,0,0,PS1,NAS,CeNasTaskEntry_slp2_1,P_VALUE,swLogPrintf("CENAS vote to enter SLEEP2 state "); +575488,1178634239,0,0,PS1,NAS,CeNasTaskEntry_4,P_VALUE,swLogPrintf("CENAS cannot enter HIB state "); +575488,1178636287,0,0,PS1,NAS,CeNasTaskEntry_5,P_VALUE,swLogPrintf("CENAS cannot enter SLEEP2 state "); +575488,1178636544,0,0,PS1,NAS,DecodeAttachAccept_1,P_WARNING,swLogPrintf("esmPduLen 0x%x is equal or greater than inDataLen 0x%x! "); +576512,1180700671,0,0,PS1,CEMM,CemmRegRequest_1,P_INFO,swLogPrintf("Receiving registration while in connected state "); +576512,1180702719,0,0,PS1,CEMM,CemmEmergencyCampRequest_1,P_INFO,swLogPrintf("Receiving emergency camp request while in connected state , buffer it. "); +576512,1180704767,0,0,PS1,CEMM,CemmSetCpsmsParm_1,P_INFO,swLogPrintf("set AT+CPSMS under PSM state , service status is No service! "); +576512,1180706815,0,0,PS1,CEMM,CemmSetCpsmsParm_2,P_INFO,swLogPrintf("set AT+CPSMS under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No service! "); +576512,1180707328,0,0,PS1,CEMM,CemmSetCpsmsParm_3,P_VALUE,swLogPrintf("emmState is %d , bUlMsgSuspend is %d , bWaitCampInd is %d , can ' t define tau pending it! "); +576512,1180710911,0,0,PS1,CEMM,CemmSetCpsmsParm_4,P_INFO,swLogPrintf("set AT+CPSMS while PLMN searching! "); +576512,1180710912,0,0,PS1,CEMM,CemmSetCpsmsParm_5,P_VALUE,swLogPrintf("set AT+CPSMS while specific procedure %d is ongoing! "); +576512,1180715007,0,0,PS1,CEMM,CemmSetCedrxsParm_1,P_INFO,swLogPrintf("set AT+CEDRXS under PSM state , service status is No service! "); +576512,1180717055,0,0,PS1,CEMM,CemmSetCedrxsParm_2,P_INFO,swLogPrintf("set AT+CEDRXS under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No service! "); +576512,1180717568,0,0,PS1,CEMM,CemmSetCedrxsParm_3,P_VALUE,swLogPrintf("emmState is %d , bUlMsgSuspend is %d , bWaitCampInd is %d , can ' t define tau pending it! "); +576512,1180721151,0,0,PS1,CEMM,CemmSetCedrxsParm_4,P_INFO,swLogPrintf("set AT+CEDRXS while PLMN searching! "); +576512,1180721152,0,0,PS1,CEMM,CemmSetCedrxsParm_5,P_VALUE,swLogPrintf("set AT+CEDRXS while specific procedure %d is ongoing! "); +576512,1180725247,0,0,PS1,CEMM,CemmSetCciotoptParm_1,P_INFO,swLogPrintf("set AT+CCIOTOPT under PSM state , service status is No service! "); +576512,1180727295,0,0,PS1,CEMM,CemmSetCciotoptParm_2,P_INFO,swLogPrintf("set AT+CCIOTOPT under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No service! "); +576512,1180727808,0,0,PS1,CEMM,CemmSetCciotoptParm_3,P_VALUE,swLogPrintf("emmState is %d , bUlMsgSuspend is %d , bWaitCampInd is %d , can ' t define tau pending it! "); +576512,1180731391,0,0,PS1,CEMM,CemmSetCciotoptParm_4,P_INFO,swLogPrintf("set AT+CCIOTOPT while PLMN searching! "); +576512,1180731392,0,0,PS1,CEMM,CemmSetCciotoptParm_5,P_VALUE,swLogPrintf("set AT+CCIOTOPT while specific procedure %d is ongoing! "); +576512,1180735487,0,0,PS1,CEMM,CemmSetCemodeParm_1,P_INFO,swLogPrintf("set AT+CEMODE under PSM state , service status is No service! "); +576512,1180737535,0,0,PS1,CEMM,CemmSetCemodeParm_2,P_INFO,swLogPrintf("set AT+CEMODE under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No service! "); +576512,1180738048,0,0,PS1,CEMM,CemmSetCemodeParm_3,P_VALUE,swLogPrintf("emmState is %d , bUlMsgSuspend is %d , bWaitCampInd is %d , can ' t define tau pending it! "); +576512,1180741631,0,0,PS1,CEMM,CemmSetCemodeParm_4,P_INFO,swLogPrintf("set AT+CEMODE while PLMN searching! "); +576512,1180741632,0,0,PS1,CEMM,CemmSetCemodeParm_5,P_VALUE,swLogPrintf("set AT+CEMODE while specific procedure %d is ongoing! "); +576512,1180743680,0,0,PS1,CEMM,CemmSetParmReq_nasT_1,P_WARNING,swLogPrintf("CE NAS , CAM set NAS timer , not invalid tId : %d "); +576512,1180745728,0,0,PS1,CEMM,CemmSetParmReq_1,P_WARNING,swLogPrintf("CE NAS , Unexpected set parameter type : %d "); +576512,1180747776,0,0,PS1,CEMM,CemmGetParmReq_w_1,P_WARNING,swLogPrintf("CE NAS , unknown parmType : %d , can ' t get related CAM param info "); +576512,1180751871,0,0,PS1,CEMM,CemmPowerRecoverRequest_1,P_INFO,swLogPrintf("NW not configured T3324 , use AT+ECCFG configured T3324MaxValueS! "); +576512,1180752128,0,0,PS1,CEMM,CemmProcTriggerTauReq_1,P_VALUE,swLogPrintf("emmSpecificProcedure is %d ; emmState is %d "); +576512,1180754432,0,0,PS1,CEMM,SaveForbiddenTaiToTinyContext_1,P_VALUE,swLogPrintf("This forbidden tai ( 0x%x , 0x%x , 0x%x ) is already in tiny ctx "); +576512,1180756736,0,0,PS1,CEMM,SaveForbiddenTaiToTinyContext_2,P_VALUE,swLogPrintf("forbiddenTaiNum is %d , mcc is 0x%X , mnc is 0x%x , tac is 0x%X "); +576512,1180758528,0,0,PS1,CEMM,SaveForbiddenTaiToTinyContext_3,P_VALUE,swLogPrintf("This forbidden tai ( 0x%x , 0x%x , 0x%x ) is already in tiny ctx "); +576512,1180760832,0,0,PS1,CEMM,SaveForbiddenTaiToTinyContext_4,P_VALUE,swLogPrintf("forbiddenTaiNum is %d , mcc is 0x%X , mnc is 0x%x , tac is 0x%X "); +576512,1180764159,0,0,PS1,CEMM,SaveTaiListToTinyContext_1,P_INFO,swLogPrintf("Number of allocated TAI exceed CE_NAS_TINY_CTX_TAI_NUM! "); +576512,1180766207,0,0,PS1,CEMM,SaveTaiListToTinyContext_2,P_INFO,swLogPrintf("Number of allocated TAI exceed CE_NAS_TINY_CTX_TAI_NUM! "); +576512,1180768255,0,0,PS1,CEMM,SaveTaiListToTinyContext_3,P_INFO,swLogPrintf("Number of allocated TAI exceed CE_NAS_TINY_CTX_TAI_NUM! "); +576512,1180770303,0,0,PS1,CEMM,PendingEsmDataOutOfDate_1,P_INFO,swLogPrintf("Pending data is out of date , and need to discard it. "); +576512,1180772351,0,0,PS1,CEMM,PendingEsmDataOutOfDate_2,P_INFO,swLogPrintf("Pending data is out of date , and not need to discard , there ' s no pending data in DR / ESM , still retry "); +576512,1180774399,0,0,PS1,CEMM,PendingEsmDataOutOfDate_3,P_INFO,swLogPrintf("Pending data is out of date , and not need to discard , but there ' s new pending data in DR / ESM , discard current data. "); +576512,1180776447,0,0,PS1,CEMM,CemmStartT3324Check_1,P_SIG,swLogPrintf("Start T3324 "); +576512,1180778495,0,0,PS1,CEMM,CemmStartT3324Check_2,P_SIG,swLogPrintf("T3324 assigned by NW is zero "); +576512,1180780543,0,0,PS1,CEMM,CemmStartT3412Check_1,P_SIG,swLogPrintf("Start T3412 "); +576512,1180782591,0,0,PS1,CEMM,EpsAttachStateChange_1,P_WARNING,swLogPrintf("updateEpsnscToNvm "); +576512,1180784639,0,0,PS1,CEMM,EpsAttachStateChange_2,P_WARNING,swLogPrintf("updateEpslociToNvm "); +576512,1180786687,0,0,PS1,CEMM,EpsConnectionStateChange_4,P_WARNING,swLogPrintf("updateEpsnscToNvm "); +576512,1180788735,0,0,PS1,CEMM,EpsConnectionStateChange_5,P_WARNING,swLogPrintf("updateEpslociToNvm "); +576512,1180790783,0,0,PS1,CEMM,EmmSelectProtocolState_1,P_WARNING,swLogPrintf("State changing wrong! "); +576512,1180790785,0,0,PS1,CEMM,EmmChangeProtocolState_1,P_INFO,swLogPrintf("EMM state change to %s "); +576512,1180794879,0,0,PS1,CEMM,GetAttachProcedure_1,P_INFO,swLogPrintf("No Attach Procedure! "); +576512,1180795904,0,0,PS1,CEMM,GetTauProcedure_1,P_VALUE,swLogPrintf("epsUpdateStatus is %d ; tauRequired is %d ; pendingTau is %d , tauForSmsOnly is %d , updateCs is %d "); +576512,1180798975,0,0,PS1,CEMM,GetTauProcedure_2,P_INFO,swLogPrintf("Normal TAU is triggered "); +576512,1180801023,0,0,PS1,CEMM,GetTauProcedure_3,P_INFO,swLogPrintf("Normal TAU is triggered "); +576512,1180803071,0,0,PS1,CEMM,GetTauProcedure_4,P_INFO,swLogPrintf("Periodic TAU is triggered "); +576512,1180805119,0,0,PS1,CEMM,GetTauProcedure_5,P_INFO,swLogPrintf("No TAU is triggered "); +576512,1180807167,0,0,PS1,CEMM,GetTauProcedure_6,P_INFO,swLogPrintf("Combined TA updating with IMSI ATTACH is triggered "); +576512,1180809215,0,0,PS1,CEMM,GetTauProcedure_7,P_INFO,swLogPrintf("Combined TAU is triggered "); +576512,1180811263,0,0,PS1,CEMM,GetTauProcedure_8,P_INFO,swLogPrintf("Combined TAU is triggered "); +576512,1180813311,0,0,PS1,CEMM,GetTauProcedure_9,P_INFO,swLogPrintf("Periodic TAU is triggered "); +576512,1180815359,0,0,PS1,CEMM,GetTauProcedure_10,P_INFO,swLogPrintf("No TAU is triggered "); +576512,1180815360,0,0,PS1,CEMM,GetTauProcedure_11,P_INFO,swLogPrintf("Current service is %d , No Tau Procedure is triggered! "); +576512,1180817408,0,0,PS1,CEMM,EmmAttachAbnormal_1,P_VALUE,swLogPrintf("Attach attempt counter is %d "); +576512,1180821503,0,0,PS1,CEMM,EmmAttachAbnormal_2,P_INFO,swLogPrintf("Delete GUTI! "); +576512,1180821504,0,0,PS1,CEMM,EmmCombinedAttachOnlyEpsSucceed_1,P_VALUE,swLogPrintf("Combined ATTACH successful for EPS only , TAU attempt counter is %d "); +576512,1180823552,0,0,PS1,CEMM,EmmTauAbnormal_1,P_VALUE,swLogPrintf("TAU attempt counter is %d "); +576512,1180825856,0,0,PS1,CEMM,IsAttachWithImsi_1,P_VALUE,swLogPrintf("power on with IMSI is %d , power on attach end is %d "); +576512,1180827904,0,0,PS1,CEMM,IsAttachWithoutIntegrityProtected_1,P_VALUE,swLogPrintf("power on without integrity protected is %d , power on attach end is %d "); +576512,1180830208,0,0,PS1,CEMM,GetTaiType_1,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) , TAC ( 0x%x ) is in the list of ' forbidden tracking areas for regional provision of service ' ! "); +576512,1180832256,0,0,PS1,CEMM,GetTaiType_2,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) , TAC ( 0x%x ) is in the list of ' forbidden tracking areas for regional provision of service ' ! "); +576512,1180834304,0,0,PS1,CEMM,GetTaiType_3,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) , TAC ( 0x%x ) is in the list of ' forbidden tracking areas for roaming ' ! "); +576512,1180836352,0,0,PS1,CEMM,GetTaiType_4,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) , TAC ( 0x%x ) is in the list of ' forbidden tracking areas for roaming ' ! "); +576512,1180837888,0,0,PS1,CEMM,GetCurrentAttachService_1,P_VALUE,swLogPrintf("Current service type is %d "); +576512,1180841983,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_1,P_INFO,swLogPrintf("Can ' t perform ATTACH while T3402 is running! "); +576512,1180844031,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_2,P_INFO,swLogPrintf("Still can perform ATTACH while T3346 is running! "); +576512,1180846079,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_3,P_INFO,swLogPrintf("Can ' t perform ATTACH while T3346 is running! "); +576512,1180848127,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_4,P_INFO,swLogPrintf("Can ' t perform ATTACH while Ul Msg is Suspend by Rrc! "); +576512,1180850175,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_5,P_INFO,swLogPrintf("Can ' t perform TAU while T3402 is running! "); +576512,1180852223,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_6,P_INFO,swLogPrintf("Still Can perform TAU while T3346 is running! "); +576512,1180854271,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_7,P_INFO,swLogPrintf("Can ' t perform TAU while T3346 is running! "); +576512,1180856319,0,0,PS1,CEMM,CemmCheckAttachOrTauTriggered_8,P_INFO,swLogPrintf("Can ' t perform TAU while Ul Msg is Suspend by Rrc! "); +576512,1180856321,0,0,PS1,CEMM,CemmCheckAnySpecificProcedure_1,P_INFO,swLogPrintf("Current EMM state %s "); +576512,1180860415,0,0,PS1,CEMM,CemmInitialise_1,P_INFO,swLogPrintf("EMM submodule initialise! "); +576512,1180862463,0,0,PS1,CEMM,CemmInitialise_2,P_WARNING,swLogPrintf("Read IMEI failed , use default IMEI "); +576512,1180862464,0,0,PS1,CEMM,CemmPmuDeepSlpEnterCallBack_1,P_VALUE,swLogPrintf("Cemm Enter Deep Sleep , the lowPowerState is %d "); +576512,1180864768,0,0,PS1,CEMM,FreeCachedCpData_1,P_VALUE,swLogPrintf("Del CpDataIndex ( index is %d ) and corresponding reTransMsgType ( subscript is %d ) "); +576512,1180866816,0,0,PS1,CEMM,CemmSaveCpDataInCacheQueue_1,P_VALUE,swLogPrintf("Cp Data is already in cache queue , just update index from %d to %d "); +576512,1180868864,0,0,PS1,CEMM,CemmSaveCpDataInCacheQueue_2,P_VALUE,swLogPrintf("Cp Data Cache Queue is full , Free the oldest cp Data ( index is %d ) , then save this cp data ( index is %d ) "); +576512,1180870912,0,0,PS1,CEMM,CemmDelCpDataInCacheQueue_1,P_VALUE,swLogPrintf("Find CpDataIndex ( %d ) in cache queue ( %d ) , Del Succ! "); +576512,1180872704,0,0,PS1,CEMM,CemmDelCpDataInCacheQueue_2,P_INFO,swLogPrintf("Can ' t find CpDataIndex ( %d ) in cache queue , Del Fail! "); +576512,1180876799,0,0,PS1,CEMM,CemmClearRetransmissionInfo_1,P_INFO,swLogPrintf("Clear retransmit failed messages! "); +576512,1180878847,0,0,PS1,CEMM,CemmCheckEnterHibernate_1,P_INFO,swLogPrintf("Not allow enter hib "); +576512,1180880895,0,0,PS1,CEMM,CemmCheckAnyPsm_1,P_SIG,swLogPrintf("T3324 assigned by NW is zero "); +576512,1180882943,0,0,PS1,CEMM,CemmCheckAnyPsm_2,P_SIG,swLogPrintf("EmmStartTimer : timerId is T3324 "); +576512,1180882944,0,0,PS1,CEMM,RandomizeDownlinkEmmMessage_1,P_VALUE,swLogPrintf("data length is %d "); +576512,1180887039,0,0,PS1,CEMM,RandomizeDownlinkEmmMessage_3,P_INFO,swLogPrintf("Only PD and message type "); +576512,1180889087,0,0,PS1,CEMM,EcnbTraceEmmCause_1,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_IMSI_UNKNOWN_IN_HSS "); +576512,1180891135,0,0,PS1,CEMM,EcnbTraceEmmCause_2,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_ILLEGAL_UE "); +576512,1180893183,0,0,PS1,CEMM,EcnbTraceEmmCause_3,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_IMEI_NOT_ACCEPTED "); +576512,1180895231,0,0,PS1,CEMM,EcnbTraceEmmCause_4,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_ILLEGAL_ME "); +576512,1180897279,0,0,PS1,CEMM,EcnbTraceEmmCause_5,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_EPS_SERVICES_NOT_ALLOWED "); +576512,1180899327,0,0,PS1,CEMM,EcnbTraceEmmCause_6,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_EPS_AND_NON_EPS_SERVICES_NOT_ALLOWED "); +576512,1180901375,0,0,PS1,CEMM,EcnbTraceEmmCause_7,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_UE_ID_CAN_NOT_BE_DERIVED_IN_NETWORK "); +576512,1180903423,0,0,PS1,CEMM,EcnbTraceEmmCause_8,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_IMPLICITLY_DETACHED "); +576512,1180905471,0,0,PS1,CEMM,EcnbTraceEmmCause_9,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_PLMN_NOT_ALLOWED "); +576512,1180907519,0,0,PS1,CEMM,EcnbTraceEmmCause_10,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_TRACKING_AREA_NOT_ALLOWED "); +576512,1180909567,0,0,PS1,CEMM,EcnbTraceEmmCause_11,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA "); +576512,1180911615,0,0,PS1,CEMM,EcnbTraceEmmCause_12,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_EPS_SERVICE_NOT_ALLOWED_IN_THIS_PLMN "); +576512,1180913663,0,0,PS1,CEMM,EcnbTraceEmmCause_13,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_NO_SUITABLE_CELLS_IN_TRACKING_AREA "); +576512,1180915711,0,0,PS1,CEMM,EcnbTraceEmmCause_14,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_MSC_TEMPORARILY_NOT_REACHABLE "); +576512,1180917759,0,0,PS1,CEMM,EcnbTraceEmmCause_15,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_NETWORK_FAILURE "); +576512,1180919807,0,0,PS1,CEMM,EcnbTraceEmmCause_16,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_CS_DOMAIN_NOT_AVAILABLE "); +576512,1180921855,0,0,PS1,CEMM,EcnbTraceEmmCause_17,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_ESM_FAILURE "); +576512,1180923903,0,0,PS1,CEMM,EcnbTraceEmmCause_18,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_MAC_FAILURE "); +576512,1180925951,0,0,PS1,CEMM,EcnbTraceEmmCause_19,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_SYNCH_FAILURE "); +576512,1180927999,0,0,PS1,CEMM,EcnbTraceEmmCause_20,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_CONGESTION "); +576512,1180930047,0,0,PS1,CEMM,EcnbTraceEmmCause_21,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_UE_SECURITY_CAPAILITIES_MISMATCH "); +576512,1180932095,0,0,PS1,CEMM,EcnbTraceEmmCause_22,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_SECURITY_MODE_REJECTED_UNSPECIFIED "); +576512,1180934143,0,0,PS1,CEMM,EcnbTraceEmmCause_23,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_NOT_AUTHORIZED_FOR_THIS_CSG "); +576512,1180936191,0,0,PS1,CEMM,EcnbTraceEmmCause_24,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_NON_EPS_AUTHENTICATION_UNACCEPTABLE "); +576512,1180938239,0,0,PS1,CEMM,EcnbTraceEmmCause_25,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_REQUESTED_SERVICE_OPTION_NOT_AUTHORIZED_IN_THIS_PLMN "); +576512,1180940287,0,0,PS1,CEMM,EcnbTraceEmmCause_26,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_CS_SERVICE_TEMPORARILY_NOT_AVAILABLE "); +576512,1180942335,0,0,PS1,CEMM,EcnbTraceEmmCause_27,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_NO_EPS_BEARER_CONTEXT_ACTIVATED "); +576512,1180944383,0,0,PS1,CEMM,EcnbTraceEmmCause_28,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_SERVERE_NETWORK_FAILURE "); +576512,1180946431,0,0,PS1,CEMM,EcnbTraceEmmCause_29,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_SYMANTICALLY_INCORRECT_MESSAGE "); +576512,1180948479,0,0,PS1,CEMM,EcnbTraceEmmCause_30,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_INVALID_MANDATORY_INFORMATION "); +576512,1180950527,0,0,PS1,CEMM,EcnbTraceEmmCause_31,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_MESSAGE_TYPE_NON_EXISTENT_OR_NOT_IMPLEMENTED "); +576512,1180952575,0,0,PS1,CEMM,EcnbTraceEmmCause_32,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_MESSAGE_TYPE_NOT_COMPATIBLE_WITH_THE_PROTOCOL_STATE "); +576512,1180954623,0,0,PS1,CEMM,EcnbTraceEmmCause_33,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_INFORMATION_ELEMENT_NON_EXISTENT_OR_NOT_IMPLEMENTED "); +576512,1180956671,0,0,PS1,CEMM,EcnbTraceEmmCause_34,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_CONDITIONAL_IE_ERROR "); +576512,1180958719,0,0,PS1,CEMM,EcnbTraceEmmCause_35,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_MESSAGE_NOT_COMPATIBLE_WITH_THE_PROTOCOL_STATE "); +576512,1180960767,0,0,PS1,CEMM,EcnbTraceEmmCause_36,P_INFO,swLogPrintf("Reject cause-EMM_CAUSE_PROTOCOL_ERROR_UNSPECIFIED "); +576512,1180960768,0,0,PS1,CEMM,EcnbTraceEmmCause_37,P_VALUE,swLogPrintf("Unknown EMM cause %d! "); +576512,1180964863,0,0,PS1,CEMM,ProcessGutiReallocCommand_1,P_INFO,swLogPrintf("Ignore GUTI reallocation during MO detach! "); +576512,1180966911,0,0,PS1,CEMM,ProcessGutiReallocCommand_2,P_INFO,swLogPrintf("Ignore GUTI reallocation during TAU! "); +576512,1180968959,0,0,PS1,CEMM,ProcessAuthenticationRequest_1,P_INFO,swLogPrintf("Ignore authentication request while USIM is absent! "); +576512,1180971007,0,0,PS1,CEMM,ProcessAuthenticationRequest_2,P_INFO,swLogPrintf("Ignore authentication request during power off! "); +576512,1180973055,0,0,PS1,CEMM,ProcessAuthenticationRequest_3,P_INFO,swLogPrintf("RAND is same as previous one "); +576512,1180975103,0,0,PS1,CEMM,ProcessAuthenticationRequest_4,P_INFO,swLogPrintf("Separation bit checking failed! "); +576512,1180977151,0,0,PS1,CEMM,ProcessIdentityRequest_1,P_INFO,swLogPrintf("Ignore Identity Request during power off detach! "); +576512,1180979199,0,0,PS1,CEMM,ProcessSecurityModeCommand_1,P_INFO,swLogPrintf("EIA0 is not supported! "); +576512,1180981247,0,0,PS1,CEMM,ProcessSecurityModeCommand_2,P_INFO,swLogPrintf("Replayed security capability mismatch! "); +576512,1180983295,0,0,PS1,CEMM,ProcessSecurityModeCommand_3,P_INFO,swLogPrintf("eKSI mismatch! "); +576512,1180985343,0,0,PS1,CEMM,ProcessAttachAccept_1,P_INFO,swLogPrintf("Received ATTACH ACCEPT with same GUTI as last one! "); +576512,1180987391,0,0,PS1,CEMM,ProcessAttachAccept_2,P_INFO,swLogPrintf("NW configured T3324 > = AT+ECCFG configured T3324MaxValueS , use AT configured T3324MaxValueS! "); +576512,1180989439,0,0,PS1,CEMM,ProcessAttachAccept_3,P_INFO,swLogPrintf("NW not configured T3324 , use AT+ECCFG configured T3324MaxValueS! "); +576512,1180991487,0,0,PS1,CEMM,ProcessAttachAccept_4,P_INFO,swLogPrintf("Attach successful for EPS services and not accepted for SMS services! "); +576512,1180993535,0,0,PS1,CEMM,ProcessAttachAccept_5,P_INFO,swLogPrintf("tauForSmsCount exceed the max limit , no longer try to register sms in this plmn! "); +576512,1180995583,0,0,PS1,CEMM,ProcessDetachAccept_1,P_INFO,swLogPrintf("ProcessDetachAccept : ignore DETACH ACCEPT during poweroff detach! "); +576512,1180997631,0,0,PS1,CEMM,ProcessTauAccept_1,P_INFO,swLogPrintf("NW configured T3324 > = AT+ECCFG configured T3324MaxValueS , use AT configured T3324MaxValueS! "); +576512,1180999679,0,0,PS1,CEMM,ProcessTauAccept_2,P_INFO,swLogPrintf("NW not configured T3324 , use AT+ECCFG configured T3324MaxValueS! "); +576512,1181001727,0,0,PS1,CEMM,ProcessTauAccept_3,P_INFO,swLogPrintf("Tau successful for EPS services and not accepted for SMS services! "); +576512,1181003775,0,0,PS1,CEMM,ProcessTauAccept_4,P_INFO,swLogPrintf("tauForSmsCount exceed the max limit , no longer try to register sms in this plmn! "); +576512,1181005823,0,0,PS1,CEMM,ProcessTauAccept_5,P_INFO,swLogPrintf("Waiting the indication of TAU COMPLETE transmission succeed. "); +576512,1181007871,0,0,PS1,CEMM,CemmDrReestablishRequest_1,P_INFO,swLogPrintf("Now can ' t initiate service request "); +576512,1181009919,0,0,PS1,CEMM,CemmDrReestablishRequest_2,P_INFO,swLogPrintf("TauRequired is TRUE , perform a TAU firstly "); +576512,1181009921,0,0,PS1,CEMM,CemmDrReestablishRequest_3,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181014015,0,0,PS1,CEMM,CemmDrReestablishRequest_4,P_INFO,swLogPrintf("Waiting cell camp indication , pending DR reestablish request! "); +576512,1181016063,0,0,PS1,CEMM,CemmDrReestablishRequest_5,P_INFO,swLogPrintf("Already pended another request! "); +576512,1181018111,0,0,PS1,CEMM,CemmDrReestablishRequest_6,P_INFO,swLogPrintf("Waiting for RRC Act Cnf , Pending the DrReestablishRequest "); +576512,1181020159,0,0,PS1,CEMM,CemmDrReestablishRequest_7,P_INFO,swLogPrintf("Dr re-establish is received under EMM_REGISTERED_NO_CELL_AVAILABLE! "); +576512,1181022207,0,0,PS1,CEMM,EcnbTraceEmmMessageType_1,P_INFO,swLogPrintf("Sending ATTACH_REQUEST "); +576512,1181024255,0,0,PS1,CEMM,EcnbTraceEmmMessageType_2,P_INFO,swLogPrintf("Receiving ATTACH_ACCEPT "); +576512,1181026303,0,0,PS1,CEMM,EcnbTraceEmmMessageType_3,P_INFO,swLogPrintf("Sending ATTACH_COMPLETE "); +576512,1181028351,0,0,PS1,CEMM,EcnbTraceEmmMessageType_4,P_INFO,swLogPrintf("Receiving ATTACH_REJECT "); +576512,1181030399,0,0,PS1,CEMM,EcnbTraceEmmMessageType_5,P_INFO,swLogPrintf("Sending DETACH_REQUEST "); +576512,1181032447,0,0,PS1,CEMM,EcnbTraceEmmMessageType_6,P_INFO,swLogPrintf("Receiving DETACH_REQUEST "); +576512,1181034495,0,0,PS1,CEMM,EcnbTraceEmmMessageType_7,P_INFO,swLogPrintf("Sending DETACH_ACCEPT "); +576512,1181036543,0,0,PS1,CEMM,EcnbTraceEmmMessageType_8,P_INFO,swLogPrintf("Receiving DETACH_ACCEPT "); +576512,1181038591,0,0,PS1,CEMM,EcnbTraceEmmMessageType_9,P_INFO,swLogPrintf("Sending TA_UPDATE_REQUEST "); +576512,1181040639,0,0,PS1,CEMM,EcnbTraceEmmMessageType_10,P_INFO,swLogPrintf("Receiving TA_UPDATE_ACCEPT "); +576512,1181042687,0,0,PS1,CEMM,EcnbTraceEmmMessageType_11,P_INFO,swLogPrintf("Sending TA_UPDATE_COMPLETE "); +576512,1181044735,0,0,PS1,CEMM,EcnbTraceEmmMessageType_12,P_INFO,swLogPrintf("Receiving TA_UPDATE_REJECT "); +576512,1181046783,0,0,PS1,CEMM,EcnbTraceEmmMessageType_13,P_INFO,swLogPrintf("Sending EXTENDED_SERVICE_REQUEST "); +576512,1181048831,0,0,PS1,CEMM,EcnbTraceEmmMessageType_14,P_INFO,swLogPrintf("Sending CONTROL_PLANE_SERVICE_REQUEST "); +576512,1181050879,0,0,PS1,CEMM,EcnbTraceEmmMessageType_15,P_INFO,swLogPrintf("Receiving SERVICE_REJECT "); +576512,1181052927,0,0,PS1,CEMM,EcnbTraceEmmMessageType_16,P_INFO,swLogPrintf("Receiving SERVICE_ACCEPT "); +576512,1181054975,0,0,PS1,CEMM,EcnbTraceEmmMessageType_17,P_INFO,swLogPrintf("Receiving GUTI_REALLOC_COMMAND "); +576512,1181057023,0,0,PS1,CEMM,EcnbTraceEmmMessageType_18,P_INFO,swLogPrintf("Sending GUTI_REALLOC_COMPLETE "); +576512,1181059071,0,0,PS1,CEMM,EcnbTraceEmmMessageType_19,P_INFO,swLogPrintf("Receiving AUTHENTICATION_REQUEST "); +576512,1181061119,0,0,PS1,CEMM,EcnbTraceEmmMessageType_20,P_INFO,swLogPrintf("Sending AUTHENTICATION_RESPONSE "); +576512,1181063167,0,0,PS1,CEMM,EcnbTraceEmmMessageType_21,P_INFO,swLogPrintf("Receiving AUTHENTICATION_REJECT "); +576512,1181065215,0,0,PS1,CEMM,EcnbTraceEmmMessageType_22,P_INFO,swLogPrintf("Sending AUTHENTICATION_FAILURE "); +576512,1181067263,0,0,PS1,CEMM,EcnbTraceEmmMessageType_23,P_INFO,swLogPrintf("Receiving IDENTITY_REQUEST "); +576512,1181069311,0,0,PS1,CEMM,EcnbTraceEmmMessageType_24,P_INFO,swLogPrintf("Sending IDENTITY_RESPONSE "); +576512,1181071359,0,0,PS1,CEMM,EcnbTraceEmmMessageType_25,P_INFO,swLogPrintf("Receiving SECURITY_MODE_COMMAND "); +576512,1181073407,0,0,PS1,CEMM,EcnbTraceEmmMessageType_26,P_INFO,swLogPrintf("Sending SECURITY_MODE_COMPLETE "); +576512,1181075455,0,0,PS1,CEMM,EcnbTraceEmmMessageType_27,P_INFO,swLogPrintf("Sending SECURITY_MODE_REJECT "); +576512,1181077503,0,0,PS1,CEMM,EcnbTraceEmmMessageType_28,P_INFO,swLogPrintf("Sending EMM_STATUS "); +576512,1181079551,0,0,PS1,CEMM,EcnbTraceEmmMessageType_29,P_INFO,swLogPrintf("Receiving EMM_STATUS "); +576512,1181081599,0,0,PS1,CEMM,EcnbTraceEmmMessageType_30,P_INFO,swLogPrintf("Receiving EMM_INFORMATION "); +576512,1181083647,0,0,PS1,CEMM,EcnbTraceEmmMessageType_31,P_INFO,swLogPrintf("Receiving DOWNLINK_NAS_TRANSPORT "); +576512,1181085695,0,0,PS1,CEMM,EcnbTraceEmmMessageType_32,P_INFO,swLogPrintf("Sending UPLINK_NAS_TRANSPORT "); +576512,1181087743,0,0,PS1,CEMM,EcnbTraceEmmMessageType_33,P_INFO,swLogPrintf("Receiving DOWNLINK_GENERIC_NAS_TRANSPORT "); +576512,1181089791,0,0,PS1,CEMM,EcnbTraceEmmMessageType_34,P_INFO,swLogPrintf("Sending UPLINK_GENERIC_NAS_TRANSPORT "); +576512,1181091839,0,0,PS1,CEMM,EcnbTraceEmmMessageType_35,P_INFO,swLogPrintf("Sending SERVICE_REQUEST "); +576512,1181091840,0,0,PS1,CEMM,EcnbTraceEmmMessageType_36,P_INFO,swLogPrintf("Unknown message type %d! "); +576512,1181093888,0,0,PS1,CEMM,EcnbTraceEsmMessageType_32,P_VALUE,swLogPrintf("ESM_DATA_TRANSPORT ul data tempLen : %d "); +576512,1181097983,0,0,PS1,CEMM,EcnbTraceEsmMessageType_1,P_INFO,swLogPrintf("Receiving ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_REQUEST "); +576512,1181100031,0,0,PS1,CEMM,EcnbTraceEsmMessageType_2,P_INFO,swLogPrintf("Sending ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_ACCEPT "); +576512,1181102079,0,0,PS1,CEMM,EcnbTraceEsmMessageType_3,P_INFO,swLogPrintf("Sending ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_REJECT "); +576512,1181104127,0,0,PS1,CEMM,EcnbTraceEsmMessageType_4,P_INFO,swLogPrintf("Receiving ACTIVATE_DEDICATED_EPS_BEARER_CONTEXT_REQUEST "); +576512,1181106175,0,0,PS1,CEMM,EcnbTraceEsmMessageType_5,P_INFO,swLogPrintf("Sending ACTIVATE_DEDICATED_EPS_BEARER_CONTEXT_ACCEPT "); +576512,1181108223,0,0,PS1,CEMM,EcnbTraceEsmMessageType_6,P_INFO,swLogPrintf("Sending ACTIVATE_DEDICATED_EPS_BEARER_CONTEXT_REJECT "); +576512,1181110271,0,0,PS1,CEMM,EcnbTraceEsmMessageType_7,P_INFO,swLogPrintf("Receiving MODIFY_EPS_BEARER_CONTEXT_REQUEST "); +576512,1181112319,0,0,PS1,CEMM,EcnbTraceEsmMessageType_8,P_INFO,swLogPrintf("Sending MODIFY_EPS_BEARER_CONTEXT_ACCEPT "); +576512,1181114367,0,0,PS1,CEMM,EcnbTraceEsmMessageType_9,P_INFO,swLogPrintf("Sending MODIFY_EPS_BEARER_CONTEXT_REJECT "); +576512,1181116415,0,0,PS1,CEMM,EcnbTraceEsmMessageType_10,P_INFO,swLogPrintf("Receiving DEACTIVATE_EPS_BEARER_CONTEXT_REQUEST "); +576512,1181118463,0,0,PS1,CEMM,EcnbTraceEsmMessageType_11,P_INFO,swLogPrintf("Sending DEACTIVATE_EPS_BEARER_CONTEXT_ACCEPT "); +576512,1181120511,0,0,PS1,CEMM,EcnbTraceEsmMessageType_12,P_INFO,swLogPrintf("Sending PDN_CONNECTIVITY_REQUEST "); +576512,1181122559,0,0,PS1,CEMM,EcnbTraceEsmMessageType_13,P_INFO,swLogPrintf("Receiving PDN_CONNECTIVITY_REJECT "); +576512,1181124607,0,0,PS1,CEMM,EcnbTraceEsmMessageType_14,P_INFO,swLogPrintf("Sending PDN_DISCONNECT_REQUEST "); +576512,1181126655,0,0,PS1,CEMM,EcnbTraceEsmMessageType_15,P_INFO,swLogPrintf("Receiving PDN_DISCONNECT_REJECT "); +576512,1181128703,0,0,PS1,CEMM,EcnbTraceEsmMessageType_16,P_INFO,swLogPrintf("Sending BEARER_RESOURCE_ALLOCATION_REQUEST "); +576512,1181130751,0,0,PS1,CEMM,EcnbTraceEsmMessageType_17,P_INFO,swLogPrintf("Receiving BEARER_RESOURCE_ALLOCATION_REJECT "); +576512,1181132799,0,0,PS1,CEMM,EcnbTraceEsmMessageType_18,P_INFO,swLogPrintf("Sending BEARER_RESOURCE_MODIFICATION_REQUEST "); +576512,1181134847,0,0,PS1,CEMM,EcnbTraceEsmMessageType_19,P_INFO,swLogPrintf("Receiving BEARER_RESOURCE_MODIFICATION_REJECT "); +576512,1181136895,0,0,PS1,CEMM,EcnbTraceEsmMessageType_20,P_INFO,swLogPrintf("Receiving ESM_INFORMATION_REQUEST "); +576512,1181138943,0,0,PS1,CEMM,EcnbTraceEsmMessageType_21,P_INFO,swLogPrintf("Sending ESM_INFORMATION_RESPONSE "); +576512,1181140991,0,0,PS1,CEMM,EcnbTraceEsmMessageType_22,P_INFO,swLogPrintf("Receiving ESM_NOTIFICATION "); +576512,1181143039,0,0,PS1,CEMM,EcnbTraceEsmMessageType_23,P_INFO,swLogPrintf("Sending ESM_DUMMY_MESSAGE "); +576512,1181145087,0,0,PS1,CEMM,EcnbTraceEsmMessageType_24,P_INFO,swLogPrintf("Receiving ESM_DUMMY_MESSAGE "); +576512,1181147135,0,0,PS1,CEMM,EcnbTraceEsmMessageType_25,P_INFO,swLogPrintf("Sending ESM_STATUS "); +576512,1181149183,0,0,PS1,CEMM,EcnbTraceEsmMessageType_26,P_INFO,swLogPrintf("Receiving ESM_STATUS "); +576512,1181151231,0,0,PS1,CEMM,EcnbTraceEsmMessageType_27,P_INFO,swLogPrintf("Sending REMOTE_UE_REPORT "); +576512,1181153279,0,0,PS1,CEMM,EcnbTraceEsmMessageType_28,P_INFO,swLogPrintf("Receiving REMOTE_UE_REPORT_RESPONSE "); +576512,1181155327,0,0,PS1,CEMM,EcnbTraceEsmMessageType_29,P_INFO,swLogPrintf("Sending ESM_DATA_TRANSPORT "); +576512,1181157375,0,0,PS1,CEMM,EcnbTraceEsmMessageType_30,P_INFO,swLogPrintf("Receiving ESM_DATA_TRANSPORT "); +576512,1181157376,0,0,PS1,CEMM,EcnbTraceEsmMessageType_31,P_INFO,swLogPrintf("Unknown message type %d! "); +576512,1181159424,0,0,PS1,CEMM,CemmNasSecurityKey_1,P_VALUE,swLogPrintf("CemmNasSecurityKey : UL NAS COUNT is %d "); +576512,1181161472,0,0,PS1,CEMM,CemmNasSecurityKey_2,P_VALUE,swLogPrintf("CemmNasSecurityKey : UL NAS COUNT is %d "); +576512,1181163776,0,0,PS1,CEMM,CemmNasMacForReEst_1,P_VALUE,swLogPrintf("CemmNasMacForReEst : NAS-MAC is %d , UL NAS COUNT is %d "); +576512,1181167615,0,0,PS1,CEMM,CemmCpReestablishInfo_1,P_INFO,swLogPrintf("NAS security is not activated! "); +576512,1181169663,0,0,PS1,CEMM,CemmCpReestablishInfo_2,P_INFO,swLogPrintf("Uplink NAS count overflow! "); +576512,1181171711,0,0,PS1,CEMM,CemmSendCerrcConnReq_1,P_WARNING,swLogPrintf("gCemm.srInfo.srReason is wrong! "); +576512,1181173759,0,0,PS1,CEMM,CemmSendCerrcConnReq_2,P_WARNING,swLogPrintf("gCemm.srInfo.srReason is wrong! "); +576512,1181173760,0,0,PS1,CEMM,CemmSendCerrcConnReq_4,P_VALUE,swLogPrintf("Uplink Nas Count is %d "); +576512,1181175808,0,0,PS1,CEMM,CemmSendCerrcNasMsgReq_1,P_VALUE,swLogPrintf("Uplink Nas Count is %d "); +576512,1181179903,0,0,PS1,CEMM,CemmSendCerrcResumeReq_1,P_WARNING,swLogPrintf("gCemm.srInfo.srReason is wrong! "); +576512,1181181951,0,0,PS1,CEMM,EcnbTraceTcMessageType_1,P_SIG,swLogPrintf("Receiving CLOSE_UE_TEST_LOOP "); +576512,1181183999,0,0,PS1,CEMM,EcnbTraceTcMessageType_3,P_SIG,swLogPrintf("Sending CLOSE_UE_TEST_LOOP_COMPLETE "); +576512,1181186047,0,0,PS1,CEMM,EcnbTraceTcMessageType_5,P_SIG,swLogPrintf("Receiving OPEN_UE_TEST_LOOP "); +576512,1181188095,0,0,PS1,CEMM,EcnbTraceTcMessageType_7,P_SIG,swLogPrintf("Sending OPEN_UE_TEST_LOOP_COMPLETE "); +576512,1181190143,0,0,PS1,CEMM,EcnbTraceTcMessageType_9,P_SIG,swLogPrintf("Receiving ACTIVATE_TEST_MODE "); +576512,1181192191,0,0,PS1,CEMM,EcnbTraceTcMessageType_11,P_SIG,swLogPrintf("Sending ACTIVATE_TEST_MODE_COMPLETE "); +576512,1181194239,0,0,PS1,CEMM,EcnbTraceTcMessageType_13,P_SIG,swLogPrintf("Receiving DEACTIVATE_TEST_MODE "); +576512,1181196287,0,0,PS1,CEMM,EcnbTraceTcMessageType_15,P_SIG,swLogPrintf("Sending DEACTIVATE_TEST_MODE_COMPLETE "); +576512,1181198335,0,0,PS1,CEMM,EcnbTraceTcMessageType_17,P_SIG,swLogPrintf("Receiving RESET_UE_POSITIONING_STORED_INFORMATION "); +576512,1181198336,0,0,PS1,CEMM,EcnbTraceTcMessageType_19,P_SIG,swLogPrintf("Unknown message type %d! "); +576512,1181202431,0,0,PS1,CEMM,CemmSendCerrcMessage_1,P_WARNING,swLogPrintf("Already sent out a SIG_CERRC_CONN_REQ , should not send another one! "); +576512,1181202944,0,0,PS1,CEMM,CemmCellCampCnf_1,P_VALUE,swLogPrintf("CemmCellCampCnf : Plmn is ( 0x%x , 0x%x ) , TAC is 0x%x "); +576512,1181204480,0,0,PS1,CEMM,CemmCellCampCnf_2,P_VALUE,swLogPrintf("CemmCellCampCnf : actStatus is %d "); +576512,1181208575,0,0,PS1,CEMM,CemmCellCampCnf_3,P_INFO,swLogPrintf("when moving to a non EPLMN and configure attachWithIMSI , shall need perform attach. "); +576512,1181210623,0,0,PS1,CEMM,CemmCellCampCnf_4,P_INFO,swLogPrintf("Keep ESM DATA TRANSPORT msg , waiting PLMN search result. "); +576512,1181210624,0,0,PS1,CEMM,CemmCellCampCnf_5,P_INFO,swLogPrintf("gCemm.flags.cellStatus is %d. "); +576512,1181214719,0,0,PS1,CEMM,CemmCellCampCnf_6,P_WARNING,swLogPrintf("Discard this ESM Data! "); +576512,1181216767,0,0,PS1,CEMM,CemmPagingRequest_1,P_WARNING,swLogPrintf("During enter PSM procedure , ignore paging. "); +576512,1181216768,0,0,PS1,CEMM,CemmPagingRequest_2,P_VALUE,swLogPrintf("Ignore S-TMSI paging under emmState %d "); +576512,1181218816,0,0,PS1,CEMM,CemmPagingRequest_3,P_VALUE,swLogPrintf("Ignore IMSI paging under emmState %d "); +576512,1181222911,0,0,PS1,CEMM,CemmReTransmitMessage_1,P_INFO,swLogPrintf("There is already a new msg before process the retrans msg , process the new msg firstly "); +576512,1181223680,0,0,PS1,CEMM,CemmReTransmitMessage_2,P_VALUE,swLogPrintf("Current re-transmit msg ( msg index is %d in cache queue ( %d ) , msg type is %d ) already define Emm proceduce ( %d ) , pause process others reTransMsgType "); +576512,1181225728,0,0,PS1,CEMM,CemmReTransmitMessage_3,P_VALUE,swLogPrintf("Current re-transmit msg ( msg index is %d in cache queue ( %d ) , msg type is %d ) is pause by Emm proceduce ( %d ) , re-transmit it later! "); +576512,1181229055,0,0,PS1,CEMM,CemmCellCampInd_1,P_WARNING,swLogPrintf("CemmCellCampInd : unexpected SIG_CERRC_ACT_IND during SIG_CERRC_ACT_REQ procedure! "); +576512,1181229568,0,0,PS1,CEMM,CemmCellCampInd_2,P_VALUE,swLogPrintf("CemmCellCampInd : Plmn is ( 0x%x , 0x%x ) ; TAC is 0x%x "); +576512,1181231104,0,0,PS1,CEMM,CemmCellCampInd_3,P_VALUE,swLogPrintf("CemmCellCampInd : actStatus is %d "); +576512,1181235199,0,0,PS1,CEMM,CemmCellCampInd_4,P_INFO,swLogPrintf("As Cell cellIdentity has changed , stop T3411. "); +576512,1181237247,0,0,PS1,CEMM,CemmCellCampInd_5,P_INFO,swLogPrintf("Check any retransmit message "); +576512,1181239295,0,0,PS1,CEMM,CemmCellCampInd_6,P_INFO,swLogPrintf("need retransmit message "); +576512,1181241343,0,0,PS1,CEMM,CemmCellCampInd_7,P_INFO,swLogPrintf("Initiate TAU "); +576512,1181243391,0,0,PS1,CEMM,CemmCellCampInd_8,P_INFO,swLogPrintf("Keep ESM DATA TRANSPORT msg , waiting PLMN search result. "); +576512,1181243392,0,0,PS1,CEMM,CemmCellCampInd_9,P_INFO,swLogPrintf("gCemm.flags.cellStatus is %d. "); +576512,1181245440,0,0,PS1,CEMM,CemmConnCnf_1,P_VALUE,swLogPrintf("establishStatus is %d "); +576512,1181247488,0,0,PS1,CEMM,CemmConnCnf_2,P_VALUE,swLogPrintf("CESTABLISH_FAIL_T300_EXPIRY , sigRetransmitCounter is %d "); +576512,1181251583,0,0,PS1,CEMM,CemmConnCnf_3,P_INFO,swLogPrintf("ESM data still valid , could retry SR "); +576512,1181251840,0,0,PS1,CEMM,CemmConnRelInd_1,P_VALUE,swLogPrintf("release cause is %d , bNwRel is %d "); +576512,1181255679,0,0,PS1,CEMM,CemmConnRelInd_2,P_WARNING,swLogPrintf("Expected to receive SIG_CERRC_CONN_NAS_UL_MSG_RESUME_IND before release! "); +576512,1181257727,0,0,PS1,CEMM,CemmConnRelInd_3,P_INFO,swLogPrintf("UE is using CP optimization only , and has DL data expected , need initiate TAU to recover connection "); +576512,1181259775,0,0,PS1,CEMM,CemmConnRelInd_4,P_INFO,swLogPrintf("UE is using CP optimization only , but has no DL data expected , don ' t trigger TAU "); +576512,1181261823,0,0,PS1,CEMM,CemmConnRelInd_5,P_INFO,swLogPrintf("Will retry SR later "); +576512,1181263871,0,0,PS1,CEMM,CemmConnRelInd_6,P_INFO,swLogPrintf("Treat the release of RRCconnection as SR succeed. "); +576512,1181263873,0,0,PS1,CEMM,CemmConnRelInd_7,P_INFO,swLogPrintf("Received SIG_CERRC_RELEASE_IND under EMM state %s "); +576512,1181267967,0,0,PS1,CEMM,CemmConnRelCnf_1,P_WARNING,swLogPrintf("Expected to receive SIG_CERRC_CONN_NAS_UL_MSG_RESUME_IND before release! "); +576512,1181270015,0,0,PS1,CEMM,CemmTransmissionFailure_1,P_INFO,swLogPrintf("During power off detach , ignore transmit failure indication! "); +576512,1181270528,0,0,PS1,CEMM,CemmTransmissionFailure_2,P_VALUE,swLogPrintf("failMsgIndex is 0x%x ; msgIndexOfSignaling is %d ; EmmMessageType is 0x%x "); +576512,1181272576,0,0,PS1,CEMM,CemmTransmissionFailure_3,P_VALUE,swLogPrintf("failMsgIndex is 0x%x ; msgIndexOfData is %d ; EmmMessageType is 0x%x "); +576512,1181276159,0,0,PS1,CEMM,CemmTransmissionFailure_4,P_WARNING,swLogPrintf("More than MAX_NUM_OF_TRANS_FAILURE_MESSAGE message transmit failed!! "); +576512,1181278207,0,0,PS1,CEMM,CemmTransmissionFailure_5,P_DEBUG,swLogPrintf("Discard the TaiList received in attach accept! "); +576512,1181280255,0,0,PS1,CEMM,CemmTransmissionFailure_6,P_WARNING,swLogPrintf("PendingUlEsmMsg is not empty , free it! "); +576512,1181280512,0,0,PS1,CEMM,CemmTransmissionFailure_7,P_VALUE,swLogPrintf("failMsgIndex ( 0x%x ) is still in cache queue ( %d ) and not out of date , retransmitted later! "); +576512,1181282560,0,0,PS1,CEMM,CemmTransmissionFailure_8,P_VALUE,swLogPrintf("failMsgIndex ( 0x%x ) is still in cache queue ( %d ) but out of data , discard it! "); +576512,1181284352,0,0,PS1,CEMM,CemmTransmissionFailure_9,P_VALUE,swLogPrintf("failMsgIndex ( 0x%x ) is not in cache queue , no longer retransmit! "); +576512,1181286912,0,0,PS1,CEMM,CemmTransmissionSucc_1,P_VALUE,swLogPrintf("SuccMsgIndex is 0x%x ; msgIndexOfSignaling is %d EmmMessageType is 0x%x "); +576512,1181288960,0,0,PS1,CEMM,CemmTransmissionSucc_2,P_VALUE,swLogPrintf("SuccMsgIndex is 0x%x ; msgIndexOfData is %d ; EmmMessageType is 0x%x "); +576512,1181292543,0,0,PS1,CEMM,CemmTransmissionSucc_3,P_INFO,swLogPrintf("TAU COMPLETE transmission succeed , T3440 is running. "); +576512,1181292544,0,0,PS1,CEMM,CemmResumeCnf_1,P_VALUE,swLogPrintf("Unexpeted resumeMsgType : 0x%x "); +576512,1181296639,0,0,PS1,CEMM,CemmResumeCnf_2,P_SIG,swLogPrintf("EmmStartTimer : timerId is T3412 "); +576512,1181296896,0,0,PS1,CEMM,NasMessageSecurityCheck_1,P_VALUE,swLogPrintf("Received mac is 0x%lx ; xmac is 0x%lx "); +576512,1181298688,0,0,PS1,CEMM,NasMessageSecurityCheck_2,P_VALUE,swLogPrintf("Sequence Number is %d "); +576512,1181300736,0,0,PS1,CEMM,NasMessageSecurityCheck_3,P_VALUE,swLogPrintf("Integrity Algorithm is %d "); +576512,1181303040,0,0,PS1,CEMM,NasMessageSecurityCheck_4,P_VALUE,swLogPrintf("The correct DL NAS OVERFLOW COUNT is 0x%x , current tryIndex is %d "); +576512,1181305088,0,0,PS1,CEMM,NasMessageSecurityCheck_5,P_VALUE,swLogPrintf("The correct DL NAS OVERFLOW COUNT is 0x%x , current tryIndex is %d "); +576512,1181307136,0,0,PS1,CEMM,NasMessageSecurityCheck_6,P_VALUE,swLogPrintf("MAC mismatch.Received mac is 0x%lx ; xmac is 0x%lx "); +576512,1181308928,0,0,PS1,CEMM,NasMessageSecurityCheck_7,P_VALUE,swLogPrintf("dataLength is : %d "); +576512,1181310976,0,0,PS1,CEMM,ProcessMessageError_1,P_INFO,swLogPrintf("Message decode error!Error code is %d "); +576512,1181313024,0,0,PS1,CEMM,CemmIsNeedIngoreDlEmmMsg_1,P_VALUE,swLogPrintf("Emm rcv repeated dl msg ( msg type is %d ) , but corresponding ul msg is still transmitting , discard it! "); +576512,1181315072,0,0,PS1,CEMM,CemmIsNeedIngoreDlEmmMsg_2,P_VALUE,swLogPrintf("Emm rcv repeated dl msg ( msg type is %d ) , and corresponding ul msg is transmitted succ , continue to process it! "); +576512,1181317120,0,0,PS1,CEMM,CemmIsNeedIngoreDlEmmMsg_3,P_VALUE,swLogPrintf("Emm rcv repeated dlmsg type ( msg type is %d ) , but msg content is differnet , continue to process it! "); +576512,1181321215,0,0,PS1,CEMM,ProcessDownlinkEmmMessage_1,P_INFO,swLogPrintf("Discard ATTACH REJECT cause #25 without integrity protected! "); +576512,1181323263,0,0,PS1,CEMM,ProcessDownlinkEmmMessage_2,P_INFO,swLogPrintf("Discard TA UPDATE REJECT cause #25 without integrity protected! "); +576512,1181325311,0,0,PS1,CEMM,ProcessDownlinkEmmMessage_3,P_INFO,swLogPrintf("Discard SERVICE REJECT cause #25 without integrity protected! "); +576512,1181327359,0,0,PS1,CEMM,ProcessDownlinkEmmMessage_4,P_INFO,swLogPrintf("Rceive EMM STATUS! "); +576512,1181327360,0,0,PS1,CEMM,CemmNasMsgInd_Warning,P_WARNING,swLogPrintf("Emm ConnState is %d , not connected , ignore this msg "); +576512,1181329408,0,0,PS1,CEMM,CemmNasMsgInd_w,P_WARNING,swLogPrintf("Recived security protected NAS message with unexpected length %d , discard it! "); +576512,1181333503,0,0,PS1,CEMM,CemmNasMsgInd_1,P_INFO,swLogPrintf("Ignore security mode command during power off "); +576512,1181335551,0,0,PS1,CEMM,CemmNasMsgInd_2,P_INFO,swLogPrintf("Security Mode Command integrity checking failed! "); +576512,1181335552,0,0,PS1,CEMM,CemmNasMsgInd_3,P_VALUE,swLogPrintf("Unexpected message , PD is 0x%x! "); +576512,1181339647,0,0,PS1,CEMM,CemmNasMsgInd_4,P_INFO,swLogPrintf("Integrity checking of NAS message fail! "); +576512,1181341695,0,0,PS1,CEMM,CemmNasMsgInd_6,P_INFO,swLogPrintf("Destroy any allocated memory in abnormal case! "); +576512,1181341696,0,0,PS1,CEMM,CemmNasMsgInd_8,P_VALUE,swLogPrintf("Downlink Nas Count is %d "); +576512,1181345791,0,0,PS1,CEMM,EmmAsDeactCnf_1,P_SIG,swLogPrintf("Enter Psm Mode Succeed! "); +576512,1181346048,0,0,PS1,CEMM,CemmSendEsmFeatureSupportInd_1,P_VALUE,swLogPrintf("CemmSendEsmFeatureSupportInd : uePreferOpt in nvm is %d , but the select uePreferOpt is %d "); +576512,1181349887,0,0,PS1,CEMM,CemmEsmMsgContainerRspMsg_1,P_WARNING,swLogPrintf("Receive unexpected ESM Message container , argvPtr is 0x X% "); +576512,1181351935,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_1,P_INFO,swLogPrintf("Waiting cell camp indication , pending ESM establish request! "); +576512,1181353983,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_2,P_INFO,swLogPrintf("Already pended another request! "); +576512,1181356031,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_3,P_INFO,swLogPrintf("T3346 is running! "); +576512,1181358079,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_4,P_VALUE,swLogPrintf("Already in Service Request procedure , will reply later "); +576512,1181360127,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_5,P_INFO,swLogPrintf("ESM request is received under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No_Service! "); +576512,1181362175,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_6,P_INFO,swLogPrintf("Waiting for RRC Act Cnf , Pending the ESM Establish req "); +576512,1181364223,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_7,P_INFO,swLogPrintf("ESM request is received under EMM_REGISTERED_NO_CELL_AVAILABLE! "); +576512,1181364225,0,0,PS1,CEMM,CemmEsmEstablishReqMsg_8,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181366273,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_1,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181370367,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_2,P_WARNING,swLogPrintf("PendingUlEsmMsg is not empty ignore the new CemmEsmUnitDataRequestMsg! "); +576512,1181370368,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_3,P_VALUE,swLogPrintf("Unexpected ESM message 0x%x! "); +576512,1181374463,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_4,P_INFO,swLogPrintf("Waiting cell camp indication , pending ESM unitData request! "); +576512,1181376511,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_5,P_INFO,swLogPrintf("Already pended another request! "); +576512,1181378559,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_6,P_INFO,swLogPrintf("Receiving CemmEsmUnitDataReq but now is not allow to init cpsr "); +576512,1181380607,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_8,P_INFO,swLogPrintf("During Attach / Tau Complete transmission , pending it. "); +576512,1181380608,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_9,P_VALUE,swLogPrintf("Wrong msgType : %d "); +576512,1181382656,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_10,P_VALUE,swLogPrintf("Can ' t process CemmEsmUnitDataReq while under emmConnState : %d "); +576512,1181384704,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_11,P_VALUE,swLogPrintf("Wrong msgType : %d "); +576512,1181388799,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_12,P_INFO,swLogPrintf("No PS signalling exists ignore ESM request! "); +576512,1181390847,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_13,P_INFO,swLogPrintf("Not exceptional event ignore ESM request! "); +576512,1181392895,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_14,P_INFO,swLogPrintf("ESM request is received under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No_Service! "); +576512,1181394943,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_15,P_INFO,swLogPrintf("Waiting for RRC Act Cnf , Pending the ESM Data req "); +576512,1181396991,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_16,P_INFO,swLogPrintf("ESM request is received under EMM_REGISTERED_NO_CELL_AVAILABLE! "); +576512,1181399039,0,0,PS1,CEMM,CemmEsmUnitDataRequestMsg_17,P_INFO,swLogPrintf("Already in Service Request procedure , will reply later "); +576512,1181401087,0,0,PS1,CEMM,CemmEsmLocalDetachReAttachIndMsg_1,P_INFO,swLogPrintf("Indication from ESM to perform local detach and re-attach! "); +576512,1181401088,0,0,PS1,CEMM,CemmIsAllowEsmSendExceptionDataInSuspendState_1,P_VALUE,swLogPrintf("bRslt is %d "); +576512,1181403137,0,0,PS1,CEMM,CemmIsAllowSendNormalPriSignallingInSuspendState_1,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181407231,0,0,PS1,CEMM,CemmPlmnSelectRequest_1,P_INFO,swLogPrintf("Sending CemmPlmnSelectRequest while Ue is not in idle state "); +576512,1181409279,0,0,PS1,CEMM,CemmProcPlmnSelectCnfMsg_1,P_INFO,swLogPrintf("Already registered on this PLMN! "); +576512,1181411327,0,0,PS1,CEMM,CemmProcPlmnSelectCnfMsg_2,P_INFO,swLogPrintf("Currently trying to register on this PLMN! "); +576512,1181413375,0,0,PS1,CEMM,CemmProcPlmnSelectCnfMsg_3,P_INFO,swLogPrintf("Already sent out SIG_CERRC_ACT_REQ , just wait SIG_CERRC_ACT_CNF. "); +576512,1181415423,0,0,PS1,CEMM,CemmProcPlmnSelectCnfMsg_4,P_INFO,swLogPrintf("Currently trying to register on this PLMN! "); +576512,1181417471,0,0,PS1,CEMM,CemmProcPlmnSelectCnfMsg_5,P_INFO,swLogPrintf("Can ' t perform registration while in connected state! "); +576512,1181419519,0,0,PS1,CEMM,CemmProcPlmnSelectInd_1,P_INFO,swLogPrintf("Already registered on this PLMN! "); +576512,1181421567,0,0,PS1,CEMM,CemmProcPlmnSelectInd_2,P_INFO,swLogPrintf("Can ' t perform registration while in connected state! "); +576512,1181423615,0,0,PS1,CEMM,CemmProcNoPlmnSelectIndMsg_1,P_INFO,swLogPrintf("Before rcv plmn srch cnf , Detach Req has already sent , Ue should still kept in EMM_DEREGISTERED_INITIATED "); +576512,1181425663,0,0,PS1,CEMM,CemmProcNoPlmnSelectIndMsg_2,P_INFO,swLogPrintf("Receiving emergency camp request while in connected state , buffer it. "); +576512,1181427711,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_1,P_INFO,swLogPrintf("EMM specific procedure is ongoing.Waiting UE to complete specific procedure "); +576512,1181429759,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_2,P_INFO,swLogPrintf("No EMM specific procedure ongoing.Waiting UE go idle "); +576512,1181431807,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_3,P_INFO,swLogPrintf("EMM specific procedure ongoing.Abort current procedure "); +576512,1181433855,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_4,P_INFO,swLogPrintf("No EMM specific procedure ongoing.Release RRC connection "); +576512,1181435903,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_5,P_INFO,swLogPrintf("EMM specific procedure is ongoing.Waiting UE to complete specific procedure "); +576512,1181437951,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_6,P_INFO,swLogPrintf("No EMM specific procedure ongoing. Release RRC connection "); +576512,1181439999,0,0,PS1,CEMM,CemmProcIdleStateReqMsg_7,P_INFO,swLogPrintf("Unexpected CemmPlmnIdleReqCause! "); +576512,1181440000,0,0,PS1,CEMM,ULNasCounterRollback_1,P_VALUE,swLogPrintf("Uplink Nas Count is %d "); +576512,1181442304,0,0,PS1,CEMM,ULNasCounterRollback_2,P_VALUE,swLogPrintf("Uplink Nas Count overflow is %d , %d "); +576512,1181446143,0,0,PS1,CEMM,ULNasCounterUpdate_1,P_WARNING,swLogPrintf("NAS UL COUNT wrap around , delete eKsi , Re-attach "); +576512,1181448191,0,0,PS1,CEMM,DLNasCounterUpdate_1,P_WARNING,swLogPrintf("NAS DL COUNT wrap around , delete eKsi , Re-attach "); +576512,1181448192,0,0,PS1,CEMM,PrintNasConfig_1,P_INFO,swLogPrintf("NAS signalling priority value is %d : NAS signalling low priority "); +576512,1181450240,0,0,PS1,CEMM,PrintNasConfig_2,P_INFO,swLogPrintf("NAS signalling priority value is %d : Reserved "); +576512,1181452288,0,0,PS1,CEMM,PrintNasConfig_3,P_INFO,swLogPrintf("Minimum Periodic Search Timer value is %d minutes "); +576512,1181456383,0,0,PS1,CEMM,PrintNasConfig_4,P_INFO,swLogPrintf("Extended access barring value indicates that the extended access barring is applied for the UE "); +576512,1181458431,0,0,PS1,CEMM,PrintNasConfig_5,P_INFO,swLogPrintf("Extended access barring value indicates that the extended access barring is not applied for the UE "); +576512,1181460479,0,0,PS1,CEMM,PrintNasConfig_6,P_INFO,swLogPrintf("Timer T3245 Behaviour value indicates that the timer T3245 is used "); +576512,1181462527,0,0,PS1,CEMM,PrintNasConfig_7,P_INFO,swLogPrintf("Timer T3245 Behaviour value indicates that the timer T3245 is not used "); +576512,1181464575,0,0,PS1,CEMM,PrintNasConfig_8,P_INFO,swLogPrintf("Override NAS signalling low priority value indicates that the UE can override the NAS signalling low priority indicator "); +576512,1181466623,0,0,PS1,CEMM,PrintNasConfig_9,P_INFO,swLogPrintf("Override NAS signalling low priority value indicates that the UE cannot override the NAS signalling low priority indicator "); +576512,1181468671,0,0,PS1,CEMM,PrintNasConfig_10,P_INFO,swLogPrintf("Override Extended access barring value indicates that the UE can override extended access barring "); +576512,1181470719,0,0,PS1,CEMM,PrintNasConfig_11,P_INFO,swLogPrintf("Override Extended access barring value indicates that the UE cannot override extended access barring "); +576512,1181472767,0,0,PS1,CEMM,PrintNasConfig_12,P_INFO,swLogPrintf("Fast First Higher Priority PLMN value indicates that the Fast First Higher Priority PLMN Search is enabled "); +576512,1181474815,0,0,PS1,CEMM,PrintNasConfig_13,P_INFO,swLogPrintf("Fast First Higher Priority PLMN value indicates that the Fast First Higher Priority PLMN Search is disabled "); +576512,1181474816,0,0,PS1,CEMM,PrintNasConfig_14,P_INFO,swLogPrintf("SM_RetryWaitTime value is %d minutes "); +576512,1181476864,0,0,PS1,CEMM,PrintNasConfig_15,P_INFO,swLogPrintf("Default_DCN_ID value is %d "); +576512,1181480959,0,0,PS1,CEMM,PrintNasConfig_16,P_INFO,swLogPrintf("Exception Data Reporting Allowed value indicates that the UE is allowed to use the RRC establishment cause mo-ExceptionData "); +576512,1181483007,0,0,PS1,CEMM,PrintNasConfig_17,P_INFO,swLogPrintf("Exception Data Reporting Allowed value indicates that the UE is not allowed to use the RRC establishment cause mo-ExceptionData "); +576512,1181485055,0,0,PS1,CEMM,PrintNasConfig_18,P_INFO,swLogPrintf("AttachWithIMSI value indicates that attach with IMSI is performed when moving to a non-equivalent PLMN "); +576512,1181487103,0,0,PS1,CEMM,PrintNasConfig_19,P_INFO,swLogPrintf("AttachWithIMSI value indicates that normal behaviour is applied "); +576512,1181489151,0,0,PS1,CEMM,CemmSimReady_1,P_INFO,swLogPrintf("Last visited registered TAI is invalid in EFepsloci. "); +576512,1181489664,0,0,PS1,CEMM,CemmSimReady_3,P_VALUE,swLogPrintf("EFepsloci Last visited registered TAI is : Plmn ( 0x%x , 0x%x ) , TAC 0x%x "); +576512,1181491200,0,0,PS1,CEMM,CemmSimReady_4,P_VALUE,swLogPrintf("EFepsloci EPS update status is : %d "); +576512,1181495295,0,0,PS1,CEMM,CemmSimReady_5,P_INFO,swLogPrintf("LAI is invalid in EFloci. "); +576512,1181497343,0,0,PS1,CEMM,CemmSimReady_6,P_INFO,swLogPrintf("USIM EFepsloci invalid.Use NVM value "); +576512,1181499391,0,0,PS1,CEMM,CemmSimReady_7,P_INFO,swLogPrintf("USIM EFepsnsc invalid.Use NVM value "); +576512,1181499392,0,0,PS1,CEMM,CemmSimReady_8,P_WARNING,swLogPrintf("eKSI or integrity algorithm is wrong stored in NVM!eKSI is %d "); +576512,1181503487,0,0,PS1,CEMM,CemmSimReady_9,P_VALUE,swLogPrintf("USIM EFepsloci invalid.NVM IMSI mismatch with USIM IMSI.Set to default value "); +576512,1181505535,0,0,PS1,CEMM,CemmSimReady_10,P_VALUE,swLogPrintf("USIM EFepsnsc invalid.NVM IMSI mismatch with USIM IMSI.Set to default value "); +576512,1181507583,0,0,PS1,CEMM,CemmSimReady_11,P_VALUE,swLogPrintf("USIM EFloci is invalid , set to default value "); +576512,1181509631,0,0,PS1,CEMM,CemmSimReady_12,P_WARNING,swLogPrintf("UE is set to power on attach without Integrity Protected , delete key "); +576512,1181511679,0,0,PS1,CEMM,CemmSimReady_13,P_WARNING,swLogPrintf("UE is set to power on attach with IMSI , delete GUTI and last register TAI / LAI "); +576512,1181513727,0,0,PS1,CEMM,CemmSimWriteData_1,P_WARNING,swLogPrintf("EFepsloci is not present , can ' t write to SIM , store into NVM! "); +576512,1181515775,0,0,PS1,CEMM,CemmSimWriteData_2,P_WARNING,swLogPrintf("pending updateEpslociToNvm! "); +576512,1181517823,0,0,PS1,CEMM,CemmSimWriteData_3,P_WARNING,swLogPrintf("updateEpslociToNvm! "); +576512,1181519871,0,0,PS1,CEMM,CemmSimWriteData_4,P_WARNING,swLogPrintf("EFepsnsc is not present , can ' t write to SIM , store into NVM! "); +576512,1181521919,0,0,PS1,CEMM,CemmSimWriteData_5,P_WARNING,swLogPrintf("pending updateEpsnscToNvm! "); +576512,1181523967,0,0,PS1,CEMM,CemmSimWriteData_6,P_WARNING,swLogPrintf("updateEpsnscToNvm! "); +576512,1181526015,0,0,PS1,CEMM,CemmSimWriteData_7,P_WARNING,swLogPrintf("EFloci is not present , can ' t write to SIM! "); +576512,1181528063,0,0,PS1,CEMM,CemmSimWriteData_8,P_WARNING,swLogPrintf("No USIM file to update! "); +576512,1181528832,0,0,PS1,CEMM,CemmSimWriteData_9,P_WARNING,swLogPrintf("Can ' t write USIM file! SimPresent is %d , WriteSimFlag is %d , SimRefresh is %d , SimRemove is %d "); +576512,1181532159,0,0,PS1,CEMM,CemmSimWriteCnf_1,P_INFO,swLogPrintf("Writing USIM file failed! "); +576512,1181534207,0,0,PS1,CEMM,CemmSimWriteCnf_111,P_WARNING,swLogPrintf("pending updateEpslociToNvm! "); +576512,1181536255,0,0,PS1,CEMM,CemmSimWriteCnf_112,P_WARNING,swLogPrintf("updateEpslociToNvm! "); +576512,1181538303,0,0,PS1,CEMM,CemmSimWriteCnf_113,P_WARNING,swLogPrintf("pending updateEpsnscToNvm! "); +576512,1181540351,0,0,PS1,CEMM,CemmSimWriteCnf_114,P_WARNING,swLogPrintf("updateEpsnscToNvm! "); +576512,1181542399,0,0,PS1,CEMM,NetworkFailingAuthentication_1,P_INFO,swLogPrintf("UE deems that the network has failed the authentication check! "); +576512,1181544447,0,0,PS1,CEMM,CemmSimAuthenticationCnf_1,P_WARNING,swLogPrintf("The RAND value from SIM is different with the current one , ignore this SIM authentication result! "); +576512,1181544448,0,0,PS1,CEMM,CemmSimUsatImeiSvReq_1,P_VALUE,swLogPrintf("Error idType ( %d ) "); +576512,1181548543,0,0,PS1,CEMM,CemmSmsEstRequest_1,P_WARNING,swLogPrintf("Received a new CemmSmsEstRequest , discard the PendingSmsMsg! "); +576512,1181550591,0,0,PS1,CEMM,CemmSmsEstRequest_2,P_WARNING,swLogPrintf("Reached max connection number! "); +576512,1181552639,0,0,PS1,CEMM,CemmSmsEstRequest_3,P_INFO,swLogPrintf("Waiting cell camp indication , pending SMS establish request! "); +576512,1181554687,0,0,PS1,CEMM,CemmSmsEstRequest_4,P_INFO,swLogPrintf("Already pended another request! "); +576512,1181556735,0,0,PS1,CEMM,CemmSmsEstRequest_5,P_INFO,swLogPrintf("T3346 is running! "); +576512,1181556736,0,0,PS1,CEMM,CemmSmsEstRequest_6,P_WARNING,swLogPrintf("Current cell camp status is %d , can ' t process SS establish req "); +576512,1181560831,0,0,PS1,CEMM,CemmSmsEstRequest_7,P_WARNING,swLogPrintf("Waiting for RRC Act Cnf , Pending the SMS establish req "); +576512,1181562879,0,0,PS1,CEMM,CemmSmsEstRequest_8,P_INFO,swLogPrintf("Can ' t process SMS establish req under EMM_REGISTERED_NO_CELL_AVAILABLE "); +576512,1181562881,0,0,PS1,CEMM,CemmSmsEstRequest_9,P_INFO,swLogPrintf("Can ' t process SMS establish req under emmState %s "); +576512,1181566975,0,0,PS1,CEMM,CemmSmsEstRequest_10,P_WARNING,swLogPrintf("Not registered for SMS only! "); +576512,1181567744,0,0,PS1,CEMM,CemmSmsRelRequest_1,P_VALUE,swLogPrintf("Sms release , index %d , connUsed %d , tiValue %d , tiFlag %d "); +576512,1181571071,0,0,PS1,CEMM,CemmSmsUnitDataRequest_1,P_WARNING,swLogPrintf("PendingSmsMsg is not empty! "); +576512,1181573119,0,0,PS1,CEMM,CemmSsEstRequest_1,P_INFO,swLogPrintf("Waiting cell camp indication , pending SS establish request! "); +576512,1181575167,0,0,PS1,CEMM,CemmSsEstRequest_2,P_INFO,swLogPrintf("Already pended another request! "); +576512,1181577215,0,0,PS1,CEMM,CemmSsEstRequest_3,P_INFO,swLogPrintf("Currently no allowed initiate SERVICE REQUEST! "); +576512,1181577216,0,0,PS1,CEMM,CemmSsEstRequest_4,P_WARNING,swLogPrintf("Current cell camp status is %d , can ' t process SS establish req "); +576512,1181581311,0,0,PS1,CEMM,CemmSsEstRequest_5,P_WARNING,swLogPrintf("Waiting for RRC Act Cnf , Pending the SS establish req "); +576512,1181583359,0,0,PS1,CEMM,CemmSsEstRequest_6,P_INFO,swLogPrintf("Can ' t process SS establish req under EMM_REGISTERED_NO_CELL_AVAILABLE "); +576512,1181583361,0,0,PS1,CEMM,CemmSsEstRequest_7,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181587455,0,0,PS1,CEMM,CemmSsUnitDataRequest_1,P_WARNING,swLogPrintf("Pending SS message is not empty! "); +576512,1181587457,0,0,PS1,CEMM,EmmStartTimer_1,P_INFO,swLogPrintf("EMM timer %s start "); +576512,1181589505,0,0,PS1,CEMM,EmmStartHibTimer_1,P_INFO,swLogPrintf("EMM Hibernate timer %s start "); +576512,1181591552,0,0,PS1,CEMM,EmmStartHibTimer_2,P_INFO,swLogPrintf("Timer period is %d MS "); +576512,1181593601,0,0,PS1,CEMM,EmmT3245Expiry_1,P_INFO,swLogPrintf("EmmT3245Expiry : emmState.now is %s "); +576512,1181595649,0,0,PS1,CEMM,EmmT3247Expiry_1,P_INFO,swLogPrintf("EmmT3247Expiry : emmState.now is %s "); +576512,1181598208,0,0,PS1,CEMM,EmmT3324Expiry_1,P_VALUE,swLogPrintf("EmmT3324Expiry : emmConnState is %d , emmState is %d , pendingRequest is %d "); +576512,1181601791,0,0,PS1,CEMM,EmmT3324Expiry_2,P_WARNING,swLogPrintf("EmmT3324Expiry : Already during enter PSM procedure. "); +576512,1181603839,0,0,PS1,CEMM,EmmT3324Expiry_3,P_INFO,swLogPrintf("Due to allow enter hib while t3346 or sigRetransmitTimer is running , so still allow to enter psm! "); +576512,1181605887,0,0,PS1,CEMM,EmmT3324Expiry_4,P_WARNING,swLogPrintf("Has pending ESM data , can ' t enter psm! "); +576512,1181605888,0,0,PS1,CEMM,EmmT3324Expiry_5,P_WARNING,swLogPrintf("Had reTransMsg ( msg type is %d ) , can ' t enter psm! "); +576512,1181609983,0,0,PS1,CEMM,EmmT3324Expiry_6,P_INFO,swLogPrintf("ESM data is out of date! "); +576512,1181612031,0,0,PS1,CEMM,EmmT3346Expiry_1,P_INFO,swLogPrintf("No pending data , maybe enter hib before , no need to retransmit! "); +576512,1181614079,0,0,PS1,CEMM,EmmT3346Expiry_2,P_INFO,swLogPrintf("T3346 expire under EMM_REGISTERED_NO_CELL_AVAILABLE , cell service status is No_Service! "); +576512,1181614081,0,0,PS1,CEMM,EmmT3412Expiry_1,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181618175,0,0,PS1,CEMM,EmmT3412Expiry_2,P_SIG,swLogPrintf("Continue to Start T3412 "); +576512,1181618176,0,0,PS1,CEMM,EmmT3440Expiry_other_1,P_WARNING,swLogPrintf("T3440 expiry , but current emmState is %d "); +576512,1181620225,0,0,PS1,CEMM,EmmT3448Expiry_1,P_INFO,swLogPrintf("Current emmState is %s "); +576512,1181624319,0,0,PS1,CEMM,EmmT3448Expiry_2,P_INFO,swLogPrintf("No pending data , maybe enter hib before , no need to retransmit! "); +576512,1181626367,0,0,PS1,CEMM,EmmT3448Expiry_3,P_INFO,swLogPrintf("ESM request is received under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No_Service! "); +576512,1181628415,0,0,PS1,CEMM,EmmT3448Expiry_4,P_INFO,swLogPrintf("Under OOS , will retransmit after plmn search succeed. "); +576512,1181628416,0,0,PS1,CEMM,EmmT3448Expiry_other_1,P_WARNING,swLogPrintf("T3448 expiry , but current emmState is %d "); +576512,1181632511,0,0,PS1,CEMM,EmmSigRetransmitTimerExpiry_1,P_WARNING,swLogPrintf("No pending Data need to retransmit! "); +576512,1181634559,0,0,PS1,CEMM,EmmSigRetransmitTimerExpiry_2,P_INFO,swLogPrintf("ESM request is received under EMM_REGISTERED_NO_CELL_AVAILABLE , service status is No_Service! "); +576512,1181636607,0,0,PS1,CEMM,EmmSigRetransmitTimerExpiry_3,P_INFO,swLogPrintf("Under OOS , will retransmit after plmn search succeed. "); +576512,1181638655,0,0,PS1,CEMM,EmmSigRetransmitTimerExpiry_4,P_INFO,swLogPrintf("TAU is ongoing , will retransmit after TAU succeed. "); +576512,1181640703,0,0,PS1,CEMM,EmmSigRetransmitTimerExpiry_5,P_INFO,swLogPrintf("Plmn Searching , will retransmit after plmn search succeed. "); +576512,1181640704,0,0,PS1,CEMM,EmmSigRetransmitTimerExpiry_6,P_VALUE,swLogPrintf("Can ' t retransmit under EMM state : %d "); +576512,1181642753,0,0,PS1,CEMM,EmmTimerExpiry_1,P_INFO,swLogPrintf("EMM timer %s expire "); +576512,1181644801,0,0,PS1,CEMM,EmmHibTimerExpiry_1,P_INFO,swLogPrintf("EMM Hibernate timer %s expire "); +576512,1181646848,0,0,PS1,CEMM,ConstructAttachRequest_1,P_WARNING,swLogPrintf("Unexpected ATTACH procedure : %d "); +576512,1181648896,0,0,PS1,CEMM,ConstructDetachRequest_1,P_WARNING,swLogPrintf("Unexpected DETACH procedure : %d "); +576512,1181652991,0,0,PS1,CEMM,CemmIsNeedSetSaf_1,P_VALUE,swLogPrintf("Had pending ul esm msg in cp data cache , need to set saf! "); +576512,1181655039,0,0,PS1,CEMM,ConstructTauRequest_1,P_WARNING,swLogPrintf("EMM specific procedure wrong! "); +576512,1181657087,0,0,PS1,CEMM,ConstructTauRequest_2,P_WARNING,swLogPrintf("GUTI is invalid! "); +576512,1181659135,0,0,PS1,CEMM,UsatGetImeiSv_1,P_WARNING,swLogPrintf("Read IMEI failed , use default IMEI "); +577536,1182795776,0,0,PS1,CESM,CesmSendEsmUnitDataReqMsg_v_1,P_VALUE,swLogPrintf("CESM , CemmEsmUnitDataReq , msgType : 0x%x "); +577536,1182797824,0,0,PS1,CESM,CesmConstructBrResourceAllocReq_pti_1,P_VALUE,swLogPrintf("CESM , MO dedicated BR ACT , retx BEARER_RESOURCE_ALLOCATION_REQUEST , re-use old pti : %d "); +577536,1182799872,0,0,PS1,CESM,CesmConstructBrResourceAllocReq_pf_num_1,P_WARNING,swLogPrintf("CESM , CID : %d , MO act dedicated BR req more TFA packet filter , but we only support 4 "); +577536,1182801920,0,0,PS1,CESM,CesmConstructBearerResourceAllocReq_eqos_1,P_WARNING,swLogPrintf("CESM , CID : %d , BearerResourceAllocReq qos IE is Mandatory , must be set before allocReq , default set to 0 "); +577536,1182803968,0,0,PS1,CESM,CesmSendPdnDisconnectReq_pti_1,P_VALUE,swLogPrintf("CESM , retx PDN_DISCONNECT_REQUEST , re-use old pti : %d "); +577536,1182806016,0,0,PS1,CESM,CesmSendBrResourceModifyReqForDedBrDeact_pti_1,P_VALUE,swLogPrintf("CESM , retx BEARER_RESOURCE_MODIFICATION_REQUEST , re-use old pti : %d "); +577536,1182808576,0,0,PS1,CESM,CesmSendBrResourceModifyReqForDedBrDeact_tft_w_1,P_WARNING,swLogPrintf("CESM , more TFT packetfilter in dedicated ebi : %d , delPfNum : %d , delPfListIdx : %d "); +577536,1182812159,0,0,PS1,CESM,CesmSendBrResourceModifyReqForDedBrDeact_tft_w_2,P_WARNING,swLogDump("CESM , dump delPfIdList : "); +577536,1182812928,0,0,PS1,CESM,CesmSendBrResourceModifyReqForDedBrDeact_notft_w_1,P_WARNING,swLogPrintf("CESM , dedicated ebi : %d , brState : %d , but no TFT assigned , tft1present : %d , tft2present : %d "); +577536,1182814208,0,0,PS1,CESM,CesmSendBrResourceModifyReq_pti_1,P_VALUE,swLogPrintf("CESM , MO modify , retx BEARER_RESOURCE_MODIFICATION_REQUEST , re-use old pti : %d "); +577536,1182816256,0,0,PS1,CESM,CesmSendBrResourceModifyReq_pf_num_1,P_WARNING,swLogPrintf("CESM , CID : %d , MO modify req more TFA packet filter , but we only support 4 "); +577536,1182818560,0,0,PS1,CESM,CesmSendEsmDataTransport_len_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , invalid UL ESM_DATA_TRANSPORT data length : %d , discard current PKG "); +577536,1182820352,0,0,PS1,CESM,CesmSendEsmDataTransport_len_w_2,P_WARNING,swLogPrintf("CESM , ebi : %d , no valid UL ESM_DATA_TRANSPORT left , not need Tx "); +577536,1182822400,0,0,PS1,CESM,CesmSendEsmDataTransport_rai_w_1,P_WARNING,swLogPrintf("CESM , RAI : %d ( 1 -NO_UL_DL / 2 -ONLY_DL ) , but still UL PKG pending , RAI change to 0 - NO_INFO "); +577536,1182824704,0,0,PS1,CESM,CesmSendEsmDataTransport_rai_s_1,P_SIG,swLogPrintf("CESM , EBI : %d , RAI flag : %d , RAI_NO_INFO ( 0 ) / NO_UL_DL ( 1 ) / ONLY_DL ( 2 ) / REVD ( 3 ) "); +577536,1182828543,0,0,PS1,CESM,CesmUpdateDlPcoInfoFromDlMsg_v4_w_1,P_WARNING,swLogDump("CESM , IPv4 DNS list is full , can ' t add a new IPV4 DNS : "); +577536,1182830591,0,0,PS1,CESM,CesmUpdateDlPcoInfoFromDlMsg_v6_w_1,P_WARNING,swLogDump("CESM , IPv6 DNS list is full , can ' t add a new IPV6 DNS : "); +577536,1182830848,0,0,PS1,CESM,CesmUpdateDlPcoInfoFromDlMsg_type_w_1,P_WARNING,swLogPrintf("CESM , index : %d , invalid DNS iptype : %d , or all zero addr "); +577536,1182832640,0,0,PS1,CESM,CesmUpdateDlPcoInfoFromDlMsg_mtu_w_1,P_WARNING,swLogPrintf("CESM , invalid / not support ipv4 MTU in DL PCO : %d "); +577536,1182834688,0,0,PS1,CESM,CesmUpdateDefBrBasicFromActDefEpsBrCtxReq_cp_1,P_WARNING,swLogPrintf("CESM , EBI : %d , CP only set in ActivateDefEpsBearerCtxRequest , not right , ignore "); +577536,1182836992,0,0,PS1,CESM,CesmUpdateDefBrBasicFromActDefEpsBrCtxReq_w_1,P_WARNING,swLogPrintf("CESM , EBI : %d , invalid APN in ActivateDefEpsBearerCtxRequest , len : %d "); +577536,1182839296,0,0,PS1,CESM,CesmBrBasicAddTftPacketFilter_in_1,P_VALUE,swLogPrintf("CESM , ebi : %d , try add / replace TFT pfId : %d , pfEpId : %d "); +577536,1182842112,0,0,PS1,CESM,CesmBrBasicAddTftPacketFilter_ded_same_1,P_VALUE,swLogPrintf("CESM , ded ebi : %d , tft1Present : %d , pfId : %d / %d , pfEpId : %d / %d replace "); +577536,1182844160,0,0,PS1,CESM,CesmBrBasicAddTftPacketFilter_ded_same_2,P_VALUE,swLogPrintf("CESM , ded ebi : %d , tft2Present : %d , pfId : %d / %d , pfEpId : %d / %d replace "); +577536,1182846208,0,0,PS1,CESM,CesmBrBasicAddTftPacketFilter_def_same_1,P_VALUE,swLogPrintf("CESM , def ebi : %d , tftPresent : %d , pfId : %d / %d , pfEpId : %d / %d replace "); +577536,1182848000,0,0,PS1,CESM,CesmBrBasicAddTftPacketFilter_same_2,P_VALUE,swLogPrintf("CESM , ebi : %d , pfId : %d / %d , pfEpId : %d / %d found , replace "); +577536,1182849280,0,0,PS1,CESM,CesmBrBasicAddTftPacketFilter_mem_w_1,P_WARNING,swLogPrintf("CESM , no slp2 mem left to add new TFT PF , ebi : %d , pfId : %d "); +577536,1182851328,0,0,PS1,CESM,CesmBrBasicDeleteTftPacketFilter_in_1,P_VALUE,swLogPrintf("CESM , ebi : %d , try delete TFT pfId : %d "); +577536,1182853376,0,0,PS1,CESM,CesmBrBasicDeleteTftPacketFilter_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , no TFT pfId : %d found , can ' t delete "); +577536,1182855936,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_tft_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , tft opcode : %d , but no pf config : %d / 0x%x , reject "); +577536,1182857728,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_pfId_dup_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , tft opcode : %d , pfId : %d , duplicated in request , reject "); +577536,1182859776,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_pfEpId_dup_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , tft opcode : %d , pfEpId : %d , duplicated in request , reject "); +577536,1182861824,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_del_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , tft opcode : Delete existing TFT , but pf list not empty : %d / 0x%x in TFT , reject "); +577536,1182863360,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_del_w_3,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , dedicated BR not allow to delete existing TFT , reject "); +577536,1182865664,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_del_w_4,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , tft opcode : Delete packet filters from existing TFT , but pf list empty : %d in TFT , reject "); +577536,1182867456,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_del_w_5,P_WARNING,swLogPrintf("CESM , ded ebi : %d , delete packet filters from existing TFT , not allow to del all , reject "); +577536,1182870016,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_no_tft_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , tft opcode : No TFT operation , but pf list not empty : %d / 0x%x in TFT , reject "); +577536,1182872064,0,0,PS1,CESM,CesmUpdateTftFromModifyEpsBrCtxReq_opCode_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv modify BR reqest , unkown TFT opCode : %d , pfNum : %d , ignore "); +577536,1182873856,0,0,PS1,CESM,CesmUpdateBrBasicFromModifyEpsBrCtxReq_tft_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , modify TFT NOK , retErr : %d "); +577536,1182875648,0,0,PS1,CESM,CesmUpdateBrBasicFromModifyEpsBrCtxReq_apnrate_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , dedicated BR , not support APN rate CTRL , ignore "); +577536,1182877696,0,0,PS1,CESM,CesmUpdateBrBasicFromModifyEpsBrCtxReq_apnrate_w_2,P_WARNING,swLogPrintf("CESM , ebi : %d , dedicated BR , not support additional APN rate CTRL , ignore "); +577536,1182880256,0,0,PS1,CESM,CesmUpdateTftFromActDedEpsBrCtxReq_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , cid : %d , act dedicated BR , but TFT opCode : %d , not right , reject case : 41 "); +577536,1182882560,0,0,PS1,CESM,CesmUpdateTftFromActDedEpsBrCtxReq_num_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , cid : %d , act dedicated BR , but packet filer number : %d / 0x%x , not right , reject case : 42 "); +577536,1182884352,0,0,PS1,CESM,CesmUpdateTftFromActDedEpsBrCtxReq_pfId_dup_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv act ded BR reqest , tft opcode : %d , pfId : %d , duplicated in request , reject "); +577536,1182886400,0,0,PS1,CESM,CesmUpdateTftFromActDedEpsBrCtxReq_pfEpId_dup_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , recv act ded BR reqest , tft opcode : %d , pfEpId : %d , duplicated in request , reject "); +577536,1182887936,0,0,PS1,CESM,CesmUpdateDedBrBasicFromActDedEpsBrCtxReq_eps_w_2,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , dedicated ebi : %d , no EPS basic CTX avaiable "); +577536,1182890496,0,0,PS1,CESM,CesmUpdateDedBrBasicFromActDedEpsBrCtxReq_tft_1,P_WARNING,swLogPrintf("CESM , act ded BR , ebi : %d , cid : %d , check TFT not right , esmCause : %d "); +577536,1182892032,0,0,PS1,CESM,CesmBrMoActEstablishCnf_ded_s_1,P_SIG,swLogPrintf("CESM , CID : %d , request act dedicated bearer , but EMM establish failed , start T3480 and retry later "); +577536,1182894336,0,0,PS1,CESM,CesmBrMoActEstablishCnf_def_s_2,P_SIG,swLogPrintf("CESM , CID : %d , request act default bearer , but EMM establish failed , start T3482 : %d ms and retry later "); +577536,1182896384,0,0,PS1,CESM,CesmBrMoActEstablishCnf_def_s_3,P_SIG,swLogPrintf("CESM , CID : %d , start timer T3482 , MS : %d , and send PDN CONNECTIVITY REQUEST "); +577536,1182898176,0,0,PS1,CESM,CesmBrMoModifyEstablishCnf_est_s_1,P_SIG,swLogPrintf("CESM , CID : %d , request modify BR , but EMM establish failed , start T3481 and retry later "); +577536,1182900736,0,0,PS1,CESM,CesmBrMoModifyEstablishCnf_br_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , EBI : %d , brState : %d , request modify BR , but no basic BR info , abnormal , local deact "); +577536,1182902784,0,0,PS1,CESM,CesmBrMoModifyEstablishCnf_modify_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , EBI : %d , brState : %d , no reqTFA or reqEQOS , can ' t MO modify "); +577536,1182904576,0,0,PS1,CESM,CesmBrMoDeactEstablishCnf_ded_s_1,P_SIG,swLogPrintf("CESM , CID : %d , ebi : %d , request deact dedicated bearer , but EMM establish failed , start T3481 and retry later "); +577536,1182906880,0,0,PS1,CESM,CesmBrMoDeactEstablishCnf_def_s_1,P_SIG,swLogPrintf("CESM , CID : %d , ebi : %d , request act default bearer , but EMM establish failed , start T3492 : %dms and retry later "); +577536,1182908672,0,0,PS1,CESM,CesmBrMoDeactEstablishCnf_ded_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , dedicated ebi : %d , brState CESM_BR_CTX_MO_DEACT_PENDING , but no basic info "); +577536,1182910464,0,0,PS1,CESM,CesmMoReactDeactOldEpsBrReq_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , re-act BR , new BR activated , but old BR not found "); +577536,1182912768,0,0,PS1,CESM,CesmMoReactDeactOldEpsBrReq_brState_1,P_VALUE,swLogPrintf("CESM , cid : %d , deact old BR , brState : %e "); +577536,1182914816,0,0,PS1,CESM,CesmMoReactDeactOldEpsBrReq_brState_w_4,P_WARNING,swLogPrintf("CESM , cid : %d , deact old BR , while brState : %d , local deact firstly "); +577536,1182916608,0,0,PS1,CESM,CesmMoReactDeactOldEpsBrReq_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , deact old BR , but ESM is suspended , pending "); +577536,1182918656,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_pti_w_1,P_WARNING,swLogPrintf("CESM , invalid PTI : %d in ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_REQUEST "); +577536,1182920704,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_ebi_w_1,P_WARNING,swLogPrintf("CESM , invalid EBI : %d in ACTIVATE_DEFAULT_EPS_BEARER_CONTEXT_REQUEST "); +577536,1182923520,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_ebi_w_2,P_WARNING,swLogPrintf("CESM , EPS bearer ebi : %d , already exist , DL duplicated , msgPti : %d , brPti : %d , brState : %d "); +577536,1182924800,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_ebi_w_3,P_WARNING,swLogPrintf("CESM , EPS bearer ebi : %d , already exist , local deact "); +577536,1182927104,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_pti_w_2,P_WARNING,swLogPrintf("CESM , no EPS bearer found for PTI : %d , EBI : %d "); +577536,1182929664,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_pti_ebi_1,P_WARNING,swLogPrintf("CESM , found EPS bearer via PTI : %d , brEbi : %d , brState : %d already set , msgEbi : %d , reject cur req "); +577536,1182930944,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_basic_w_1,P_WARNING,swLogPrintf("CESM , no memory left for ESM basic bearer info , ebi : %d , reject cur req "); +577536,1182933504,0,0,PS1,CESM,CesmProcActDefEpsBrCtxReq_state_w_1,P_WARNING,swLogPrintf("CESM , EBI : %d , CID : %d , invalid brState : %d , when proc ActivateDefEpsBearerCtxRequest "); +577536,1182935040,0,0,PS1,CESM,CesmProcEsmInfoReq_pti_w_1,P_WARNING,swLogPrintf("CESM , no EPS BR found via PTI : %d , carried in ESMInformationRequest "); +577536,1182937344,0,0,PS1,CESM,CesmProcEsmInfoReq_pti_w_2,P_WARNING,swLogPrintf("CESM , dedicated EPS BR CID : %d , found via PTI : %d , not right "); +577536,1182939392,0,0,PS1,CESM,CesmProcEsmInfoReq_brState_w_1,P_WARNING,swLogPrintf("CESM , BR CID : %d , brState : %d not right when proc ESMInformationRequest "); +577536,1182941185,0,0,PS1,CESM,CesmProcEsmInfoReq_att_w_1,P_WARNING,swLogPrintf("CESM , attach request APN changed to : %s into tiny "); +577536,1182945279,0,0,PS1,CESM,CesmProcEsmInfoReq_att_w_2,P_WARNING,swLogPrintf("CESM , attach req APN changed to NULL , save into tiny "); +577536,1182945792,0,0,PS1,CESM,CesmProcDeactEpsBrCtxReq_pti_br_w_1,P_WARNING,swLogPrintf("CESM , PTI : %d , CID : %d , brState : %d not right when proc DeactivateEPSBearerCtxRequest "); +577536,1182947328,0,0,PS1,CESM,CesmProcDeactEpsBrCtxReq_pti_w_2,P_WARNING,swLogPrintf("CESM , PTI : %d in DeactivateEPSBearerCtxRequest , but no bearer found "); +577536,1182951423,0,0,PS1,CESM,CesmProcDeactEpsBrCtxReq_reatt_1,P_WARNING,swLogPrintf("CESM , last default BR deact , need re-attach "); +577536,1182951680,0,0,PS1,CESM,CesmProcPdnConnectivityRej_pti_w_1,P_WARNING,swLogPrintf("CESM , recv PDNConnectivityReject with pti : %d , cause : %d. but no BR found via pti , or is dedicated bearer "); +577536,1182953984,0,0,PS1,CESM,CesmProcPdnConnectivityRej_brState_w_1,P_WARNING,swLogPrintf("CESM , recv PDNConnectivityReject , cid : %d , ebi : %d , brState : %d , but BR activated , abnormal "); +577536,1182955521,0,0,PS1,CESM,CesmProcPdnConnectivityRej_brState_w_2,P_WARNING,swLogPrintf("CESM , recv PDNConnectivityReject , but ebi : %s is set , abnormal "); +577536,1182958080,0,0,PS1,CESM,CesmProcPdnConnectivityRej_brState_w_3,P_WARNING,swLogPrintf("CESM , recv PDNConnectivityReject , cid : %d , ebi : %d , brState : %d , abnormal , local deact "); +577536,1182960384,0,0,PS1,CESM,CesmProcPdnConnectivityRej_auth_1,P_WARNING,swLogPrintf("CESM , cid : %d , state : %d , authtype : %d , attachPdnAuthRetry : %d "); +577536,1182963711,0,0,PS1,CESM,CesmProcPdnConnectivityRej_auth_fail,P_WARNING,swLogPrintf("CESM , recv PDN connect reject again as CHAP / PAP auth , should local deactivated "); +577536,1182963712,0,0,PS1,CESM,CesmProcMtActDedEpsBrCtxReq_cid_w_1,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , dedicated ebi : %d , no valid CID could allocated "); +577536,1182966272,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_cid_v_1,P_VALUE,swLogPrintf("CESM , dedicated ebi : %d , but cid : %d is used , try to use cid : %d "); +577536,1182968064,0,0,PS1,CESM,CesmProcMtActDedEpsBrCtxReq_cid_undefine_1,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , find a default bearer , cid : %d , brState : %d , undefined it "); +577536,1182969856,0,0,PS1,CESM,CesmProcMtActDedEpsBrCtxReq_eps_w_1,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , dedicated ebi : %d , no EPS CTX avaiable "); +577536,1182972160,0,0,PS1,CESM,CesmProcMtActDedEpsBrCtxReq_eps_w_2,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , dedicated ebi : %d , update ctx fail esmCause : %d "); +577536,1182973952,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_ebi_w_1,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , ebi : %d , not valid / supported "); +577536,1182976512,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_linkedebi_w_1,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , dedicated ebi : %d , can ' t find linked ebi : %d , or linked BR not act : %d "); +577536,1182978304,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_ebi_dup_w_1,P_WARNING,swLogPrintf("CESM , ActivateDedEpsBearerCtxRequest , dedicated ebi : %d , BR already exist , brState : %d "); +577536,1182980864,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_dup_ebi_w_2,P_WARNING,swLogPrintf("CESM , dedicated bearer ebi : %d , already exist , DL duplicated , msgPti : %d , brPti : %d , brState : %d "); +577536,1182982144,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_dup_ebi_w_3,P_WARNING,swLogPrintf("CESM , EPS bearer ebi : %d , already exist , local deact "); +577536,1182984192,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_pti_w_1,P_WARNING,swLogPrintf("CESM , pti : %d in ActivateDedEpsBearerCtxRequest , can ' t find EPS bearer , reject "); +577536,1182986496,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_mo_act_w_1,P_WARNING,swLogPrintf("CESM , pti : %d , UE request a default bearer cid : %d , but a dedicated bearer accept "); +577536,1182988800,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_mo_mod_w_1,P_WARNING,swLogPrintf("CESM , pti : %d , UE request to modify bearer cid : %d , but a dedicated bearer ebi : %d accept , reject MO modify proc "); +577536,1182991104,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_brState_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , pti : %d , brState : %e , but a dedicated bearer ebi : %d accept "); +577536,1182992640,0,0,PS1,CESM,CesmProcModifyEpsBrCtxReq_pti_w_1,P_WARNING,swLogPrintf("CESM , can ' t find BR via pti : %d , can ' t proc ModifyEPSBearerCtxRequest , ebi : %d "); +577536,1182994432,0,0,PS1,CESM,CesmProcActDedEpsBrCtxReq_dup_pti_w_2,P_WARNING,swLogPrintf("CESM , ModifyEPSBearerCtxRequest duplicated , pti : %d , act as a MT proc , and ongoing "); +577536,1182996480,0,0,PS1,CESM,CesmProcModifyEpsBrCtxReq_no_ebi_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , no BR found , can ' t proc ModifyEPSBearerCtxRequest "); +577536,1182999552,0,0,PS1,CESM,CesmProcModifyEpsBrCtxReq_pti_ebi_w_1,P_WARNING,swLogPrintf("CESM , recv ModifyEPSBearerCtxRequest , ebi : %d , cid : %d , pti : %d , but pti is for BR CID : %d , brState : %d "); +577536,1183000576,0,0,PS1,CESM,CesmProcModifyEpsBrCtxReq_no_ebi_w_2,P_WARNING,swLogPrintf("CESM , ebi : %d , BR deacted , can ' t proc ModifyEPSBearerCtxRequest "); +577536,1183003136,0,0,PS1,CESM,CesmProcModifyEpsBrCtxReq_basic_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , ebi : %d , brState : %d , but basic context not exist , local deact "); +577536,1183005184,0,0,PS1,CESM,CesmProcModifyEpsBrCtxReq_update_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , brState : %d , modify NOK , esmCause : %d "); +577536,1183007744,0,0,PS1,CESM,CesmProcPdnDisconnectRej_state_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , pti : %d , PDNDisconnectReject with cause : %d , brState : %d not right , or not default BR : %d "); +577536,1183009536,0,0,PS1,CESM,CesmProcPdnDisconnectRej_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , brState : %d , pti : %d , PDNDisconnectReject with casue : %d , last PDN not allow to deact "); +577536,1183011328,0,0,PS1,CESM,CesmProcPdnDisconnectRej_pti_w_1,P_WARNING,swLogPrintf("CESM , PDNDisconnectReject with casue : %d , pti : %d , ebi : %d , can ' t find BR via PTI "); +577536,1183013120,0,0,PS1,CESM,CesmProcPdnDisconnectRej_ebi_w_1,P_WARNING,swLogPrintf("CESM , PDNDisconnectReject with casue : %d , ebi : %d , accord 3 GPP should be 0 , not right "); +577536,1183015936,0,0,PS1,CESM,CesmProcBrResourceAllocRej_state_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , pti : %d , BrResourceAllocRej with cause : %d , brState : %d not right , or not dedicated BR : %d "); +577536,1183017216,0,0,PS1,CESM,CesmProcBrResourceAllocRej_def_w_1,P_WARNING,swLogPrintf("CESM , BrResourceAllocRej with cause : invalid EBI : 43 , need local deact linked def BR , EBI : %d , cid : %d "); +577536,1183019520,0,0,PS1,CESM,CesmProcBrResourceAllocRej_pti_w_1,P_WARNING,swLogPrintf("CESM , BrResourceAllocRej with casue : %d , pti : %d , ebi : %d , can ' t find BR via PTI "); +577536,1183021056,0,0,PS1,CESM,CesmProcBrResourceAllocRej_T3396_w_1,P_WARNING,swLogPrintf("CESM , BrResourceAllocRej with cause : %d , and Backoff timer set , but UE not support now "); +577536,1183023360,0,0,PS1,CESM,CesmProcBrResourceAllocRej_ebi_w_1,P_WARNING,swLogPrintf("CESM , BrResourceAllocRej with casue : %d , ebi : %d , accord 3 GPP should be 0 , not right "); +577536,1183025920,0,0,PS1,CESM,CesmProcBrResourceModRej_state_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , pti : %d , BrResourceModRej with cause : %d , brState : %d not right "); +577536,1183027456,0,0,PS1,CESM,CesmProcBrResourceModRej_ebi_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , pti : %d , BrResourceModRej with cause : invalid EPS bearer identity , local deact "); +577536,1183029760,0,0,PS1,CESM,CesmProcBrResourceModRej_deact_1,P_SIG,swLogPrintf("CESM , ebi : %d , pti : %d , BrResourceModRej with cause : %d , MO deact proc , local deact "); +577536,1183031808,0,0,PS1,CESM,CesmProcBrResourceModRej_mod_1,P_SIG,swLogPrintf("CESM , ebi : %d , pti : %d , BrResourceModRej with cause : %d , MO modify proc , back to ACT state "); +577536,1183034112,0,0,PS1,CESM,CesmProcBrResourceModRej_br_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , pti : %d , BrResourceModRej with cause : %d , brState : %d , ignore "); +577536,1183035904,0,0,PS1,CESM,CesmProcBrResourceModRej_pti_w_1,P_WARNING,swLogPrintf("CESM , BrResourceModRej with casue : %d , pti : %d , ebi : %d , can ' t find BR via PTI "); +577536,1183037440,0,0,PS1,CESM,CesmProcBrResourceModRej_T3396_w_1,P_WARNING,swLogPrintf("CESM , BrResourceModRej with cause : %d , and Backoff timer set , but UE not support now "); +577536,1183039744,0,0,PS1,CESM,CesmProcBrResourceModRej_ebi_w_2,P_WARNING,swLogPrintf("CESM , BrResourceModRej with casue : %d , ebi : %d , accord 3 GPP should be 0 , not right "); +577536,1183042048,0,0,PS1,CESM,CesmProcEsmDataTransport_ciot_w_1,P_WARNING,swLogPrintf("CESM , UE or NW not support CP OPT , nwSupCiotOpt : %d , uePreferOpt : %d , ueSuptOptType : %d , but still recv DL CP data "); +577536,1183043840,0,0,PS1,CESM,CesmProcEsmDataTransport_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , not exist , discard DL CP data , length : %d "); +577536,1183045632,0,0,PS1,CESM,CesmProcEsmDataTransport_f_1,P_WARNING,swLogPrintf("CESM , DL PKG mem high , discard DL CP data , length : %d "); +577536,1183047680,0,0,PS1,CESM,CesmProcEsmDataTransport_hf_1,P_WARNING,swLogPrintf("CESM , heap full , can ' t report MT CP data , length : %d "); +577536,1183050240,0,0,PS1,CESM,CesmProcESMStatus_s_1,P_SIG,swLogPrintf("CESM , recv ESMStatus , ebi : %d , pti : %d , esmCause : %d "); +577536,1183051776,0,0,PS1,CESM,CesmProcESMStatus_ebi_w_1,P_WARNING,swLogPrintf("CESM , recv ESMStatus , ebi : %d , esmCause : Invalid EPS BR ID , but no BR found "); +577536,1183054336,0,0,PS1,CESM,CesmProcESMStatus_97_w_1,P_WARNING,swLogPrintf("CESM , recv ESMStatus , ebi : %d , pti : %d , esmCause : %d , BR state : CESM_BR_CTX_ATTACH_ACT_PENDING , let EMM retry "); +577536,1183056640,0,0,PS1,CESM,CesmProcESMStatus_97_w_2,P_WARNING,swLogPrintf("CESM , recv ESMStatus , pti : %d , ebi : %d , esmCause : %d , BR state : %d , not right "); +577536,1183058432,0,0,PS1,CESM,CesmProcESMStatus_other_w_1,P_WARNING,swLogPrintf("CESM , recv ESMStatus , pti : %d , ebi : %d , esmCause : %d , not need to proc "); +577536,1183062015,0,0,PS1,CESM,CesmCheckSendEsmDataTransport_clear_1,P_INFO,swLogPrintf("CESM , all UL data Tx / clear "); +577536,1183064063,0,0,PS1,CESM,CesmCheckSendEsmDataTransport_timer_1,P_WARNING,swLogPrintf("CESM , UL data retry timer is running , pending ESM DATA TRANSPORT till timer expiry "); +577536,1183066111,0,0,PS1,CESM,CesmProcUlDataTransReqSig_busy_1,P_SIG,swLogPrintf("CESM , UL data busy , pending current data request "); +577536,1183068159,0,0,PS1,CESM,CesmCheckSendEsmDataTransport_suspend_1,P_SIG,swLogPrintf("CESM , ESM suspended , but except data allowed "); +577536,1183068160,0,0,PS1,CESM,CesmCheckSendEsmDataTransport_suspend_2,P_SIG,swLogPrintf("CESM , ESM suspended , can ' t Tx UL data , ebi : %d "); +577536,1183070208,0,0,PS1,CESM,CemmEsmProcMsgContainerIndMsg_msg_w_1,P_WARNING,swLogPrintf("CESM , ESM signalling in ATTACH REQUEST : 0x%x , change to PDN_CONNECTIVITY_REQUEST "); +577536,1183072256,0,0,PS1,CESM,CemmEsmProcMsgContainerIndMsg_cid_w_1,P_WARNING,swLogPrintf("CESM , invalid attached EPS CID : %d setting , using CID 0 "); +577536,1183074816,0,0,PS1,CESM,CemmEsmProcMsgContainerIndMsg_auth_1,P_WARNING,swLogPrintf("CESM , CID : %d , state : %d , pdnAuthReqRetry : %d "); +577536,1183076352,0,0,PS1,CESM,CemmEsmProcMsgContainerIndMsg_cid_1,P_VALUE,swLogPrintf("CESM , CID : %d , MO request bearer same as attached bearer "); +577536,1183078656,0,0,PS1,CESM,CemmEsmProcMsgContainerIndMsg_state_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , attached bearer state is not right : %e "); +577536,1183080448,0,0,PS1,CESM,CemmEsmProcUnitDataIndMsg_1,P_VALUE,swLogPrintf("CESM , recv DL msgType : %e "); +577536,1183082496,0,0,PS1,CESM,CemmEsmProcUnitDataIndMsg_dup_w_1,P_WARNING,swLogPrintf("CESM , recv duplicated DL msgType : 0x%x "); +577536,1183084544,0,0,PS1,CESM,CemmEsmProcUnitDataIndMsg_unknown_w_1,P_WARNING,swLogPrintf("CESM , unknown ESM msg : 0x%x , not proc "); +577536,1183086592,0,0,PS1,CESM,CemmEsmProcEstablishCnfMsg_s_1,P_SIG,swLogPrintf("CESM , EMM EST CNF bSucc : %d "); +577536,1183088640,0,0,PS1,CESM,CemmEsmProcEstablishCnfMsg_w_1,P_SIG,swLogPrintf("CESM , EMM EST CNF bSucc : %d , but no ESM procedure pending "); +577536,1183091200,0,0,PS1,CESM,CemmEsmProcBearerContextStatusIndMsg_nw_syn_w_1,P_WARNING,swLogPrintf("CESM , NW syn BR status , EBI : %d , not found : 0x%lx , or not acted State : %d , and no BR act ongoing "); +577536,1183093248,0,0,PS1,CESM,CemmEsmProcBearerContextStatusIndMsg_reAttach_0,P_WARNING,swLogPrintf("CESM , NW syn BR status , CID : %d , EBI : %d , state : %d , is the last def eps bearer , should re-attach "); +577536,1183095040,0,0,PS1,CESM,CemmEsmProcBearerContextStatusIndMsg_nw_syn_w_2,P_WARNING,swLogPrintf("CESM , NW syn BR status , EBI : %d INACT in NW , but in UE brState : %d , local deact "); +577536,1183098879,0,0,PS1,CESM,CemmEsmProcBearerContextStatusIndMsg_ue_syn_w_1,P_WARNING,swLogPrintf("CESM , SYN BR status , no EPS activated "); +577536,1183100927,0,0,PS1,CESM,CemmEsmProcTransmissionFailureIndMsg_s_1,P_SIG,swLogPrintf("CESM , attach complete trans fail , need ESM re-tx ActivateDefaultEpsBearerContextAccept "); +577536,1183102975,0,0,PS1,CESM,CemmEsmProcTransmissionFailureIndMsg_s_2,P_SIG,swLogPrintf("CESM , attach complete trans fail , need ESM re-tx EsmDummy "); +577536,1183103232,0,0,PS1,CESM,CemmEsmProcSuspendIndMsg_1,P_VALUE,swLogPrintf("CESM , EMM suspend ESM , ExptDataViaCPAllowed : %d , UpDataAllowed : %d "); +577536,1183107071,0,0,PS1,CESM,CemmEsmProcResumeIndMsg_1,P_VALUE,swLogPrintf("CESM , EMM resume ESM "); +577536,1183107072,0,0,PS1,CESM,CemmEsmProcResumeIndMsg_w_1,P_WARNING,swLogPrintf("CESM , ESM resumed , but more MO proc is pending : %d "); +577536,1183109120,0,0,PS1,CESM,CemmEsmProcReleaseIndMsg_s_1,P_SIG,swLogPrintf("CESM , proc CesmReleaseInd msg , bePowerOff : %d , local deact all bearers "); +577536,1183111168,0,0,PS1,CESM,CemmEsmProcAbortIndMsg_act_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , MO ACT , abort by MM , local deact "); +577536,1183113216,0,0,PS1,CESM,CemmEsmProcAbortIndMsg_mod_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , MO MODIFY , abort by MM , MO modify failed , back to ACT state "); +577536,1183115264,0,0,PS1,CESM,CemmEsmProcAbortIndMsg_deact_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , MO DEACT , abort by MM , local deact "); +577536,1183119359,0,0,PS1,CESM,CemmEsmProcAbortIndMsg_clear_1,P_WARNING,swLogPrintf("CESM , all UL data clear / discard "); +577536,1183119360,0,0,PS1,CESM,CemmEsmProcAbortIndMsg_retry_1,P_SIG,swLogPrintf("CESM , UL data abort by MM , start retry time : %d ms "); +577536,1183121664,0,0,PS1,CESM,CemmEsmProcFeatureSupportIndMsg_epco_1,P_VALUE,swLogPrintf("CESM , FeatureInd , NW support ePCO : %d , UE request ePCO : %d "); +577536,1183123456,0,0,PS1,CESM,CemmEsmProcFeatureSupportIndMsg_without_pdn_1,P_VALUE,swLogPrintf("CESM , FeatureInd , NW support attachWithoutPdn : %d "); +577536,1183126016,0,0,PS1,CESM,CemmEsmProcFeatureSupportIndMsg_ciot_1,P_VALUE,swLogPrintf("CESM , FeatureInd , nwSupCiotOpt : %d , uePreferOpt : %d , ueSuptOptType : %d ( 0 -NO_OPT , 1 -CP_OPT , 2 -UP_OPT , 3 -CP_UP_OPT ) "); +577536,1183128064,0,0,PS1,CESM,CemmEsmProcFeatureSupportIndMsg_ciot_w_1,P_WARNING,swLogPrintf("CESM , UE or NW not support CP OPT , nwSupCiotOpt : %d , uePreferOpt : %d , ueSuptOptType : %d , free all pending UL CP data "); +577536,1183131647,0,0,PS1,CESM,CemmEsmProcSimAclConfigIndMsg_error_1,P_WARNING,swLogPrintf("CESM , recv sim ACL config is NULL or RawData NULL , consider sim ACL disable "); +577536,1183131648,0,0,PS1,CESM,CemmEsmProcSimAclConfigIndMsg_error_2,P_WARNING,swLogPrintf("CESM , recv invalid aclrawLen : %d , or the rawdata is PNULL "); +577536,1183133952,0,0,PS1,CESM,CemmEsmProcSimAclConfigIndMsg_0,P_INFO,swLogPrintf("CESM parse SIM ACl , Bytes : 0x%x , 0x%x "); +577536,1183136000,0,0,PS1,CESM,CemmEsmProcSimAclConfigIndMsg_2,P_WARNING,swLogPrintf("CESM parse SIM ACl , check attach pdn Apn is %d ( 1 : Not Check , 0 : Check ) , ACL totalLen : %d "); +577536,1183138048,0,0,PS1,CESM,CesmGetDefBrCmiDnsAddr_ipv4_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , ipv4 dns index : %d , all zero , invalid "); +577536,1183140096,0,0,PS1,CESM,CesmGetDefBrCmiDnsAddr_ipv6_w_1,P_WARNING,swLogPrintf("CESM , ebi : %d , ipv4 dns index : %d , all zero , invalid "); +577536,1183143935,0,0,PS1,CESM,CesmConvertSubnetMaskToPrefixFormat_1,P_WARNING,swLogPrintf("CAC PS , Invalid subnet mask... "); +577536,1183144192,0,0,PS1,CESM,CesmAddCmiTftFilter_cid_w_1,P_WARNING,swLogPrintf("CESM , invalid cid : %d , or packet filter ID : %d , can ' t add CGTFT "); +577536,1183146240,0,0,PS1,CESM,CesmAddCmiTftFilter_dstport_w_1,P_WARNING,swLogPrintf("CESM , remotePort : [ %d , %d ] not right , can ' t add CGTFT "); +577536,1183148288,0,0,PS1,CESM,CesmAddCmiTftFilter_srcport_w_1,P_WARNING,swLogPrintf("CESM , localPort : [ %d , %d ] not right , can ' t add CGTFT "); +577536,1183150336,0,0,PS1,CESM,CesmAddCmiTftFilter_remote_addr_w_1,P_WARNING,swLogPrintf("CESM , remote addr type : %d or subnetMaskLen : %d not right , can ' t add CGTFT "); +577536,1183152128,0,0,PS1,CESM,CesmAddCmiTftFilter_asmb_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , add CGTFT , no memory left "); +577536,1183154432,0,0,PS1,CESM,CesmAddCmiTftFilter_modify_w_1,P_VALUE,swLogPrintf("CESM , cid : %d , pfId : %d , already exist , modify by CGATT "); +577536,1183156480,0,0,PS1,CESM,CesmAddCmiTftFilter_num_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , MAX 4 PF could be set for one BR , can ' t add new pfId : %d "); +577536,1183158784,0,0,PS1,CESM,CesmAddCmiTftFilter_add_n_1,P_WARNING,swLogPrintf("CESM , cid : %d , pfId : %d , no memory left , or lots : %d pf set , can ' t add new "); +577536,1183160832,0,0,PS1,CESM,CesmGetActedBrCmiPsTftFilterList_tftnum_1,P_ERROR,swLogPrintf("CESM , EBI : %d , cid : %d , acted TFT number is not right : %d "); +577536,1183162624,0,0,PS1,CESM,CesmCheckEpsBrNeedReact_dup_1,P_WARNING,swLogPrintf("CESM , another re-act CID : %d is ongoing , can ' t re-act another cid : %d "); +577536,1183164672,0,0,PS1,CESM,CesmCheckEpsBrNeedReact_ded_1,P_VALUE,swLogPrintf("CESM , CID : %d , EPSID : %d is a dedicated BR , but CGDCONT defined ctx , need to re-act "); +577536,1183166720,0,0,PS1,CESM,CesmCheckEpsBrNeedReact_apn_1,P_VALUE,swLogPrintf("CESM , CID : %d , EPSID : %d CGDCONT NULL APN , need to re-act "); +577536,1183169280,0,0,PS1,CESM,CesmCheckEpsBrNeedReact_invalid_1,P_WARNING,swLogPrintf("CESM , CID : %d , EPSID : %d activated default BR , but no basic info : 0x%lx , or APN is NULL : %d , need to re-act "); +577536,1183170816,0,0,PS1,CESM,CesmCheckEpsBrNeedReact_apn_2,P_VALUE,swLogPrintf("CESM , CID : %d , EPSID : %d APN not same , need to re-act "); +577536,1183173376,0,0,PS1,CESM,CesmCheckEpsBrNeedReact_iptype_1,P_VALUE,swLogPrintf("CESM , CID : %d , EPSID : %d , CGDCONT request iptype : %d , current acted iptype : %d , need to re-act "); +577536,1183175168,0,0,PS1,CESM,CesmMoReactEpsBrReq_dup_1,P_WARNING,swLogPrintf("CESM , another re-act is ongoing cid : %d , brState : %d , can ' t re-act new cid : %d "); +577536,1183176704,0,0,PS1,CESM,CesmMoReactEpsBrReq_mem_1,P_WARNING,swLogPrintf("CESM , no SLP2 mem left for re-act BR , cid : %d "); +577536,1183178752,0,0,PS1,CESM,CesmMoReactEpsBrReq_def_1,P_WARNING,swLogPrintf("CESM , re-act CID : %d , but CGDCONT not defined , abnormal "); +577536,1183181056,0,0,PS1,CESM,CesmMoReactEpsBrReq_est_req_1,P_SIG,swLogPrintf("CESM , CID : %d , as upgrade the NSLPI to %d , can to send establish req "); +577536,1183182848,0,0,PS1,CESM,CesmMoReactEpsBrReq_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , re-act EPS bearer request , but ESM is suspended , pending "); +577536,1183185155,0,0,PS1,CESM,CesmCheckEpsBrNeedRemap_apn_1,P_VALUE,swLogPrintf("CESM , new req apn : %s , attach request apn : %s , just same "); +577536,1183187203,0,0,PS1,CESM,CesmCheckEpsBrNeedRemap_apn_2,P_VALUE,swLogPrintf("CESM , new req apn : %s , attach NW assigned apn : %s , just same "); +577536,1183189248,0,0,PS1,CESM,CesmCheckEpsBrNeedRemap_s_1,P_SIG,swLogPrintf("CESM , remap type 1 , new req cid : %d , need remap to old cid : %d "); +577536,1183192356,0,0,PS1,CESM,CesmCheckEpsBrNeedRemap_t2_apn_1,P_SIG,swLogPrintf("CESM , remap type 2 , req new cid : %d , iptype : %d , apn : %s same as acted cid : %d , iptype : %d , apn : %s , remapping "); +577536,1183193088,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_cid_1,P_WARNING,swLogPrintf("CESM , invalid CID : %d in CcmCesmSetEpsBearerCtxReq "); +577536,1183195136,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_iptype_1,P_WARNING,swLogPrintf("CESM , invalid iptype : %d in CcmCesmSetEpsBearerCtxReq "); +577536,1183197442,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_apn_1,P_WARNING,swLogPrintf("CESM , invalid apnLen : %d > 99 , APN : %s , in CcmCesmSetEpsBearerCtxReq "); +577536,1183199748,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_apn_2,P_WARNING,swLogPrintf("CESM , invalid APN CHAR : %d , idx : %d , APN : %s , in CcmCesmSetEpsBearerCtxReq "); +577536,1183201280,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_apn_3,P_WARNING,swLogPrintf("CESM , apnPresentType : %d , don ' t need to update APN "); +577536,1183203328,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_ipv4allo_1,P_WARNING,swLogPrintf("CESM , ipv4AlloType : %d , not support "); +577536,1183205632,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_ipv4allo_2,P_WARNING,swLogPrintf("CESM , pdnType : %d , not ipv4 , or ipv4v6 , not need to set ipv4AlloType : %d "); +577536,1183207424,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_reqType_1,P_WARNING,swLogPrintf("CESM , reqType : %d , not support "); +577536,1183209472,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_NSLPI_1,P_WARNING,swLogPrintf("CESM , NSLPI : %d , not support "); +577536,1183211520,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_RDS_1,P_WARNING,swLogPrintf("CESM , RDS : %d , not support "); +577536,1183213568,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_secpco_1,P_WARNING,swLogPrintf("CESM , SEC PCO : %d , not support "); +577536,1183215616,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_pcscf_1,P_WARNING,swLogPrintf("CESM , PCSCF discovery type : %d , not support "); +577536,1183217664,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_imcn_1,P_WARNING,swLogPrintf("CESM , imCnSigFlag : %d , not support "); +577536,1183219712,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_same_1,P_INFO,swLogPrintf("CESM , define default cid : %d , same as before , not need update "); +577536,1183221760,0,0,PS1,CESM,CesmProcSetEpsBearerCtxReqSig_full_1,P_WARNING,swLogPrintf("CESM , can ' t allc memory for new bearer , cid : %d "); +577536,1183223808,0,0,PS1,CESM,CesmProcCcmGetEpsBrCtxReqSig_cid_1,P_WARNING,swLogPrintf("CESM , invalid cid : %d , can ' t get bearer context "); +577536,1183225856,0,0,PS1,CESM,CesmProcCcmGetEpsBrCtxReqSig_ded_1,P_WARNING,swLogPrintf("CESM , CID : %d , request dedicated bearer info , but bearer is default bearer "); +577536,1183229951,0,0,PS1,CESM,CesmProcCcmGetEpsBrCtxReqSig_brNum_1,P_VALUE,swLogPrintf("CESM , request all bearer info , but no bearer found need to return "); +577536,1183229952,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_cid_w_1,P_WARNING,swLogPrintf("CESM , CCM act EPS bearer request , but BR not found via CID : %d "); +577536,1183232000,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_cid_w_2,P_WARNING,swLogPrintf("CESM , CCM act attach CID : %d EPS bearer , create the BR ctx "); +577536,1183234048,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_brstate_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , CCM act EPS bearer request , but BR state : MO_ACT_PENDING , return "); +577536,1183236096,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_brstate_w_2,P_WARNING,swLogPrintf("CESM , CID : %d , CCM act EPS bearer request , but BR state : ATTACH_ACT_PENDING , change to MO_ACT_PENDING "); +577536,1183238400,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_brstate_w_3,P_WARNING,swLogPrintf("CESM , CID : %d , CCM act EPS bearer request , but BR state : %e , confirm OK "); +577536,1183240448,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_brstate_w_4,P_WARNING,swLogPrintf("CESM , CID : %d , CCM act EPS bearer request , but BR state : %e , reject "); +577536,1183242496,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_est_req_1,P_SIG,swLogPrintf("CESM , CID : %d , as upgrade the NSLPI to %d , can to send establish req "); +577536,1183244288,0,0,PS1,CESM,CesmProcCcmActEpsBrCtxReqSig_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , CCM act EPS bearer request , but ESM is suspended , pending "); +577536,1183246336,0,0,PS1,CESM,CesmProcCcmDelEpsBrCtxReqSig_none_1,P_VALUE,swLogPrintf("CESM , no BR find via cid : %d , BR delete OK "); +577536,1183248384,0,0,PS1,CESM,CesmProcCcmDelEpsBrCtxReqSig_ded_w_1,P_WARNING,swLogPrintf("CESM , delete default cid : %d , BR is dedicated , can ' t delete , but still CNF OK "); +577536,1183250688,0,0,PS1,CESM,CesmProcCcmDelEpsBrCtxReqSig_brState_1,P_WARNING,swLogPrintf("CESM , cid : %d , BR state : %e , not allow to delete "); +577536,1183252480,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_none_1,P_VALUE,swLogPrintf("CESM , deact EPS BR , BR not found via cid : %d "); +577536,1183254784,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_brState_1,P_VALUE,swLogPrintf("CESM , cid : %d , CCM deact BR , brState : %e "); +577536,1183256832,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_brState_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , CCM deact BR , while brState : %e "); +577536,1183258624,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_brState_w_2,P_WARNING,swLogPrintf("CESM , cid : %d , CCM deact BR , while brState : CESM_BR_CTX_ATTACH_ACT_PENDING , not allow to deact "); +577536,1183260928,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_brState_w_3,P_WARNING,swLogPrintf("CESM , cid : %d , CCM deact BR , while brState : %d , abnormal , local deact "); +577536,1183262720,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_last_br_1,P_WARNING,swLogPrintf("CESM , cid : %d , CCM deact BR , last default EPS bearer , not allow to deact "); +577536,1183265024,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_brState_w_4,P_WARNING,swLogPrintf("CESM , cid : %d , CCM deact BR , while brState : %d , local deact firstly "); +577536,1183266816,0,0,PS1,CESM,CesmProcCcmDeactEpsBrCtxReqSig_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , CCM deact BR , but ESM is suspended , pending "); +577536,1183268864,0,0,PS1,CESM,CesmProcCcmModifyEpsBrCtxReqSig_no_br_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , can ' t find EPS BR , can ' t MO modify "); +577536,1183270912,0,0,PS1,CESM,CesmProcCcmModifyEpsBrCtxReqSig_brState_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , already under MO modification , return "); +577536,1183273216,0,0,PS1,CESM,CesmProcCcmModifyEpsBrCtxReqSig_brState_w_2,P_WARNING,swLogPrintf("CESM , CID : %d , brState : %d , can ' t MO modify "); +577536,1183275008,0,0,PS1,CESM,CesmProcCcmModifyEpsBrCtxReqSig_param_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , no TFA / EQOS set , can ' t MO modify "); +577536,1183277312,0,0,PS1,CESM,CesmProcCcmModifyEpsBrCtxReqSig_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , EBI : %d , MO modify , but ESM is suspended , pending "); +577536,1183279360,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_cid_w_1,P_WARNING,swLogPrintf("CESM , invalid CID : %d / pCid : %d , can ' t define dedicated PDP "); +577536,1183281920,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_linkeps_w_1,P_WARNING,swLogPrintf("CESM , can ' t define dedicated PDP cid : %d , linked CID : %d not exist : 0x%x , or not default PDP : %d , or not activated "); +577536,1183283456,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_def_w_1,P_WARNING,swLogPrintf("CESM , can ' t define dedicated PDP cid : %d , cid already allc for default bearer , and brState : %d "); +577536,1183285248,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_def_w_2,P_WARNING,swLogPrintf("CESM , define dedicated PDP cid : %d , cid already allc for default bearer , delete default bearer context "); +577536,1183287552,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_dup_w_2,P_WARNING,swLogPrintf("CESM , define dedicated PDP cid : %d , already exist , and brState : %d , not allow to define "); +577536,1183289344,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_e_1,P_ERROR,swLogPrintf("CESM , define dedicated PDP cid : %d , BR should not exist "); +577536,1183291392,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_basic_w_1,P_WARNING,swLogPrintf("CESM , define dedicated PDP cid : %d , can ' t alloc basic info "); +577536,1183293440,0,0,PS1,CESM,CesmProcCcmSetDedEpsBrCtxReqSig_basic_e_1,P_ERROR,swLogPrintf("CESM , define dedicated PDP cid : %d , but BR basic context already exist , abnormal "); +577536,1183295488,0,0,PS1,CESM,CesmProcCcmDelDedEpsBrCtxReqSig_no_eps_1,P_VALUE,swLogPrintf("CESM , can ' t find BR via cid : %d , delete dedicated BR OK "); +577536,1183297536,0,0,PS1,CESM,CesmProcCcmDelDedEpsBrCtxReqSig_def_eps_1,P_WARNING,swLogPrintf("CESM , cid : %d is default BR , can ' t delete dedicated BR , but here confirm OK "); +577536,1183299840,0,0,PS1,CESM,CesmProcCcmDelDedEpsBrCtxReqSig_brState_w_1,P_WARNING,swLogPrintf("CESM , cid : %d brState : %e , can ' t delete dedicated BR "); +577536,1183301632,0,0,PS1,CESM,CesmProcCcmDefineTFTParamReqSig_cid_w_1,P_WARNING,swLogPrintf("CESM , cid : %d BR not found / defined , can ' t set TFT "); +577536,1183303680,0,0,PS1,CESM,CesmProcCcmDelTFTParamReqSig_cid_v_1,P_VALUE,swLogPrintf("CESM , cid : %d , delete TFT , but BR not found "); +577536,1183305728,0,0,PS1,CESM,CesmProcCcmDefineEpsQosReqSig_no_eps_w_1,P_WARNING,swLogPrintf("CESM , can ' t find BR via CID : %d , can ' t define EPS QOS "); +577536,1183307776,0,0,PS1,CESM,CesmProcCcmDefineEpsQosReqSig_no_mem_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , no mem left , can ' t define EPS QOS "); +577536,1183309824,0,0,PS1,CESM,CesmProcCcmDelEpsQosReqSig_no_eps_1,P_VALUE,swLogPrintf("CESM , can ' t find BR via CID : %d , or no EPS QOS defined , when del EPS QOS "); +577536,1183313919,0,0,PS1,CESM,CesmProcCcmSetAttachBrCtxReqSig_w_1,P_WARNING,swLogPrintf("CESM , AT+ECATTBEARER is not support anymore , please try : AT+CGDCONT to define the attach bearer context "); +577536,1183315967,0,0,PS1,CESM,CesmProcCcmGetAttachBrCtxReqSig_w_1,P_WARNING,swLogPrintf("CESM , AT+ECATTBEARER is not support anymore , please try : AT+CGDCONT to read the attach bearer context "); +577536,1183316224,0,0,PS1,CESM,CesmProcCcmSetMtCpDataReportCfgReqSig_s_1,P_SIG,swLogPrintf("CESM , try set CRTDCP : %d , atSrcHandler : 0x%x "); +577536,1183318784,0,0,PS1,CESM,CesmProcCcmSetDefineAuthReqSig_param_w_1,P_WARNING,swLogPrintf("CESM , invalid CID : %d , or authType : %d , or userIdLen : %d , or pwdLen : %d in CcmCesmSetDefineAuthReq "); +577536,1183320064,0,0,PS1,CESM,CesmProcCcmSetDefineAuthReqSig_def_1,P_WARNING,swLogPrintf("CESM , cid : %d , not defined , can ' t set AUTH info , please try AT+CGDCONT to define the PDP firstly "); +577536,1183322112,0,0,PS1,CESM,CesmProcCcmSetDefineAuthReqSig_ded_1,P_WARNING,swLogPrintf("CESM , cid : %d , dedicated bearer , not support to set AUTH info "); +577536,1183324160,0,0,PS1,CESM,CesmProcCcmSetDefineAuthReqSig_same_1,P_INFO,swLogPrintf("CESM , cid : %d , set auth info , nothing need update "); +577536,1183326464,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_w_1,P_WARNING,swLogPrintf("CESM , recv CcmCesmAbortMoProcReq , abortProc : %d , abortCid : %d , but BR not found "); +577536,1183328768,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_s_1,P_SIG,swLogPrintf("CESM , cid : %d , brState : %d , abort moProc : %d "); +577536,1183330560,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_react_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , react BR , new BR already acted EBI : %d , local deact old BR "); +577536,1183332352,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_react_w_2,P_WARNING,swLogPrintf("CESM , cid : %d , react BR , new BR not acted , local deact new BR "); +577536,1183334656,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_act_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , abort MO act request , but BR already acted : %d , remain "); +577536,1183336704,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_deact_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , abort MO deact request , but BR state : %d "); +577536,1183338752,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_mod_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , abort MO modify request , but BR state : %d , not right , for safe , local deact this BR "); +577536,1183340800,0,0,PS1,CESM,CesmProcCcmAbortMoProcReqSig_proc_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , abort invalid / known MO proc : %d "); +577536,1183343616,0,0,PS1,CESM,CesmProcUlDataTransReqSig_w_in_1,P_WARNING,swLogPrintf("CESM , CesmUlDataTransReq , invalid input ebi : %d , pHdr : 0x%x , pTailer : 0x%x , pTailer->pNext : 0x%x , pTailer->bCont : %d "); +577536,1183345152,0,0,PS1,CESM,CesmProcUlDataTransReqSig_E_1,P_ERROR,swLogPrintf("CESM , ebi : %d , CAT1 not support CP CIOT , UE OPT : %d , NW OPT : %d , can ' t Tx user data , free all "); +577536,1183346688,0,0,PS1,CESM,CesmProcUlDataTransReqSig_E_2,P_ERROR,swLogPrintf("CESM , ebi : %d not found , can ' t Tx user data , free all "); +577536,1183349248,0,0,PS1,CESM,CesmHandleT3480Expiry_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3480 expiry , brState : %d not right , or not dedicated beerer : %d , abnormal "); +577536,1183350784,0,0,PS1,CESM,CesmHandleT3480Expiry_timer_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3480 expiry , but guard timer not created "); +577536,1183353088,0,0,PS1,CESM,CesmHandleT3480Expiry_fifth_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3480 expiry , total try : %d times , reject / deact "); +577536,1183354880,0,0,PS1,CESM,CesmHandleT3480Expiry_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , retry MO act dedicated EPS bearer , but ESM is suspended , pending "); +577536,1183356928,0,0,PS1,CESM,CesmHandleT3481Expiry_timer_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3481 expiry , but guard timer not created "); +577536,1183359488,0,0,PS1,CESM,CesmHandleT3481Expiry_fifth_1,P_WARNING,swLogPrintf("CESM , cid : %d , ebi : %d , T3481 expiry , total try : %d times , deact dedicated BR "); +577536,1183361536,0,0,PS1,CESM,CesmHandleT3481Expiry_fifth_2,P_WARNING,swLogPrintf("CESM , cid : %d , ebi : %d , T3481 expiry , total try : %d times , MO modify fail , back to ACT state "); +577536,1183363072,0,0,PS1,CESM,CesmHandleT3481Expiry_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , retry MO modify / deact EPS bearer , but ESM is suspended , pending "); +577536,1183365632,0,0,PS1,CESM,CesmHandleT3482Expiry_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3482 expiry , brState : %d not right , or not default beerer : %d , abnormal "); +577536,1183367168,0,0,PS1,CESM,CesmHandleT3482Expiry_timer_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3482 expiry , but guard timer not created "); +577536,1183369728,0,0,PS1,CESM,CesmHandleT3482Expiry_fifth_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3482 expiry , has try : %d times , max retry : %d , reject / deact "); +577536,1183371264,0,0,PS1,CESM,CesmHandleT3482Expiry_suspend_s_1,P_SIG,swLogPrintf("CESM , CID : %d , retry MO act default EPS bearer , but ESM is suspended , pending "); +577536,1183373824,0,0,PS1,CESM,CesmHandleT3492Expiry_invalid_0,P_WARNING,swLogPrintf("CESM , cid : %d , T3492 expiry , brState : %d not right , or not default beerer : %d , abnormal "); +577536,1183375360,0,0,PS1,CESM,CesmHandleT3492Expiry_invalid_1,P_WARNING,swLogPrintf("CESM , cid : %d , T3482 expiry , but guard timer not created "); +577536,1183377920,0,0,PS1,CESM,CesmHandleT3492Expiry_invalid_2,P_WARNING,swLogPrintf("CESM , cid : %d , T3492 expiry , has try : %d times , max retry : %d , local deact "); +577536,1183379456,0,0,PS1,CESM,CesmHandleT3492Expiry_invalid_3,P_WARNING,swLogPrintf("CESM , CID : %d , retry MO act default EPS bearer , but ESM is suspended , pending "); +577536,1183383551,0,0,PS1,CESM,CesmHandleUlDataRetryTimerExpiry_w_1,P_WARNING,swLogPrintf("CESM , UL_DATA_RETRY_TIMER expiry , but timer not created or stop "); +577536,1183383552,0,0,PS1,CESM,CesmStartBrTimer_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , guard timer already created / start , need to restart "); +577536,1183386112,0,0,PS1,CESM,CesmStartBrTimer_s_1,P_SIG,swLogPrintf("CESM , cid : %d , start BR timer : %d , ms : %d "); +577536,1183387648,0,0,PS1,CESM,CesmTimerExpiry_s_1,P_SIG,swLogPrintf("CESM , Timer expiry , Tid : 0x%x "); +577536,1183389952,0,0,PS1,CESM,CesmTimerExpiry_no_eps_1,P_WARNING,swLogPrintf("CESM , BR timer : %d expiry , can ' t find BR via CID : %d "); +577536,1183392000,0,0,PS1,CESM,CesmTimerExpiry_brState_w_1,P_WARNING,swLogPrintf("CESM , BR timer : 0x%x expiry , but brState : %d , abnormal "); +577536,1183394048,0,0,PS1,CESM,CesmTimerExpiry_brTimer_w_1,P_WARNING,swLogPrintf("CESM , BR timer : 0x%x expiry , invalid BrTid : %d , abnormal "); +577536,1183396096,0,0,PS1,CESM,CesmFreeEpsBrCtx_react_s_1,P_SIG,swLogPrintf("CESM , free re-act BR context , EBI : %d , CID : %d "); +577536,1183398144,0,0,PS1,CESM,CesmFreeEpsBrCtx_s_1,P_SIG,swLogPrintf("CESM , free BR context , EBI : %d , CID : %d "); +577536,1183400192,0,0,PS1,CESM,CesmFreeEpsBrCtx_timer_1,P_VALUE,swLogPrintf("CESM , EBI : %d , CID : %d , when free BR context , guardtimer is still runing "); +577536,1183401984,0,0,PS1,CESM,CesmSaveDefEpsBearerDefinition_del_1,P_VALUE,swLogPrintf("CESM , delete default bearer definition , cid : %d "); +577536,1183404032,0,0,PS1,CESM,CesmSaveDefEpsBearerDefinition_update_1,P_VALUE,swLogPrintf("CESM , set / update default bearer definition , cid : %d "); +577536,1183406080,0,0,PS1,CESM,CesmSaveEpsBrAuthDefinition_del_1,P_VALUE,swLogPrintf("CESM , delete bearer AUTH definition , cid : %d "); +577536,1183408128,0,0,PS1,CESM,CesmSaveEpsBrAuthDefinition_update_1,P_VALUE,swLogPrintf("CESM , set / update bearer AUTH definition , cid : %d "); +577536,1183410176,0,0,PS1,CESM,CesmInitialise_auth_w_1,P_WARNING,swLogPrintf("CESM , init / wakeup , CID : %d , PDP not defined , but has AUTH info , delete AUTH info "); +577536,1183412736,0,0,PS1,CESM,CesmInitialise_s_1,P_SIG,swLogPrintf("CESM , init / wakeup , CID : %d , bDedicated : %d , brState : %e "); +577536,1183414784,0,0,PS1,CESM,CesmProcOut_proc_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , proc state : %e , not allow sleep2 / HIB "); +577536,1183416832,0,0,PS1,CESM,CesmProcOut_tiny_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , basic ctx store to tiny mem , index : %d "); +577536,1183418624,0,0,PS1,CESM,CesmProcOut_bs_slp2_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , basic context using sleep2 mem "); +577536,1183420672,0,0,PS1,CESM,CesmProcOut_ded_tft_slp2_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , dedicated bearer , more TFT configed , using sleep2 mem "); +577536,1183422720,0,0,PS1,CESM,CesmProcOut_def_tft_slp2_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , default bearer , more TFT configed , using sleep2 mem "); +577536,1183424768,0,0,PS1,CESM,CesmProcOut_tft_slp2_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , TFA configed by user , using sleep2 mem "); +577536,1183426816,0,0,PS1,CESM,CesmProcOut_qos_slp2_1,P_VALUE,swLogPrintf("CESM , EPSID : %d , CID : %d , EPS QOS configed by user , using sleep2 mem "); +577536,1183430655,0,0,PS1,CESM,CesmProcOut_acl_slp1_1,P_VALUE,swLogPrintf("CESM , sim configured ACL enable , should vote to SLEEP2 "); +577536,1183431168,0,0,PS1,CESM,CesmProcOut_react_1,P_WARNING,swLogPrintf("CESM , allow slp : %d , but re-act BR exist , cid : %d , brState : %d , not allow deep SLP "); +577536,1183434751,0,0,PS1,CESM,CesmProcOut_idle_1,P_VALUE,swLogPrintf("CESM , not allow sleep2 , or HIB "); +577536,1183436799,0,0,PS1,CESM,CesmProcOut_slp2_1,P_VALUE,swLogPrintf("CESM , vote sleep2 "); +577536,1183438847,0,0,PS1,CESM,CesmProcOut_hib_1,P_VALUE,swLogPrintf("CESM , vote HIB "); +577536,1183439360,0,0,PS1,CESM,CesmProcOut_hib_tiny_1,P_VALUE,swLogPrintf("CESM , CID : %d , EPSID : %d , be dedicated : %d , update tiny "); +577536,1183441152,0,0,PS1,CESM,CesmProcOut_hib_tiny_2,P_VALUE,swLogPrintf("CESM , CID : %d , EPSID : %d , basic context changed , update tiny "); +577536,1183442944,0,0,PS1,CESM,CesmAllocPti_0,P_INFO,swLogPrintf("CESM , return last pti : %d "); +577536,1183444992,0,0,PS1,CESM,CesmAllocPti_1,P_INFO,swLogPrintf("CESM , allocate pti : %d "); +577536,1183449087,0,0,PS1,CESM,CesmBeEpco_epco_1,P_VALUE,swLogPrintf("CESM , UE config ePCO , but NW not support ePCO , set to PCO "); +577536,1183451135,0,0,PS1,CESM,CesmCopyBrBasic_mem_w_1,P_WARNING,swLogPrintf("CESM , no slp2 memory left for TFT packet filter , can ' t copy "); +577536,1183451392,0,0,PS1,CESM,CesmBrMoProcDone_w_1,P_WARNING,swLogPrintf("CESM , cid : %d , MO proc done , but brState : %d , not right "); +577536,1183453440,0,0,PS1,CESM,CesmFindBrCtxViaPti_react_1,P_VALUE,swLogPrintf("CESM , Re-act EPS BR ( CID : %d ) found via pti = %d "); +577536,1183455232,0,0,PS1,CESM,CesmFindBrCtxViaPti_w_1,P_WARNING,swLogPrintf("CESM , cannot find the bearer context! , pti = %d "); +577536,1183457536,0,0,PS1,CESM,CesmFindBrCtxViaEbi_react_1,P_VALUE,swLogPrintf("CESM , Re-act EPS BR ( CID : %d ) found via ebi = %d "); +577536,1183459328,0,0,PS1,CESM,CesmFindBrCtxViaEbi_w_1,P_VALUE,swLogPrintf("CESM , cannot find the bearer context , ebi = %d "); +577536,1183461376,0,0,PS1,CESM,CesmFindBrCtxViaCid_w_1,P_VALUE,swLogPrintf("CESM , cannot find the bearer context! , cid = %d "); +577536,1183463424,0,0,PS1,CESM,CesmFindUnusedCid_v_1,P_VALUE,swLogPrintf("CESM , find an unused cid : %d "); +577536,1183465472,0,0,PS1,CESM,CesmFindUnusedCid_v_2,P_VALUE,swLogPrintf("CESM , find an unused cid : %d "); +577536,1183469567,0,0,PS1,CESM,CesmFindUnusedCid_w_1,P_WARNING,swLogPrintf("CESM , can ' t find unused cid "); +577536,1183469824,0,0,PS1,CESM,CesmFindActedPFilterViaPfId_in_w_1,P_WARNING,swLogPrintf("CESM , can ' t find pfId , invalid EPSBR : 0x%lx , or pfId : %d "); +577536,1183472128,0,0,PS1,CESM,CesmFindActedPFilterViaPfId_in_w_2,P_WARNING,swLogPrintf("CESM , CID : %d , brState : %d , no basic BR ctx , can ' t find pfId : %d "); +577536,1183473664,0,0,PS1,CESM,CesmGetDefBrCmiIpAddr_ipv4_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , IPV4 PDN , but all zero ipv4 addr "); +577536,1183475712,0,0,PS1,CESM,CesmGetDefBrCmiIpAddr_ipv4v6_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , IPV4V6 PDN , but all zero ipv4 addr "); +577536,1183477760,0,0,PS1,CESM,CesmGetDefBrCmiIpAddr_ipv6_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , IPV6 PDN , but all zero ipv6 ID "); +577536,1183479808,0,0,PS1,CESM,CesmAllocEpsBrCtx_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , alloc EPS bearer , but EPS bearer already exist "); +577536,1183481856,0,0,PS1,CESM,CesmAllocEpsBrCtx_e_1,P_ERROR,swLogPrintf("CESM , cannot alloc EPS bearer for cid : %d , as ASMB mem limited "); +577536,1183484160,0,0,PS1,CESM,CesmAllocEpsBrBasicCtx_w_1,P_WARNING,swLogPrintf("CESM , more EPS basic bearer created : %d , try alloc from ASMB for cid : %d "); +577536,1183485952,0,0,PS1,CESM,CesmAllocEpsBrBasicCtx_e_1,P_ERROR,swLogPrintf("CESM , CID : %d , EPS basic bearer alloc fail in ASMB "); +577536,1183488512,0,0,PS1,CESM,CesmUpdateEpsBrCtxState_s_1,P_SIG,swLogPrintf("CESM , EPS CID : %d , change state from : %e to %e "); +577536,1183490560,0,0,PS1,CESM,CesmLocalDeactEpsBr_ded_1,P_SIG,swLogPrintf("CESM , dedicated BR cid : %d , ebi : %d local deact , as linked default BR : %d deact "); +577536,1183492352,0,0,PS1,CESM,CesmLocalDeactEpsBr_react_1,P_VALUE,swLogPrintf("CESM , EPS ID : %d , CID : %d , BR re-act , old BR local deactivated "); +577536,1183494400,0,0,PS1,CESM,CesmLocalDeactEpsBr_deact_old_1,P_VALUE,swLogPrintf("CESM , EPS ID : %d , CID : %d , BR re-act , old BR MO deact "); +577536,1183496704,0,0,PS1,CESM,CesmLocalDeactEpsBr_w_1,P_WARNING,swLogPrintf("CESM , EPS ID : %d , CID : %d , invalid BR state : %d , when local deact "); +577536,1183498752,0,0,PS1,CESM,CesmLocalDeactEpsBr_react_w_1,P_WARNING,swLogPrintf("CESM , CID : %d , re-act new BR deacted , but old BR also deacted : 0x%lx , %d "); +577536,1183500544,0,0,PS1,CESM,CesmGetFullIpv6AddrFromNetif_1,P_VALUE,swLogPrintf("CESM , CID : %d , netif can ' t get full ipv6 addr with cause : %d "); +577536,1183502336,0,0,PS1,CESM,CesmCheckDedEpsBrCtxBeforeMoAct_ded_bs_w_1,P_WARNING,swLogPrintf("CESM , dedicated cid : %d , no context info , can ' t act dedicated BR "); +577536,1183505408,0,0,PS1,CESM,CesmCheckDedEpsBrCtxBeforeMoAct_ded_bs_w_2,P_WARNING,swLogPrintf("CESM , dedicated cid : %d , linked BR cid : %d not found : 0x%lx , or not acted : %d / %d , can ' t act dedicated BR "); +577536,1183506688,0,0,PS1,CESM,CesmConstructUlPcoAttrInfo_iptype_w_1,P_WARNING,swLogPrintf("CESM , invalid ipType : %d , set for CID : %d , change to IPV4 "); +577536,1183508992,0,0,PS1,CESM,CesmConstructUlPcoAttrInfo_alloType_1,P_WARNING,swLogPrintf("CESM , EPS CID : %d , ipType : %d , not ipv4 , but request ipv4AlloType : %d , ignore "); +577536,1183510528,0,0,PS1,CESM,CesmConstructUlPcoAttrInfo_sec_s_1,P_SIG,swLogPrintf("CESM , EPS CID : %d , CHAP failed , try PAP "); +577536,1183513088,0,0,PS1,CESM,CesmConstructUlPcoAttrInfo_sec_w_1,P_WARNING,swLogPrintf("CESM , EPS CID : %d , request PAP , but nameLen : %d , or pwdLen : %d , not right , still carried "); +577536,1183515136,0,0,PS1,CESM,CesmConstructUlPcoAttrInfo_sec_w_2,P_WARNING,swLogPrintf("CESM , EPS CID : %d , request CHAP / PAP , but nameLen : %d , or pwdLen : %d , not right , still carried "); +577536,1183516672,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_pti_1,P_VALUE,swLogPrintf("CESM , MO BR ACT , retx PDN_CONNECTIVITY_REQUEST , re-use old pti : %d "); +577536,1183518976,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_iptype_w_1,P_WARNING,swLogPrintf("CESM , construct : PDN_CONNECTIVITY_REQUEST , invalid ipType : %d , set for CID : %d , change to IPV4 "); +577536,1183520768,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_reqtype_1,P_VALUE,swLogPrintf("CESM , EPS CID : %d , request emergency bearer "); +577536,1183523072,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_reqtype_w_1,P_WARNING,swLogPrintf("CESM , EPS CID : %d , invalid reqType : %d configed , change to normal "); +577536,1183524865,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_att_v_1,P_VALUE,swLogPrintf("CESM , save attach req APN : %s into tiny "); +577536,1183528959,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_att_v_2,P_VALUE,swLogPrintf("CESM , attach req APN is NULL , save into tiny "); +577536,1183529216,0,0,PS1,CESM,CesmConstructPDNConnectivityRequest_eitf_1,P_VALUE,swLogPrintf("CESM , EPS CID : %d , PDN_CONNECTIVITY_REQUEST eitf : %d , not set PCO "); +577536,1183531008,0,0,PS1,CESM,CesmSetEpcoFlag_s_1,P_SIG,swLogPrintf("CESM , bEpco flag set to : %d "); +577536,1183533056,0,0,PS1,CESM,CesmSetAttachEpsCid_s_1,P_SIG,swLogPrintf("CESM , attach CID try set to : %d "); +577536,1183536128,0,0,PS1,CESM,CesmSetUserDefinedTimer_s_1,P_SIG,swLogPrintf("CESM , user config T : %d , tryNumPresent : %d , tryNum : %d , tValPresent : %d , tValSec : %d "); +577536,1183537408,0,0,PS1,CESM,CesmSetUserDefinedTimer_w_1,P_WARNING,swLogPrintf("CESM , user config T : %d , tryNum : %d , not valid "); +577536,1183539456,0,0,PS1,CESM,CesmSetUserDefinedTimer_w_2,P_WARNING,swLogPrintf("CESM , user config T : %d , tValSec : %d , not valid "); +577536,1183541504,0,0,PS1,CESM,CesmGetNSLPIWithSimConfig_0,P_VALUE,swLogPrintf("CESM , overrideNasSignallingPriority : %d , nasSignallingPriority : %d in SIM "); +577536,1183543552,0,0,PS1,CESM,CesmGetNSLPIWithSimConfig_result,P_VALUE,swLogPrintf("CESM , result , nslpiPresent : %d , nslpiVal : %d "); +577536,1183545344,0,0,PS1,CESM,CesmSetAclFlag_write_1,P_SIG,swLogPrintf("CESM , set ACL val to : %d "); +577536,1183547392,0,0,PS1,CESM,CesmSetPdpRemapFlagFromNv_w_1,P_WARNING,swLogPrintf("CESM , invalid bPdpRemap val : %d in NVM "); +577536,1183549440,0,0,PS1,CESM,CesmSetPdpRemapFlag_write_1,P_SIG,swLogPrintf("CESM , try set pdpRemap to : %d "); +577536,1183551488,0,0,PS1,CESM,CesmSetPdpReactFlagFromNv_w_1,P_WARNING,swLogPrintf("CESM , invalid bPdpReact val : %d in NVM "); +577536,1183553536,0,0,PS1,CESM,CesmSetPdpReactFlag_write_1,P_SIG,swLogPrintf("CESM , try set bPdpReact to : %d "); +577536,1183557631,0,0,PS1,CESM,CesmFindApnWithAclConfig_result,P_SIG,swLogPrintf("CESM , no find apn in acl , should forbidden it "); +577536,1183557632,0,0,PS1,CESM,CesmCheckSendPdnConReqByAclApn_0,P_SIG,swLogPrintf("CESM , check send pdn apn with ACL result : %d ( 0 : Forbidden , 1 , Allow ) "); +577536,1183559680,0,0,PS1,CESM,CesmConvertCmiTftToPFFormat_netmask_1,P_WARNING,swLogPrintf("CESM , subnet mask length : %d in TFT , ip address type is IPV4 "); +577536,1183561728,0,0,PS1,CESM,CesmConvertCmiTftToPFFormat_netmask_2,P_WARNING,swLogPrintf("CESM , subnet mask length : %d in TFT , ip address type is IPV6 "); +577536,1183564032,0,0,PS1,CESM,CesmConvertCmiTftToPFFormat_port_w_2,P_WARNING,swLogPrintf("CESM , invalid local port range : [ %d , %d ] in TFT setting "); +577536,1183566080,0,0,PS1,CESM,CesmConvertCmiTftToPFFormat_port_w_1,P_WARNING,swLogPrintf("CESM , invalid destination port range : [ %d , %d ] in TFT setting "); +577536,1183568131,0,0,PS1,CESM,CesmDisplayApnCmp_same_1,P_VALUE,swLogPrintf("CESM , APN : %s , and APN : %s , act as same APN "); +577536,1183569920,0,0,PS1,CESM,CesmMoReactEpsBrSucc_tfa_1,P_WARNING,swLogPrintf("CESM , re-act old BR CID : %d , Tfa should be already freed "); +577536,1183571968,0,0,PS1,CESM,CesmMoReactEpsBrSucc_eqos_1,P_WARNING,swLogPrintf("CESM , re-act old BR CID : %d , ReqTfa should be already freed "); +577536,1183574016,0,0,PS1,CESM,CesmMoReactEpsBrSucc_cgauth_1,P_WARNING,swLogPrintf("CESM , re-act old BR CID : %d , AUTH Req should be already freed "); +577536,1183576064,0,0,PS1,CESM,DecodePCO_1,P_ERROR,swLogPrintf("Unexpected content Length of APNRC in PCO decode , contentLength : %d "); +577536,1183578112,0,0,PS1,CESM,DecodePCO_2,P_ERROR,swLogPrintf("Unexpected content Length of additional APNRC in PCO decode , contentLength : %d "); +577536,1183580160,0,0,PS1,CESM,DecodeEPCO_1,P_ERROR,swLogPrintf("Unexpected content Length of APNRC in PCO decode , contentLength : %d "); +577536,1183582208,0,0,PS1,CESM,DecodeEPCO_2,P_ERROR,swLogPrintf("Unexpected content Length of additional APNRC in PCO decode , contentLength : %d "); +577536,1183584256,0,0,PS1,CESM,DecodeNasEsmMessage_len_w_1,P_WARNING,swLogPrintf("CESM , can ' t decode signalling with len : %d < 3 "); +577536,1183586304,0,0,PS1,CESM,DecodeNasEsmMessage_pd_w_1,P_WARNING,swLogPrintf("CESM , invalid DL ESM signalling , PD : %d , not for ESM "); +577536,1183590399,0,0,PS1,CESM,EncodeTFT_1,P_WARNING,swLogPrintf("unsupported remoteAddrSubnetMask type "); +577536,1183592447,0,0,PS1,CESM,EncodeTFT_2,P_WARNING,swLogPrintf("unsupported destPortRange type "); +577536,1183594495,0,0,PS1,CESM,EncodeTFT_3,P_WARNING,swLogPrintf("unsupported localPort type "); +577536,1183594496,0,0,PS1,CESM,EncodeTFT_5,P_WARNING,swLogPrintf("Encode TFT , unknown tftOpCode = %d "); +577536,1183598591,0,0,PS1,CESM,EncodeTFT_ebit_w_1,P_WARNING,swLogPrintf("Encode TFT , parameterlist does not support! "); +577536,1183598592,0,0,PS1,CESM,EncodeTFT_6,P_INFO,swLogPrintf("CESM , Encode TFT , len = %d "); +577536,1183602687,0,0,PS1,CESM,EncodeBearerResourceAllocReq_1,P_WARNING,swLogPrintf("tft not present but required in Alloc!! "); +577536,1183604735,0,0,PS1,CESM,EncodeBearerResourceModificationReq_1,P_WARNING,swLogPrintf("tft not present but required in Modificaion!! "); +578560,1184892928,0,0,PS1,SMS,CesmcbDecodeWarningType_1,P_WARNING,swLogPrintf("Reserved warningTypeValue : %d "); +578560,1184894976,0,0,PS1,SMS,CesmcbDecodeDCS_1,P_WARNING,swLogPrintf("unknown cb DCS value : %d "); +578560,1184897024,0,0,PS1,SMS,CesmcbDecodeDCS_2,P_WARNING,swLogPrintf("unknown reserved DCS value : %d "); +578560,1184899072,0,0,PS1,SMS,CesmcbDecodeDCS_3,P_WARNING,swLogPrintf("unknown cb reserved DCS value : %d "); +578560,1184901120,0,0,PS1,SMS,CesmcbDecodeDCS_4,P_WARNING,swLogPrintf("unknown DCS value : %d "); +578560,1184903424,0,0,PS1,SMS,CesmcbEtwsPrimDuplicateCheck_1,P_WARNING,swLogPrintf("duplicate check failed of prim Smcb with messageID : %d , serialNum : %d "); +578560,1184905216,0,0,PS1,SMS,cesmcbSendEtwsCmasData_1,P_WARNING,swLogPrintf("Invalid Smcb MessageType : %d "); +578560,1184907264,0,0,PS1,SMS,CemmSmscbMessageIdCheck_1,P_WARNING,swLogPrintf("Unexpected messageIdentifier %d received when UE is not on HPLMN / EHPLMN or PLMN equivalent to HPLMN / EHPLMN "); +578560,1184909568,0,0,PS1,SMS,CesmsProcSmscbCmasDataIndSig_1,P_WARNING,swLogPrintf("duplicate check failed of cmas Smcb with messageID : %d , serialNum : %d "); +578560,1184913407,0,0,PS1,SMS,CesmsProcSmscbCmasDataIndSig_2,P_WARNING,swLogPrintf("message ID check failed! "); +578560,1184913408,0,0,PS1,SMS,CesmsProcSmscbCmasDataIndSig_3,P_WARNING,swLogPrintf("Authentication is not finish when cmas data received isAuthenticated : %d "); +578560,1184917503,0,0,PS1,SMS,CesmsProcSmscbEtwsPrimaryDataIndSig_1,P_WARNING,swLogPrintf("Duplicate check failed of primary Smcb "); +578560,1184919551,0,0,PS1,SMS,CesmsProcSmscbEtwsPrimaryDataIndSig_2,P_WARNING,swLogPrintf("message ID check failed! "); +578560,1184921599,0,0,PS1,SMS,CesmsProcSmscbEtwsPrimaryDataIndSig_3,P_WARNING,swLogPrintf("Authentication is not finish when primary data is received "); +578560,1184921856,0,0,PS1,SMS,CesmsProcSmscbEtwsSecondDataIndSig_1,P_WARNING,swLogPrintf("duplicate check failed of secondary Smcb with messageID : %d , serialNum : %d "); +578560,1184925695,0,0,PS1,SMS,CesmsProcSmscbEtwsSecondDataIndSig_2,P_WARNING,swLogPrintf("message ID check failed! "); +578560,1184927743,0,0,PS1,SMS,CesmsProcSmscbEtwsSecondDataIndSig_3,P_WARNING,swLogPrintf("Authentication is not finish when secondary data is received "); +578560,1184929791,0,0,PS1,SMS,AllocateMtEntity_1,P_WARNING,swLogPrintf("MT entity allocated fail! "); +578560,1184929792,0,0,PS1,SMS,ReleaseSmcmEntity_1,P_VALUE,swLogPrintf("free Entitynum is : %d "); +578560,1184931840,0,0,PS1,SMS,ReleaseSmcmEntity_2,P_VALUE,swLogPrintf("free cp user data for Entitynum : %d "); +578560,1184933888,0,0,PS1,SMS,ReleaseSmcmEntity_3,P_VALUE,swLogPrintf("free Entitynum is : %d "); +578560,1184935936,0,0,PS1,SMS,ReleaseSmcmEntity_4,P_VALUE,swLogPrintf("free cp user data for Entitynum : %d "); +578560,1184938240,0,0,PS1,SMS,isInAvailEntity_1,P_VALUE,swLogPrintf("This entity %d is at %d "); +578560,1184940032,0,0,PS1,SMS,CesmcmDecodeRpMessageType_1,P_WARNING,swLogPrintf("rpduInfoLength %d is less than 2 "); +578560,1184942080,0,0,PS1,SMS,CesmcmDecodeRpMessageType_2,P_WARNING,swLogPrintf("RP message type %d is unexpected "); +578560,1184944128,0,0,PS1,SMS,CesmcmDecodeRpMessageType_3,P_WARNING,swLogPrintf("RP-Originator Address length %d is incorrect "); +578560,1184946176,0,0,PS1,SMS,CesmcmDecodeRpMessageType_4,P_WARNING,swLogPrintf("RP-Destination Address length %d is incorrect "); +578560,1184948224,0,0,PS1,SMS,CesmcmDecodeRpMessageType_5,P_WARNING,swLogPrintf("RP-User Data length %d is incorrect "); +578560,1184950272,0,0,PS1,SMS,CesmcmDecodeRpMessageType_6,P_WARNING,swLogPrintf("tpduInfoLength %d is less than 1 "); +578560,1184952320,0,0,PS1,SMS,GetTimerEnumBasedEtyNum_1,P_WARNING,swLogPrintf("Incorrect NAS SMS timer Type %d "); +578560,1184954368,0,0,PS1,SMS,ConstructCpMessage_1,P_VALUE,swLogPrintf("buildCpBodyType %d "); +578560,1184956416,0,0,PS1,SMS,ConstructCpMessage_2,P_WARNING,swLogPrintf("Unexpected SMS msgType %d "); +578560,1184960511,0,0,PS1,SMS,CesmscmFindEntity_2,P_WARNING,swLogPrintf("cp user data memory for establish request allocated failure "); +578560,1184962559,0,0,PS1,SMS,CesmscmFindEntity_3,P_WARNING,swLogPrintf("etyNo for establish request allocated failure "); +578560,1184964607,0,0,PS1,SMS,CesmscmFindEntity_4,P_WARNING,swLogPrintf("etyNo for data / rel / abort req can not be found "); +578560,1184966655,0,0,PS1,SMS,CesmscmFindEntity_5,P_WARNING,swLogPrintf("etyNo for timer expiry can not be found "); +578560,1184968703,0,0,PS1,SMS,CesmscmFindEntity_6,P_WARNING,swLogPrintf("etyNo for est cnf can not be found "); +578560,1184970751,0,0,PS1,SMS,CesmscmFindEntity_7,P_WARNING,swLogPrintf("etyNo for err ind can not be found "); +578560,1184972799,0,0,PS1,SMS,CesmscmFindEntity_8,P_WARNING,swLogPrintf("Message is received that is too short to contain a complete message type information element , ignore it! "); +578560,1184972800,0,0,PS1,SMS,CesmscmFindEntity_9,P_WARNING,swLogPrintf("Entity for MT SMS data ind can not be allocated : %d "); +578560,1184976895,0,0,PS1,SMS,CesmscmFindEntity_10,P_WARNING,swLogPrintf("Entity for MO SMS data ind can not be found "); +578560,1184976896,0,0,PS1,SMS,CesmscmFindEntity_11,P_WARNING,swLogPrintf("SMS header decode error code %d "); +578560,1184978944,0,0,PS1,SMS,CesmscmFindEntity_12,P_WARNING,swLogPrintf("unexpected etyMsgType %d "); +578560,1184980992,0,0,PS1,SMS,CesmsDecodeLoopbackData_1,P_WARNING,swLogPrintf("CesmsDecodeLoopbackData received SMS unknown message type : %d "); +578560,1184983296,0,0,PS1,SMS,CesmsDecodeLoopbackData_2,P_WARNING,swLogPrintf("CesmsDecodeLoopbackData incorrect pdu length for RP-Originator Address , offset : %d , smsLen : %d "); +578560,1184985344,0,0,PS1,SMS,CesmsDecodeLoopbackData_3,P_WARNING,swLogPrintf("CesmsDecodeLoopbackData incorrect pdu length for for RP-Destination Address , offset : %d , smsLen : %d "); +578560,1184987392,0,0,PS1,SMS,CesmsDecodeLoopbackData_4,P_WARNING,swLogPrintf("CesmsDecodeLoopbackData incorrect pdu length for RP-user data , offset : %d , smsLen : %d "); +578560,1184989184,0,0,PS1,SMS,CesmsDecodeLoopbackData_5,P_INFO,swLogPrintf("CesmsDecodeLoopbackData RP-user decoded mt userDat.tpduLen %d "); +578560,1184991232,0,0,PS1,SMS,CesmsDecodeLoopbackData_6,P_INFO,swLogPrintf("pSmtlDeliveredInd->smsLen %d "); +578560,1184993280,0,0,PS1,SMS,CeSmcmProcessMoEstReqData_1,P_WARNING,swLogPrintf("Received SMCM_EST_REQ for entity number : %d "); +578560,1184995328,0,0,PS1,SMS,CeSmcmProcessMoEstReqData_2,P_WARNING,swLogPrintf("UE failed to find entity context for entity number : %d est req "); +578560,1184997632,0,0,PS1,SMS,CeSmcmProcessMoEstReqData_3,P_WARNING,swLogPrintf("Received SMCM_EST_REQ for entity number : %d and smcm state is : %d "); +578560,1185001471,0,0,PS1,SMS,CeSmcmProcessMoEstReqData_5,P_WARNING,swLogPrintf("Received SMCM_EST_REQ when SMS is suspended by EMM "); +578560,1185001728,0,0,PS1,SMS,CeSmcmProcessMoEstReqData_6,P_WARNING,swLogPrintf("Received SMCM_EST_REQ in unexpected SMCM state : %d ; for entity number : %d "); +578560,1185003520,0,0,PS1,SMS,CemmSmcmHandleAbortReq_1,P_WARNING,swLogPrintf("UE fail to find entity context for entity number : %d! "); +578560,1185005568,0,0,PS1,SMS,CemmSmcmHandleAbortReq_2,P_WARNING,swLogPrintf("Handle SMRL abort request under state %d! "); +578560,1185007616,0,0,PS1,SMS,CemmSmcmHandleAbortReq_3,P_INFO,swLogPrintf("SMCM state transfer to IDLE state from state : %d "); +578560,1185009664,0,0,PS1,SMS,CemmSmcmHandleRelReq_1,P_WARNING,swLogPrintf("UE fail to find entity context for entity number : %d! "); +578560,1185012480,0,0,PS1,SMS,CemmSmcmHandleRelReq_2,P_VALUE,swLogPrintf("ProcessSmcmRelReq entityNum %d ; Delay sendCpAck %d , TI_Flag : %d , TI_Value : %d "); +578560,1185014016,0,0,PS1,SMS,CemmSmcmHandleRelReq_3,P_VALUE,swLogPrintf("ProcessSmcmRelReq entityNum %d ; sendCpAck %d "); +578560,1185017855,0,0,PS1,SMS,CemmSmcmHandleRelReq_4,P_VALUE,swLogPrintf("sending ack "); +578560,1185017856,0,0,PS1,SMS,CemmSmcmHandleRelReq_5,P_INFO,swLogPrintf("smcm state : %d transfer to idle "); +578560,1185020160,0,0,PS1,SMS,CemmSmcmHandleRelReq_6,P_WARNING,swLogPrintf("Received SMCM_REL_REQ in SMCM state : %d ; for entity number : %d with relpendingornot true "); +578560,1185022720,0,0,PS1,SMS,CemmSmcmHandleRelReq_7,P_VALUE,swLogPrintf("ProcessSmcmRelReq entityNum %d ; send Delay CpAck %d , Ti_Flag : %d , Ti_value : %d "); +578560,1185024256,0,0,PS1,SMS,CemmSmcmHandleRelReq_8,P_WARNING,swLogPrintf("Received SMCM_REL_REQ in unexpected SMCM state : %d ; for entity number : %d "); +578560,1185026048,0,0,PS1,SMS,CemmSmcmHandleDataReq_1,P_WARNING,swLogPrintf("UE fail to find entity context for entity number : %d "); +578560,1185028352,0,0,PS1,SMS,CemmSmcmHandleDataReq_2,P_WARNING,swLogPrintf("Received SMCM_DATA_REQ in unexpected SMCM state : %d ; for entity number : %d "); +578560,1185032191,0,0,PS1,SMS,CeSmcmSendEmmSmsUnitDataReq_1,P_INFO,swLogPrintf("CP_DATA is sent "); +578560,1185034239,0,0,PS1,SMS,CeSmcmSendEmmSmsUnitDataReq_2,P_INFO,swLogPrintf("CP_ERROR is sent "); +578560,1185036287,0,0,PS1,SMS,CeSmcmSendEmmSmsUnitDataReq_3,P_INFO,swLogPrintf("CP_ACK is sent "); +578560,1185036288,0,0,PS1,SMS,CeSmcmSendEmmSmsUnitDataReq_4,P_WARNING,swLogPrintf("Unexpected messageType : %d "); +578560,1185038592,0,0,PS1,SMS,CeSmcmSendEmmRelReq_1,P_INFO,swLogPrintf("SMCM send release request for TI value : %d ; TI flag : %d "); +578560,1185040640,0,0,PS1,SMS,CeSmcmSendSmcmErrInd_1,P_INFO,swLogPrintf("SMCM send ERR IND for etyNo : %d ; cause : %d "); +578560,1185044479,0,0,PS1,SMS,CeSmsUlConsLoopbackPduForUpData_1,P_WARNING,swLogPrintf("LoopbackData can not be decoded successfully "); +578560,1185046527,0,0,PS1,SMS,CeSmsUlSendLoopDataReq_1,P_WARNING,swLogPrintf("LoopbackData can not be contructed successfully "); +578560,1185046528,0,0,PS1,SMS,CemmSmsProcEstCnfMsg_1,P_WARNING,swLogPrintf("UE failed to find entity context for entity number : %d est confirm "); +578560,1185048576,0,0,PS1,SMS,CemmSmsProcEstCnfMsg_2,P_INFO,swLogPrintf("Received CEMM_SMS_EST_CNF for TI : %d "); +578560,1185050880,0,0,PS1,SMS,CemmSmsProcEstCnfMsg_3,P_WARNING,swLogPrintf("Received CEMM_SMS_EST_CNF in unexpected SMCM state : %d ; for entity number : %d "); +578560,1185052928,0,0,PS1,SMS,CemmSmsProcErrorIndMsg_1,P_INFO,swLogPrintf("SMCM state : %d transfer to idle state for etynum : %d "); +578560,1185054976,0,0,PS1,SMS,CemmSmsProcErrorIndMsg_2,P_INFO,swLogPrintf("SMCM state : %d receive error ind with cause fail_normal_cause for etynum : %d "); +578560,1185056768,0,0,PS1,SMS,CemmSmsProcErrorIndMsg_3,P_INFO,swLogPrintf("clear cp data info for etynum : %d "); +578560,1185058816,0,0,PS1,SMS,CemmSmsProcErrorIndMsg_4,P_WARNING,swLogPrintf("CESMS received ERROR ind , but no entity %d found "); +578560,1185060864,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_1,P_ERROR,swLogPrintf("UE fail to find correct smcm entity context : %d for sms_data_ind "); +578560,1185064959,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_2,P_WARNING,swLogPrintf("Message is received that is too short to contain a complete message type information element , ignore it! "); +578560,1185064960,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_3,P_WARNING,swLogPrintf("MT SMS data message decode error %d "); +578560,1185067008,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_4,P_WARNING,swLogPrintf("MT SMS data header decode error %d "); +578560,1185069056,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_5,P_WARNING,swLogPrintf("MT SMS data message decode error %d "); +578560,1185073151,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_6,P_WARNING,swLogPrintf("Message is received with TI value ' 111 ' , ignore it! "); +578560,1185073408,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_7,P_INFO,swLogPrintf("SMCM state : %d transfer to idle state for etynum : %d "); +578560,1185075200,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_8,P_INFO,swLogPrintf("SMCM state : SMCM2_WAIT_FOR_CP_ACK transfer to SMCM0_IDLE for etynum : %d after CP ACK received "); +578560,1185077248,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_9,P_WARNING,swLogPrintf("CP ACK is received in incorrect state %d "); +578560,1185079296,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_10,P_VALUE,swLogPrintf("smsMsgType decoded %d "); +578560,1185081344,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_11,P_VALUE,swLogPrintf("deliver cp ack for msg type %d "); +578560,1185083648,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_12,P_INFO,swLogPrintf("SMCM state : %d transfer to idle state for etynum : %d after CP ERROR received and send errorind to SMRL "); +578560,1185085696,0,0,PS1,SMS,CemmSmsProcUnitDataIndMsg_13,P_WARNING,swLogPrintf("decodeResult %d , smcmReadyToReceive : %d "); +578560,1185089535,0,0,PS1,SMS,CemmSmsProcSuspendIndMsg_1,P_VALUE,swLogPrintf("SMS service is suspended by EMM "); +578560,1185091583,0,0,PS1,SMS,CemmSmsProcResumeIndMsg_1,P_VALUE,swLogPrintf("SMS service is resumed by EMM "); +578560,1185091584,0,0,PS1,SMS,CemmSmsProcResumeIndMsg_2,P_VALUE,swLogPrintf("Pending SMS will be sent to EMM for entityNo %d "); +578560,1185095679,0,0,PS1,SMS,SmcmSendSmcmDataIndToSmrl_2,P_WARNING,swLogPrintf("gSmcmExData.smcmReadyToReceive is FALSE "); +578560,1185095680,0,0,PS1,SMS,CeSmcmProcessTimerExpiry_1,P_WARNING,swLogPrintf("CESMS Timer expired but fail to find entity context %d "); +578560,1185097728,0,0,PS1,SMS,CeSmcmProcessTimerExpiry_2,P_WARNING,swLogPrintf("TC1M expired in SMCM2 state for entity number %d "); +578560,1185100032,0,0,PS1,SMS,CeSmcmProcessTimerExpiry_3,P_INFO,swLogPrintf("SMCM state : %d transfer to idle state for etynum : %d "); +578560,1185102080,0,0,PS1,SMS,CeSmcmProcessTimerExpiry_6,P_WARNING,swLogPrintf("TC1M expired in unexpected state %d for entity number %d "); +578560,1185103872,0,0,PS1,SMS,CeNasSmsProcessTimerExpiry_1,P_WARNING,swLogPrintf("CeNasSmsTimerExpiry unexpected timerEnum : %d "); +578560,1185105920,0,0,PS1,SMS,EncodeSmsUsrDataTo7Bit_1,P_WARNING,swLogPrintf("CESMS too much SMS User Data Header %d "); +578560,1185107968,0,0,PS1,SMS,EncodeSmsUsrDataTo7Bit_2,P_WARNING,swLogPrintf("SMS User Data len %d is too long "); +578560,1185112063,0,0,PS1,SMS,Encode8BitFormatData_1,P_WARNING,swLogPrintf("CESMS Input data too long for ENC 8 bit "); +578560,1185114111,0,0,PS1,SMS,EncodeSmsDataToDefault_1,P_WARNING,swLogPrintf("CESMS too much SMS User Data Header "); +578560,1185116159,0,0,PS1,SMS,EncodeSmsDataToDefault_2,P_WARNING,swLogPrintf("SMS User Data exceed packing 7 bit max len "); +578560,1185116160,0,0,PS1,SMS,AssembleSmsSubmit_2,P_WARNING,swLogPrintf("MAX_SMS_LEN is less than dataLen %d "); +578560,1185118208,0,0,PS1,SMS,AssembleSmsCommand_1,P_WARNING,swLogPrintf("MAX_SMS_LEN is less than dataLen %d "); +578560,1185120256,0,0,PS1,SMS,ConstructCemmSmtlDeliveredInd_1,P_INFO,swLogPrintf("pCemmSmtlDeliveredInd->smsLen is %d after DecodeUserDataToOctet "); +578560,1185122304,0,0,PS1,SMS,ConstructCemmSmtlDeliveredInd_2,P_INFO,swLogPrintf("pCemmSmtlDeliveredInd->smsLen %d after DecodeUserDataToDef "); +578560,1185124352,0,0,PS1,SMS,ConstructCemmSmtlDeliveredInd_3,P_INFO,swLogPrintf("pCemmSmtlDeliveredInd->smsLen %d output "); +578560,1185126400,0,0,PS1,SMS,PackCesmsDeliver_1,P_WARNING,swLogPrintf("MAX_TPDU_INFO_LENGTH is less then ieLen %d "); +578560,1185128448,0,0,PS1,SMS,CemmSmrlProcessReportFromSmtl_1,P_ERROR,swLogPrintf("SMRL Received report from SMTL , but fail to find entity number %d "); +578560,1185132543,0,0,PS1,SMS,CemmSmrlProcessReportFromSmtl_2,P_INFO,swLogPrintf("TR2M timer is stopped "); +578560,1185132800,0,0,PS1,SMS,CemmSmrlProcessReportFromSmtl_3,P_WARNING,swLogPrintf("Deliver RP_ERROR_MS_TO_NW RP cause : %d ; TP Cause : %d "); +578560,1185134592,0,0,PS1,SMS,CemmSmrlProcessReportFromSmtl_4,P_WARNING,swLogPrintf("Unexpected SMRL state for SMRL_STATUS_REPORT %d "); +578560,1185136640,0,0,PS1,SMS,CemmSmrlProcessMoSubmitedData_1,P_WARNING,swLogPrintf("SMRL Received submitted data , but got unexpected entity number %d "); +578560,1185138688,0,0,PS1,SMS,CemmSmrlProcessMoSubmitedData_2,P_ERROR,swLogPrintf("SMRL Received submitted data , but fail to find entity number %d "); +578560,1185140736,0,0,PS1,SMS,CemmSmrlProcessMoSubmitedData_3,P_INFO,swLogPrintf("SMRL_DATA_REQ is received in SMRL state %d "); +578560,1185142784,0,0,PS1,SMS,CemmSmrlProcessMoSubmitedData_4,P_WARNING,swLogPrintf("SMRL_DATA_REQ is received in unexpected SMRL state %d "); +578560,1185144832,0,0,PS1,SMS,CemmSmrlProcessMoSMMA_1,P_WARNING,swLogPrintf("SMRL Received submitted data , but got unexpected entity number %d "); +578560,1185146880,0,0,PS1,SMS,CemmSmrlProcessMoSMMA_2,P_ERROR,swLogPrintf("SMRL Received submitted data , but fail to find entity number %d "); +578560,1185149184,0,0,PS1,SMS,CemmSmrlProcessConfigureSetting_1,P_INFO,swLogPrintf("moreSmsToSend setting : %d ; sms ready or not setting : %d "); +578560,1185150976,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_1,P_WARNING,swLogPrintf("CemmSmrlDecodeRpMsg received SMS RP message length too short : %d "); +578560,1185153024,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_2,P_WARNING,swLogPrintf("CemmSmrlDecodeRpMsg received SMS message Non-semantical mandatory information element : %d "); +578560,1185155072,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_3,P_WARNING,swLogPrintf("CemmSmrlDecodeRpMsg received SMS unknown message type : %d "); +578560,1185157632,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_4,P_WARNING,swLogPrintf("RP message type : %d with different message reference , MR from nw : %d , local MR : %d "); +578560,1185161215,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_5,P_INFO,swLogPrintf("SMS RP message type : RP_ACK_NW_TO_ME "); +578560,1185163263,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_6,P_INFO,swLogPrintf("SMS RP message type : RP_DATA_NW_TO_ME "); +578560,1185165311,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_7,P_WARNING,swLogPrintf("SMS RP message type : RP_ERROR_NW_TO_ME "); +578560,1185167359,0,0,PS1,SMS,CemmSmrlDecodeRpMsg_8,P_WARNING,swLogPrintf("Invalid case to switch on msgType "); +578560,1185167616,0,0,PS1,SMS,CemmSmrlDecodeRpAckData_1,P_INFO,swLogPrintf("decode RP_USER_DATA offset : %d greater or equal to smsLen : %d "); +578560,1185169408,0,0,PS1,SMS,CemmSmrlDecodeRpAckData_2,P_WARNING,swLogPrintf("RP user data length %d exceed MAX_SMS_TPDU_INFO_LEN "); +578560,1185171456,0,0,PS1,SMS,CemmSmrlDecodeRpAckData_3,P_WARNING,swLogPrintf("RP_USER_DATA decoding meet unexpected data %d "); +578560,1185173760,0,0,PS1,SMS,CemmSmrlDecodeRpData_1,P_ERROR,swLogPrintf("Message too short to contain RP-Originator Address , offset : %d , smsLen : %d "); +578560,1185175552,0,0,PS1,SMS,CemmSmrlDecodeRpData_2,P_ERROR,swLogPrintf("RP-Originator Address too long : %d "); +578560,1185177856,0,0,PS1,SMS,CemmSmrlDecodeRpData_3,P_ERROR,swLogPrintf("Message too short to contain RP-Destination Address , offset : %d , smsLen : %d "); +578560,1185179904,0,0,PS1,SMS,CemmSmrlDecodeRpData_4,P_ERROR,swLogPrintf("Message too short to contain RP-User Data , offset : %d , smsLen : %d "); +578560,1185181696,0,0,PS1,SMS,CemmSmrlDecodeRpData_5,P_WARNING,swLogPrintf("TPDU length %d exceed TPDU_MAXIMUM_LENGTH "); +578560,1185183744,0,0,PS1,SMS,CemmSmrlDecodeRpError_1,P_ERROR,swLogPrintf("not enough room for RP-Cause , smsLen : %d "); +578560,1185185792,0,0,PS1,SMS,CemmSmrlDecodeRpError_2,P_ERROR,swLogPrintf("causeLen : %d with incorrect data "); +578560,1185188096,0,0,PS1,SMS,CemmSmrlDecodeRpError_3,P_ERROR,swLogPrintf("length compatability check failure , %d , %d "); +578560,1185189888,0,0,PS1,SMS,CemmSmrlSendRpResponse_1,P_WARNING,swLogPrintf("Invalid RP message type %d "); +578560,1185191936,0,0,PS1,SMS,CemmSmrlFindRunningDelayTimerMoEty_1,P_INFO,swLogPrintf("SM-RL stop the running delayTimer , timerIndex %d "); +578560,1185194240,0,0,PS1,SMS,CesmrlFindAvailEntity_info_1,P_INFO,swLogPrintf("Input entity no : %d , EtyMsgType : %d "); +578560,1185198079,0,0,PS1,SMS,CesmrlFindAvailEntity_1,P_WARNING,swLogPrintf("no free entity in SMRL "); +578560,1185198080,0,0,PS1,SMS,CesmrlFindAvailEntity_2,P_WARNING,swLogPrintf("free entity : %d in SMRL allocate memory failure "); +578560,1185200128,0,0,PS1,SMS,CesmrlFindAvailEntity_3,P_WARNING,swLogPrintf("GET_ETY_FOR_DATA_ERR_IND fail to find corresponding entity no : %d "); +578560,1185202176,0,0,PS1,SMS,CesmrlFindAvailEntity_4,P_WARNING,swLogPrintf("GET_ETY_FOR_DATA_ERR_IND fail to find inuse entity no : %d "); +578560,1185204224,0,0,PS1,SMS,CesmrlFindAvailEntity_5,P_WARNING,swLogPrintf("GET_ETY_FOR_EST_IND fail to find inuse entity no : %d "); +578560,1185206272,0,0,PS1,SMS,CemmSmrlReleaseEntity_1,P_INFO,swLogPrintf("SM-RL start release entity , entityNo = %d "); +578560,1185208320,0,0,PS1,SMS,CemmSmrlReleaseEntity_2,P_INFO,swLogPrintf("SM-RL start release entity , entityNo = %d "); +578560,1185212415,0,0,PS1,SMS,CemmSmrlSendRelReqToSmcm_1,P_INFO,swLogPrintf("SMRL-Delay release timer is started "); +578560,1185212416,0,0,PS1,SMS,CemmSmrlProcessTimerExpiry_1,P_INFO,swLogPrintf("SMRL received timer expiry , entityNumber %d "); +578560,1185214464,0,0,PS1,SMS,CemmSmrlProcessTimerExpiry_2,P_ERROR,swLogPrintf("SMRL received timer expiry , but failed to find entity number %d "); +578560,1185216768,0,0,PS1,SMS,CemmSmrlProcessTimerExpiry_3,P_WARNING,swLogPrintf("Incorrect timer expiry in unexpected SMRL state %d ; For entity number %d "); +578560,1185218560,0,0,PS1,SMS,CemmSmrlProcessTimerExpiry_4,P_WARNING,swLogPrintf("Incorrect timer expiry for unexpected entity number %d "); +578560,1185220608,0,0,PS1,SMS,CemmSmrlHandleEstIndFromSmcm_1,P_ERROR,swLogPrintf("SMRL received smcm_est_ind , but fail to find entity number %d "); +578560,1185222656,0,0,PS1,SMS,CemmSmrlHandleEstIndFromSmcm_2,P_WARNING,swLogPrintf("could not decode RP msg in EST_IND successfully for entity number %d "); +578560,1185224704,0,0,PS1,SMS,CemmSmrlHandleEstIndFromSmcm_3,P_WARNING,swLogPrintf("SMRL deliver RP_ERROR_MS_TO_NW RP RESPONSE for entity number %d "); +578560,1185227008,0,0,PS1,SMS,CemmSmrlHandleEstIndFromSmcm_4,P_WARNING,swLogPrintf("Received smcm_est_ind in unexpected SMRL state %d ; For entity number %d "); +578560,1185228800,0,0,PS1,SMS,CemmSmrlHandleDataIndFromSmcm_1,P_ERROR,swLogPrintf("SMRL received smcm_data_ind , but failed to find entity number %d "); +578560,1185230848,0,0,PS1,SMS,CemmSmrlHandleDataIndFromSmcm_2,P_WARNING,swLogPrintf("Could not decode RP msg in DATA_IND successfully for entity number %d "); +578560,1185232896,0,0,PS1,SMS,CemmSmrlHandleDataIndFromSmcm_3,P_WARNING,swLogPrintf("Invalid pEtyDat->rpMsg.rpRc.msgDecodeRc %d "); +578560,1185235200,0,0,PS1,SMS,CemmSmrlHandleDataIndFromSmcm_4,P_WARNING,swLogPrintf("Received smcm_data_ind in unexpected SMRL state %d ; For entity number %d "); +578560,1185236992,0,0,PS1,SMS,CemmSmrlHandleErrIndFromSmcm_1,P_ERROR,swLogPrintf("SMRL Received smcm_err_ind , but fail to find entity number %d "); +578560,1185239296,0,0,PS1,SMS,CemmSmrlHandleErrIndFromSmcm_2,P_WARNING,swLogPrintf("Received smcm_err_ind in unexpected SMRL state %d ; for entity number %d "); +578560,1185241088,0,0,PS1,SMS,CemmSmrlSendReptIndtoSmtl_1,P_WARNING,swLogPrintf("fail to find SMRL entity : %d for RPT_FOR_DATA_IND "); +578560,1185243136,0,0,PS1,SMS,CemmSmrlSendReptIndtoSmtl_2,P_WARNING,swLogPrintf("fail to find SMRL entity : %d for RPT_FOR_ERR_IND "); +578560,1185245184,0,0,PS1,SMS,CemmSmrlSendReptIndtoSmtl_3,P_WARNING,swLogPrintf("fail to find SMRL entity : %d for RPT_FOR_TIMER_EXPIRY "); +578560,1185249279,0,0,PS1,SMS,CemmSmrlSendReptIndtoSmtl_4,P_WARNING,swLogPrintf("Invalid signal passed to function SendSmrlReportInd "); +578560,1185249536,0,0,PS1,SMS,CemmSmrlSendReptIndNoEntitytoSmtl_1,P_INFO,swLogPrintf("SMRL deliver error report to SMTL for smsId : %d ; cause : %d "); +578560,1185251584,0,0,PS1,SMS,CemmSmrlSendAbortReqtoSmcm_1,P_INFO,swLogPrintf("SMRL send Abort to SMCM for etyNo : %d ; cause : %d "); +578560,1185253376,0,0,PS1,SMS,CemmSmtlProcessSmrlMtDataInd_1,P_WARNING,swLogPrintf("SMTL can not decode SMS for smsId : %d "); +578560,1185257471,0,0,PS1,SMS,DecodeSmsMessageBody_1,P_SIG,swLogPrintf("Receiving SMS CP DATA "); +578560,1185259519,0,0,PS1,SMS,DecodeSmsMessageBody_2,P_SIG,swLogPrintf("Receiving SMS CP ACK "); +578560,1185261567,0,0,PS1,SMS,DecodeSmsMessageBody_3,P_SIG,swLogPrintf("Receiving SMS CP ERROR "); +578560,1185261568,0,0,PS1,SMS,DecodeSmsMessageBody_4,P_WARNING,swLogPrintf("Unknown sms msg type %d received "); +578560,1185265663,0,0,PS1,SMS,EncodeSmsMessageBody_1,P_SIG,swLogPrintf("Sending SMS CP DATA "); +578560,1185267711,0,0,PS1,SMS,EncodeSmsMessageBody_2,P_SIG,swLogPrintf("Sending SMS CP ACK "); +578560,1185269759,0,0,PS1,SMS,EncodeSmsMessageBody_3,P_SIG,swLogPrintf("Sending SMS CP ERROR "); +578560,1185269760,0,0,PS1,SMS,EncodeSmsMessage_1,P_ERROR,swLogPrintf("Encode fail , incorrect RPDU len : %d "); +578560,1185271808,0,0,PS1,SMS,smsPduDecodeCbsDCS_1,P_WARNING,swLogPrintf("unknown cb DCS value : %d "); +578560,1185273856,0,0,PS1,SMS,smsPduDecodeCbsDCS_2,P_WARNING,swLogPrintf("unknown reserved DCS value : %d "); +578560,1185275904,0,0,PS1,SMS,smsPduDecodeCbsDCS_3,P_WARNING,swLogPrintf("unknown cb reserved DCS value : %d "); +578560,1185277952,0,0,PS1,SMS,smsPduDecodeCbsDCS_4,P_WARNING,swLogPrintf("unknown DCS value : %d "); +580608,1189087744,0,0,PS1,NAS_PLMN,CemmCalcEmergencyOosTimerInterval_1,P_VALUE,swLogPrintf("Base on power level ( %d ) , emergency OOS timer start times ( %d ) , calculate the emergency oos timer value is %d ( s ) "); +580608,1189089280,0,0,PS1,NAS_PLMN,CePlmnAddPreferFreqStatic_1,P_VALUE,swLogPrintf("CE PLMN , cell locked , can ' t add the FREQ : 0x%x into the FREQ header "); +580608,1189091328,0,0,PS1,NAS_PLMN,CePlmnAddPreferFreqStatic_2,P_VALUE,swLogPrintf("CE PLMN , euArfcn ( 0x%x ) is not belong any band in nvm , can ' t add to the FREQ header "); +580608,1189093632,0,0,PS1,NAS_PLMN,CePlmnIsFplmn_1,P_VALUE,swLogPrintf("PLMN , plmn : ( 0x%x , 0x%x ) is ( E ) HPLMN , not FPLMN "); +580608,1189095680,0,0,PS1,NAS_PLMN,CePlmnIsFplmn_2,P_VALUE,swLogPrintf("PLMN , plmn : ( 0x%x , 0x%x ) is forbidden in NVM list "); +580608,1189097728,0,0,PS1,NAS_PLMN,CePlmnIsFplmn_3,P_VALUE,swLogPrintf("PLMN , plmn : ( 0x%x , 0x%x ) is forbidden in UICC list "); +580608,1189099776,0,0,PS1,NAS_PLMN,CePlmnIsFplmn_4,P_WARNING,swLogPrintf("PLMN , FPLMN in UICC is not read , can ' t decide whether the PLMN : ( 0x%x , 0x%x ) is a FPLMN "); +580608,1189101824,0,0,PS1,NAS_PLMN,CePlmnIsGprsFplmn_1,P_VALUE,swLogPrintf("PLMN , plmn : ( 0x%x , 0x%x ) is forbidden for GPRS service "); +580608,1189103872,0,0,PS1,NAS_PLMN,CePlmnIsBlockedPlmnBlockedTac_1,P_VALUE,swLogPrintf("PLMN , PLMN : ( 0x%x , 0x%x ) is T3346 blocked temporarily "); +580608,1189105920,0,0,PS1,NAS_PLMN,CePlmnIsBlockedPlmnBlockedTac_2,P_VALUE,swLogPrintf("PLMN , PLMN : ( 0x%x , 0x%x ) is blocked temporarily due to severe network failure "); +580608,1189108480,0,0,PS1,NAS_PLMN,CePlmnIsEplmnStatic_eplmn_1,P_VALUE,swLogPrintf("CE PLMN , DEST PLMN : ( 0x%x , 0x%x ) and SRC PLMN : ( 0x%x , 0x%x ) are all EHPLMN , act as EPLMN "); +580608,1189110528,0,0,PS1,NAS_PLMN,CePlmnIsEplmnStatic_eplmn_2,P_VALUE,swLogPrintf("CE PLMN , DEST PLMN : ( 0x%x , 0x%x ) and SRC PLMN : ( 0x%x , 0x%x ) are all EHPLMN / HPLMN , act as EPLMN "); +580608,1189113088,0,0,PS1,NAS_PLMN,CePlmnIsEplmnStatic_eplmn_3,P_VALUE,swLogPrintf("CE PLMN , srcFound : %d , destFound : %d , DEST PLMN : ( 0x%x , 0x%x ) and SRC PLMN : ( 0x%x , 0x%x ) are not EPLMN "); +580608,1189114112,0,0,PS1,NAS_PLMN,CePlmnIsEqualRplmnStatic_1,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is RPLMN "); +580608,1189116160,0,0,PS1,NAS_PLMN,CePlmnIsEqualRplmnStatic_2,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is EPLMN of RPLMN "); +580608,1189118208,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_1,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is HPLMN "); +580608,1189120256,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_2,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is EHPLMN "); +580608,1189122304,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_3,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is FPLMN "); +580608,1189124352,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_4,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is UPLMN "); +580608,1189126400,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_5,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is OPLMN "); +580608,1189128448,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_6,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is RPLMN "); +580608,1189130496,0,0,PS1,NAS_PLMN,CePlmnGetPlmnTypeStatic_7,P_VALUE,swLogPrintf("PLMN ( 0x%x , 0x%x ) is EPLMN of RPLMN "); +580608,1189132288,0,0,PS1,NAS_PLMN,CePlmnFreqBelongValidBand_1,P_WARNING,swLogPrintf("CE PLMN , FREQ : %d , not belong to any band "); +580608,1189134592,0,0,PS1,NAS_PLMN,CePlmnFreqBelongValidBand_2,P_WARNING,swLogPrintf("CE PLMN , FREQ : %d , belong to band : %d , not the setting band "); +580608,1189136384,0,0,PS1,NAS_PLMN,CePlmnClearNvmPreFreqList_1,P_WARNING,swLogPrintf("CE PLMN , lock FREQ : %d , not right , clear cell lock info "); +580608,1189138944,0,0,PS1,NAS_PLMN,CePlmnAddSaveUiccEHPlmnInfo_1,P_WARNING,swLogPrintf("PLMN , local EHPLMN full : %d , can ' t add new EHPLMN : ( 0x%x , 0x%x ) "); +580608,1189140736,0,0,PS1,NAS_PLMN,CePlmnAddSaveUiccPlmnInfo_1,P_WARNING,swLogPrintf("Insert FPLMN number is %d , current FPLMN number is %d "); +580608,1189142784,0,0,PS1,NAS_PLMN,CePlmnAddSaveUiccPlmnInfo_2,P_WARNING,swLogPrintf("Insert UPLMN number is %d , current UPLMN number is %d "); +580608,1189144576,0,0,PS1,NAS_PLMN,CePlmnAddSaveUiccPlmnInfo_3,P_VALUE,swLogPrintf("No valid PLMN type : %d need to store "); +580608,1189148671,0,0,PS1,NAS_PLMN,CePlmnRemoveUiccPlmnInfo_1,P_INFO,swLogPrintf("PLMN , remove all FPLMN in local PLMN context "); +580608,1189148928,0,0,PS1,NAS_PLMN,CePlmnSendPlmnSearchReqSig_1,P_VALUE,swLogPrintf("CePlmnSendPlmnSearchReqSig , requested Plmn : ( 0x%x , 0x%x ) "); +580608,1189150721,0,0,PS1,NAS_PLMN,CePlmnSendPlmnSearchReqSig_3,P_SIG,swLogPrintf("Start Plmn Search , Request Band ( s ) : %s "); +580608,1189152768,0,0,PS1,NAS_PLMN,CePlmnSendPlmnSearchReqSig_bcinfo_4,P_VALUE,swLogPrintf("CE PLMN , start BCINFO Plmn Search , Without Band , PLMN FREQ num is %d "); +580608,1189154816,0,0,PS1,NAS_PLMN,CePlmnSendPlmnSearchReqSig_4,P_SIG,swLogPrintf("Start Plmn Search , Without Band , Cell Lock Flag is %d "); +580608,1189157120,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_1,P_VALUE,swLogPrintf("PLMN , fobidden PLMN is HPLMN ( 0x%x , 0x%x ) , can ' t add into FPLMN "); +580608,1189159168,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_2,P_VALUE,swLogPrintf("PLMN , forbidden PLMN is EHPLMN ( 0x%x , 0x%x ) , can ' t add into FPLMN list "); +580608,1189161216,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_3,P_VALUE,swLogPrintf("PLMN , add forbidden PLMN ( 0x%x , 0x%x ) to NVM FPLMN list "); +580608,1189163264,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_4,P_VALUE,swLogPrintf("PLMN , FPLMN ( 0x%x , 0x%x ) already in NVM FPLMN list "); +580608,1189165312,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_5,P_VALUE,swLogPrintf("PLMN , add forbidden PLMN ( 0x%x , 0x%x ) to UICC FPLMN list "); +580608,1189167360,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_6,P_WARNING,swLogPrintf("PLMN , can ' t add the FPLMN ( 0x%x , 0x%x ) into UICC FPLMN list , as UICC FPLMN haven ' t been read "); +580608,1189169408,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_7,P_VALUE,swLogPrintf("PLMN , can ' t add the FPLMN ( 0x%x , 0x%x ) to local PLMN list "); +580608,1189171456,0,0,PS1,NAS_PLMN,CePlmnAddFplmn_8,P_VALUE,swLogPrintf("PLMN , FPLMN ( 0x%x , 0x%x ) already in UICC FPLMN list "); +580608,1189173504,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_1,P_VALUE,swLogPrintf("PLMN , GPRS forbidden PLMN is HPLMN ( 0x%x , 0x%x ) , can ' t add into FPLMN list "); +580608,1189175552,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_2,P_VALUE,swLogPrintf("PLMN , GPRS forbidden PLMN is EHPLMN ( 0x%x , 0x%x ) , can ' t add into FPLMN list "); +580608,1189177600,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_3,P_VALUE,swLogPrintf("PLMN , add GPRS forbidden PLMN ( 0x%x , 0x%x ) "); +580608,1189179648,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_4,P_WARNING,swLogPrintf("PLMN , GPRS forbidden PLMN ( 0x%x , 0x%x ) is already in list [ fplmnIdx ] "); +580608,1189181696,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_5,P_VALUE,swLogPrintf("PLMN , can ' t add GPRS forbidden PLMN ( 0x%x , 0x%x ) due to list is full "); +580608,1189183744,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_6,P_WARNING,swLogPrintf("PLMN , GPRS forbidden PLMN ( 0x%x , 0x%x ) is already in list [ fplmnIdx ] "); +580608,1189185792,0,0,PS1,NAS_PLMN,CePlmnAddGprsFplmn_7,P_VALUE,swLogPrintf("PLMN , add GPRS forbidden PLMN ( 0x%x , 0x%x ) "); +580608,1189188096,0,0,PS1,NAS_PLMN,CePlmnAddBlockPlmnBlockTac_1,P_VALUE,swLogPrintf("PLMN , T3402 block list is full , remove the oldest PLMN ( 0x%x , 0x%x ) , TAC 0x%x "); +580608,1189191679,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_1,P_WARNING,swLogPrintf("PLMN , no valid PLMN in EPLMN list "); +580608,1189193727,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_2,P_INFO,swLogPrintf("PLMN , update EPLMN , but no EPLMN received , only need clear EPLMN "); +580608,1189193728,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_3,P_INFO,swLogPrintf("PLMN , update EPLMN , all EPLMN ( %d ) just same as in local NVM file , don ' t need to update "); +580608,1189196032,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_4,P_INFO,swLogPrintf("PLMN , need to up EPLMN list , valid EPLMN number : %d , all already in local NVM : %d , only need to update NVM "); +580608,1189197824,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_5,P_INFO,swLogPrintf("PLMN , need to up EPLMN list , valid EPLMN number : %d , need to check whether anyone forbidden "); +580608,1189200128,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_6,P_VALUE,swLogPrintf("PLMN , EPLMN : 0x%x , 0x%x , is the FPLMN , need to remove from EPLMN list "); +580608,1189202176,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_7,P_VALUE,swLogPrintf("PLMN , EPLMN : 0x%x , 0x%x , is the UICC FPLMN , need to remove from EPLMN list "); +580608,1189206015,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_8,P_WARNING,swLogPrintf("PLMN , need to update UICC FPLMN , but have not read from UICC "); +580608,1189206272,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_9,P_VALUE,swLogPrintf("PLMN , EPLMN : 0x%x , 0x%x , is the GPRS FPLMN , need to remove from EPLMN list "); +580608,1189210111,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_11,P_INFO,swLogPrintf("PLMN , update EPLMN , but all EPLMN are FPLMN , only need clear EPLMN "); +580608,1189210112,0,0,PS1,NAS_PLMN,CePlmnUpdateEqualRplmnList_12,P_INFO,swLogPrintf("PLMN , after filtered by FPLMN , all EPLMN ( %d ) just same as in local NVM file , don ' t need to update "); +580608,1189212416,0,0,PS1,NAS_PLMN,CePlmnCheckRemoveBlockedOrGprsFPlmn_1,P_VALUE,swLogPrintf("PLMN , remove blocked PLMN : ( 0x%x , 0x%x ) "); +580608,1189214464,0,0,PS1,NAS_PLMN,CePlmnCheckRemoveBlockedOrGprsFPlmn_2,P_VALUE,swLogPrintf("PLMN , remove GPRS forbidden PLMN ( 0x%x , 0x%x ) "); +580608,1189216768,0,0,PS1,NAS_PLMN,CePlmnCalcOosTimeValue_1,P_VALUE,swLogPrintf("Base on power level ( %d ) , Oos times ( %d ) , calc the oos timer value is %d ( s ) "); +580608,1189220351,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_1,P_INFO,swLogPrintf("PLMN , CUR PLMN search procedure is done "); +580608,1189222399,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_2,P_INFO,swLogPrintf("PLMN , Already camp on ( E ) HPLMN , stop HPLMN search timer. "); +580608,1189222400,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_3,P_VALUE,swLogPrintf("PLMN , start pending PLMN search ( %d ) proccedure "); +580608,1189224704,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_4,P_VALUE,swLogPrintf("PLMN , Already camp on ( E ) HPLMN 0x%x , 0x%x , cancel pending High Priority Plmn search. "); +580608,1189228543,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_6,P_INFO,swLogPrintf("PLMN , no valid selected PLMN found , need to start PLMN OOS timer , and retry "); +580608,1189230591,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_7,P_INFO,swLogPrintf("PLMN , period plmn T timer is running , need to stop it "); +580608,1189230592,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_8,P_VALUE,swLogPrintf("PLMN , start OOS PLMN timer : %d Seconds "); +580608,1189232640,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_9,P_VALUE,swLogPrintf("CE PLMN , PLMN search level : %d , already tried once oos plmn search , for power consumption considerations , no longer plmn search! "); +580608,1189234944,0,0,PS1,NAS_PLMN,CePlmnCurPlmnSearchDone_10,P_VALUE,swLogPrintf("PLMN , period high PLMN search done , selectedPlmn : 0x%x , 0x%x , check whether need to start period T timer "); +580608,1189238783,0,0,PS1,NAS_PLMN,CePlmnProcedureOut_1,P_INFO,swLogPrintf("PLMN , CUR PLMN search procedure is done , need to free it ' s memory "); +580608,1189240831,0,0,PS1,NAS_PLMN,CePlmnProcedureOut_2,P_WARNING,swLogPrintf("PLMN , Ready to enter PSM , PERIOD_HIGH_PLMN_SEARCH_TIMER is running , stop it and check whether need to re-start when leave psm "); +580608,1189242879,0,0,PS1,NAS_PLMN,CePlmnProcedureOut_3,P_INFO,swLogPrintf("PLMN , no procedure is ongoing / pending , need to free Dyn context "); +580608,1189242880,0,0,PS1,NAS_PLMN,CePlmnAbortCurPlmnSearch_1,P_INFO,swLogPrintf("PLMN , WiFi Scan is ongoing , Status : %d , just wait for the WiFi Scan "); +580608,1189246975,0,0,PS1,NAS_PLMN,CePlmnAbortCurPlmnSearch_2,P_INFO,swLogPrintf("PLMN , already aborted current PLMN search before , just wait for AS CNF "); +580608,1189249023,0,0,PS1,NAS_PLMN,CePlmnAbortCurPlmnSearch_3,P_WARNING,swLogPrintf("PLMN , Manual PLMN search aborted "); +580608,1189251071,0,0,PS1,NAS_PLMN,CePlmnAbortCurPlmnSearch_4,P_WARNING,swLogPrintf("PLMN , BCINFO Manual PLMN search aborted "); +580608,1189251072,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_1,P_VALUE,swLogPrintf("PLMN , AUTO PLMN search req , but another PLMN searching ( %d ) is ongoing , maybe need to pending "); +580608,1189253120,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_2,P_VALUE,swLogPrintf("PLMN , AUTO PLMN search is ongoing , and procStatus : %d "); +580608,1189257215,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_3,P_INFO,swLogPrintf("PLMN , AUTO PLMN search is ongoing , but already under ABORT procedure "); +580608,1189259263,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_4,P_INFO,swLogPrintf("PLMN , AUTO PLMN search is ongoing , and ignore current request one "); +580608,1189259520,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_5,P_VALUE,swLogPrintf("PLMN , a PLMN search ( %d ) is ongoing ( %d ) , abort it , and pending AUTO PLMN search "); +580608,1189261312,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_6,P_VALUE,swLogPrintf("PLMN , already another PLMN search ( %d ) is pending "); +580608,1189265407,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_7,P_INFO,swLogPrintf("PLMN , current PLMN is already AUTO in NVM "); +580608,1189267455,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_8,P_INFO,swLogPrintf("PLMN , AUTO PLMN search , no valid RPLMN / ignore RPLMN , try EHPMN / HPLMN "); +580608,1189267712,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_9,P_VALUE,swLogPrintf("PLMN , current selected PLMN just the same as the requested PLMN : ( 0x%x , 0x%x ) "); +580608,1189269504,0,0,PS1,NAS_PLMN,CePlmnAutoPlmnSearchReq_10,P_VALUE,swLogPrintf("PLMN , AUTO PLMN search , but AS is not in IDLE state ( %d ) , wait for AS to go ILDE "); +580608,1189271808,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSearchReq_1,P_VALUE,swLogPrintf("PLMN , current PLMN search ( %d ) is ongoing , and still a PLMN search pending ( %d ) , reject this MANUAL PLMN search request "); +580608,1189273856,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSearchReq_2,P_VALUE,swLogPrintf("PLMN , current PLMN search ( %d ) is ongoing ( %d ) , pending this MANUAL PLMN search "); +580608,1189275648,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSearchReq_3,P_VALUE,swLogPrintf("PLMN , current MANUAL PLMN search is ongoing ( %d ) , but another MANUAL PLMN search comes , reject , and abort current procedure "); +580608,1189277952,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSearchReq_4,P_VALUE,swLogPrintf("PLMN , current High priority PLMN search is ongoing ( %d ) , and still a PLMN search pending ( %d ) , reject this MANUAL PLMN search request "); +580608,1189279744,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSearchReq_5,P_VALUE,swLogPrintf("PLMN , abort current High priority PLMN search ( %d ) , pending this MANUAL PLMN search "); +580608,1189281792,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSearchReq_6,P_VALUE,swLogPrintf("PLMN , start manual PLMN search , but current AS is not in IDLE state ( %d ) , force to do IDLE firstly "); +580608,1189284096,0,0,PS1,NAS_PLMN,CePlmnBcInfoManualPlmnSearchReq_busy_1,P_VALUE,swLogPrintf("PLMN , current PLMN search ( %d ) is ongoing , and still a PLMN search pending ( %d ) , reject this ECINFO MANUAL PLMN search request "); +580608,1189286144,0,0,PS1,NAS_PLMN,CePlmnBcInfoManualPlmnSearchReq_busy_2,P_VALUE,swLogPrintf("PLMN , current PLMN search ( %d ) is ongoing ( %d ) , pending this ECINFO MANUAL PLMN search "); +580608,1189287936,0,0,PS1,NAS_PLMN,CePlmnBcInfoManualPlmnSearchReq_cft_1,P_WARNING,swLogPrintf("PLMN , current MANUAL PLMN search is ongoing ( %d ) , but another BCINFO MANUAL PLMN search comes , reject , and abort current procedure "); +580608,1189290240,0,0,PS1,NAS_PLMN,CePlmnBcInfoManualPlmnSearchReq_busy_3,P_VALUE,swLogPrintf("PLMN , current High priority PLMN search is ongoing ( %d ) , and still a PLMN search pending ( %d ) , reject this BCINFO MANUAL PLMN search request "); +580608,1189292032,0,0,PS1,NAS_PLMN,CePlmnBcInfoManualPlmnSearchReq_busy_4,P_VALUE,swLogPrintf("PLMN , abort current High priority PLMN search ( %d ) , pending this BCINFO MANUAL PLMN search "); +580608,1189294848,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSelectReq_1,P_VALUE,swLogPrintf("Manual PLMN selection ( %d ) , request PLMN : ( 0x%x , 0x%x ) , but another PLMN search ( %d ) is ongoing now "); +580608,1189298175,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSelectReq_2,P_INFO,swLogPrintf("PLMN , current manual PLMN selection just the same as the new request one , just return directly "); +580608,1189298176,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSelectReq_3,P_VALUE,swLogPrintf("PLMN , already another PLMN search ( %d ) is pending , need to abort it "); +580608,1189300736,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSelectReq_4,P_VALUE,swLogPrintf("PLMN , PLMN select type : %d and manual PLMN : ( 0x%x , 0x%x ) , as the same as the value in NVM "); +580608,1189302528,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSelectReq_5,P_VALUE,swLogPrintf("PLMN , current selected PLMN just the same as the manual request : ( 0x%x , 0x%x ) "); +580608,1189304320,0,0,PS1,NAS_PLMN,CePlmnManualPlmnSelectReq_6,P_VALUE,swLogPrintf("PLMN , start manual PLMN selection , but current AS is not in IDLE state ( %d ) , force to go IDLE firstly "); +580608,1189306624,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnSearchReq_1,P_VALUE,swLogPrintf("PLMN , while trigger period high plmn search , another plmn is ongoing , type : %d , status : %d , just pending it "); +580608,1189308416,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnSearchReq_2,P_VALUE,swLogPrintf("PLMN , while trigger period high plmn search , another plmn is also pending , type : %d , just discard it "); +580608,1189310720,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnSearchReq_3,P_VALUE,swLogPrintf("PLMN , rplmn : 0x%x , 0x%x , check whether need to start period T timer "); +580608,1189312768,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnSearchReq_4,P_WARNING,swLogPrintf("PLMN , selectedPlmn : 0x%x , 0x%x , check whether need to start period T timer "); +580608,1189314560,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_1,P_VALUE,swLogPrintf("PLMN , default PLMN search req , but another PLMN searching ( %d ) is ongoing , maybe need to pending "); +580608,1189318655,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_2,P_WARNING,swLogPrintf("PLMN , Ignore current default PLMN search req "); +580608,1189320703,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_warning_2,P_WARNING,swLogPrintf("PLMN , Auto PLMN search is ongoing , ignore current default PLMN search req "); +580608,1189320960,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_3,P_WARNING,swLogPrintf("PLMN , default PLMN request , curent ongoing PLMN : %d , but still a PLMN searching ( %d ) in pending , replace it! "); +580608,1189324799,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_4,P_INFO,swLogPrintf("PLMN , manual PLMN selection "); +580608,1189326847,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_5,P_INFO,swLogPrintf("PLMN , manual then auto PLMN selection "); +580608,1189328895,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_6,P_INFO,swLogPrintf("PLMN , first power on , attemptHplmn is set , try HPLMN "); +580608,1189330943,0,0,PS1,NAS_PLMN,CePlmnDefaultPlmnSearchReq_7,P_INFO,swLogPrintf("PLMN , no valid RPLMN or roaming is not allowed , try HPLMN "); +580608,1189331456,0,0,PS1,NAS_PLMN,CePlmnCehckPlmnSuitable_1,P_VALUE,swLogPrintf("PLMN , plmn ( 0x%x , 0x%x ) , current TAC : %d is forbidden "); +580608,1189332992,0,0,PS1,NAS_PLMN,CePlmnCehckPlmnSuitable_2,P_VALUE,swLogPrintf("PLMN , Cell ( phyCellId : %d ) is barred "); +580608,1189337087,0,0,PS1,NAS_PLMN,CeplmnChooseHighestPriorityEhplmn_1,P_INFO,swLogPrintf("try to choose highest priority EHPLMN "); +580608,1189337344,0,0,PS1,NAS_PLMN,CeplmnChooseHighestPriorityEhplmn_2,P_VALUE,swLogPrintf("PLMN , choose highest prirority EHPLMN ( 0x%x , 0x%x ) "); +580608,1189341183,0,0,PS1,NAS_PLMN,CeplmnChooseHighestPriorityUplmn_1,P_INFO,swLogPrintf("try to choose highest priority UPLMN "); +580608,1189341440,0,0,PS1,NAS_PLMN,CeplmnChooseHighestPriorityUplmn_2,P_VALUE,swLogPrintf("PLMN , choose highest prirority UPLMN ( 0x%x , 0x%x ) "); +580608,1189345279,0,0,PS1,NAS_PLMN,CeplmnChooseHighestPriorityOplmn_1,P_INFO,swLogPrintf("try to choose highest priority OPLMN "); +580608,1189345536,0,0,PS1,NAS_PLMN,CeplmnChooseHighestPriorityOplmn_2,P_VALUE,swLogPrintf("PLMN , choose highest priority OPLMN ( 0x%x , 0x%x ) "); +580608,1189349375,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_1,P_INFO,swLogPrintf("PLMN , AUTO PLMN selection , try to choose a suitable PLMN "); +580608,1189349632,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_2,P_VALUE,swLogPrintf("PLMN , Roaming disable mode , Plmn ( 0x%x , 0x%x ) is not the HPLMN / EHPLMN "); +580608,1189353471,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_3,P_INFO,swLogPrintf("PLMN , choose RPLMN / EPLMN "); +580608,1189355519,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_4,P_WARNING,swLogPrintf("suitablePlmnNum equal to SUPPORT_MAX_PLMN_NUM "); +580608,1189356032,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_5,P_VALUE,swLogPrintf("PLMN user reselection , highPlmnType %d , PLMN : ( 0x%x , 0x%x ) "); +580608,1189358080,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_6,P_VALUE,swLogPrintf("PLMN user reselection , curPlmnType %d , PLMN : ( 0x%x , 0x%x ) "); +580608,1189361663,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_7,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM EHPLMN are found "); +580608,1189363711,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_8,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM UPLMN are found "); +580608,1189365759,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_9,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM OPLMN are found "); +580608,1189366016,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_10,P_VALUE,swLogPrintf("PLMN , MANUAL PLMN selection , try to choose PLMN : ( 0x%x , 0x%x ) "); +580608,1189368064,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_11,P_VALUE,swLogPrintf("PLMN , Manual PLMN ( 0x%x , 0x%x ) found "); +580608,1189371903,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_12,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM EHPLMN are found "); +580608,1189372160,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_13,P_VALUE,swLogPrintf("PLMN , Manual select plmn not found , could choose HPLMN ( 0x%x , 0x%x ) "); +580608,1189375999,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_14,P_INFO,swLogPrintf("PLMN , Manual select plmn not found , try to choose highest priority EHPLMN "); +580608,1189378047,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_15,P_INFO,swLogPrintf("PLMN , period High priority PLMN selection , try to choose high priority PLMN "); +580608,1189378560,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_16,P_VALUE,swLogPrintf("PLMN , current VPLMN ( 0x%x , 0x%x ) type is : %d "); +580608,1189382143,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_17,P_WARNING,swLogPrintf("suitablePlmnNum equal to SUPPORT_MAX_PLMN_NUM "); +580608,1189384191,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_18,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM EHPLMN are found "); +580608,1189386239,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_19,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM UPLMN are found "); +580608,1189388287,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_20,P_INFO,swLogPrintf("PLMN , more than UICC_PLMN_TRUNCATED_NUM OPLMN are found "); +580608,1189390335,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_21,P_INFO,swLogPrintf("PLMN , Roaming disable mode , VPLMN is not allowed "); +580608,1189390848,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_22,P_VALUE,swLogPrintf("PLMN , choose PLMN ( 0x%x , 0x%x ) , and PLMN type : %d "); +580608,1189394431,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_23,P_INFO,swLogPrintf("PLMN , user reselection , choose RPLMN "); +580608,1189396479,0,0,PS1,NAS_PLMN,CePlmnChooseSuitableFoundPlmn_24,P_INFO,swLogPrintf("PLMN , no suitable PLMN could choose to use "); +580608,1189396480,0,0,PS1,NAS_PLMN,CePlmnSetBandInfoReq_1,P_VALUE,swLogPrintf("PLMN , band : %d , RF not support "); +580608,1189398528,0,0,PS1,NAS_PLMN,CePlmnSetBandInfoReq_2,P_VALUE,swLogPrintf("PLMN , band : %d , RF not support "); +580608,1189400576,0,0,PS1,NAS_PLMN,CePlmnSetBandInfoReq_3,P_VALUE,swLogPrintf("PLMN , band : %d , RF not support "); +580608,1189402624,0,0,PS1,NAS_PLMN,CePlmnSetBandInfoReq_4,P_VALUE,swLogPrintf("PLMN , band : %d , RF not support "); +580608,1189406719,0,0,PS1,NAS_PLMN,CePlmnSetBandInfoReq_5,P_VALUE,swLogPrintf("PLMN , invalid band setting "); +580608,1189408767,0,0,PS1,NAS_PLMN,CePlmnSetBandInfoReq_6,P_VALUE,swLogPrintf("PLMN , set band , clear celllock "); +580608,1189408768,0,0,PS1,NAS_PLMN,CePlmnSetPreferFreqInfoReq_1,P_WARNING,swLogPrintf("PLMN , invalid ARFCN num : %d in CemmPlmnSetFreqInfo "); +580608,1189412863,0,0,PS1,NAS_PLMN,CePlmnSetPreferFreqInfoReq_2,P_WARNING,swLogPrintf("PLMN , no valid FREQ setting in CemmPlmnSetFreqInfo "); +580608,1189412864,0,0,PS1,NAS_PLMN,CePlmnSetCellLockInfoReq_1,P_WARNING,swLogPrintf("Cell Lock , ARFCN num is not equal to 1 : %d in CePlmnSetCellLockInfoReq "); +580608,1189414912,0,0,PS1,NAS_PLMN,CePlmnSetCellLockInfoReq_2,P_WARNING,swLogPrintf("Cell Lock fail , ARFCN not belong to the right band , and phyCellId is not valid : %d "); +580608,1189419007,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_1,P_INFO,swLogPrintf("PLMN , RPLMN is HPLMN / EHPLMN , don ' t need to start PERIOD_HIGH_PLMN_SEARCH_TIMER "); +580608,1189421055,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_2,P_INFO,swLogPrintf("PLMN , PERIOD_HIGH_PLMN_SEARCH_TIMER is running , need to stop it "); +580608,1189423103,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_3,P_INFO,swLogPrintf("PLMN , period high priority PLMN search is ongoing , don ' t need to start period T timer "); +580608,1189425151,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_4,P_INFO,swLogPrintf("PLMN , period high priority PLMN search is pending , don ' t need to start period T timer "); +580608,1189427199,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_EnableHPPlmnSearch,P_INFO,swLogPrintf("PLMN , period high priority PLMN search is disabled by user , don ' t need to start PERIOD_HIGH_PLMN_SEARCH_TIMER "); +580608,1189427712,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_UserSetValid,P_INFO,swLogPrintf("PLMN , SearchCount : %d , try_count : %d , timer_val : %d "); +580608,1189431295,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_stopHPPLMNSearchAttempts,P_INFO,swLogPrintf("PLMN , No higher priority PLMN search attempts , don ' t need to start PERIOD_HIGH_PLMN_SEARCH_TIMER "); +580608,1189433343,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_NoHPPLMNSearchAttempts,P_INFO,swLogPrintf("PLMN , No higher priority PLMN search attempts , don ' t need to start PERIOD_HIGH_PLMN_SEARCH_TIMER "); +580608,1189435391,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_5,P_INFO,swLogPrintf("PLMN , plmnSelectType is not CEMM_AUTO_PLMN_REG , don ' t need to start PERIOD_HIGH_PLMN_SEARCH_TIMER "); +580608,1189437439,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_6,P_INFO,swLogPrintf("PLMN , PERIOD_HIGH_PLMN_SEARCH_TIMER is still running "); +580608,1189437696,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_7,P_VALUE,swLogPrintf("PLMN , UE registered on RPLMN ( 0x%x , 0x%x ) , but OOS timer is still running , abnormal , stop it "); +580608,1189439488,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_8,P_VALUE,swLogPrintf("PLMN , try to start PERIOD_HIGH_PLMN_SEARCH_TIMER , sec : %d "); +580608,1189441536,0,0,PS1,NAS_PLMN,CePlmnCheckHighPlmnSearchTimer_9,P_VALUE,swLogPrintf("PLMN , try to start PERIOD_HIGH_PLMN_SEARCH_TIMER , mins : %d "); +580608,1189445631,0,0,PS1,NAS_PLMN,CePlmnOosSearchTimerExpiry_1,P_INFO,swLogPrintf("PLMN , OOS PLMN timer expiry , but timer state is not started , maybe this timer already stop before "); +580608,1189447679,0,0,PS1,NAS_PLMN,CePlmnOosSearchTimerExpiry_2,P_INFO,swLogPrintf("PLMN , OOS PLMN timer expiry , but PERIOD_HIGH_PLMN_SEARCH_TIMER is running... "); +580608,1189449727,0,0,PS1,NAS_PLMN,CePlmnOosSearchTimerExpiry_3,P_INFO,swLogPrintf("PLMN , OOS PLMN timer expiry , start PLMN search again "); +580608,1189451775,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnTimerExpiry_1,P_WARNING,swLogPrintf("PLMN , period PLMN timer expiry , but timer state is not started , maybe this timer already stopped before "); +580608,1189453823,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnTimerExpiry_2,P_INFO,swLogPrintf("PLMN , period PLMN timer expiry , but OOS PLMN search timer is running... "); +580608,1189455871,0,0,PS1,NAS_PLMN,CePlmnPeriodHighPlmnTimerExpiry_3,P_INFO,swLogPrintf("PLMN , period PLMN timer expiry , start high priority PLMN search "); +580608,1189455872,0,0,PS1,NAS_PLMN,CePlmnOosPlmnSelectReq_1,P_VALUE,swLogPrintf("PLMN , can ' t process OOS PLMN selection , as plmnSelectState is not DEACTIVATED or OOS SLEEP state : %d "); +580608,1189457920,0,0,PS1,NAS_PLMN,CePlmnOosPlmnSelectReq_2,P_VALUE,swLogPrintf("PLMN , current plmn is in searing procedure with search type %d , no longer to process this oos plmn select req "); +580608,1189462015,0,0,PS1,NAS_PLMN,CePlmnOosPlmnSelectReq_3,P_INFO,swLogPrintf("PLMN , PLMN OOS timer is running , need to stop it "); +580608,1189464063,0,0,PS1,NAS_PLMN,CePlmnOosPlmnSelectReq_4,P_INFO,swLogPrintf("PLMN , no valid RPLMN , try HPLMN "); +580608,1189464320,0,0,PS1,NAS_PLMN,CePlmnPostponedPeriodHighPlmnSearch_1,P_VALUE,swLogPrintf("PLMN , while trigger period high plmn search , another plmn is ongoing , type : %d , status : %d , just pending it "); +580608,1189466112,0,0,PS1,NAS_PLMN,CePlmnPostponedPeriodHighPlmnSearch_2,P_VALUE,swLogPrintf("PLMN , while trigger period high plmn search , another plmn is also pending , type : %d , just discard it "); +580608,1189468416,0,0,PS1,NAS_PLMN,CePlmnPostponedPeriodHighPlmnSearch_3,P_VALUE,swLogPrintf("PLMN , rplmn : 0x%x , 0x%x , check whether need to start period T timer "); +580608,1189470464,0,0,PS1,NAS_PLMN,CePlmnPostponedPeriodHighPlmnSearch_4,P_WARNING,swLogPrintf("PLMN , selectedPlmn : 0x%x , 0x%x , check whether need to start period T timer "); +580608,1189474303,0,0,PS1,NAS_PLMN,CePlmnCheckHplmnTimerWakeUpFromPsm_1,P_ERROR,swLogPrintf("PLMN , PERIOD_HIGH_PLMN_SEARCH_TIMER should not running , Pls Check it! "); +580608,1189474560,0,0,PS1,NAS_PLMN,CePlmnCheckHplmnTimerWakeUpFromPsm_2,P_INFO,swLogPrintf("PLMN , currSC is %d , hplmnTimerExpiredSC is %d , PERIOD_HIGH_PLMN_SEARCH_TIMER had expired under psm , postponed this period high plmn search until the end of business! "); +580608,1189476864,0,0,PS1,NAS_PLMN,CePlmnCheckHplmnTimerWakeUpFromPsm_3,P_INFO,swLogPrintf("PLMN , currSC is %d , hplmnTimerExpiredSC is %d , Wakeup from Psm , Re-Start PERIOD_HIGH_PLMN_SEARCH_TIMER with remain seconds : %d "); +580608,1189480447,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_1,P_WARNING,swLogPrintf("PLMN SIM card changes , IMSI is not same as pervious in NVM "); +580608,1189482495,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_2,P_WARNING,swLogPrintf("PLMN , SIM card changes , RPLMN not valid in USIM , delete NVM stored RPLMN "); +580608,1189483264,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_cmp_1,P_WARNING,swLogPrintf("PLMN , HPLMN in SIM : ( 0x%x , 0x%x ) , not the same as previous : ( 0x%x , 0x%x ) , need to clear old prefer FREQ "); +580608,1189486591,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_3,P_WARNING,swLogPrintf("PLMN , HPPLMN period in SIM < minPeriodicSearchTimer "); +580608,1189486592,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_4,P_WARNING,swLogPrintf("More EHPMN : %d in UICC ; need read more "); +580608,1189488896,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_5,P_WARNING,swLogPrintf("PLMN , no EPS Location info in UICC , get RPLMN ( 0x%x , 0x%x ) from NVM "); +580608,1189490688,0,0,PS1,NAS_PLMN,CePlmnSimReadyInd_6,P_WARNING,swLogPrintf("More FPLMN : %d in UICC , need read more "); +580608,1189492992,0,0,PS1,NAS_PLMN,CePlmnFillActReqInfo_1,P_VALUE,swLogPrintf("CePlmnFillActReqInfo : Plmn is ( 0x%x , 0x%x ) "); +580608,1189495040,0,0,PS1,NAS_PLMN,CePlmnFillActReqInfo_2,P_VALUE,swLogPrintf("CePlmnFillActReqInfo , cell lock : FREQ : %ld , phyCellId : %d "); +580608,1189497088,0,0,PS1,NAS_PLMN,CePlmnRegisteredInd_1,P_VALUE,swLogPrintf("PLMN , RPLMN ( 0x%x , 0x%x ) is not changed , just same as before "); +580608,1189499136,0,0,PS1,NAS_PLMN,CePlmnRegisteredInd_2,P_VALUE,swLogPrintf("PLMN , RPLMN ( 0x%x , 0x%x ) is in the FPLMN list stored in NVM , remove it "); +580608,1189501184,0,0,PS1,NAS_PLMN,CePlmnRegisteredInd_3,P_VALUE,swLogPrintf("PLMN , RPLMN ( 0x%x , 0x%x ) is in the FPLMN list stored in UICC , remove it "); +580608,1189505023,0,0,PS1,NAS_PLMN,CePlmnRegisteredInd_4,P_WARNING,swLogPrintf("PLMN , need to update UICC FPLMN , but have not read from UICC , update later "); +580608,1189507071,0,0,PS1,NAS_PLMN,CePlmnDeregisteredInd_1,P_INFO,swLogPrintf("PLMN , clear EPLMN "); +580608,1189509119,0,0,PS1,NAS_PLMN,CePlmnDeregisteredInd_2,P_INFO,swLogPrintf("PLMN , PLMN select type is Manual then Auto , but manual PLMN selection failed , try to AUTO mode "); +580608,1189509376,0,0,PS1,NAS_PLMN,CePlmnRemoveBlockPlmnBlockTac_1,P_VALUE,swLogPrintf("PLMN , EMM notify to remove blocked PLMN ( 0x%x , 0x%x ) "); +580608,1189511424,0,0,PS1,NAS_PLMN,CePlmnRemoveBlockPlmnBlockTac_2,P_VALUE,swLogPrintf("PLMN , EMM notify to remove blocked PLMN ( 0x%x , 0x%x ) "); +580608,1189513728,0,0,PS1,NAS_PLMN,CePlmnRemoveBlockPlmnBlockTac_3,P_WARNING,swLogPrintf("PLMN , blockReason %d , t3402BlockNum %d , blockPlmnPresent %d! "); +580608,1189517311,0,0,PS1,NAS_PLMN,CePlmnDelLastPreferFreq_1,P_VALUE,swLogPrintf("CE PLMN , cell locked , can ' t del the FREQ list "); +580608,1189519359,0,0,PS1,NAS_PLMN,CePlmnDelPreferFreq_1,P_VALUE,swLogPrintf("CE PLMN , cell locked , can ' t del the FREQ list "); +580608,1189519360,0,0,PS1,NAS_PLMN,CePlmnSetPreferFreqList_1,P_VALUE,swLogPrintf("CE PLMN , cell locked , can ' t set prefer FREQ list : %d "); +580608,1189523455,0,0,PS1,NAS_PLMN,CePlmnSetPreferFreqList_2,P_INFO,swLogPrintf("CE PLMN , FREQ is same , don ' t need update "); +580608,1189523968,0,0,PS1,NAS_PLMN,CePlmnSimReadDataCnf_1,P_VALUE,swLogPrintf("PLMN read : type %d of PLMN info from UICC , startIndex : %d , total num : %d "); +580608,1189525760,0,0,PS1,NAS_PLMN,CePlmnSimReadDataCnf_2,P_VALUE,swLogPrintf("PLMN , RPLMN ( 0x%x , 0x%x ) is in the FPLMN list stored in UICC , remove it "); +580608,1189528064,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_1,P_VALUE,swLogPrintf("PLMN , CEMM Reqest to do PLMN selection , type : %d manual Plmn : 0x%x , 0x%x "); +580608,1189529600,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_2,P_VALUE,swLogPrintf("PLMN , CEMM Reqest to do PLMN selection , type : %d "); +580608,1189533695,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_3,P_INFO,swLogPrintf("PLMN , PLMN OOS timer is running , need to stop it "); +580608,1189535743,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_5,P_INFO,swLogPrintf("PLMN , UE in manual PLMN reg state , initiate reg ( not the first time ) on FPLMN / FPLMN for GPRS , need to start PLMN OOS timer , and retry "); +580608,1189537791,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_6,P_INFO,swLogPrintf("PLMN , period plmn T timer is running , need to stop it "); +580608,1189537792,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_7,P_VALUE,swLogPrintf("PLMN , start OOS PLMN timer : %d Seconds "); +580608,1189539840,0,0,PS1,NAS_PLMN,CePlmnProcSelectReqMsg_8,P_VALUE,swLogPrintf("CE PLMN , PLMN search level : %d , already tried once oos plmn search , for power consumption considerations , no longer plmn search! "); +580608,1189541888,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_1,P_VALUE,swLogPrintf("PLMN , Deact PLMN with cause : %d "); +580608,1189545983,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_2,P_INFO,swLogPrintf("PLMN , DEACT , PERIOD_HIGH_PLMN_SEARCH_TIMER is running , need to stop it "); +580608,1189548031,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_3,P_INFO,swLogPrintf("PLMN , DEACT , OOS_PLMN_SEARCH_TIMER is running , need to stop it "); +580608,1189550079,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_Psm,P_WARNING,swLogPrintf("PLMN , Ready to enter PSM , PERIOD_HIGH_PLMN_SEARCH_TIMER is running , stop it and when leave psm decide whether to re-Start! "); +580608,1189550592,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_4,P_WARNING,swLogPrintf("PLMN , PLMN search is ongoing when DEACT PLMN with cause : %d , type : %d , procStatus : %d "); +580608,1189552128,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_5,P_INFO,swLogPrintf("PLMN , need to ABORT AS PLMN search , as DEACT by EMM with cause : %d "); +580608,1189554176,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_6,P_INFO,swLogPrintf("PLMN , manual PLMN search , deact cause : %d , abort it and confirm with no PLMN "); +580608,1189556224,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_bcinfo_1,P_INFO,swLogPrintf("PLMN , BCINFO manual PLMN search , deact cause : %d , abort it and confirm with no PLMN "); +580608,1189558272,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_wifiscan_1,P_INFO,swLogPrintf("PLMN , Wifi Scan , deact cause : %d , abort it and confirm with no WiFi "); +580608,1189562367,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_8,P_WARNING,swLogPrintf("PLMN , PLMN search is ongoing , but EMM trigger to enter PSM , pending PSM deactivation "); +580608,1189562368,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_9,P_WARNING,swLogPrintf("PLMN , another PLMN search procedure ( %d ) is pending "); +580608,1189564416,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_10,P_INFO,swLogPrintf("PLMN , manual PLMN search pending , deactCause : %d , abort it and confirm with no PLMN "); +580608,1189566464,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_bcinfo_2,P_INFO,swLogPrintf("PLMN , BCINFO manual PLMN search pending , deactCause : %d , abort it and confirm with no PLMN "); +580608,1189568512,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_wifiscan_2,P_INFO,swLogPrintf("PLMN , WiFi Scan pending , deactCause : %d , abort it and confirm with no WiFi "); +580608,1189572607,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_11,P_WARNING,swLogPrintf("PLMN , PLMN search is pending , but EMM trigger to enter PSM , pending PSM deactivation "); +580608,1189574655,0,0,PS1,NAS_PLMN,CePlmnProcDeactReqMsg_12,P_WARNING,swLogPrintf("PLMN , Ready to enter PSM , PERIOD_HIGH_PLMN_SEARCH_TIMER is running , stop it and check whether need to re-start when leave psm "); +580608,1189576703,0,0,PS1,NAS_PLMN,CePlmnProcIdleStateCnfMsg_1,P_INFO,swLogPrintf("PLMN , Idle state is requested because of WiFi SCAN , do nothing here "); +580608,1189578751,0,0,PS1,NAS_PLMN,CePlmnProcIdleStateIndMsg_1,P_WARNING,swLogPrintf("PLMN , Idle state is requested because of WiFi SCAN , do nothing here "); +580608,1189579008,0,0,PS1,NAS_PLMN,CePlmnProcIdleStateIndMsg_2,P_VALUE,swLogPrintf("PLMN , current selected PLMN just the same as the ( E ) HPLMN : ( 0x%x , 0x%x ) "); +580608,1189580800,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_1,P_VALUE,swLogPrintf("PLMN , Current PLMN search type : %d , and already aborted , but still received CerrcPlmnSearchInd , ignore it "); +580608,1189583104,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_2,P_VALUE,swLogPrintf("PLMN , Roaming Disable mode , Plmn ( 0x%x , 0x%x ) in CerrcPlmnSearchInd is not HPLMN / EHPLMN "); +580608,1189585664,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_3,P_VALUE,swLogPrintf("PLMN , Plmn ( 0x%x , 0x%x ) in CerrcPlmnSearchInd is not the EPLMN as the request PLMN : 0x%x , 0x%x "); +580608,1189587712,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_4,P_VALUE,swLogPrintf("PLMN , Manual PLMN selection mode , Plmn ( 0x%x , 0x%x ) in CerrcPlmnSearchInd should not consider as the EPLMN of the request PLMN : ( 0x%x , 0x%x ) "); +580608,1189588992,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_5,P_VALUE,swLogPrintf("PLMN , TAC ( %d ) in CerrcPlmnSearchInd is forbidden "); +580608,1189591040,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_6,P_VALUE,swLogPrintf("PLMN , Cell ( phyCellId : %d ) in CerrcPlmnSearchInd is barred "); +580608,1189595135,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_7,P_INFO,swLogPrintf("PLMN , PLMN select type is Manual then Auto , but can ' t find manual PLMN , try to AUTO mode "); +580608,1189597183,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_8,P_INFO,swLogPrintf("PLMN , no suitable PLMN could be selected in CerrcPlmnSearchInd , try to find next plmn "); +580608,1189597440,0,0,PS1,NAS_PLMN,CePlmnProcCerrcPlmnSearchIndSig_9,P_VALUE,swLogPrintf("PLMN , Suitable PLMN ( 0x%x , 0x%x ) selected in CerrcPlmnSearchInd "); +580608,1189599232,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcPlmnSearchCnfSig_1,P_VALUE,swLogPrintf("PLMN , PLMN search type : %d , aready aborted , but still received CerrcPlmnSearchCnf , need to wait for CerrcAbortPlmnSearchCnf "); +580608,1189601280,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcPlmnSearchCnfSig_2,P_VALUE,swLogPrintf("PLMN , PLMN select type : %d , suitable PLMN already selected in CerrcPlmnSearchInd , PLMN search procedure done "); +580608,1189605375,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcPlmnSearchCnfSig_3,P_INFO,swLogPrintf("PLMN , PLMN select type is Manual then Auto , but can ' t find manual PLMN , try to AUTO mode "); +580608,1189605376,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcPlmnSearchCnfSig_4,P_VALUE,swLogPrintf("PLMN , PLMN search type : %d , can ' t find any suitable PLMN... "); +580608,1189607680,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcPlmnSearchCnfSig_5,P_VALUE,swLogPrintf("PLMN , Suitable PLMN ( 0x%x , 0x%x ) selected in CerrcPlmnSearchCnf "); +580608,1189611519,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcPlmnSearchCnfSig_6,P_INFO,swLogPrintf("PLMN , pending Manual PLMN search proccedure , confirm to upper layer. "); +580608,1189611776,0,0,PS1,NAS_PLMN,CemmPlmnProcCerrcAbortPlmnSearchCnfSig_1,P_VALUE,swLogPrintf("PLMN , plmn search type : %d , procedure status : %d , abort confirm from CERRC "); +580608,1189615615,0,0,PS1,NAS_PLMN,CemmPlmnProcAbortPlmnSearchReqSig_1,P_INFO,swLogPrintf("PLMN , receive CemmAbortPlmnSearchReq from CCM , abort current manual PLMN search procedure "); +580608,1189617663,0,0,PS1,NAS_PLMN,CemmPlmnProcAbortPlmnSearchReqSig_2,P_INFO,swLogPrintf("PLMN , abort request already send to CERRC before , just wait for confirm "); +580608,1189619711,0,0,PS1,NAS_PLMN,CemmPlmnProcAbortPlmnSearchReqSig_3,P_INFO,swLogPrintf("PLMN , manual PLMN search is under pending , abort it "); +580608,1189621759,0,0,PS1,NAS_PLMN,CemmPlmnProcAbortPlmnSearchReqSig_4,P_INFO,swLogPrintf("PLMN , BCINFO manual PLMN search is under pending , abort it "); +580608,1189621760,0,0,PS1,NAS_PLMN,CemmPlmnProcAsCapabilityIndSig_1,P_VALUE,swLogPrintf("PLMN , band : %d in NVM , RF is not supported "); +580608,1189623808,0,0,PS1,NAS_PLMN,CemmPlmnProcAsCapabilityIndSig_2,P_VALUE,swLogPrintf("PLMN , band : %d in NVM , RF is not supported "); +580608,1189625856,0,0,PS1,NAS_PLMN,CemmPlmnProcAsCapabilityIndSig_3,P_VALUE,swLogPrintf("PLMN , band : %d in NVM , RF is not supported "); +580608,1189627904,0,0,PS1,NAS_PLMN,CemmPlmnProcAsCapabilityIndSig_4,P_VALUE,swLogPrintf("PLMN , band : %d in NVM , RF is not supported "); +580608,1189631999,0,0,PS1,NAS_PLMN,CemmPlmnProcAsCapabilityIndSig_5,P_WARNING,swLogPrintf("PLMN , no valid band is left , just set current band to RF supported band "); +580608,1189634047,0,0,PS1,NAS_PLMN,CePlmnSetPlmnRegTypeParm_1,P_INFO,swLogPrintf("Still Auto Plmn Reg , No Need To Write Nv "); +580608,1189634560,0,0,PS1,NAS_PLMN,CePlmnSetPlmnRegTypeParm_2,P_VALUE,swLogPrintf("Plmn Select Type is still %d , And the Plmn is still ( 0x%x , 0x%x ) , No Need To Write Nv "); +580608,1189636864,0,0,PS1,NAS_PLMN,CePlmnSetUserDefinedHighPriPlmnTimer_s_1,P_SIG,swLogPrintf("CE PLMN , set / cfg high priority timer , tryNumPresent : %d / tryNum : %d , tValPreset : %d / tValSec : %d "); +580608,1189638400,0,0,PS1,NAS_PLMN,CePlmnSetUserDefinedHighPriPlmnTimer_w_1,P_WARNING,swLogPrintf("CE PLMN , set / cfg high priority timer , tryNum : %d , invalid tValSec : 0x%lx > 0xFFFFF "); +580608,1189640448,0,0,PS1,NAS_PLMN,CePlmnSetUserDefinedHighPriPlmnTimer_w_2,P_WARNING,swLogPrintf("CE PLMN , set / cfg high priority timer , tryNumPresent : %d and tValPresent : %d , should set together "); +580608,1189642240,0,0,PS1,NAS_PLMN,CePlmnSetRoamModeFromNv_1,P_VALUE,swLogPrintf("CE PLMN , Power Up , enableRoam init from NV %d "); +580608,1189644544,0,0,PS1,NAS_PLMN,CePlmnSetRoamMode_1,P_VALUE,swLogPrintf("CE PLMN , set enableRoam from %d to %d "); +580608,1189648383,0,0,PS1,NAS_PLMN,CePlmnSetRoamMode_2,P_VALUE,swLogPrintf("CE PLMN , roaming mode is changed and take effect immediately "); +580608,1189650431,0,0,PS1,NAS_PLMN,CePlmnSetRoamMode_3,P_VALUE,swLogPrintf("CE PLMN , don ' t need to trigger PLMN selection in Manual mode "); +580608,1189652479,0,0,PS1,NAS_PLMN,CePlmnSetRoamMode_4,P_VALUE,swLogPrintf("CE PLMN , roaming mode will take effect after rebooting "); +580608,1189652480,0,0,PS1,NAS_PLMN,CePlmnSetSavePlmnSelModeFromNv_1,P_VALUE,swLogPrintf("CE PLMN , Power Up , savePlmnSelMode init from NV %d "); +580608,1189656575,0,0,PS1,NAS_PLMN,CePlmnSetSavePlmnSelModeFromNv_2,P_INFO,swLogPrintf("CE PLMN , Power Up , reset PLMN select Mode to Auto "); +580608,1189656832,0,0,PS1,NAS_PLMN,CePlmnSetSavePlmnSelMode_1,P_VALUE,swLogPrintf("CE PLMN , set savePlmnSelMode from %d to %d "); +580608,1189658880,0,0,PS1,NAS_PLMN,CePlmnProcWiFiScan_1,P_VALUE,swLogPrintf("PLMN , WiFiScan , AS state ( %d ) , wifiPriority : %d "); +580608,1189662719,0,0,PS1,NAS_PLMN,CePlmnProcWiFiScan_2,P_INFO,swLogPrintf("PLMN , WiFiScan , WiFi pref , force to do IDLE "); +580608,1189664767,0,0,PS1,NAS_PLMN,CePlmnProcWiFiScan_3,P_INFO,swLogPrintf("PLMN , WiFiScan , DATA pref , waiting for RRC release "); +580608,1189664768,0,0,PS1,NAS_PLMN,CePlmnStartWiFiScanReqSig_1,P_VALUE,swLogPrintf("PLMN , WiFiScan , Receive SIG_CEMM_START_WIFISCAN_REQ , Priority : %d "); +580608,1189666816,0,0,PS1,NAS_PLMN,CePlmnProcStartWiFiScanReq_1,P_VALUE,swLogPrintf("PLMN , WiFiScan , PLMN / WiFi search pending ( %d ) , reject this WiFiScan request "); +580608,1189668864,0,0,PS1,NAS_PLMN,CePlmnProcStartWiFiScanReq_2,P_VALUE,swLogPrintf("PLMN , WiFiScan , current WiFiScan is ongoing , state : %d , reject this WiFiScan request "); +580608,1189671168,0,0,PS1,NAS_PLMN,CePlmnProcStartWiFiScanReq_3,P_VALUE,swLogPrintf("PLMN , WiFiScan , current PLMN search ( %d ) is ongoing ( %d ) , pending this WiFi scan "); +580608,1189675007,0,0,PS1,NAS_PLMN,CePlmnAbortWiFiScanReqSig_1,P_VALUE,swLogPrintf("PLMN , WiFiScan , Receive SIG_CEMM_ABORT_WIFISCAN_REQ "); +580608,1189677055,0,0,PS1,NAS_PLMN,CePlmnAbortWiFiScanReqSig_2,P_INFO,swLogPrintf("PLMN , WiFiScan , discard the pending WiFiScan if there is "); +580608,1189679103,0,0,PS1,NAS_PLMN,CePlmnAbortWiFiScanReqSig_3,P_INFO,swLogPrintf("PLMN , WiFiScan , abort RRC "); +580608,1189679104,0,0,PS1,NAS_PLMN,CePlmnProcCerrcWiFiScanCnfSig_1,P_VALUE,swLogPrintf("PLMN , WiFiScan , Receive SIG_CERRC_WIFI_SCAN_CNF , WiFiScanProcStatus : %d "); +580608,1189681152,0,0,PS1,NAS_PLMN,CePlmnProcCerrcAbortWiFiScanCnfSig_1,P_VALUE,swLogPrintf("PLMN , WiFiScan , Receive SIG_CERRC_ABORT_WIFI_SCAN_CNF , WiFiScanProcStatus : %d "); +580608,1189685247,0,0,PS1,NAS_PLMN,CePlmnProcCellCampIndMsg_1,P_INFO,swLogPrintf("PLMN , WiFiScan , start the WiFi Scan. "); +585728,1199575039,0,0,PS1,UICC,UiccCtrlCheckPinEnable_0,P_INFO,swLogPrintf("universal PIN or PIN1 is enable "); +585728,1199575808,0,0,PS1,UICC,UiccCtrlVotePmuState_0,P_INFO,swLogPrintf("bSimPowerSave %d , bSimSleep %d , usatCmdOngoing %d , bipSessionOpen %d , UiccCtrl Voted deep sleep not allowed "); +585728,1199577089,0,0,PS1,UICC,UiccTimerExpiryTrace_0,P_VALUE,swLogPrintf("%s expired "); +585728,1199581183,0,0,PS1,UICC,UiccCtrlHandleTimerExpiry_1,P_SIG,swLogPrintf("UICC presence detect timer expired , send STATUS command "); +585728,1199583231,0,0,PS1,UICC,UiccCtrlHandleTimerExpiry_2,P_INFO,swLogPrintf("UICC presence detect not required as UICC was not active "); +585728,1199583488,0,0,PS1,UICC,UiccCtrlCheckTestCard_0,P_INFO,swLogPrintf("UICC , MCC : 0x%lx , MNC : 0x%lx "); +585728,1199585536,0,0,PS1,UICC,UiccCtrlCheckTestCard_1,P_SIG,swLogPrintf("UICC , MCC : 0x%lx , MNC : 0x%lx , is a TEST SIM "); +585728,1199587584,0,0,PS1,UICC,UiccCtrlHandleUnexpectedSignal_0,P_VALUE,swLogPrintf("UiccCtrl , Handle unexpected signal 0x%x on state %d "); +585728,1199589376,0,0,PS1,UICC,UiccCtrlHandleUnexpectedSignal_1,P_WARNING,swLogPrintf("UiccCtrl , unexpected signal 0x%x will be destroyed without cnf "); +585728,1199591424,0,0,PS1,UICC,UiccCtrlNotifyCardRemoved_1,P_VALUE,swLogPrintf("UICC Card removed with cause : %d "); +585728,1199593472,0,0,PS1,UICC,UiccCtrlHandleCardInserted_1,P_ERROR,swLogPrintf("Select MF error , SW : %x , it ' s an invalid card! Terminate it... "); +585728,1199597567,0,0,PS1,UICC,UiccCtrlStart3GSession_0,P_ERROR,swLogPrintf("The IMSI is invalid , so the uicc intialization failed! "); +585728,1199599615,0,0,PS1,UICC,UiccCtrlStart3GSession_1,P_INFO,swLogPrintf("The access control class is invalid "); +585728,1199599872,0,0,PS1,UICC,UiccCtrlStart3GSession_acl1,P_VALUE,swLogPrintf("CemmsimAppReadyInd bAclEnable : %d , aclRawDataLen %d "); +585728,1199603711,0,0,PS1,UICC,UiccCtrlStart3GSession_2,P_SIG,swLogPrintf("The Uicc initialized OK , send CemmSimAppReadyInd! The USIM is ready...... "); +585728,1199605759,0,0,PS1,UICC,UiccCtrlStart3GSession_3,P_ERROR,swLogPrintf("The uicc initialisation failed!! Cannot send SIM ready to CEMM! "); +585728,1199607807,0,0,PS1,UICC,HandleUiccCtrlInitState_0,P_INFO,swLogPrintf("The USIM power on start.... "); +585728,1199609855,0,0,PS1,UICC,HandleUiccCtrlInitState_1,P_INFO,swLogPrintf("The card is detected , start initialization... "); +585728,1199611903,0,0,PS1,UICC,HandleUiccCtrlInitState_2,P_ERROR,swLogPrintf("The USIM is not detected , please check the card plugged in well!! "); +585728,1199613951,0,0,PS1,UICC,HandleUiccCtrlInitState_3,P_ERROR,swLogPrintf("The USIM is removed! Please check if the usim card is plugged out! "); +585728,1199613952,0,0,PS1,UICC,HandleUiccCtrlInitState_timer,P_WARNING,swLogPrintf("UICC presence detect timer ( sigId : 0x%x ) triggers recovery the UICC after wakeup from HIB / sleep2 "); +585728,1199616256,0,0,PS1,UICC,HandleUiccCtrlInitState_4,P_VALUE,swLogPrintf("bUSimActive %d , leaveSleepMode %d "); +585728,1199618048,0,0,PS1,UICC,HandleUiccCtrlInitState_5,P_WARNING,swLogPrintf("Signal ( sigId : 0x%x ) triggers recovery the UICC after wakeup from HIB / sleep2... "); +585728,1199620352,0,0,PS1,UICC,HandleUiccCtrlAppActiveState_error,P_INFO,swLogPrintf("UiccCtrl , stop recovery retry as error occurred %d times , or reqSignal 0x%x "); +585728,1199624191,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_0,P_SIG,swLogPrintf("Enter UICC Recovery procedure "); +585728,1199626239,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_1,P_INFO,swLogPrintf("The initial communiation with card is estabilshed , start initialization for recovery... "); +585728,1199628287,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_110,P_INFO,swLogPrintf("The Uicc resumed status ok... "); +585728,1199628544,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_verifyPin,P_ERROR,swLogPrintf("Uicc recovery with PIN verify failed , cmdStatus : %x , status words : %x! "); +585728,1199632383,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_2,P_ERROR,swLogPrintf("Select usim application failed!... "); +585728,1199634431,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_3,P_ERROR,swLogPrintf("The IMSI is invalid , so the uicc intialization failed! "); +585728,1199636479,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_get_iccid,P_WARNING,swLogPrintf("The ICCID is invalid , uicc intialization failed "); +585728,1199638527,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_4,P_INFO,swLogPrintf("The uicc initialized OK... "); +585728,1199640575,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_5,P_ERROR,swLogPrintf("UICC card changed "); +585728,1199642623,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_6,P_SIG,swLogPrintf("UICC recovery done "); +585728,1199642880,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_7,P_WARNING,swLogPrintf("Select MF error , uiccCtrlData->cmdStatus : %d , SW : %x "); +585728,1199646719,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_8,P_WARNING,swLogPrintf("unexpected signal , destroy it "); +585728,1199648767,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_9,P_WARNING,swLogPrintf("UICC error occurred or card removed "); +585728,1199649024,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_10,P_WARNING,swLogPrintf("UICC recovery failed status : %d , recovery times : %d "); +585728,1199652863,0,0,PS1,UICC,HandleUiccCtrlRecoveryState_11,P_WARNING,swLogPrintf("UICC recovery failed , notify card removed "); +585728,1199654911,0,0,PS1,UICC,UiccCtrlRealSimEntry_0,P_INFO,swLogPrintf("Enter real sim process "); +585728,1199655168,0,0,PS1,UICC,UiccCtrlStartTimer_debug,P_VALUE,swLogPrintf("timer : %d start , timerPeriod : %d "); +585728,1199656960,0,0,PS1,UICC,UiccCtrlStartTimer_1,P_VALUE,swLogPrintf("timer : %d is already started! "); +585728,1199659008,0,0,PS1,UICC,UiccCtrlStopTimer_debug,P_VALUE,swLogPrintf("timer : %d stop "); +585728,1199663103,0,0,PS1,UICC,UiccCtrlTaskEntry_0,P_INFO,swLogPrintf("Enter UiccCtrl task , start init.... "); +585728,1199665151,0,0,PS1,UICC,CountUiccExecuteWriteCmd_0,P_VALUE,swLogPrintf("SIM write counter is not enable , ignore it "); +585728,1199665152,0,0,PS1,UICC,ResetUiccCmdStatus_1,P_VALUE,swLogPrintf("Bad cmdStatus ( %d ) cannot be reset as normal , maybe should recovery uicc... "); +585728,1199667456,0,0,PS1,UICC,ParseUiccStatusWords_1,P_WARNING,swLogPrintf("Invalid status words : %x %x! "); +585728,1199669248,0,0,PS1,UICC,ParseUiccEFTotalFileSize_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199671296,0,0,PS1,UICC,ParseUiccEFTotalFileSize_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199673344,0,0,PS1,UICC,ParseUiccDfName_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199675392,0,0,PS1,UICC,ParseUiccDfName_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199677440,0,0,PS1,UICC,ParseUiccDirId_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199679488,0,0,PS1,UICC,ParseUiccDirId_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199681536,0,0,PS1,UICC,ParseUiccDirFileDescriptor_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199683584,0,0,PS1,UICC,ParseUiccDirFileDescriptor_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199685632,0,0,PS1,UICC,ParseUiccDirSecurityAttributes_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199687680,0,0,PS1,UICC,ParseUiccUsageQualifier_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199689728,0,0,PS1,UICC,ParseUiccUsageQualifier_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199691776,0,0,PS1,UICC,ParseUiccKeyReference_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199693824,0,0,PS1,UICC,ParseUiccKeyReference_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199695872,0,0,PS1,UICC,ParseUiccPinStatusTemplateDO_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199698432,0,0,PS1,UICC,UpdateUiccPinStatus_debug,P_VALUE,swLogPrintf("keyRef 0x%x , usePin %d , enabled %d "); +585728,1199699968,0,0,PS1,UICC,ParseUiccCharacteristics_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199702016,0,0,PS1,UICC,ParseUiccCharacteristics_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199704064,0,0,PS1,UICC,ParseEfFileDescriptor_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199706112,0,0,PS1,UICC,ParseEfFileDescriptor_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199708160,0,0,PS1,UICC,ParseEfFileId_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199710208,0,0,PS1,UICC,ParseEfFileId_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199712256,0,0,PS1,UICC,ParseUiccAppPowerConsumption_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199714304,0,0,PS1,UICC,ParseUiccAppPowerConsumption_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199716352,0,0,PS1,UICC,ParseUiccMinClockFrequency_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199718400,0,0,PS1,UICC,ParseUiccMinClockFrequency_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199720448,0,0,PS1,UICC,ParseUiccMemAvailable_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199722496,0,0,PS1,UICC,ParseUiccFileProprietaryInfo_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199724544,0,0,PS1,UICC,ParseFileLifeCycleStatus_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199726592,0,0,PS1,UICC,ParseFileLifeCycleStatus_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199728640,0,0,PS1,UICC,ParseEfCompactFormat_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199730688,0,0,PS1,UICC,ParseEfCompactFormat_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199732736,0,0,PS1,UICC,ParseUiccKeyRef_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199734784,0,0,PS1,UICC,ParseUiccKeyRef_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199736832,0,0,PS1,UICC,ParseUiccEfExpandedFormat_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199738880,0,0,PS1,UICC,ParseUiccRefToExpandedFormat_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199740928,0,0,PS1,UICC,ParseUiccFileSize_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199742976,0,0,PS1,UICC,ParseUiccFileSize_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199745024,0,0,PS1,UICC,ParseUiccTotalDirFileSize_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199747072,0,0,PS1,UICC,ParseUiccSfi_1,P_WARNING,swLogPrintf("unexpected tag : %x "); +585728,1199749120,0,0,PS1,UICC,ParseUiccSfi_2,P_WARNING,swLogPrintf("wrong length : %x "); +585728,1199751424,0,0,PS1,UICC,ParseUiccEfFcp_0,P_VALUE,swLogPrintf("abnormal fcp length 0x%x , rspdata length 0x%x "); +585728,1199753216,0,0,PS1,UICC,ParseUiccEfFcp_1,P_VALUE,swLogPrintf("ignore unknown EF fcp tag 0x%x "); +585728,1199757311,0,0,PS1,UICC,ParseUiccSelectEfResponse_1,P_VALUE,swLogPrintf("parse EF FCP error "); +585728,1199757312,0,0,PS1,UICC,ParseUiccDirFcp_1,P_VALUE,swLogPrintf("ignore unknown ADF / DF fcp tag 0x%x "); +585728,1199759616,0,0,PS1,UICC,ParseUiccSelectDirResponse_0,P_VALUE,swLogPrintf("saved currentlySelectedDir : %x , decode fileOperaData.currentDir : %x "); +585728,1199761408,0,0,PS1,UICC,ExecuteUiccSelectCommand_1,P_ERROR,swLogPrintf("Unsupport select menthod : 0x%x "); +585728,1199763456,0,0,PS1,UICC,ExecuteUiccSelectCommand_2,P_INFO,swLogPrintf("Abnormal cmdstatus : %d "); +585728,1199765504,0,0,PS1,UICC,ExecuteUiccStatusCommand_1,P_INFO,swLogPrintf("Abnormal cmdstatus : %d "); +585728,1199767552,0,0,PS1,UICC,ExecuteUiccReadBinaryCommand_1,P_WARNING,swLogPrintf("EF %x met file size as 0 !!! "); +585728,1199770112,0,0,PS1,UICC,ExecuteUiccReadBinaryCommand_2,P_INFO,swLogPrintf("Abnormal SW : %x when read EF : %x , cmd status change : %d "); +585728,1199771904,0,0,PS1,UICC,ExecuteUiccReadBinaryCommand_3,P_INFO,swLogPrintf("Abnormal EF Id : %x or cmdstatus : %d "); +585728,1199773696,0,0,PS1,UICC,ExecuteUiccUpdateBinaryCommand_0,P_ERROR,swLogPrintf("EF %x met file size as 0 !!! "); +585728,1199775744,0,0,PS1,UICC,ExecuteUiccUpdateBinaryCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned when UPDATE BINARY CMD execute "); +585728,1199778048,0,0,PS1,UICC,ExecuteUiccUpdateBinaryCommand_2,P_INFO,swLogPrintf("Abnormal EF Id : %x or cmdstatus : %d "); +585728,1199779840,0,0,PS1,UICC,ExecuteUiccReadRecordCommand_0,P_ERROR,swLogPrintf("EF %x met file record length as 0 "); +585728,1199781888,0,0,PS1,UICC,ExecuteUiccReadRecordCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned when READ RECORD CMD execute "); +585728,1199784192,0,0,PS1,UICC,ExecuteUiccReadRecordCommand_2,P_INFO,swLogPrintf("Abnormal EF Id : %x or cmdstatus : %d "); +585728,1199785984,0,0,PS1,UICC,ExecuteUiccUpdateRecordCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned when UPDATE RECORD CMD execute "); +585728,1199788288,0,0,PS1,UICC,ExecuteUiccUpdateRecordCommand_2,P_INFO,swLogPrintf("Abnormal EF Id : %x or cmdstatus : %d "); +585728,1199790080,0,0,PS1,UICC,ExecuteUiccSearchRecordCommand_0,P_ERROR,swLogPrintf("EF %x met file record length as 0 "); +585728,1199792128,0,0,PS1,UICC,ExecuteUiccSearchRecordCommand_1,P_VALUE,swLogPrintf("Abnormal statusWords : %x is returned "); +585728,1199794432,0,0,PS1,UICC,ExecuteUiccSearchRecordCommand_2,P_INFO,swLogPrintf("Abnormal EF Id : %x or cmdstatus : %d "); +585728,1199796480,0,0,PS1,UICC,ExecuteUiccAuthenticateCommand_0,P_INFO,swLogPrintf("Current directory %x is not USIM ADF , adfUsimId %x "); +585728,1199800319,0,0,PS1,UICC,ExecuteUiccAuthenticateCommand_1,P_WARNING,swLogPrintf("SYNC failure!!! "); +585728,1199802367,0,0,PS1,UICC,ExecuteUiccAuthenticateCommand_2,P_WARNING,swLogPrintf("Unknown response data!! "); +585728,1199802368,0,0,PS1,UICC,ExecuteUiccAuthenticateCommand_3,P_WARNING,swLogPrintf("Abnormal SW : %x returned "); +585728,1199804416,0,0,PS1,UICC,ExecuteSuspendUiccCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned. "); +585728,1199806464,0,0,PS1,UICC,ExecuteUiccManageChannelCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned. "); +585728,1199808512,0,0,PS1,UICC,ExecuteUiccGenAccessCommand_1,P_INFO,swLogPrintf("Abnormal cmdStatus %d "); +585728,1199810816,0,0,PS1,UICC,ExecuteUiccGenLogicalChAccessCommand_1,P_INFO,swLogPrintf("Abnormal cmdStatus : %x , SW : %x "); +585728,1199812608,0,0,PS1,UICC,ExecuteUiccTerminalProfileCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned "); +585728,1199814656,0,0,PS1,UICC,ExecuteUiccFetchCommand_1,P_WARNING,swLogPrintf("Abnormal SW : %x is returned. "); +585728,1199818751,0,0,PS1,UICC,ReceiveUiccDrvSignal_1,P_WARNING,swLogPrintf("Uicc clock stop timer has already been stopped! "); +585728,1199820799,0,0,PS1,UICC,ReceiveUiccDrvSignal_2,P_ERROR,swLogPrintf("Uicc polling and presence detect timer has already been stopped! "); +585728,1199822847,0,0,PS1,UICC,ReceiveUiccDrvSignal_3,P_ERROR,swLogPrintf("Uicc wait response timer has already been stopped! "); +585728,1199824895,0,0,PS1,UICC,ReceiveUiccDrvSignal_4,P_ERROR,swLogPrintf("Uicc waitting response timer expired , try recovery "); +585728,1199824896,0,0,PS1,UICC,TransceiveUiccCtrlDrvCmdRsp_1,P_WARNING,swLogPrintf("Uiccctrl cmdStatus : %x , set uicc recovery flag "); +585728,1199828991,0,0,PS1,UICC,TransceiveUiccCtrlDrvCmdRsp_2,P_WARNING,swLogPrintf("Destory CARD_INSERTED_IND for reset frequency "); +585728,1199828992,0,0,PS1,UICC,TransceiveUiccCtrlDrvCmdRsp_3,P_WARNING,swLogPrintf("unexpected signal 0x%x recvd here "); +585728,1199833087,0,0,PS1,UICC,TransceiveUiccCtrlDrvCmdRsp_4,P_INFO,swLogPrintf("Change uicc state to init as unexpected card removed Ind recved "); +585728,1199833088,0,0,PS1,UICC,UiccCtrlClearUiccDrvSignal_1,P_VALUE,swLogPrintf("destroy drv signal %x "); +585728,1199837183,0,0,PS1,UICC,DecodeDialNumberParams_1,P_INFO,swLogPrintf("All data is unused bytes FF , no valid dial number "); +585728,1199839231,0,0,PS1,UICC,DecodeDialNumberParams_2,P_INFO,swLogPrintf("All alphaId is unused bytes FF "); +585728,1199841279,0,0,PS1,UICC,DecodeDialNumberParams_3,P_INFO,swLogPrintf("All dialling number is unused bytes FF "); +585728,1199841280,0,0,PS1,UICC,ReadUiccMaxPowerConsumption_1,P_INFO,swLogPrintf("Uicc suspension procedure supported flag : %d "); +585728,1199845375,0,0,PS1,UICC,ReadEpsNscInfo_1,P_WARNING,swLogPrintf("Usim service num_85 ( EMM Info ) is not available "); +585728,1199845376,0,0,PS1,UICC,ReadEpsNscInfo_2,P_INFO,swLogPrintf("Reset command status when read EpsNscInfo cmdstatus : %d "); +585728,1199849471,0,0,PS1,UICC,ReadLoci_0,P_WARNING,swLogPrintf("MCC / MNC check failed as not digit "); +585728,1199849472,0,0,PS1,UICC,ReadLoci_1,P_INFO,swLogPrintf("Reset command status : %d as ok. "); +585728,1199853567,0,0,PS1,UICC,ReadEpsLoci_1,P_WARNING,swLogPrintf("Usim service num_85 ( EMM Info ) is not available "); +585728,1199855615,0,0,PS1,UICC,ReadEpsLoci_check_guti,P_WARNING,swLogPrintf("GUTI MCC / MNC check failed as not digit "); +585728,1199857663,0,0,PS1,UICC,ReadEpsLoci_check_TAI,P_WARNING,swLogPrintf("GUTI MCC / MNC check failed as not digit "); +585728,1199857664,0,0,PS1,UICC,ReadEpsLoci_2,P_INFO,swLogPrintf("Reset command status : %d as ok. "); +585728,1199859968,0,0,PS1,UICC,ReadAccessCtrlInfo_1,P_INFO,swLogPrintf("Read EF_ACC with SW : 0x%x cmdStatus : %d "); +585728,1199861760,0,0,PS1,UICC,ReadAccessCtrlInfo_2,P_WARNING,swLogPrintf("cmdStatus : %d incorrect can not Read EF_ACC "); +585728,1199863808,0,0,PS1,UICC,ReadLrPlmnsi_1,P_INFO,swLogPrintf("Reset command status : %d to ok "); +585728,1199865856,0,0,PS1,UICC,ReadHpplmnSearchPeriod_1,P_INFO,swLogPrintf("Reset command status : %d to ok "); +585728,1199868672,0,0,PS1,UICC,ReadPlmnData_3,P_INFO,swLogPrintf("UICC READ DATA status : %d , totalEntries : %d , numValidEntries : %d , startFieldNum : %d "); +585728,1199869952,0,0,PS1,UICC,ReadPlmnData_1,P_ERROR,swLogPrintf("Service table for ( PlmnFileId : %x ) is not available "); +585728,1199872000,0,0,PS1,UICC,ReadNasConfigParams_1,P_INFO,swLogPrintf("Reset command status : %d to ok "); +585728,1199874048,0,0,PS1,UICC,ReadKeysPs_1,P_WARNING,swLogPrintf("Read EFkeyPS failed , cmdstatus : %d , ignore it.. , "); +585728,1199878143,0,0,PS1,UICC,ReadSmspReq_1,P_WARNING,swLogPrintf("UST for EFSmsp is not available "); +585728,1199878400,0,0,PS1,UICC,ReadSmspReq_2,P_WARNING,swLogPrintf("Record error , read record number : %d , all file records : %d "); +585728,1199882239,0,0,PS1,UICC,ReadSmssReq_1,P_WARNING,swLogPrintf("UST for EFSmss is not available "); +585728,1199884287,0,0,PS1,UICC,ReadSmReq_1,P_WARNING,swLogPrintf("UST for EFSms is not available "); +585728,1199884544,0,0,PS1,UICC,ReadSmReq_2,P_INFO,swLogPrintf("requested status %d mismatch with response status %d "); +585728,1199886592,0,0,PS1,UICC,ReadSmReq_3,P_WARNING,swLogPrintf("Record error , read record number : %d , all file records : %d "); +585728,1199890431,0,0,PS1,UICC,GetSmsRecordNumsReq_1,P_WARNING,swLogPrintf("UST for EFsms is not available "); +585728,1199892479,0,0,PS1,UICC,ReadMsisdnReq_1,P_WARNING,swLogPrintf("USIM service table of EFmsisdn is not available "); +585728,1199892736,0,0,PS1,UICC,ReadMsisdnReq_2,P_WARNING,swLogPrintf("Record error , read record number : %d , all file records : %d "); +585728,1199894528,0,0,PS1,UICC,UpdateUserPlmnActReq_1,P_WARNING,swLogPrintf("No free location , offset %d file size "); +585728,1199898623,0,0,PS1,UICC,UpdateUserPlmnActReq_2,P_WARNING,swLogPrintf("EFplmnwAcT is not available in UST "); +585728,1199900671,0,0,PS1,UICC,UpdateEpsLociReq_1,P_WARNING,swLogPrintf("Usim service num_85 ( EMM Info ) is not available "); +585728,1199902719,0,0,PS1,UICC,UpdateEpsNscReq_1,P_WARNING,swLogPrintf("Usim service num_85 ( EMM Info ) is not available "); +585728,1199904767,0,0,PS1,UICC,UpdateSmspReq_0,P_WARNING,swLogPrintf("UST for EFSmsp is not available "); +585728,1199906815,0,0,PS1,UICC,UpdateSmssReq_0,P_WARNING,swLogPrintf("UST for EFSmss is not available "); +585728,1199908863,0,0,PS1,UICC,WriteSmReq_0,P_WARNING,swLogPrintf("UST for EFSms is not available "); +585728,1199910911,0,0,PS1,UICC,WriteSmReq_1,P_INFO,swLogPrintf("No free space found "); +585728,1199912959,0,0,PS1,UICC,DeleteSmReq_0,P_WARNING,swLogPrintf("UST for EFSms is not available "); +585728,1199913216,0,0,PS1,UICC,DeleteSmReq_1,P_INFO,swLogPrintf("requested status %d mismatch with response status %d , do nothing "); +585728,1199915776,0,0,PS1,UICC,UsatGetCurrentTimerValue_0,P_INFO,swLogPrintf("timerId %d currTicksCount %d usatStartTimerTicks %d uiccCtrlData timerPeriod %d "); +585728,1199917056,0,0,PS1,UICC,UsatGetCurrentTimerValue_1,P_INFO,swLogPrintf("timerId %d not start "); +585728,1199919104,0,0,PS1,UICC,UsatDeactiveTimer_1,P_INFO,swLogPrintf("timerId %d not start "); +585728,1199921152,0,0,PS1,UICC,UsatDecBearDescription_0,P_ERROR,swLogPrintf("Unsupport bearerType %x "); +585728,1199925247,0,0,PS1,UICC,UsatEncCommandResult_0,P_ERROR,swLogPrintf("additInfoData is PNULL while additInfoLen is not 0 ! Ignore it! "); +585728,1199925760,0,0,PS1,UICC,UsatEncDateTimeZone_0,P_INFO,swLogPrintf("utcTimePtr->UTCtimer1 , %d / %d / %d "); +585728,1199928064,0,0,PS1,UICC,UsatEncDateTimeZone_1,P_INFO,swLogPrintf("utcTimePtr->UTCtimer2 , %d : %d : %d+%d "); +585728,1199929344,0,0,PS1,UICC,UsatEncImeiSv_0,P_VALUE,swLogPrintf("unknown Id type %d "); +585728,1199931392,0,0,PS1,UICC,UsatEncEventDownload_0,P_ERROR,swLogPrintf("Currently unsupport event : %x "); +585728,1199933440,0,0,PS1,UICC,UsatProcRefreshCmd_0,P_WARNING,swLogPrintf("Unsupport refresh type %x "); +585728,1199935488,0,0,PS1,UICC,UsatProcRefreshCmd_1,P_VALUE,swLogPrintf("FCN fileId %x "); +585728,1199937536,0,0,PS1,UICC,UsatProcRefreshCmd_2,P_VALUE,swLogPrintf("Current not support FCN fileId %x "); +585728,1199939584,0,0,PS1,UICC,UsatProcProvideLocalInfoCmd_0,P_ERROR,swLogPrintf("Unsupport qualifier ( %x ) of provide local info command "); +585728,1199941632,0,0,PS1,UICC,UsatProcOpenChannelCmd_0,P_ERROR,swLogPrintf("Unknown data field ( tag : %x ) on open channel proactive command! "); +585728,1199945727,0,0,PS1,UICC,UsatProcOpenChannelCmd_1,P_INFO,swLogPrintf("BIP session open "); +585728,1199945728,0,0,PS1,UICC,UsatProcReceiveDataCmd_0,P_ERROR,swLogPrintf("Unknown data field ( tag : %x ) on Receive data channel proactive command! "); +585728,1199947776,0,0,PS1,UICC,UsatProcSendDataCmd_0,P_ERROR,swLogPrintf("Unknown data field ( tag : %x ) on send data channel proactive command! "); +585728,1199951871,0,0,PS1,UICC,UsatProcTimerExpiration_1,P_INFO,swLogPrintf("finish usat timer expiration process "); +585728,1199952128,0,0,PS1,UICC,UiccCtrlHandleUsatFetchReq_0,P_WARNING,swLogPrintf("proactive command fetch failed as pendingFetch %d , isPoweringdown %d "); +585728,1199955967,0,0,PS1,UICC,UiccCtrlHandleUsatFetchReq_1,P_WARNING,swLogPrintf("Decode length field error , length is 0 ... "); +585728,1199955968,0,0,PS1,UICC,UiccCtrlHandleUsatFetchReq_2,P_VALUE,swLogPrintf("Fetched USAT proactive command type : 0x%x "); +585728,1199958016,0,0,PS1,UICC,UiccCtrlHandleUsatFetchReq_3,P_VALUE,swLogPrintf("USAT proactive command failed , usatcmdResult %d "); +585728,1199962111,0,0,PS1,UICC,UiccCtrlHandleSmsPpDownloadReq_1,P_WARNING,swLogPrintf("sms pp download in usim service table is disabled. "); +585728,1199964159,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_1,P_WARNING,swLogPrintf("mosms in usim service table is disabled. "); +585728,1199964160,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_2,P_INFO,swLogPrintf("response present or not ( %d ) for mo control envelop cmd "); +585728,1199968255,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_3,P_WARNING,swLogPrintf("sc address is not gotten from usat control cnf. "); +585728,1199970303,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_4,P_WARNING,swLogPrintf("dest address is not gotten from usat control cnf. "); +585728,1199972351,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_5,P_INFO,swLogPrintf("mo sms info present in resp data. "); +585728,1199974399,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_6,P_WARNING,swLogPrintf("mo sms info is not present in resp data. "); +585728,1199974400,0,0,PS1,UICC,UiccCtrlHandleMoSmsCtrlReq_7,P_WARNING,swLogPrintf("cmdResult for mo sms control is : %d "); +585728,1199978495,0,0,PS1,UICC,UiccCtrlHandleTeminateSessionReq_0,P_INFO,swLogPrintf("Ignor the error status for power down "); +585728,1199978752,0,0,PS1,UICC,UiccCtrlHandleTeminateSessionReq_1,P_INFO,swLogPrintf("Skip terminate USIM APP by select ADF for errorStateOccurred : %d or tsCause : %d "); +585728,1199980544,0,0,PS1,UICC,UiccCtrlHandlePinOperateReq_1,P_VALUE,swLogPrintf("Unsupport pinKeyReference %d "); +585728,1199982592,0,0,PS1,UICC,UiccCtrlHandleCcmReadDataReq_1,P_WARNING,swLogPrintf("Unsupported request item %d "); +585728,1199986687,0,0,PS1,UICC,UiccCtrlHandleCcmUpdateDataReq_1,P_ERROR,swLogPrintf("Unknown Update data Item !! "); +585728,1199986688,0,0,PS1,UICC,UiccCtrlHandleGenAccessReq_0,P_INFO,swLogPrintf("cannot process due to cmdstatus %d "); +585728,1199988992,0,0,PS1,UICC,UiccCtrlHandleGenAccessReq_1,P_VALUE,swLogPrintf("current EF : %x , current Generic access EF : %x "); +585728,1199990784,0,0,PS1,UICC,UiccCtrlHandleGenAccessReq_2,P_VALUE,swLogPrintf("SELECT 2 FXX by fileid , but current dir : %x "); +585728,1199992832,0,0,PS1,UICC,UiccCtrlHandleGenAccessReq_3,P_VALUE,swLogPrintf("saved current Generic access EF : %x "); +585728,1199995136,0,0,PS1,UICC,UiccCtrlHandleGenAccessReq_4,P_INFO,swLogPrintf("select path return SW %x%x "); +585728,1199997184,0,0,PS1,UICC,UiccCtrlHandleGenAccessReq_5,P_INFO,swLogPrintf("return data invalid , rspApduLen : %d , rspApdu : %x "); +585728,1200001023,0,0,PS1,UICC,UiccCtrlHandleSimSleepReq_0,P_SIG,swLogPrintf("not allow SIM sleep , send STATUS command to detect SIM "); +585728,1200003071,0,0,PS1,UICC,UiccCtrlHandleSimWriteCntReq_1,P_VALUE,swLogPrintf("operation not allowed by SWC disable "); +585728,1200005119,0,0,PS1,UICC,UiccCtrlHandleSimWriteCntReq_2,P_WARNING,swLogPrintf("pSwcList is NULL "); +585728,1200007167,0,0,PS1,UICC,UiccCtrlHandleSimWriteCntReq_3,P_VALUE,swLogPrintf("operation not allowed by SWC disable "); +585728,1200009215,0,0,PS1,UICC,UiccCtrlHandleSimWriteCntReq_4,P_WARNING,swLogPrintf("pSwcList is NULL "); +585728,1200009216,0,0,PS1,UICC,UiccCtrlHandleSimWriteCntReq_5,P_VALUE,swLogPrintf("unsupport write counter mode : %d "); +585728,1200011776,0,0,PS1,UICC,UiccCtrlHandleSetSimParamReq_0,P_VALUE,swLogPrintf("simSimuPresent %d , bSimSimulator %d , bUsimSimulator %d "); +585728,1200013824,0,0,PS1,UICC,UiccCtrlHandleSetSimParamReq_1,P_VALUE,swLogPrintf("simSimuPresent %d , bSimSimulator %d , bUsimSimulator %d "); +585728,1200017407,0,0,PS1,UICC,UiccCtrlHandleMmReadDataReq_1,P_ERROR,swLogPrintf("Unknown read data Item !! "); +585728,1200019455,0,0,PS1,UICC,UiccCtrlHandleMmWriteDataReq_1,P_ERROR,swLogPrintf("Unknown Update data Item !! \n "); +585728,1200019456,0,0,PS1,UICC,UiccCtrlHandleMmAuthReq_1,P_ERROR,swLogPrintf("Authentication error , SW : %x , will enter uicc recovery procedure! "); +585728,1200021760,0,0,PS1,UICC,UiccCtrlHandlePowerReduceInd_0,P_ERROR,swLogPrintf("Cannot deactivate the uicc , suspension support : %x , PIN status : %x! "); +585728,1200024064,0,0,PS1,UICC,UiccCtrlHandlePowerReduceInd_1,P_WARNING,swLogPrintf("Cannot deactivate the uicc , suspension support : %x , PIN status : %x , additional info : %x in EFad! "); +585728,1200027647,0,0,PS1,UICC,UiccCtrlHandlePowerReduceInd_2,P_SIG,swLogPrintf("Leave PSM / EDRX , make uicc recovery "); +585728,1200027648,0,0,PS1,UICC,UiccCtrlHandlePowerReduceInd_3,P_ERROR,swLogPrintf("Unknown type : %x! "); +585728,1200029952,0,0,PS1,UICC,UiccCtrlHandlePowerReduceInd_4,P_INFO,swLogPrintf("Ignore it as pUiccCtrlTinyCtx->bSimPowerSave %d bSimSleep %d "); +585728,1200032000,0,0,PS1,UICC,SelectUiccApplication_1,P_WARNING,swLogPrintf("Activate APP returned %d ( 0 -FCI / 1 -FCP ) failed on logical channel %d "); +585728,1200033792,0,0,PS1,UICC,UiccctrlHandleOpenLogicalChannelReq_2,P_INFO,swLogPrintf("unsupport logical channel number %d , current only support standard logical channels 1 -3 "); +585728,1200036096,0,0,PS1,UICC,UiccCtrlHandleGenLogicalChAccessReq_0,P_INFO,swLogPrintf("logical channel access failed reqData->length %d , reqData->logicChNum %d "); +585728,1200038144,0,0,PS1,UICC,UiccCtrlHandleGenLogicalChAccessReq_1,P_INFO,swLogPrintf("logical channel access failed uiccCtrlData->state %d , uiccCtrlData->cmdStatus %d "); +585728,1200040192,0,0,PS1,UICC,UiccCtrlHandleGenLogicalChAccessReq_2,P_INFO,swLogPrintf("return data invalid , rspApduLen : %d , rspApdu : %x "); +585728,1200044031,0,0,PS1,UICC,UsimSimuAppInit_0,P_SIG,swLogPrintf("The Uicc initialized OK , send CemmSimAppReadyInd! The USIM is ready...... "); +585728,1200046079,0,0,PS1,UICC,UsimSimuProcCCMReadData_1,P_INFO,swLogPrintf("Unsupported request Item! "); +585728,1200048127,0,0,PS1,UICC,UsimSimuProcCEMMReadData_1,P_INFO,swLogPrintf("Unsupported request Item! "); +585728,1200048640,0,0,PS1,UICC,UsimSimuSetSimParamReq_0,P_VALUE,swLogPrintf("simSimuPresent %d , bSimSimulator %d , bUsimSimulator %d "); +585728,1200050688,0,0,PS1,UICC,UsimSimuSetSimParamReq_1,P_VALUE,swLogPrintf("simSimuPresent %d , bSimSimulator %d , bUsimSimulator %d "); +585728,1200054271,0,0,PS1,UICC,UsimSimulatorEntry_0,P_WARNING,swLogPrintf("Enter usim simulator / TEST SIM.... "); +585728,1200054784,0,0,PS1,UICC,UiccInterruptServiceRoutine_0,P_INFO,swLogPrintf("IIR : 0x%x , FSR : 0x%x , LSR : 0x%x "); +585728,1200056320,0,0,PS1,UICC,UiccHwCardReset_0,P_WARNING,swLogPrintf("Unknow voltage %d , set as default class C "); +586752,1201672191,0,0,PS1,UICC_DRV,Usim1ClkLatchByAONIO_weak,P_WARNING,swLogPrintf("weak function is unexpected! "); +586752,1201674239,0,0,PS1,UICC_DRV,Usim1GpioConfig_weak,P_WARNING,swLogPrintf("weak function is unexpected! "); +586752,1201674240,0,0,PS1,UICC_DRV,UiccDrvSendErrorIndication_0,P_INFO,swLogPrintf("UiccDrv ErrInd status %d "); +586752,1201678335,0,0,PS1,UICC_DRV,UiccDrvSleepPrepare_0,P_INFO,swLogPrintf("The uicc prepares to enter sleep1 mode "); +586752,1201678336,0,0,PS1,UICC_DRV,UiccDrvSleepPrepare_1,P_INFO,swLogPrintf("The uicc clock has already been stopped as uiccCardState %d "); +586752,1201682431,0,0,PS1,UICC_DRV,UiccDrvSleepPrepare_2,P_INFO,swLogPrintf("USIM CLK Is not Latched , latch it "); +586752,1201684479,0,0,PS1,UICC_DRV,UiccDrvSleepRecovery_0,P_INFO,swLogPrintf("The uicc recover from sleep1 mode "); +586752,1201684736,0,0,PS1,UICC_DRV,UiccPmuCheckDeepSleepAvail_0,P_INFO,swLogPrintf("pUiccDrvData->uiccCardState %d , lowPowerState %d "); +586752,1201688575,0,0,PS1,UICC_DRV,UiccDrvProcPmuDeepSlpDeactivate_0,P_INFO,swLogPrintf("Stop deactivate session since uicctrl vote not allowed for new request "); +586752,1201690623,0,0,PS1,UICC_DRV,UiccDrvProcPmuDeepSlpDeactivate_1,P_INFO,swLogPrintf("Terminate UICC since PS all vote hibernate / sleep "); +586752,1201692671,0,0,PS1,UICC_DRV,UiccDrvProcPmuDeepSlpDeactivate_2,P_INFO,swLogPrintf("The uicc has already been deactivated , nothing to do... "); +586752,1201694719,0,0,PS1,UICC_DRV,UiccDrvPmuDeepSlpEnterCallBack_1,P_WARNING,swLogPrintf("Miss UICC deativation! power off immediately "); +586752,1201694720,0,0,PS1,UICC_DRV,UiccDrvPmuDeepSlpEnterCallBack_2,P_SIG,swLogPrintf("Uicc , prepare to enter : %d , HIB ( 4 ) / SLEEP2 ( 3 ) state "); +586752,1201698815,0,0,PS1,UICC_DRV,UiccDrvTerminateTaskWait_0,P_WARNING,swLogPrintf("Terminate uiccdrv task wait "); +586752,1201698816,0,0,PS1,UICC_DRV,UiccDrvTerminateTaskWait_1,P_WARNING,swLogPrintf("uiccdrv task wait flag set result %d "); +586752,1201702911,0,0,PS1,UICC_DRV,UiccReset_softsim,P_INFO,swLogPrintf("No ATR recvd from softsim "); +586752,1201703168,0,0,PS1,UICC_DRV,UiccDrvHandleDeActivation_0,P_INFO,swLogPrintf("uiccCardState : %x , start to deactivate the uicc card , send remove Ind : %d "); +586752,1201704960,0,0,PS1,UICC_DRV,UiccDecodeATRContent_2,P_VALUE,swLogPrintf("ATR length %d is wrong "); +586752,1201709055,0,0,PS1,UICC_DRV,UiccDecodeATRContent_3,P_WARNING,swLogPrintf("clock stop indicated on HIGH "); +586752,1201709056,0,0,PS1,UICC_DRV,UiccPPSProcedure_3,P_VALUE,swLogPrintf("PPS procedure failed , rs : %d "); +586752,1201713151,0,0,PS1,UICC_DRV,UiccDrvRestartCardClock_0,P_INFO,swLogPrintf("The uicc clock has not been stopped , nothing to do.. "); +586752,1201715199,0,0,PS1,UICC_DRV,UiccDrvRestartCardClock_2,P_INFO,swLogPrintf("USIM CLK is latched , release it "); +586752,1201717247,0,0,PS1,UICC_DRV,UiccDrvRestartCardClock_1,P_WARNING,swLogPrintf("Clock start failed on busy state of UCR_REG! "); +586752,1201719295,0,0,PS1,UICC_DRV,UiccDrvStopCardClock_1,P_INFO,swLogPrintf("The uicc clock has already been stopped "); +586752,1201721343,0,0,PS1,UICC_DRV,UiccDrvHandleClockStopReq_2,P_WARNING,swLogPrintf("Clock stop failed on busy state of UCR_REG... "); +586752,1201723391,0,0,PS1,UICC_DRV,UiccInitCommEst_00,P_INFO,swLogPrintf("The card support class A_B , change to 3 v and reset "); +586752,1201725439,0,0,PS1,UICC_DRV,UiccInitCommEst_0,P_INFO,swLogPrintf("ATR anlyze ok "); +586752,1201727487,0,0,PS1,UICC_DRV,UiccInitCommEst_atr,P_WARNING,swLogPrintf("ATR decode error "); +586752,1201729535,0,0,PS1,UICC_DRV,UiccInitCommEst_ATR_TIMEOUT_TERMINATE,P_INFO,swLogPrintf("Terminate the initial communication "); +586752,1201729792,0,0,PS1,UICC_DRV,UiccInitCommEst_convention_before,P_INFO,swLogPrintf("curr LCR : 0x%x , RBR : 0x%x "); +586752,1201731584,0,0,PS1,UICC_DRV,UiccInitCommEst_convention_after,P_INFO,swLogPrintf("set LCR 0x%x "); +586752,1201735679,0,0,PS1,UICC_DRV,UiccInitCommEst_try_3v,P_INFO,swLogPrintf("no ATR recvd on class_C_1_8v , reset UICC with 3 v "); +586752,1201737727,0,0,PS1,UICC_DRV,UiccInitCommEst_tryMinClck,P_INFO,swLogPrintf("try minclock for UICC "); +586752,1201739775,0,0,PS1,UICC_DRV,UiccInitCommEst_1,P_ERROR,swLogPrintf("no ATR recvd on class_C_1_8V and class_B_3v , UICC detection failed "); +586752,1201741823,0,0,PS1,UICC_DRV,UiccInitCommEst_2,P_ERROR,swLogPrintf("ATR error for reset 3 times on class_B_3v , UICC activation failed "); +586752,1201743871,0,0,PS1,UICC_DRV,UiccInitCommEst_3,P_INFO,swLogPrintf("PPS done "); +586752,1201745919,0,0,PS1,UICC_DRV,UiccInitCommEst_PPS_TIMEOUT_TERMINATE,P_INFO,swLogPrintf("Terminate the initial communication "); +586752,1201745920,0,0,PS1,UICC_DRV,UiccInitCommEst_4,P_INFO,swLogPrintf("The ta1 : 0x%x is invalid or unsupported , set default value "); +586752,1201750015,0,0,PS1,UICC_DRV,UiccInitCommEst_configMinClck,P_INFO,swLogPrintf("configure minclock for PPS "); +586752,1201752063,0,0,PS1,UICC_DRV,UiccInitCommEst_T1_init,P_INFO,swLogPrintf("T1 initiate "); +586752,1201754111,0,0,PS1,UICC_DRV,UiccDrvStartCardInit_1,P_INFO,swLogPrintf("USIM1 starts init "); +586752,1201756159,0,0,PS1,UICC_DRV,UiccDriverInit_1,P_INFO,swLogPrintf("Uiccdrv task starts init... "); +586752,1201756160,0,0,PS1,UICC_DRV,UiccDriverTaskEntry_1,P_ERROR,swLogPrintf("Uicc driver received unexpected signal : %x! "); +586752,1201760255,0,0,PS1,UICC_DRV,UiccDllHandleProcedureByte_3,P_INFO,swLogPrintf("No data recvd "); +586752,1201760256,0,0,PS1,UICC_DRV,UiccDllHandleProcedureByte_4,P_INFO,swLogPrintf("Rx procedure byte : %x "); +586752,1201762304,0,0,PS1,UICC_DRV,UiccDllHandleBwtInterrupt_0,P_VALUE,swLogPrintf("gUiccWtCnt : 0x%x "); +586752,1201764608,0,0,PS1,UICC_DRV,UiccDllHandleBwtInterrupt_1,P_VALUE,swLogPrintf("WTR : 0x%x , EWTR : 0x%x "); +586752,1201768447,0,0,PS1,UICC_DRV,UiccDllHandleBwtInterrupt_setbr,P_WARNING,swLogPrintf("Set baud rate divisior failed "); +586752,1201768704,0,0,PS1,UICC_DRV,UiccDllHandleBwtInterrupt_2,P_VALUE,swLogPrintf("WTR : 0x%x , EWTR : 0x%x "); +586752,1201772543,0,0,PS1,UICC_DRV,UiccDllHandleBwtInterrupt_3,P_VALUE,swLogPrintf("core is not idle , CWT / BWT maybe not trigger again "); +586752,1201772544,0,0,PS1,UICC_DRV,UiccDllHandleCwtInterrupt_0,P_VALUE,swLogPrintf("gUiccWtCnt : 0x%x "); +586752,1201774848,0,0,PS1,UICC_DRV,UiccDllHandleCwtInterrupt_1,P_VALUE,swLogPrintf("WTR : 0x%x , EWTR : 0x%x "); +586752,1201778687,0,0,PS1,UICC_DRV,UiccDllHandleCwtInterrupt_setbr,P_WARNING,swLogPrintf("Set baud rate divisior failed "); +586752,1201778944,0,0,PS1,UICC_DRV,UiccDllHandleCwtInterrupt_2,P_VALUE,swLogPrintf("WTR : 0x%x , EWTR : 0x%x "); +586752,1201782783,0,0,PS1,UICC_DRV,UiccDllHandleCwtInterrupt_3,P_VALUE,swLogPrintf("core is not idle , CWT / BWT maybe not trigger again "); +586752,1201784831,0,0,PS1,UICC_DRV,UiccDllReceiveHandler_0,P_VALUE,swLogPrintf("BWT expired and enable BWT IRQ again "); +586752,1201786879,0,0,PS1,UICC_DRV,UiccDllReceiveHandler_cwt,P_VALUE,swLogPrintf("CWT expired and enable CWT IRQ again "); +586752,1201788927,0,0,PS1,UICC_DRV,UiccDllSendHandler_0,P_ERROR,swLogPrintf("The TX error interrupt occurred... "); +586752,1201790975,0,0,PS1,UICC_DRV,UiccDllSendHandler_1,P_ERROR,swLogPrintf("The TX fifo don ' t have enough space , wait for the next interrupt. "); +586752,1201790976,0,0,PS1,UICC_DRV,UiccDllSendHandler_5,P_VALUE,swLogPrintf("Enable UICC DMA RX , expected data length : %d "); +586752,1201794048,0,0,PS1,UICC_DRV,UiccDllSendHandler_DEBUG,P_INFO,swLogPrintf("FCR 0x%x , TOR 0x%x , IIR 0x%x , FSR 0x%x , DCR 0x%x "); +586752,1201795584,0,0,PS1,UICC_DRV,UiccDllHandleDmaRx_1,P_INFO,swLogPrintf("Uicc DMA expected data length %d , actual recvd data length %d , DCR 0x%x "); +586752,1201797376,0,0,PS1,UICC_DRV,UiccDllHandleDmaRx_1_debug,P_INFO,swLogPrintf("CGR 0x%x , DCR 0x%x "); +586752,1201799168,0,0,PS1,UICC_DRV,UiccDllHandleDmaRx_3,P_INFO,swLogPrintf("recv the remianing %d bytes by IRQ "); +586752,1201803263,0,0,PS1,UICC_DRV,UiccDllSendRecvDataFunc_0,P_ERROR,swLogPrintf("The DMA TX in busy state... "); +586752,1201803264,0,0,PS1,UICC_DRV,UiccDllSendRecvDataFunc_1,P_INFO,swLogPrintf("TX DMA trans length %d "); +586752,1201807359,0,0,PS1,UICC_DRV,UiccDllSendRecvDataFunc_terminate,P_INFO,swLogPrintf("Get terminate flag by no response timer expired. "); +586752,1201807360,0,0,PS1,UICC_DRV,UiccDllSendRecvDataFunc_3,P_ERROR,swLogPrintf("Unexpected task wait flag : 0x%x... "); +586752,1201811455,0,0,PS1,UICC_DRV,UiccDllSendRecvDataFunc_4,P_INFO,swLogPrintf("Rx error! "); +586752,1201811712,0,0,PS1,UICC_DRV,UiccDllSendRecvDataFunc_5,P_INFO,swLogPrintf("send & recv abnormal , uiccDlState : %d , uiccParityErrCnt : %d "); +586752,1201813504,0,0,PS1,UICC_DRV,UiccDllDecodeT1SBlock_0,P_WARNING,swLogPrintf("Unknown S-Block type ( 0x%x ) ! "); +586752,1201817599,0,0,PS1,UICC_DRV,UiccDllDecodeT1Response_0,P_ERROR,swLogPrintf("Decode error! "); +586752,1201819647,0,0,PS1,UICC_DRV,UiccDllDecodeT1Response_1,P_INFO,swLogPrintf("I-block! "); +586752,1201821695,0,0,PS1,UICC_DRV,UiccDllDecodeT1Response_2,P_INFO,swLogPrintf("R-block! "); +586752,1201823743,0,0,PS1,UICC_DRV,UiccDllDecodeT1Response_3,P_INFO,swLogPrintf("S-block! "); +586752,1201823744,0,0,PS1,UICC_DRV,UiccDllDecodeT1Response_4,P_ERROR,swLogPrintf("Error : unknown block type ( %x ) !!! "); +586752,1201827839,0,0,PS1,UICC_DRV,UiccHwConfigCardClckReq_2,P_WARNING,swLogPrintf("Uicc Clock register change busy!!! "); +586752,1201829887,0,0,PS1,UICC_DRV,UiccHwSetClockDivisior_1,P_WARNING,swLogPrintf("Uicc Clock register change busy!!! "); +586752,1201831935,0,0,PS1,UICC_DRV,UiccHwConfigureBaudRate_2,P_WARNING,swLogPrintf("Uicc baud rate register change busy!!! "); +586752,1201833983,0,0,PS1,UICC_DRV,UiccHwConfigureBaudRate_3,P_WARNING,swLogPrintf("Uicc baud rate register change busy!!! "); +586752,1201836031,0,0,PS1,UICC_DRV,UiccHwCardReset_1,P_INFO,swLogPrintf("USIM CLK is latched , release it "); +586752,1201838079,0,0,PS1,UICC_DRV,UiccHwCheckInteAbnormalStatus_1,P_ERROR,swLogPrintf("Unknown interrupt occurred!!! "); +586752,1201838080,0,0,PS1,UICC_DRV,UiccHwConfigParamByAtrPps_test1,P_VALUE,swLogPrintf("atrInfo->clkStopInd %d "); +586752,1201842175,0,0,PS1,UICC_DRV,UiccHwConfigParamByAtrPps_0,P_ERROR,swLogPrintf("Uicc Clock Register is on change busy state! "); +586752,1201844223,0,0,PS1,UICC_DRV,UiccHwConfigParamByAtrPps_stopclck,P_WARNING,swLogPrintf("Clock stop failed on busy state of UCR_REG... "); +586752,1201846271,0,0,PS1,UICC_DRV,UiccHwConfigParamByAtrPps_1,P_ERROR,swLogPrintf("Set clock divisior failed!! "); +586752,1201848319,0,0,PS1,UICC_DRV,UiccHwConfigParamByAtrPps_startclck,P_WARNING,swLogPrintf("Clock start failed on busy state of UCR_REG! "); +586752,1201850367,0,0,PS1,UICC_DRV,UiccHwConfigParamByAtrPps_2,P_ERROR,swLogPrintf("Set baud rate divisior failed!! "); +586752,1201850624,0,0,PS1,UICC_DRV,UiccTransLayerHandleCmdCase12_softsim_2,P_VALUE,swLogPrintf("delete INS byte %x , rspDataLen %d "); +586752,1201854463,0,0,PS1,UICC_DRV,UiccTransLayerHandleCmdCase12_2,P_INFO,swLogPrintf("Rx error! "); +586752,1201854720,0,0,PS1,UICC_DRV,UiccTransLayerHandleCmdCase34_3,P_INFO,swLogPrintf("Rx data Len : %d , cmdHeader->lc : %d "); +586752,1201858559,0,0,PS1,UICC_DRV,UiccTransLayerHandleCmdCase34_6,P_INFO,swLogPrintf("Rx error! "); +586752,1201858816,0,0,PS1,UICC_DRV,UiccTransLayerHandleT0Cmd_buffer,P_INFO,swLogPrintf("bLargeApdu %d , Rx buffer offset %d , stop it "); +586752,1201860864,0,0,PS1,UICC_DRV,UiccTransLayerHandleT0Cmd_1,P_INFO,swLogPrintf("Non-procedure bytes %x %x "); +586752,1201862656,0,0,PS1,UICC_DRV,UiccTransLayerHandleT0Cmd_2,P_INFO,swLogPrintf("removed procedure bytes in buffer , offset %d "); +586752,1201866751,0,0,PS1,UICC_DRV,UiccVerifyTerminateSessionCase_begin,P_SIG,swLogPrintf("The uicc verify terminate card "); +586752,1201868799,0,0,PS1,UICC_DRV,UiccVerifyTerminateSessionCase_0,P_INFO,swLogPrintf("The uicc has already been deactivated , nothing to do "); +586752,1201870847,0,0,PS1,UICC_DRV,UiccVerifyTerminateSessionCase_end1,P_SIG,swLogPrintf("The uicc verify terminate card ok "); +586752,1201872895,0,0,PS1,UICC_DRV,UiccVerifyTerminateSessionCase_end2,P_SIG,swLogPrintf("The uicc verify terminate card fail "); +586752,1201874943,0,0,PS1,UICC_DRV,UiccVerifyOtherSimAccessCase_0,P_SIG,swLogPrintf("Uicc verify USIM Access case : Authenticate / read_write SMS "); +586752,1201876991,0,0,PS1,UICC_DRV,UiccVerifyOtherSimAccessCase_end1,P_SIG,swLogPrintf("Uicc verify USIM Access case : Authenticate / read_write SMS ok "); +586752,1201879039,0,0,PS1,UICC_DRV,UiccVerifyOtherSimAccessCase_end2,P_SIG,swLogPrintf("Uicc verify USIM Access case : Authenticate / read_write SMS fail "); +586752,1201881087,0,0,PS1,UICC_DRV,UiccVerifyUsimAppInitCase_0,P_SIG,swLogPrintf("Uicc verify USIM application initalization "); +586752,1201883135,0,0,PS1,UICC_DRV,UiccVerifyUsimAppInitCase_end1,P_SIG,swLogPrintf("Uicc verify USIM application initalization ok "); +586752,1201885183,0,0,PS1,UICC_DRV,UiccVerifyUsimAppInitCase_end2,P_SIG,swLogPrintf("Uicc verify USIM application initalization fail "); +586752,1201887231,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_0,P_SIG,swLogPrintf("Uicc verify initial communication establishment case start... "); +586752,1201889279,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_1,P_INFO,swLogPrintf("Cold reset and Wait for ATR "); +586752,1201891327,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_2,P_SIG,swLogPrintf("ATR ok "); +586752,1201893375,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_3,P_SIG,swLogPrintf("PPS done "); +586752,1201895423,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_4,P_SIG,swLogPrintf("PPS failed "); +586752,1201897471,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_5,P_SIG,swLogPrintf("ATR fail "); +586752,1201899519,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_6,P_SIG,swLogPrintf("Uicc initial communication establishment ok "); +586752,1201901567,0,0,PS1,UICC_DRV,UiccVerifyInitCommEstCase_7,P_SIG,swLogPrintf("Uicc initial communication establishment failed "); +586752,1201903615,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_0,P_SIG,swLogPrintf("Uicc verify warm reset case "); +586752,1201905663,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_1,P_SIG,swLogPrintf("ATR ok "); +586752,1201907711,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_2,P_SIG,swLogPrintf("PPS done "); +586752,1201909759,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_3,P_SIG,swLogPrintf("PPS failed "); +586752,1201911807,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_4,P_SIG,swLogPrintf("ATR fail "); +586752,1201913855,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_5,P_SIG,swLogPrintf("Uicc verify warm reset OK "); +586752,1201915903,0,0,PS1,UICC_DRV,UiccVerifyWarmResetCase_6,P_SIG,swLogPrintf("Uicc verify warm reset failed "); +586752,1201917951,0,0,PS1,UICC_DRV,UiccVerifyClockOffOnCase_0,P_SIG,swLogPrintf("Uicc verify Clock Off / On "); +586752,1201919999,0,0,PS1,UICC_DRV,UiccVerifyClockOffOnCase_1,P_SIG,swLogPrintf("Uicc verify Clock Off / On case pass "); +586752,1201922047,0,0,PS1,UICC_DRV,UiccVerifyInit_0,P_SIG,swLogPrintf("Uicc start init... "); +586752,1201924095,0,0,PS1,UICC_DRV,UiccVerifyEntry_0,P_SIG,swLogPrintf("USIM FPGA verify start... "); +586752,1201926143,0,0,PS1,UICC_DRV,UiccVerifyEntry_1,P_SIG,swLogPrintf("Uicc verify all Pass... "); +586752,1201928191,0,0,PS1,UICC_DRV,UiccVerifyEntry_2,P_SIG,swLogPrintf("Uicc verify failed... "); +586752,1201930239,0,0,PS1,UICC_DRV,UiccVerifyEntry_3,P_SIG,swLogPrintf("test end "); +595968,1220544512,0,0,PS1,CCM,CcmInit_w_1,P_WARNING,swLogPrintf("CCM , sigId : 0x%x , should be enqueue before CerrcCcmInitConfigCnf "); +595968,1220546560,0,0,PS1,CCM,CcmPmuDeepSlpEnterCallBack_1,P_SIG,swLogPrintf("CCM , prepare to enter : %d , HIB ( 4 ) / SLEEP2 ( 3 ) state "); +595968,1220550144,0,0,PS1,CCM,CcmSetSetExtCfgReq_new_1,P_VALUE,swLogPrintf("Set extended CFG , bRohc : %d , bIpv6RsForTestSim : %d , bTcpTptOpt : %d ipv6GetPrefixTime : %d , bEnablePsSoftReset %d , bEnableDataCounter %d , emergencyCamp %d "); +595968,1220552703,0,0,PS1,CCM,CcmTaskEntry_1,P_VALUE,swLogPrintf("CCM allow to enter HIB state "); +595968,1220554751,0,0,PS1,CCM,CcmTaskEntry_2,P_VALUE,swLogPrintf("CCM allow to enter SLEEP2 state "); +595968,1220556799,0,0,PS1,CCM,CcmTaskEntry_3,P_VALUE,swLogPrintf("CCM not allow to enter HIB state "); +595968,1220558847,0,0,PS1,CCM,CcmTaskEntry_4,P_VALUE,swLogPrintf("CCM not allow to enter SLEEP2 state "); +596992,1222641920,0,0,PS1,CCM_REG,CcmRegTriggeredRegProcCnf_1,P_WARNING,swLogPrintf("CCM REG , SIM not ready : %d , or not CFUN1 state : %d , can ' t proc pending attach REQ "); +596992,1222643712,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_1,P_WARNING,swLogPrintf("CCM REG , invalid request REG PROC : %d "); +596992,1222645760,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_2,P_WARNING,swLogPrintf("CCM REG , ongoing proc : %d , abort current proc , try to power off! "); +596992,1222648064,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_3,P_WARNING,swLogPrintf("CCM REG , proc cfun0 , but ongoing REG proc : %d , pending REG proc : %d , abort pending proc "); +596992,1222650368,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_4,P_WARNING,swLogPrintf("CCM REG , ongoing REG proc : %d , pending REG proc : %d , can ' t process new proc : %d "); +596992,1222651904,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_5,P_WARNING,swLogPrintf("CCM REG , pending PROC : %d "); +596992,1222655999,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_6,P_WARNING,swLogPrintf("CCM REG , CEMM already under REG procedure , don ' t need to trigger again "); +596992,1222658047,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_7,P_WARNING,swLogPrintf("CCM REG , CEMM already under DEACT procedure , don ' t need to trigger again "); +596992,1222660095,0,0,PS1,CCM_REG,CcmRegHandleRegProcedure_8,P_WARNING,swLogPrintf("CCM REG , CEMM already under DEREG procedure , don ' t need to trigger again "); +596992,1222662143,0,0,PS1,CCM_REG,CcmRegProcedureOut_1,P_INFO,swLogPrintf("CCM REG , all procedure done "); +596992,1222662144,0,0,PS1,CCM_REG,CcmRegCheckPendingRegProc_1,P_INFO,swLogPrintf("CCM REG , process pending REG procedure : %d "); +596992,1222664448,0,0,PS1,CCM_REG,CcmRegCheckPendingRegProc_2,P_WARNING,swLogPrintf("CCM REG , SIM not ready : %d , or not CFUN1 state : %d , can ' t proc pending attach REQ "); +596992,1222668287,0,0,PS1,CCM_REG,CcmRegProcCemmrRegCnfSig_1,P_WARNING,swLogPrintf("CCM REG , no REG procedure is ongoing when receive : SIG_CEMMR_REG_CNF "); +596992,1222668288,0,0,PS1,CCM_REG,CcmRegProcCemmrRegCnfSig_2,P_WARNING,swLogPrintf("CCM REG , CemmrReg confirm failed : %d "); +596992,1222672383,0,0,PS1,CCM_REG,CcmRegProcCemmrDeregCnfSig_1,P_WARNING,swLogPrintf("CCM REG , no DEREG procedure is ongoing when receive : SIG_CEMMR_DEREG_CNF "); +596992,1222674431,0,0,PS1,CCM_REG,CcmRegProcCemmrDeregCnfSig_2,P_WARNING,swLogPrintf("CCM REG , the detachType of pDeregCnf is inconsistent with detachType of ongoingReg , discard this msg! "); +596992,1222676479,0,0,PS1,CCM_REG,CcmRegProcCemmManualPlmnSearchCnfSig_1,P_INFO,swLogPrintf("CCM REG , manual PLMN search confirmed , need to stop the protection timer "); +596992,1222678527,0,0,PS1,CCM_REG,CcmRegProcCemmManualPlmnSearchCnfSig_2,P_WARNING,swLogPrintf("CCM REG , manual PLMN search confirmed , but no protection timer running , maybe confirmed before "); +596992,1222678528,0,0,PS1,CCM_REG,CcmRegProcCemmManualPlmnSearchCnfSig_3,P_WARNING,swLogPrintf("CCM REG , RC not succ ( %d ) in CemmManualPlmnSearchCnf "); +596992,1222682623,0,0,PS1,CCM_REG,CcmRegProcCemmManualPlmnSearchCnfSig_4,P_WARNING,swLogPrintf("CCM REG , no PLMN found in CemmManualPlmnSearchCnf "); +596992,1222682624,0,0,PS1,CCM_REG,CcmRegProcCemmAbortPlmnSearchCnfSig_1,P_WARNING,swLogPrintf("CCM REG , RC not succ ( %d ) in AbortPlmnSearchCnf "); +596992,1222686719,0,0,PS1,CCM_REG,CcmRegProcCemmAbortPlmnSearchCnfSig_2,P_WARNING,swLogPrintf("CCM REG , no PLMN found in AbortPlmnSearchCnf "); +596992,1222686720,0,0,PS1,CCM_REG,CcmRegProcCemmrOosPlmnSelectCnfSig_1,P_WARNING,swLogPrintf("CCM REG , RC not succ ( %d ) in CemmPlmnOosPlmnSelectCnf "); +596992,1222688768,0,0,PS1,CCM_REG,CcmRegProcCemmrDeRegIndSig_1,P_WARNING,swLogPrintf("Trigger slent reset %d time "); +596992,1222692863,0,0,PS1,CCM_REG,CcmRegProcCemmrDeRegIndSig_2,P_WARNING,swLogPrintf("Silent Reset reach max count! "); +596992,1222692864,0,0,PS1,CCM_REG,CcmRegProcCemmPlmnSetBandFreqCnfSig_autocfg_1,P_WARNING,swLogPrintf("CCM REG , SET CIOT BAND CEMM confirm failed : %d "); +596992,1222694912,0,0,PS1,CCM_REG,CcmRegProcCemmPlmnSetBandFreqCnfSig_1,P_WARNING,swLogPrintf("CCM REG , SET CIOT BAND CEMM confirm failed : %d "); +596992,1222696960,0,0,PS1,CCM_REG,CcmRegProcCemmPlmnSetBandFreqCnfSig_2,P_WARNING,swLogPrintf("CCM REG , SET CIOT FREQ CEMM confirm failed : %d "); +596992,1222699264,0,0,PS1,CCM_REG,CcmRegProcCemmPlmnGetBandFreqCnfSig_1,P_WARNING,swLogPrintf("CCM REG , can ' t get band / freq info type : %d , ret error : %d "); +596992,1222703103,0,0,PS1,CCM_REG,CcmRegProcManualPlmnSearchProtectTimerExpiry_1,P_ERROR,swLogPrintf("CCM REG , manual plmn protect timer expiry , but no such time info in CCM REG side "); +596992,1222705151,0,0,PS1,CCM_REG,CcmRegProcManualPlmnSearchProtectTimerExpiry_2,P_WARNING,swLogPrintf("CCM REG , manual PLMN search time expiry , need to abort the PLMN search "); +596992,1222705152,0,0,PS1,CCM_REG,CcmRegProcPoweronReqMsg_1,P_WARNING,swLogPrintf("CCM REG , CEMM UNDER REG state : %d , don ' t need to process CcmRegPoweronReq "); +596992,1222707200,0,0,PS1,CCM_REG,CcmRegProcPoweronReqMsg_2,P_WARNING,swLogPrintf("CCM REG , SIM not ready : %d , don ' t need to process CcmRegPoweronReq "); +596992,1222709248,0,0,PS1,CCM_REG,CcmRegProcPoweronReqMsg_3,P_INFO,swLogPrintf("CCM REG , SIM state is : %d "); +596992,1222711296,0,0,PS1,CCM_REG,CcmRegProcSimReadyIndMsg_1,P_WARNING,swLogPrintf("CCM REG , CEMM UNDER REG state : %d , don ' t need to process SimReadyInd "); +596992,1222713344,0,0,PS1,CCM_REG,CcmRegProcSimReadyIndMsg_2,P_WARNING,swLogPrintf("CCM REG , SIM ready , but not on power on state : %d "); +596992,1222717439,0,0,PS1,CCM_REG,CcmRegSetCiotFreqReq_1,P_WARNING,swLogPrintf("This command must be restricted to execute in the CFUN0 or CFUN4 state "); +596992,1222717696,0,0,PS1,CCM_REG,CcmRegAutoPlmnSelectReq_1,P_WARNING,swLogPrintf("CCM REG , SIM is not ready : %d or CFUN is not power on : %d , just pass the AUTO PLMN param to CEMM "); +596992,1222719744,0,0,PS1,CCM_REG,CcmRegManualPlmnSelectReq_1,P_WARNING,swLogPrintf("CCM REG , SIM is not ready : %d , or CFUN is not power on : %d , just pass MANUAL PLMN selection to CEMM "); +596992,1222721536,0,0,PS1,CCM_REG,CcmRegDeregReq_1,P_WARNING,swLogPrintf("CCM REG , can ' t process DEREG req ( COPS = 2 ) , as SIM is initing ( %d ) "); +596992,1222723584,0,0,PS1,CCM_REG,CcmRegSetCmiMmCurOperInfoCnfInfo_1,P_WARNING,swLogPrintf("CCM REG , invalid / not suitable plmn select type : %d "); +596992,1222727679,0,0,PS1,CCM_REG,CcmRegSetCmiMmCurOperInfoCnfInfo_2,P_ERROR,swLogPrintf("CCM REG , can ' t get PLMN long name , not support now "); +596992,1222729727,0,0,PS1,CCM_REG,CcmRegSetCmiMmCurOperInfoCnfInfo_3,P_ERROR,swLogPrintf("CCM REG , can ' t get PLMN short name , not support now "); +596992,1222729728,0,0,PS1,CCM_REG,CcmRegSetCmiMmCurOperInfoCnfInfo_4,P_WARNING,swLogPrintf("CCM REG , plmn select state : %d "); +596992,1222731776,0,0,PS1,CCM_REG,CcmRegSetCmiMmCurOperInfoCnfInfo_5,P_WARNING,swLogPrintf("CCM REG , regStaticCtx.plmnValid : %d "); +596992,1222733824,0,0,PS1,CCM_REG,CcmRegSetCmiMmCurOperInfoCnfInfo_6,P_WARNING,swLogPrintf("CCM REG , can ' t get PLMN info , as REG status : %d "); +596992,1222735872,0,0,PS1,CCM_REG,CcmRegManualPlmnSearchReq_3,P_WARNING,swLogPrintf("CCM REG , MANUAL PLMN search timer ( 0x%lx ) is already created , when start request manual plmn search "); +596992,1222737920,0,0,PS1,CCM_REG,CcmRegCemmBeUnderReg_1,P_WARNING,swLogPrintf("CCM REG , CEMM is not attached , and first to do attach ( %d ) "); +596992,1222739968,0,0,PS1,CCM_REG,CcmRegProcPsAttachReqMsg_cfun,P_WARNING,swLogPrintf("CCM REG , not CFUN1 state : %d , can ' t proc PS attach REQ "); +596992,1222744063,0,0,PS1,CCM_REG,CcmRegProcPsAttachReqMsg_sim_off,P_WARNING,swLogPrintf("CCM REG , SIM removed , can ' t proc PS attach REQ "); +596992,1222744064,0,0,PS1,CCM_REG,CcmRegProcPsAttachReqMsg_sim_not_ready,P_WARNING,swLogPrintf("CCM REG , SIM not ready : %d , pending proc PS attach REQ "); +596992,1222746112,0,0,PS1,CCM_REG,CcmRegProcPsDetachReqMsg_1,P_WARNING,swLogPrintf("CCM REG , can ' t process CGATT0 , as SIM is initing ( %d ) "); +596992,1222750207,0,0,PS1,CCM_REG,CcmRegGetLocationInfo_1,P_WARNING,swLogPrintf("CCM REG , no valid PLMN info "); +596992,1222752255,0,0,PS1,CCM_REG,CcmRegGetLocationInfo_2,P_WARNING,swLogPrintf("CCM REG , no valid cell info "); +596992,1222754303,0,0,PS1,CCM_REG,CcmRegGetCellInfo_1,P_WARNING,swLogPrintf("CCM REG , no valid PLMN info "); +596992,1222756351,0,0,PS1,CCM_REG,CcmRegGetCellInfo_2,P_WARNING,swLogPrintf("CCM REG , no valid cell info "); +596992,1222756352,0,0,PS1,CCM_REG,CcmRegOosPlmnSelectReq_1,P_WARNING,swLogPrintf("CCM REG , can ' t process OOS PLMN search , as SIM is not ready : %d "); +596992,1222758400,0,0,PS1,CCM_REG,CcmRegOosPlmnSelectReq_2,P_WARNING,swLogPrintf("CCM REG , can ' t process OOS PLMN selection , as CFUN is not power on state : %d "); +596992,1222760704,0,0,PS1,CCM_REG,CcmRegPlmnReselectReq_1,P_WARNING,swLogPrintf("CCM REG , SIM is not ready : %d or CFUN is not power on : %d "); +598016,1224740863,0,0,PS1,CCM_DEV,CcmDevStopPeriodStatisProc_1,P_VALUE,swLogPrintf("CCM DEV , stop period statisic info report "); +598016,1224742911,0,0,PS1,CCM_DEV,CcmDevProcOut_1,P_INFO,swLogPrintf("CCM DEV procedure done , free the DYN context "); +598016,1224744959,0,0,PS1,CCM_DEV,CcmDevProcOut_2,P_INFO,swLogPrintf("CCM DEV no procedure is ongoing , could enter HIB mode "); +598016,1224745216,0,0,PS1,CCM_DEV,CcmDevHandleCfun0Proc_1,P_WARNING,swLogPrintf("CCM DEV current ongoing cfun proc : %d , and pending cfun proc : %d , can ' t proc the new CFUN0 req "); +598016,1224749055,0,0,PS1,CCM_DEV,CcmDevHandleCfun0Proc_2,P_INFO,swLogPrintf("CCM DEV , proc the cfun0 ; power off the protocol firstly "); +598016,1224749312,0,0,PS1,CCM_DEV,CcmDevHandleCfun4Proc_1,P_WARNING,swLogPrintf("CCM DEV current ongoing cfun proc : %d , and pending cfun proc : %d , can ' t proc the new CFUN4 req "); +598016,1224753151,0,0,PS1,CCM_DEV,CcmDevHandleCfun4Proc_2,P_INFO,swLogPrintf("CCM DEV , proc the cfun4 , power off the protocol "); +598016,1224753408,0,0,PS1,CCM_DEV,CcmDevHandleCfun1Proc_1,P_WARNING,swLogPrintf("CCM DEV current ongoing cfun proc : %d ; and pending cfun proc : %d ; can ' t proc the new CFUN1 req "); +598016,1224757247,0,0,PS1,CCM_DEV,CcmDevHandleProc_1,P_WARNING,swLogPrintf("CCM DEV ; no procedure need onogoing "); +598016,1224757504,0,0,PS1,CCM_DEV,CcmDevCurProcDone_1,P_VALUE,swLogPrintf("CCM DEV PROC pending procedue : %d , which SRC module : %d "); +598016,1224759296,0,0,PS1,CCM_DEV,CcmDevProcGetExtStatusCnf_1,P_WARNING,swLogPrintf("CCM DEV , get layer : %d STATUS CNF , but no AT+ECSTATUS? is pending , ignore it "); +598016,1224761344,0,0,PS1,CCM_DEV,CcmDevProcStatisInfoInd_1,P_WARNING,swLogPrintf("CCM DEV , get layer : %d STATIS INFO , but no statistic proc is pending , ignore it "); +598016,1224765439,0,0,PS1,CCM_DEV,CcmDevProcStatisPeriodTimerExpiry_1,P_WARNING,swLogPrintf("CCM DEV , Statis Period Timer expiry , but no statis proc ongoing "); +598016,1224767487,0,0,PS1,CCM_DEV,CcmDevProcCerrcBasicCellListInfoCnfSig_asyn_1,P_WARNING,swLogPrintf("CCM DEV , no cell found in CerrcCcmBasicCellListInfoCnf , not report BCINFO URC "); +598016,1224769535,0,0,PS1,CCM_DEV,CcmDevProcCerrcAbortBasicCellListInfoCnfSig_asyn_1,P_WARNING,swLogPrintf("CCM DEV , no cell found in CerrcCcmAbortBasicCellListInfoCnf , not report BCINFO URC "); +598016,1224771583,0,0,PS1,CCM_DEV,CcmDevProcBasicCellGuardTimerExpiry_1,P_WARNING,swLogPrintf("CCM DEV , ECBCINFO guard Timer expiry , but timer not created "); +598016,1224771840,0,0,PS1,CCM_DEV,CcmDevSetCfunReq_1,P_WARNING,swLogPrintf("CCM DEV invaild cfun request : %d ; from sub-mod : %d "); +598016,1224774144,0,0,PS1,CCM_DEV,CcmDevPowerWakeUpReq_1,P_WARNING,swLogPrintf("WAKE UP , but already procedure : %d / %d / %d "); +598016,1224777727,0,0,PS1,CCM_DEV,CcmDevPowerWakeUpReq_2,P_VALUE,swLogPrintf("WAKE UP from HIB / Sleep2 state "); +598016,1224779775,0,0,PS1,CCM_DEV,CcmDevProcSimPoweronCnfMsg_1,P_WARNING,swLogPrintf("CCM DEV no procedure ongoing , but received a SIM power on CNF "); +598016,1224781823,0,0,PS1,CCM_DEV,CcmDevProcSimPoweronCnfMsg_2,P_WARNING,swLogPrintf("CCM DEV set the AIR PLANE state even no SIM "); +598016,1224783871,0,0,PS1,CCM_DEV,CcmDevProcSimPoweronCnfMsg_3,P_WARNING,swLogPrintf("CCM DEV set the POWER ON state even no SIM "); +598016,1224784128,0,0,PS1,CCM_DEV,CcmDevProcSimPoweronCnfMsg_4,P_WARNING,swLogPrintf("CCM DEV ongoing CFUN PROC : %d , POWER PROC : %d , but received a SIM power on CNF "); +598016,1224787967,0,0,PS1,CCM_DEV,CcmDevProcRegPoweronCnfMsg_1,P_WARNING,swLogPrintf("CCM DEV no procedure ongoing , but received a REG power on CNF "); +598016,1224787968,0,0,PS1,CCM_DEV,CcmDevProcRegPoweronCnfMsg_2,P_WARNING,swLogPrintf("CCM DEV , POWER WAKE UP Fail from CCM REG : %d "); +598016,1224790016,0,0,PS1,CCM_DEV,CcmDevProcRegPoweronCnfMsg_3,P_WARNING,swLogPrintf("CCM DEV , POWER PROC : %d , but recv CCM REG CNF "); +598016,1224794111,0,0,PS1,CCM_DEV,CcmDevProcSimPoweroffCnfMsg_1,P_WARNING,swLogPrintf("CCM DEV no procedure ongoing , but received a SIM power OFF CNF "); +598016,1224794112,0,0,PS1,CCM_DEV,CcmDevProcSimPoweroffCnfMsg_2,P_WARNING,swLogPrintf("CCM DEV ongoing CFUN PROC : %d , but received a SIM power OFF CNF "); +598016,1224798207,0,0,PS1,CCM_DEV,CcmDevProcRegPoweroffCnfMsg_1,P_VALUE,swLogPrintf("CCM DEV , no procedure ongoing but recv REG power off CNF "); +598016,1224798208,0,0,PS1,CCM_DEV,CcmDevProcRegPoweroffCnfMsg_2,P_WARNING,swLogPrintf("CCM DEV , Reg Poweroff Cnf failed with : %d "); +598016,1224802303,0,0,PS1,CCM_DEV,CcmDevProcRegPoweroffCnfMsg_3,P_VALUE,swLogPrintf("CCM DEV , protocol power off done power off the SIM "); +598016,1224802304,0,0,PS1,CCM_DEV,CcmDevProcRegPoweroffCnfMsg_6,P_WARNING,swLogPrintf("CCM DEV , ongoing CFUN PROC : %d but received a REG power OFF CNF "); +598016,1224806399,0,0,PS1,CCM_DEV,CcmDevGetCurPowerState_1,P_WARNING,swLogPrintf("CCM DEV when get power state , A CFUN : 4 is ongoing "); +598016,1224808447,0,0,PS1,CCM_DEV,CcmDevGetCurPowerState_2,P_WARNING,swLogPrintf("CCM DEV when get power state , A CFUN : 1 is ongoing "); +598016,1224808448,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_plmnSearchPowerLevel,P_WARNING,swLogPrintf("CCM DEV , ' plmnSearchPowerLevel ' can only be set to 0 -3 , can ' t set to : %d "); +598016,1224810496,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_enableEpco,P_WARNING,swLogPrintf("CCM DEV , ' EPCO ' can only be set to TRUE ( 1 ) or FALSE ( 0 ) , can ' t set to : %d "); +598016,1224812544,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_qRxLevMin,P_WARNING,swLogPrintf("CCM DEV , ' qRxLevMin ' can only be set to 0 , or -156< = qRxLevMin< = -44 , can ' t set to : %d "); +598016,1224814592,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_reselToWeakNcellOpt,P_WARNING,swLogPrintf("CCM DEV , ' reselToWeakNcellOpt ' can only be set to 0 < = reselToWeakNcellOpt < = 100 , can ' t set to : %d "); +598016,1224816640,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_dataInactTimerS,P_WARNING,swLogPrintf("CCM DEV , ' dataInactTimer ' can only be set to 0 , or > = 15 s , can ' t set to : %d "); +598016,1224818688,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_relaxMonitorDeltaP,P_WARNING,swLogPrintf("CCM DEV , ' relaxMonitorDeltaP ' can only be set to < = 15 db , can ' t set to : %d "); +598016,1224820736,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_relVersion,P_WARNING,swLogPrintf("CCM DEV , CAT1 ' relVersion ' can only be set 13 or 14 , can ' t set to : %d "); +598016,1224822784,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_nbCategory,P_WARNING,swLogPrintf("CCM DEV , CAT1 ' UeCategory ' can only be set 1 or 2 , can ' t set to : %d "); +598016,1224824832,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_14,P_WARNING,swLogPrintf("CCM DEV , ' bRohc ' can only be set to TRUE ( 1 ) or FALSE ( 0 ) , can ' t set to : %d "); +598016,1224826880,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_be_RS_for_ipv6,P_WARNING,swLogPrintf("CCM DEV , ' bIpv6RsForTestSim ' can only be set to TRUE ( 1 ) or FALSE ( 0 ) , can ' t set to : %d "); +598016,1224828928,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_ipv6GetPrefixTime,P_WARNING,swLogPrintf("CCM DEV , ' ipv6GetPrefixTime ' can only be set to ( 0 ~65535 ) , can ' t set to : %d "); +598016,1224830976,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_psSoftReset,P_WARNING,swLogPrintf("CCM DEV , ' bEnablePsSoftReset ' can only be set to TRUE ( 1 ) or FALSE ( 0 ) , can ' t set to : %d "); +598016,1224833024,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_bTcpTptOpt,P_WARNING,swLogPrintf("CCM DEV , ' bTcpTptOpt ' can only be set to 0 / 1 / 2 , can ' t set to : %d "); +598016,1224835072,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_bEnableDataCounter,P_WARNING,swLogPrintf("CCM DEV , ' bEnableDataCounter ' can only be set to TRUE ( 1 ) or FALSE ( 0 ) , can ' t set to : %d "); +598016,1224837120,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_enableaAcl_1,P_WARNING,swLogPrintf("CCM DEV , ' EnableAcl ' can only be set to TRUE ( 1 ) or FALSE ( 0 ) , can ' t set to : %d "); +598016,1224839168,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_pdpRemap_1,P_WARNING,swLogPrintf("CCM DEV , ' PdpRemap ' can only be set to 0 / 1 / 2 , can ' t set to : %d "); +598016,1224841216,0,0,PS1,CCM_DEV,CcmDevSetExtCfgReq_pdpreact_1,P_WARNING,swLogPrintf("CCM DEV , ' PdpReact ' can only be set to 0 / 1 , can ' t set to : %d "); +598016,1224845311,0,0,PS1,CCM_DEV,CcmDevGetExtCfgReq_1,P_WARNING,swLogPrintf("CCM DEV , already get EXT CFG PARAM ongoing "); +598016,1224847359,0,0,PS1,CCM_DEV,CcmDevGetExtStatusReq_1,P_WARNING,swLogPrintf("CCM DEV , already a AT+ECSTATUS ongoing "); +598016,1224849407,0,0,PS1,CCM_DEV,CcmDevSetExtStatisModeReq_1,P_VALUE,swLogPrintf("CCM DEV , stop statisic info report "); +598016,1224851455,0,0,PS1,CCM_DEV,CcmDevSetExtStatisModeReq_2,P_VALUE,swLogPrintf("CCM DEV , stop statisic count , but no statisic before "); +598016,1224851456,0,0,PS1,CCM_DEV,CcmDevSetExtStatisModeReq_3,P_WARNING,swLogPrintf("CCM DEV , not cfun1 state : %d , can ' t start statisic info report "); +598016,1224853504,0,0,PS1,CCM_DEV,CcmDevSetExtStatisModeReq_w_rptS,P_WARNING,swLogPrintf("CCM DEV , statisic interval too short : %d < 1 "); +598016,1224855552,0,0,PS1,CCM_DEV,CcmDevSetExtStatisModeReq_4,P_VALUE,swLogPrintf("CCM DEV , start statisic info report with interval : %d s "); +598016,1224859647,0,0,PS1,CCM_DEV,CcmDevSetExtStatisModeReq_5,P_WARNING,swLogPrintf("CCM DEV , already a statisic info report is ongoing "); +598016,1224861695,0,0,PS1,CCM_DEV,CcmDevGetEmmCapaParmCnf_1,P_WARNING,swLogPrintf("CCM DEV , get EMM CFG PARAM CNF , but no AT+ECCFG? is pending , ignore it "); +598016,1224863743,0,0,PS1,CCM_DEV,CcmDevGetCerrcExtendedConfigParamCnf_1,P_WARNING,swLogPrintf("CCM DEV , get CERRC CFG PARAM CNF , but no AT+ECCFG? is pending , ignore it "); +598016,1224865791,0,0,PS1,CCM_DEV,CcmDevGetBcInfoFromTinyContext_1,P_WARNING,swLogPrintf("CCM DEV , no saved BCINFO , please AT+ECBCINFO to save the BCINFO firstly "); +598016,1224867839,0,0,PS1,CCM_DEV,CcmDevGetBasicCellListInfoReq_1,P_WARNING,swLogPrintf("CCM DEV , another basic cell info means maybe ongoing "); +598016,1224868096,0,0,PS1,CCM_DEV,CcmDevGetBasicCellListInfoReq_cfun_1,P_WARNING,swLogPrintf("CCM DEV , CFUN : %d / %d is ongoing / pending , can ' t proc BCINFO "); +598016,1224869888,0,0,PS1,CCM_DEV,CcmDevGetBasicCellListInfoReq_sim_1,P_WARNING,swLogPrintf("CCM DEV , SIM is not ready : %d , AT+ECBCINFO = 0 change to AT+ECBCINFO = 1 , let PLMN search "); +598016,1224871936,0,0,PS1,CCM_DEV,CcmDevGetBasicCellListInfoReq_cfun_2,P_WARNING,swLogPrintf("CCM DEV , CFUN is not power on state : %d , AT+ECBCINFO = 0 change to AT+ECBCINFO = 1 , let PLMN search "); +598016,1224874496,0,0,PS1,CCM_DEV,CcmDevGetBasicCellListInfoReq_band_1,P_SIG,swLogPrintf("CCM DEV , BCCELL mode : %d , SIM not ready : %d and emergency disable , or not cfun1 state : %d , should change to search band "); +598016,1224876032,0,0,PS1,CCM_DEV,CcmDevBcInfoManualPlmnSearchCnf_1,P_WARNING,swLogPrintf("CCM DEV , RC not succ ( %d ) in BCINFO PLMN seach confirm "); +598016,1224878336,0,0,PS1,CCM_DEV,CcmDevBcInfoManualPlmnSearchCnf_asyn_1,P_WARNING,swLogPrintf("CCM DEV , CCM RC not succ ( %d ) , or no cell ( %d ) found in BCINFO , not report URC "); +598016,1224882175,0,0,PS1,CCM_DEV,CcmDevSetPowerClassReq_1,P_WARNING,swLogPrintf("AT+ECPOWERCLASS must be restricted to execute under CFUN0 or CFUN4 state "); +598016,1224882176,0,0,PS1,CCM_DEV,CcmDevProcEventStatisInfoCnf_1,P_WARNING,swLogPrintf("CCM DEV , get layer : %d STATUS CNF , but no AT+ECEVENTSTATIS? is pending , ignore it "); +598016,1224886271,0,0,PS1,CCM_DEV,CcmDevSetEventStatisModeReq_1,P_WARNING,swLogPrintf("This command must be restricted to execute in the CFUN0 state "); +598016,1224888319,0,0,PS1,CCM_DEV,CcmDevEventStatisAllocMemoryReq_1,P_WARNING,swLogPrintf("CCM DEV , already a AT+ECEVENTSTATIS ongoing "); +598016,1224890367,0,0,PS1,CCM_DEV,CcmDevProcWifiScanGuardTimerExpiry_1,P_WARNING,swLogPrintf("CCM DEV , QWIFISCAN guard Timer expiry , but timer not created "); +598016,1224892415,0,0,PS1,CCM_DEV,CcmDevProcPowerOnGuardTimerExpiry_1,P_WARNING,swLogPrintf("CCM DEV , Power on delay guard Timer expiry , but timer not created "); +598016,1224892416,0,0,PS1,CCM_DEV,CcmCfgPowerOnRead_parse_e_1,P_ERROR,swLogPrintf("PS CFG NVM , get next parameter err : %d "); +598016,1224894464,0,0,PS1,CCM_DEV,CcmCfgPowerOnRead_parse_1,P_VALUE,swLogPrintf("PS CFG NVM , pCfgParam->paramId %d "); +598016,1224896512,0,0,PS1,CCM_DEV,CcmCfgPowerOnRead_unkown_param_1,P_WARNING,swLogPrintf("CCM CFG , can ' t parse paramID : %d , ignore and remove it "); +598016,1224898816,0,0,PS1,CCM_DEV,CcmCfgPowerOnRead_rm_w_1,P_WARNING,swLogPrintf("CCM CFG , can ' t parse paramId : %d , type : %d , remove this param "); +598016,1224902655,0,0,PS1,CCM_DEV,CcmCfgPowerOnRead_parse_error_1,P_ERROR,swLogPrintf("CCM CFG , uepsconfig.nvm file parse error , reset to default PS config "); +598016,1224902656,0,0,PS1,CCM_DEV,CcmProcCerrcCcmGetParamCnfSig_1,P_WARNING,swLogPrintf("CCM main , unexpected param type %d in CerrcCcmGetParamCnf! "); +598016,1224906751,0,0,PS1,CCM_DEV,CcmRegProcSimNokIndMsg_1,P_INFO,swLogPrintf("Power on without SIM inserted , trigger emergency camp on "); +598016,1224908799,0,0,PS1,CCM_DEV,CcmSmsProcMemCapIndDelayTimerExpiry_1,P_WARNING,swLogPrintf("CCM SMS , CCM_SMS_MEM_CAP_IND_DELAY_TIMER expiry , but timer not created "); +599040,1226838015,0,0,PS1,CCM_PS,CcmPsStartGuardTimer_w_1,P_WARNING,swLogPrintf("CCM PS , start guard time , but guard timer is not null , restart "); +599040,1226838272,0,0,PS1,CCM_PS,CcmPsStartGuardTimer_s_1,P_SIG,swLogPrintf("CCM PS , start guard timer Id : %d , val : %d ticks / ms "); +599040,1226840064,0,0,PS1,CCM_PS,CcmPsProcedureOut_1,P_VALUE,swLogPrintf("CCM PS , proc : %e is ongoing , can ' t enter deep sleep "); +599040,1226844159,0,0,PS1,CCM_PS,CcmPsProcedureOut_w_1,P_WARNING,swLogPrintf("CCM PS , no proc ongoing , but guard timer is not null "); +599040,1226844160,0,0,PS1,CCM_PS,CcmPsProcCesmActEpsBearerCtxCnfSig_w_1,P_WARNING,swLogPrintf("CCM PS , recv CcmCesmActEpsBearerCtxCnf , but CCM curPoc : %d "); +599040,1226846208,0,0,PS1,CCM_PS,CcmPsProcCesmActEpsBearerCtxRejSig_w_1,P_WARNING,swLogPrintf("CCM PS , recv CcmCesmActEpsBearerCtxRej , but CCM curPoc : %d "); +599040,1226848256,0,0,PS1,CCM_PS,CcmPsProcCesmDeactEpsBearerCtxCnfSig_w_1,P_WARNING,swLogPrintf("CCM PS , recv CcmCesmDeactEpsBearerCtxCnf , but CCM curPoc : %d "); +599040,1226850304,0,0,PS1,CCM_PS,CcmPsProcCesmDeactEpsBearerCtxRejSig_w_1,P_WARNING,swLogPrintf("CCM PS , recv CcmCesmDeactEpsBearerCtxRej , but CCM curPoc : %d "); +599040,1226852352,0,0,PS1,CCM_PS,CcmPsProcCesmModifyEpsBearerCtxCnfSig_w_1,P_WARNING,swLogPrintf("CCM PS , recv CcmCesmModifyEpsBearerCtxCnf , but CCM curPoc : %d "); +599040,1226854400,0,0,PS1,CCM_PS,CcmPsProcActBrGuardTimerExpiry_w_1,P_WARNING,swLogPrintf("CCM PS , CCM_PS_ACT_BR_GUARD_TIMER expiry , but curProc : %d "); +599040,1226856448,0,0,PS1,CCM_PS,CcmPsProcDeactBrGuardTimerExpiry_w_1,P_WARNING,swLogPrintf("CCM PS , CCM_PS_DEACT_BR_GUARD_TIMER expiry , but curProc : %d "); +599040,1226858496,0,0,PS1,CCM_PS,CcmPsProcModifyBrGuardTimerExpiry_w_1,P_WARNING,swLogPrintf("CCM PS , CCM_PS_MODIFY_BR_GUARD_TIMER expiry , but curProc : %d "); +599040,1226860544,0,0,PS1,CCM_PS,CcmPsProcRegAttachCnfMsg_t_w_1,P_WARNING,swLogPrintf("CCM PS , curProc : %d , CGATT , but guard timer is not running "); +599040,1226862592,0,0,PS1,CCM_PS,CcmPsProcRegAttachCnfMsg_cgact_w_1,P_WARNING,swLogPrintf("CCM PS , curProc : %d , CGACT , but guard timer is not running "); +599040,1226864640,0,0,PS1,CCM_PS,CcmPsProcRegAttachCnfMsg_cgatt_w_2,P_WARNING,swLogPrintf("CCM PS , PS not attach , and not allow to attach , can ' t ACT a bearer , cause : %d "); +599040,1226866688,0,0,PS1,CCM_PS,CcmPsProcRegAttachCnfMsg_proc_w_1,P_WARNING,swLogPrintf("CCM PS , REG proc ps attach cnf , not curProc : %d "); +599040,1226868736,0,0,PS1,CCM_PS,CcmPsProcRegDetachCnfMsg_proc_w_1,P_WARNING,swLogPrintf("CCM PS , REG proc ps detach cnf , not curProc : %d "); +599040,1226870784,0,0,PS1,CCM_PS,CcmPsModifyBearerCtxReq_proc_w_1,P_WARNING,swLogPrintf("CCM PS , proc modify bearer request , but a proc : %d ongoing , reject "); +599040,1226874879,0,0,PS1,CCM_PS,CcmPsModifyBearerCtxReq_timer_w_1,P_WARNING,swLogPrintf("CCM PS , proc modify bearer request , but guardtimer is created "); +599040,1226874880,0,0,PS1,CCM_PS,CcmPsAttachReq_proc_w_1,P_WARNING,swLogPrintf("CCM PS , proc PS attach request , but a proc : %d ongoing , reject "); +599040,1226878975,0,0,PS1,CCM_PS,CcmPsAttachReq_timer_w_1,P_WARNING,swLogPrintf("CCM PS , proc PS attach request , but guardtimer is created "); +599040,1226878976,0,0,PS1,CCM_PS,CcmPsDetachReq_proc_w_1,P_WARNING,swLogPrintf("CCM PS , proc PS detach request , but a proc : %d ongoing , reject "); +599040,1226883071,0,0,PS1,CCM_PS,CcmPsDetachReq_timer_w_1,P_WARNING,swLogPrintf("CCM PS , proc PS detach request , but guardtimer is created "); +599040,1226883072,0,0,PS1,CCM_PS,CcmPsActEpsBearerReq_proc_w_1,P_WARNING,swLogPrintf("CCM PS , proc act bearer request , but a proc : %d ongoing , reject "); +599040,1226887167,0,0,PS1,CCM_PS,CcmPsActEpsBearerReq_timer_w_1,P_WARNING,swLogPrintf("CCM PS , proc act bearer request , but guardtimer is created "); +599040,1226889215,0,0,PS1,CCM_PS,CcmPsActEpsBearerReq_s_1,P_SIG,swLogPrintf("CCM PS , proc act bearer request , need trigger PS attach firstly "); +599040,1226889216,0,0,PS1,CCM_PS,CcmPsDeactEpsBearerReq_proc_w_1,P_WARNING,swLogPrintf("CCM PS , proc deact bearer request , but a proc : %d ongoing , reject "); +599040,1226893311,0,0,PS1,CCM_PS,CcmPsDeactEpsBearerReq_timer_w_1,P_WARNING,swLogPrintf("CCM PS , proc deact bearer request , but guardtimer is created "); +599040,1226895359,0,0,PS1,CCM_PS,CcmPsProcDataCounterOptionReq_1,P_WARNING,swLogPrintf("CCM PS , data counter is disable , can ' t proc this cmd! "); +599040,1226897407,0,0,PS1,CCM_PS,CcmPsSetSaveDataCounterPeriodReq_1,P_VALUE,swLogPrintf("CCM PS , stop auto save data counter "); +599040,1226897408,0,0,PS1,CCM_PS,CcmPsSetSaveDataCounterPeriodReq_2,P_VALUE,swLogPrintf("CCM PS , start auto save data counter timer with new interval : %d s "); +599040,1226899456,0,0,PS1,CCM_PS,CcmPsSetSaveDataCounterPeriodReq_3,P_VALUE,swLogPrintf("CCM PS , keep auto save data counter timer with previous interval : %d s "); +600064,1228933120,0,0,PS1,CCM_SMS,CcmSmsGetSmsAddrfromPdu_1,P_WARNING,swLogPrintf("CCM sms address length %d is incorrect "); +600064,1228935424,0,0,PS1,CCM_SMS,CcmSmsGetUserDatafromPdu_1,P_WARNING,swLogPrintf("CcmSmsGetUserDatafromPdu : user data header length %d , length %d "); +600064,1228937472,0,0,PS1,CCM_SMS,CcmSmsGetUserDatafromPdu_2,P_WARNING,swLogPrintf("CcmSmsGetUserDatafromPdu : user data length %d , user data header length %d "); +600064,1228939264,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_w,P_WARNING,swLogPrintf("PDU length %d is abnormal "); +600064,1228941312,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_1,P_INFO,swLogPrintf("CCM SRR enable / disable %d "); +600064,1228943360,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_2,P_INFO,swLogPrintf("CCM sms message reference from EFsms file is : %d "); +600064,1228945408,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_3,P_INFO,swLogPrintf("CCM sms messageReference is : %d "); +600064,1228947456,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_4,P_INFO,swLogPrintf("CCM sms address length %d is 0 or greater than largest length "); +600064,1228949504,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_5,P_WARNING,swLogPrintf("CCM SMS , Incorrect validityPeriodFormat %d "); +600064,1228951552,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_6,P_WARNING,swLogPrintf("CCM SMS , Incorrect PDU Length %d "); +600064,1228955647,0,0,PS1,CCM_SMS,CcmMsgConstructSmsSendReqfromPdu_8,P_WARNING,swLogPrintf("CCM SMS , TP-DCS field check failed "); +600064,1228955648,0,0,PS1,CCM_SMS,CcmMsgConvertSmsAddrToBcdNum_1,P_WARNING,swLogPrintf("SMSC address length is too long %d "); +600064,1228959743,0,0,PS1,CCM_SMS,CcmMsgConvertSmsAddrToBcdNum_2,P_WARNING,swLogPrintf("SMSC address can not be decoded to BCD number "); +600064,1228961791,0,0,PS1,CCM_SMS,CcmsmsGetSmsId_1,P_WARNING,swLogPrintf("Invalid SMS ID "); +600064,1228962304,0,0,PS1,CCM_SMS,CcmSmsBuildUserDataToPdu_1,P_INFO,swLogPrintf("CCM SMS , userDataLen = %d , uDataHeadLen = %d , bits7Len = %d "); +600064,1228965887,0,0,PS1,CCM_SMS,CcmSmsBuildUserDataToPdu_2,P_INFO,swLogPrintf("CCM SMS , No User Data , but just UDH "); +600064,1228966144,0,0,PS1,CCM_SMS,CcmSmsGenerateCbsDeliveryPDU_1,P_WARNING,swLogPrintf("Page length %d of page %d is not correct "); +600064,1228967936,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_1,P_WARNING,swLogPrintf("ccm sms state : %d not correct when sending SMS "); +600064,1228972031,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_2,P_WARNING,swLogPrintf("ccm reg is under registration when sending SMS "); +600064,1228974079,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_3,P_INFO,swLogPrintf("SMSC address can be used directly "); +600064,1228976127,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_4,P_INFO,swLogPrintf("Get smsc address from USIM firstly "); +600064,1228978175,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_5,P_INFO,swLogPrintf("MO Short Message Control by USIM "); +600064,1228980223,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_6,P_ERROR,swLogPrintf("CCM SMS , PDU parameter is incorrect and can not be decoded successfully!! "); +600064,1228980224,0,0,PS1,CCM_SMS,CcmSmsSendMessageReq_7,P_WARNING,swLogPrintf("Wrong ccmSmsContext.state %d "); +600064,1228982272,0,0,PS1,CCM_SMS,CcmSmsSendCommandReq_1,P_WARNING,swLogPrintf("ccm sms status : %d not correct when sms sending "); +600064,1228986367,0,0,PS1,CCM_SMS,CcmSmsSendCommandReq_2,P_WARNING,swLogPrintf("ccm reg is not registered when sms sending "); +600064,1228988415,0,0,PS1,CCM_SMS,CcmSmsSendCommandReq_3,P_WARNING,swLogPrintf("smsc addr can not be got "); +600064,1228990463,0,0,PS1,CCM_SMS,CcmSmsSendCommandReq_4,P_ERROR,swLogPrintf("CCM SMS , PDU parameter is incorrect and can not be decoded successfully!! "); +600064,1228990464,0,0,PS1,CCM_SMS,CcmSmsSendSMMAReq_1,P_WARNING,swLogPrintf("ccm sms state : %d not correct when sending SMMA "); +600064,1228994559,0,0,PS1,CCM_SMS,CcmSmsSendSMMAReq_2,P_WARNING,swLogPrintf("ccm reg is under registration when sending SMMA "); +600064,1228994560,0,0,PS1,CCM_SMS,CcmSmsSendSMMAReq_3,P_INFO,swLogPrintf("CCM sms message reference from EFsms file is : %d "); +600064,1228996608,0,0,PS1,CCM_SMS,CcmSmsSendSMMAReq_4,P_INFO,swLogPrintf("CCM sms messageReference is : %d "); +600064,1228998656,0,0,PS1,CCM_SMS,CcmSmsSendSMMAReq_5,P_WARNING,swLogPrintf("Wrong ccmSmsContext.state %d "); +600064,1229000960,0,0,PS1,CCM_SMS,CcmSmsSetMemCapReq_1,P_VALUE,swLogPrintf("CCM SMS , EFsmss smsMemCapExceed : 0x%x , memCapExceed %d "); +600064,1229004799,0,0,PS1,CCM_SMS,CcmSmsSetMemCapReq_2,P_WARNING,swLogPrintf("CCM SMS , the smsMemCapExceed is same as ccmSmsContext , no need to send to SIM "); +600064,1229004800,0,0,PS1,CCM_SMS,CcmSmsProcGetSmspInfoCnfMsg_1,P_INFO,swLogPrintf("gGetSmscForCsca : %d "); +600064,1229007616,0,0,PS1,CCM_SMS,CcmSmsProcGetSmspInfoCnfMsg_2,P_WARNING,swLogPrintf("rcCode : %d , smspDataValid : %d , scAddrPresent : %d , ccmSmsContext.isReady : %d "); +600064,1229008896,0,0,PS1,CCM_SMS,CcmSmsProcGetSmssInfoCnfMsg_1,P_WARNING,swLogPrintf("CCM SMS can not get EFsms infor with sim rc : %d "); +600064,1229010944,0,0,PS1,CCM_SMS,CcmSmsSimOkIndMsg_1,P_WARNING,swLogPrintf("CCM SMS receive simokind in incorrect state : %d "); +600064,1229012992,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlReportIndSig_1,P_WARNING,swLogPrintf("CCM SMS , SMS not succ ( %d ) in CemmSmtlReportInd "); +600064,1229015296,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlReportIndSig_2,P_WARNING,swLogPrintf("CCM SMS , received msg ref ( %d ) is different from global val : %d "); +600064,1229019135,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlDeliveredIndSig_1,P_INFO,swLogPrintf("CCM SMS , start pp download procedure "); +600064,1229019392,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlDeliveredIndSig_2,P_INFO,swLogPrintf("CCM SMS , don ' t need report to upper layer , msgService is %d , sms class is %d "); +600064,1229023231,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlSmsServiceAvailIndSig_1,P_DEBUG,swLogPrintf("CCM SMS , delay 1 sec to report smsMemCapExceed "); +600064,1229025279,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlSmsServiceAvailIndSig_2,P_DEBUG,swLogPrintf("CCM SMS memCapIndDelayTimer is running , stop it since SMS service is not available "); +600064,1229025280,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmtlSmsServiceAvailIndSig_3,P_WARNING,swLogPrintf("CCM SMS receive CemmSmtlSmsServiceAvailInd in wrong state : %d "); +600064,1229027840,0,0,PS1,CCM_SMS,bFilteredMessageId_0,P_INFO,swLogPrintf("CCM SMS , messageIdentifier : %d , mode : %d , bFiltered : %d "); +600064,1229029888,0,0,PS1,CCM_SMS,bFilteredDcs_0,P_INFO,swLogPrintf("CCM SMS , dcs : %d , mode : %d , bFiltered : %d "); +600064,1229031424,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmcbEtwsCmasDataIndSig_1,P_WARNING,swLogPrintf("CCM Page number is not correct : %d "); +600064,1229033728,0,0,PS1,CCM_SMS,CcmSmsProcCemmSmcbEtwsCmasDataIndSig_2,P_WARNING,swLogPrintf("CCM CBS Filter message : mode : %d , bFilterAllCb : %d "); +600064,1229035520,0,0,PS1,CCM_SMS,CcmSmsProcMoSmControCnfFunc_1,P_INFO,swLogPrintf("CCM SMS , mosm control result : %d "); +600064,1229037568,0,0,PS1,CCM_SMS,CcmSmsProcMoSmControCnfFunc_2,P_WARNING,swLogPrintf("CCM SMS , Invalid MO SMS CONTROL Response %d "); +600064,1229041663,0,0,PS1,CCM_SMS,CcmSmsProcWriteSmssInfoCnfMsg_1,P_INFO,swLogPrintf("SMSS update successfully "); +600064,1229041664,0,0,PS1,CCM_SMS,CcmSmsProcWriteSmssInfoCnfMsg_2,P_VALUE,swLogPrintf("smsMemCapExceed : %d "); +600064,1229045759,0,0,PS1,CCM_SMS,CcmSmsSendMoreMessageReqFunc_1,P_INFO,swLogPrintf("Change Sms send more message mode from 1 to 0 . "); +600064,1229045760,0,0,PS1,CCM_SMS,CcmSmsProcUsatPpDownloadCnfFunc_1,P_WARNING,swLogPrintf("CCM SMS , Unknown SIM Confirmation %d "); +600064,1229047808,0,0,PS1,CCM_SMS,CcmSmsProcUsatSendSmIndFunc_1,P_INFO,swLogPrintf("CCM SMS , sms proactive msg scAddr length : %d "); +600064,1229049856,0,0,PS1,CCM_SMS,CcmSmsProcUsatSendSmIndFunc_2,P_INFO,swLogPrintf("CCM SMS , sms proactive msg tpdu type : %d "); +600064,1229052416,0,0,PS1,CCM_SMS,CcmSmsProcReadSimSmCnfFunc_1,P_VALUE,swLogPrintf("CCM SMS Read result : Trasid : %d , cnfStatus : %d , smStatus : %d "); +600064,1229054464,0,0,PS1,CCM_SMS,CcmSmsProcWriteSimSmCnfFunc_1,P_VALUE,swLogPrintf("CCM SMS Write result : Trasid : %d , cnfStatus : %d , ret index : %d "); +600064,1229056768,0,0,PS1,CCM_SMS,CcmSmsProcListSimSmCnfFunc_1,P_VALUE,swLogPrintf("CCM SMS List result : index : %d , cnfStatus : %d , final result : %d , tpduLen : %d "); +600064,1229058560,0,0,PS1,CCM_SMS,CcmSmsProcListSmStorageStatusCnfFunc_1,P_VALUE,swLogPrintf("CCM SMS SIM Storage info : transId : %d , usedNum : %d , totalNum : %d "); +601088,1231032319,0,0,PS1,CCM_SIM,CcmSimProcAppStartedInd_1,P_VALUE,swLogPrintf("MSG = > CcmDevProcSimPoweronCnfMsg , srcId : 21 , argvUint8 : 1 , argvUint16 : 0 , argvUint32 : 0 "); +601088,1231032320,0,0,PS1,CCM_SIM,CcmSimProcAppStartedInd_2,P_ERROR,swLogPrintf("The uicc card inserted in Error state : %x , stop uicc initialization... "); +601088,1231036415,0,0,PS1,CCM_SIM,CcmSimProcAppStartedInd_3,P_VALUE,swLogPrintf("MSG = > CcmDevProcSimPoweronCnfMsg , srcId : 21 , argvUint8 : 0 , argvUint16 : 0 , argvUint32 : 0 "); +601088,1231036416,0,0,PS1,CCM_SIM,CcmSimProcAppInitCnf_1,P_ERROR,swLogPrintf("Unknown UICC Initialise failure cause : %x ! "); +601088,1231038464,0,0,PS1,CCM_SIM,CcmSimProcCardRemovedInd_0,P_VALUE,swLogPrintf("The uicc state of simUiccStaticCtx is %d "); +601088,1231042559,0,0,PS1,CCM_SIM,CcmSimProcCardRemovedInd_1,P_VALUE,swLogPrintf("MSG = > CcmDevProcSimPoweronCnfMsg , srcId : 21 , argvUint8 : 0 , argvUint16 : 0 , argvUint32 : 0 "); +601088,1231044607,0,0,PS1,CCM_SIM,CcmSimProcCardRemovedInd_2,P_VALUE,swLogPrintf("The uicc state has been removed , nothing to do "); +601088,1231046655,0,0,PS1,CCM_SIM,CcmSimProcGenAccessCnf_1,P_ERROR,swLogPrintf("Unknown command reference! "); +601088,1231046656,0,0,PS1,CCM_SIM,CcmSimProcReadDataCnf_1,P_WARNING,swLogPrintf("Unknown trans id %d "); +601088,1231048704,0,0,PS1,CCM_SIM,CcmSimProcReadDataCnf_2,P_WARNING,swLogPrintf("Unknown request item : %x! "); +601088,1231050752,0,0,PS1,CCM_SIM,CcmSimProcUpdateDataCnf_1,P_ERROR,swLogPrintf("Unknown request item : %x! "); +601088,1231054847,0,0,PS1,CCM_SIM,CcmSimProcEpsConnectionModeInd_1,P_WARNING,swLogPrintf("No simUsatDynCtx is available! "); +601088,1231056895,0,0,PS1,CCM_SIM,CcmSimProcEpsConnectionModeInd_2,P_INFO,swLogPrintf("curr power off state , clear locStatusChange "); +601088,1231057152,0,0,PS1,CCM_SIM,CcmSimStartCfunGuardTimer_1,P_VALUE,swLogPrintf("timer : %d start , timerPeriod : %d "); +601088,1231058944,0,0,PS1,CCM_SIM,CcmSimStartCfunGuardTimer_2,P_VALUE,swLogPrintf("timer : %d has already been started "); +601088,1231060992,0,0,PS1,CCM_SIM,CcmSimStopCfunGuardTimer_1,P_VALUE,swLogPrintf("timer : %d stop "); +601088,1231065087,0,0,PS1,CCM_SIM,CcmSimProcCfunGuardTimerExpiry_1,P_VALUE,swLogPrintf("MSG = > CcmDevProcSimPoweronCnfMsg , srcId : 21 , argvUint8 : 0 , argvUint16 : 0 , argvUint32 : 0 "); +601088,1231067135,0,0,PS1,CCM_SIM,CcmSimProcCfunGuardTimerExpiry_2,P_VALUE,swLogPrintf("MSG = > CcmDevProcSimPoweronCnfMsg , srcId : 21 , argvUint8 : 0 , argvUint16 : 0 , argvUint32 : 0 "); +601088,1231069183,0,0,PS1,CCM_SIM,CcmSimProcCfunGuardTimerExpiry_3,P_ERROR,swLogPrintf("CCM SIM , SIM cfun guard timer expiry , but no such time info in CCM SIM side "); +601088,1231071231,0,0,PS1,CCM_SIM,CcmSimProcCfunGuardTimerExpiry_4,P_WARNING,swLogPrintf("CCM SIM , SIM cfun guard timer expiry , need to abort the UICC procedure "); +601088,1231071232,0,0,PS1,CCM_SIM,CcmSimUsatProcTerminalProfileCnf_1,P_WARNING,swLogPrintf("unknown terminal profile operation mode %d "); +601088,1231073280,0,0,PS1,CCM_SIM,CcmSimUsatProcRefreshInd_1,P_WARNING,swLogPrintf("Currently the refresh qualifier ( %x ) is not support! "); +601088,1231075328,0,0,PS1,CCM_SIM,CcmSimUsatProcProvideLocalInfoInd_1,P_WARNING,swLogPrintf("Currently the command qualifier ( %x ) is not supported in CCM! "); +601088,1231077888,0,0,PS1,CCM_SIM,CcmSimUsatProcSendDataInd_1,P_INFO,swLogPrintf("Immediate mode : stored PDU length %d , SendDataInd Length %d , offset %d "); +601088,1231079680,0,0,PS1,CCM_SIM,CcmSimUsatProcSendDataInd_2,P_INFO,swLogPrintf("Immediate mode : create new PDU for SendDataInd Length %d , offset %d "); +601088,1231081984,0,0,PS1,CCM_SIM,CcmSimUsatProcSendDataInd_3,P_INFO,swLogPrintf("Stored mode : stored PDU length %d , new SendDataInd Length %d , offset %d "); +601088,1231083520,0,0,PS1,CCM_SIM,CcmSimUsatProcSendDataInd_4,P_INFO,swLogPrintf("Stored mode : create nww PDU for SendDataInd Length %d , offset "); +601088,1231085568,0,0,PS1,CCM_SIM,CcmSimUsatProcEventDownloadCnf_1,P_WARNING,swLogPrintf("The event ( %x ) download confirm is not ok! "); +601088,1231087872,0,0,PS1,CCM_SIM,CcmSimHandleUiccFailure_0,P_VALUE,swLogPrintf("simUiccStaticCtx.uiccState %d , NokCause %d "); +601088,1231090432,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_1,P_INFO,swLogPrintf("regstate %d , bLocInfoChange %d , tac %x , currConnStatus %d "); +601088,1231093759,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_debug_1,P_INFO,swLogPrintf("simUsatDynCtx is null , do nothing "); +601088,1231095807,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_debug_2,P_INFO,swLogPrintf("refresh is Ongoing , do nothing "); +601088,1231097855,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_debug_3,P_INFO,swLogPrintf("curr power off state , do nothing "); +601088,1231097856,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_2,P_INFO,swLogPrintf("Location status ( %d ) and location info are not changed "); +601088,1231101951,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_3,P_INFO,swLogPrintf("Location status-limit service is not changed "); +601088,1231103999,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_4,P_INFO,swLogPrintf("Location status-no service is not changed "); +601088,1231104000,0,0,PS1,CCM_SIM,CcmSimRegStatusChangeInfoInd_5,P_INFO,swLogPrintf("Unknown Dereg type %x! "); +601088,1231106304,0,0,PS1,CCM_SIM,CcmSimProcUsatDataAvailableReq_1,P_INFO,swLogPrintf("BIP PDU channel Id %d is invalid , saved bipChannel Id %d "); +601088,1231110143,0,0,PS1,CCM_SIM,CcmSimUsatReceiveDataRspFunc_0,P_INFO,swLogPrintf("pDataPdu->ptr is null "); +601088,1231112191,0,0,PS1,CCM_SIM,CcmSimUsatReceiveDataRspFunc_1,P_INFO,swLogPrintf("pDataPdu is null "); +601088,1231112192,0,0,PS1,CCM_SIM,CcmSimUsatRefreshResetFunc_1,P_WARNING,swLogPrintf("Refresh qualifier ( %x ) is wrong! "); +601088,1231114240,0,0,PS1,CCM_SIM,CcmSimSetSimSleepFunc_1,P_VALUE,swLogPrintf("Set SIM sleep mode : %d "); +601088,1231116288,0,0,PS1,CCM_SIM,CcmSimGetPreferPlmnListReqFunc_1,P_WARNING,swLogPrintf("unknown select prefer plmn list %d "); +606208,1241516288,0,0,PS1,CAM,CamProcCmiReq_1,P_ERROR,swLogPrintf("CAM , SG : %d , can ' t process the reqPrimId : %d "); +606208,1241518336,0,0,PS1,CAM,CamProcCmiRsp_1,P_ERROR,swLogPrintf("CAM , SG : %d , can ' t process the rspPrimId : %d "); +606208,1241520640,0,0,PS1,CAM,CamCmiSyncSigCnf_w_1,P_WARNING,swLogPrintf("CAM , CMI SYNC CNF , cnfId : 0x%x , handler : 0x%x , but no req pending : 0x%x "); +606208,1241522432,0,0,PS1,CAM,CamProcCamCmiSyncReqSig_w_1,P_WARNING,swLogPrintf("CAM , CMI SYNC table full : 0x%lx , can ' t proc reqId : 0x%lx "); +606208,1241524480,0,0,PS1,CAM,CamProcCenasCamSetParmCnfSig_1,P_WARNING,swLogPrintf("CAM Main , CEMM PARM setting : ( %d ) , confirm failed : ( %d ) "); +606208,1241526528,0,0,PS1,CAM,CamProcCemmCacGetParmCnfSig_1,P_WARNING,swLogPrintf("CAC Main , NAS get PARM : ( %d ) , confirm failed : ( %d ) "); +606208,1241530367,0,0,PS1,CAM,CamCmiReqEnBuf_1,P_WARNING,swLogPrintf("CAM ; CmiReq BIT buffer full : total 16 request "); +606208,1241530368,0,0,PS1,CAM,CamCmiReqOnBuf_1,P_VALUE,swLogPrintf("CAM , CmiReqId : 0x%lx , already found in the pending buffer "); +606208,1241532416,0,0,PS1,CAM,CamCmiReqBufDelLastOutput_1,P_WARNING,swLogPrintf("CAM , invalid lastOutput index : %d in pending CmiReq buffer "); +607232,1243613184,0,0,PS1,CAM_DEV,CamDevCmiDevSetCfunReqFunc_1,P_WARNING,swLogPrintf("CAM DEV : not support cfun : %d "); +607232,1243615232,0,0,PS1,CAM_DEV,CamDevCmiDevSetCiotBandReqFunc_1,P_WARNING,swLogPrintf("CAM DEV : not support ECBAND setting parms , bandNum : %d "); +607232,1243617280,0,0,PS1,CAM_DEV,CamDevCmiDevSetCiotFreqReqFunc_1,P_WARNING,swLogPrintf("AT+ECFREQ , invalid mode : %d "); +607232,1243619328,0,0,PS1,CAM_DEV,CamDevCmiDevSetCiotFreqReqFunc_2,P_WARNING,swLogPrintf("AT+ECFREQ , set FREQ , but no FREQ / more FREQ : %d "); +607232,1243621632,0,0,PS1,CAM_DEV,CamDevCmiDevSetCiotFreqReqFunc_3,P_WARNING,swLogPrintf("AT+ECFREQ , LOCK CELL , but no FREQ / more FREQ : %d , or invalid phyCellId : %d "); +607232,1243623424,0,0,PS1,CAM_DEV,CamDevCmiDevSetPowerStateReqFunc_1,P_WARNING,swLogPrintf("CAM DEV : not support CIOTPOWER : %d "); +607232,1243627519,0,0,PS1,CAM_DEV,CamDevCmiDevSetPowerStateReqFunc_4,P_SIG,swLogPrintf("CAM DEV , CIOTPOWER wake from HIB "); +607232,1243629567,0,0,PS1,CAM_DEV,CamDevCmiDevSetPowerStateReqFunc_5,P_SIG,swLogPrintf("CAM DEV , CIOTPOWER wake from SLEEP2 "); +607232,1243631615,0,0,PS1,CAM_DEV,CamDevCmiDevSetPowerStateReqFunc_6,P_SIG,swLogPrintf("CAM DEV , CIOTPOWER wake from HIB / SLEEP2 "); +607232,1243633663,0,0,PS1,CAM_DEV,CamDevCmiDevSetExtCfgReqFunc_1,P_WARNING,swLogPrintf("CAM DEV , no valid CFG set in AT+ECCFG "); +607232,1243635711,0,0,PS1,CAM_DEV,CamDevCmiDevSetExtCfgReqFunc_4,P_WARNING,swLogPrintf("Some Parameters must be restricted to execute in the CFUN0 or CFUN4 state "); +607232,1243637759,0,0,PS1,CAM_DEV,CamDevCmiDevSetExtCfgReqFunc_5,P_WARNING,swLogPrintf("CAM DEV , AT+ECCFG set failed , maybe some parameters not suitable "); +607232,1243637760,0,0,PS1,CAM_DEV,CamDevCmiDevRemoveFPlmnReqFunc_1,P_WARNING,swLogPrintf("CAM DEV : not support AT+ECRMFPLMN : %d "); +607232,1243641855,0,0,PS1,CAM_DEV,CamDevCmiDevGetExtStatusReqFunc_1,P_WARNING,swLogPrintf("CAM DEV , another AT+ECSTATUS? is ongoing , can ' t request again "); +607232,1243643903,0,0,PS1,CAM_DEV,CamDevCmiDevSetExtStatisModeReqFunc_1,P_WARNING,swLogPrintf("CAM DEV , AT+ECSTATUS? is ongoing , can ' t request this "); +607232,1243645951,0,0,PS1,CAM_DEV,CamDevCmiDevGetBasicCellListInfoReqFunc_1,P_WARNING,swLogPrintf("CAM DEV , another AT+ECBCINFO / CFUN / COPS is ongoing , can ' t proc current : AT+ECBCINFO "); +607232,1243646208,0,0,PS1,CAM_DEV,CamDevCmiDevGetBasicCellListInfoReqFunc_param_1,P_WARNING,swLogPrintf("CAM DEV , another AT+ECBCINFO , invalid mode : %d , or invalid rptMode : %d "); +607232,1243650047,0,0,PS1,CAM_DEV,CamDevCmiDevGetPsTestReqFunc_1,P_WARNING,swLogPrintf("CAM DEV , another AT+ECPSTEST? is ongoing , can ' t request again "); +607232,1243650048,0,0,PS1,CAM_DEV,CamDevCmiDevSetPowerClassReqFunc_1,P_WARNING,swLogPrintf("CAM DEV : not support ECPOWERCLASS setting parms , power class : %d "); +607232,1243654143,0,0,PS1,CAM_DEV,CamDevCmiDevGetPowerClassReqFunc_1,P_WARNING,swLogPrintf("CAM DEV , another AT+ECPOWERCLASS? is ongoing , can ' t request again "); +607232,1243656191,0,0,PS1,CAM_DEV,CamDevSetCfunCnf_1,P_WARNING,swLogPrintf("CAM DEV ; no CMI_DEV_SET_CFUN_REQ pending when process the cfun CNF from CCM DEV "); +607232,1243658239,0,0,PS1,CAM_DEV,CamDevSetCiotBandCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_SET_CIOT_BAND_REQ ' pending , when process the SET CIOT BAND CONF from CCM REG "); +607232,1243660287,0,0,PS1,CAM_DEV,CamDevSetCiotFreqCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_SET_CIOT_REQ_REQ ' pending , when process the SET CIOT FREQ CONF from CCM REG "); +607232,1243662335,0,0,PS1,CAM_DEV,CamDevGetCurCiotBandCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_CIOT_BAND_REQ ' pending , when process the GET CIOT BAND CONF from CCM REG "); +607232,1243662336,0,0,PS1,CAM_DEV,CamDevGetCurCiotBandCnf_2,P_ERROR,swLogPrintf("CAM DEV , current bandNum : %d , no band info in current setting "); +607232,1243664384,0,0,PS1,CAM_DEV,CamDevGetCurCiotBandCnf_3,P_WARNING,swLogPrintf("CAM DEV , can ' t get current band info , rc : %d "); +607232,1243668479,0,0,PS1,CAM_DEV,CamDevGetCiotBandCapaCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_CIOT_BAND_CAPA_REQ ' pending , when process the GET CIOT BAND CAPA CONF from CCM REG "); +607232,1243668480,0,0,PS1,CAM_DEV,CamDevGetCiotBandCapaCnf_2,P_ERROR,swLogPrintf("CAM DEV , bandNum : %d , no band CAPC info "); +607232,1243670528,0,0,PS1,CAM_DEV,CamDevGetCiotBandCapaCnf_3,P_WARNING,swLogPrintf("CAM DEV , can ' t get band CAPA info , rc : %d "); +607232,1243674623,0,0,PS1,CAM_DEV,CamDevGetCurCiotFreqCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_CIOT_FREQ_REQ ' pending , when process the GET CIOT FREQ CONF from CCM REG "); +607232,1243674624,0,0,PS1,CAM_DEV,CamDevGetCurCiotFreqCnf_2,P_WARNING,swLogPrintf("CAM DEV , can ' t get current FREQ info , rc : %d "); +607232,1243678719,0,0,PS1,CAM_DEV,CamDevSetPowerStateCnf_1,P_WARNING,swLogPrintf("CAM DEV ; no CMI_DEV_SET_POWER_STATE_REQ pending when process the POWER CNF from CCM DEV "); +607232,1243680767,0,0,PS1,CAM_DEV,CamDevCemmCacRemoveFPlmnCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_REMOVE_FPLMN_REQ ' pending , when process the REMOVE FPLMN CNF "); +607232,1243682815,0,0,PS1,CAM_DEV,CamDevGetExtCfgCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_EXT_CFG_REQ ' pending , when process the get ExtCfg CNF "); +607232,1243684863,0,0,PS1,CAM_DEV,CamDevGetPsTestCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_ECPSTEST_REQ ' pending , when process the get PS test enable mode CNF "); +607232,1243686911,0,0,PS1,CAM_DEV,CamDevSetPowerClassCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_SET_ECPOWERCLASS_REQ ' pending , when process the set power class confirm from CCM DEV "); +607232,1243688959,0,0,PS1,CAM_DEV,CamDevGetPowerClassCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_ECPOWERCLASS_REQ ' pending , when process the get power class confirm "); +607232,1243691007,0,0,PS1,CAM_DEV,CamDevGetPowerClassCapaCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_ECPOWERCLASS_CAPA_REQ ' pending , when process the get power class capability confirm "); +607232,1243693055,0,0,PS1,CAM_DEV,CamDevGetExtStatusCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_EXT_STATUS_REQ ' pending , when process the get ExtCfg CNF "); +607232,1243695103,0,0,PS1,CAM_DEV,CamDevGetBasicCellListInfoCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_BASIC_CELL_LIST_INFO_REQ ' pending , when process the get basic cell info CNF "); +607232,1243697151,0,0,PS1,CAM_DEV,CamDevCmiDevGetEventStatusFunc_1,P_WARNING,swLogPrintf("CAM DEV , another AT+ECEVENTSTATIS? is ongoing , can ' t request again "); +607232,1243699199,0,0,PS1,CAM_DEV,CamDevSetEventStatisCnf_1,P_WARNING,swLogPrintf("CAM DEV ; no CMI_DEV_SET_ECEVENTSTATIS_MODE_REQ pending when process the AT+ECEVENTSTATIS = CNF from CCM DEV "); +607232,1243701247,0,0,PS1,CAM_DEV,CamDevSendEventStatisCnf_1,P_WARNING,swLogPrintf("CAM DEV ; no CMI_DEV_GET_ECEVENTSTATIS_STATUS_REQ pending when process the AT+ECEVENTSTATIS? CNF from CCM DEV "); +607232,1243703295,0,0,PS1,CAM_DEV,CamDevGetNBRelFeatureCnf_1,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_NB_REL_FEATURE_REQ ' pending , when process the NB Rel feature CNF "); +607232,1243705343,0,0,PS1,CAM_DEV,CamDevGetTimerParaCnf_0,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_GET_NAS_TIMER_PARA_REQ ' pending , when process CenasGetTimerParmInfo CNF "); +607232,1243707391,0,0,PS1,CAM_DEV,CamDevSetTimerParaCnf_0,P_WARNING,swLogPrintf("CAM DEV , no ' CMI_DEV_SET_NAS_TIMER_PARA_REQ ' pending , when process set NAS Timer CNF "); +608256,1245710336,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_1,P_WARNING,swLogPrintf("CAM MM , invalid year : 0x%x in EMM TZ INFO "); +608256,1245712384,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_2,P_WARNING,swLogPrintf("CAM MM , invalid nomth : 0x%x in EMM TZ INFO "); +608256,1245714432,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_3,P_WARNING,swLogPrintf("CAM MM , invalid day : 0x%x in EMM TZ INFO "); +608256,1245716480,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_4,P_WARNING,swLogPrintf("CAM MM , invalid hour : 0x%x in EMM TZ INFO "); +608256,1245718528,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_5,P_WARNING,swLogPrintf("CAM MM , invalid minute : 0x%x in EMM TZ INFO "); +608256,1245720576,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_6,P_WARNING,swLogPrintf("CAM MM , invalid second : 0x%x in EMM TZ INFO "); +608256,1245722624,0,0,PS1,CAM_MM,CamMmDecodeUTCInfoFromEmmTimeInfo_7,P_WARNING,swLogPrintf("CAM MM , invalid timeZone : 0x%x in EMM TZ INFO "); +608256,1245724672,0,0,PS1,CAM_MM,CamMmCmiMmManualPlmnSelectReqFunc_1,P_WARNING,swLogPrintf("CAM MM , invalid manualMode : %d , in CMI_MM_MANUAL_PLMN_SELECT_REQ "); +608256,1245726976,0,0,PS1,CAM_MM,CamMmCmiMmManualPlmnSelectReqFunc_2,P_WARNING,swLogPrintf("CAM MM , invalid plmnFormat : %d , or act : %d , in CMI_MM_MANUAL_PLMN_SELECT_REQ "); +608256,1245729024,0,0,PS1,CAM_MM,CamMmCmiMmManualPlmnSelectReqFunc_3,P_WARNING,swLogPrintf("CAM MM , invalid plmn : %x , %x , in CMI_MM_MANUAL_PLMN_SELECT_REQ "); +608256,1245730816,0,0,PS1,CAM_MM,CamMmCmiMmSetOperIdFormatReqFunc_1,P_ERROR,swLogPrintf("CAM MM , invalid PLMN format setting : %d "); +608256,1245732864,0,0,PS1,CAM_MM,CamMmCmiMmManualPlmnSearchReqFunc_1,P_VALUE,swLogPrintf("CAM MM , Manual Plmn search gard timer is : %d sec "); +608256,1245735168,0,0,PS1,CAM_MM,CamMmCmiMmSetPsmParmReqFunc_1,P_WARNING,swLogPrintf("CAM MM , not support req mode : %d , or req bit map : 0x%lx in CmiMmSetPsmParmReq "); +608256,1245737216,0,0,PS1,CAM_MM,CamMmCmiMmSetEdrxParmReqFunc_1,P_WARNING,swLogPrintf("CAM MM , not support req mode : %d , or actType : %d , in CmiMmSetEdrxParmReq "); +608256,1245739264,0,0,PS1,CAM_MM,CamMmCmiMmSetEdrxParmReqFunc_4,P_WARNING,swLogPrintf("CAM MM , not right reqEdrxValue : %d / reqEdrxValueMs : %d , in CmiMmSetEdrxParmReq "); +608256,1245741056,0,0,PS1,CAM_MM,CamMmCemmCamGetRequestedEdrxParmCnf_1,P_WARNING,swLogPrintf("CAM MM , can ' t get UE request EDRX parm : %d "); +608256,1245745151,0,0,PS1,CAM_MM,CamMmCemmCamGetEdrxDynParmCnf_1,P_WARNING,swLogPrintf("CAM MM , NW config to use EDRX , but UE requested / configed EDRX parm is not avaiable "); +608256,1245745152,0,0,PS1,CAM_MM,CamMmCemmCamGetEdrxDynParmCnf_2,P_WARNING,swLogPrintf("CAM MM , can ' t get UE DYN EDRX parm : %d "); +608256,1245747200,0,0,PS1,CAM_MM,CamMmCemmCamGetRequestedPtwEdrxParmCnf_1,P_WARNING,swLogPrintf("CAM MM , can ' t get UE request PTW / EDRX parm : %d "); +608256,1245749504,0,0,PS1,CAM_MM,CamMmCmiMmSetPtwEdrxParmReqFunc_1,P_WARNING,swLogPrintf("CAM MM , not support req mode : %d , or actType : %d , in CmiMmSetPtwEdrxParmReq "); +608256,1245751552,0,0,PS1,CAM_MM,CamMmCmiMmSetPtwEdrxParmReqFunc_2,P_WARNING,swLogPrintf("CAM MM , not right reqEdrxValue : %d / reqEdrxValueMs : %d , in CmiMmSetPtwEdrxParmReq "); +608256,1245755391,0,0,PS1,CAM_MM,CamMmCmiMmSetCiotOptCfgReqFunc_1,P_WARNING,swLogPrintf("CAM MM , set CCIOTOPT , no valid PARM input "); +608256,1245755904,0,0,PS1,CAM_MM,CamMmCmiMmSetCiotOptCfgReqFunc_2,P_WARNING,swLogPrintf("CAM MM , set CCIOTOPT , invalid PARM : reportMode ( %d ) , ueSuptOptType ( %d ) , uePreferOpt ( %d ) "); +608256,1245757696,0,0,PS1,CAM_MM,CamMmCmiMmSetCiotOptCfgReqFunc_3,P_WARNING,swLogPrintf("CAM MM , set CCIOTOPT , invalid input ueSuptOptType : %d , uePreferOpt : %d , ( 0 -NO_OPT , 1 -CP_OPT , 2 -UP_OPT , 3 -CP_UP_OPT ) "); +608256,1245759488,0,0,PS1,CAM_MM,CamMmCmiMmSetCiotOptCfgReqFunc_4,P_INFO,swLogPrintf("CAM MM , set CCIOTOPT , only set the report type to : %d "); +608256,1245763583,0,0,PS1,CAM_MM,CamMmRegProcedureCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_SET_AUTO_PLMN_REQ / CMI_MM_MANUAL_PLMN_SELECT_REQ ' pending , when process the REG CNF from CCM REG "); +608256,1245765631,0,0,PS1,CAM_MM,CamMmDeregProcedureCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_DEREGISTER_REQ ' pending , when process the DEREG CNF from CCM REG "); +608256,1245767679,0,0,PS1,CAM_MM,CamMmManualPlmnSearchCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_MANUAL_PLMN_SEARCH_REQ ' pending , when process the MANUAL PLMN SEARCH CNF from CCM REG "); +608256,1245769727,0,0,PS1,CAM_MM,CamMmCemmCamSetPsmParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_SET_REQUESTED_PSM_PARM_REQ ' pending , when process the PSM PARM setting CNF "); +608256,1245771775,0,0,PS1,CAM_MM,CamMmCemmCamSetEdrxParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_SET_REQUESTED_EDRX_PARM_REQ ' pending , when process the EDRX PARM setting CNF "); +608256,1245773823,0,0,PS1,CAM_MM,CamMmCemmCamSetPtwEdrxParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_SET_REQUESTED_PTW_EDRX_PARM_REQ ' pending , when process the PTW / EDRX PARM setting CNF "); +608256,1245775871,0,0,PS1,CAM_MM,CamMmCemmCamSetCiotOptCfgParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_SET_CIOT_OPT_CFG_REQ ' pending , when process the CIOT OPT CFG PARM setting CNF "); +608256,1245777919,0,0,PS1,CAM_MM,CamMmCemmCamGetRequestPsmParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_GET_REQUESTED_PSM_PARM_REQ ' pending , when process the GET PSM REQUEST PARM CNF "); +608256,1245779967,0,0,PS1,CAM_MM,CamMmCemmCamGetEdrxParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_GET_REQUESTED_PSM_PARM_REQ / CMI_MM_READ_EDRX_DYN_PARM_REQ ' pending , when process the GET EDRX REQUEST PARM CNF "); +608256,1245782015,0,0,PS1,CAM_MM,CamMmCemmCamGetPtwEdrxParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_GET_REQUESTED_PTW_PSM_PARM_REQ ' pending , when process the GET PTW EDRX REQUEST PARM CNF "); +608256,1245784063,0,0,PS1,CAM_MM,CamMmCemmCamGetCiotOptCfgParmCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_GET_CIOT_OPT_CFG_REQ ' pending , when process the GET CIOT OPT CFG CNF "); +608256,1245786111,0,0,PS1,CAM_MM,CamMmCemmCamGetPlmnSelectStateCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_GET_PLMN_SELECT_STATE_REQ ' pending , when process the CMI_MM_GET_PLMN_SELECT_STATE_CNF "); +608256,1245788159,0,0,PS1,CAM_MM,CamMmOosPlmnSelectCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_START_OOS_PLMN_SELECT_REQ ' pending , when process the CMI_MM_START_OOS_PLMN_SELECT_CNF from CCM REG "); +608256,1245790207,0,0,PS1,CAM_MM,CamMmEmmNwInfoInd_1,P_WARNING,swLogPrintf("CAM MM , no valid info in ' EMM information ' "); +608256,1245790208,0,0,PS1,CAM_MM,CamMmEmmNwInfoInd_2,P_WARNING,swLogPrintf("CAM MM , invalid localTimeZone : 0x%x in EMM TZ INFO "); +608256,1245794303,0,0,PS1,CAM_MM,CamMmCmiMmGetCurOperNameCnf_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_GET_CURRENT_OPER_NAME_REQ ' pending , when process the CMI_MM_GET_CURRENT_OPER_NAME_CNF from CCM REG "); +608256,1245796351,0,0,PS1,CAM_MM,CamMmTriggerTauCnfFunc_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_TRIGGER_TAU_REQ ' pending "); +608256,1245796352,0,0,PS1,CAM_MM,CamMmTriggerTauCnfFunc_2,P_WARNING,swLogPrintf("CAM MM , TAU is triggered : %d "); +608256,1245800447,0,0,PS1,CAM_MM,CamMmTriggerRrcReleaseCnfFunc_1,P_WARNING,swLogPrintf("CAM MM , no ' CMI_MM_TRIGGER_RRC_RELEASE_REQ ' pending "); +608256,1245800448,0,0,PS1,CAM_MM,CamMmTriggerRrcReleaseCnfFunc_2,P_WARNING,swLogPrintf("CAM MM , RRC Release is triggered : %d "); +609280,1247809535,0,0,PS1,CAM_PS,CamPsCmiPsGetDefinedBearerCtxReqFunc_1,P_WARNING,swLogPrintf("CAM PS , another ' CMI_PS_GET_DEFINED_BEARER_CTX_REQ ' is pending , can ' t process this one "); +609280,1247809536,0,0,PS1,CAM_PS,CamPsCmiPsGetDefinedBearerCtxReqFunc_2,P_WARNING,swLogPrintf("CAM PS , invalid CID : %d in CMI_PS_GET_DEFINED_BEARER_CTX_REQ "); +609280,1247813631,0,0,PS1,CAM_PS,CamPsCmiPsGetDedBearerCtxReqFunc_1,P_WARNING,swLogPrintf("CAM PS , another ' CMI_PS_GET_DEFINED_DEDICATED_BEARER_CTX_REQ ' is pending , can ' t process this one "); +609280,1247813632,0,0,PS1,CAM_PS,CamPsCmiPsGetDedBearerCtxReqFunc_2,P_WARNING,swLogPrintf("CAM PS , invalid CID : %d in CMI_PS_GET_DEFINED_DEDICATED_BEARER_CTX_REQ "); +609280,1247817727,0,0,PS1,CAM_PS,CamPsCmiPsReadDynBearerCtxReqFunc_1,P_WARNING,swLogPrintf("CAM PS , another ' CMI_PS_READ_BEARER_DYN_CTX_REQ ' is pending , can ' t process this one "); +609280,1247817728,0,0,PS1,CAM_PS,CamPsCmiPsReadDynBearerCtxReqFunc_2,P_WARNING,swLogPrintf("CAM PS , invalid CID : %d in : CGCONTRDP "); +609280,1247821823,0,0,PS1,CAM_PS,CamPsCmiPsReadDynDedBearerCtxReqFunc_1,P_WARNING,swLogPrintf("CAM PS , another ' CMI_PS_READ_DEDICATED_BEARER_DYN_CTX_REQ ' is pending , can ' t process this one "); +609280,1247821824,0,0,PS1,CAM_PS,CamPsCmiPsReadDynDedBearerCtxReqFunc_2,P_WARNING,swLogPrintf("CAM PS , invalid CID : %d in : CGSCONTRDP "); +609280,1247824384,0,0,PS1,CAM_PS,CamPsCmiPsSendUlDataReqFunc_1,P_WARNING,swLogPrintf("AT+ECSENDDATA , invalid CID : %d , or length : %d , or pData : %d "); +609280,1247825920,0,0,PS1,CAM_PS,CamPsCmiPsSetAttachWithOrWithoutPdnReqFunc_1,P_ERROR,swLogPrintf("CAM PS , invalid CIPCA param2 : %d "); +609280,1247828480,0,0,PS1,CAM_PS,CamPsCmiSendDataViaCpReq_1,P_WARNING,swLogPrintf("AT+CSODCP , invalid CID : %d , or length : %d , or pData : %d "); +609280,1247830016,0,0,PS1,CAM_PS,CamPsCmiPsTransCiotPlaneReqFunc_1,P_WARNING,swLogPrintf("AT+ECCIOTPLANE , invalid plane set : %d "); +609280,1247834111,0,0,PS1,CAM_PS,CamPsCmiPsTransCiotPlaneReqFunc_2,P_WARNING,swLogPrintf("AT+ECCIOTPLANE , another CMI_PS_TRANS_CIOT_PLANE_REQ pending , can ' t process cur one "); +609280,1247834112,0,0,PS1,CAM_PS,CamPsCmiPsDefineAuthCtxFunc_invalid_0,P_WARNING,swLogPrintf("CAM PS , not supprt auth prot : %d "); +609280,1247836672,0,0,PS1,CAM_PS,CamPsCmiPsDefineAuthCtxFunc_invalid_1,P_WARNING,swLogPrintf("CAM PS , invalid userNameLen : %d , or pwdLen : %d , > %d "); +609280,1247840255,0,0,PS1,CAM_PS,CamPsCmiPsDefineBearerCtxCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEFINE_BEARER_CTX_REQ ' pending "); +609280,1247842303,0,0,PS1,CAM_PS,CamPsCmiPsGetDefinedBearerCtxCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEFINE_BEARER_CTX_REQ ' pending "); +609280,1247842560,0,0,PS1,CAM_PS,CamPsCmiPsGetDefinedBearerCtxCnfFunc_2,P_WARNING,swLogPrintf("CAM PS , CID : %d , is a dedicated bearer , PCID : %d , don ' t need to confirm for CGDCONT "); +609280,1247846399,0,0,PS1,CAM_PS,CamPsCmiPsDelDefineBearerCtxCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEL_BEARER_CTX_REQ ' pending "); +609280,1247848447,0,0,PS1,CAM_PS,CamPsCmiPsModifyEpsEearerCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_MODIFY_BEARER_CTX_REQ ' pending "); +609280,1247850495,0,0,PS1,CAM_PS,CamPsCmiPsDefineDedBearerCtxCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEFINE_DEDICATED_BEARER_CTX_REQ ' pending "); +609280,1247852543,0,0,PS1,CAM_PS,CamPsCmiPsDelDedBearerCtxCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEL_DEDICATED_BEARER_CTX_REQ ' pending "); +609280,1247854591,0,0,PS1,CAM_PS,CamPsCmiPsGetDedBearerCtxCnf_0,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DEFINED_DEDICATED_BEARER_CTX_REQ ' pending "); +609280,1247854848,0,0,PS1,CAM_PS,CamPsCmiPsGetDedBearerCtxCnf_1,P_WARNING,swLogPrintf("CAM PS , CID : %d , is a default bearer , PCID : %d , don ' t need to confirm for CGDSCONT "); +609280,1247858687,0,0,PS1,CAM_PS,CamPsReadBearerDynCtxParamCnfFunc_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_READ_BEARER_DYN_CTX_REQ ' pending "); +609280,1247858944,0,0,PS1,CAM_PS,CamPsReadBearerDynCtxParamCnfFunc_2,P_INFO,swLogPrintf("CAM PS , CID : %d , is a dedicated bearer , PCID : %d , don ' t need to confirm for CGCONTRDP "); +609280,1247860992,0,0,PS1,CAM_PS,CamPsReadBearerDynCtxParamCnfFunc_3,P_INFO,swLogPrintf("CAM PS , CID : %d , brState : %d , is not activated , don ' t need to confirm for CGCONTRDP "); +609280,1247864831,0,0,PS1,CAM_PS,CamPsReadDedBearerDynCtxParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_READ_DEDICATED_BEARER_DYN_CTX_REQ ' pending "); +609280,1247865088,0,0,PS1,CAM_PS,CamPsReadDedBearerDynCtxParamCnf_2,P_WARNING,swLogPrintf("CAM PS , CID : %d , PCID : %d , don ' t need to confirm for CGSCONTRDP "); +609280,1247867136,0,0,PS1,CAM_PS,CamPsReadDedBearerDynCtxParamCnf_3,P_WARNING,swLogPrintf("CAM PS , CID : %d , brState : %d , is not activated , don ' t need to confirm for CGCONTRDP "); +609280,1247870975,0,0,PS1,CAM_PS,CamPsGetBearerIpAddrCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_BEARER_IPADDR_REQ ' pending "); +609280,1247873023,0,0,PS1,CAM_PS,CamPsAttachDetachCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_ATTACH_STATE_REQ ' pending , when process the ATTACH / DETACH CNF "); +609280,1247873024,0,0,PS1,CAM_PS,CamPsAttachDetachCnf_2,P_WARNING,swLogPrintf("CAM PS , AT+CGATT , ATTACH / DETACH Fail : %d "); +609280,1247877119,0,0,PS1,CAM_PS,CamPsCemmCacSetCipcaParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_ATTACH_WITH_OR_WITHOUT_PDN_REQ ' pending , when process the setting CNF "); +609280,1247879167,0,0,PS1,CAM_PS,CamPsCemmCacGetCipcaCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_ATTACH_WITH_OR_WITHOUT_PDN_REQ ' pending , when process the CNF "); +609280,1247881215,0,0,PS1,CAM_PS,CamPsGetAPNRateCtrlCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_APN_RATE_CTRL_PARM_REQ ' pending "); +609280,1247881216,0,0,PS1,CAM_PS,CamPsGetAPNRateCtrlCnf_2,P_WARNING,swLogPrintf("CAM PS , CID : %d not activated , can ' t return APNRC , continue... "); +609280,1247885311,0,0,PS1,CAM_PS,CamPsCmiPsSetDefineTftParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEFINE_TFT_PARM_REQ ' pending "); +609280,1247887359,0,0,PS1,CAM_PS,CamPsCmiPsGetDefineTftParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DEFINED_TFT_PARM_REQ ' pending "); +609280,1247889407,0,0,PS1,CAM_PS,CamPsCmiPsGetDefineTftParamCnf_2,P_WARNING,swLogPrintf("CAM PS , CGTFT request all TFTs , current CID no TFT , check next one "); +609280,1247891455,0,0,PS1,CAM_PS,CamPsCmiPsGetDynTftParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DEFINED_TFT_PARM_REQ ' pending "); +609280,1247893503,0,0,PS1,CAM_PS,CamPsCmiPsGetDynTftParamCnf_2,P_INFO,swLogPrintf("CAM PS , CGTFTRDP request all TFTs , current CID no TFT , check next one "); +609280,1247895551,0,0,PS1,CAM_PS,CamPsCmiPsDeleteTftParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DELETE_TFT_PARM_REQ ' pending "); +609280,1247897599,0,0,PS1,CAM_PS,CamPsCmiPsSetDefineEpsQosCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEFINE_EPS_QOS_REQ ' pending "); +609280,1247899647,0,0,PS1,CAM_PS,CamPsCmiPsDelEpsQosCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEL_DEFINE_EPS_QOS_REQ ' pending "); +609280,1247901695,0,0,PS1,CAM_PS,CamPsGetDefinedEpsQoSCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DEFINED_EPS_QOS_REQ ' pending "); +609280,1247903743,0,0,PS1,CAM_PS,CamPsGetDefinedEpsQoSCnf_2,P_WARNING,swLogPrintf("CAM PS , CGEQOS request all QOSs , current CID no EQOS , check next one "); +609280,1247905791,0,0,PS1,CAM_PS,CamPsGetDynEpsQoSCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_READ_DYN_BEARER_EPS_QOS_REQ ' pending "); +609280,1247907839,0,0,PS1,CAM_PS,CamPsGetDynEpsQoSCnf_2,P_WARNING,swLogPrintf("CAM PS , CGEQOS request all QOSs , current CID no EQOS , check next one "); +609280,1247909887,0,0,PS1,CAM_PS,CamPsGetAllBearersBasicInfoCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_ALL_BEARERS_CIDS_INFO_REQ ' pending "); +609280,1247911935,0,0,PS1,CAM_PS,CamPsCmiPsAttBearCtxPresetCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_ATTACHED_BEARER_CTX_REQ ' pending "); +609280,1247913983,0,0,PS1,CAM_PS,CamPsCmiPsGetAttBearCtxCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_ATTACHED_BEARER_CTX_REQ ' pending "); +609280,1247916031,0,0,PS1,CAM_PS,CamPsCmiPsSetMtCpDataReportCfgCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_MT_CP_DATA_REPORT_CFG_REQ ' pending "); +609280,1247918079,0,0,PS1,CAM_PS,CamPsCmiPsGetMtCpDataReportCfgCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_MT_CP_DATA_REPORT_CFG_REQ ' pending "); +609280,1247920127,0,0,PS1,CAM_PS,CamPsTransCiotPlaneCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_TRANS_CIOT_PLANE_REQ ' pending "); +609280,1247922175,0,0,PS1,CAM_PS,CamPsCmiPsSetDefineAuthCtxCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_DEFINE_AUTH_CTX_REQ ' pending "); +609280,1247924223,0,0,PS1,CAM_PS,CamPsGetDefineAuthCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DEFINED_AUTH_CTX_REQ ' pending "); +609280,1247926271,0,0,PS1,CAM_PS,CamPsCmiPsSetDataOffCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_DATA_OFF_REQ ' pending "); +609280,1247928319,0,0,PS1,CAM_PS,CamPsCmiPsGetDataOffCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DATA_OFF_REQ ' pending "); +609280,1247930367,0,0,PS1,CAM_PS,CamPsCmiSetDataCounterCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_DATA_COUNTER_REQ ' pending "); +609280,1247932415,0,0,PS1,CAM_PS,CamPsCmiGetDataCounterCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_DATA_COUNTER_REQ ' pending "); +609280,1247934463,0,0,PS1,CAM_PS,CamPsCmiGetSaveDataCounterPeriodCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_SAVE_DATA_COUNTER_PERIOD_REQ ' pending "); +609280,1247936511,0,0,PS1,CAM_PS,CamPsCmiGetTrafficIdleMonitorCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_GET_TRAFFIC_IDLE_MONITOR_REQ ' pending "); +609280,1247938559,0,0,PS1,CAM_PS,CamPsCemmCamSetCemodeParamCnf_1,P_WARNING,swLogPrintf("CAM PS , no ' CMI_PS_SET_UE_OPERATION_MODE_REQ ' pending , when process the setting CNF "); +610304,1249906687,0,0,PS1,CAM_SIM,CamSimCmiSimFacilityLockReqFunc_0,P_ERROR,swLogPrintf("Unknown lock mode "); +610304,1249908735,0,0,PS1,CAM_SIM,CamSimCmiSimFacilityLockReqFunc_1,P_WARNING,swLogPrintf("Don ' t support FDN / MEP , so send cnf with error code of CME_OPERATION_NOT_SUPPORT! "); +610304,1249910783,0,0,PS1,CAM_SIM,CamSimCmiSimSetExtCfgReqFunc_1,P_WARNING,swLogPrintf("CAM SIM , no valid CFG set in AT+ECSIMCFG "); +610304,1249912831,0,0,PS1,CAM_SIM,CamSimCmiSimSetExtCfgReqFunc_2,P_WARNING,swLogPrintf("CAM SIM , not allowed set SIM slot or softsim in AT+ECSIMCFG as non-cfun0 state "); +610304,1249914879,0,0,PS1,CAM_SIM,CamSimCmiSimOperPinCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_OPERATE_PIN_REQ ' pending , when process the CCM_SIM_OPERATE_PIN_CNF from CCM SIM. "); +610304,1249916927,0,0,PS1,CAM_SIM,CamSimCmiSimLockFacilityCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_LOCK_FACILITY_REQ ' pending , when process the CCM_SIM_LOCK_FACILITY_CNF from CCM SIM. "); +610304,1249918975,0,0,PS1,CAM_SIM,CamSimCmiSimGenericAccessCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_GENERIC_ACCESS_REQ ' pending , when process the CCM_SIM_GENERIC_ACCESS_CNF from CCM SIM. "); +610304,1249919232,0,0,PS1,CAM_SIM,CacSimCmiSimGenericAccessCnfFunc_2,P_VALUE,swLogPrintf("abnormal len %d data 0x%x "); +610304,1249923071,0,0,PS1,CAM_SIM,CamSimCmiSimRestrictedAccessCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_RESTRICTED_ACCESS_REQ ' pending , when process the CCM_SIM_RESTRICTED_ACCESS_CNF from CCM SIM. "); +610304,1249923328,0,0,PS1,CAM_SIM,CacSimCmiSimRestrictedAccessCnfFunc_2,P_VALUE,swLogPrintf("abnormal len %d data 0x%x "); +610304,1249927167,0,0,PS1,CAM_SIM,CamSimCmiSimOpenLogicalChCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_OPEN_LOGICAL_CHANNEL_REQ ' pending , when process the CMI_SIM_OPEN_LOGICAL_CHANNEL_CNF from CCM SIM. "); +610304,1249929215,0,0,PS1,CAM_SIM,CamSimCmiSimCloseLogicalChCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_CLOSE_LOGICAL_CHANNEL_REQ ' pending , when process the CMI_SIM_CLOSE_LOGICAL_CHANNEL_CNF from CCM SIM. "); +610304,1249931263,0,0,PS1,CAM_SIM,CamSimCmiSimGenLogicalChAccessCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_GENERIC_LOGICAL_CHANNEL_ACCESS_REQ ' pending , when process the CMI_SIM_GENERIC_LOGICAL_CHANNEL_ACCESS_CNF from CCM SIM. "); +610304,1249933311,0,0,PS1,CAM_SIM,CCamSimCmiSimSetSimWriteCntCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_SET_SIM_WRITE_COUNTER_REQ ' pending , when process the CMI_SIM_CLOSE_LOGICAL_CHANNEL_CNF from CCM SIM. "); +610304,1249935359,0,0,PS1,CAM_SIM,CamSimCmiSimSetSimRemovalCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_SET_SIM_REMOVAL_REQ ' pending , when process the CMI_SIM_SET_SIM_REMOVAL_CNF from CCM SIM. "); +610304,1249937407,0,0,PS1,CAM_SIM,CamSimCmiSimGetSmsParamsCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_GET_SMS_PARAMS_REQ ' pending , when process the CMI_SIM_GET_SMS_PARAMS_CNF from CCM SIM. "); +610304,1249939455,0,0,PS1,CAM_SIM,CamSimCmiSimGetSubscriberNumberCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_GET_SUBSCRIBER_NUMBER_REQ ' pending , when process the CMI_SIM_GET_SUBSCRIBER_NUMBER_CNF from CCM SIM. "); +610304,1249941503,0,0,PS1,CAM_SIM,CacSimCmiUsatSetTerminalProfileCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_SET_TERMINAL_PROFILE_REQ ' pending , when process the CMI_SIM_SET_TERMINAL_PROFILE_CNF from CCM SIM. "); +610304,1249943551,0,0,PS1,CAM_SIM,CacSimCmiUsatGetTerminalProfileCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_GET_TERMINAL_PROFILE_REQ ' pending , when process the CMI_SIM_GET_TERMINAL_PROFILE_CNF from CCM SIM. "); +610304,1249945599,0,0,PS1,CAM_SIM,CamSimCmiSimSetPreferredPlmnListCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_SET_PREFERRED_PLMN_LIST_REQ ' pending , when process the CMI_SIM_SET_PREFERRED_PLMN_LIST_CNF from CCM SIM. "); +610304,1249947647,0,0,PS1,CAM_SIM,CamSimCmiSimGetPreferredPlmnListCnfFunc_1,P_WARNING,swLogPrintf("No ' CMI_SIM_GET_PREFERRED_PLMN_LIST_REQ ' pending , when process the CMI_SIM_GET_PREFERRED_PLMN_LIST_CNF from CCM SIM. "); +611328,1252001792,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendMsgReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support pdu length : %d "); +611328,1252003840,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendStoredMsgReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support pdu length : %d "); +611328,1252005888,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendCommandReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support pdu length : %d "); +611328,1252007936,0,0,PS1,CAM_SMS,CamSmsCmiSetSmspReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support SMSC Addr setting parms length : %d "); +611328,1252009984,0,0,PS1,CAM_SMS,CamSmsCmiSetSmsServiceReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support sms service setting : %d "); +611328,1252012032,0,0,PS1,CAM_SMS,CamSmsCmiGetSmsMsgRecordReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support the read commad : %d "); +611328,1252014080,0,0,PS1,CAM_SMS,CamSmsCmiSetSmsMsgRecordReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support the write commad : %d "); +611328,1252018175,0,0,PS1,CAM_SMS,CamSmsCmiSetSmsMsgRecordReqFunc_2,P_WARNING,swLogPrintf("CAM SMS , CcmMsgConvertSmsAddrToBcdNum return FALSE. "); +611328,1252018176,0,0,PS1,CAM_SMS,CamSmsCmiSetSmsMsgRecordReqFunc_3,P_WARNING,swLogPrintf("CAM SMS , input TPDU length : %d is incorrect. "); +611328,1252020480,0,0,PS1,CAM_SMS,CamSmsCmiDelSmsMsgRecordReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , input delFlag is invalid , index : %d , delFlag : %d. "); +611328,1252022272,0,0,PS1,CAM_SMS,CamSmsCmiListSmsMsgRecordReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , input invalid status , request status : %d. "); +611328,1252024320,0,0,PS1,CAM_SMS,CamSmsCmiGetStorageStatusReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , input invalid parameter , operatmode %d. "); +611328,1252028415,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendMessageCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no ' CMI_SMS_SEND_MESSAGE_REQ ' pending , when process the cmgs CNF from CCM SMS "); +611328,1252030463,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendStoredMessageCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no ' CMI_SMS_SEND_STORED_MSG_REQ ' pending , when process the cmgs CNF from CCM SMS "); +611328,1252032511,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendCommandCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no ' CMI_SMS_SEND_COMMAND_REQ ' pending , when process the cmgc CNF from CCM SMS "); +611328,1252034559,0,0,PS1,CAM_SMS,CamSmsGetSmsServiceCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_GET_CURRENT_SMS_SERVICE_REQ pending , when process CMI_SMS_GET_CURRENT_SMS_SERVICE_CNF "); +611328,1252034560,0,0,PS1,CAM_SMS,CamSmsGetSmsServiceCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t get SMS service info : %d "); +611328,1252038655,0,0,PS1,CAM_SMS,CcmSmsSetSmsServiceCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_SELECT_MESSAGE_SERVICE_REQ pending , when process CMI_SMS_SELECT_MESSAGE_SERVICE_CNF "); +611328,1252038656,0,0,PS1,CAM_SMS,CcmSmsSetSmsServiceCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , set SMS service command error : %d "); +611328,1252042751,0,0,PS1,CAM_SMS,CcmSmsSetSmspCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_SET_SMSP_REQ pending , when process CMI_SMS_SET_SMSP_CNF "); +611328,1252044799,0,0,PS1,CAM_SMS,CcmSmsGetSmscAddrCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_GET_SMSC_ADDR_REQ pending , when process CMI_SMS_GET_SMSC_ADDR_CNF "); +611328,1252044800,0,0,PS1,CAM_SMS,CcmSmsGetSmscAddrCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t get smsc address info : %d "); +611328,1252046848,0,0,PS1,CAM_SMS,CamSmsCmiSetMoreMsgModeReqFunc_1,P_WARNING,swLogPrintf("CAM SMS , not support sms more message mode setting : %d "); +611328,1252050943,0,0,PS1,CAM_SMS,CcmSmsSetMoreMessageModeCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_SET_MORE_MESSAGE_MODE_REQ pending , when process CMI_SMS_SET_MORE_MESSAGE_MODE_CNF "); +611328,1252052991,0,0,PS1,CAM_SMS,CamSmsGetMoreMessageModeCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_GET_MORE_MESSAGE_MODE_REQ pending , when process CMI_SMS_GET_MORE_MESSAGE_MODE_CNF "); +611328,1252052992,0,0,PS1,CAM_SMS,CamSmsGetMoreMessageModeCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t get SMS more message mode : %d "); +611328,1252057087,0,0,PS1,CAM_SMS,CamSmsCmiGetSmsMsgRecordCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_GET_SMS_MSG_RECORD_REQ pending , when process CMI_SMS_GET_SMS_MSG_RECORD_CNF "); +611328,1252057088,0,0,PS1,CAM_SMS,CamSmsCmiGetSmsMsgRecordCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t get SMS Record from SIM : error cause %d "); +611328,1252061183,0,0,PS1,CAM_SMS,CamSmsCmiSetSmsMsgRecordCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_SET_SMS_MSG_RECORD_REQ pending , when process CMI_SMS_SET_SMS_MSG_RECORD_CNF "); +611328,1252061184,0,0,PS1,CAM_SMS,CamSmsCmiSetSmsMsgRecordCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t save SMS Record to SIM : error cause %d "); +611328,1252065279,0,0,PS1,CAM_SMS,CamSmsCmiDeltSmsMsgRecordCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_DEL_SMS_MSG_RECORD_REQ pending , when process CMI_SMS_DEL_SMS_MSG_RECORD_CNF "); +611328,1252065280,0,0,PS1,CAM_SMS,CamSmsCmiDelSmsMsgRecordCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t Delete SMS Record to SIM : error cause %d "); +611328,1252069375,0,0,PS1,CAM_SMS,CamSmsCmiListSmsMsgRecordCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_LIST_SMS_MSG_RECORD_REQ pending , when process CMI_SMS_LIST_SMS_MSG_RECORD_CNF "); +611328,1252069376,0,0,PS1,CAM_SMS,CamSmsCmiListSmsMsgRecordCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , get Invalid SMS Record from SIM : error cause %d "); +611328,1252073471,0,0,PS1,CAM_SMS,CamSmsCmiGetStorageStatusCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_GET_SMS_STORAGE_STATUS_REQ pending , when process CMI_SMS_GET_SMS_STORAGE_STATUS_CNF "); +611328,1252073472,0,0,PS1,CAM_SMS,CamSmsCmiGetStorageStatusCnfFunc_2,P_WARNING,swLogPrintf("CAM SMS , can ' t Get SMS Storage status from SIM : error cause %d "); +611328,1252077567,0,0,PS1,CAM_SMS,CamSmsCmiSmsSendSMMACnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no ' CMI_SMS_SEND_SMMA_REQ ' pending , when process the cmgs CNF from CCM SMS "); +611328,1252079615,0,0,PS1,CAM_SMS,CamSmsSetMemCapCnfFunc_1,P_WARNING,swLogPrintf("CAM SMS , no CMI_SMS_SET_MEM_CAP_REQ pending , when process CMI_SMS_SET_MEM_CAP_CNF "); +786432,1610614785,0,0,CUSTOMER,LUATOS,debug,P_INFO,swLogPrintf("%s "); + +Structs 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+ +SigStructs +CAMCMISIGID_enum,CAMCMISIGID +CCM_CFG_SMS_CSCB_SETTING,CcmCscbNvmConfig +cesmpdpauthconfig,CesmNvmPdpAuthConfig +cesmpdpconfig,CesmNvmPdpConfig +CCM_CFG_SMS_MORE_MSG_MODE,CmiSmsMoreMessage +MW_CFG_AT_CHAN_1_CONFIG,MWCfgAtChanConfig +MW_CFG_ALARM_PARAM,MWNvmCfgAlarmParam +MW_CFG_AT_PEND_URC_PARAM,MWNvmCfgAtPendUrcParam +MW_CFG_AT_SOCKET_PARAM,MWNvmCfgAtSocketParam +MW_CFG_SMS_URC_CNMI_PARAM,MWNvmCfgCNMIParam +MW_CFG_SMS_MEM_CPMS_PARAM,MWNvmCfgCPMSParam +MW_CFG_SMS_SCA_CSCA_PARAM,MWNvmCfgCSCAParam +MW_CFG_CSCS_PARAM,MWNvmCfgCSCSParam +MW_CFG_SMS_TEXT_CSMP_PARAM,MWNvmCfgCSMPParam +MW_CFG_CTW_HTTP_PARAM,MWNvmCfgCtwHttpParam +MW_CFG_CTW_MQTT_PARAM,MWNvmCfgCtwMqttParam +MW_CFG_CTW_CFG_PARAM,MWNvmCfgCtwParamCfg +MW_CFG_CTW_TCP_PARAM,MWNvmCfgCtwTcpParam +MW_CFG_DEFAULT_DNS,MWNvmCfgDefaultDns +MW_CFG_DM_CMCC_PARAM,MWNvmCfgDmCmccParam +MW_CFG_DM_CTCC_PARAM,MWNvmCfgDmCtccParam +MW_CFG_DM_CUCC_PARAM,MWNvmCfgDmCuccParam +MW_CFG_NET_PARAM,MWNvmCfgNetParam +MW_CFG_POWER_ON_CFUN,MWNvmCfgPowerOnCfun +MW_CFG_URC_DELAY_PARAM,MWNvmCfgUrcDelayParam +MW_CFG_URC_RI_OTHER_PARAM,MWNvmCfgUrcRIOtherParam +MW_CFG_URC_RI_SMS_INCOMING_PARAM,MWNvmCfgUrcRISmsIncomingParam +mwinfo,MidWareNvmInfo +mwsms,MidWareNvmSms +CCM_CFG_SMS_SERVICE_TYPE,MsgService +CCM_CFG_NW_MODE,NwMode +OSASIGIDTAG,OSASIGID +PSL1SIGIDTAG,PSL1SIGID +PSSIGIDTAG,PSSIGID +CEPLMN_CFG_PLMN_SEARCH_LEVEL,PlmnSearchPowerLevel +CEPLMN_CFG_CELL_LOCK_INFO,PsCfgCellLockInfo +CEMM_CFG_CIOT_SETTING,PsCfgCemmCiotSetting +CEMM_CFG_EDRX_SETTING,PsCfgCemmEdrxSetting +CEMM_CFG_MS_CLASSMARK2,PsCfgCemmMsClassMark2 +CEMM_CFG_PSM_SETTING,PsCfgCemmPsmSetting +CEMM_CFG_UE_NW_CAPA,PsCfgCemmUeNwCapa +CEMM_CFG_USER_MAX_T3324_SETTING,PsCfgCemmUserMaxT3324Setting +CEMM_CFG_VOICE_DOMAIN_UE_USAGE,PsCfgCemmVoiceDomainUeUsage +CESM_CFG_USER_DEFINED_T3482,PsCfgCesmUserDefinedT3482 +CESM_CFG_USER_DEFINED_T3492,PsCfgCesmUserDefinedT3492 +L2_CFG_DATA_COUNTER_INFO,PsCfgL2DataCounterInfo +CEPLMN_CFG_BAND_INFO,PsCfgPlmnBandInfo +CEPLMN_CFG_PLMN_SELECT_TYPE,PsCfgPlmnSelectType +CEPLMN_CFG_USER_DEFINED_HIGH_PRI_PLMN_TIMER,PsCfgUserDefinedHighPriPlmnTimer +CCM_CFG_UE_OPERATION_MODE,PsUeOperationModeEnum +SIMSTKPSPROXYSIGID_Tag,SIMBIPSTKPSPROXYSIGID +CCM_CFG_UE_SERVICE,UeService +cmsSigId_Enum,cmsSigId +plat_config,plat_config_fs_t + +OptionalSegment +optional_sk_01,CDF79F7617C17AE28D6AC5019D7E74EF20C37E00E0C955BF69FAA8E4A4707C9E + diff --git a/PLAT/core/common/include/bsp_common.h b/PLAT/core/common/include/bsp_common.h new file mode 100644 index 0000000..97032cd --- /dev/null +++ b/PLAT/core/common/include/bsp_common.h @@ -0,0 +1,563 @@ +/* + * Copyright (c) 2022 OpenLuat & AirM2M + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __BSP_COMMON_H__ +#define __BSP_COMMON_H__ +#include +#include +#include +#include +#include +#include "cmsis_compiler.h" + +typedef struct +{ + uint32_t MaigcNum; //å‡çº§åŒ…标识,标识ä¸å¯¹ç›´æŽ¥æŠ›å¼ƒ + uint32_t CRC32; //åŽç»­å­—节的CRC32校验,所有CRC32规则与ZIP压缩一致 + uint32_t Param1; //å‡çº§å‚数,其中byte0å‡çº§ç±»åž‹ï¼Œbyte1å‡çº§åŒ…存放ä½ç½®ï¼Œbyte2外设总线åºå·ï¼Œå’Œplatform_define里的外设åºå·ä¸€è‡´ + uint32_t Param2; //é¢å¤–çš„å‚数,需è¦å’Œå¤–置存储总线é…åˆä½¿ç”¨ï¼Œä¸€èˆ¬æ˜¯å¤–置存储总线的PIN + uint32_t DataStartAddress;//å‡çº§åŒ…在flash中的起始地å€ï¼Œå¤–部和内部都å¯ä»¥ç”¨ + uint32_t DataLen;//å‡çº§åŒ…å¤§å° + uint32_t DataCRC32;//å‡çº§åŒ…整包数æ®çš„CRC32 + char FilePath[100];//å‡çº§åŒ…在文件系统中的ç»å¯¹è·¯å¾„,如果在flash中则éšæ„填写 +}CoreUpgrade_HeadStruct; + +typedef struct +{ + uint32_t MaigcNum; //å‡çº§åŒ…标识,标识ä¸å¯¹ç›´æŽ¥æŠ›å¼ƒ + uint32_t CRC32; //åŽç»­å­—节的CRC32校验 + uint32_t MainVersion;//目标的底层版本,å‡çº§æˆåŠŸçš„è¯å°±æ˜¯è¿™ä¸ªç‰ˆæœ¬å·äº† + uint32_t AppVersion;//æ•´åŒ…çš„ç‰ˆæœ¬å· + uint32_t STDVersion;//å…许å‡çº§çš„åº•å±‚ç‰ˆæœ¬å· + uint32_t DataLen;//å‡çº§åŒ…å¤§å° + uint32_t DataCRC32;//å‡çº§åŒ…整包数æ®çš„CRC32,这里验è¯ä¼ è¾“的准确性 +}CoreUpgrade_FileHeadStruct; + +typedef struct +{ + uint32_t MaigcNum; //å‡çº§åŒ…标识,标识ä¸å¯¹ç›´æŽ¥æŠ›å¼ƒ + uint32_t TotalLen; //解压å‰å æ®çš„空间 + uint32_t DataLen; //解压åŽå æ®çš„空间,如果和TotalLen一样,则表示未å¯ç”¨åŽ‹ç¼©ï¼Œä¸éœ€è¦è§£åŽ‹ï¼Œä¹Ÿæ²¡æœ‰åŽ‹ç¼©å‚æ•° + //如果是0,则表示是差分å‡çº§ + //其他表示是整包å‡çº§ï¼Œæ•°æ®åŒ…ç»è¿‡äº†lzma压缩 + uint32_t DataCRC32; //解压åŽçš„æ•°æ®çš„CRC32,这里验è¯çƒ§å½•çš„正确性 + uint32_t StartAddress; //çƒ§å†™çš„èµ·å§‹åœ°å€ +}CoreUpgrade_SectorStruct; + +typedef struct +{ + uint32_t param_max_num; + uint32_t param_max_len; + uint32_t param_num; + int8_t *param_str; +}CmdParam; + +typedef struct +{ + uint8_t Sec; + uint8_t Min; + uint8_t Hour; + uint8_t Week;//表示日期0~6,sun~sat,表示预约时,bit0~bit6,sun~sat +}Time_UserDataStruct; + +typedef struct +{ + uint16_t Year; + uint8_t Mon; + uint8_t Day; +}Date_UserDataStruct; + +typedef union +{ + uint32_t dwTime; + Time_UserDataStruct Time; +}Time_Union; + +typedef union +{ + uint32_t dwDate; + Date_UserDataStruct Date; +}Date_Union; + +typedef struct +{ + uint8_t *Data; + uint32_t Len; + uint32_t Offset; + uint32_t MaxLength; + uint32_t DataSize; +}Loop_Buffer; + +typedef struct +{ + uint8_t *Data; + uint32_t Pos; + uint32_t MaxLen; +}Buffer_Struct; + + +typedef struct +{ + uint8_t *pCache[2]; + uint32_t pCacheLen[2]; + uint32_t MaxLen; + uint8_t CurCacheSn; +}DBuffer_Struct; + +typedef union +{ + void *p; + char *pc8; + uint8_t *pu8; + uint16_t *pu16; + uint32_t *pu32; + uint32_t u32; + uint8_t u8[4]; + uint16_t u16[2]; +}PV_Union; + +enum +{ + ERROR_NONE, + ERROR_NO_SUCH_ID, + ERROR_PERMISSION_DENIED, + ERROR_PARAM_INVALID, + ERROR_PARAM_OVERFLOW, + ERROR_DEVICE_BUSY, + ERROR_OPERATION_FAILED, + ERROR_BUFFER_FULL, + ERROR_NO_MEMORY, + ERROR_CMD_NOT_SUPPORT, + ERROR_NO_DATA, + ERROR_NO_FLASH, + ERROR_NO_TIMER, + ERROR_TIMEOUT, + ERROR_SSL_HANDSHAKE, + ERROR_PROTOCL, + ERROR_ID_INVALID, + ERROR_MID_INVALID, + ERROR_RETRY_TOO_MUCH, + ERROR_CMD_BLOCK, + LIST_FIND = 1, + LIST_PASS = 0, + LIST_DEL = -1, + + DMA_CB_DONE = 0, + UART_CB_TX_BUFFER_DONE, + UART_CB_TX_ALL_DONE, + UART_CB_RX_NEW, + UART_CB_RX_TIMEOUT, + UART_CB_RX_BUFFER_FULL, + UART_CB_ERROR, + UART_CB_CONNECTED, //串å£å·¥å…·å¯¹æ–¹å·²ç»æ‰“å¼€ + DMA_CB_ERROR = 0xffffffff, + + + CORE_EVENT_ID_ANY = 0, + CORE_EVENT_ID_START = 0xf0000000, + CORE_EVENT_TIMEOUT, + CORE_TIMER_TIMEOUT = 0xf0010000, + SERVICE_EVENT_ID_START = 0xf0100000, + DEV_EVENT_ID_START = 0xf0200000, + DEV_SPIFLASH_SPI_DONE, + DEV_SDHC_SPI_DONE, + USB_APP_EVENT_ID_START = 0xf0300000, + USER_EVENT_ID_START = 0xf1000000, + INVALID_EVENT_ID = 0xffffffff, + + NW_EVENT_SENT = 0, + NW_EVENT_RECV, + NW_EVENT_ERR, + NW_EVENT_CONNECTED, + NW_EVENT_REMOTE_CLOSE, + NW_EVENT_ACCEPT, + NW_EVENT_CLOSE_OK, + + + +}; + +#define INVALID_HANDLE_VALUE ((void *)0xffffffff) +#define INVALID_PARAM (0xffffffff) +#define CRC32_GEN (0x04C11DB7) +#define CRC32_START (0xffffffff) +#define CRC16_CCITT_GEN (0x1021) +#define CRC16_MODBUS_GEN (0x8005) +#define CRC16_START (0xffff) +#define CRC16_IBM_SEED (0xffff) +#define CRC16_CCITT_SEED (0x1D0F) +#define HANDLE void * +#ifndef BIT +#define BIT(n) (1UL << (n)) +#endif +#ifndef MIN +#define MIN(X,Y) (((X) < (Y))?(X):(Y)) +#endif +typedef void (*IrqHandler)(int32_t IrqLine, void *pData); +typedef void (* TaskFun_t)( void * ); +typedef void (* CommonFun_t)(void); +typedef void(* CBDataFun_t)(uint8_t *Data, uint32_t Len); +typedef int32_t(*CBFuncEx_t)(void *pData, void *pParam); +typedef uint64_t LongInt; + + + +#define INIT_FUN_EXPORT(fn, location, level) const CommonFun_t __ex_init_##fn __attribute__((section(location level))) = fn +#define INIT_HW_EXPORT(fn, level) INIT_FUN_EXPORT(fn, ".preinit_fun_array.", level) +#define INIT_DRV_EXPORT(fn, level) INIT_FUN_EXPORT(fn, ".init_fun_array.", level) +#define INIT_TASK_EXPORT(fn, level) INIT_FUN_EXPORT(fn, ".task_fun_array.", level) + +/* board init routines will be called in board_init() function */ +#define INIT_BOARD_EXPORT(fn) INIT_EXPORT(fn, "1") + +/* pre/device/component/env/app init routines will be called in init_thread */ +/* components pre-initialization (pure software initilization) */ +#define INIT_PREV_EXPORT(fn) INIT_EXPORT(fn, "2") +/* device initialization */ +#define INIT_DEVICE_EXPORT(fn) INIT_EXPORT(fn, "3") +/* components initialization (dfs, lwip, ...) */ +#define INIT_COMPONENT_EXPORT(fn) INIT_EXPORT(fn, "4") +/* environment initialization (mount disk, ...) */ +#define INIT_ENV_EXPORT(fn) INIT_EXPORT(fn, "5") +/* appliation initialization (rtgui application etc ...) */ +#define INIT_APP_EXPORT(fn) INIT_EXPORT(fn, "6") + +typedef struct +{ + uint32_t ID; + uint32_t Param1; + uint32_t Param2; + uint32_t Param3; +}OS_EVENT; + +typedef struct +{ + CBFuncEx_t CB; + union { + void *pParam; //ç”¨æˆ·å›žè°ƒæ¨¡å¼ + uint32_t MaxCnt; //设置æ•èŽ·æ¨¡å¼æ—¶çš„最大tick,æ•èŽ·æ—¶çš„tick + }uParam; + + union { + struct { + uint8_t Level; //IO输入输出电平,æ•èŽ·æ¨¡å¼ä¸‹ä¸­æ–­æ—¶IO电平 + uint8_t PullMode; //IO上下拉控制 + } IOArg; + struct { + uint8_t ExtiMode; //ä¸­æ–­æ¨¡å¼ + uint8_t PullMode; //IO上下拉控制 + } ExitArg; + uint16_t Time; //delay时间,us + } uArg; + uint8_t Operation; //æ“作类型 + uint8_t PinOrDelay; //IOæ“作时为IOpin,delayæ“作时则为微调值,0~47,48为1us +}OPQueue_CmdStruct; + +enum +{ + UDATA_TYPE_UNDEFINED = 0, + UDATA_MULTIPLE_RESOURCE, + UDATA_TYPE_STRING, + UDATA_TYPE_OPAQUE, + UDATA_TYPE_INTEGER, + UDATA_TYPE_DWORD, + UDATA_TYPE_WORD, + UDATA_TYPE_BYTE, + UDATA_TYPE_FLOAT, + UDATA_TYPE_BOOLEAN, + UDATA_TYPE_UNSIGNED, + UDATA_TYPE_UNUSD +}; + +typedef struct _u_data_t uData_t; + +struct _u_data_t +{ + union + { + uint8_t asBoolean; + uint64_t asUnsigned; + int64_t asInteger; + PV_Union asDword; + double asFloat; + struct + { + size_t length; + uint8_t *buffer; + } asBuffer; + struct + { + size_t count; + uData_t *array; + } asChildren; + } value; + uint32_t ID; + uint8_t Type; +}; + +__attribute__((weak)) uint8_t OS_CheckInIrq(void); +#define __BUILD_OS__ +#ifdef __BUILD_OS__ +HANDLE OS_MutexCreate(void); +HANDLE OS_MutexCreateUnlock(void); +void OS_MutexLock(HANDLE Sem); +int32_t OS_MutexLockWtihTime(HANDLE Sem, uint32_t TimeoutMs); +void OS_MutexRelease(HANDLE Sem); +void OS_MutexDelete(HANDLE Sem); +void OS_SuspendTask(HANDLE taskHandle); +void OS_ResumeTask(HANDLE taskHandle); +uint8_t OS_IsSchedulerRun(void); +#endif +uint32_t OS_EnterCritical(void); +void OS_ExitCritical(uint32_t Critical); +void OS_MemInfo(uint32_t *curalloc, uint32_t *totfree, uint32_t *maxfree); +int32_t OS_InitBuffer(Buffer_Struct *Buf, uint32_t Size); +void OS_DeInitBuffer(Buffer_Struct *Buf); +int32_t OS_ReInitBuffer(Buffer_Struct *Buf, uint32_t Size); +int32_t OS_ReSizeBuffer(Buffer_Struct *Buf, uint32_t Size); +int32_t OS_BufferWrite(Buffer_Struct *Buf, void *Data, uint32_t Len); +int32_t OS_BufferWriteLimit(Buffer_Struct *Buf, void *Data, uint32_t Len); +void OS_BufferRemove(Buffer_Struct *Buf, uint32_t Len); +void DBuffer_Init(DBuffer_Struct *DBuf, uint32_t Size); +void DBuffer_ReInit(DBuffer_Struct *DBuf, uint32_t Size); +void DBuffer_DeInit(DBuffer_Struct *DBuf); +void *DBuffer_GetCache(DBuffer_Struct *DBuf, uint8_t IsCurrent); +void DBuffer_SwapCache(DBuffer_Struct *DBuf); +void DBuffer_SetDataLen(DBuffer_Struct *DBuf, uint32_t Len, uint8_t IsCurrent); +uint32_t DBuffer_GetDataLen(DBuffer_Struct *DBuf, uint8_t IsCurrent); + + +void Buffer_StaticInit(Buffer_Struct *Buf, void *Src, uint32_t MaxLen); +int32_t Buffer_StaticWrite(Buffer_Struct *Buf, void *Data, uint32_t Len); +void Buffer_Remove(Buffer_Struct *Buf, uint32_t Len); +void LoopBuffer_Init(Loop_Buffer *Buf, void *Src, uint32_t MaxLen, uint32_t DataSize); +uint32_t LoopBuffer_Query(Loop_Buffer *Buf, void *Src, uint32_t Len); +uint32_t LoopBuffer_Read(Loop_Buffer *Buf, void *Src, uint32_t Len); +void LoopBuffer_Del(Loop_Buffer *Buf, uint32_t Len); +uint32_t LoopBuffer_Write(Loop_Buffer *Buf, void *Src, uint32_t Len); +int32_t BSP_SetBit(uint8_t *Data, uint32_t Sn, uint8_t Value); +int32_t BSP_GetBit(uint8_t *Data, uint32_t Sn, uint8_t *Value); +uint8_t BSP_TestBit(uint8_t *Data, uint32_t Sn); +uint8_t XorCheck(void *Src, uint32_t Len, uint8_t CheckStart); +uint8_t SumCheck(uint8_t *Data, uint32_t Len); +uint16_t CRC16Cal(void *Data, uint16_t Len, uint16_t CRC16Last, uint16_t CRCRoot, uint8_t IsReverse); +uint32_t AsciiToU32(uint8_t *Src, uint32_t Len); +void CRC32_CreateTable(uint32_t *Tab, uint32_t Gen); +uint32_t CRC32_Cal(uint32_t * CRC32_Table, uint8_t *Buf, uint32_t Size, uint32_t CRC32Last); +uint32_t CmdParseParam(int8_t* pStr, CmdParam *CmdParam, int8_t Cut); +uint8_t IsLeapYear(uint32_t Year); +LongInt UTC2Tamp(Date_UserDataStruct *Date, Time_UserDataStruct *Time); +uint32_t Tamp2UTC(LongInt Sec, Date_UserDataStruct *Date, Time_UserDataStruct *Time, uint32_t LastDDay); + +uint32_t TransferPack(uint8_t Flag, uint8_t Code, uint8_t F1, uint8_t F2, uint8_t *InBuf, uint32_t Len, uint8_t *OutBuf); +/* + * 转义解包 + * 标识Flag,å³åŒ…头包尾加入Flag + * æ•°æ®ä¸­é‡åˆ°Code F1 -> Flag + * æ•°æ®ä¸­é‡åˆ°Code F2 -> Code + * æ•°æ®ä¸­é‡åˆ°Flag 出错返回0 + */ + +uint32_t TransferUnpack(uint8_t Flag, uint8_t Code, uint8_t F1, uint8_t F2, uint8_t *InBuf, uint32_t Len, uint8_t *OutBuf); +/* + * llist相关代ç ï¼Œå¤§éƒ¨åˆ†æ¥è‡ªlinux内核 + */ +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + + +/* + * These are non-NULL pointers that will result in page faults + * under normal circumstances, used to verify that nobody uses + * non-initialized llist entries. + */ +#define LLIST_POISON1 (0) +#define LLIST_POISON2 (0) + +/* + * Simple doubly linked llist implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole llists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +typedef struct llist_head_t{ + struct llist_head_t *next, *prev; +}llist_head; + +#define LLIST_HEAD_INIT(name) { &(name), &(name) } + +#define LLIST_HEAD(name) \ + llist_head name = LLIST_HEAD_INIT(name) + +#define INIT_LLIST_HEAD(ptr) do { \ + (ptr)->next = (ptr); (ptr)->prev = (ptr); \ +} while (0) + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal llist manipulation where we know + * the prev/next entries already! + */ +void __llist_add(llist_head *p, + llist_head *prev, + llist_head *next); + +/** + * llist_add - add a new entry + * @new: new entry to be added + * @head: llist head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +void llist_add(llist_head *p, llist_head *head); + +/** + * llist_add_tail - add a new entry + * @new: new entry to be added + * @head: llist head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +void llist_add_tail(llist_head *p, llist_head *head); + + +/* + * Delete a llist entry by making the prev/next entries + * point to each other. + * + * This is only for internal llist manipulation where we know + * the prev/next entries already! + */ +void __llist_del(llist_head * prev, llist_head * next); + +/** + * llist_del - deletes entry from llist. + * @entry: the element to delete from the llist. + * Note: llist_empty on entry does not return true after this, the entry is + * in an undefined state. + */ +void llist_del(llist_head *entry); + +/** + * llist_del_init - deletes entry from llist and reinitialize it. + * @entry: the element to delete from the llist. + */ +void llist_del_init(llist_head *entry); + +/** + * llist_move - delete from one llist and add as another's head + * @llist: the entry to move + * @head: the head that will precede our entry + */ +void llist_move(llist_head *llist, llist_head *head); + +/** + * llist_move_tail - delete from one llist and add as another's tail + * @llist: the entry to move + * @head: the head that will follow our entry + */ +void llist_move_tail(llist_head *llist, + llist_head *head); + +/** + * llist_empty - tests whether a llist is empty + * @head: the llist to test. + */ +int llist_empty(const llist_head *head); + +uint32_t llist_num(const llist_head *head); + +void *llist_traversal(llist_head *head, CBFuncEx_t cb, void *pData); +/** + * llist_entry - get the struct for this entry + * @ptr: the &llist_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the llist_struct within the struct. + */ +#define llist_entry(ptr, type, member) \ + container_of(ptr, type, member) + + +uint16_t BSP_Swap16(uint16_t n); +uint32_t BSP_Swap32(uint32_t n); + +uint8_t BytesGet8(const void *ptr); +void BytesPut8(void *ptr, uint8_t v); +uint16_t BytesGetBe16(const void *ptr); +void BytesPutBe16(void *ptr, uint16_t v); +uint32_t BytesGetBe32(const void *ptr); +void BytesPutBe32(void *ptr, uint32_t v); +uint16_t BytesGetLe16(const void *ptr); +void BytesPutLe16(void *ptr, uint16_t v); +uint32_t BytesGetLe32(const void *ptr); +void BytesPutLe32(void *ptr, uint32_t v); +uint64_t BytesGetLe64(const void *ptr); +void BytesPutLe64(void *ptr, uint64_t v); +uint8_t BytesGet8FromBuf(Buffer_Struct *Buf); +void BytesPut8ToBuf(Buffer_Struct *Buf, uint8_t v); +uint16_t BytesGetBe16FromBuf(Buffer_Struct *Buf); +void BytesPutBe16ToBuf(Buffer_Struct *Buf, uint16_t v); +uint32_t BytesGetBe32FromBuf(Buffer_Struct *Buf); +void BytesPutBe32ToBuf(Buffer_Struct *Buf, uint32_t v); +uint16_t BytesGetLe16FromBuf(Buffer_Struct *Buf); +void BytesPutLe16ToBuf(Buffer_Struct *Buf, uint16_t v); +uint32_t BytesGetLe32FromBuf(Buffer_Struct *Buf); +void BytesPutLe32ToBuf(Buffer_Struct *Buf, uint32_t v); +uint64_t BytesGetLe64FromBuf(Buffer_Struct *Buf); +void BytesPutLe64ToBuf(Buffer_Struct *Buf, uint64_t v); +float BytesGetFloatFromBuf(Buffer_Struct *Buf); +void BytesPutFloatToBuf(Buffer_Struct *Buf, float v); +double BytesGetDoubleFromBuf(Buffer_Struct *Buf); +void BytesPutDoubleToBuf(Buffer_Struct *Buf, double v); +/*************************************************************************/ + +extern uint64_t GetSysTickMS(); + +//void *__wrap_malloc(size_t Size); +//void *__wrap_zalloc(size_t Size); +//void *__wrap_calloc(size_t count, size_t eltsize); +//void *__wrap_realloc(void *buf, size_t size); +//void __wrap_free(void *p); + +#ifndef ASSERT +#if defined(__DEBUG__) +#define ASSERT( x ) if( ( x ) == 0 ) { __disable_irq(); DBG_Trace("\r\nassert %s,%d", __FUNCTION__, __LINE__); for( ;; ); } +#else +#define ASSERT( x ) +#endif +#endif +#endif diff --git a/PLAT/core/common/include/bsp_custom.h b/PLAT/core/common/include/bsp_custom.h new file mode 100644 index 0000000..52f5f01 --- /dev/null +++ b/PLAT/core/common/include/bsp_custom.h @@ -0,0 +1,20 @@ +#ifndef BSP_CUSTOM_H +#define BSP_CUSTOM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp.h" + +void BSP_CustomInit(void); +uint32_t BSP_UsbGetVBUSMode(void); +uint32_t BSP_UsbGetVBUSWkupPad(void); +void Usim1GpioConfig(BOOL bSetUsimFunc); + + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_CUSTOM_H */ diff --git a/PLAT/core/common/include/common_api.h b/PLAT/core/common/include/common_api.h new file mode 100644 index 0000000..984059c --- /dev/null +++ b/PLAT/core/common/include/common_api.h @@ -0,0 +1,150 @@ +#ifndef __COMMON_API_H__ +#define __COMMON_API_H__ +#include "stdint.h" +#include "stdarg.h" +#include "string.h" +#include "stdio.h" +#include "stdbool.h" +#include "bsp_common.h" +#include "platform_define.h" + +#ifdef LOW_SPEED_SERVICE_ONLY +#define PS_DIAL_PS_UP_MEM_SIZE 248000 +#else //Full speed version +#define PS_DIAL_PS_UP_MEM_SIZE 421000 +#endif + +enum +{ + I2S_MODE_I2S, + I2S_MODE_LSB, + I2S_MODE_MSB, + I2S_FRAME_SIZE_16_16, + I2S_FRAME_SIZE_16_32, + I2S_FRAME_SIZE_24_32, + I2S_FRAME_SIZE_32_32, +}; + +typedef void (* usb_serial_in)(uint8_t channel, uint8_t *input, uint32_t len); +typedef void (*pad_wakeup_fun_t)(uint32_t pad_num); +/** + * @brief æ ¼å¼åŒ–打å°è¾“出log,在EPAT工具里是customer luatos + * @param fmt 打å°æ ¼å¼ + * @param ... å‚æ•° + */ +void soc_printf(const char *fmt, ...); + +/** + * @brief 直接输出string,在EPAT工具里是customer luatos + * + * @param string 需è¦è¾“出的字符串 + * @param size 字符串长度,å¯ä»¥é€‰ä¸º0 + */ +void soc_debug_out(char *string, uint32_t size); + +/** + * @brief 设置USB串å£è¾“入的回调函数 + * + * @param cb_fun 回调函数 + */ +void soc_set_usb_serial_input_callback(usb_serial_in cb_fun); +#define set_usb_serial_input_callback(x) soc_set_usb_serial_input_callback(x) + +/** + * @brief USB串å£è¾“出 + * + * @param channel USB串å£é€šé“,目å‰é»˜è®¤æ˜¯4,或者与输入时的channelä¿æŒä¸€è‡´ * @param output è¾“å‡ºçš„æ•°æ® + * @param len 输出的数æ®é•¿åº¦ + * @return int 0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int soc_usb_serial_output(uint8_t channel, uint8_t *output, uint32_t len); +#define usb_serial_output(x,y,z) soc_usb_serial_output(x,y,z) +/** + * @brief 设置低功耗模å¼ä¸‹,wakeuppad唤醒中断回调,注æ„这是在中断回调 + * + * @param cb_fun + */ +void soc_set_pad_wakeup_callback(pad_wakeup_fun_t cb_fun); +#define set_pad_wakeup_callback(x) soc_set_pad_wakeup_callback(x) +/** + * @brief 创建一个带event收å‘机制的task,event就是一个16byteçš„queue,在创建task的时候,åŒæ—¶åˆ›å»ºå¥½äº†ä¸€ä¸ªqueue,event结构è§OS_EVENT + * + * @param task_fun taskçš„å…¥å£å‡½æ•° + * @param param taskçš„å…¥å£å‚æ•° + * @param stack_bytes task的堆栈长度,å•ä½byte,会强制4å­—èŠ‚å¯¹é½ + * @param priority task的任务优先级,注æ„是百分比,0~100,100为底层OSå…许的最高级,0为底层OSå…许的最低级 + * @param task_name taskçš„name + * @param event_max_cnt,如果OSä¸å¸¦mailbox,就需è¦æœ¬å‚æ•°æ¥åˆ›å»ºqueue + * @return void* taskçš„å¥æŸ„,åŽç»­æ”¶å‘event都需è¦è¿™ä¸ªå‚数,NULL为创建失败 + */ +void *create_event_task(TaskFun_t task_fun, void *param, uint32_t stack_bytes, uint8_t priority, uint16_t event_max_cnt, const char *task_name); + +/** + * @brief 删除掉一个带event收å‘机制的task,比正常删除task多了一步删除event queue。 + * + * @param task_handle taskçš„å¥æŸ„ + */ +void delete_event_task(void *task_handle); + +/** + * @brief å‘é€ä¸€ä¸ªeventç»™task + * + * @param task_handle taskçš„å¥æŸ„ + * @param event 一个已ç»æž„建好的event,如果传入指针ä¸ä¸ºNULL,将忽略åŽç»­4个å‚数,å之,会由åŽç»­4个å‚数构建一个event,æ¯ä¸ªå‡½æ•°å‚数对应event内åŒåå‚æ•° + * @param event_id 需è¦æž„建的event id + * @param param1 需è¦æž„建的param1 + * @param param2 需è¦æž„建的param2 + * @param param3 需è¦æž„建的param3 + * @param timeout_ms å‘é€çš„超时时间,0ä¸ç­‰å¾…,0xffffffff永远等待,建议就直接写0 + * @return int æˆåŠŸè¿”回0,其他都是失败 + */ +int send_event_to_task(void *task_handle, OS_EVENT *event, uint32_t event_id, uint32_t param1, uint32_t param2, uint32_t param3, uint32_t timeout_ms); + +/** + * @brief 获å–一个event,并根æ®éœ€è¦è¿”回 + * 如果target_event_id != 0 && != 0xffffffff,那么收到对应event id时返回,如果ä¸æ˜¯ï¼Œåˆ™ç”±callback交给用户临时处ç†ï¼Œå¦‚æžœcallback为空,则抛弃掉 + * 如果target_event_id == 0,收到消æ¯å°±è¿”回 + * 如果target_event_id == 0xffffffff,收到消æ¯åˆ™ç”±callback交给用户临时处ç†ï¼Œå¦‚æžœcallback为空,则抛弃掉 + * + * @param task_handle taskçš„å¥æŸ„ + * @param target_event_id 指定收到的event id + * @param event 缓存event的空间,当收到需è¦çš„event时,缓存在这里 + * @param callback 在收到ä¸éœ€è¦çš„event时,回调给用户处ç†ï¼Œå›žè°ƒå‡½æ•°ä¸­çš„第一个å‚数就是event指针,第二个å‚数是taskå¥æŸ„。这里å¯ä»¥ä¸ºNULL,直接抛弃event + * @param timeout_ms 0å’Œ0xffffffff永远等待,建议就直接写0 + * @return int 收到需è¦çš„event返回0 + */ +int get_event_from_task(void *task_handle, uint32_t target_event_id, OS_EVENT *event, CBFuncEx_t callback, uint32_t timeout_ms); + +/** + * @brief 获å–开机到现在的ms时间 + * + * @return uint64_t + */ +uint64_t soc_get_poweron_time_ms(void); + +uint64_t soc_get_poweron_time_tick(void); +/** + * @brief 获å–å †ä¿¡æ¯ + * + * @param total æ€»é‡ + * @param total_free å‰©ä½™é‡ + * @param min_free 历å²æœ€å°è¿è¡Œé‡ï¼ŒåŒæ—¶ä¹Ÿå¯¹åº”历å²æœ€å¤§ä½¿ç”¨é‡ + */ +void soc_get_heap_info(uint32_t *total, uint32_t *total_free, uint32_t *min_free); +/** + * @brief 请求改å˜å…¨å±€ä½ŽåŠŸè€—çŠ¶æ€ + * + * @param state 0全速 1IDLE 2SLEEP + */ +void soc_require_lowpower_state(uint8_t state); + +uint32_t soc_get_utc(void); +uint64_t soc_get_utc_ms(void); +int soc_get_sn(char *sn, uint8_t buf_size); +/** + * @brief 带函数å称和ä½ç½®çš„æ ¼å¼åŒ–æ‰“å° + * + */ +#define DBG(X,Y...) soc_printf("%s %d:"X, __FUNCTION__,__LINE__,##Y) + +#endif diff --git a/PLAT/core/common/include/platform_define.h b/PLAT/core/common/include/platform_define.h new file mode 100644 index 0000000..f8deaad --- /dev/null +++ b/PLAT/core/common/include/platform_define.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2022 OpenLuat & AirM2M + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __PLATFORM_DEFINE_H__ +#define __PLATFORM_DEFINE_H__ +enum +{ + UART_DATA_BIT5 = 5, + UART_DATA_BIT6 = 6, + UART_DATA_BIT7 = 7, + UART_DATA_BIT8 = 8, + UART_DATA_BIT9 = 9, + UART_PARITY_NONE = 0, + UART_PARITY_ODD, + UART_PARITY_EVEN, + UART_STOP_BIT1 = 0, + UART_STOP_BIT1_5, + UART_STOP_BIT2, + + I2C_OP_READ_REG = 0, //i2c通用读寄存器,一写一读,自动带startä¿¡å· + I2C_OP_READ, //i2c通用读,åªè¯» + I2C_OP_WRITE, //i2c通用写,åªå†™ + + OP_QUEUE_CMD_END = 0, + OP_QUEUE_CMD_ONE_TIME_DELAY, //åªæœ‰ä¸€æ¬¡delay + OP_QUEUE_CMD_CONTINUE_DELAY, //è¿žç»­delay,é…åˆOP_QUEUE_CMD_REPEAT_DELAY使用 + OP_QUEUE_CMD_REPEAT_DELAY, //é‡å¤OP_QUEUE_CMD_CONTINUE_DELAY + OP_QUEUE_CMD_SET_GPIO_DIR_OUT, + OP_QUEUE_CMD_SET_GPIO_DIR_IN, + OP_QUEUE_CMD_GPIO_OUT, + OP_QUEUE_CMD_GPIO_IN, + OP_QUEUE_CMD_GPIO_IN_CB, + OP_QUEUE_CMD_CB, + OP_QUEUE_CMD_CAPTURE_SET, + OP_QUEUE_CMD_CAPTURE, + OP_QUEUE_CMD_CAPTURE_CB, + OP_QUEUE_CMD_CAPTURE_END, + OP_QUEUE_CMD_IO_PULL_NONE = 0, + OP_QUEUE_CMD_IO_PULL_UP, + OP_QUEUE_CMD_IO_PULL_DOWN, + + OP_QUEUE_CMD_IO_EXTI_UP = 0, //上å‡æ²¿ä¸­æ–­ + OP_QUEUE_CMD_IO_EXTI_DOWN, //下é™æ²¿ä¸­æ–­ + OP_QUEUE_CMD_IO_EXTI_BOTH, //åŒè¾¹æ²¿ä¸­æ–­ + + COLOR_MODE_RGB_565 = 0, + COLOR_MODE_GRAY, + COLOR_MODE_RGB_888, + COLOR_MODE_YCBCR_422_UYVY, + COLOR_MODE_YCBCR_422_YUYV, + COLOR_MODE_YCBCR_422_CBYCRY, + + CORE_OTA_MODE_FULL = 0, //param1çš„byte0 + CORE_OTA_MODE_DIFF, + CORE_OTA_IN_FLASH = 0, //param1çš„byte1 + CORE_OTA_OUT_SPI_FLASH, + CORE_OTA_IN_FILE, + +}; + + +enum +{ + + I2C_ID0 = 0, + I2C_ID1, + I2C_MAX, + UART_ID0 = 0, + UART_ID1, + UART_ID2, +// UART_ID4, +// UART_ID5, + UART_MAX, + VIRTUAL_UART0 = 0, + VIRTUAL_UART_MAX, + SPI_ID0, + SPI_ID1, + SPI_MAX, + + SPI_MODE_0 = 0, + SPI_MODE_1, + SPI_MODE_2, + SPI_MODE_3, +// +// HW_TIMER0 = 0, +// HW_TIMER1, +// HW_TIMER2, +// HW_TIMER3, +// HW_TIMER4, +// HW_TIMER5, +// HW_TIMER_MAX, +// +// ADC_CHANNEL_0 = 0, +// ADC_CHANNEL_1, +// ADC_CHANNEL_2, +// ADC_CHANNEL_3, +// ADC_CHANNEL_4, +// ADC_CHANNEL_5, +// ADC_CHANNEL_6, +// ADC_CHANNEL_MAX, + + + HAL_GPIO_0 = 0, + HAL_GPIO_1, + HAL_GPIO_2, + HAL_GPIO_3, + HAL_GPIO_4, + HAL_GPIO_5, + HAL_GPIO_6, + HAL_GPIO_7, + HAL_GPIO_8, + HAL_GPIO_9, + HAL_GPIO_10, + HAL_GPIO_11, + HAL_GPIO_12, + HAL_GPIO_13, + HAL_GPIO_14, + HAL_GPIO_15, + HAL_GPIO_16, + HAL_GPIO_17, + HAL_GPIO_18, + HAL_GPIO_19, + HAL_GPIO_20, + HAL_GPIO_21, + HAL_GPIO_22, + HAL_GPIO_23, + HAL_GPIO_24, + HAL_GPIO_25, + HAL_GPIO_26, + HAL_GPIO_27, + HAL_GPIO_28, + HAL_GPIO_29, + HAL_GPIO_30, + HAL_GPIO_31, + HAL_GPIO_MAX, + HAL_GPIO_NONE = HAL_GPIO_MAX, //大于等于HAL_GPIO_NONE,说明ä¸å­˜åœ¨ +}; + +#define SOC_TICK_1US (26ul) +#define SOC_TICK_1MS (26000ul) +#define SOC_TICK_1S (26000000ul) +#define SOC_TICK_TIMER (3) +#endif diff --git a/PLAT/core/driver/include/driver_gpio.h b/PLAT/core/driver/include/driver_gpio.h new file mode 100644 index 0000000..9feab02 --- /dev/null +++ b/PLAT/core/driver/include/driver_gpio.h @@ -0,0 +1,175 @@ +/** + * @file driver_gpio.h + * @brief 使用本模å—API时,ä¸å¯ä»¥ä½¿ç”¨åŽŸåŽ‚çš„GPIO API,ä¸èƒ½ç”¨wakeupPAD相关API,但是能使用PAD 普通API。所有API都是任务ä¸å®‰å…¨çš„和中断ä¸å®‰å…¨çš„ï¼ï¼ï¼ + * @version 0.1 + * @date 2022-10-25 + * + * @copyright + * + */ + +#ifndef __CORE_GPIO_H__ +#define __CORE_GPIO_H__ +#include "bsp_common.h" +/** + * @brief GPIO全局åˆå§‹åŒ– + * + * @param Fun 中断回调函数,回调时,PINåºå·æ˜¯pData,void *->uint32_t。这里是给全部的GPIO统一设置,å¯ä»¥ç•™ç©ºï¼Œç„¶åŽç»™æ¯ä¸ªGPIOå•ç‹¬é…ç½® + + */ +void GPIO_GlobalInit(CBFuncEx_t Fun); + +/** + * @brief GPIOåˆå§‹åŒ– + * + * @param Pin Pinåºå· + * @param IsInput 是å¦ä¸ºè¾“入功能,1是,0å¦ + * @param InitValue åˆå§‹ç”µå¹³ï¼Œ1高,0低,åªå¯¹è¾“出有效 + + */ +void GPIO_Config(uint32_t Pin, uint8_t IsInput, uint8_t InitValue); + +/** + * @brief GPIOåˆå§‹åŒ–,并且åŒæ­¥æŽ§åˆ¶ä¸Šä¸‹æ‹‰ç”µé˜»ï¼Œå¢žå¼ºé©±åŠ¨åŠ›ï¼ŒåŒæ—¶å¸Œæœ›èƒ½æŽ¥è§£å†³ä¼‘眠无法ä¿æŒç”µå¹³çš„问题 + * + * @param Pin Pinåºå· + * @param IsInput 是å¦ä¸ºè¾“入功能,1是,0å¦ + * @param InitValue åˆå§‹ç”µå¹³ï¼Œ1高并且上拉,0低并且下拉 + * @param AltFun å¤ç”¨åŠŸèƒ½ï¼Œå¤§éƒ¨åˆ†Padå’ŒGPIO是一一对应的,如果出现多个Pad对应1个GPIO,如果AltFunä¸èƒ½åŒ¹é…则默认用Alt0çš„PAD + */ +void GPIO_ConfigWithPullEC618(uint32_t Pin, uint8_t IsInput, uint8_t InitValue, uint8_t AltFun); + +/** + * @brief GPIO上下拉控制 + * + * @param Pad Padåºå·ï¼Œæ³¨æ„这个ä¸æ˜¯Pinåºå· + * @param IsPull 是å¦éœ€è¦ä¸Šä¸‹æ‹‰ + * @param IsUp 是å¦ä¸Šæ‹‰ + + */ +void GPIO_PullConfig(uint32_t Pad, uint8_t IsPull, uint8_t IsUp); + +/** + * @brief GPIO外部中断åˆå§‹åŒ– + * + * @param Pin Pinåºå· + * @param IsLevel 是å¦æ˜¯ç”µå¹³ä¸­æ–­ï¼Œ0边沿型,1电平型 + * @param IsRiseHigh 上å‡æ²¿æˆ–者高电平,EC618的大部分GPIOåªèƒ½å•è¾¹æ²¿ä¸­æ–­ï¼Œæ‰€ä»¥ä¸Šå‡æ²¿å’Œä¸‹é™æ²¿åŒæ—¶é…置,设置æˆä¸Šå‡æ²¿ã€‚GPIO20~22å¯ä»¥å®žçŽ°åŒè¾¹æ²¿è§¦å‘ + * @param IsFallLow 下é™æ²¿æˆ–者低电平 + */ +void GPIO_ExtiConfig(uint32_t Pin, uint8_t IsLevel, uint8_t IsRiseHigh, uint8_t IsFallLow); + +/** + * @brief GPIOå¤ç”¨åŠŸèƒ½ + * + * @param Pad Padåºå·ï¼Œæ³¨æ„这个ä¸æ˜¯Pinåºå· + * @param Function å¤ç”¨åŠŸèƒ½ï¼Œè¿™ä¸ªéœ€è¦æ ¹æ®èŠ¯ç‰‡å®žé™…情况决定,当å‰æ˜¯0~7 + * @param AutoPull 上下拉是å¦å¯åŠ¨å¤–设功能的默认é…置,1å¯åŠ¨ï¼Œ0关闭,调用GPIO_PullConfig时会自动关闭,如果é…ç½®æˆå¤–è®¾åŠŸèƒ½ï¼Œå»ºè®®å¼€å¯ + * @param IsInputBuffer 输入是å¦å¯ç”¨ç¼“冲功能,1å¼€å¯ï¼Œ0å…³é—­ï¼Œå¦‚æžœæ˜¯ä¸­æ–­ï¼Œå»ºè®®å¼€å¯ + * + */ +void GPIO_IomuxEC618(uint32_t Pad, uint32_t Function, uint8_t AltFunctionPull, uint8_t IsInputBuffer); +/** + * @brief GPIO输出电平 + * + * @param Pin Pinåºå· + * @param Level 1高电平,0低电平 + */ +void GPIO_Output(uint32_t Pin, uint8_t Level); + +/** + * @brief GPIO输出电平,并且åŒæ­¥æŽ§åˆ¶ä¸Šä¸‹æ‹‰ç”µé˜»ï¼Œå¢žå¼ºé©±åŠ¨åŠ›ï¼ŒåŒæ—¶å¸Œæœ›èƒ½æŽ¥è§£å†³ä¼‘眠无法ä¿æŒç”µå¹³çš„问题 + * + * @param Pin Pinåºå· + * @param Level 1高电平,0低电平 + * @param AltFun å¤ç”¨åŠŸèƒ½ï¼Œå¤§éƒ¨åˆ†Padå’ŒGPIO是一一对应的,如果出现多个Pad对应1个GPIO,如果AltFunä¸èƒ½åŒ¹é…则默认用Alt0çš„PAD + */ +void GPIO_OutputWithPullEC618(uint32_t Pin, uint8_t Level, uint8_t AltFun); + +/** + * @brief 读å–GPIO输入电平 + * + * @param Pin Pinåºå· + * @return 1高电平, 0低电平,其他无效 + */ +uint8_t GPIO_Input(uint32_t Pin); + +/** + * @brief 翻转GPIO输出电平 + * + * @param Pin Pinåºå· + * @return æ—  + */ +void GPIO_Toggle(uint32_t Pin); +/** + * @brief GPIOåŒä¸€ç«¯å£å¤šä¸ªpin输出电平,针对类似STM32GPIO分布有效 + * + * @param Port 端å£å· 0或者1 + * @param Pins Pinåºå·ç»„åˆ + * @param Level 1高电平,0低电平 + */ +void GPIO_OutputMulti(uint32_t Port, uint32_t Pins, uint32_t Level); + +/** + * @brief 读å–GPIOåŒä¸€ç«¯å£å¤šä¸ªpin输入电平,如果是端å£1,GPIO20~GPIO22对应的bitå¯èƒ½æ˜¯ä¸æ­£å¸¸çš„,需è¦ç”¨GPIO_Input + * + * @param Port 端å£å· 0或者1 + * @return 0x0000~0xffff,æ¯ä¸ªbit代表一个pin的电平 + */ +uint32_t GPIO_InputMulti(uint32_t Port); + +/** + * @brief 翻转GPIOåŒä¸€ç«¯å£å¤šä¸ªpin输出电平 + * @param Port 端å£å· + * @param Pins Pinåºå·ç»„åˆ + * @return æ—  + */ +void GPIO_ToggleMulti(uint32_t Port, uint32_t Pins); + +/** + * @brief GPIO模拟å•çº¿è¾“å‡ºæ¨¡å¼ + * @param Pin Pinåºå· + * @param Data 输出电平åºåˆ— + * @param BitLen 输出电平åºåˆ—中一共有几个bit + * @param Delay æ¯ä¸ªbit之间的delay + * @return æ—  + */ +void GPIO_OutPulse(uint32_t Pin, uint8_t *Data, uint16_t BitLen, uint16_t Delay); + +/** + * @brief 设置外部中断,注æ„低功耗模å¼ä¸‹æ™®é€šGPIO是ä¸èƒ½ç”¨çš„,åªèƒ½ç”¨wakepad唤醒 + * @param Pin Pinåºå·ï¼Œè¿˜æœ‰WAKEPAD0 = HAL_GPIO_MAX,WAKEUPPAD2 = HAL_GPIO_MAX+1。WAKEUPPAD3~5å·²ç»å’ŒGPIOå¤ç”¨äº† + * @param CB 中断回调函数 + * @param Pins 中断回调时的param + * @return æ—  + */ +void GPIO_ExtiSetCB(uint32_t Pin, CBFuncEx_t CB, void *pParam); + +/** + * @brief GPIOåˆå§‹åŒ–æˆOD门输出 + * @param Pin Pinåºå· + * @param InitValue åˆå§‹ç”µå¹³ + * @return æ—  + */ +void GPIO_ODConfig(uint32_t Pin, uint8_t InitValue); + +/** + * @brief 从GPIOåºå·è½¬æ¢å‡ºPadåºå·ï¼Œå¦‚果有多个Padåºå·ï¼Œåˆ™ä¼šé€šè¿‡AltFun决定用哪个 + * + * @param Pin Pinåºå· + * @param AltFun å¤ç”¨åŠŸèƒ½ï¼Œå¤§éƒ¨åˆ†Padå’ŒGPIO是一一对应的,如果出现多个Pad对应1个GPIO,如果AltFunä¸èƒ½åŒ¹é…则默认用Alt0çš„PAD + * @return Padåºå· + */ +uint32_t GPIO_ToPadEC618(uint32_t Pin, uint8_t AltFun); + +/** + * @brief 设置WAKEUPPAD0å’ŒPAD2中断 + * + * @param Pin Pinåºå·ï¼Œåªæœ‰HAL_GPIO_MAXå’ŒHAL_GPIO_MAX+1,分别对应PAD0å’ŒPAD2,PAD1被USB用了,PAD3~PAD5有对应的GPIO,ä¸èƒ½åœ¨è¿™é‡Œè®¾ç½® + * @param IsRiseHigh 上å‡æ²¿è§¦å‘ + * @param IsFallLow 下é™æ²¿è§¦å‘ + * @param Pullup 上拉 + * @param Pulldown 下拉 + */ +void GPIO_WakeupPadConfig(uint32_t Pin, uint8_t IsRiseHigh, uint8_t IsFallLow, uint8_t Pullup, uint8_t Pulldown); +#endif diff --git a/PLAT/core/ld/ec618_0h00_flash.c b/PLAT/core/ld/ec618_0h00_flash.c new file mode 100644 index 0000000..91bea11 --- /dev/null +++ b/PLAT/core/ld/ec618_0h00_flash.c @@ -0,0 +1,339 @@ + +#include "mem_map.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ + ASMB_AREA(rwx) : ORIGIN = 0x00000000, LENGTH = 0x010000 /* 64KB */ + MSMB_AREA(rwx) : ORIGIN = 0x00400000, LENGTH = 0x140000 /* 1.25MB */ + FLASH_AREA(rx) : ORIGIN = 0x00824000, LENGTH = 2944K /* 2.5MB */ +} + +/* Define output sections */ +SECTIONS +{ + . = AP_FLASH_LOAD_ADDR; + .vector : + { + KEEP(*(.isr_vector)) + } >FLASH_AREA + .cache : ALIGN(128) + { + Image$$UNLOAD_NOCACHE$$Base = .; + *cache.o(.text*) + } >FLASH_AREA + + .load_bootcode 0x0 : + { + . = ALIGN(4); + Load$$LOAD_BOOTCODE$$Base = LOADADDR(.load_bootcode); + Image$$LOAD_BOOTCODE$$Base = .; + KEEP(*(.mcuVector)) + *(.ramBootCode) + *qspi.o(.text*) + *flash.o(.text*) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + + Image$$LOAD_BOOTCODE$$Length = SIZEOF(.load_bootcode); + + .load_ap_piram_asmb 0x1400 : + { + . = ALIGN(4); + Load$$LOAD_AP_PIRAM_ASMB$$Base = LOADADDR(.load_ap_piram_asmb); + Image$$LOAD_AP_PIRAM_ASMB$$Base = .; + *(.psPARamcode) + *(.platPARamcode) + *memset.o(.text*) + *memcpy-armv7m.o(.text*) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_PIRAM_ASMB$$Length = SIZEOF(.load_ap_piram_asmb); + + .load_ap_firam_asmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FIRAM_ASMB$$Base = LOADADDR(.load_ap_firam_asmb); + Image$$LOAD_AP_FIRAM_ASMB$$Base = .; + *(.psFARamcode) + *(.platFARamcode) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_FIRAM_ASMB$$Length = SIZEOF(.load_ap_firam_asmb); + + .load_ap_rwdata_asmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ap_rwdata_asmb); + Image$$LOAD_AP_FDATA_ASMB$$RW$$Base = .; + *(.platFARWData) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_FDATA_ASMB$$Length = SIZEOF(.load_ap_rwdata_asmb); + + .load_ps_rwdata_asmb : ALIGN(4) + { + Load$$LOAD_PS_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ps_rwdata_asmb); + Image$$LOAD_PS_FDATA_ASMB$$RW$$Base = .; + *(.psFARWData) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_PS_FDATA_ASMB$$RW$$Length = SIZEOF(.load_ps_rwdata_asmb); + + .load_ap_zidata_asmb (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_AP_FDATA_ASMB$$ZI$$Base = .; + *(.platFAZIData) + . = ALIGN(4); + Image$$LOAD_AP_FDATA_ASMB$$ZI$$Limit = .; + + Image$$LOAD_PS_FDATA_ASMB$$ZI$$Base = .; + *(.psFAZIData) + . = ALIGN(4); + Image$$LOAD_PS_FDATA_ASMB$$ZI$$Limit = .; + + *(.exceptCheck) + } >ASMB_AREA + + .load_rrcmem 0xB000 (NOLOAD): + { + *(.rrcMem) + } >ASMB_AREA + + .load_flashmem 0xC000 (NOLOAD): + { + *(.apFlashMem) + } >ASMB_AREA + + .load_ap_piram_msmb MSMB_START_ADDR : + { + . = ALIGN(4); + Load$$LOAD_AP_PIRAM_MSMB$$Base = LOADADDR(.load_ap_piram_msmb); + Image$$LOAD_AP_PIRAM_MSMB$$Base = .; + *(.psPMRamcode) + *(.platPMRamcode) + *(.platPMRamcodeFCLK) + *(.recordNodeRO) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_PIRAM_MSMB$$Length = SIZEOF(.load_ap_piram_msmb); + + .load_ap_firam_msmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FIRAM_MSMB$$Base = LOADADDR(.load_ap_firam_msmb); + Image$$LOAD_AP_FIRAM_MSMB$$Base = .; + *(.ramCode2) + *(.upRamCode) + *(.psFMRamcode) + *(.platFMRamcode) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_FIRAM_MSMB$$Length = SIZEOF(.load_ap_firam_msmb); + + .load_apos : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_APOS$$Base = LOADADDR(.load_apos); + Image$$LOAD_APOS$$Base = .; + *event_groups.o(.text*) + *heap_6.o(.text*) + *tlsf.o(.text*) + *list.o(.text*) + *queue.o(.text*) + *tasks.o(.text*) + *timers.o(.text*) + *port.o(.text*) + *port_asm.o(.text*) + *cmsis_os2.o(.text*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_APOS$$Length = SIZEOF(.load_apos); + + .load_dram_bsp : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_DRAM_BSP$$Base = LOADADDR(.load_dram_bsp); + Image$$LOAD_DRAM_BSP$$Base = .; + *bsp_spi.o(.data*) + *flash.o(.data*) + *flash_rt.o(.data*) + *gpr.o(.data*) + *apmu.o(.data*) + *apmuTiming.o(.data*) + *bsp.o(.data*) + *plat_config.o(.data*) + *system_ec618.o(.data*) + *unilog.o(.data*) + *pad.o(.data*) + *ic.o(.data*) + *ec_main.o(.data*) + *slpman.o(.data*) + *bsp_usart.o(.data*) + *bsp_lpusart.o(.data*) + *timer.o(.data*) + *dma.o(.data*) + *adc.o(.data*) + *wdt.o(.data*) + *usb_device.o(.data*) + *uart_device.o(.data*) + *clock.o(.data*) + *hal_adcproxy.o(.data*) + *hal_alarm.o(.data*) + *exception_process.o(.data*) + *exception_dump.o(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_DRAM_BSP$$Length = SIZEOF(.load_dram_bsp); + + .load_dram_bsp_zi (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_DRAM_BSP$$ZI$$Base = .; + *bsp_spi.o(.bss*) + *flash.o(.bss*) + *flash_rt.o(.bss*) + *gpr.o(.bss*) + *apmu.o(.bss*) + *apmuTiming.o(.bss*) + *bsp.o(.bss*) + *plat_config.o(.bss*) + *system_ec618.o(.bss*) + *unilog.o(.bss*) + *pad.o(.bss*) + *ic.o(.bss*) + *ec_main.o(.bss*) + *slpman.o(.bss*) + *bsp_usart.o(.bss*) + *bsp_lpusart.o(.bss*) + *timer.o(.bss*) + *dma.o(.bss*) + *adc.o(.bss*) + *wdt.o(.bss*) + *usb_device.o(.bss*) + *uart_device.o(.bss*) + *clock.o(.bss*) + **hal_trim.o(.bss*) + *hal_adcproxy.o(.bss*) + *hal_alarm.o(.bss*) + *exception_process.o(.bss*) + *exception_dump.o(.bss*) + *(.recordNodeZI) + . = ALIGN(4); + Image$$LOAD_DRAM_BSP$$ZI$$Limit = .; + } >MSMB_AREA + + .unload_slpmem (NOLOAD): + { + *(.sleepmem) + } >MSMB_AREA + + .load_dram_shared : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_DRAM_SHARED$$Base = LOADADDR(.load_dram_shared); + Image$$LOAD_DRAM_SHARED$$Base = .; + *(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_DRAM_SHARED$$Length = SIZEOF(.load_dram_shared); + + .load_dram_shared_zi (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_DRAM_SHARED$$ZI$$Base = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + *(.stack) /* stack should be 4 byte align */ + Image$$LOAD_DRAM_SHARED$$ZI$$Limit = .; + *(.USB_NOINIT_DATA_BUF) + } >MSMB_AREA + + + PROVIDE(end_ap_data = . ); + PROVIDE(start_up_buffer = up_buf_start); + .load_up_buffer start_up_buffer(NOLOAD): + { + *(.catShareBuf) + Image$$LOAD_UP_BUFFER$$Limit = .; + } >MSMB_AREA + + PROVIDE(end_up_buffer = . ); + heap_size = start_up_buffer - end_ap_data; + ASSERT(heap_size>=min_heap_size_threshold,"ap use too much ram, heap less than min_heap_size_threshold!") + ASSERT(end_up_buffer<=MSMB_APMEM_END_ADDR,"ap use too much ram, exceed to MSMB_APMEM_END_ADDR") + + .text : + { + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.text*) + } >FLASH_AREA + + .preinit_fun_array : + { + . = ALIGN(4); + __preinit_fun_array_start = .; + KEEP (*(SORT(.preinit_fun_array.*))) + KEEP (*(.preinit_fun_array*)) + __preinit_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + .init_fun_array : + { + . = ALIGN(4); + __init_fun_array_start = .; + KEEP (*(SORT(.init_fun_array.*))) + KEEP (*(.init_fun_array*)) + __init_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + + .task_fun_array : + { + . = ALIGN(4); + __task_fun_array_start = .; + KEEP (*(SORT(.task_fun_array.*))) + KEEP (*(.task_fun_array*)) + __task_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + + .unload_cpaon CP_AONMEMBACKUP_START_ADDR (NOLOAD): + { + + } >MSMB_AREA + + .load_xp_sharedinfo XP_SHAREINFO_BASE_ADDR (NOLOAD): + { + *(.shareInfo) + } >MSMB_AREA + + .load_dbg_area XP_DBGRESERVED_BASE_ADDR (NOLOAD): + { + *(.resetFlag) + } >MSMB_AREA + + .unload_xp_ipcmem IPC_SHAREDMEM_START_ADDR (NOLOAD): + { + + } >MSMB_AREA + +} + +GROUP( + libgcc.a + libc.a + libm.a + ) \ No newline at end of file diff --git a/PLAT/core/lib/libaisound50_16K.a b/PLAT/core/lib/libaisound50_16K.a new file mode 100644 index 0000000..8f9509e Binary files /dev/null and b/PLAT/core/lib/libaisound50_16K.a differ diff --git a/PLAT/core/lib/libaisound50_16K_lite_beta.a b/PLAT/core/lib/libaisound50_16K_lite_beta.a new file mode 100644 index 0000000..0325a17 Binary files /dev/null and b/PLAT/core/lib/libaisound50_16K_lite_beta.a differ diff --git a/PLAT/core/lib/libaisound50_8K.a b/PLAT/core/lib/libaisound50_8K.a new file mode 100644 index 0000000..1a33ec2 Binary files /dev/null and b/PLAT/core/lib/libaisound50_8K.a differ diff --git a/PLAT/core/lib/libaisound50_8K_lite_beta.a b/PLAT/core/lib/libaisound50_8K_lite_beta.a new file mode 100644 index 0000000..e484a31 Binary files /dev/null and b/PLAT/core/lib/libaisound50_8K_lite_beta.a differ diff --git a/PLAT/core/multimedia/include/audio_ll_drv.h b/PLAT/core/multimedia/include/audio_ll_drv.h new file mode 100644 index 0000000..9bb2638 --- /dev/null +++ b/PLAT/core/multimedia/include/audio_ll_drv.h @@ -0,0 +1,117 @@ +/** + * @file audio_ll_drv.h + * @brief 音频数æ®å¯¹æŽ¥åˆ°åº•å±‚硬件驱动的中间层,为了兼容多ç§æƒ…况并ä¸æ˜¯æœ€ä¼˜åŒ–,由于硬件驱动代ç æ˜¯å¼€æºçš„,用户å¯ä»¥ä¸ç”¨ï¼Œè‡ªå·±å¯¹æŽ¥é©±åŠ¨ä»£ç  + * @version 0.1 + * @date 2022-10-23 + * + * @copyright + * + */ +#ifndef __AUDIO_LL_DRV_H__ +#define __AUDIO_LL_DRV_H__ + +typedef enum +{ + AUSTREAM_FORMAT_UNKNOWN, ///< placeholder for unknown format + AUSTREAM_FORMAT_PCM, ///< raw PCM data + AUSTREAM_FORMAT_WAVPCM, ///< WAV, PCM inside + AUSTREAM_FORMAT_MP3, ///< MP3 + AUSTREAM_FORMAT_AMRNB, ///< AMR-NB + AUSTREAM_FORMAT_AMRWB, ///< AMR_WB + AUSTREAM_FORMAT_SBC, ///< bt SBC +} auStreamFormat_t; + +typedef enum +{ + AUSTREAM_BUS_DAC, + AUSTREAM_BUS_I2S, +} auStreamBusType_t; + +typedef struct +{ + CBFuncEx_t CB; //pData是自身Audio_StreamStruct指针 + CBFuncEx_t Decoder; + CBFuncEx_t Encoder; + void *pParam; + void *fd; + void *CoderParam; + void *UserParam; + Buffer_Struct FileDataBuffer; + Buffer_Struct AudioDataBuffer; + Buffer_Struct RomDataBuffer; + llist_head DataHead; + llist_head NeedFreeDataHead; + uint32_t SampleRate; + uint32_t waitRequire; + uint8_t BitDepth; + uint8_t ChannelCount; //声é“,目å‰åªæœ‰1或者2 + auStreamFormat_t Format; + auStreamBusType_t BusType; //音频总线类型,DAC, IIS之类的 + uint8_t BusID; //音频总线ID + uint8_t IsDataSigned; //æ•°æ®æ˜¯å¦æ˜¯æœ‰ç¬¦å·çš„ + uint8_t IsHardwareRun; + uint8_t IsPause; + uint8_t IsStop; + uint8_t IsPlaying; + uint8_t IsFileNotEnd; + uint8_t DecodeStep; +}Audio_StreamStruct; + +/** + * @brief 音频驱动åˆå§‹åŒ– + * + */ +void Audio_GlobalInit(void); +/** + * @brief 基于I2S总线的外部codec相关I2S总线模å¼é…置,并ä¸å¯¹codecçš„I2Cå¤„ç† + * + * @param bus_id I2S总线åºå·ï¼Œ0或者1 + * @param mode I2S模å¼ï¼ŒI2S_MODE_I2S,I2S_MODE_MSB,I2S_MODE_LSB,一般常è§MODE_I2Så’ŒMODE_MSB + * @param frame_size I2S帧模å¼ï¼ŒI2S_FRAME_SIZE_16_16,I2S_FRAME_SIZE_16_32,I2S_FRAME_SIZE_24_32,I2S_FRAME_SIZE_32_32,目å‰åªç”¨åˆ° + * I2S_FRAME_SIZE_16_16 + */ +void Audio_CodecI2SInit(uint8_t bus_id, uint8_t mode, uint8_t frame_size); + +/** + * @brief å¼€å§‹æ’­æ”¾åŽŸå§‹éŸ³é¢‘æµ + * + * @param pStream 原始音频æµæ•°æ®ç»“æž„, 底层ä¸ä¿å­˜è¿™ä¸ªç»“构,需è¦ç”¨æˆ·ä¿å­˜ + * @return =0 æˆåŠŸ < 0å¤±è´¥é”™è¯¯ç  + */ +int32_t Audio_StartRaw(Audio_StreamStruct *pStream); +/** + * @brief 写入原始音频数æ®åˆ°åº•å±‚ + * + * @param pStream 原始音频æµæ•°æ®ç»“æž„ + * @param pByteData åŽŸå§‹éŸ³é¢‘æ•°æ® + * @param ByteLen 原始音频数æ®å­—节长度 + * @param AddHead 是å¦æ’入到开头播放åºåˆ—,1æ’入开头,0æ’入结尾。一般用于开始/æ¢å¤æ’­æ”¾æ—¶æ’入空白段以消除爆破音,正常数æ®ä¸è¦æ’入开头 + * @return int32_t =0 æˆåŠŸ < 0å¤±è´¥é”™è¯¯ç  + */ +int32_t Audio_WriteRaw(Audio_StreamStruct *pStream, uint8_t *pByteData, uint32_t ByteLen, uint8_t AddHead); +/** + * @brief 终止音频数æ®æ’­æ”¾ + * + * @param pStream 原始音频æµæ•°æ®ç»“æž„ + */ +void Audio_Stop(Audio_StreamStruct *pStream); +/** + * @brief 清除播放完的数æ®ï¼Œéœ€è¦åœ¨ä»»åŠ¡ä¸­è¿›è¡Œ + * + * @param pStream 原始音频æµæ•°æ®ç»“æž„ + */ +void Audio_DeleteOldData(Audio_StreamStruct *pStream); +/** + * @brief æš‚åœæ’­æ”¾éŸ³é¢‘æ•°æ®ï¼Œåªæ˜¯è®¾ç½®åœæ­¢æ ‡å¿—,已ç»åœ¨é©±åŠ¨ä¸­çš„æ•°æ®ä»ç„¶ä¼šæ’­æ”¾ + * + * @param pStream 原始音频æµæ•°æ®ç»“æž„ + */ +void Audio_Pause(Audio_StreamStruct *pStream); +/** + * @brief æ¢å¤æ’­æ”¾éŸ³é¢‘æ•°æ® + * + * @param pStream 原始音频æµæ•°æ®ç»“æž„ + */ +void Audio_Resume(Audio_StreamStruct *pStream); + +#endif diff --git a/PLAT/core/multimedia/include/audio_play.h b/PLAT/core/multimedia/include/audio_play.h new file mode 100644 index 0000000..bc9172b --- /dev/null +++ b/PLAT/core/multimedia/include/audio_play.h @@ -0,0 +1,177 @@ +/** + * @file audio_play.h + + * @brief 音频播放层,需è¦é…åˆtts库,audio_decoder库和audio_ll_drv使用 + * @version 0.1 + * @date 2022-10-23 + * + * @copyright + * + */ + +#ifndef __AUDIO_PLAY_H__ +#define __AUDIO_PLAY_H__ + +typedef struct +{ + char *path; //文件路径,如果为NULL,则表示是ROM数组 + uint32_t address; //ROMæ•°ç»„åœ°å€ + uint32_t rom_data_len; //ROM数组长度 + uint8_t fail_continue; //如果解ç å¤±è´¥æ˜¯å¦è·³è¿‡ç»§ç»­ä¸‹ä¸€ä¸ªï¼Œå¦‚果是最åŽä¸€ä¸ªæ–‡ä»¶ï¼Œå¼ºåˆ¶åœæ­¢å¹¶è®¾ç½®é”™è¯¯ä¿¡æ¯ + uint8_t dummy[3]; +}audio_play_info_t; + +enum +{ + MULTIMEDIA_DATA_TYPE_NONE, + MULTIMEDIA_DATA_TYPE_PCM, + MULTIMEDIA_DATA_TYPE_MP3, + MULTIMEDIA_DATA_TYPE_WAV, + MULTIMEDIA_DATA_TYPE_AMR_NB, + MULTIMEDIA_DATA_TYPE_AMR_WB, +}; + +enum +{ + MULTIMEDIA_CB_AUDIO_DECODE_START, //开始解ç æ–‡ä»¶ + MULTIMEDIA_CB_AUDIO_OUTPUT_START, //开始输出解ç åŽçš„éŸ³æ•°æ® + MULTIMEDIA_CB_AUDIO_NEED_DATA, //底层驱动播放播放完一部分数æ®ï¼Œéœ€è¦æ›´å¤šæ•°æ® + MULTIMEDIA_CB_AUDIO_DONE, //底层驱动播放完全部数æ®äº† + MULTIMEDIA_CB_DECODE_DONE, //音频解ç å®Œæˆ + MULTIMEDIA_CB_TTS_INIT, //TTSåšå®Œäº†å¿…è¦çš„åˆå§‹åŒ–,用户å¯ä»¥é€šè¿‡audio_play_tts_set_paramåšä¸ªæ€§åŒ–é…ç½® + MULTIMEDIA_CB_TTS_DONE, //TTSç¼–ç å®Œæˆäº†ã€‚注æ„ä¸æ˜¯æ’­æ”¾å®Œæˆ +}; +extern const unsigned char ivtts_8k[]; +extern const unsigned char ivtts_8k_lite[]; +extern const unsigned char ivtts_16k_lite[]; +extern const unsigned char ivtts_16k[]; +extern const unsigned char ivtts_8k_tz_data[]; +extern const unsigned char ivtts_8k_tz_frags[]; +extern const unsigned char ivtts_16k_tz_data[]; +extern const unsigned char ivtts_16k_tz_frags[]; +/** + * @brief 播放时event回调,è§MULTIMEDIA_CB_XXX,user_param就是åˆå§‹åŒ–时传入的user_param + * + */ +typedef void (*audio_play_event_cb_fun_t)(uint32_t cb_audio_event, void *user_param); + +/** + * @brief 播放文件时,在数æ®è§£ç å‡ºæ¥åŽï¼Œä¼šå›žè°ƒç»™ç”¨æˆ·åšè¿›ä¸€æ­¥å¤„ç†ï¼Œæ¯”如音é‡çš„软件增å‡ï¼Œè½¯ä»¶é™éŸ³ï¼Œå½“然也å¯ä»¥ä¸å¤„ç†ã€‚æ•°æ®é•¿åº¦æ˜¯å­—节数,bits是é‡åŒ–ä½æ•°ï¼Œä¸€èˆ¬æ˜¯16,channels是声é“数,1或者2 + * + */ +typedef void (*audio_play_data_cb_fun_t)(uint8_t *data, uint32_t data_len, uint8_t bits, uint8_t channels); + +typedef void (*audio_play_default_fun_t)(void *param); +/** + * @brief 音频播放åˆå§‹åŒ– + * + * @param event_cb 播放时event回调函数 + * @param data_cb æ•°æ®è§£ç å›žè°ƒå‡½æ•°ï¼Œå¦‚果是直接播放原始数æ®æµå°±ä¸ä¼šç”¨åˆ° + * @param user_param 回调函数的用户å‚æ•° + */ +void audio_play_global_init(audio_play_event_cb_fun_t event_cb, audio_play_data_cb_fun_t data_cb, void *user_param); + +/** + * @brief 播放指定数é‡çš„文件或者ROM数组(文件数æ®ç›´æŽ¥å†™æˆæ•°ç»„å½¢å¼ï¼‰ + * + * @param multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param info 文件信æ¯ï¼Œæ–‡ä»¶è·¯å¾„或者ROMä¿¡æ¯ + * @param files_num æ–‡ä»¶æ•°é‡ + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_multi_files(uint32_t multimedia_id, audio_play_info_t info[], uint32_t files_num); + +/** + * @brief 是å¦æ’­æ”¾å®Œå…¨éƒ¨æ•°æ® + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @return uint8_t =1是,=0没有 + */ +uint8_t audio_play_is_finish(uint32_t multimedia_id); + +/** + * @brief 强制åœæ­¢æ’­æ”¾æ–‡ä»¶ï¼Œä½†æ˜¯ä¸ä¼šåœæ­¢å·²ç»è¾“出到底层驱动的数æ®æ’­æ”¾ + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_stop(uint32_t multimedia_id); +/** + * @brief æš‚åœ/æ¢å¤æ’­æ”¾ + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param is_pause 0æ¢å¤ï¼Œå…¶ä»–æš‚åœ + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_pause_raw(uint32_t multimedia_id, uint8_t is_pause); + +/** + * @brief 获å–上一次播放结果,在MULTIMEDIA_CB_AUDIO_DONE回调时调用最佳 + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @return int =0完整的播放完æˆï¼Œ<0被用户åœæ­¢äº†ï¼Œ>0 TTS失败,或者第几个音频文件解ç å¤±è´¥ï¼ˆç”¨æˆ·åœ¨play_info未设置了解ç å¤±è´¥åŽç»§ç»­ï¼Œæ–‡ä»¶ä½ç½®+1) + */ +int audio_play_get_last_error(uint32_t multimedia_id); + +/** + * @brief æ’入多段空白数æ®ï¼Œæ¯æ®µæ•°æ®çº¦100ms + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param cnt 段数 + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_write_blank_raw(uint32_t multimedia_id, uint8_t cnt); +/** + * @brief 立刻åˆå§‹åŒ–播放未编ç çš„原始音频数æ®æµ + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param audio_format 音频数æ®æ ¼å¼ï¼Œç›®å‰åªæ”¯æŒPCM,å³éœ€è¦æ‰‹åŠ¨è§£ç  + * @param num_channels 声é“数,目å‰åªèƒ½1或2 + * @param sample_rate 采样率,注æ„åªæœ‰8K,16K,32K,48K,96K,22.05K,44.1Kè¿™äº›èƒ½è¢«æ”¯æŒ + * @param bits_per_sample é‡åŒ–bit,åªèƒ½æ˜¯16 + * @param is_signed é‡åŒ–æ•°æ®æ˜¯å¦å¸¦ç¬¦å·ï¼Œåªèƒ½æ˜¯1 + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_start_raw(uint32_t multimedia_id, uint8_t audio_format, uint8_t num_channels, uint32_t sample_rate, uint8_t bits_per_sample, uint8_t is_signed); +/** + * @brief å‘åº•å±‚é©±åŠ¨ä¼ å…¥ä¸€æ®µåŽŸå§‹éŸ³é¢‘æ•°æ® + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param data åŽŸå§‹éŸ³é¢‘æ•°æ® + * @param len 原始音频数æ®é•¿åº¦ + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_write_raw(uint32_t multimedia_id, uint8_t *data, uint32_t len); +/** + * @brief 强制åœæ­¢æ‰€æœ‰æ’­æ”¾ï¼ŒåŒæ—¶åº•å±‚驱动也会åœæ­¢è¾“出,ä¸è¦ç”¨äºŽæ’­æ”¾æ–‡ä»¶çš„ç»“æŸ + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_stop_raw(uint32_t multimedia_id); +/** + * @brief ç¼–ç å¹¶æ’­æ”¾ä¸€æ®µæ–‡å­— + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param text æ–‡å­—æ•°æ® + * @param text_bytes 文字数æ®é•¿åº¦ + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_tts_text(uint32_t multimedia_id, void *text, uint32_t text_bytes); +/** + * @brief 在收到MULTIMEDIA_CB_TTS_INIT回调时,å¯ä»¥è®¾ç½®TTSå‚数,等åŒäºŽivTTS_SetParam + * + * @param multimedia_id multimedia_id 多媒体通é“,目å‰åªæœ‰0 + * @param param_id è§ivTTS_PARAM_XXX + * @param param_value param_id对应的value + * @return int =0æˆåŠŸï¼Œå…¶ä»–失败 + */ +int audio_play_tts_set_param(uint32_t multimedia_id, uint32_t param_id, uint32_t param_value); +/** + * @brief 设置TTS的资æºå’Œå¯¹åº”SDKID,TTS资æºæœ‰å¾ˆå¤šç§ã€‚ + * + * @param address 资æºçš„flash或者ramåœ°å€ + * @param sdk_id 本质上就是传入AISOUND_SDK_USERID + */ +void audio_play_tts_set_resource(void *address, void *sdk_id); +#endif diff --git a/PLAT/core/speed/lte_speed.c b/PLAT/core/speed/lte_speed.c new file mode 100644 index 0000000..64c2a71 --- /dev/null +++ b/PLAT/core/speed/lte_speed.c @@ -0,0 +1,15 @@ +#include "psdial_ps_ctrl.h" +#include "cms_comm.h" +#include "common_api.h" + +ALIGNED_4BYTE CAT_PSPHY_SHAREDATA UINT8 psUpMem[PS_DIAL_PS_UP_MEM_SIZE]; + +void *psDialGetUpMemAndSize(UINT32 *pUpMemSize) +{ + if (pUpMemSize != PNULL) + { + *pUpMemSize = sizeof(psUpMem); + } + + return (void *)psUpMem; +} diff --git a/PLAT/core/tts/include/16k_lite_ver/ivTTSSDKID.h b/PLAT/core/tts/include/16k_lite_ver/ivTTSSDKID.h new file mode 100644 index 0000000..6ce5a73 --- /dev/null +++ b/PLAT/core/tts/include/16k_lite_ver/ivTTSSDKID.h @@ -0,0 +1,9 @@ + +/* SDK ID */ + +#ifndef AISOUND_5_0_SDK_CONSISTENCE__H +#define AISOUND_5_0_SDK_CONSISTENCE__H + +#define AISOUND_SDK_USERID ((ivCStrA)"\x35\x30\x63\x32\x63\x34\x63\x65\x66\x31\x61\x39\x34\x30\x31\x66\x61\x61\x31\x30\x66\x64\x61\x30\x36\x31\x61\x61\x37\x66\x62\x34") +#endif /* !AISOUND_SDK_CONSISTENCE__H */ + diff --git a/PLAT/core/tts/include/8k_lite_ver/ivTTSSDKID.h b/PLAT/core/tts/include/8k_lite_ver/ivTTSSDKID.h new file mode 100644 index 0000000..a52294a --- /dev/null +++ b/PLAT/core/tts/include/8k_lite_ver/ivTTSSDKID.h @@ -0,0 +1,9 @@ + +/* SDK ID */ + +#ifndef AISOUND_5_0_SDK_CONSISTENCE__H +#define AISOUND_5_0_SDK_CONSISTENCE__H + +#define AISOUND_SDK_USERID ((ivCStrA)"\x32\x65\x36\x31\x31\x32\x62\x65\x32\x30\x31\x64\x34\x34\x63\x39\x61\x30\x61\x66\x36\x65\x64\x30\x66\x62\x61\x64\x62\x64\x37\x00") +#endif /* !AISOUND_SDK_CONSISTENCE__H */ + diff --git a/PLAT/core/tts/include/ivDefine.h b/PLAT/core/tts/include/ivDefine.h new file mode 100644 index 0000000..9402b1a --- /dev/null +++ b/PLAT/core/tts/include/ivDefine.h @@ -0,0 +1,388 @@ +/*--------------------------------------------------------------+ + | | + | ivDefine.h - Basic Definitions | + | | + | Copyright (c) 1999-2008, ANHUI USTC iFLYTEK CO.,LTD. | + | All rights reserved. | + | | + +--------------------------------------------------------------*/ + +#ifndef IFLYTEK_VOICE__DEFINE__H +#define IFLYTEK_VOICE__DEFINE__H + + +#include "ivPlatform.h" + + +#define IV_CHECK_RES_READ 1 /* ÊÇ·ñ¼ì²éÓû§»Øµ÷º¯Êý¶ÁÈ¡×ÊÔ´µÄ³É¹¦ÐÔ */ +/* + * ÐÞÊηû + */ + +#define ivConst IV_CONST +#define ivStatic IV_STATIC +#ifdef IV_INLINE +#define ivInline IV_STATIC IV_INLINE +#else +#define ivInline IV_STATIC +#endif +#define ivExtern IV_EXTERN + +#define ivPtr IV_PTR_PREFIX* +#define ivCPtr ivConst ivPtr +#define ivPtrC ivPtr ivConst +#define ivCPtrC ivConst ivPtr ivConst + +#define ivCall IV_CALL_STANDARD /* ·ÇµÝ¹éµÄ(²»¿ÉÖØÈëµÄ) */ +#define ivReentrant IV_CALL_REENTRANT /* µÝ¹éµÄ(¿ÉÖØÈëµÄ) */ +#define ivVACall IV_CALL_VAR_ARG /* Ö§³Ö±ä²ÎµÄ */ + +#define ivProc ivCall ivPtr + + +/* + * ¶¨Òå + */ + +#define ivNull (0) + +/* ²¼¶ûÀàÐͼ°ÆäÖµ(Ðë¸ù¾Ýƽ̨¶¨ÖÆ) */ +typedef int ivBool; + +#define ivTrue (~0) +#define ivFalse (0) + +/* ¶Ô±ÈÀàÐͼ°ÆäÖµ */ +typedef int ivComp; + +#define ivGreater (1) +#define ivEqual (0) +#define ivLesser (-1) + +#define ivIsGreater(v) ((v)>0) +#define ivIsEqual(v) (0==(v)) +#define ivIsLesser(v) ((v)<0) + + +/* + * Êý¾ÝÀàÐÍ + */ + +/* »ù±¾ÖµÀàÐÍ */ +typedef signed IV_TYPE_INT8 ivInt8; /* 8-bit */ +typedef unsigned IV_TYPE_INT8 ivUInt8; /* 8-bit */ + +typedef signed IV_TYPE_INT16 ivInt16; /* 16-bit */ +typedef unsigned IV_TYPE_INT16 ivUInt16; /* 16-bit */ + +typedef signed IV_TYPE_INT24 ivInt24; /* 24-bit */ +typedef unsigned IV_TYPE_INT24 ivUInt24; /* 24-bit */ + +typedef signed IV_TYPE_INT32 ivInt32; /* 32-bit */ +typedef unsigned IV_TYPE_INT32 ivUInt32; /* 32-bit */ + +#ifdef IV_TYPE_INT48 +typedef signed IV_TYPE_INT48 ivInt48; /* 48-bit */ +typedef unsigned IV_TYPE_INT48 ivUInt48; /* 48-bit */ +#endif + +#ifdef IV_TYPE_INT64 +typedef signed IV_TYPE_INT64 ivInt64; /* 64-bit */ +typedef unsigned IV_TYPE_INT64 ivUInt64; /* 64-bit */ +#endif + +/* ÏàÓ¦µÄÖ¸ÕëÀàÐÍ */ +typedef ivInt8 ivPtr ivPInt8; /* 8-bit */ +typedef ivUInt8 ivPtr ivPUInt8; /* 8-bit */ + +typedef ivInt16 ivPtr ivPInt16; /* 16-bit */ +typedef ivUInt16 ivPtr ivPUInt16; /* 16-bit */ + +typedef ivInt24 ivPtr ivPInt24; /* 24-bit */ +typedef ivUInt24 ivPtr ivPUInt24; /* 24-bit */ + +typedef ivInt32 ivPtr ivPInt32; /* 32-bit */ +typedef ivUInt32 ivPtr ivPUInt32; /* 32-bit */ + +#ifdef IV_TYPE_INT48 +typedef ivInt48 ivPtr ivPInt48; /* 48-bit */ +typedef ivUInt48 ivPtr ivPUInt48; /* 48-bit */ +#endif + +#ifdef IV_TYPE_INT64 +typedef ivInt64 ivPtr ivPInt64; /* 64-bit */ +typedef ivUInt64 ivPtr ivPUInt64; /* 64-bit */ +#endif + +/* ³£Á¿Ö¸ÕëÀàÐÍ */ +typedef ivInt8 ivCPtr ivPCInt8; /* 8-bit */ +typedef ivUInt8 ivCPtr ivPCUInt8; /* 8-bit */ + +typedef ivInt16 ivCPtr ivPCInt16; /* 16-bit */ +typedef ivUInt16 ivCPtr ivPCUInt16; /* 16-bit */ + +typedef ivInt24 ivCPtr ivPCInt24; /* 24-bit */ +typedef ivUInt24 ivCPtr ivPCUInt24; /* 24-bit */ + +typedef ivInt32 ivCPtr ivPCInt32; /* 32-bit */ +typedef ivUInt32 ivCPtr ivPCUInt32; /* 32-bit */ + +#ifdef IV_TYPE_INT48 +typedef ivInt48 ivCPtr ivPCInt48; /* 48-bit */ +typedef ivUInt48 ivCPtr ivPCUInt48; /* 48-bit */ +#endif + +#ifdef IV_TYPE_INT64 +typedef ivInt64 ivCPtr ivPCInt64; /* 64-bit */ +typedef ivUInt64 ivCPtr ivPCUInt64; /* 64-bit */ +#endif + +/* ±ß½çÖµ¶¨Òå */ +#define IV_SBYTE_MAX (+127) +#define IV_MAX_INT16 (+32767) +#define IV_INT_MAX (+8388607L) +#define IV_MAX_INT32 (+2147483647L) + +#define IV_SBYTE_MIN (-IV_SBYTE_MAX - 1) +#define IV_MIN_INT16 (-IV_MAX_INT16 - 1) +#define IV_INT_MIN (-IV_INT_MAX - 1) +#define IV_MIN_INT32 (-IV_MAX_INT32 - 1) + +#define IV_BYTE_MAX (0xffU) +#define IV_USHORT_MAX (0xffffU) +#define IV_UINT_MAX (0xffffffUL) +#define IV_ULONG_MAX (0xffffffffUL) + +/* ÄÚ´æ»ù±¾µ¥Ôª */ +typedef ivUInt8 ivByte; +typedef ivPUInt8 ivPByte; +typedef ivPCUInt8 ivPCByte; + +typedef signed ivInt; +typedef signed ivPtr ivPInt; +typedef signed ivCPtr ivPCInt; + +typedef unsigned ivUInt; +typedef unsigned ivPtr ivPUInt; +typedef unsigned ivCPtr ivPCUInt; + +/* Ö¸Õë */ +typedef void ivPtr ivPointer; +typedef void ivCPtr ivCPointer; + +/* ¾ä±ú */ +typedef ivPointer ivHandle; + +/* µØÖ·¡¢³ß´çÀàÐÍ */ +typedef IV_TYPE_ADDRESS ivAddress; +typedef IV_TYPE_SIZE ivSize; + +typedef ivAddress ivPtr ivPAddress; +/* + * ×Ö·ûÏà¹Ø¶¨Òå + */ + +/* ×Ö·ûÀàÐͶ¨Òå */ +typedef ivInt8 ivCharA; +typedef ivUInt16 ivCharW; + +#if IV_UNICODE +typedef ivCharW ivChar; +#else +typedef ivCharA ivChar; +#endif + + +/* ×Ö·û´®ÀàÐͶ¨Òå */ +typedef ivCharA ivPtr ivStrA; +typedef ivCharA ivCPtr ivCStrA; + +typedef ivCharW ivPtr ivStrW; +typedef ivCharW ivCPtr ivCStrW; + +typedef ivChar ivPtr ivStr; +typedef ivChar ivCPtr ivCStr; + + +/* Îı¾³£Á¿ºê */ +#define ivTextA(s) ((ivCStrA)s) +#define ivTextW(s) ((ivCStrW)L##s) + +#if IV_UNICODE +#define ivText(s) ivTextW(s) +#else +#define ivText(s) ivTextA(s) +#endif + + +/* + * ×ÊÔ´µØÖ·¡¢³ß´çÀàÐͼ°Êý¾ÝÀàÐÍ´óС³£Á¿ + */ + +typedef ivUInt32 ivResAddress; +typedef ivUInt32 ivResSize; + +#define ivResSize_Int8 1 +#define ivResSize_Int16 2 +#define ivResSize_Int32 4 + +/* read resource callback type */ +#if IV_UNIT_BITS == 16 + +/* #if IV_CHECK_RES_READ */ +typedef ivBool (ivProc ivCBReadResExt)( + ivPointer pParameter, /* [in] user callback parameter */ + ivPointer pBuffer, /* [out] read resource buffer */ + ivResAddress iPos, /* [in] read start position */ + ivResSize nSize, /* [in] read size */ + ivSize nCount ); /* [in] read count */ +/* #else */ +typedef void (ivProc ivCBReadRes)( + ivPointer pParameter, /* [in] user callback parameter */ + ivPointer pBuffer, /* [out] read resource buffer */ + ivResAddress iPos, /* [in] read start position */ + ivResSize nSize, /* [in] read size */ + ivSize nCount ); /* [in] read count */ +/* #endif */ + +#else + +/* #if IV_CHECK_RES_READ */ +typedef ivBool (ivProc ivCBReadResExt)( + ivPointer pParameter, /* [in] user callback parameter */ + ivPointer pBuffer, /* [out] read resource buffer */ + ivResAddress iPos, /* [in] read start position */ + ivResSize nSize ); /* [in] read size */ +/* #else */ +typedef void (ivProc ivCBReadRes)( + ivPointer pParameter, /* [in] user callback parameter */ + ivPointer pBuffer, /* [out] read resource buffer */ + ivResAddress iPos, /* [in] read start position */ + ivResSize nSize ); /* [in] read size */ +/* #endif */ + +#endif + +/* map resource callback type */ +typedef ivCPointer (ivProc ivCBMapRes)( + ivPointer pParameter, /* [in] user callback parameter */ + ivResAddress iPos, /* [in] map start position */ + ivResSize nSize ); /* [in] map size */ + +/* log callback type */ +typedef ivUInt16 (ivProc ivCBLogExt) +( + ivPointer pParameter, /* [out] user callback parameter */ + ivCPointer pcData, /* [in] output data buffer */ + ivSize nSize /* [in] output data size */ + ); + + +/* resource pack description */ +typedef struct tagResPackDescExt ivTResPackDescExt, ivPtr ivPResPackDescExt; + +struct tagResPackDescExt +{ + ivPointer pCBParam; /* resource callback parameter */ + ivCBReadResExt pfnRead; /* read resource callback entry */ + ivCBMapRes pfnMap; /* map resource callback entry (optional) */ + ivResSize nSize; /* resource pack size (optional, 0 for null) */ + + ivPUInt8 pCacheBlockIndex; /* cache block index (optional, size = dwCacheBlockCount) */ + ivPointer pCacheBuffer; /* cache buffer (optional, size = dwCacheBlockSize * dwCacheBlockCount) */ + ivSize nCacheBlockSize; /* cache block size (optional, must be 2^N) */ + ivSize nCacheBlockCount; /* cache block count (optional, must be 2^N) */ + ivSize nCacheBlockExt; /* cache block ext (optional) */ +}; + + +/* ESR resource pack description */ +typedef struct tagResPackDesc ivTResPackDesc, ivPtr ivPResPackDesc; + +struct tagResPackDesc +{ + ivPointer pCBParam; /* resource callback parameter */ + ivCBReadRes pfnRead; /* read resource callback entry */ + ivCBMapRes pfnMap; /* map resource callback entry (optional) */ + ivResSize nSize; /* resource pack size (optional, 0 for null) */ + + ivPUInt8 pCacheBlockIndex; /* cache block index (optional, size = dwCacheBlockCount) */ + ivPointer pCacheBuffer; /* cache buffer (optional, size = dwCacheBlockSize * dwCacheBlockCount) */ + ivSize nCacheBlockSize; /* cache block size (optional, must be 2^N) */ + ivSize nCacheBlockCount; /* cache block count (optional, must be 2^N) */ + ivSize nCacheBlockExt; /* cache block ext (optional) */ +}; + + + + + + + +/* Save data callback type */ +typedef ivBool (ivProc ivCBSaveData)( + ivPointer pUserParam, + ivPointer pSrcBuffer, + ivSize nBufferBytes + ); + +/* Load data callback type */ +typedef ivBool (ivProc ivCBLoadData)( + ivPointer pUserParam, + ivPointer pDstBuffer, + ivSize ivPtr pnBufferBytes + ); + +/* LOG output callback type */ +typedef void (ivProc ivCBLog)( + ivPointer pUserParam, + ivCPointer pLogData, + ivSize nBytes + ); + + +typedef ivPointer (ivProc ivCBRealloc)( + ivPointer pUserParam, + ivPointer pMemblock, + ivSize nBytes + ); + +typedef void (ivProc ivCBFree)( + ivPointer pUserParam, + ivPointer pBuffer + ); + +typedef ivBool (ivProc ivCBStartRecord)( + ivPointer pUserParam + ); + +typedef ivBool (ivProc ivCBStopRecord)( + ivPointer pUserParam + ); + +typedef struct tagUserSys +{ + ivPointer pWorkBuffer; + ivSize nWorkBufferBytes; + + ivPointer pResidentBuffer; + ivSize nResidentBufferBytes; + + ivBool bCheckResource; + + ivPointer pCBParam; + + ivCBSaveData pfnSaveData; + ivCBLoadData pfnLoadData; + + ivCBRealloc pfnRealloc; + ivCBFree pfnFree; + + ivCBStartRecord pfnStartRecord; + ivCBStopRecord pfnStopRecord; + + ivCBLog pfnLog; +}TUserSys, ivPtr PUserSys, ivPtr ivPUserSys; + + +#endif /* !IFLYTEK_VOICE__DEFINE__H */ diff --git a/PLAT/core/tts/include/ivPlatform.h b/PLAT/core/tts/include/ivPlatform.h new file mode 100644 index 0000000..8245989 --- /dev/null +++ b/PLAT/core/tts/include/ivPlatform.h @@ -0,0 +1,77 @@ +/*--------------------------------------------------------------+ + | | + | ivPlatform.h - Platform Config | + | | + | Platform: Win32 (X86) | + | | + | Copyright (c) 1999-2008, ANHUI USTC iFLYTEK CO.,LTD. | + | All rights reserved. | + | | + +--------------------------------------------------------------*/ + + +/* + * TODO: ÔÚÕâÀï°üº¬Ä¿±êƽ̨³ÌÐòÐèÒªµÄ¹«¹²Í·Îļþ + */ + +//#include +//#include +#include +#include +#include +//#include +//#include + + +/* + * TODO: ¸ù¾ÝÄ¿±êƽ̨ÌØÐÔÐÞ¸ÄÏÂÃæµÄÅäÖÃÑ¡Ïî + */ + +#define IV_UNIT_BITS 8 /* ÄÚ´æ»ù±¾µ¥ÔªÎ»Êý */ +#define IV_BIG_ENDIAN 0 /* ÊÇ·ñÊÇ Big-Endian ×Ö½ÚÐò */ +#define IV_PTR_GRID 4 /* ×î´óÖ¸Õë¶ÔÆëÖµ */ + +#define IV_PTR_PREFIX /* Ö¸ÕëÐÞÊιؼü×Ö(µäÐÍÈ¡ÖµÓÐ near | far, ¿ÉÒÔΪ¿Õ) */ +#define IV_CONST const /* ³£Á¿¹Ø¼ü×Ö(¿ÉÒÔΪ¿Õ) */ +#define IV_EXTERN extern /* Íⲿ¹Ø¼ü×Ö */ +#define IV_STATIC static /* ¾²Ì¬º¯Êý¹Ø¼ü×Ö(¿ÉÒÔΪ¿Õ) */ +#define IV_INLINE __inline /* ÄÚÁª¹Ø¼ü×Ö(µäÐÍÈ¡ÖµÓÐ inline, ¿ÉÒÔΪ¿Õ) */ +#define IV_CALL_STANDARD /* ÆÕͨº¯ÊýÐÞÊιؼü×Ö(µäÐÍÈ¡ÖµÓÐ stdcall | fastcall | pascal, ¿ÉÒÔΪ¿Õ) */ +#define IV_CALL_REENTRANT /* µÝ¹éº¯ÊýÐÞÊιؼü×Ö(µäÐÍÈ¡ÖµÓÐ stdcall | reentrant, ¿ÉÒÔΪ¿Õ) */ +#define IV_CALL_VAR_ARG /* ±ä²Îº¯ÊýÐÞÊιؼü×Ö(µäÐÍÈ¡ÖµÓÐ cdecl, ¿ÉÒÔΪ¿Õ) */ + +#define IV_TYPE_INT8 char /* 8λÊý¾ÝÀàÐÍ */ +#define IV_TYPE_INT16 short /* 16λÊý¾ÝÀàÐÍ */ +#define IV_TYPE_INT24 int /* 24λÊý¾ÝÀàÐÍ */ +#define IV_TYPE_INT32 long /* 32λÊý¾ÝÀàÐÍ */ + +#if 1 /* 48/64 λÊý¾ÝÀàÐÍÊÇ¿ÉÑ¡µÄ, Èç·Ç±ØÒªÔò²»Òª¶¨Òå, ÔÚijЩ 32 λƽ̨ÏÂ, ʹÓÃÄ£ÄⷽʽÌṩµÄ 48/64 λÊý¾ÝÀàÐÍÔËËãЧÂÊºÜµÍ */ +#define IV_TYPE_INT48 long long /* 48λÊý¾ÝÀàÐÍ */ +#define IV_TYPE_INT64 long long /* 64λÊý¾ÝÀàÐÍ */ +#endif + +#define IV_TYPE_ADDRESS long /* µØÖ·Êý¾ÝÀàÐÍ */ +#define IV_TYPE_SIZE long /* ´óСÊý¾ÝÀàÐÍ */ + +#define IV_ANSI_MEMORY 1 /* ÊÇ·ñʹÓà ANSI ÄÚ´æ²Ù×÷¿â */ +#define IV_ANSI_STRING 0 /* ÊÇ·ñʹÓà ANSI ×Ö·û´®²Ù×÷¿â */ + +#define IV_ASSERT(exp) /* ¶ÏÑÔ²Ù×÷(¿ÉÒÔΪ¿Õ) */ +#define IV_YIELD /* ¿ÕÏвÙ×÷(ÔÚЭ×÷ʽµ÷¶ÈϵͳÖÐÓ¦¶¨ÒåΪÈÎÎñÇл»µ÷ÓÃ, ¿ÉÒÔΪ¿Õ) */ +#define IV_TTS_ARM_CODECACHE 0 /* ÊÖ¹¤´úÂëCache */ + +/* TTS¿ª·¢°ü²»Ö§³Öµ÷ÊÔ */ +#define IV_DEBUG 0 /* ÊÇ·ñÖ§³Öµ÷ÊÔ */ + +/* µ÷ÊÔ·½Ê½ÏÂÔòÊä³öÈÕÖ¾ */ +#ifndef IV_LOG + #define IV_LOG IV_DEBUG /* ÊÇ·ñÊä³öÈÕÖ¾ */ +#endif + +/* ÄÚºËÖ§³ÖUnicode´úÂëÒ³²»ÐèÒª±àÒëΪUnicode°æ */ +#if defined(UNICODE) || defined(_UNICODE) + #define IV_UNICODE 1 /* ÊÇ·ñÒÔ Unicode ·½Ê½¹¹½¨ */ +#else + #define IV_UNICODE 0 /* ÊÇ·ñÒÔ Unicode ·½Ê½¹¹½¨ */ +#endif + diff --git a/PLAT/core/tts/include/ivTTS.h b/PLAT/core/tts/include/ivTTS.h new file mode 100644 index 0000000..a4386f1 --- /dev/null +++ b/PLAT/core/tts/include/ivTTS.h @@ -0,0 +1,451 @@ +/*--------------------------------------------------------------+ + | | + | ivTTS.h - AiSound 4 Kernel API | + | | + | Copyright (c) 1999-2008, ANHUI USTC iFLYTEK CO.,LTD. | + | All rights reserved. | + | | + +--------------------------------------------------------------*/ + +#ifndef IFLYTEK_VOICE__TTS__H +#define IFLYTEK_VOICE__TTS__H + + +#include "ivDefine.h" +#include "ivTTSSDKID.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * COMMON DEFINES + */ + +typedef ivUInt16 ivTTSErrID; +typedef ivPointer ivHTTS; + + +/* +* TTS User Info +*/ +typedef struct tagTTSUserInfo ivTTTsUserInfo, ivPtr ivPTTSUserInfo; +struct tagTTSUserInfo +{ + ivPointer pCBLogParameter; /* log callback parameter */ + ivCBLogExt pfnLog; /* write log callback entry */ + ivPointer pCheckoutInfo; /* Checkout Info to TTS */ +}; + +/* + * FUNCTION ENTRIES + */ + /* 返回值:-1:æœåŠ¡å†…部未知异常 + 0:鉴æƒé€šè¿‡ + 1:当å‰åº”ç”¨æ— æŽˆæƒ + 2:应用总授æƒè¶…é™ + 3:当å‰è®¾å¤‡åˆ·æœºæ¬¡æ•°è¶…é™ + 4:当å‰è®¾å¤‡æˆ–应用授æƒå·²è¢«ç¦æ­¢ä½¿ç”¨ + 5:设备å‚数异常或丢失 + 6:数æ®è§£æžå¤±è´¥ï¼Œç§˜é’¥ä¸åŒ¹é… + 7:æœåŠ¡æµæŽ§é™åˆ¶ï¼Œè¯·é€€é¿é‡è¯• + */ +int ivTTS_Auth(void); + +/* get SDK version */ +ivTTSErrID ivCall ivTTS_GetVersion( + ivPUInt8 piMajor, /* [out] major version number */ + ivPUInt8 piMinor, /* [out] minor version number */ + ivPUInt16 piRevision); /* [out] revision number */ + +/* create an instance */ +#define ivTTS_Create(phTTS, pHeap, nHeapSize, pCBParam, pResPackDesc, nResPackCount,pUserInfo) \ +ivTTS_CreateG(phTTS, pHeap, nHeapSize, pCBParam, pResPackDesc, nResPackCount,pUserInfo, AISOUND_SDK_USERID) + +/* create an instance (Decrypt version) */ +#define ivTTS_Create_Decrypt(phTTS, pHeap, nHeapSize, pCBParam, pResPackDesc, nResPackCount,pUserInfo) \ +ivTTS_CreateGecrypt(phTTS, pHeap, nHeapSize, pCBParam, pResPackDesc, nResPackCount,pUserInfo, AISOUND_SDK_USERID) + +ivTTSErrID ivCall ivTTS_CreateGecrypt( + ivHTTS ivPtr phTTS, /* [out] handle to an instance */ + ivPointer pHeap, /* [in] heap for instance */ + ivSize nHeapSize, /* [in] size of the heap */ + ivPointer pCBParam, /* [in] user callback parameter */ + ivPResPackDescExt pResPackDesc, /* [in] resource pack description array */ + ivSize nResPackCount, /* [in] resource pack count */ + ivPTTSUserInfo pUserInfo, /* [in] TTS User Info */ + ivCStrA pUserID); /* [in] SDK ID */ + +ivTTSErrID ivCall ivTTS_CreateG( + ivHTTS ivPtr phTTS, /* [out] handle to an instance */ + ivPointer pHeap, /* [in] heap for instance */ + ivSize nHeapSize, /* [in] size of the heap */ + ivPointer pCBParam, /* [in] user callback parameter */ + ivPResPackDescExt pResPackDesc, /* [in] resource pack description array */ + ivSize nResPackCount, /* [in] resource pack count */ + ivPTTSUserInfo pUserInfo, /* [in] TTS User Info */ + ivCStrA pUserID); /* [in] SDK ID */ + + +/* destroy an instance */ +ivTTSErrID ivCall ivTTS_Destroy( + ivHTTS hTTS ); /* [in] handle to an instance */ + +/* get a parameter associated with an instance */ +ivTTSErrID ivCall ivTTS_GetParam( + ivHTTS hTTS, /* [in] handle to an instance */ + ivUInt32 nParamID, /* [in] parameter ID */ + ivPAddress pnParamValue ); /* [out] buffer to receive the parameter value */ + +/* set a parameter associated with an instance */ +ivTTSErrID ivCall ivTTS_SetParam( + ivHTTS hTTS, /* [in] handle to an instance */ + ivUInt32 nParamID, /* [in] parameter ID */ + ivSize nParamValue ); /* [in] parameter value */ + +/* run an instance and hold current thread's control */ +ivTTSErrID ivCall ivTTS_Run( + ivHTTS hTTS ); /* [in] handle to an instance */ + +/* exit running of an instance and leave current thread's control */ +ivTTSErrID ivCall ivTTS_Exit( + ivHTTS hTTS ); /* [in] handle to an instance */ + +/* synthesize a buffer of text on an instance */ +ivTTSErrID ivCall ivTTS_SynthText( + ivHTTS hTTS, /* [in] handle to an instance */ + ivCPointer pcData, /* [in] pointer of text buffer data to be synthesized */ + ivSize nSize ); /* [in] size of text buffer data to be synthesized */ + +/* begin to synthesize from callback on an instance */ +ivTTSErrID ivCall ivTTS_SynthStart( + ivHTTS hTTS ); /* [in] handle to an instance */ + + +/* + * ERROR CODES + */ + +#define ivTTS_ERR_OK 0x0000 /* success */ +#define ivTTS_ERR_FAILED 0xFFFF /* failed */ + +#define ivTTS_ERR_END_OF_INPUT 0x0001 /* end of input stream */ +#define ivTTS_ERR_EXIT 0x0002 /* exit TTS */ +#define ivTTS_STATE_BASE 0x0100 /* state base */ +#define ivTTS_STATE_INVALID_DATA ivTTS_STATE_BASE + 2 /* invalid data */ +#define ivTTS_STATE_TTS_STOP ivTTS_STATE_BASE + 3 /* TTS stop */ + +#define ivTTS_ERR_BASE 0x8000 /* error number base */ + +#define ivTTS_ERR_UNIMPEMENTED ivTTS_ERR_BASE + 0 /* unimplemented function */ +#define ivTTS_ERR_UNSUPPORTED ivTTS_ERR_BASE + 1 /* unsupported on this platform */ +#define ivTTS_ERR_INVALID_HANDLE ivTTS_ERR_BASE + 2 /* invalid handle */ +#define ivTTS_ERR_INVALID_PARAMETER ivTTS_ERR_BASE + 3 /* invalid parameter(s) */ +#define ivTTS_ERR_INSUFFICIENT_HEAP ivTTS_ERR_BASE + 4 /* insufficient heap size */ +#define ivTTS_ERR_STATE_REFUSE ivTTS_ERR_BASE + 5 /* refuse to do in current state */ +#define ivTTS_ERR_INVALID_PARAM_ID ivTTS_ERR_BASE + 6 /* invalid parameter ID */ +#define ivTTS_ERR_INVALID_PARAM_VALUE ivTTS_ERR_BASE + 7 /* invalid parameter value */ +#define ivTTS_ERR_RESOURCE ivTTS_ERR_BASE + 8 /* Resource is error */ +#define ivTTS_ERR_RESOURCE_READ ivTTS_ERR_BASE + 9 /* read resource error */ +#define ivTTS_ERR_LBENDIAN ivTTS_ERR_BASE + 10 /* the Endian of SDK is error */ +#define ivTTS_ERR_HEADFILE ivTTS_ERR_BASE + 11 /* the HeadFile is different of the SDK */ +#define ivTTS_ERR_SIZE_EXCEED_BUFFER ivTTS_ERR_BASE + 12 /* get data size exceed the data buffer */ +#define ivTTS_ERR_RESOURCE_LICENSE ivTTS_ERR_BASE + 13 /* some Resources haven't license */ + + +/* + * INSTANCE PARAMETERS + */ + +/* constants for values of field nParamID */ +#define ivTTS_PARAM_PARAMCH_CALLBACK 0x00000000 /* parameter change callback entry */ +#define ivTTS_PARAM_LANGUAGE 0x00000100 /* language, e.g. Chinese */ +#define ivTTS_PARAM_INPUT_CODEPAGE 0x00000101 /* input code page, e.g. GBK */ +#define ivTTS_PARAM_TEXT_MARK 0x00000102 /* text mark, e.g. CSSML */ +#define ivTTS_PARAM_USE_PROMPTS 0x00000104 /* whether use prompts */ +#define ivTTS_PARAM_RECOGNIZE_PHONEME 0x00000105 /* how to recognize phoneme input */ +#define ivTTS_PARAM_INPUT_MODE 0x00000200 /* input mode, e.g. from fixed buffer, from callback */ +#define ivTTS_PARAM_INPUT_TEXT_BUFFER 0x00000201 /* input text buffer */ +#define ivTTS_PARAM_INPUT_TEXT_SIZE 0x00000202 /* input text size */ +#define ivTTS_PARAM_INPUT_CALLBACK 0x00000203 /* input callback entry */ +#define ivTTS_PARAM_PROGRESS_BEGIN 0x00000204 /* current processing position */ +#define ivTTS_PARAM_PROGRESS_LENGTH 0x00000205 /* current processing length */ +#define ivTTS_PARAM_PROGRESS_CALLBACK 0x00000206 /* progress callback entry */ +#define ivTTS_PARAM_READ_AS_NAME 0x00000301 /* whether read as name */ +#define ivTTS_PARAM_READ_DIGIT 0x00000302 /* how to read digit, e.g. read as number, read as value */ +#define ivTTS_PARAM_CHINESE_NUMBER_1 0x00000303 /* how to read number "1" in Chinese */ +#define ivTTS_PARAM_MANUAL_PROSODY 0x00000304 /* whether use manual prosody */ +#define ivTTS_PARAM_ENGLISH_NUMBER_0 0x00000305 /* how to read number "0" in Englsih */ +#define ivTTS_PARAM_READ_WORD 0x00000306 /* how to read word in Englsih, e.g. read by word, read as alpha */ +#define ivTTS_PARAM_OUTPUT_CALLBACK 0x00000401 /* output callback entry */ +#define ivTTS_PARAM_ROLE 0x00000500 /* speaker role */ +#define ivTTS_PARAM_SPEAK_STYLE 0x00000501 /* speak style */ +#define ivTTS_PARAM_VOICE_SPEED 0x00000502 /* voice speed */ +#define ivTTS_PARAM_VOICE_PITCH 0x00000503 /* voice tone */ +#define ivTTS_PARAM_VOLUME 0x00000504 /* volume value */ +#define ivTTS_PARAM_CHINESE_ROLE 0x00000510 /* Chinese speaker role */ +#define ivTTS_PARAM_ENGLISH_ROLE 0x00000511 /* English speaker role */ +#define ivTTS_PARAM_VEMODE 0x00000600 /* voice effect - predefined mode */ +#define ivTTS_PARAM_USERMODE 0x00000701 /* user's mode */ +#define ivTTS_PARAM_NAVIGATION_MODE 0x00000701 /* Navigation Version*/ + +#define ivTTS_PARAM_EVENT_CALLBACK 0x00001001 /* sleep callback entry */ +#define ivTTS_PARAM_OUTPUT_BUF 0x00001002 /* output buffer */ +#define ivTTS_PARAM_OUTPUT_BUFSIZE 0x00001003 /* output buffer size */ +#define ivTTS_PARAM_DELAYTIME 0x00001004 /* delay time */ + + +/* constants for values of parameter ivTTS_PARAM_LANGUAGE */ +#define ivTTS_LANGUAGE_AUTO 0 /* Detect language automatically */ +#define ivTTS_LANGUAGE_CHINESE 1 /* Chinese (with English) */ +#define ivTTS_LANGUAGE_ENGLISH 2 /* English */ + +/* constants for values of parameter ivTTS_PARAM_INPUT_CODEPAGE */ +#define ivTTS_CODEPAGE_ASCII 437 /* ASCII */ +#define ivTTS_CODEPAGE_GBK 936 /* GBK (default) */ +#define ivTTS_CODEPAGE_BIG5 950 /* Big5 */ +#define ivTTS_CODEPAGE_UTF16LE 1200 /* UTF-16 little-endian */ +#define ivTTS_CODEPAGE_UTF16BE 1201 /* UTF-16 big-endian */ +#define ivTTS_CODEPAGE_UTF8 65001 /* UTF-8 */ +#define ivTTS_CODEPAGE_GB2312 ivTTS_CODEPAGE_GBK +#define ivTTS_CODEPAGE_GB18030 ivTTS_CODEPAGE_GBK +#if IV_BIG_ENDIAN +#define ivTTS_CODEPAGE_UTF16 ivTTS_CODEPAGE_UTF16BE +#else +#define ivTTS_CODEPAGE_UTF16 ivTTS_CODEPAGE_UTF16LE +#endif +#define ivTTS_CODEPAGE_UNICODE ivTTS_CODEPAGE_UTF16 +#define ivTTS_CODEPAGE_PHONETIC_PLAIN 23456 /* Kingsoft Phonetic Plain */ + +/* constants for values of parameter ivTTS_PARAM_TEXT_MARK */ +#define ivTTS_TEXTMARK_NONE 0 /* none */ +#define ivTTS_TEXTMARK_SIMPLE_TAGS 1 /* simple tags (default) */ + +/* constants for values of parameter ivTTS_PARAM_INPUT_MODE */ +#define ivTTS_INPUT_FIXED_BUFFER 0 /* from fixed buffer */ +#define ivTTS_INPUT_CALLBACK 1 /* from callback */ + +/* constants for values of parameter ivTTS_PARAM_READ_DIGIT */ +#define ivTTS_READDIGIT_AUTO 0 /* decide automatically (default) */ +#define ivTTS_READDIGIT_AS_NUMBER 1 /* say digit as number */ +#define ivTTS_READDIGIT_AS_VALUE 2 /* say digit as value */ + +/* constants for values of parameter ivTTS_PARAM_CHINESE_NUMBER_1 */ +#define ivTTS_CHNUM1_READ_YAO 0 /* read number "1" [yao1] in chinese (default) */ +#define ivTTS_CHNUM1_READ_YI 1 /* read number "1" [yi1] in chinese */ + +/* constants for values of parameter ivTTS_PARAM_ENGLISH_NUMBER_0 */ +#define ivTTS_ENNUM0_READ_ZERO 0 /* read number "0" [zero] in english (default) */ +#define ivTTS_ENNUM0_READ_O 1 /* read number "0" [o] in englsih */ + +/* constants for values of parameter ivTTS_PARAM_SPEAKER */ +#define ivTTS_ROLE_TIANCHANG 1 /* Tianchang (female, Chinese) */ +#define ivTTS_ROLE_WENJING 2 /* Wenjing (female, Chinese) */ +#define ivTTS_ROLE_XIAOYAN 3 /* Xiaoyan (female, Chinese) */ +#define ivTTS_ROLE_YANPING 3 /* Xiaoyan (female, Chinese) */ +#define ivTTS_ROLE_XIAOFENG 4 /* Xiaofeng (male, Chinese) */ +#define ivTTS_ROLE_YUFENG 4 /* Xiaofeng (male, Chinese) */ +#define ivTTS_ROLE_SHERRI 5 /* Sherri (female, US English) */ +#define ivTTS_ROLE_XIAOJIN 6 /* Xiaojin (female, Chinese) */ +#define ivTTS_ROLE_NANNAN 7 /* Nannan (child, Chinese) */ +#define ivTTS_ROLE_JINGER 8 /* Jinger (female, Chinese) */ +#define ivTTS_ROLE_JIAJIA 9 /* Jiajia (girl, Chinese) */ +#define ivTTS_ROLE_YUER 10 /* Yuer (female, Chinese) */ +#define ivTTS_ROLE_XIAOQIAN 11 /* Xiaoqian (female, Chinese Northeast) */ +#define ivTTS_ROLE_LAOMA 12 /* Laoma (male, Chinese) */ +#define ivTTS_ROLE_BUSH 13 /* Bush (male, US English) */ +#define ivTTS_ROLE_XIAORONG 14 /* Xiaorong (female, Chinese Szechwan) */ +#define ivTTS_ROLE_XIAOMEI 15 /* Xiaomei (female, Cantonese) */ +#define ivTTS_ROLE_ANNI 16 /* Anni (female, Chinese) */ +#define ivTTS_ROLE_JOHN 17 /* John (male, US English) */ +#define ivTTS_ROLE_ANITA 18 /* Anita (female, British English) */ +#define ivTTS_ROLE_TERRY 19 /* Terry (female, US English) */ +#define ivTTS_ROLE_CATHERINE 20 /* Catherine (female, US English) */ +#define ivTTS_ROLE_TERRYW 21 /* Terry (female, US English Word) */ +#define ivTTS_ROLE_XIAOLIN 22 /* Xiaolin (female, Chinese) */ +#define ivTTS_ROLE_XIAOMENG 23 /* Xiaomeng (female, Chinese) */ +#define ivTTS_ROLE_XIAOQIANG 24 /* Xiaoqiang (male, Chinese) */ +#define ivTTS_ROLE_XIAOKUN 25 /* XiaoKun (male, Chinese) */ +#define ivTTS_ROLE_JIUXU 51 /* Jiu Xu (male, Chinese) */ +#define ivTTS_ROLE_DUOXU 52 /* Duo Xu (male, Chinese) */ +#define ivTTS_ROLE_XIAOPING 53 /* Xiaoping (female, Chinese) */ +#define ivTTS_ROLE_DONALDDUCK 54 /* Donald Duck (male, Chinese) */ +#define ivTTS_ROLE_BABYXU 55 /* Baby Xu (child, Chinese) */ +#define ivTTS_ROLE_DALONG 56 /* Dalong (male, Cantonese) */ +#define ivTTS_ROLE_TOM 57 /* Tom (male, US English) */ +#define ivTTS_ROLE_USER 99 /* user defined */ + +/* constants for values of parameter ivTTS_PARAM_SPEAK_STYLE */ +#define ivTTS_STYLE_PLAIN 0 /* plain speak style */ +#define ivTTS_STYLE_NORMAL 1 /* normal speak style (default) */ + +/* constants for values of parameter ivTTS_PARAM_VOICE_SPEED */ +/* the range of voice speed value is from -32768 to +32767 */ +#define ivTTS_SPEED_MIN -32768 /* slowest voice speed */ +#define ivTTS_SPEED_NORMAL 0 /* normal voice speed (default) */ +#define ivTTS_SPEED_MAX +32767 /* fastest voice speed */ + +/* constants for values of parameter ivTTS_PARAM_VOICE_PITCH */ +/* the range of voice tone value is from -32768 to +32767 */ +#define ivTTS_PITCH_MIN -32768 /* lowest voice tone */ +#define ivTTS_PITCH_NORMAL 0 /* normal voice tone (default) */ +#define ivTTS_PITCH_MAX +32767 /* highest voice tone */ + +/* constants for values of parameter ivTTS_PARAM_VOLUME */ +/* the range of volume value is from -32768 to +32767 */ +#define ivTTS_VOLUME_MIN -32768 /* minimized volume */ +#define ivTTS_VOLUME_NORMAL 0 /* normal volume */ +#define ivTTS_VOLUME_MAX +32767 /* maximized volume (default) */ + +/* constants for values of parameter ivTTS_PARAM_VEMODE */ +#define ivTTS_VEMODE_NONE 0 /* none */ +#define ivTTS_VEMODE_WANDER 1 /* wander */ +#define ivTTS_VEMODE_ECHO 2 /* echo */ +#define ivTTS_VEMODE_ROBERT 3 /* robert */ +#define ivTTS_VEMODE_CHROUS 4 /* chorus */ +#define ivTTS_VEMODE_UNDERWATER 5 /* underwater */ +#define ivTTS_VEMODE_REVERB 6 /* reverb */ +#define ivTTS_VEMODE_ECCENTRIC 7 /* eccentric */ + +/* constants for values of parameter ivTTS_PARAM_USERMODE(ivTTS_PARAM_NAVIGATION_MODE) */ +#define ivTTS_USE_NORMAL 0 /* synthesize in the Mode of Normal */ +#define ivTTS_USE_NAVIGATION 1 /* synthesize in the Mode of Navigation */ +#define ivTTS_USE_MOBILE 2 /* synthesize in the Mode of Mobile */ +#define ivTTS_USE_EDUCATION 3 /* synthesize in the Mode of Education */ + +/* constants for values of parameter ivTTS_PARAM_READ_WORD */ +#define ivTTS_READWORD_BY_WORD 2 /* say words by the way of word */ +#define ivTTS_READWORD_BY_ALPHA 1 /* say words by the way of alpha */ +#define ivTTS_READWORD_BY_AUTO 0 /* say words by the way of auto */ + +/* parameter change callback type */ +typedef ivTTSErrID (ivProc ivTTSCB_ParamChange)( + ivPointer pParameter, /* [in] user callback parameter */ + ivUInt32 nParamID, /* [in] parameter ID */ + ivUInt32 nParamValue ); /* [in] parameter value */ + +/* progress callback type */ +typedef ivTTSErrID (ivProc ivTTSCB_Progress)( + ivPointer pParameter, /* [in] user callback parameter */ + ivUInt32 iProcBegin, /* [in] current processing position */ + ivUInt32 nProcLen ); /* [in] current processing length */ + +/* input callback type */ +typedef ivTTSErrID (ivProc ivTTSCB_Input)( + ivPointer pParameter, /* [in] user callback parameter */ + ivPointer pText, /* [out] input text buffer */ + ivSize ivPtr pnSize ); /* [in/out] input text size */ + +/* output callback type */ +typedef ivTTSErrID (ivProc ivTTSCB_Output)( + ivPointer pParameter, /* [in] user callback parameter */ + ivUInt16 nCode, /* [in] output data code */ + ivCPointer pcData, /* [in] output data buffer */ + ivSize nSize ); /* [in] output data size */ + +/* parameter change callback type */ +typedef ivTTSErrID (ivProc ivTTSCB_Event)( + ivPointer pParameter, /* [in] user callback parameter */ + ivUInt32 nEventID, /* [in] parameter ID */ + ivUInt32 nValue ); /* [in] parameter value */ + + +/* constants for values of parameter nEventID */ +#define ivTTS_EVENT_SLEEP 0x0100 /* sleep */ +#define ivTTS_EVENT_PLAYSTART 0x0101 /* start playing */ +#define ivTTS_EVENT_SWITCHCONTEXT 0x0102 /* context switch */ + +/* constants for values of parameter wCode */ +#define ivTTS_CODE_PCM8K16B 0x0208 /* PCM 8K 16bit */ +#define ivTTS_CODE_PCM11K16B 0x020B /* PCM 11K 16bit */ +#define ivTTS_CODE_PCM16K16B 0x0210 /* PCM 16K 16bit */ + +/* + * PARAMETER STRUCTURES + */ + +/* parameters for voice effect amplify */ +typedef struct tagIsTTSVEAmplifyParam TIsTTSVEAmplifyParam; + +struct tagIsTTSVEAmplifyParam +{ + ivUInt16 m_nPeriod; /* 1-2000ms */ + ivUInt8 m_fAmpMin; /* 0-100% */ + ivUInt8 m_fAmpMax; /* 0-100% */ +}; + + +/* parameters for voice effect echo */ +typedef struct tagIsTTSVEEchoParam TIsTTSVEEchoParam; + +struct tagIsTTSVEEchoParam +{ + ivUInt8 m_fInitDecay; /* 0-100% */ + ivUInt8 m_fDecay; /* 0-100% */ + ivUInt16 m_nDelay; /* 1-2000ms */ +}; + + +/* parameters for voice effectVE reverb */ +typedef struct tagIsTTSVEReverbParam TIsTTSVEReverbParam; + +struct tagIsTTSVEReverbParam +{ + ivUInt8 m_fInitDecay; /* 0-100% */ + ivUInt8 m_nFilters; /* 1-16 */ + ivUInt8 m_fDecay[16]; /* 0-100% */ + ivUInt8 m_nDelay[16]; /* 1-100ms */ +}; + + +/* parameters for voice effect chrous */ +typedef struct tagIsTTSVEChrousParam TIsTTSVEChrousParam; + +struct tagIsTTSVEChrousParam +{ + ivUInt8 m_fInitDecay; /* 0-100% */ + ivUInt8 m_fInitRatio; /* 0-100% */ + ivUInt8 m_nDelayMin; /* 1-40ms */ + ivUInt8 m_nDelayMax; /* 1-40ms */ + ivUInt8 m_nFilters; /* 1-16 */ + ivUInt8 m_nFilterFreq; /* 1-50Hz */ + ivUInt8 m_nFilterFreqDelta; /* 1-50Hz */ +}; + + +/* parameters for voice effect pitch */ +typedef struct tagIsTTSVEPitchParam TIsTTSVEPitchParam; + +struct tagIsTTSVEPitchParam +{ + ivUInt8 m_fDeltaPitch; /* 0-90% */ + ivUInt16 m_nPeriod; /* 1-20000ms */ +}; + + +/* get pcm data */ +ivTTSErrID ivCall ivTTS_GetData( + ivHTTS hTTS, /* [in] handle to an instance */ + ivPointer pData, /* [in] pointer of pcm data buffer */ + ivSize ivPtr pSize ); /* [in/out] data size */ + +/* Label text with symbol */ +ivTTSErrID ivCall ivTTS_SymbolLabel( + ivHTTS hTTS, /* [in] handle to an instance */ + ivCPointer pText, /* [in] pointer of the text buffer */ + ivSize nTextLen, /* [in] size of the text buffer */ + ivCPointer pSymbol, /* [in] pointer of the symbol buffer */ + ivSize nSymbolLen, /* [in] size of the symbol buffer */ + ivPointer pOut, /* [out] pointer of the output buffer */ + ivPUInt32 pnOutLen, /* [in], max size of the output buffer,[out] actually used size of the output buffer */ + ivBool bTone /* [in], if the symbols have tone */ + ); + +#ifdef __cplusplus +} +#endif + + +#endif /* !IFLYTEK_VOICE__TTS__H */ + diff --git a/PLAT/core/tts/include/ivTTSSDKID_all.h b/PLAT/core/tts/include/ivTTSSDKID_all.h new file mode 100644 index 0000000..74386e9 --- /dev/null +++ b/PLAT/core/tts/include/ivTTSSDKID_all.h @@ -0,0 +1,9 @@ + +/* SDK ID */ + +#ifndef AISOUND_5_0_SDK_CONSISTENCE_ALL_H +#define AISOUND_5_0_SDK_CONSISTENCE_ALL_H +#define AISOUND_SDK_USERID_16K ((ivCStrA)"\x65\x37\x38\x38\x66\x63\x33\x66\x35\x39\x32\x63\x34\x63\x36\x61\x61\x39\x62\x33\x36\x64\x32\x62\x36\x36\x65\x61\x38\x33\x31\x31") +#define AISOUND_SDK_USERID_8K ((ivCStrA)"\x65\x33\x32\x36\x35\x39\x63\x30\x61\x39\x34\x32\x34\x30\x38\x61\x39\x65\x66\x65\x66\x61\x61\x66\x30\x32\x39\x62\x65\x65\x32\x00") + +#endif /* !AISOUND_SDK_CONSISTENCE__H */ diff --git a/PLAT/device/target/board/common/ARMCM3/inc/arm_math.h b/PLAT/device/target/board/common/ARMCM3/inc/arm_math.h new file mode 100644 index 0000000..4be7e8c --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/arm_math.h @@ -0,0 +1,7226 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_math.h + * Description: Public header file for CMSIS DSP Library + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library + * on ARMv8M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( + q31_t data); + + CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if (x > 0) + { + posMax = (posMax - 1); + + if (x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if (x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#if 0 + /* + * @brief C custom defined PKHBT for unavailable DSP extension + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT( + uint32_t x, + uint32_t y, + uint32_t leftshift) + { + return ( ((x ) & 0x0000FFFFUL) | + ((y << leftshift) & 0xFFFF0000UL) ); + } + + /* + * @brief C custom defined PKHTB for unavailable DSP extension + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB( + uint32_t x, + uint32_t y, + uint32_t rightshift) + { + return ( ((x ) & 0xFFFF0000UL) | + ((y >> rightshift) & 0x0000FFFFUL) ); + } +#endif + +/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armcc.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armcc.h new file mode 100644 index 0000000..1d96b98 --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armcc.h @@ -0,0 +1,815 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (ARM compiler V5) header file + * @version V5.0.2 + * @date 13. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ +#define __enable_irq() __set_PRIMASK(0) + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ +#define __disable_irq() __set_PRIMASK(1) + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armclang.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armclang.h new file mode 100644 index 0000000..2148297 --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armclang.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file + * @version V5.0.3 + * @date 27. March 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for ARM Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +/* #define __get_FPSCR __builtin_arm_get_fpscr */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +/* #define __set_FPSCR __builtin_arm_set_fpscr */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_compiler.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_compiler.h new file mode 100644 index 0000000..28b8a07 --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_compiler.h @@ -0,0 +1,361 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.2 + * @date 13. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif + #define __GET_RETURN_ADDRESS() __return_address() + +/* + * ARM Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" +#ifndef __FORCEINLINE + + #define __FORCEINLINE __attribute__((always_inline)) inline + +#endif + #define __GET_RETURN_ADDRESS() __builtin_return_address(0) + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include + + /* CMSIS compiler control architecture macros */ + #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) + #ifndef __ARM_ARCH_6M__ + #define __ARM_ARCH_6M__ 1 + #endif + #elif (__CORE__ == __ARM7M__) + #ifndef __ARM_ARCH_7M__ + #define __ARM_ARCH_7M__ 1 + #endif + #elif (__CORE__ == __ARM7EM__) + #ifndef __ARM_ARCH_7EM__ + #define __ARM_ARCH_7EM__ 1 + #endif + #endif + + #ifndef __NO_RETURN + #define __NO_RETURN __noreturn + #endif + #ifndef __USED + #define __USED __root + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION __packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + __packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + // Workaround for missing __CLZ intrinsic in + // various versions of the IAR compilers. + // __IAR_FEATURE_CLZ__ should be defined by + // the compiler that supports __CLZ internally. + #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__)) + __STATIC_INLINE uint32_t __CLZ(uint32_t data) + { + if (data == 0u) { return 32u; } + + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } + #endif + + +/* + * TI ARM Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_gcc.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_gcc.h new file mode 100644 index 0000000..04d9fac --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_gcc.h @@ -0,0 +1,1991 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.2 + * @date 13. February 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (SP). + \return SP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP(void) +{ + register uint32_t result; + + __ASM volatile ("MOV %0, r13" : "=r" (result) ); + return(result); +} + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ + (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +//{ +// __ASM volatile ("nop"); +//} +#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +//{ +// __ASM volatile ("wfi"); +//} +#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +//{ +// __ASM volatile ("wfe"); +//} +#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +//{ +// __ASM volatile ("sev"); +//} +#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_version.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_version.h new file mode 100644 index 0000000..d458a6c --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/PLAT/device/target/board/common/ARMCM3/inc/commontypedef.h b/PLAT/device/target/board/common/ARMCM3/inc/commontypedef.h new file mode 100644 index 0000000..b733141 --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/commontypedef.h @@ -0,0 +1,123 @@ + +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: CommonTypedef.h + * Description: Common type define file + * History: 08/23/2017 Originated by Yunfei Li + * + ****************************************************************************/ + +#ifndef _COMMON_TYPEDEF_H +#define _COMMON_TYPEDEF_H + +#ifndef PHY_PC_SIM +#include "cmsis_compiler.h" +#else +#define __FORCEINLINE __inline +typedef unsigned long uint32_t; + +#endif + +//#define PUBLIC_CMCC_EDRX_DEBUG 1 + +/***************************************************************************** + armcc definition + +char 8 1 (byte-aligned) 0 to 255 (unsigned) by default. + C128 to 127 (signed) when compiled with + --signed_chars. +signed char 8 1 (byte-aligned) ¨C128 to 127 +unsigned char 8 1 (byte-aligned) 0 to 255 +(signed) short 16 2 (halfword-aligned) ¨C32,768 to 32,767 +unsigned short 16 2 (halfword-aligned) 0 to 65,535 +(signed) int 32 4 (word-aligned) ¨C2,147,483,648 to 2,147,483,647 +unsigned int 32 4 (word-aligned) 0 to 4,294,967,295 +(signed) long 32 4 (word-aligned) ¨C2,147,483,648 to 2,147,483,647 +unsigned long 32 4 (word-aligned) 0 to 4,294,967,295 +(signed) long long 64 8 (doubleword-aligned) ¨C9,223,372,036,854,775,808 to 9,223,372,036,854,775,807 +unsigned long long 64 8 (doubleword-aligned) 0 to 18,446,744,073,709,551,615 +float 32 4 (word-aligned) 1.175494351e-38 to 3.40282347e+38 (normalized values) +double 64 8 (doubleword-aligned) 2.22507385850720138e-308 to 1.79769313486231571e + +308 (normalized values) +long double 64 8 (doubleword-aligned) 2.22507385850720138e-308 to 1.79769313486231571e + +308 (normalized values) +wchar_t 16 2 (halfword-aligned) 0 to 65,535 by default. + 32 4 (word-aligned) 0 to 4,294,967,295 when compiled with --wchar32. + +All pointers 32 4 (word-aligned) Not applicable. +bool (C++ only) 8 1 (byte-aligned) false or true +_Bool (C only) 8 1 (byte-aligned) false or true +*****************************************************************************/ + +//#define VC_VERSION /* defined for windows, if undefined, unix or linux */ + +#ifndef VC_VERSION +typedef signed char INT8; +typedef unsigned char UINT8; + +typedef signed short INT16; +typedef unsigned short UINT16; + +typedef signed long INT32; +typedef unsigned long UINT32; + +typedef long long INT64; +typedef unsigned long long UINT64; + +#if (!defined PHY_PC_SIM)||(!defined PHY_PC_UNILOG) +typedef unsigned char BOOL; +#else +#define BOOL UINT8 +#endif + +typedef char CHAR; +#else +typedef signed char INT8; +typedef unsigned char UINT8; + +typedef signed short INT16; +typedef unsigned short UINT16; + +typedef signed long INT32; +typedef unsigned long UINT32; + +typedef __int64 INT64; +typedef unsigned __int64 UINT64; + +typedef unsigned char BOOL; +typedef char CHAR; +#endif //#ifndef VC_VERSION + +typedef void ( *PhyCBFunc_T )(void* sigBody); + +typedef struct +{ + INT32 integer; + INT32 fwl; +} DCXODouble; + + +#ifndef FALSE +#define FALSE ((BOOL)0) +#endif + +#ifndef TRUE +#define TRUE ((BOOL)1) +#endif + + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef PNULL +#define PNULL ((void*) NULL) +#endif + +#ifndef PPNULL +#define PPNULL ((void*)((void*) NULL)) +#endif + +#endif //#ifndef _COMMON_TYPEDEF_H + diff --git a/PLAT/device/target/board/common/ARMCM3/inc/core_cm3.h b/PLAT/device/target/board/common/ARMCM3/inc/core_cm3.h new file mode 100644 index 0000000..2bf2faf --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/core_cm3.h @@ -0,0 +1,1958 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + + +__STATIC_INLINE uint32_t SysTick_32KSetup(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL =SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +__STATIC_INLINE uint32_t SysTick_Get_CurrentVal() +{ + + return SysTick->VAL; +} + + +__STATIC_INLINE uint32_t SysTick_Disable() +{ + + SysTick->CTRL =0; + return 0; +} + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/PLAT/device/target/board/common/ARMCM3/inc/mpu_armv7.h b/PLAT/device/target/board/common/ARMCM3/inc/mpu_armv7.h new file mode 100644 index 0000000..e6420b3 --- /dev/null +++ b/PLAT/device/target/board/common/ARMCM3/inc/mpu_armv7.h @@ -0,0 +1,182 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for ARMv7 MPU + * @version V5.0.2 + * @date 09. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0u +#define ARM_MPU_AP_PRIV 1u +#define ARM_MPU_AP_URO 2u +#define ARM_MPU_AP_FULL 3u +#define ARM_MPU_AP_PRO 5u +#define ARM_MPU_AP_RO 6u + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos)) + +/** +* MPU Region Attribut and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + ((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + ((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + ((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + ((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + ((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + ((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + ((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + ((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk) + + +/** +* Struct for a single MPU Region +*/ +typedef struct _ARM_MPU_Region_t { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + //SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable() +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0u; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0u; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u); +} + +#endif diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash.ld b/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash.ld new file mode 100644 index 0000000..852da0c --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash.ld @@ -0,0 +1,291 @@ +ENTRY(Reset_Handler) +MEMORY +{ + ASMB_AREA(rwx) : ORIGIN = 0x00000000, LENGTH = 0x010000 + MSMB_AREA(rwx) : ORIGIN = 0x00400000, LENGTH = 0x140000 + FLASH_AREA(rx) : ORIGIN = 0x00824000, LENGTH = 2944K +} +SECTIONS +{ + . = (0x00824000); + .vector : + { + KEEP(*(.isr_vector)) + } >FLASH_AREA + .cache : ALIGN(128) + { + Image$$UNLOAD_NOCACHE$$Base = .; + *cache.o(.text*) + } >FLASH_AREA + .load_bootcode 0x0 : + { + . = ALIGN(4); + Load$$LOAD_BOOTCODE$$Base = LOADADDR(.load_bootcode); + Image$$LOAD_BOOTCODE$$Base = .; + KEEP(*(.mcuVector)) + *(.ramBootCode) + *qspi.o(.text*) + *flash.o(.text*) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_BOOTCODE$$Length = SIZEOF(.load_bootcode); + .load_ap_piram_asmb 0x1000 : + { + . = ALIGN(4); + Load$$LOAD_AP_PIRAM_ASMB$$Base = LOADADDR(.load_ap_piram_asmb); + Image$$LOAD_AP_PIRAM_ASMB$$Base = .; + *(.psPARamcode) + *(.platPARamcode) + *memset.o(.text*) + *memcpy-armv7m.o(.text*) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_PIRAM_ASMB$$Length = SIZEOF(.load_ap_piram_asmb); + .load_ap_firam_asmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FIRAM_ASMB$$Base = LOADADDR(.load_ap_firam_asmb); + Image$$LOAD_AP_FIRAM_ASMB$$Base = .; + *(.psFARamcode) + *(.platFARamcode) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_FIRAM_ASMB$$Length = SIZEOF(.load_ap_firam_asmb); + .load_ap_rwdata_asmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ap_rwdata_asmb); + Image$$LOAD_AP_FDATA_ASMB$$RW$$Base = .; + *(.platFARWData) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_FDATA_ASMB$$Length = SIZEOF(.load_ap_rwdata_asmb); + .load_ps_rwdata_asmb : ALIGN(4) + { + Load$$LOAD_PS_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ps_rwdata_asmb); + Image$$LOAD_PS_FDATA_ASMB$$RW$$Base = .; + *(.psFARWData) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_PS_FDATA_ASMB$$RW$$Length = SIZEOF(.load_ps_rwdata_asmb); + .load_ap_zidata_asmb (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_AP_FDATA_ASMB$$ZI$$Base = .; + *(.platFAZIData) + . = ALIGN(4); + Image$$LOAD_AP_FDATA_ASMB$$ZI$$Limit = .; + Image$$LOAD_PS_FDATA_ASMB$$ZI$$Base = .; + *(.psFAZIData) + . = ALIGN(4); + Image$$LOAD_PS_FDATA_ASMB$$ZI$$Limit = .; + *(.exceptCheck) + } >ASMB_AREA + .load_rrcmem 0xB000 (NOLOAD): + { + *(.rrcMem) + } >ASMB_AREA + .load_flashmem 0xC000 (NOLOAD): + { + *(.apFlashMem) + } >ASMB_AREA + .load_ap_piram_msmb (0x00400000) : + { + . = ALIGN(4); + Load$$LOAD_AP_PIRAM_MSMB$$Base = LOADADDR(.load_ap_piram_msmb); + Image$$LOAD_AP_PIRAM_MSMB$$Base = .; + *(.psPMRamcode) + *(.platPMRamcode) + *(.platPMRamcodeFCLK) + *(.recordNodeRO) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_PIRAM_MSMB$$Length = SIZEOF(.load_ap_piram_msmb); + .load_ap_firam_msmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FIRAM_MSMB$$Base = LOADADDR(.load_ap_firam_msmb); + Image$$LOAD_AP_FIRAM_MSMB$$Base = .; + *(.ramCode2) + *(.upRamCode) + *(.psFMRamcode) + *(.platFMRamcode) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_FIRAM_MSMB$$Length = SIZEOF(.load_ap_firam_msmb); + .load_apos : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_APOS$$Base = LOADADDR(.load_apos); + Image$$LOAD_APOS$$Base = .; + *event_groups.o(.text*) + *heap_6.o(.text*) + *tlsf.o(.text*) + *list.o(.text*) + *queue.o(.text*) + *tasks.o(.text*) + *timers.o(.text*) + *port.o(.text*) + *port_asm.o(.text*) + *cmsis_os2.o(.text*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + Image$$LOAD_APOS$$Length = SIZEOF(.load_apos); + .load_dram_bsp : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_DRAM_BSP$$Base = LOADADDR(.load_dram_bsp); + Image$$LOAD_DRAM_BSP$$Base = .; + *bsp_spi.o(.data*) + *flash.o(.data*) + *flash_rt.o(.data*) + *gpr.o(.data*) + *apmu.o(.data*) + *apmuTiming.o(.data*) + *bsp.o(.data*) + *plat_config.o(.data*) + *system_ec618.o(.data*) + *unilog.o(.data*) + *pad.o(.data*) + *ic.o(.data*) + *ec_main.o(.data*) + *slpman.o(.data*) + *bsp_usart.o(.data*) + *bsp_lpusart.o(.data*) + *timer.o(.data*) + *dma.o(.data*) + *adc.o(.data*) + *wdt.o(.data*) + *usb_device.o(.data*) + *uart_device.o(.data*) + *clock.o(.data*) + *hal_adcproxy.o(.data*) + *hal_alarm.o(.data*) + *exception_process.o(.data*) + *exception_dump.o(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + Image$$LOAD_DRAM_BSP$$Length = SIZEOF(.load_dram_bsp); + .load_dram_bsp_zi (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_DRAM_BSP$$ZI$$Base = .; + *bsp_spi.o(.bss*) + *flash.o(.bss*) + *flash_rt.o(.bss*) + *gpr.o(.bss*) + *apmu.o(.bss*) + *apmuTiming.o(.bss*) + *bsp.o(.bss*) + *plat_config.o(.bss*) + *system_ec618.o(.bss*) + *unilog.o(.bss*) + *pad.o(.bss*) + *ic.o(.bss*) + *ec_main.o(.bss*) + *slpman.o(.bss*) + *bsp_usart.o(.bss*) + *bsp_lpusart.o(.bss*) + *timer.o(.bss*) + *dma.o(.bss*) + *adc.o(.bss*) + *wdt.o(.bss*) + *usb_device.o(.bss*) + *uart_device.o(.bss*) + *clock.o(.bss*) + **hal_trim.o(.bss*) + *hal_adcproxy.o(.bss*) + *hal_alarm.o(.bss*) + *exception_process.o(.bss*) + *exception_dump.o(.bss*) + *(.recordNodeZI) + . = ALIGN(4); + Image$$LOAD_DRAM_BSP$$ZI$$Limit = .; + } >MSMB_AREA + .unload_slpmem (NOLOAD): + { + *(.sleepmem) + } >MSMB_AREA + .load_dram_shared : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_DRAM_SHARED$$Base = LOADADDR(.load_dram_shared); + Image$$LOAD_DRAM_SHARED$$Base = .; + *(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + Image$$LOAD_DRAM_SHARED$$Length = SIZEOF(.load_dram_shared); + .load_dram_shared_zi (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_DRAM_SHARED$$ZI$$Base = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + *(.stack) + Image$$LOAD_DRAM_SHARED$$ZI$$Limit = .; + *(.USB_NOINIT_DATA_BUF) + } >MSMB_AREA + PROVIDE(end_ap_data = . ); + PROVIDE(start_up_buffer = 0x499000); + .load_up_buffer start_up_buffer(NOLOAD): + { + *(.catShareBuf) + Image$$LOAD_UP_BUFFER$$Limit = .; + } >MSMB_AREA + PROVIDE(end_up_buffer = . ); + heap_size = start_up_buffer - end_ap_data; + ASSERT(heap_size>=0x20000,"ap use too much ram, heap less than min_heap_size_threshold!") + ASSERT(end_up_buffer<=(0x00500000),"ap use too much ram, exceed to MSMB_APMEM_END_ADDR") + .text : + { + *(.rodata*) + *(.text*) + } >FLASH_AREA + .preinit_fun_array : + { + . = ALIGN(4); + __preinit_fun_array_start = .; + KEEP (*(SORT(.preinit_fun_array.*))) + KEEP (*(.preinit_fun_array*)) + __preinit_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + .init_fun_array : + { + . = ALIGN(4); + __init_fun_array_start = .; + KEEP (*(SORT(.init_fun_array.*))) + KEEP (*(.init_fun_array*)) + __init_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + .task_fun_array : + { + . = ALIGN(4); + __task_fun_array_start = .; + KEEP (*(SORT(.task_fun_array.*))) + KEEP (*(.task_fun_array*)) + __task_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + .unload_cpaon (0x0053D000) (NOLOAD): + { + } >MSMB_AREA + .load_xp_sharedinfo (0x0053E000) (NOLOAD): + { + *(.shareInfo) + } >MSMB_AREA + .load_dbg_area (0x0053EF00) (NOLOAD): + { + *(.resetFlag) + } >MSMB_AREA + .unload_xp_ipcmem (0x0053F000) (NOLOAD): + { + } >MSMB_AREA +} +GROUP( + libgcc.a + libc.a + libm.a + ) diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash_common.ld b/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash_common.ld new file mode 100644 index 0000000..e7d974d --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash_common.ld @@ -0,0 +1,337 @@ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ + ASMB_AREA(rwx) : ORIGIN = 0x00000000, LENGTH = 0x010000 /* 64KB */ + MSMB_AREA(rwx) : ORIGIN = 0x00400000, LENGTH = 0x140000 /* 1.25MB */ + FLASH_AREA(rx) : ORIGIN = 0x00824000, LENGTH = 2944K /* 2.5MB */ +} + + +/* Define output sections */ +SECTIONS +{ + . = 0x00824000; + .vector : + { + KEEP(*(.isr_vector)) + } >FLASH_AREA + .cache : ALIGN(128) + { + Image$$UNLOAD_NOCACHE$$Base = .; + *cache.o(.text*) + } >FLASH_AREA + + .load_bootcode 0x0 : + { + . = ALIGN(4); + Load$$LOAD_BOOTCODE$$Base = LOADADDR(.load_bootcode); + Image$$LOAD_BOOTCODE$$Base = .; + KEEP(*(.mcuVector)) + *(.ramBootCode) + *qspi.o(.text*) + *flash.o(.text*) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + + Image$$LOAD_BOOTCODE$$Length = SIZEOF(.load_bootcode); + + .load_ap_piram_asmb 0x1000 : + { + . = ALIGN(4); + Load$$LOAD_AP_PIRAM_ASMB$$Base = LOADADDR(.load_ap_piram_asmb); + Image$$LOAD_AP_PIRAM_ASMB$$Base = .; + *(.psPARamcode) + *(.platPARamcode) + *memset.o(.text*) + *memcpy-armv7m.o(.text*) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_PIRAM_ASMB$$Length = SIZEOF(.load_ap_piram_asmb); + + .load_ap_firam_asmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FIRAM_ASMB$$Base = LOADADDR(.load_ap_firam_asmb); + Image$$LOAD_AP_FIRAM_ASMB$$Base = .; + *(.psFARamcode) + *(.platFARamcode) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_FIRAM_ASMB$$Length = SIZEOF(.load_ap_firam_asmb); + + .load_ap_rwdata_asmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ap_rwdata_asmb); + Image$$LOAD_AP_FDATA_ASMB$$RW$$Base = .; + *(.platFARWData) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_AP_FDATA_ASMB$$Length = SIZEOF(.load_ap_rwdata_asmb); + + .load_ps_rwdata_asmb : ALIGN(4) + { + Load$$LOAD_PS_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ps_rwdata_asmb); + Image$$LOAD_PS_FDATA_ASMB$$RW$$Base = .; + *(.psFARWData) + . = ALIGN(4); + } >ASMB_AREA AT>FLASH_AREA + Image$$LOAD_PS_FDATA_ASMB$$RW$$Length = SIZEOF(.load_ps_rwdata_asmb); + + .load_ap_zidata_asmb (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_AP_FDATA_ASMB$$ZI$$Base = .; + *(.platFAZIData) + . = ALIGN(4); + Image$$LOAD_AP_FDATA_ASMB$$ZI$$Limit = .; + + Image$$LOAD_PS_FDATA_ASMB$$ZI$$Base = .; + *(.psFAZIData) + . = ALIGN(4); + Image$$LOAD_PS_FDATA_ASMB$$ZI$$Limit = .; + + *(.exceptCheck) + } >ASMB_AREA + + .load_rrcmem 0xB000 (NOLOAD): + { + *(.rrcMem) + } >ASMB_AREA + + .load_flashmem 0xC000 (NOLOAD): + { + *(.apFlashMem) + } >ASMB_AREA + + .load_ap_piram_msmb 0x400000 : + { + . = ALIGN(4); + Load$$LOAD_AP_PIRAM_MSMB$$Base = LOADADDR(.load_ap_piram_msmb); + Image$$LOAD_AP_PIRAM_MSMB$$Base = .; + *(.psPMRamcode) + *(.platPMRamcode) + *(.platPMRamcodeFCLK) + *(.recordNodeRO) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_PIRAM_MSMB$$Length = SIZEOF(.load_ap_piram_msmb); + + .load_ap_firam_msmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_AP_FIRAM_MSMB$$Base = LOADADDR(.load_ap_firam_msmb); + Image$$LOAD_AP_FIRAM_MSMB$$Base = .; + *(.ramCode2) + *(.upRamCode) + *(.psFMRamcode) + *(.platFMRamcode) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_AP_FIRAM_MSMB$$Length = SIZEOF(.load_ap_firam_msmb); + + .load_apos : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_APOS$$Base = LOADADDR(.load_apos); + Image$$LOAD_APOS$$Base = .; + *event_groups.o(.text*) + *heap_6.o(.text*) + *tlsf.o(.text*) + *list.o(.text*) + *queue.o(.text*) + *tasks.o(.text*) + *timers.o(.text*) + *port.o(.text*) + *port_asm.o(.text*) + *cmsis_os2.o(.text*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_APOS$$Length = SIZEOF(.load_apos); + + .load_dram_bsp : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_DRAM_BSP$$Base = LOADADDR(.load_dram_bsp); + Image$$LOAD_DRAM_BSP$$Base = .; + *bsp_spi.o(.data*) + *flash.o(.data*) + *flash_rt.o(.data*) + *gpr.o(.data*) + *apmu.o(.data*) + *apmuTiming.o(.data*) + *bsp.o(.data*) + *plat_config.o(.data*) + *system_ec618.o(.data*) + *unilog.o(.data*) + *pad.o(.data*) + *ic.o(.data*) + *ec_main.o(.data*) + *slpman.o(.data*) + *bsp_usart.o(.data*) + *bsp_lpusart.o(.data*) + *timer.o(.data*) + *dma.o(.data*) + *adc.o(.data*) + *wdt.o(.data*) + *usb_device.o(.data*) + *uart_device.o(.data*) + *clock.o(.data*) + *hal_adcproxy.o(.data*) + *hal_alarm.o(.data*) + *exception_process.o(.data*) + *exception_dump.o(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_DRAM_BSP$$Length = SIZEOF(.load_dram_bsp); + + .load_dram_bsp_zi (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_DRAM_BSP$$ZI$$Base = .; + *bsp_spi.o(.bss*) + *flash.o(.bss*) + *flash_rt.o(.bss*) + *gpr.o(.bss*) + *apmu.o(.bss*) + *apmuTiming.o(.bss*) + *bsp.o(.bss*) + *plat_config.o(.bss*) + *system_ec618.o(.bss*) + *unilog.o(.bss*) + *pad.o(.bss*) + *ic.o(.bss*) + *ec_main.o(.bss*) + *slpman.o(.bss*) + *bsp_usart.o(.bss*) + *bsp_lpusart.o(.bss*) + *timer.o(.bss*) + *dma.o(.bss*) + *adc.o(.bss*) + *wdt.o(.bss*) + *usb_device.o(.bss*) + *uart_device.o(.bss*) + *clock.o(.bss*) + **hal_trim.o(.bss*) + *hal_adcproxy.o(.bss*) + *hal_alarm.o(.bss*) + *exception_process.o(.bss*) + *exception_dump.o(.bss*) + *(.recordNodeZI) + . = ALIGN(4); + Image$$LOAD_DRAM_BSP$$ZI$$Limit = .; + } >MSMB_AREA + + .unload_slpmem (NOLOAD): + { + *(.sleepmem) + } >MSMB_AREA + + .load_dram_shared : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_DRAM_SHARED$$Base = LOADADDR(.load_dram_shared); + Image$$LOAD_DRAM_SHARED$$Base = .; + *(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_DRAM_SHARED$$Length = SIZEOF(.load_dram_shared); + + .load_dram_shared_zi (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_DRAM_SHARED$$ZI$$Base = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + *(.stack) /* stack should be 4 byte align */ + Image$$LOAD_DRAM_SHARED$$ZI$$Limit = .; + *(.USB_NOINIT_DATA_BUF) + } >MSMB_AREA + + + PROVIDE(end_ap_data = . ); + PROVIDE(start_up_buffer = up_buf_start); + .load_up_buffer start_up_buffer(NOLOAD): + { + *(.catShareBuf) + Image$$LOAD_UP_BUFFER$$Limit = .; + } >MSMB_AREA + + PROVIDE(end_up_buffer = . ); + heap_size = start_up_buffer - end_ap_data; + ASSERT(heap_size>=min_heap_size_threshold,"ap use too much ram, heap less than min_heap_size_threshold!") + ASSERT(end_up_buffer<=0x500000,"ap use too much ram, exceed to 0x500000") + + .text : + { + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.text*) + } >FLASH_AREA + + .preinit_fun_array : + { + . = ALIGN(4); + __preinit_fun_array_start = .; + KEEP (*(SORT(.preinit_fun_array.*))) + KEEP (*(.preinit_fun_array*)) + __preinit_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + .init_fun_array : + { + . = ALIGN(4); + __init_fun_array_start = .; + KEEP (*(SORT(.init_fun_array.*))) + KEEP (*(.init_fun_array*)) + __init_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + + .task_fun_array : + { + . = ALIGN(4); + __task_fun_array_start = .; + KEEP (*(SORT(.task_fun_array.*))) + KEEP (*(.task_fun_array*)) + __task_fun_array_end = .; + . = ALIGN(4); + } > FLASH_AREA + + .unload_cpaon 0x0053D000 (NOLOAD): + { + + } >MSMB_AREA + + .load_xp_sharedinfo 0x0053E000 (NOLOAD): + { + *(.shareInfo) + } >MSMB_AREA + + .load_dbg_area 0x0053EF00 (NOLOAD): + { + *(.resetFlag) + } >MSMB_AREA + + .unload_xp_ipcmem 0x0053f000 (NOLOAD): + { + + } >MSMB_AREA +} + +GROUP( + libgcc.a + libc.a + libm.a + ) \ No newline at end of file diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash_low_spd.ld b/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash_low_spd.ld new file mode 100644 index 0000000..2dea9a0 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/ec618_0h00_flash_low_spd.ld @@ -0,0 +1,3 @@ +min_heap_size_threshold = 0x19000; +up_buf_start = 0x4c3500; +INCLUDE ec618_0h00_flash_common.ld \ No newline at end of file diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/prec_init.c b/PLAT/device/target/board/ec618_0h00/ap/gcc/prec_init.c new file mode 100644 index 0000000..9ca4aec --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/prec_init.c @@ -0,0 +1,457 @@ +#include +#include "commontypedef.h" +#include "ec618.h" +#include "cache.h" +#include "mpu_armv7.h" +#include "mem_map.h" +#include "exception_process.h" +#include "apmu_external.h" + +typedef struct +{ + UINT32 *base_addr; + INT32 offset; + UINT32 size; + UINT8 access_permission; + UINT8 cacheable; + UINT8 excute_disabled; +}mpu_setting_t; + + +#if defined(__CC_ARM) +__asm void __fast_memset(UINT32 *dst, UINT32 value, UINT32 length) +{ + push {r4-r9} + cmp r2, #0 + beq memset_return + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + and r8, r2,#0xf + mov r9, r8 + cmp r8, #0 + beq clr_16Byte +clr_4Byte + stmia r0!,{r4} + subs r8,r8,#4 + cmp r8,#0 + bne clr_4Byte + cmp r2, #0xf + bls memset_return + sub r2,r2,r9 +clr_16Byte + stmia r0!,{r4,r5,r6,r7} + subs r2,r2,#16 + cmp r2,#0 + bne clr_16Byte +memset_return + pop {r4-r9} + bx lr +} +#elif defined(__GNUC__) +__attribute__((__noinline__)) void __fast_memset(UINT32 *dst, UINT32 value, UINT32 length) +{ + asm volatile( + "push {r4-r9}\n\t" + "cmp r2, #0\n\t" + "beq memset_return\n\t" + "mov r4, r1\n\t" + "mov r5, r1\n\t" + "mov r6, r1\n\t" + "mov r7, r1\n\t" + "and r8, r2,#0xf\n\t" + "mov r9, r8\n\t" + "cmp r8, #0\n\t" + "beq clr_16Byte\n\t" +"clr_4Byte:\n\t" + "stmia r0!,{r4}\n\t" + "subs r8,r8,#4\n\t" + "cmp r8,#0\n\t" + "bne clr_4Byte\n\t" + "cmp r2, #0xf\n\t" + "bls memset_return\n\t" + "sub r2,r2,r9\n\t" +"clr_16Byte:\n\t" + "stmia r0!,{r4,r5,r6,r7}\n\t" + "subs r2,r2,#16\n\t" + "cmp r2,#0\n\t" + "bne clr_16Byte\n\t" +"memset_return:\n\t" + "pop {r4-r9}\n\t" + "bx lr\n\t" + ); +} +#endif + + + +extern UINT32 Load$$LOAD_BOOTCODE$$Base ; +extern UINT32 Image$$LOAD_BOOTCODE$$Base ; +extern UINT32 Image$$LOAD_BOOTCODE$$Length ; + +extern UINT32 Load$$LOAD_APOS$$Base ; +extern UINT32 Image$$LOAD_APOS$$Base ; +extern UINT32 Image$$LOAD_APOS$$Length ; + +extern UINT32 Load$$LOAD_DRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_DRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_DRAM_SHARED$$Length ; +extern UINT32 Image$$LOAD_DRAM_SHARED$$ZI$$Base; +extern UINT32 Image$$LOAD_DRAM_SHARED$$ZI$$Limit; + +extern UINT32 Load$$LOAD_DRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_DRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_DRAM_BSP$$Length ; +extern UINT32 Image$$LOAD_DRAM_BSP$$ZI$$Base; +extern UINT32 Image$$LOAD_DRAM_BSP$$ZI$$Limit; + +extern UINT32 Load$$LOAD_AP_FIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_MSMB$$Length ; + +extern UINT32 Load$$LOAD_AP_PIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_ASMB$$Length ; + +extern UINT32 Load$$LOAD_AP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_MSMB$$Length ; + +extern UINT32 Load$$LOAD_AP_FIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_ASMB$$Length ; + +extern UINT32 Load$$LOAD_AP_FDATA_ASMB$$RW$$Base; +extern UINT32 Image$$LOAD_AP_FDATA_ASMB$$RW$$Base; +extern UINT32 Image$$LOAD_AP_FDATA_ASMB$$Length; +extern UINT32 Image$$LOAD_AP_FDATA_ASMB$$ZI$$Base; +extern UINT32 Image$$LOAD_AP_FDATA_ASMB$$ZI$$Limit; + +extern UINT32 Load$$LOAD_PS_FDATA_ASMB$$RW$$Base; +extern UINT32 Image$$LOAD_PS_FDATA_ASMB$$RW$$Base; +extern UINT32 Image$$LOAD_PS_FDATA_ASMB$$RW$$Length; +extern UINT32 Image$$LOAD_PS_FDATA_ASMB$$ZI$$Base; +extern UINT32 Image$$LOAD_PS_FDATA_ASMB$$ZI$$Limit; + +extern UINT32 Image$$UNLOAD_NOCACHE$$Base; + +extern UINT32 __StackTop; +extern UINT32 __StackLimit; + +UINT32 Image$$ER_IROM1$$Base = 0;//temp define for usbc + + +const mpu_setting_t mpu_region[] = +{ + // base_addr offset size access cache excute + {0, 0, ARM_MPU_REGION_SIZE_8KB, ARM_MPU_AP_RO, 1, 0}, + {&Image$$UNLOAD_NOCACHE$$Base, 0, ARM_MPU_REGION_SIZE_128B, ARM_MPU_AP_RO, 0, 0}, + {(UINT32 *)MSMB_APMEM_END_ADDR, 0, ARM_MPU_REGION_SIZE_128KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x500000-0x520000 + {(UINT32 *)MSMB_APMEM_END_ADDR, 0x20000, ARM_MPU_REGION_SIZE_64KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x520000-0x530000 + {(UINT32 *)MSMB_APMEM_END_ADDR, 0x30000, ARM_MPU_REGION_SIZE_32KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x530000-0x538000 + {(UINT32 *)MSMB_APMEM_END_ADDR, 0x38000, ARM_MPU_REGION_SIZE_16KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x538000-0x53c000 + {(UINT32 *)MSMB_APMEM_END_ADDR, 0x3C000, ARM_MPU_REGION_SIZE_8KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x53c000-0x53e000 +}; + +#pragma GCC push_options +#pragma GCC optimize("O1") +void psFDataInAsmbInit(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + UINT32 *start_addr; + UINT32 *end_addr ; + + dst = &(Image$$LOAD_PS_FDATA_ASMB$$RW$$Base); + src = &(Load$$LOAD_PS_FDATA_ASMB$$RW$$Base); + length = (UINT32)&(Image$$LOAD_PS_FDATA_ASMB$$RW$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + start_addr = &(Image$$LOAD_PS_FDATA_ASMB$$ZI$$Base) ; + end_addr = &(Image$$LOAD_PS_FDATA_ASMB$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); + +} + + +void platFDataInAsmbInit(void) +{ + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32 *src; + UINT32 *dst; + UINT32 length; + + dst = &(Image$$LOAD_AP_FDATA_ASMB$$RW$$Base); + src = &(Load$$LOAD_AP_FDATA_ASMB$$RW$$Base); + length = (UINT32)&(Image$$LOAD_AP_FDATA_ASMB$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + start_addr = &(Image$$LOAD_AP_FDATA_ASMB$$ZI$$Base) ; + end_addr = &(Image$$LOAD_AP_FDATA_ASMB$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); + +} + + +void SetZIDataToZero(void) +{ + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32 length; + UINT32* stack_len = (UINT32*)(&__StackTop - &__StackLimit); + + start_addr = &(Image$$LOAD_DRAM_SHARED$$ZI$$Base) ; + end_addr = &(Image$$LOAD_DRAM_SHARED$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length-(UINT32)stack_len); +} + + +void CopyRWDataFromBin(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + APBootFlag_e apBootFlag = apmuGetAPBootFlag(); + + switch(apBootFlag) + { + case AP_BOOT_FROM_POWER_ON: + case AP_BOOT_FROM_AO: + case AP_BOOT_FROM_AH: + { + dst = &(Image$$LOAD_AP_FIRAM_ASMB$$Base); + src = &(Load$$LOAD_AP_FIRAM_ASMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_FIRAM_ASMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case AP_BOOT_FROM_AS2: + { + dst = &(Image$$LOAD_AP_FIRAM_MSMB$$Base); + src = &(Load$$LOAD_AP_FIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_FIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + dst = &(Image$$LOAD_APOS$$Base); + src = &(Load$$LOAD_APOS$$Base); + length = (unsigned int)&(Image$$LOAD_APOS$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + break; + + default: + EC_ASSERT(0, apBootFlag, 0, 0); + } + + DisableICache(); // flush cache when ramcode update + EnableICache(); + + dst = &(Image$$LOAD_DRAM_SHARED$$Base); + src = &(Load$$LOAD_DRAM_SHARED$$Base); + length = (UINT32)&(Image$$LOAD_DRAM_SHARED$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + +} + + +void CopyRamCodeForDeepSleep(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + + APBootFlag_e apBootFlag = apmuGetAPLLBootFlag(); + switch(apBootFlag) + { + case AP_BOOT_FROM_POWER_ON: + case AP_BOOT_FROM_AO: + case AP_BOOT_FROM_AH: + { + dst = &(Image$$LOAD_BOOTCODE$$Base); + src = &(Load$$LOAD_BOOTCODE$$Base); + length = (unsigned int)&(Image$$LOAD_BOOTCODE$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + dst = &(Image$$LOAD_AP_PIRAM_ASMB$$Base); + src = &(Load$$LOAD_AP_PIRAM_ASMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_PIRAM_ASMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case AP_BOOT_FROM_AS2: + { + dst = &(Image$$LOAD_AP_PIRAM_MSMB$$Base); + src = &(Load$$LOAD_AP_PIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_PIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + } + break; + + default: + EC_ASSERT(0, apBootFlag, 0, 0); + } + + DisableICache(); // flush cache when ramcode update + EnableICache(); + +} + + +void CopyDataRWZIForDeepSleep(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + + dst = &(Image$$LOAD_DRAM_BSP$$Base); + src = &(Load$$LOAD_DRAM_BSP$$Base); + length = (UINT32)&(Image$$LOAD_DRAM_BSP$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + UINT32 *start_addr; + UINT32 *end_addr ; + start_addr = &(Image$$LOAD_DRAM_BSP$$ZI$$Base) ; + end_addr = &(Image$$LOAD_DRAM_BSP$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); +} +#pragma GCC pop_options + + +void mpu_init(void) +{ + int i=0; + uint8_t region_num = 0; + + if(MPU->TYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + + region_num = sizeof(mpu_region)/sizeof(mpu_setting_t); + + for(i=0;iTYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + +} + + + + diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/startup_ec618_gcc.s b/PLAT/device/target/board/ec618_0h00/ap/gcc/startup_ec618_gcc.s new file mode 100644 index 0000000..8f79d01 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/startup_ec618_gcc.s @@ -0,0 +1,161 @@ + .syntax unified + .arch armv7-m + .cpu cortex-m3 + +.global __isr_vector +.global Reset_Handler + +.global __StackTop +.global __StackLimit + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x1000 +#endif +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .isr_vector,"a",%progbits + .align 2 + .type __isr_vector, %object + .size __isr_vector, .- __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long Pad0_WakeupIntHandler /* 0: Pad0 Wakeup */ + .long Pad1_WakeupIntHandler /* 1: Pad1 Wakeup */ + .long Pad2_WakeupIntHandler /* 2: Pad2 Wakeup */ + .long Pad3_WakeupIntHandler /* 3: Pad3 Wakeup */ + .long Pad4_WakeupIntHandler /* 4: Pad4 Wakeup */ + .long Pad5_WakeupIntHandler /* 5: Pad5 Wakeup */ + .long LPUSART_WakeupIntHandler /* 6: LPUART Wakeup */ + .long LPUSB_WakeupIntHandler /* 7: LPUSB Wakeup */ + .long PwrKey_WakeupIntHandler /* 8: PwrKey Wakeup */ + .long ChrgPad_WakeupIntHandler /* 9: ChrgPad Wakeup */ + .long RTC_WakeupIntHandler /* 10: RTC Wakeup */ + .long USB_IRQ_Handler /* 11: USB Wakeup */ + + .long XIC_IntHandler /* 12: XIC IRQ */ + .long XIC_IntHandler /* 13: XIC IRQ */ + .long XIC_IntHandler /* 14: XIC IRQ */ + .long XIC_IntHandler /* 15: XIC IRQ */ + + .text + .thumb + .thumb_func + .align 2 + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =0x4d020190 + ldr r1, =0x00000000 + str r1, [r0] + + .extern SystemInit + .extern ec_main + ldr r0, =SystemInit + blx r0 + ldr r0, =ec_main + bx r0 + .size Reset_Handler, .-Reset_Handler + + .thumb + .thumb_func + .align 2 + .type HardFault_Handler, %function +HardFault_Handler: + + .extern excepHardFaultHandler + .extern excepInfoStore + + mrs r1, PRIMASK /* backup PRIMASK */ + mov r0, #1 + msr PRIMASK, r0 + + ldr r12, =excepInfoStore + add r12, r12, #12 + stmia r12!, {r0-r11} + + add r12, r12, #20 + mov r0, lr /* store exc_return */ + stmia r12!, {r0} + + mrs r0, msp /* store msp */ + stmia r12!, {r0} + mrs r0, psp /* store psp */ + stmia r12!, {r0} + + mrs r0, CONTROL + stmia r12!, {r0} + + mrs r0, BASEPRI + stmia r12!, {r0} + mov r0, r1 /* restore PRIMASK */ + stmia r12!, {r0} + mrs r0, FAULTMASK + stmia r12!, {r0} + + mov r0, sp + mrs r1, psp + mov r2, lr + B excepHardFaultHandler + .size HardFault_Handler, .-HardFault_Handler + + .align 1 + .thumb + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, .-Default_Handler + + .macro def_irq_handler handler_name + .weak \handler_name + .thumb_set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler RTC_WakeupIntHandler + def_irq_handler Pad0_WakeupIntHandler + def_irq_handler Pad1_WakeupIntHandler + def_irq_handler Pad2_WakeupIntHandler + def_irq_handler Pad3_WakeupIntHandler + def_irq_handler Pad4_WakeupIntHandler + def_irq_handler Pad5_WakeupIntHandler + def_irq_handler LPUSART_WakeupIntHandler + def_irq_handler LPUSB_WakeupIntHandler + def_irq_handler PwrKey_WakeupIntHandler + def_irq_handler ChrgPad_WakeupIntHandler + def_irq_handler USB_IRQ_Handler + def_irq_handler XIC_IntHandler + + .end diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/syscalls.c b/PLAT/device/target/board/ec618_0h00/ap/gcc/syscalls.c new file mode 100644 index 0000000..b7a4b17 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/syscalls.c @@ -0,0 +1,100 @@ +#include +extern int io_putc(int ch) __attribute__((weak)); +extern int io_getc(void) __attribute__((weak)); + +int _close(int file) +{ + return 0; +} + +int _fstat(int file, struct stat *st) +{ + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(const char *name, int flags, int mode) +{ + return -1; +} + +int _read(int file, char *ptr, int len) +{ + return 0; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = io_getc(); + } + + return len; +} + + +#define __MYPID 1 +int _getpid() +{ + return __MYPID; +} + + + +int _kill(int pid, int sig) +{ + return -1; +} + +void _exit(int val) +{ + while(1); +} + +caddr_t _sbrk(int incr) +{ + extern char _heap_memory_start, _heap_memory_end; /* Defined by the linker */ + + static char *heap_end; + char *prev_heap_end; + + if (heap_end == NULL) { + heap_end = (char *)&_heap_memory_start; + } + + prev_heap_end = heap_end; + + if (heap_end + incr >= (char *)&_heap_memory_end) { + + return (caddr_t) - 1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + + + +int _write(int file, char *ptr, int len) +{ + extern int io_putchar(int ch); + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + io_putchar(*ptr++); + } + return len; +} + + + + + diff --git a/PLAT/device/target/board/ec618_0h00/ap/gcc/version.h b/PLAT/device/target/board/ec618_0h00/ap/gcc/version.h new file mode 100644 index 0000000..17d8832 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/gcc/version.h @@ -0,0 +1,7 @@ +#define SDK_MAJOR_VERSION "001" // For Major version +#define SDK_MINOR_VERSION "013" // For minor version +#define SDK_RA_VERSION "xxx" // For jenkins release use +#define SDK_PATCH_VERSION "p001.001" // For patch verion, modify when patch release +#define EVB_MAJOR_VERSION "1" +#define EVB_MINOR_VERSION "0" +#define EC_CHIP_VERSION "EcChipVerEc618CoreAp" diff --git a/PLAT/device/target/board/ec618_0h00/ap/inc/system_ec618.h b/PLAT/device/target/board/ec618_0h00/ap/inc/system_ec618.h new file mode 100644 index 0000000..30309a6 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/inc/system_ec618.h @@ -0,0 +1,105 @@ +/**************************************************************************//** + * @file system_ARMCM3.h + * @brief CMSIS Device System Header File for + * ARMCM3 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_CATERPILLER_H +#define SYSTEM_CATERPILLER_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#include "commontypedef.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +#define XTAL (204800000U) /* Oscillator frequency */ +#define DEFAULT_SYSTEM_CLOCK (XTAL) +#define SYSTICK_CLOCK (3250000) + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void); + +/** + \brief Save and set IRQ mask. + + Close irq and save current IRQ mask. + */ +static __FORCEINLINE uint32_t SaveAndSetIRQMask(void) +{ + uint32_t mask = __get_PRIMASK(); + __disable_irq(); + return mask; +} + + +/** + \brief Restore IRQ mask. + + Restore IRQ mask and enable irq. + */ +static __FORCEINLINE void RestoreIRQMask(uint32_t mask) +{ + __DSB(); + __ISB(); + __set_PRIMASK(mask); +} + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CATERPILLER_H */ diff --git a/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00.sct b/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00.sct new file mode 100644 index 0000000..36508b3 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00.sct @@ -0,0 +1,13 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00028000 { ; load region size_region + ER_IROM1 0x00000000 0x00028000 { ; load address = execution address + *.o (RESET, +First) + .ANY (+RO) + } + RW_IRAM1 0x00028000 0x00018000 { ; RW data + .ANY (+RW +ZI) + } +} diff --git a/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00_flash.sct b/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00_flash.sct new file mode 100644 index 0000000..bae40c1 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00_flash.sct @@ -0,0 +1,114 @@ +#! armcc -E +#include "..\..\common\inc\mem_map.h" + +LR_IROM1 AP_FLASH_LOAD_ADDR AP_FLASH_LOAD_SIZE { ; ap 2.5MB flash code + UNLOAD_IROM AP_FLASH_LOAD_ADDR AP_FLASH_LOAD_SIZE { ; load address = execution address + *.o (RESET, +First) + .ANY (+RO) + } + UNLOAD_NOCACHE +0 ALIGN 128{ + cache*.o (+RO) + } + + ; asmb define start + LOAD_BOOTCODE ASMB_START_ADDR { ; code in ram + *.o (.mcuVector, +First) + *.o (.ramBootCode) + qspi.o(+RO) + flash.o(+RO) + } + + LOAD_AP_PIRAM_ASMB ASMB_IRAM_START_ADDR { ; for ap paging image, placed in asmb + *.o (.psPARamcode) + *.o (.platPARamcode) + } + LOAD_AP_FIRAM_ASMB +0 { ; for ap full image code, but placed in asmb + *.o (.psFARamcode) + *.o (.platFARamcode) + } + LOAD_AP_DATA_ASMB +0 { + *.o (.asmbRWData) + *.o (.asmbZIData) + } + LOAD_RRCMEM ASMB_RRCMEM_START_ADDR { ; rrcMem + *.o (.rrcMem) + } + LOAD_FLASHMEM ASMB_FLASHMEM_START_ADDR { ; apFlashMem + *.o (.apFlashMem) + } + ; msmb define start + LOAD_AP_PIRAM_MSMB MSMB_START_ADDR { ; for ap paging image, placed in msmb + *.o (.psPMRamcode) + *.o (.platPMRamcode) + *.o (.platPMRamcodeFCLK) + *.o (.recordNodeRO) + } + LOAD_AP_FIRAM_MSMB +0 { ; for ap full image, placed in msmb + *.o (.ramCode2) + *.o (.upRamCode) + *.o (.psFMRamcode) + *.o (.platFMRamcode) + } + LOAD_APOS +0 { + event_groups.o(+RO) + heap_6.o(+RO) + tlsf.o(+RO) + list.o(+RO) + queue.o(+RO) + tasks.o(+RO) + timers.o(+RO) + port.o(+RO) + port_asm.o(+RO) + cmsis_os2.o(+RO) + } + LOAD_DRAM_BSP +0 { + bsp_spi.o(+RW +ZI) +; cache.o(+RW +ZI) + flash.o(+RW +ZI) + flash_rt.o(+RW +ZI) +; qspi.o(+RW +ZI) +; gpio.o(+RW +ZI) + gpr.o(+RW +ZI) + apmu.o(+RW +ZI) + bsp.o(+RW +ZI) + plat_config.o(+RW +ZI) + system_ec618.o(+RW +ZI) + unilog.o(+RW +ZI) + pad.o(+RW +ZI) + ic.o(+RW +ZI) + ec_main.o(+RW +ZI) + slpman.o(+RW +ZI) + bsp_usart.o(+RW +ZI) + bsp_lpusart.o(+RW +ZI) + timer.o(+RW +ZI) + dma.o(+RW +ZI) + adc.o(+RW +ZI) + wdt.o(+RW +ZI) + usb_device.o(+RW +ZI) + uart_device.o(+RW +ZI) + clock.o(+RW +ZI) + hal_trim.o(+ZI) + hal_adcproxy.o(+RW +ZI) + *(.recordNodeZI) + } + UNLOAD_SLPMEM +0 { + *.o(.sleepmem) + } + LOAD_DRAM_SHARED +0 { ; ap 256KB sram code + .ANY (+RW +ZI) + } + LOAD_UP_BUFFER +0 { ;ALIGN 131072{ + *(.catUpBuffer) + *(.catUpMem) + } + ScatterAssert(ImageLimit(LOAD_UP_BUFFER) <= MSMB_APMEM_END_ADDR) + UNLOAD_CPAON CP_AONMEMBACKUP_START_ADDR EMPTY 0x1000{ + + } + LOAD_XP_SHAREDINFO XP_SHAREINFO_BASE_ADDR { + *.o (.shareInfo) + } + UNLOAD_XP_IPCMEM IPC_SHAREDMEM_START_ADDR EMPTY 0x1000{ + + } +} diff --git a/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00_flash_fpga.sct b/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00_flash_fpga.sct new file mode 100644 index 0000000..bb52762 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/keil/ec618_0h00_flash_fpga.sct @@ -0,0 +1,108 @@ +#! armcc -E +#include "..\..\common\inc\mem_map.h" + +LR_IROM1 AP_FLASH_LOAD_ADDR 0x200000 { ; ap 1.5MB flash code on fpga + UNLOAD_IROM AP_FLASH_LOAD_ADDR 0x200000 { ; load address = execution address + *.o (RESET, +First) + .ANY (+RO) + } + UNLOAD_NOCACHE +0 ALIGN 128{ + cache*.o (+RO) + } + + ; asmb define start + LOAD_BOOTCODE ASMB_START_ADDR { ; code in ram + *.o (.mcuVector, +First) + *.o (.ramBootCode) + qspi.o(+RO) + flash.o(+RO) + } + + LOAD_AP_PIRAM_ASMB ASMB_IRAM_START_ADDR { ; for ap paging image, placed in asmb + *.o (.psPARamcode) + *.o (.platPARamcode) + } + LOAD_AP_FIRAM_ASMB +0 { ; for ap full image code, but placed in asmb + *.o (.psFARamcode) + *.o (.platFARamcode) + } + LOAD_AP_DATA_ASMB +0 { + *.o (.asmbData) + } + LOAD_RRCMEM ASMB_RRCMEM_START_ADDR { ; rrcMem + *.o (.rrcMem) + } + LOAD_FLASHMEM ASMB_FLASHMEM_START_ADDR { ; apFlashMem + *.o (.apFlashMem) + } + ; msmb define start + LOAD_AP_PIRAM_MSMB MSMB_START_ADDR { ; for ap paging image, placed in msmb + *.o (.psPMRamcode) + *.o (.platPMRamcode) + *.o (.platPMRamcodeFCLK) + } + LOAD_AP_FIRAM_MSMB +0 { ; for ap full image, placed in msmb + *.o (.ramCode2) + *.o (.upRamCode) + *.o (.psFMRamcode) + *.o (.platFMRamcode) + } + LOAD_APOS +0 { + event_groups.o(+RO) + heap_6.o(+RO) + tlsf.o(+RO) + list.o(+RO) + queue.o(+RO) + tasks.o(+RO) + timers.o(+RO) + port.o(+RO) + port_asm.o(+RO) + cmsis_os2.o(+RO) + } + LOAD_DRAM_BSP +0 { + bsp_spi.o(+RW +ZI) +; cache.o(+RW +ZI) + flash.o(+RW +ZI) + flash_rt.o(+RW +ZI) + qspi.o(+RW +ZI) +; gpio.o(+RW +ZI) + gpr.o(+RW +ZI) + apmu.o(+RW +ZI) + bsp.o(+RW +ZI) + plat_config.o(+RW +ZI) + system_ec618.o(+RW +ZI) + unilog.o(+RW +ZI) + pad.o(+RW +ZI) + ic.o(+RW +ZI) + ec_main.o(+RW +ZI) + slpman.o(+RW +ZI) + bsp_usart.o(+RW +ZI) + bsp_lpusart.o(+RW +ZI) + timer.o(+RW +ZI) + dma.o(+RW +ZI) + adc.o(+RW +ZI) + wdt.o(+RW +ZI) + usb_device.o(+RW +ZI) + uart_device.o(+RW +ZI) + clock.o(+RW +ZI) + hal_trim.o(+ZI) + *(.recordNode) + } + UNLOAD_SLPMEM +0 { + *.o(.sleepmem) + } + LOAD_DRAM_SHARED +0 { ; ap 256KB sram code + .ANY (+RW +ZI) + } + + ScatterAssert(ImageLimit(LOAD_DRAM_SHARED) <= MSMB_APMEM_END_ADDR) + UNLOAD_CPAON CP_AONMEMBACKUP_START_ADDR EMPTY 0x1000{ + + } + LOAD_XP_SHAREDINFO XP_SHAREINFO_BASE_ADDR { + *.o (.shareInfo) + } + UNLOAD_XP_IPCMEM IPC_SHAREDMEM_START_ADDR EMPTY 0x1000{ + + } +} diff --git a/PLAT/device/target/board/ec618_0h00/ap/keil/prec_init.c b/PLAT/device/target/board/ec618_0h00/ap/keil/prec_init.c new file mode 100644 index 0000000..2182d34 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/keil/prec_init.c @@ -0,0 +1,388 @@ +#include +#include "commontypedef.h" +#include "ec618.h" +#include "cache.h" +#include "mpu_armv7.h" +#include "mem_map.h" +#include "exception_process.h" +#include "apmu_external.h" + +typedef struct +{ + UINT32 *base_addr; + INT32 offset; + UINT32 size; + UINT8 access_permission; + UINT8 cacheable; + UINT8 excute_disabled; +}mpu_setting_t; + + + +__asm void __fast_memset(UINT32 *dst, UINT32 value, UINT32 length) +{ + push {r4-r9} + cmp r2, #0 + beq memset_return + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + and r8, r2,#0xf + mov r9, r8 + cmp r8, #0 + beq clr_16Byte +clr_4Byte + stmia r0!,{r4} + subs r8,r8,#4 + cmp r8,#0 + bne clr_4Byte + sub r2,r2,r9 +clr_16Byte + stmia r0!,{r4,r5,r6,r7} + subs r2,r2,#16 + cmp r2,#0 + bne clr_16Byte +memset_return + pop {r4-r9} + bx lr +} + + +#if defined(__CC_ARM) +extern UINT32 Load$$LOAD_BOOTCODE$$Base ; +extern UINT32 Image$$LOAD_BOOTCODE$$Base ; +extern UINT32 Image$$LOAD_BOOTCODE$$Length ; + +extern UINT32 Load$$LOAD_APOS$$Base ; +extern UINT32 Image$$LOAD_APOS$$Base ; +extern UINT32 Image$$LOAD_APOS$$Length ; + +extern UINT32 Image$$UNLOAD_NOCACHE$$Base ; + +extern UINT32 Load$$LOAD_DRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_DRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_DRAM_SHARED$$Length ; +extern UINT32 Image$$LOAD_DRAM_SHARED$$ZI$$Base; +extern UINT32 Image$$LOAD_DRAM_SHARED$$ZI$$Limit; + +extern UINT32 Load$$LOAD_DRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_DRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_DRAM_BSP$$Length ; +extern UINT32 Image$$LOAD_DRAM_BSP$$ZI$$Base; +extern UINT32 Image$$LOAD_DRAM_BSP$$ZI$$Limit; + +extern UINT32 Load$$LOAD_AP_FIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_MSMB$$Length ; + +extern UINT32 Load$$LOAD_AP_PIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_ASMB$$Length ; + +extern UINT32 Load$$LOAD_AP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_AP_PIRAM_MSMB$$Length ; + +extern UINT32 Load$$LOAD_AP_FIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_FIRAM_ASMB$$Length ; + +extern UINT32 Load$$LOAD_AP_DATA_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_DATA_ASMB$$Base ; +extern UINT32 Image$$LOAD_AP_DATA_ASMB$$Length ; +extern UINT32 Image$$LOAD_AP_DATA_ASMB$$ZI$$Base; +extern UINT32 Image$$LOAD_AP_DATA_ASMB$$ZI$$Limit; + + +extern UINT32 Image$$UNLOAD_IROM$$Base; + +extern UINT32 Stack_Size; +UINT32 Image$$ER_IROM1$$Base = 0;//temp define for usbc +#endif + +const mpu_setting_t mpu_region[] = +{ + // base_addr offset size access cache excute + {0, 0, ARM_MPU_REGION_SIZE_8KB, ARM_MPU_AP_RO, 1, 0}, + {(UINT32 *)MSMB_APMEM_END_ADDR, 0, ARM_MPU_REGION_SIZE_16KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x4f0000-0x500000 + {(UINT32 *)0x500000, 0, ARM_MPU_REGION_SIZE_128KB, ARM_MPU_AP_RO, 1, 0}, // cp region: 0x500000-0x520000 + +}; + + + +void SetZIDataToZero(void) +{ +#if defined(__CC_ARM) + APBootFlag_e apBootFlag = apmuGetAPBootFlag(); + + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32 length; + UINT32* stack_len = &(Stack_Size); + start_addr = &(Image$$LOAD_DRAM_SHARED$$ZI$$Base) ; + end_addr = &(Image$$LOAD_DRAM_SHARED$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length-(UINT32)stack_len); + + if((apBootFlag == AP_BOOT_FROM_POWER_ON) || (apBootFlag >= AP_BOOT_FROM_AH)) + { + start_addr = &(Image$$LOAD_AP_DATA_ASMB$$ZI$$Base) ; + end_addr = &(Image$$LOAD_AP_DATA_ASMB$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); + } +#endif +} + + +void CopyRWDataFromBin(void) +{ + + UINT32 *src; + UINT32 *dst; + UINT32 length; +#if defined(__CC_ARM) + + APBootFlag_e apBootFlag = apmuGetAPBootFlag(); + + switch(apBootFlag) + { + case AP_BOOT_FROM_POWER_ON: + case AP_BOOT_FROM_AO: + case AP_BOOT_FROM_AH: + { + dst = &(Image$$LOAD_AP_FIRAM_ASMB$$Base); + src = &(Load$$LOAD_AP_FIRAM_ASMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_FIRAM_ASMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case AP_BOOT_FROM_AS2: + { + dst = &(Image$$LOAD_AP_FIRAM_MSMB$$Base); + src = &(Load$$LOAD_AP_FIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_FIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + dst = &(Image$$LOAD_APOS$$Base); + src = &(Load$$LOAD_APOS$$Base); + length = (unsigned int)&(Image$$LOAD_APOS$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + break; + + default: + EC_ASSERT(0, apBootFlag, 0, 0); + } + + DisableICache(); // flush cache when ramcode update + EnableICache(); + + dst = &(Image$$LOAD_DRAM_SHARED$$Base); + src = &(Load$$LOAD_DRAM_SHARED$$Base); + length = (UINT32)&(Image$$LOAD_DRAM_SHARED$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + if((apBootFlag == AP_BOOT_FROM_POWER_ON) || (apBootFlag >= AP_BOOT_FROM_AH)) + { + dst = &(Image$$LOAD_AP_DATA_ASMB$$Base); + src = &(Load$$LOAD_AP_DATA_ASMB$$Base); + length = (UINT32)&(Image$$LOAD_AP_DATA_ASMB$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } +#endif +} + + +void CopyRamCodeForDeepSleep(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; +#if defined(__CC_ARM) + APBootFlag_e apBootFlag = apmuGetAPLLBootFlag(); + switch(apBootFlag) + { + case AP_BOOT_FROM_POWER_ON: + case AP_BOOT_FROM_AO: + case AP_BOOT_FROM_AH: + { + dst = &(Image$$LOAD_BOOTCODE$$Base); + src = &(Load$$LOAD_BOOTCODE$$Base); + length = (unsigned int)&(Image$$LOAD_BOOTCODE$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + dst = &(Image$$LOAD_AP_PIRAM_ASMB$$Base); + src = &(Load$$LOAD_AP_PIRAM_ASMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_PIRAM_ASMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case AP_BOOT_FROM_AS2: + { + dst = &(Image$$LOAD_AP_PIRAM_MSMB$$Base); + src = &(Load$$LOAD_AP_PIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_AP_PIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + } + break; + + default: + EC_ASSERT(0, apBootFlag, 0, 0); + } + + DisableICache(); // flush cache when ramcode update + EnableICache(); + +#endif + +} + + +void CopyDataRWZIForDeepSleep(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; +#if defined(__CC_ARM) + dst = &(Image$$LOAD_DRAM_BSP$$Base); + src = &(Load$$LOAD_DRAM_BSP$$Base); + length = (UINT32)&(Image$$LOAD_DRAM_BSP$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + UINT32 *start_addr; + UINT32 *end_addr ; + start_addr = &(Image$$LOAD_DRAM_BSP$$ZI$$Base) ; + end_addr = &(Image$$LOAD_DRAM_BSP$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); + +#endif + +} + + +void mpu_init(void) +{ + int i=0; + uint8_t region_num = 0; + + if(MPU->TYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + + region_num = sizeof(mpu_region)/sizeof(mpu_setting_t); + + for(i=0;iTYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + +} + + + + diff --git a/PLAT/device/target/board/ec618_0h00/ap/keil/startup_ec618.s b/PLAT/device/target/board/ec618_0h00/ap/keil/startup_ec618.s new file mode 100644 index 0000000..f565e78 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/keil/startup_ec618.s @@ -0,0 +1,309 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + EXPORT Stack_Size +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +;Heap_Size EQU 0x00000C00 +; +; AREA HEAP, NOINIT, READWRITE, ALIGN=3 +;__heap_base +;Heap_Mem SPACE Heap_Size +;__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD Pad0_WakeupIntHandler ; 0: Pad0 Wakeup + DCD Pad1_WakeupIntHandler ; 1: Pad1 Wakeup + DCD Pad2_WakeupIntHandler ; 2: Pad2 Wakeup + DCD Pad3_WakeupIntHandler ; 3: Pad3 Wakeup + DCD Pad4_WakeupIntHandler ; 4: Pad4 Wakeup + DCD Pad5_WakeupIntHandler ; 5: Pad5 Wakeup + DCD Lpuart_WakeupIntHandler ; 6: LPUART Wakeup + DCD LPUSB_WakeupIntHandler ; 7: LPUSB Wakeup + DCD PwrKey_WakeupIntHandler ; 8: PwrKey Wakeup + DCD ChrgPad_WakeupIntHandler ; 9: ChrgPad Wakeup + DCD RTC_WakeupIntHandler ; 10: RTC Wakeup + DCD USB_IRQ_Handler ; 11: USB Irq + DCD XIC_IntHandler ; 12: + DCD XIC_IntHandler ; 13 + DCD XIC_IntHandler ; 14: + DCD XIC_IntHandler ; 15: + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT ec_main + LDR R0, =0x4d020190 ; Not remapping + LDR R1, =0x00000000 + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + LDR R0, =ec_main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler\ + PROC + IMPORT excepHardFaultHandler + IMPORT excepInfoStore + EXPORT HardFault_Handler [WEAK] + + mrs r1, PRIMASK ;;backup PRIMASK + mov r0, #1 + msr PRIMASK, r0 + + ldr r12, =excepInfoStore + ldr r0, =0xf2f0f1f3 + stmia r12!, {r0} + ldr r0, =0xe2e0e1e3 + stmia r12!, {r0} + add r12, r12, #8 + stmia r12!, {r0-r11} + + add r12, r12, #20 + mov r0, lr ;;store exc_return + stmia r12!, {r0} + + mrs r0, msp ;;store msp + stmia r12!, {r0} + mrs r0, psp ;;store psp + stmia r12!, {r0} + + mrs r0, CONTROL + stmia r12!, {r0} + + mrs r0, BASEPRI + stmia r12!, {r0} + mov r0, r1 ;;restore PRIMASK + stmia r12!, {r0} + mrs r0, FAULTMASK + stmia r12!, {r0} + + mov r0, sp + mrs r1, psp + mov r2, lr + B excepHardFaultHandler + ENDP + +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + BL Default_Handler + B . + ENDP + +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + BL Default_Handler + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + BL Default_Handler + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Pad0_WakeupIntHandler PROC + EXPORT Pad0_WakeupIntHandler [WEAK] + B . + ENDP +Pad1_WakeupIntHandler PROC + EXPORT Pad1_WakeupIntHandler [WEAK] + B . + ENDP +Pad2_WakeupIntHandler PROC + EXPORT Pad2_WakeupIntHandler [WEAK] + B . + ENDP +Pad3_WakeupIntHandler PROC + EXPORT Pad3_WakeupIntHandler [WEAK] + B . + ENDP +Pad4_WakeupIntHandler PROC + EXPORT Pad4_WakeupIntHandler [WEAK] + B . + ENDP +Pad5_WakeupIntHandler PROC + EXPORT Pad5_WakeupIntHandler [WEAK] + B . + ENDP +Lpuart_WakeupIntHandler PROC + EXPORT Lpuart_WakeupIntHandler [WEAK] + B . + ENDP +LPUSB_WakeupIntHandler PROC + EXPORT LPUSB_WakeupIntHandler [WEAK] + B . + ENDP +PwrKey_WakeupIntHandler PROC + EXPORT PwrKey_WakeupIntHandler [WEAK] + B . + ENDP +ChrgPad_WakeupIntHandler PROC + EXPORT ChrgPad_WakeupIntHandler [WEAK] + B . + ENDP +RTC_WakeupIntHandler PROC + EXPORT RTC_WakeupIntHandler [WEAK] + B . + ENDP +USB_IRQ_Handler PROC + EXPORT USB_IRQ_Handler [WEAK] + B . + ENDP +XIC_IntHandler PROC + EXPORT XIC_IntHandler [WEAK] + B . + ENDP + +Default_Handler PROC + B . + ENDP +__clr_240K_mem PROC + MOVS R0, #0 + STM R6!,{R0} + ADDS R5, R5, #1 + CMP R5, #0xEC00 + BCC __clr_240K_mem + LDR R0, =0x08080000 + LDR SP, [R0,#0] + MOVS LR, R7 + BX LR + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + +; IF :DEF:__MICROLIB + + EXPORT __initial_sp +; EXPORT __heap_base +; EXPORT __heap_limit + +; ELSE + +; IMPORT __use_two_region_memory +; EXPORT __user_initial_stackheap + +;__user_initial_stackheap PROC +; LDR R0, = Heap_Mem +; LDR R1, =(Stack_Mem + Stack_Size) +; LDR R2, = (Heap_Mem + Heap_Size) +; LDR R3, = Stack_Mem +; BX LR +; ENDP + +; ALIGN + +; ENDIF + + + END diff --git a/PLAT/device/target/board/ec618_0h00/ap/keil/version.h b/PLAT/device/target/board/ec618_0h00/ap/keil/version.h new file mode 100644 index 0000000..b76c1b5 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/keil/version.h @@ -0,0 +1,7 @@ +#define SDK_MAJOR_VERSION "001" // For Major version +#define SDK_MINOR_VERSION "027" // For minor version +#define SDK_RA_VERSION "xxx" // For jenkins release use +#define SDK_PATCH_VERSION "000" // For patch verion, modify when patch release + +#define EVB_MAJOR_VERSION "1" +#define EVB_MINOR_VERSION "0" diff --git a/PLAT/device/target/board/ec618_0h00/ap/src/system_ec618.c b/PLAT/device/target/board/ec618_0h00/ap/src/system_ec618.c new file mode 100644 index 0000000..1b38122 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/ap/src/system_ec618.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include "RTE_Device.h" +#include "ec618.h" +#include "mpu_armv7.h" +#include "driver_common.h" +#include "cache.h" +#include "mem_map.h" +#include "slpman.h" +#include "clock.h" +#include "apmu_external.h" +#include "reset.h" +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +#define SYS_ADDRESS AP_FLASH_LOAD_ADDR + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__CC_ARM) + extern uint32_t __Vectors; +#elif defined(__GNUC__) + extern uint32_t __isr_vector; +#endif +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +#define CORE_CLOCK_SEL_ADDRESS (0x4d000020) +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ + +extern void CopyRWDataFromBin(void); +extern void SetZIDataToZero(void); +extern void CopyDataRamtoImage(void); +extern void CopyRamCodeForDeepSleep(void); +extern void CopyDataRWZIForDeepSleep(void); +extern void mpu_init(void); +extern void mpu_deinit(void); +static uint8_t sysROAddrCheck(uint32_t addr); + +extern void usblpw_retwkup_bootstat_reset(void); +extern uint32_t usblpw_retwkup_boot_start(void); +extern void usblpw_wr_reg_usb_wkdetflag(uint32_t usb_wkdetflag); +extern void usblpw_retwkup_clear_ctxstat_var(void); + + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ + +/** + \fn sysROAddrCheck(uint32_t addr) + \brief This function is called in flash erase or write apis to prevent + unexpected access the bootloader image read only area.. + \param[in] Addr: flash erase or write addr + \note Be careful if you want change this function. + */ +static uint8_t sysROAddrCheck(uint32_t addr) +{ + if(addr <(BOOTLOADER_FLASH_LOAD_ADDR+BOOTLOADER_FLASH_LOAD_SIZE-AP_FLASH_XIP_ADDR)) + { + return 1; + } + + + if((addr >=(AP_FLASH_LOAD_ADDR-AP_FLASH_XIP_ADDR)) + && (addr <(AP_FLASH_LOAD_ADDR+AP_FLASH_LOAD_SIZE-AP_FLASH_XIP_ADDR))) + { + return 1; + } + + return 0; +} + + + + /*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ + + + /** + \fn sysROSpaceCheck(uint32_t addr, uint32_t size) + \brief This function is called in flash erase or write apis to prevent + unexpected access the bootloader image read only area.. + \param[in] Addr: flash erase or write addr + Addr: flash erase or write size + \note Be careful if you want change this function. + */ +uint8_t sysROSpaceCheck(uint32_t addr, uint32_t size) + +{ + if(sysROAddrCheck(addr)) + { + return 1; + } + if (sysROAddrCheck(addr+size - 1)) + { + return 1; + } + return 0; +} + + + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ +#ifdef FPGA_TEST + SystemCoreClock = 102400000; +#else + switch((*((uint32_t *)CORE_CLOCK_SEL_ADDRESS)) & 0x3) + { + case 0: + SystemCoreClock = 26000000U; + break; + case 1: + SystemCoreClock = 204800000U; + break; + case 2: + SystemCoreClock = 102400000U; + break; + case 3: + SystemCoreClock = 32768U; + break; + } +#endif +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemFullImageInit (void) +{ + apmuRestoreBootFlag(); + + uint32_t ResetStat = apmuGetAPBootFlag(); //areg0 + + if(ResetStat == AP_BOOT_FROM_AS1) //sleep1 + return; + + mpu_deinit(); + + /*move the RW data in the image to its excution region*/ + CopyRWDataFromBin(); + + /*append the ZI region. TODO: maybe ZI data need not to be 0, + random value maybe aslo fine for application, if so we could + remove this func call, since it takes a lot of time*/ + SetZIDataToZero(); + + CopyDataRWZIForDeepSleep(); + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__CC_ARM) + SCB->VTOR = (uint32_t) &__Vectors; +#elif defined (__GNUC__) + SCB->VTOR = (uint32_t) &__isr_vector; +#endif +#endif + + /*set NVIC priority group as 4(bits 7,6,5 is group priority bits ), + 3 bits for group priority. Since our CM3 core only implemented 3 + bits for priority and freertos recommend all bits should be + group priority bits*/ + NVIC_SetPriorityGrouping(4); + + //enable div 0 trap,then div 0 operation will trigger hardfault + SCB->CCR|=SCB_CCR_DIV_0_TRP_Msk; + + + SystemCoreClockUpdate(); + + mpu_init(); +} + + +void SystemInit (void) +{ + DisableICache(); + + EnableICache(); + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__CC_ARM) + SCB->VTOR = (uint32_t) &__Vectors; +#elif defined (__GNUC__) + SCB->VTOR = (uint32_t) &__isr_vector; +#endif +#endif + + ResetApplyAPLockupCfg(); + + BOOT_TIMESTAMP_SET(0, 0); + + GPR_bootSetting(); + + usblpw_retwkup_bootstat_reset(); + + apmuRestoreBootFlag(); + + APBootFlag_e apBootFlag = apmuGetAPLLBootFlag(); //aon reg0 + +#if (RTE_USB_EN == 1) + usblpw_wr_reg_usb_wkdetflag(0); + + if(apBootFlag != AP_BOOT_FROM_POWER_ON) + { + usblpw_retwkup_boot_start(); + } + else + { + usblpw_retwkup_clear_ctxstat_var(); + } +#endif + + GPR_setApbGprAcg(); + + BOOT_TIMESTAMP_SET(0, 1); + + if(apBootFlag == AP_BOOT_FROM_AH) + apmuSetSwWakeupSlowCntFlash(); + + if(apBootFlag == AP_BOOT_FROM_AS1) //sleep1 + { + return; + } + + CopyRamCodeForDeepSleep(); + + CopyDataRWZIForDeepSleep(); + + BOOT_TIMESTAMP_SET(0, 2); + +#ifdef FEATURE_DUMP_CHECK + EXCEP_CHECK_POINT(1); +#endif + + /*set NVIC priority group as 4(bits 7,6,5 is group priority bits ), + 3 bits for group priority. Since our CM3 core only implemented 3 + bits for priority and freertos recommend all bits should be + group priority bits*/ + NVIC_SetPriorityGrouping(4); + + //enable div 0 trap,then div 0 operation will trigger hardfault + SCB->CCR|=SCB_CCR_DIV_0_TRP_Msk; + + SystemCoreClockUpdate(); + +} + diff --git a/PLAT/device/target/board/ec618_0h00/common/inc/mem_map.h b/PLAT/device/target/board/ec618_0h00/common/inc/mem_map.h new file mode 100644 index 0000000..e573325 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/common/inc/mem_map.h @@ -0,0 +1,266 @@ + +#ifndef MEM_MAP_H +#define MEM_MAP_H + + +/* +AP flash layout, toatl 4MB +flash raw address: 0x00000000---0x00400000 +flash xip address(from ap view): 0x00800000---0x00c00000 + + +0x00000000 |---------------------------------| + | header1 8KB | +0x00002000 |---------------------------------| + | header2 8KB | +0x00004000 |---------------------------------| + | bl part1 32KB | +0x0000c000 |---------------------------------| + | bl part2 96KB |------OTA write +0x00024000 |---------------------------------| + | app img 2.5MB |------OTA write +0x002a4000 |---------------------------------| + | resv1 384KB | +0x00304000 |---------------------------------| + | fota 512KB |-----OTA download write +0x00384000 |---------------------------------| + | lfs 288KB |-----FS write +0x003cc000 |---------------------------------| + | softsim 64KB |-----SOFTSIM write +0x003dc000 |---------------------------------| + | rel_ap(factory) 16KB |-----factory write +0x003e0000 |---------------------------------| + | rel_ap 16KB |-----factory write +0x003e4000 |---------------------------------| + | hib backup 96KB |-----hib write +0x003fc000 |---------------------------------| + | plat config 16KB |-----similar as FS +0x00400000 |---------------------------------| + + + + + +CP flash layout, toatl 1MB +flash raw address: 0x00000000---0x00100000 +flash xip address(from cp view): 0x00800000---0x00900000 +flash xip address(from ap view): 0x08800000---0x08900000 + +0x00000000 |---------------------------------| + | cp img 512KB | +0x00064000 |---------------------------------| + | resv 308KB | +0x000cd000 |---------------------------------| + | IP2 4KB | +0x000ce000 |---------------------------------| + | rel_cp(default) 100KB | +0x000e7000 |---------------------------------| + | rel_ap 100KB | +0x00100000 |---------------------------------| + + +*/ + +/* -------------------------------flash address define-------------------------*/ + +#define AP_VIEW_CPFLASH_XIP_ADDR (0x08800000) + + +#define AP_FLASH_XIP_ADDR (0x00800000) + +//bl addr and size +#define BOOTLOADER_FLASH_LOAD_ADDR (0x00804000) +#define BOOTLOADER_FLASH_LOAD_SIZE (0x20000)//128kB + + +//ap image addr and size +#define AP_FLASH_LOAD_ADDR (0x00824000) +#ifdef __USER_CODE__ +#define AP_FLASH_LOAD_SIZE (0x2E0000)//2.5MB + 384KB +#else +#define AP_FLASH_LOAD_SIZE (0x280000)//2.5MB +#endif + +/*0x002a4000 -----0x00304000 RESERVRD 384KB*/ + +//fota addr and size +#define FLASH_FOTA_REGION_START (0x304000) +#define FLASH_FOTA_REGION_LEN (0x80000)//512KB +#define FLASH_FOTA_REGION_END (0x384000) + +#ifdef __USER_CODE__ + +//fs addr and size +#define FLASH_FS_REGION_START (0x384000) +#define FLASH_FS_REGION_END (0x3cc000) +#define FLASH_FS_REGION_SIZE (FLASH_FS_REGION_END-FLASH_FS_REGION_START) // 352KB +#define FLASH_FDB_REGION_START (0x3cc000) //FDB 64KB +#define FLASH_FDB_REGION_END (0x3dc000) +//softsim addr and size +#define SOFTSIM_FLASH_PHYSICAL_BASEADDR (0xfcc000) +#define SOFTSIM_FLASH_MAX_SIZE (0x00000)//0KB +#else +#define FLASH_FS_REGION_START (0x384000) +#define FLASH_FS_REGION_END (0x3cc000) +#define FLASH_FS_REGION_SIZE (FLASH_FS_REGION_END-FLASH_FS_REGION_START) // 288KB + +//softsim addr and size +#define SOFTSIM_FLASH_PHYSICAL_BASEADDR (0x3cc000) +#define SOFTSIM_FLASH_MAX_SIZE (0x10000)//64KB +#endif + +//ap reliable addr and size +#define NVRAM_FACTORY_PHYSICAL_BASE (0x3dc000) +#define NVRAM_FACTORY_PHYSICAL_SIZE (0x4000)//16KB +#define NVRAM_PHYSICAL_BASE (0x3e0000) +#define NVRAM_PHYSICAL_SIZE (0x4000)//16KB + + +//hib bakcup addr and size +#define FLASH_MEM_BACKUP_ADDR (AP_FLASH_XIP_ADDR+0x3e4000) +#define FLASH_MEM_BACKUP_NONXIP_ADDR (FLASH_MEM_BACKUP_ADDR-AP_FLASH_XIP_ADDR) +#define FLASH_MEM_BLOCK_SIZE (0x6000) +#define FLASH_MEM_BLOCK_CNT (0x4) +#define FLASH_MEM_BACKUP_SIZE (0x18000)//96KB + +//plat config addr and size +#define FLASH_MEM_PLAT_INFO_ADDR (AP_FLASH_XIP_ADDR+0x3fc000) +#define FLASH_MEM_PLAT_INFO_SIZE (0x1000)//4KB +#define FLASH_MEM_PLAT_INFO_NONXIP_ADDR (FLASH_MEM_PLAT_INFO_ADDR - AP_FLASH_XIP_ADDR) + +#define FLASH_MEM_RESET_INFO_ADDR (AP_FLASH_XIP_ADDR+0x3fd000) +#define FLASH_MEM_RESET_INFO_SIZE (0x1000)//4KB +#define FLASH_MEM_RESET_INFO_NONXIP_ADDR (FLASH_MEM_RESET_INFO_ADDR - AP_FLASH_XIP_ADDR) + + +#define CP_FLASH_XIP_ADDR (0x00800000) + +//cp img +#define CP_FLASH_LOAD_ADDR (0x00800000) +#define CP_FLASH_LOAD_SIZE (0x80000)//512KB + +//for ramdump +#define CP_FLASH_RESV_ADDR (0x00880000) +//#define CP_FLASH_RESV_PHYSICAL_ADDR (0x80000) +#define CP_FLASH_RESV_SIZE (0x4d000)//308KB +//#define CP_FLASH_RESV_NUM_SECTOR (77) + +#define FLASH_EXCEP_DUMP_ADDR (0x80000) +#define FLASH_EXCEP_DUMP_SECTOR_NUM (77) + + + +#define CP_FLASH_IP2_ADDR (0x008cd000) +#define CP_FLASH_IP2_SIZE (0x1000)//4KB + +//cp reliable addr and size, cp nvm write by ap +#define CP_NVRAM_FACTORY_PHYSICAL_BASE (0xce000) +#define CP_NVRAM_FACTORY_PHYSICAL_SIZE (0x19000)//100KB +#define CP_NVRAM_PHYSICAL_BASE (0xe7000) +#define CP_NVRAM_PHYSICAL_SIZE (0x19000)//100KB + + + +//add for img merge tool,should fix as AP_xx/CP_xx/BL_xx, tool will extract img type from it +#define AP_IMG_MERGE_ADDR (0x00024000) +#define CP_IMG_MERGE_ADDR (0x00000000) +#define BL_IMG_MERGE_ADDR (0x00004000) + +#define BLS_SEC_HAED_ADDR (0x0) +#define BLS_FLASH_LOAD_SIZE (0x2000) +#define SYS_SEC_HAED_ADDR (0x2000) +#define SYS_FLASH_LOAD_SIZE (0x2000) + + + + +/* -----------ram address define, TODO: need modify according to ram lauout-------------*/ + +//csmb start +#define CSMB_START_ADDR (0x0) +#define CSMB_END_ADDR (0x10000) +#define CSMB_PHY_AONMEM_ADDR (0xf000) +//csmb end + + +//msmb start + +/* +0x00400000 |---------------------------------| + | LOAD_AP_FIRAM_MSMB | + |---------------------------------| + | LOAD_APOS | + |---------------------------------| + | LOAD_DRAM_BSP | + |---------------------------------| + | UNLOAD_SLPMEM | + |---------------------------------| + | LOAD_DRAM_SHARED | +0x00500000 |---------------------------------| <---MSMB_APMEM_END_ADDR + | LOAD_CP_FIRAM_MSMB | + |---------------------------------| + | LOAD_CPOS_IRAM | + |---------------------------------| + | UNLOAD_SLPMEM | + |---------------------------------| + | LOAD_CPDRAM_SHARED | + |---------------------------------| + | LOAD_CPDRAM_BSP | +0x0053D000 |---------------------------------| <---CP_AONMEMBACKUP_START_ADDR + | UNLOAD_CPAON | +0x0053E000 |---------------------------------| <---XP_SHAREINFO_BASE_ADDR + | LOAD_XP_SHAREDINFO | +0x0053F000 |---------------------------------| <---IPC_SHAREDMEM_START_ADDR + | LOAD_XP_IPCMEM | +0x00540000 | | <---MSMB_END_ADDR + +*/ + +#define MSMB_START_ADDR (0x00400000) +#define MSMB_END_ADDR (0x00540000) +#define MSMB_APMEM_END_ADDR (0x00500000) +#define MSMB_CPMEM_START_ADDR (0x00500000) +#define MSMB_CPDATA_START_ADDR (0x0052C000) +#define CP_AONMEMBACKUP_START_ADDR (0x0053D000) +#define XP_SHAREINFO_BASE_ADDR (0x0053E000) +#define XP_DBGRESERVED_BASE_ADDR (0x0053EF00) +#define IPC_SHAREDMEM_START_ADDR (0x0053F000) + + +//msmb end + + +//asmb start +/* +0x00000000 |---------------------------------| + | bootcode | +0x00001000 |---------------------------------| + | LOAD_AP_PIRAM_ASMB | + |---------------------------------| + | LOAD_AP_FIRAM_ASMB | +0x0000C000 |---------------------------------| + | LOAD_RRCMEM | +0x0000D000 |---------------------------------| + | LOAD_FLASHMEM | +0x00010000 |---------------------------------| +*/ +#define ASMB_START_ADDR (0x00000000) +#define ASMB_END_ADDR (0x00010000) +#define ASMB_IRAM_START_ADDR (0x00001000) +#define ASMB_RRCMEM_START_ADDR (0x0000C000) +#define ASMB_FLASHMEM_START_ADDR (0x0000D000) +//asmb end + +#ifdef LOW_SPEED_SERVICE_ONLY +#define min_heap_size_threshold 0x19000 +#define up_buf_start 0x4c3500 +#else +#define min_heap_size_threshold 0x20000 +#define up_buf_start 0x499000 +#endif + +// TODO: need re-design excption dump + + + +#endif diff --git a/PLAT/device/target/board/ec618_0h00/cp/gcc/ec618_0h00_flash.ld b/PLAT/device/target/board/ec618_0h00/cp/gcc/ec618_0h00_flash.ld new file mode 100644 index 0000000..0ee1dc9 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/gcc/ec618_0h00_flash.ld @@ -0,0 +1,275 @@ + +#include "mem_map.h" + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Specify the memory areas */ +MEMORY +{ + CSMB_AREA(rwx) : ORIGIN = 0x00000000, LENGTH = 0x010000 /* 64KB */ + MSMB_AREA(rwx) : ORIGIN = 0x00500000, LENGTH = 0x40000 /* 0.25MB */ + FLASH_AREA(rx) : ORIGIN = 0x00800000, LENGTH = 512K /* 512KB */ +} + +/* Define output sections */ +SECTIONS +{ + . = CP_FLASH_XIP_ADDR; + .vector : + { + KEEP(*(.isr_vector)) + } >FLASH_AREA + .cache : ALIGN(128) + { + Image$$UNLOAD_NOCACHE$$Base = .; + *cache.o(.text*) + } >FLASH_AREA + + _etext = .; /* define a global symbols at end of code */ + + .load_cp_piram_csmb 0x20 : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CP_PIRAM_CSMB$$Base = LOADADDR(.load_cp_piram_csmb); + Image$$LOAD_CP_PIRAM_CSMB$$Base = .; + *(.phyCodeCsmb_ICS) + *(.phyCodeCsmb_UL) + *(.phyCodeCsmb_RXDFE) + *(.phyCodeCsmb_CE) + *(.phyCodeCsmb_AXC) + *(.phyCodeCsmb_RF) + *(.phyCodeCsmb_SCHD) + *(.phyCodeCsmb_MACSF) + *(.phyCodeCsmb_MEAS) + *(.phyCodeCsmb_PMU) + *(.phyCodeCsmb_CCH) + *(.phyCodeCsmb_CSI) + *(.phyCodeCsmb_DCH) + *(.phyCodeCsmb_DEC) + *(.phyCodeCsmb_HARQ) + *(.phyCodeCsmb_TMU) + *(.phyCodeCsmb_COMN) + *(.cpPlatCodeCsmb) + *(.phyDataCsmb_Const) + *memset.o(.text*) + *memcpy-armv7m.o(.text*) + *(.recordNodeRO) + . = ALIGN(4); + } >CSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CP_PIRAM_CSMB$$Length = SIZEOF(.load_cp_piram_csmb); + + .load_cp_firam_csmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CP_FIRAM_CSMB$$Base = LOADADDR(.load_cp_firam_csmb); + Image$$LOAD_CP_FIRAM_CSMB$$Base = .; + . = ALIGN(4); + } >CSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CP_FIRAM_CSMB$$Length = SIZEOF(.load_cp_firam_csmb); + + .unload_cpcsmbdata CSMB_PHY_AONMEM_ADDR-0x1000 (NOLOAD): + { + *(.phyDataCsmb_Slp2) + } >CSMB_AREA + + .unload_cpaonmem CSMB_PHY_AONMEM_ADDR (NOLOAD): + { + *(.phyDataCsmb_AonMemBackup) + *(.phyDataCsmb) + } >CSMB_AREA + + .load_cp_slp2piram_msmb MSMB_CPMEM_START_ADDR : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CP_SLP2PIRAM_MSMB$$Base = LOADADDR(.load_cp_slp2piram_msmb); + Image$$LOAD_CP_SLP2PIRAM_MSMB$$Base = .; + *(.phyCodeMsmb_SLP2) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CP_SLP2PIRAM_MSMB$$Length = SIZEOF(.load_cp_slp2piram_msmb); + + .load_cp_piram_msmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CP_PIRAM_MSMB$$Base = LOADADDR(.load_cp_piram_msmb); + Image$$LOAD_CP_PIRAM_MSMB$$Base = .; + *(.phyCodeMsmb_HIB) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CP_PIRAM_MSMB$$Length = SIZEOF(.load_cp_piram_msmb); + + + .load_cp_firam_msmb : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CP_FIRAM_MSMB$$Base = LOADADDR(.load_cp_firam_msmb); + Image$$LOAD_CP_FIRAM_MSMB$$Base = .; + *(.phyFMRamcode) + *(.phyCodeMsmb_ICS) + *(.phyCodeMsmb_UL) + *(.phyCodeMsmb_RXDFE) + *(.phyCodeMsmb_CE) + *(.phyCodeMsmb_AXC) + *(.phyCodeMsmb_RF) + *(.phyCodeMsmb_SCHD) + *(.phyCodeMsmb_MACSF) + *(.phyCodeMsmb_MEAS) + *(.phyCodeMsmb_PMU) + *(.phyCodeMsmb_CCH) + *(.phyCodeMsmb_CSI) + *(.phyCodeMsmb_DCH) + *(.phyCodeMsmb_DEC) + *(.phyCodeMsmb_HARQ) + *(.phyCodeMsmb_TMU) + *(.phyCodeMsmb_COMN) + *(.phyDataMsmb_Const) + *(.cpPlatCodeMsmb) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CP_FIRAM_MSMB$$Length = SIZEOF(.load_cp_firam_msmb); + + .load_cpos : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CPOS_IRAM$$Base = LOADADDR(.load_cpos); + Image$$LOAD_CPOS_IRAM$$Base = .; + *event_groups.o(.text*) + *heap_6.o(.text*) + *tlsf.o(.text*) + *mm_debug.o(.text*) + *list.o(.text*) + *queue.o(.text*) + *tasks.o(.text*) + *timers.o(.text*) + *port.o(.text*) + *port_asm.o(.text*) + *cmsis_os2.o(.text*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CPOS_IRAM$$Length = SIZEOF(.load_cpos); + + .unload_slpmem MSMB_CPDATA_START_ADDR (NOLOAD): /* from 0x500000-0x52C000 is readonly */ + { + *(.sleepmem) + } >MSMB_AREA + + .load_cpdram_bsp_data : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CPDRAM_BSP$$Base = LOADADDR(.load_cpdram_bsp_data); + Image$$LOAD_CPDRAM_BSP$$Base = .; + *gpr.o(.data*) + *clock.o(.data*) + *cpmu.o(.data*) + *cp_main.o(.data*) + *slpman.o(.data*) + *exception_process.o(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CPDRAM_BSP$$Length = SIZEOF(.load_cpdram_bsp_data); + + .load_cpdram_bsp_zi : + { + . = ALIGN(4); + Image$$LOAD_CPDRAM_BSP$$ZI$$Base = .; + *gpr.o(.bss.*) + *clock.o(.bss.*) + *cpmu.o(.bss.*) + *cp_main.o(.bss.*) + *slpman.o(.bss.*) + *wdt.o(.bss.*) + *exception_process.o(.bss.*) + *(.recordNodeZI) + . = ALIGN(4); + Image$$LOAD_CPDRAM_BSP$$ZI$$Limit = .; + } >MSMB_AREA + + .load_cpdram_shared_data : ALIGN(4) + { + . = ALIGN(4); + Load$$LOAD_CPDRAM_SHARED$$Base = LOADADDR(.load_cpdram_shared_data); + Image$$LOAD_CPDRAM_SHARED$$Base = .; + *(.phyDataMsmb) + *(.phyShareDataMsmb) + *(.data*) + . = ALIGN(4); + } >MSMB_AREA AT>FLASH_AREA + + Image$$LOAD_CPDRAM_SHARED$$Length = SIZEOF(.load_cpdram_shared_data); + + .load_cpdram_shared_bss (NOLOAD): + { + . = ALIGN(4); + Image$$LOAD_CPDRAM_SHARED$$ZI$$Base = .; + *(.cpPlatDataMsmb) + *(.bss*) + . = ALIGN(4); + *(.stack) /* stack should be 4 byte align */ + Image$$LOAD_CPDRAM_SHARED$$ZI$$Limit = .; + } >MSMB_AREA + + end_cp_data = . ; + + ASSERT(end_cp_dataFLASH_AREA + + .unload_cpaon CP_AONMEMBACKUP_START_ADDR (NOLOAD): + { + *(.phyDataMsmb_AonMemBackup) + } >MSMB_AREA + + .load_xp_sharedinfo XP_SHAREINFO_BASE_ADDR (NOLOAD): + { + *(.shareInfo) + } >MSMB_AREA + + .load_dbg_area XP_DBGRESERVED_BASE_ADDR (NOLOAD): + { + *(.resetFlag) + } >MSMB_AREA + + .unload_xp_ipcmem IPC_SHAREDMEM_START_ADDR (NOLOAD): + { + + } >MSMB_AREA +} + +GROUP( + libgcc.a + libc.a + libm.a + ) \ No newline at end of file diff --git a/PLAT/device/target/board/ec618_0h00/cp/gcc/prec_init.c b/PLAT/device/target/board/ec618_0h00/cp/gcc/prec_init.c new file mode 100644 index 0000000..28c4d74 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/gcc/prec_init.c @@ -0,0 +1,453 @@ +#include +#include "commontypedef.h" +#include "ec618_internal.h" +#include "cache.h" +#include "mpu_armv7.h" +#include "mem_map.h" +#include "cpmu.h" +#include "exception_process.h" + +typedef struct +{ + UINT32 *base_addr; + INT32 offset; + UINT32 size; + UINT8 access_permission; + UINT8 cacheable; + UINT8 excute_disabled; +}mpu_setting_t; + + +#if defined(__CC_ARM) +__asm void __fast_memset(UINT32 *dst, UINT32 value, UINT32 length) +{ + push {r4-r9} + cmp r2, #0 + beq memset_return + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + and r8, r2,#0xf + mov r9, r8 + cmp r8, #0 + beq clr_16Byte +clr_4Byte + stmia r0!,{r4} + subs r8,r8,#4 + cmp r8,#0 + bne clr_4Byte + cmp r2, #0xf + bls memset_return + sub r2,r2,r9 +clr_16Byte + stmia r0!,{r4,r5,r6,r7} + subs r2,r2,#16 + cmp r2,#0 + bne clr_16Byte +memset_return + pop {r4-r9} + bx lr +} +#elif defined(__GNUC__) +__attribute__((__noinline__)) void __fast_memset(UINT32 *dst, UINT32 value, UINT32 length) +{ + asm volatile( + "push {r4-r9}\n\t" + "cmp r2, #0\n\t" + "beq memset_return\n\t" + "mov r4, r1\n\t" + "mov r5, r1\n\t" + "mov r6, r1\n\t" + "mov r7, r1\n\t" + "and r8, r2,#0xf\n\t" + "mov r9, r8\n\t" + "cmp r8, #0\n\t" + "beq clr_16Byte\n\t" +"clr_4Byte:\n\t" + "stmia r0!,{r4}\n\t" + "subs r8,r8,#4\n\t" + "cmp r8,#0\n\t" + "bne clr_4Byte\n\t" + "cmp r2, #0xf\n\t" + "bls memset_return\n\t" + "sub r2,r2,r9\n\t" +"clr_16Byte:\n\t" + "stmia r0!,{r4,r5,r6,r7}\n\t" + "subs r2,r2,#16\n\t" + "cmp r2,#0\n\t" + "bne clr_16Byte\n\t" +"memset_return:\n\t" + "pop {r4-r9}\n\t" + "bx lr\n\t" + ); +} +#endif + +////////// LOAD_CPVECTOR /////////////// +// copy by ap code before cp power on // +//////////////////////////////////////// + +////////// LOAD_CPOS_IRAM ////////////// +extern UINT32 Load$$LOAD_CPOS_IRAM$$Base; +extern UINT32 Image$$LOAD_CPOS_IRAM$$Base; +extern UINT32 Image$$LOAD_CPOS_IRAM$$Length; +//////////////////////////////////////// + +///////////// LOAD_CP_PIRAM_CSMB ////////////// +extern UINT32 Load$$LOAD_CP_PIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_CSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_SLP2PIRAM_MSMB ////////////// +extern UINT32 Load$$LOAD_CP_SLP2PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_CP_SLP2PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_CP_SLP2PIRAM_MSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_PIRAM_MSMB ////////////// +extern UINT32 Load$$LOAD_CP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_MSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_FIRAM_CSMB ////////////// +extern UINT32 Load$$LOAD_CP_FIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_FIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_FIRAM_CSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_FIRAM_MSMB ////////////// +extern UINT32 Load$$LOAD_CP_FIRAM_MSMB$$Base; +extern UINT32 Image$$LOAD_CP_FIRAM_MSMB$$Base; +extern UINT32 Image$$LOAD_CP_FIRAM_MSMB$$Length; +///////////////////////////////////////// + + +///////////// LOAD_DRAM_BSP ///////////// +extern UINT32 Load$$LOAD_CPDRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$Length ; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$ZI$$Base; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$ZI$$Limit; +///////////////////////////////////////// + +////////////// LOAD_CPDRAM_SHARED //////// +extern UINT32 Load$$LOAD_CPDRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$Length ; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$ZI$$Base; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$ZI$$Limit; + +extern UINT32 Image$$UNLOAD_NOCACHE$$Base; + +extern UINT32 __StackTop; +extern UINT32 __StackLimit; + + +const mpu_setting_t mpu_region[8] = // eight mpu region at most +{ + // base_addr offset size access cache excute + {0, 0, ARM_MPU_REGION_SIZE_32KB, ARM_MPU_AP_RO, 1, 0}, // cp 0x0-0x8000 + {(UINT32 *)0x8000, 0, ARM_MPU_REGION_SIZE_16KB, ARM_MPU_AP_RO, 1, 0}, // cp 0x8000-0xB000 + {(UINT32 *)0xB000, 0, ARM_MPU_REGION_SIZE_8KB, ARM_MPU_AP_RO, 1, 0}, // cp 0xB000-0xE000 + {(UINT32 *)0x500000, 0, ARM_MPU_REGION_SIZE_128KB, ARM_MPU_AP_RO, 1, 0}, // cp code 0x500000-0x520000 + {(UINT32 *)0x520000, 0, ARM_MPU_REGION_SIZE_32KB, ARM_MPU_AP_RO, 1, 0}, // cp code 0x520000-0x528000 + {(UINT32 *)0x528000, 0, ARM_MPU_REGION_SIZE_16KB, ARM_MPU_AP_RO, 1, 0}, // cp code 0x528000-0x52C000 + {(UINT32 *)0x400000, 0, ARM_MPU_REGION_SIZE_512KB, ARM_MPU_AP_RO, 1, 0}, // ap region 0x400000-0x480000 + #ifdef LOW_SPEED_SERVICE_ONLY + {(UINT32 *)0x480000, 0, ARM_MPU_REGION_SIZE_256KB, ARM_MPU_AP_RO, 1, 0}, // ap region 0x480000-0x4C0000, do not protect upbuffer + #else + {(UINT32 *)0x480000, 0, ARM_MPU_REGION_SIZE_64KB, ARM_MPU_AP_RO, 1, 0}, // ap region 0x480000-0x490000, do not protect upbuffer + #endif +}; + +#pragma GCC push_options +#pragma GCC optimize("O1") + +void SetStackLimitFlag(void) +{ + uint32_t *stack_limit = &__StackLimit; + *stack_limit = 0x44444444; +} + +bool pIramMsmbCopyBeforePaging(void) +{ + uint8_t cpBootFlag = cpmuGetBootFlag(); + if ((CP_BOOT_FROM_CS2 == cpBootFlag) && (TRUE == AonRegGetCpMsmbSlp2RetFlagBeforeInit())) + { + cpmuSetPIRamMSMBCopyFlag(true); + return true; + } + else + { + cpmuSetPIRamMSMBCopyFlag(false); + return false; + } +} + + +void CopyDataRWZIForPhyProcess(void) // may optimise by using different sector +{ + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32 *src; + UINT32 *dst; + UINT32 length; + + dst = &(Image$$LOAD_CPDRAM_BSP$$Base); + src = &(Load$$LOAD_CPDRAM_BSP$$Base); + length = (UINT32)&(Image$$LOAD_CPDRAM_BSP$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + start_addr = &(Image$$LOAD_CPDRAM_BSP$$ZI$$Base) ; + end_addr = &(Image$$LOAD_CPDRAM_BSP$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); + +} + + +// called by CPFullImageInit when power on or transfer to full image from paging image +void SetFullEnvForCPProcess(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + + uint8_t cpBootFlag = CP_BOOT_FROM_POWER_ON; // all data need copy, as we do not know the bootflag before this time + + // when wakeup from CO/CH or CS2 withou Meas, need to copy MSMB_SLP2 when transfer to full image + // for other case, MSMB_SLP2 has been copied in CopyRamCodeForPhyProcess + // when wakeup from paging sleep1, still need to copy code + if(cpmuGetPIRamMSMBCopyFlag() == false) + { + // load_cp_slp2piram_msmb(phyCodeMsmb_SLP2) + dst = &(Image$$LOAD_CP_SLP2PIRAM_MSMB$$Base); + src = &(Load$$LOAD_CP_SLP2PIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_SLP2PIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + switch(cpBootFlag) + { + case CP_BOOT_FROM_POWER_ON: + case CP_BOOT_FROM_CO: + case CP_BOOT_FROM_CH: + { + dst = &(Image$$LOAD_CP_FIRAM_CSMB$$Base); + src = &(Load$$LOAD_CP_FIRAM_CSMB$$Base); + length = (UINT32)&(Image$$LOAD_CP_FIRAM_CSMB$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case CP_BOOT_FROM_CS2: + { + // load_cp_firam_msmb(phyCodeMsmb_XXX) + dst = &(Image$$LOAD_CP_FIRAM_MSMB$$Base); + src = &(Load$$LOAD_CP_FIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_FIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + // load_cpos(CP PLAT code in MSMB) + dst = &(Image$$LOAD_CPOS_IRAM$$Base); + src = &(Load$$LOAD_CPOS_IRAM$$Base); + length = (UINT32)&(Image$$LOAD_CPOS_IRAM$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case CP_BOOT_FROM_CS1: + break; + default: + EC_ASSERT(0, cpBootFlag, 0, 0); + } + + // load_cpdram_shared_data(phyDataMsmb,phyShareDataMsmb) + dst = &(Image$$LOAD_CPDRAM_SHARED$$Base); + src = &(Load$$LOAD_CPDRAM_SHARED$$Base); + length = (UINT32)&(Image$$LOAD_CPDRAM_SHARED$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + // load_cpdram_shared_bss(cpPlatDataMsmb) + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32* stack_len = (UINT32*)(&__StackTop - &__StackLimit); + start_addr = &(Image$$LOAD_CPDRAM_SHARED$$ZI$$Base) ; + end_addr = &(Image$$LOAD_CPDRAM_SHARED$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length-(UINT32)stack_len); + + CopyDataRWZIForPhyProcess(); + +} + + +// called by systemInit when poweron or wakeup from CO/CH/CS2 +void CopyRamCodeForPhyProcess(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + + uint8_t cpBootFlag = cpmuGetBootFlag(); + + switch(cpBootFlag) + { + case CP_BOOT_FROM_POWER_ON: + case CP_BOOT_FROM_CO: + case CP_BOOT_FROM_CH: + { + // load_cp_piram_csmb(phyCodeCsmb_XXX) + dst = &(Image$$LOAD_CP_PIRAM_CSMB$$Base); + src = &(Load$$LOAD_CP_PIRAM_CSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_PIRAM_CSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case CP_BOOT_FROM_CS2: + { + // when PowerOn or SLEEP2 with Meas, MSMB_SLP2 need to copy + if (pIramMsmbCopyBeforePaging() == true) + { + // load_cp_slp2piram_msmb(phyCodeMsmb_SLP2) + dst = &(Image$$LOAD_CP_SLP2PIRAM_MSMB$$Base); + src = &(Load$$LOAD_CP_SLP2PIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_SLP2PIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + + // load_cp_piram_msmb (phyCodeMsmb_HIB) + dst = &(Image$$LOAD_CP_PIRAM_MSMB$$Base); + src = &(Load$$LOAD_CP_PIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_PIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + } + break; + + default: + EC_ASSERT(0, cpBootFlag, 0, 0); + } + +} + +#pragma GCC pop_options + +void mpu_init(void) +{ + int i=0; + uint8_t region_num = 0; + + if(MPU->TYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + + region_num = sizeof(mpu_region)/sizeof(mpu_setting_t); + + for(i=0;iTYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + +} + + diff --git a/PLAT/device/target/board/ec618_0h00/cp/gcc/startup_ec618_gcc.s b/PLAT/device/target/board/ec618_0h00/cp/gcc/startup_ec618_gcc.s new file mode 100644 index 0000000..3b6e79b --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/gcc/startup_ec618_gcc.s @@ -0,0 +1,164 @@ + .syntax unified + .arch armv7-m + .cpu cortex-m3 + +.global __isr_vector +.global Reset_Handler + +.global __StackTop +.global __StackLimit + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x1000 +#endif +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .isr_vector,"a",%progbits + .align 2 + .type __isr_vector, %object + .size __isr_vector, .- __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long CP_SWWakeup_IntHandler /* 0: ap sw */ + .long CP_RTWakeup_IntHandler /* 1: tmu */ + .long CP_BCWakeup_IntHandler /* 2: tmu */ + .long CP_IPC0Wakeup_IntHandler /* 3: ipc */ + .long CP_IPC1Wakeup_IntHandler /* 4: ipc */ + .long CP_IPCMWakeup_IntHandler /* 5: ipc */ + .long CP_SIPCWakeup_IntHandler /* 6: sipc */ + .long CP_APDAPWakeup_IntHandler /* 7: ap dap */ + .long CP_CPDAPWakeup_IntHandler /* 8: cp dap */ + .long 0 /* 9: Reserved */ + .long 0 /* 10: Reserved */ + .long CP_CPUSBIntHandler /* 11: */ + .long XIC_IntHandler /* 12: */ + .long XIC_IntHandler /* 13: */ + + + .text + .thumb + .thumb_func + .align 2 + .type Reset_Handler, %function +Reset_Handler: + + .extern SystemInit + .extern cp_main + .extern bootStack + + ldr r0, =bootStack + adds r0, r0, #512 + msr msp, r0 + + ldr r0, =0x4D000008 /* CP DFC vote false */ + ldr r1, =0x00000000 + str r1, [r0] + + ldr r0, =SystemInit + blx r0 + ldr r0, =cp_main + bx r0 + .size Reset_Handler, .-Reset_Handler + + .thumb + .thumb_func + .align 2 + .type HardFault_Handler, %function +HardFault_Handler: + + .extern excepHardFaultHandler + .extern excepInfoStore + + mrs r1, PRIMASK /* backup PRIMASK */ + mov r0, #1 + msr PRIMASK, r0 + + ldr r12, =excepInfoStore + add r12, r12, #12 + stmia r12!, {r0-r11} + + add r12, r12, #20 + mov r0, lr /* store exc_return */ + stmia r12!, {r0} + + mrs r0, msp /* store msp */ + stmia r12!, {r0} + mrs r0, psp /* store psp */ + stmia r12!, {r0} + + mrs r0, CONTROL + stmia r12!, {r0} + + mrs r0, BASEPRI + stmia r12!, {r0} + mov r0, r1 /* restore PRIMASK */ + stmia r12!, {r0} + mrs r0, FAULTMASK + stmia r12!, {r0} + + mov r0, sp + mrs r1, psp + mov r2, lr + B excepHardFaultHandler + .size HardFault_Handler, .-HardFault_Handler + + .align 1 + .thumb + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, .-Default_Handler + + .macro def_irq_handler handler_name + .weak \handler_name + .thumb_set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler CP_SWWakeup_IntHandler + def_irq_handler CP_RTWakeup_IntHandler + def_irq_handler CP_BCWakeup_IntHandler + def_irq_handler CP_IPC0Wakeup_IntHandler + def_irq_handler CP_IPC1Wakeup_IntHandler + def_irq_handler CP_IPCMWakeup_IntHandler + def_irq_handler CP_SIPCWakeup_IntHandler + def_irq_handler CP_APDAPWakeup_IntHandler + def_irq_handler CP_CPDAPWakeup_IntHandler + def_irq_handler CP_CPUSBIntHandler + def_irq_handler XIC_IntHandler + + .end diff --git a/PLAT/device/target/board/ec618_0h00/cp/gcc/syscalls.c b/PLAT/device/target/board/ec618_0h00/cp/gcc/syscalls.c new file mode 100644 index 0000000..47b6748 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/gcc/syscalls.c @@ -0,0 +1,83 @@ +#include +extern int io_putc(int ch) __attribute__((weak)); +extern int io_getc(void) __attribute__((weak)); + +int _close(int file) +{ + return 0; +} + +int _fstat(int file, struct stat *st) +{ + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(const char *name, int flags, int mode) +{ + return -1; +} + +int _read(int file, char *ptr, int len) +{ + return 0; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = io_getc(); + } + + return len; +} + + +#define __MYPID 1 +int _getpid() +{ + return __MYPID; +} + +/* + * * kill -- go out via exit... + * */ +int _kill(int pid, int sig) +{ + return -1; +} + +void _exit(int val) +{ + while(1); +} + +caddr_t _sbrk(int incr) +{ + + return (caddr_t) - 1; + +} + +int _write(int file, char *ptr, int len) +{ + extern int io_putchar(int ch); + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + io_putchar(*ptr++); + } + return len; +} + + + + + diff --git a/PLAT/device/target/board/ec618_0h00/cp/gcc/version.h b/PLAT/device/target/board/ec618_0h00/cp/gcc/version.h new file mode 100644 index 0000000..b55342f --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/gcc/version.h @@ -0,0 +1,7 @@ + +//EC_CHIP_VERSION---used for cp exception +#define EC_CHIP_VERSION "EcChipVerEc618CoreCp" + +// CP_VERSION: defined according to YYYY|MM|DD +#define EC618_CP_VERSION 0x20220316 + diff --git a/PLAT/device/target/board/ec618_0h00/cp/inc/system_ec618.h b/PLAT/device/target/board/ec618_0h00/cp/inc/system_ec618.h new file mode 100644 index 0000000..144ab0e --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/inc/system_ec618.h @@ -0,0 +1,103 @@ +/**************************************************************************//** + * @file system_ARMCM3.h + * @brief CMSIS Device System Header File for + * ARMCM3 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_CATERPILLER_H +#define SYSTEM_CATERPILLER_H +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#include "commontypedef.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +#define XTAL (204800000U) /* Oscillator frequency */ +#define DEFAULT_SYSTEM_CLOCK (XTAL) +#define SYSTICK_CLOCK (3250000) + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void); + +/** + \brief Save and set IRQ mask. + + Close irq and save current IRQ mask. + */ +static __FORCEINLINE uint32_t SaveAndSetIRQMask(void) +{ + uint32_t mask = __get_PRIMASK(); + __disable_irq(); + return mask; +} + + +/** + \brief Restore IRQ mask. + + Restore IRQ mask and enable irq. + */ +static __FORCEINLINE void RestoreIRQMask(uint32_t mask) +{ + __DSB(); + __ISB(); + __set_PRIMASK(mask); +} + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CATERPILLER_H */ diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash.sct b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash.sct new file mode 100644 index 0000000..cb0498e --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash.sct @@ -0,0 +1,124 @@ +#! armcc -E +#include "..\..\common\inc\mem_map.h" + +LR_CPIROM1 0x00800000 0x80000 { ; load region size_region + UNLOAD_CPVECTOR 0x00800000 0x80000{ + *.o (RESET, +First) + *(.phyCodeFlash_ICS) + *(.phyCodeFlash_UL) + *(.phyCodeFlash_RXDFE) + *(.phyCodeFlash_CE) + *(.phyCodeFlash_AXC) + *(.phyCodeFlash_RF) + *(.phyCodeFlash_ASN1) + *(.phyCodeFlash_SCHD) + *(.phyCodeFlash_MACSF) + *(.phyCodeFlash_MEAS) + *(.phyCodeFlash_PMU) + *(.phyCodeFlash_CCH) + *(.phyCodeFlash_CSI) + *(.phyCodeFlash_DCH) + *(.phyCodeFlash_DEC) + *(.phyCodeFlash_HARQ) + *(.phyCodeFlash_TMU) + *(.phyCodeFlash_COMN) + *(.cpPlatCodeFlash) + *(.phyDataFlash_Const) + .ANY (+RO) + } + LOAD_CP_PIRAM_CSMB 0x20 { ; code in ram + *(.phyCodeCsmb_ICS) + *(.phyCodeCsmb_RXDFE) + *(.phyCodeCsmb_CE) + *(.phyCodeCsmb_AXC) + *(.phyCodeCsmb_RF) + *(.phyCodeCsmb_SCHD) + *(.phyCodeCsmb_MACSF) + *(.phyCodeCsmb_MEAS) + *(.phyCodeCsmb_PMU) + *(.phyCodeCsmb_CCH) + *(.phyCodeCsmb_DCH) + *(.phyCodeCsmb_DEC) + *(.phyCodeCsmb_HARQ) + *(.phyCodeCsmb_TMU) + *(.phyCodeCsmb_COMN) + *(.cpPlatCodeCsmb) + *(.phyDataCsmb_Const) + } + LOAD_CP_FIRAM_CSMB +0 { ; code for full image, but placed on csmb + + } + + UNLOAD_CPCSMBDATA 0xe000 { + *(.phyDataCsmb_Slp2) + } + UNLOAD_CPAONMEM 0xf000 { + *(.phyDataCsmb_AonMemBackup) + } + LOAD_CP_PIRAM_MSMB MSMB_APMEM_END_ADDR { ; start from APMEM END + *(.phyCodeMsmb_SLP2) + *(.recordNodeRO) + } + LOAD_CP_FIRAM_MSMB +0 { + *(.phyFMRamcode) + *(.phyCodeMsmb_ICS) + *(.phyCodeMsmb_UL) + *(.phyCodeMsmb_RXDFE) + *(.phyCodeMsmb_CE) + *(.phyCodeMsmb_AXC) + *(.phyCodeMsmb_RF) + *(.phyCodeMsmb_SCHD) + *(.phyCodeMsmb_MACSF) + *(.phyCodeMsmb_MEAS) + *(.phyCodeMsmb_PMU) + *(.phyCodeMsmb_CCH) + *(.phyCodeMsmb_CSI) + *(.phyCodeMsmb_DCH) + *(.phyCodeMsmb_DEC) + *(.phyCodeMsmb_HARQ) + *(.phyCodeMsmb_TMU) + *(.phyCodeMsmb_COMN) + *(.cpPlatCodeMsmb) + } + LOAD_CPOS_IRAM +0 { + event_groups.o(+RO) + heap_6.o(+RO) + tlsf.o(+RO) + mm_debug.o(+RO) + list.o(+RO) + queue.o(+RO) + tasks.o(+RO) + timers.o(+RO) + port.o(+RO) + port_asm.o(+RO) + cmsis_os2.o(+RO) + } + UNLOAD_SLPMEM +0 { + *(.sleepmem) + } + LOAD_CPDRAM_SHARED +0 { ; RW data + .ANY (+RW +ZI) + } + NOINIT_CPDATA +0 { ; data initialize by phy code, plat do not initialize this area + *(.phyDataMsmb) + } + LOAD_CPDRAM_BSP +0 { ; add driver need run in cp smallimg + gpr.o(+RW +ZI) + clock.o(+RW +ZI) + cpmu.o(+RW +ZI) + cp_main.o(+RW +ZI) + slpman.o(+RW +ZI) + *(.recordNodeZI) + } + + ScatterAssert(ImageLimit(LOAD_CPDRAM_BSP) <= CP_AONMEMBACKUP_START_ADDR) + UNLOAD_CPAON CP_AONMEMBACKUP_START_ADDR { + *.o (.phyDataMsmb_AonMemBackup) + } + LOAD_XP_SHAREDINFO XP_SHAREINFO_BASE_ADDR { + *.o (.shareInfo) + } + UNLOAD_XP_IPCMEM IPC_SHAREDMEM_START_ADDR EMPTY 0x1000{ + + } +} diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash_fpga.sct b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash_fpga.sct new file mode 100644 index 0000000..fda6a3b --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash_fpga.sct @@ -0,0 +1,166 @@ +#! armcc -E +#include "..\..\common\inc\mem_map.h" + +LR_CPIROM1 0x00800000 0x80000 { ; load region size_region + UNLOAD_CPVECTOR 0x00800000 0x80000{ + *.o (RESET, +First) + *(.phyCodeFlash_ICS) + *(.phyCodeFlash_UL) + *(.phyCodeFlash_RXDFE) + *(.phyCodeFlash_CE) + *(.phyCodeFlash_AXC) + *(.phyCodeFlash_RF) + *(.phyCodeFlash_ASN1) + *(.phyCodeFlash_SCHD) + *(.phyCodeFlash_MACSF) + *(.phyCodeFlash_MEAS) + *(.phyCodeFlash_PMU) + *(.phyCodeFlash_OTDOA) + *(.phyCodeFlash_CCH) + *(.phyCodeFlash_CSI) + *(.phyCodeFlash_DCH) + *(.phyCodeFlash_DEC) + *(.phyCodeFlash_HARQ) + *(.phyCodeFlash_TMU) + *(.phyCodeFlash_COMN) + *(.cpPlatCodeFlash) + *(.phyDataFlash) + .ANY (+RO) + } + LOAD_CP_PIRAM_CSMB 0x20 { ; code in ram + *(.phyCodeCsmb0_ICS) + *(.phyCodeCsmb0_UL) + *(.phyCodeCsmb0_RXDFE) + *(.phyCodeCsmb0_CE) + *(.phyCodeCsmb0_AXC) + *(.phyCodeCsmb0_RF) + *(.phyCodeCsmb0_SCHD) + *(.phyCodeCsmb0_MACSF) + *(.phyCodeCsmb0_MEAS) + *(.phyCodeCsmb0_PMU) + *(.phyCodeCsmb0_OTDOA) + *(.phyCodeCsmb0_CCH) + *(.phyCodeCsmb0_CSI) + *(.phyCodeCsmb0_DCH) + *(.phyCodeCsmb0_DEC) + *(.phyCodeCsmb0_HARQ) + *(.phyCodeCsmb0_TMU) + *(.phyCodeCsmb0_COMN) + *(.cpPlatCodeCsmb0) + *(.phyDataCsmb0) + } + LOAD_CP_FIRAM_CSMB +0 { ; code for full image, but placed on csmb + *(.phyCodeCsmb1_ICS) + *(.phyCodeCsmb1_UL) + *(.phyCodeCsmb1_RXDFE) + *(.phyCodeCsmb1_CE) + *(.phyCodeCsmb1_AXC) + *(.phyCodeCsmb1_RF) + *(.phyCodeCsmb1_SCHD) + *(.phyCodeCsmb1_MACSF) + *(.phyCodeCsmb1_MEAS) + *(.phyCodeCsmb1_PMU) + *(.phyCodeCsmb1_OTDOA) + *(.phyCodeCsmb1_CCH) + *(.phyCodeCsmb1_CSI) + *(.phyCodeCsmb1_DCH) + *(.phyCodeCsmb1_DEC) + *(.phyCodeCsmb1_HARQ) + *(.phyCodeCsmb1_TMU) + *(.phyCodeCsmb1_COMN) + *(.cpPlatCodeCsmb1) + } + LOAD_CP_DATA_CSMB +0 { ; + *(.phyDataCsmb) + } + + UNLOAD_CPCSMBDATA 0xe000 { + *(.phyDataCsmb1) + } + UNLOAD_CPAONMEM 0xf000 { + *(.phyAonMemBackupCsmb) + } + LOAD_CP_PIRAM_MSMB MSMB_APMEM_END_ADDR { ; start from APMEM END + *(.phyCodeMsmb0_ICS) + *(.phyCodeMsmb0_UL) + *(.phyCodeMsmb0_RXDFE) + *(.phyCodeMsmb0_CE) + *(.phyCodeMsmb0_AXC) + *(.phyCodeMsmb0_RF) + *(.phyCodeMsmb0_SCHD) + *(.phyCodeMsmb0_MACSF) + *(.phyCodeMsmb0_MEAS) + *(.phyCodeMsmb0_PMU) + *(.phyCodeMsmb0_OTDOA) + *(.phyCodeMsmb0_CCH) + *(.phyCodeMsmb0_CSI) + *(.phyCodeMsmb0_DCH) + *(.phyCodeMsmb0_DEC) + *(.phyCodeMsmb0_HARQ) + *(.phyCodeMsmb0_TMU) + *(.phyCodeMsmb0_COMN) + *(.cpPlatCodeMsmb0) + } + LOAD_CP_FIRAM_MSMB +0 { + *(.phyFMRamcode) + *(.phyCodeMsmb1_ICS) + *(.phyCodeMsmb1_UL) + *(.phyCodeMsmb1_RXDFE) + *(.phyCodeMsmb1_CE) + *(.phyCodeMsmb1_AXC) + *(.phyCodeMsmb1_RF) + *(.phyCodeMsmb1_SCHD) + *(.phyCodeMsmb1_MACSF) + *(.phyCodeMsmb1_MEAS) + *(.phyCodeMsmb1_PMU) + *(.phyCodeMsmb1_OTDOA) + *(.phyCodeMsmb1_CCH) + *(.phyCodeMsmb1_CSI) + *(.phyCodeMsmb1_DCH) + *(.phyCodeMsmb1_DEC) + *(.phyCodeMsmb1_HARQ) + *(.phyCodeMsmb1_TMU) + *(.phyCodeMsmb1_COMN) + *(.cpPlatCodeMsmb1) + *(.recordNodeRO) + } + LOAD_CPOS_IRAM +0 { + event_groups.o(+RO) + heap_6.o(+RO) + list.o(+RO) + queue.o(+RO) + tasks.o(+RO) + timers.o(+RO) + port.o(+RO) + port_asm.o(+RO) + cmsis_os2.o(+RO) + } + UNLOAD_SLPMEM +0 { + *(.sleepmem) + } + LOAD_CPDRAM_SHARED +0 { ; RW data + *(.phyDataMsmb) + *(.phyWifiDataMsmb) + .ANY (+RW +ZI) + } + + LOAD_CPDRAM_BSP +0 { ; add driver need run in cp smallimg + gpr.o(+RW +ZI) + clock.o(+RW +ZI) + cpmu.o(+RW +ZI) + cp_main.o(+RW +ZI) + slpman.o(+RW +ZI) + *(.recordNodeZI) + } + + ScatterAssert(ImageLimit(LOAD_CPDRAM_BSP) <= CP_AONMEMBACKUP_START_ADDR) + UNLOAD_CPAON CP_AONMEMBACKUP_START_ADDR { + *.o (.phyAonMemBackupMsmb) + } + LOAD_XP_SHAREDINFO XP_SHAREINFO_BASE_ADDR { + *.o (.shareInfo) + } + UNLOAD_XP_IPCMEM IPC_SHAREDMEM_START_ADDR EMPTY 0x1000{ + + } +} diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash_soc_clkTest.sct b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash_soc_clkTest.sct new file mode 100644 index 0000000..98dc43a --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_flash_soc_clkTest.sct @@ -0,0 +1,74 @@ +#! armcc -E +#include "..\..\common\inc\mem_map.h" + +LR_CPIROM1 0x00000 0x10000 { ; load region size_region + + LOAD_CPVECTOR 0x00000 0x10000{ + *.o (RESET, +First) + } + LOAD_CP_PIRAM_CSMB +0 { ; code in ram + } + + + LOAD_CP_FIRAM_CSMB +0 { ; code for full image, but placed on csmb + } + UNLOAD_CPIROM +0 { ; load address = execution address + *(.phyCodeFlash_COMN) + *(.phyCodeFlash_ICS) + *(.phyCodeFlash_UL) + *(.phyCodeFlash_RXDFE) + *(.phyCodeFlash_CE) + *(.phyCodeFlash_DE) + *(.phyCodeFlash_AXC) + *(.phyCodeFlash_RF) + *(.phyCodeFlash_ASN1) + *(.phyCodeFlash_SCHD) + *(.phyCodeFlash_MACSF) + *(.phyCodeFlash_MEAS) + *(.phyCodeFlash_PMU) + *(.phyCodeFlash_OTDOA) + .(.phyCodeFlash_SQ) + *(.phyDataFlash) + *(.phyCodeMsmb0) + *(.phyCodeMsmb1) + .ANY (+RO) + } + + LOAD_CPIRAM1 +0 { ; code in ram + *(.phyCodeCsmb0) + *(.ramCode) + } + LOAD_CPIRAM2 +0 { ; code in ram + *(.phyCodeCsmb1) + *(.ramCode2) + } + LOAD_CPOS_IRAM +0 { + event_groups.o(+RO) + heap_4.o(+RO) + list.o(+RO) + queue.o(+RO) + tasks.o(+RO) + timers.o(+RO) + port.o(+RO) + port_asm.o(+RO) + cmsis_os2.o(+RO) + } + + + LOAD_CPDRAM_SHARED +0 { ; RW data + *(.phyDataZI) + .ANY (+RW +ZI) + } + LOAD_CPDRAM_BSP +0 { ; add driver need run in cp smallimg + + } + LOAD_CP_FIRAM_MSMB MSMB_APMEM_END_ADDR { ; start from APMEM END + } + LOAD_BLOCK5_SHARED 0x4E0000 { + *(.mpram4) + } + + UNLOAD_DBGDATA_AREA 0x500000 0x40000 { ; phyDebug Area + + } +} diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_ram_fpga.sct b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_ram_fpga.sct new file mode 100644 index 0000000..6464e0b --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/ec618_0h00_ram_fpga.sct @@ -0,0 +1,63 @@ +#! armcc -E +#include "mem_map.h" + +LR_CPIROM1 0x480000 0x60000 { ; load region size_region + + LOAD_CPVECTOR 0x480000 0x60000{ + *.o (RESET, +First) + } + UNLOAD_CPIROM +0 { ; load address = execution address + *(.phyCodeFlash_COMN) + *(.phyCodeFlash_ICS) + *(.phyCodeFlash_UL) + *(.phyCodeFlash_RXDFE) + *(.phyCodeFlash_CE) + *(.phyCodeFlash_DE) + *(.phyCodeFlash_AXC) + *(.phyCodeFlash_RF) + *(.phyCodeFlash_ASN1) + *(.phyCodeFlash_SCHD) + *(.phyCodeFlash_MACSF) + *(.phyCodeFlash_MEAS) + *(.phyCodeFlash_PMU) + *(.phyCodeFlash_OTDOA) + .(.phyCodeFlash_SQ) + *(.phyDataFlash) + *(.phyCodeMsmb0) + *(.phyCodeMsmb1) + .ANY (+RO) + } + + LOAD_CPIRAM1 +0 { ; code in ram + *(.phyCodeCsmb0) + *(.ramCode) + } + LOAD_CPIRAM2 +0 { ; code in ram + *(.phyCodeCsmb1) + *(.ramCode2) + } + LOAD_CPOS_IRAM +0 { + event_groups.o(+RO) + heap_4.o(+RO) + list.o(+RO) + queue.o(+RO) + tasks.o(+RO) + timers.o(+RO) + port.o(+RO) + port_asm.o(+RO) + cmsis_os2.o(+RO) + } + + + LOAD_CPDRAM_SHARED 0x4E0000 0x20000 { ; RW data + *(.phyDataZI) + .ANY (+RW +ZI) + } + LOAD_DRAM_BSP +0 { ; add driver need run in cp smallimg + + } + + UNLOAD_DBGDATA_AREA 0x500000 0x40000 { ; phyDebug Area + + } +} diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/prec_init.c b/PLAT/device/target/board/ec618_0h00/cp/keil/prec_init.c new file mode 100644 index 0000000..f3b739a --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/prec_init.c @@ -0,0 +1,351 @@ +#include +#include "commontypedef.h" +#include "ec618_internal.h" +#include "cache.h" +#include "mpu_armv7.h" +#include "mem_map.h" +#include "cpmu.h" +#include "exception_process.h" + +typedef struct +{ + UINT32 *base_addr; + INT32 offset; + UINT32 size; + UINT8 access_permission; + UINT8 cacheable; + UINT8 excute_disabled; +}mpu_setting_t; + + + +__asm void __fast_memset(UINT32 *dst, UINT32 value, UINT32 length) +{ + push {r4-r9} + cmp r2, #0 + beq memset_return + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + and r8, r2,#0xf + mov r9, r8 + cmp r8, #0 + beq clr_16Byte +clr_4Byte + stmia r0!,{r4} + subs r8,r8,#4 + cmp r8,#0 + bne clr_4Byte + sub r2,r2,r9 +clr_16Byte + stmia r0!,{r4,r5,r6,r7} + subs r2,r2,#16 + cmp r2,#0 + bne clr_16Byte +memset_return + pop {r4-r9} + bx lr +} + + +#if defined(__CC_ARM) + + +////////// LOAD_CPVECTOR /////////////// +// copy by ap code before cp power on // +//////////////////////////////////////// + +////////// LOAD_CPOS_IRAM ////////////// +extern UINT32 Load$$LOAD_CPOS_IRAM$$Base; +extern UINT32 Image$$LOAD_CPOS_IRAM$$Base; +extern UINT32 Image$$LOAD_CPOS_IRAM$$Length; +//////////////////////////////////////// + +///////////// LOAD_CP_PIRAM_CSMB ////////////// +extern UINT32 Load$$LOAD_CP_PIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_CSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_PIRAM_MSMB ////////////// +extern UINT32 Load$$LOAD_CP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_MSMB$$Base ; +extern UINT32 Image$$LOAD_CP_PIRAM_MSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_FIRAM_CSMB ////////////// +extern UINT32 Load$$LOAD_CP_FIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_FIRAM_CSMB$$Base ; +extern UINT32 Image$$LOAD_CP_FIRAM_CSMB$$Length ; +///////////////////////////////////////// + +///////////// LOAD_CP_FIRAM_MSMB ////////////// +extern UINT32 Load$$LOAD_CP_FIRAM_MSMB$$Base; +extern UINT32 Image$$LOAD_CP_FIRAM_MSMB$$Base; +extern UINT32 Image$$LOAD_CP_FIRAM_MSMB$$Length; +///////////////////////////////////////// + + +///////////// LOAD_DRAM_BSP ///////////// +extern UINT32 Load$$LOAD_CPDRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$Length ; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$ZI$$Base; +extern UINT32 Image$$LOAD_CPDRAM_BSP$$ZI$$Limit; +///////////////////////////////////////// + +////////////// LOAD_CPDRAM_SHARED //////// +extern UINT32 Load$$LOAD_CPDRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$Base ; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$Length ; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$ZI$$Base; +extern UINT32 Image$$LOAD_CPDRAM_SHARED$$ZI$$Limit; +extern UINT32 Stack_Size; + + +#endif + +const mpu_setting_t mpu_region[] = +{ + // base_addr offset size access cache excute + {0, 0, ARM_MPU_REGION_SIZE_32KB, ARM_MPU_AP_RO, 1, 0}, // cp 0x0-0x8000 +// {(UINT32 *)MSMB_START_ADDR, 0, ARM_MPU_REGION_SIZE_512KB, ARM_MPU_AP_RO, 1, 0}, // ap region 0x400000-0x480000, do not protect upbuffer +// {(UINT32 *)0x500000, 0, ARM_MPU_REGION_SIZE_16KB, ARM_MPU_AP_RO, 1, 0}, // cp code 0x500000-0x504000 + +}; + + +void CopyDataRWZIForPhyProcess(void) // may optimise by using different sector +{ + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32 *src; + UINT32 *dst; + UINT32 length; + + dst = &(Image$$LOAD_CPDRAM_BSP$$Base); + src = &(Load$$LOAD_CPDRAM_BSP$$Base); + length = (UINT32)&(Image$$LOAD_CPDRAM_BSP$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + start_addr = &(Image$$LOAD_CPDRAM_BSP$$ZI$$Base) ; + end_addr = &(Image$$LOAD_CPDRAM_BSP$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length); + +} + + +void SetFullEnvForCPProcess(void) +{ + + UINT32 *src; + UINT32 *dst; + UINT32 length; + +#if defined(__CC_ARM) + uint8_t cpBootFlag = cpmuGetBootFlag(); + + if(AonRegGetCPSlpInPaging() == true) // last time sleep in paging, so all fullimage code need copy + { + cpBootFlag = CP_BOOT_FROM_CO; + } + + switch(cpBootFlag) + { + case CP_BOOT_FROM_POWER_ON: + case CP_BOOT_FROM_CO: + case CP_BOOT_FROM_CH: + { + dst = &(Image$$LOAD_CP_FIRAM_CSMB$$Base); + src = &(Load$$LOAD_CP_FIRAM_CSMB$$Base); + length = (UINT32)&(Image$$LOAD_CP_FIRAM_CSMB$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case CP_BOOT_FROM_CS2: + { + dst = &(Image$$LOAD_CP_FIRAM_MSMB$$Base); + src = &(Load$$LOAD_CP_FIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_FIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + dst = &(Image$$LOAD_CPOS_IRAM$$Base); + src = &(Load$$LOAD_CPOS_IRAM$$Base); + length = (UINT32)&(Image$$LOAD_CPOS_IRAM$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + break; + + default: + EC_ASSERT(0, cpBootFlag, 0, 0); + } + + + DisableICache(); // flush cache when ramcode update + EnableICache(); + + dst = &(Image$$LOAD_CPDRAM_SHARED$$Base); + src = &(Load$$LOAD_CPDRAM_SHARED$$Base); + length = (UINT32)&(Image$$LOAD_CPDRAM_SHARED$$Length); + length /= sizeof(UINT32); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + + UINT32 *start_addr; + UINT32 *end_addr ; + UINT32* stack_len = &(Stack_Size); + start_addr = &(Image$$LOAD_CPDRAM_SHARED$$ZI$$Base) ; + end_addr = &(Image$$LOAD_CPDRAM_SHARED$$ZI$$Limit); + length = (UINT32)end_addr - (UINT32)start_addr; + __fast_memset((UINT32 *)start_addr, 0, length-(UINT32)stack_len); + + CopyDataRWZIForPhyProcess(); + +#endif +} + + +void CopyRamCodeForPhyProcess(void) +{ + UINT32 *src; + UINT32 *dst; + UINT32 length; + +#if defined(__CC_ARM) + + uint8_t cpBootFlag = cpmuGetBootFlag(); + + switch(cpBootFlag) + { + case CP_BOOT_FROM_POWER_ON: + case CP_BOOT_FROM_CO: + case CP_BOOT_FROM_CH: + { + dst = &(Image$$LOAD_CP_PIRAM_CSMB$$Base); + src = &(Load$$LOAD_CP_PIRAM_CSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_PIRAM_CSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + case CP_BOOT_FROM_CS2: + { + dst = &(Image$$LOAD_CP_PIRAM_MSMB$$Base); + src = &(Load$$LOAD_CP_PIRAM_MSMB$$Base); + length = (unsigned int)&(Image$$LOAD_CP_PIRAM_MSMB$$Length); + length /= sizeof(unsigned int); + + if(dst != src) + { + while(length >0) + { + dst[length-1]=src[length-1]; + length--; + } + } + } + break; + + default: + EC_ASSERT(0, cpBootFlag, 0, 0); + } + + DisableICache(); // flush cache when ramcode update + EnableICache(); + +#endif + +} + + +void mpu_init(void) +{ + int i=0; + uint8_t region_num = 0; + + if(MPU->TYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + + region_num = sizeof(mpu_region)/sizeof(mpu_setting_t); + + for(i=0;iTYPE==0) + return; + + ARM_MPU_Disable(); + + for(i=0;i<8;i++) + ARM_MPU_ClrRegion(i); + +} + + diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/startup_ec618.s b/PLAT/device/target/board/ec618_0h00/cp/keil/startup_ec618.s new file mode 100644 index 0000000..a78cbcf --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/startup_ec618.s @@ -0,0 +1,303 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + EXPORT Stack_Size +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +;Heap_Size EQU 0x00000C00 +; +; AREA HEAP, NOINIT, READWRITE, ALIGN=3 +;__heap_base +;Heap_Mem SPACE Heap_Size +;__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD CP_SWWakeup_IntHandler ; 0: ap sw + DCD CP_RTWakeup_IntHandler ; 1: tmu + DCD CP_BCWakeup_IntHandler ; 2: tmu + DCD CP_IPC0Wakeup_IntHandler ; 3: ipc + DCD CP_IPC1Wakeup_IntHandler ; 4: ipc + DCD CP_IPCMWakeup_IntHandler ; 5: ipc + DCD CP_SIPCWakeup_IntHandler ; 6: sipc + DCD CP_APDAPWakeup_IntHandler ; 7: ap dap + DCD CP_CPDAPWakeup_IntHandler ; 8: cp dap + DCD 0 ; 9: Reserved + DCD 0 ; 10: Reserved + DCD CP_CPUSBIntHandler ; 11: Reserved + DCD XIC_IntHandler ; 12: + DCD XIC_IntHandler ; 13: + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT cp_main + IMPORT bootStack + + LDR R0,=bootStack + ADDS R0,R0,#512 + MSR MSP,R0 + + LDR R0, =SystemInit + BLX R0 + LDR R0, =cp_main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler\ + PROC + IMPORT excepHardFaultHandler + IMPORT excepInfoStore + EXPORT HardFault_Handler [WEAK] + + mrs r1, PRIMASK ;;backup PRIMASK + mov r0, #1 + msr PRIMASK, r0 + ldr r12, =excepInfoStore + ldr r0, =0xf2f0f1f3 + stmia r12!, {r0} + ldr r0, =0xe2e0e1e3 + stmia r12!, {r0} + add r12, r12, #8 + stmia r12!, {r0-r11} + + add r12, r12, #20 + mov r0, lr ;;store exc_return + stmia r12!, {r0} + + mrs r0, msp ;;store msp + stmia r12!, {r0} + mrs r0, psp ;;store psp + stmia r12!, {r0} + + mrs r0, CONTROL + stmia r12!, {r0} + + mrs r0, BASEPRI + stmia r12!, {r0} + mov r0, r1 ;;restore PRIMASK + stmia r12!, {r0} + mrs r0, FAULTMASK + stmia r12!, {r0} + + mov r0, sp + mrs r1, psp + mov r2, lr + B excepHardFaultHandler + ENDP + +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + BL Default_Handler + B . + ENDP + +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + BL Default_Handler + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + BL Default_Handler + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +CP_SWWakeup_IntHandler PROC + EXPORT CP_SWWakeup_IntHandler [WEAK] + B . + ENDP +CP_RTWakeup_IntHandler PROC + EXPORT CP_RTWakeup_IntHandler [WEAK] + B . + ENDP +CP_BCWakeup_IntHandler PROC + EXPORT CP_BCWakeup_IntHandler [WEAK] + B . + ENDP +CP_IPC0Wakeup_IntHandler PROC + EXPORT CP_IPC0Wakeup_IntHandler [WEAK] + B . + ENDP +CP_IPC1Wakeup_IntHandler PROC + EXPORT CP_IPC1Wakeup_IntHandler [WEAK] + B . + ENDP +CP_IPCMWakeup_IntHandler PROC + EXPORT CP_IPCMWakeup_IntHandler [WEAK] + B . + ENDP +CP_SIPCWakeup_IntHandler PROC + EXPORT CP_SIPCWakeup_IntHandler [WEAK] + B . + ENDP +CP_APDAPWakeup_IntHandler PROC + EXPORT CP_APDAPWakeup_IntHandler [WEAK] + B . + ENDP +CP_CPDAPWakeup_IntHandler PROC + EXPORT CP_CPDAPWakeup_IntHandler [WEAK] + B . + ENDP +CP_CPUSBIntHandler PROC + EXPORT CP_CPUSBIntHandler [WEAK] + B . + ENDP +XIC_IntHandler PROC + EXPORT XIC_IntHandler [WEAK] + B . + ENDP +Default_Handler PROC + B . + ENDP + + + + +__clr_240K_mem PROC + MOVS R0, #0 + STM R6!,{R0} + ADDS R5, R5, #1 + CMP R5, #0xEC00 + BCC __clr_240K_mem + LDR R0, =0x08080000 + LDR SP, [R0,#0] + MOVS LR, R7 + BX LR + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + +; IF :DEF:__MICROLIB + + EXPORT __initial_sp +; EXPORT __heap_base +; EXPORT __heap_limit + +; ELSE + +; IMPORT __use_two_region_memory +; EXPORT __user_initial_stackheap + +;__user_initial_stackheap PROC +; LDR R0, = Heap_Mem +; LDR R1, =(Stack_Mem + Stack_Size) +; LDR R2, = (Heap_Mem + Heap_Size) +; LDR R3, = Stack_Mem +; BX LR +; ENDP + +; ALIGN + +; ENDIF + + + END diff --git a/PLAT/device/target/board/ec618_0h00/cp/keil/version.h b/PLAT/device/target/board/ec618_0h00/cp/keil/version.h new file mode 100644 index 0000000..b76c1b5 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/keil/version.h @@ -0,0 +1,7 @@ +#define SDK_MAJOR_VERSION "001" // For Major version +#define SDK_MINOR_VERSION "027" // For minor version +#define SDK_RA_VERSION "xxx" // For jenkins release use +#define SDK_PATCH_VERSION "000" // For patch verion, modify when patch release + +#define EVB_MAJOR_VERSION "1" +#define EVB_MINOR_VERSION "0" diff --git a/PLAT/device/target/board/ec618_0h00/cp/src/system_ec618.c b/PLAT/device/target/board/ec618_0h00/cp/src/system_ec618.c new file mode 100644 index 0000000..c63db14 --- /dev/null +++ b/PLAT/device/target/board/ec618_0h00/cp/src/system_ec618.c @@ -0,0 +1,177 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ec618_internal.h" +#include "mpu_armv7.h" +#include "driver_common.h" +#include "cache.h" +#include "mem_map.h" +#include "slpman.h" +#include "aonreg.h" +#include "cpmureg.h" +#include "cpmu.h" + +#define SYS_ADDRESS CP_FLASH_LOAD_ADDR + + + +extern void mpu_init(void); +extern void mpu_deinit(void); +extern void SetFullEnvForCPProcess(void); +extern void CopyRamCodeForPhyProcess(void); +extern void CopyDataRWZIForPhyProcess(void); +extern void SetStackLimitFlag(void); + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__CC_ARM) + extern uint32_t __Vectors; +#elif defined(__GNUC__) + extern uint32_t __isr_vector; +#endif +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +#define CORE_CLOCK_REGISER_ADDRESS (0x4d000020) +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ +#ifdef FPGA_TEST + SystemCoreClock = 102400000U; +#else + GPR_apAccessEnter(); + switch((*((uint32_t *)CORE_CLOCK_REGISER_ADDRESS)) & 0x3) + { + case 0: + SystemCoreClock = 26000000U; + break; + case 1: + SystemCoreClock = 204800000U; + break; + case 2: + SystemCoreClock = 102400000U; + break; + case 3: + SystemCoreClock = 32768U; + break; + } + GPR_apAccessExit(); +#endif +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void CPFullImageInit (void) +{ + mpu_deinit(); + + SetFullEnvForCPProcess(); + + SystemCoreClockUpdate (); + + mpu_init(); + + DisableICache(); // flush cache when ramcode update + + EnableICache(); +} + + +void SystemInit (void) +{ + bool powerFlag; + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__CC_ARM) + SCB->VTOR = (uint32_t) &__Vectors; +#elif defined (__GNUC__) + SCB->VTOR = (uint32_t) &__isr_vector; +#endif +#endif + + DisableICache(); + + EnableICache(); + + //// set clk on temporary ///// +#if 0 + (*(uint32_t *)0x50000008) = 0x1; + + GPR_RMI->XP2YPACCESS |= 3; + ///////////////////// +#endif + +#ifdef FEATURE_DUMP_CHECK + EXCEP_CHECK_POINT(80); +#endif + + powerFlag = cpmuRegGetPowerFlagBeforeInit(); + + cpmuRestoreBootFlagBeforeInit(); + + if((powerFlag != true) && (cpmuIsWakeupFromCS2() || cpmuIsWakeupFromCOCH() || cpmuIsFromPowerOn())) + { +#ifdef FEATURE_DUMP_CHECK + if(cpmuIsWakeupFromCS2()) + { + EXCEP_CHECK_POINT(88); + } +#endif + CopyRamCodeForPhyProcess(); + + CopyDataRWZIForPhyProcess(); + } + + SetStackLimitFlag(); + + mpu_init(); + + DisableICache(); // flush cache when ramcode update + + EnableICache(); + + /*set NVIC priority group as 4(bits 7,6,5 is group priority bits ), + 3 bits for group priority. Since our CM3 core only implemented 3 + bits for priority and freertos recommend all bits should be + group priority bits*/ + NVIC_SetPriorityGrouping(4); + + //enable div 0 trap,then div 0 operation will trigger hardfault + SCB->CCR|=SCB_CCR_DIV_0_TRP_Msk; + + SystemCoreClockUpdate(); + +} + diff --git a/PLAT/driver/board/ec618_0h00/inc/audio/codecDrv.h b/PLAT/driver/board/ec618_0h00/inc/audio/codecDrv.h new file mode 100644 index 0000000..dfa8c50 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/audio/codecDrv.h @@ -0,0 +1,36 @@ +#ifndef BSP_CODECDRV_H +#define BSP_CODECDRV_H + +#include "i2s.h" + + +typedef enum +{ + ES8388, ///< Codec ES8388 + NAU88C22, ///< Codec NAU88C22 + ES7148, ///< Codec ES7148 + ES7149, ///< Codec ES7149 + ES8311, ///< Codec ES8311 +}codecType_e; + +typedef struct +{ + uint8_t regAddr; ///< Register addr + uint16_t regVal; ///< Register value +}i2sI2cCfg_t; + + +/** + \brief Write value to codec via I2C. + \param[in] codecType The codec type you use. + \param[in] regAddr I2C register addr. + \param[in] regVal I2C register value that need to write. + \return +*/ +void codecWriteVal(codecType_e codecType, uint8_t regAddr, uint16_t regVal); +uint8_t codecReadVal(codecType_e codecType, uint8_t regAddr); +//void codecCtrlVolume(codecType_e codecType, bool raise, uint8_t step); + + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/bsp.h b/PLAT/driver/board/ec618_0h00/inc/bsp.h new file mode 100644 index 0000000..8bd6439 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/bsp.h @@ -0,0 +1,77 @@ +#ifndef BSP_H +#define BSP_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "version.h" +#include "Driver_Common.h" +#include "Driver_I2C.h" +#include "Driver_SPI.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "pad.h" +#include "gpio.h" +#include "ic.h" +#include "dma.h" +#include "clock.h" + +#define STRING_EOL "\r\n" +#define BOARD_NAME "EC618_EVK" + +#define SDK_VERSION "EC618_SW_V"SDK_MAJOR_VERSION"."SDK_MINOR_VERSION"."SDK_PATCH_VERSION +#define EVB_VERSION "EC618_HW_V"EVB_MAJOR_VERSION"."EVB_MINOR_VERSION +#define VERSION_INFO "-- SDK Version: "SDK_VERSION" -- "STRING_EOL"-- EVB Version: "EVB_VERSION" -- "STRING_EOL + +#define BSP_HEADER STRING_EOL"-- Board: "BOARD_NAME " -- "STRING_EOL \ + VERSION_INFO \ + "-- Compiled: "__DATE__" "__TIME__" -- "STRING_EOL + +#define ATI_VERSION_INFO STRING_EOL"-- Board: "BOARD_NAME " -- "STRING_EOL \ + "-- SDK Version: "SDK_VERSION" -- "STRING_EOL + +#define SOFTVERSION "V"SDK_MAJOR_VERSION"."SDK_MINOR_VERSION"."SDK_PATCH_VERSION + + +#define CREATE_SYMBOL(name, port) name##port + +/** @brief UART port index + * | UART port | Hardware Flow Control | + * |-----------|-----------------------| + * | UART0 | Y | + * | UART1 | Y | + * | UART2 | N | + */ +typedef enum usart_port +{ + PORT_USART_0, /**< USART port 0. */ + PORT_USART_1, /**< USART port 1. */ + PORT_USART_2, /**< USART port 2. */ + PORT_USART_MAX, /**< The total number of USART ports (invalid UART port number). */ + PORT_USART_INVALID /**< USART invalid. */ +} usart_port_t; + +extern ARM_DRIVER_USART *UsartPrintHandle; +extern ARM_DRIVER_USART *UsartUnilogHandle; +extern ARM_DRIVER_USART *UsartAtCmdHandle; + +/** @brief IRQ Callback functions + */ +typedef void (*IRQ_Callback_t)(); + + +uint8_t* getBuildInfo(void); +uint8_t* getATIVersionInfo(void); +uint8_t* getVersionInfo(void); +void FlushUnilogOutput(void); +void SetUnilogUart(usart_port_t port, uint32_t baudrate, bool startRecv); +void BSP_CommonInit(void); +void setOSState(uint8_t state); +uint8_t * getDebugDVersion(void); +void delay_us(uint32_t us); + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_H */ diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/bf30a2/bf30a2.h b/PLAT/driver/board/ec618_0h00/inc/camera/bf30a2/bf30a2.h new file mode 100644 index 0000000..80e27d1 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/bf30a2/bf30a2.h @@ -0,0 +1,9 @@ +#ifndef BF30A2_H +#define BF30A2_H + +#define BF30A2_I2C_ADDR 0x6e + +uint16_t bf30a2GetRegCnt(char* regName); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/cameraDrv.h b/PLAT/driver/board/ec618_0h00/inc/camera/cameraDrv.h new file mode 100644 index 0000000..c700e86 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/cameraDrv.h @@ -0,0 +1,170 @@ +#ifndef __CAMERA_DRV_H__ +#define __CAMERA_DRV_H__ + +#include "cspi.h" +#include "sp0A39.h" +#include "sp0821.h" +#include "gc6123.h" +#include "gc032A.h" +#include "bf30a2.h" +#include "gc6153.h" + +#ifdef __USER_CODE__ +#ifndef CAM_CHAIN_COUNT +#define CAMERA_ENABLE_BF30A2 1 +#define BF30A2_1SDR 1 +#define CAM_CHAIN_COUNT CAM_8W +#endif +#endif + +/** + \addtogroup cam_interface_gr + \{ + */ + +typedef struct +{ + uint8_t regAddr; ///< Sensor I2C register address + uint8_t regVal; ///< Sensor I2C register value +}camI2cCfg_t; + +typedef enum +{ + LSB_MODE = 0, ///< Little endian + MSB_MODE = 1, ///< Big endian +}endianMode_e; + +typedef enum +{ + WIRE_1 = 0, ///< 1 wire + WIRE_2 = 1, ///< 2 wire +}wireNum_e; + + +typedef enum +{ + SEQ_0 = 0, ///< rxd[0] 6 4 2 0 + ///< rxd[1] 7 5 3 1 + SEQ_1 = 1, ///< rxd[1] 6 4 2 0 + ///< rxd[0] 7 5 3 1 +}rxSeq_e; + +typedef enum +{ + CSPI_0 = 0, + CSPI_1 = 1, +}cspiInstance_e; + +typedef enum +{ + CSPI_START = 1, ///< cspi enable + CSPI_STOP = 0, ///< Cspi disable +}cspiStartStop_e; + +typedef enum +{ + CSPI_INT_ENABLE = 1, ///< cspi interrupt enable + CSPI_INT_DISABLE = 0, ///< Cspi interrupt disable +}cspiIntEnable_e; + + +typedef struct +{ + endianMode_e endianMode; ///< Endian mode + wireNum_e wireNum; ///< Wire numbers + rxSeq_e rxSeq; ///< Bit sequence in 2 wire mode + uint8_t cpol; + uint8_t cpha; + uint8_t yOnly; + uint8_t rowScaleRatio; + uint8_t colScaleRatio; + uint8_t scaleBytes; +}camParamCfg_t; + +typedef void (*camCbEvent_fn) (uint32_t event); ///< Camera callback event. +typedef void (*camIrq_fn)(void); ///< Camera irq + + +/** + \brief Init camera, include pinMux, and enable clock. + \param[in] dataAddr Mem addr to store picture. + \param[in] cb Indicate that a picture has been taken. + \return +*/ +void camInit(void* dataAddr, camCbEvent_fn cb); + +/** + \brief Receive the picture has been taken. + \param[out] dataIn The buffer which is used to store the picture. + \return +*/ +void camRecv(uint8_t * dataIn); + +/** + \brief Init sensor's registers. + \return +*/ +void camRegCfg(void); + +/** + \brief Write some parameters into the sensor. + \param[in] regInfo Sensor I2C addr and value. + \return +*/ +void camWriteReg(camI2cCfg_t* regInfo); + +/** + \brief Read from the sensor's I2C address. + \param[in] regAddr Sensor's I2C register address. + \return +*/ +uint8_t camReadReg(uint8_t regAddr); + +/** + \brief Start or stop Camera controller. + \param[in] startStop If true, start camera controller. If false, stop camera controller. + \return +*/ +void camStartStop(cspiStartStop_e startStop); + +/** + \brief Register irq for cspi. + \param[in] instance cspi0 or cspi1. + \param[in] irqCb irq cb. + \return +*/ +void camRegisterIRQ(cspiInstance_e instance, camIrq_fn irqCb); + +/** + \brief Get cspi status. + \param[in] instance cspi0 or cspi1. + \return +*/ +uint32_t camGetCspiStats(cspiInstance_e instance); + +/** + \brief Clear cspi interrupt status. + \param[in] instance cspi0 or cspi1. + \param[in] mask which bit needs to clear. + \return +*/ +void camClearIntStats(cspiInstance_e instance, uint32_t mask); + +/** + \brief Set memory addr which is used to store picture of camera. + \param[in] dataAddr data addr. + \return +*/ +void camSetMemAddr(uint32_t dataAddr); + +/** + \brief Enable or disable interrupt of cspi. + \param[in] intEnable interrupt enable or not. + \return +*/ +void cspiIntEnable(cspiIntEnable_e intEnable); + + +/** \} */ + +#endif diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/gc032A/gc032A.h b/PLAT/driver/board/ec618_0h00/inc/camera/gc032A/gc032A.h new file mode 100644 index 0000000..9ad72aa --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/gc032A/gc032A.h @@ -0,0 +1,9 @@ +#ifndef GC032A_H +#define GC032A_H + +#define GC032A_I2C_ADDR 0x21 + +uint16_t gc032aGetRegCnt(char* regName); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/gc6123/gc6123.h b/PLAT/driver/board/ec618_0h00/inc/camera/gc6123/gc6123.h new file mode 100644 index 0000000..d62cc53 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/gc6123/gc6123.h @@ -0,0 +1,9 @@ +#ifndef GC6123_H +#define GC6123_H + +#define GC6123_I2C_ADDR 0x40 + +uint16_t gc6123GetRegCnt(char* regName); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/gc6153/gc6153.h b/PLAT/driver/board/ec618_0h00/inc/camera/gc6153/gc6153.h new file mode 100644 index 0000000..e94f595 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/gc6153/gc6153.h @@ -0,0 +1,9 @@ +#ifndef GC6153_H +#define GC6153_H + +#define GC6153_I2C_ADDR 0x40 + +uint16_t gc6153GetRegCnt(char* regName); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/i2cGpio.h b/PLAT/driver/board/ec618_0h00/inc/camera/i2cGpio.h new file mode 100644 index 0000000..64e5429 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/i2cGpio.h @@ -0,0 +1,36 @@ +#ifndef __I2C_GPIO_H__ +#define __I2C_GPIO_H__ + +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + +// sda pin definition. gpio16 +#define SDA_GPIO_INSTANCE (1) +#define SDA_GPIO_PIN (0) +#define SDA_GPIO_ADDR (31) +#define SDA_PAD_ALT_FUNC (PAD_MUX_ALT0) + +// scl pin definition. gpio17 +#define SCL_GPIO_INSTANCE (1) +#define SCL_GPIO_PIN (1) +#define SCL_GPIO_ADDR (32) +#define SCL_PAD_ALT_FUNC (PAD_MUX_ALT0) + +#define I2C_SDA_0 do {GPIO_pinWrite(SDA_GPIO_INSTANCE, 1 << SDA_GPIO_PIN, 0);}while(0) +#define I2C_SDA_1 do {GPIO_pinWrite(SDA_GPIO_INSTANCE, 1 << SDA_GPIO_PIN, 1 << SDA_GPIO_PIN);}while(0) + +#define I2C_SCL_0 do {GPIO_pinWrite(SCL_GPIO_INSTANCE, 1 << SCL_GPIO_PIN, 0);}while(0) +#define I2C_SCL_1 do {GPIO_pinWrite(SCL_GPIO_INSTANCE, 1 << SCL_GPIO_PIN, 1 << SCL_GPIO_PIN);}while(0) + + +void i2cGpioInit(); +uint8_t i2cReadByte(); +void i2cWritebyte(uint8_t byte); +void i2cStop(); +void i2cStart(); +void i2cAck(); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/sp0821/sp0821.h b/PLAT/driver/board/ec618_0h00/inc/camera/sp0821/sp0821.h new file mode 100644 index 0000000..b411d3e --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/sp0821/sp0821.h @@ -0,0 +1,9 @@ +#ifndef SP0821_H +#define SP0821_H + +#define SP0821_I2C_ADDR 0x43 + +uint16_t sp0821GetRegCnt(char* regName); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/camera/sp0A39/sp0A39.h b/PLAT/driver/board/ec618_0h00/inc/camera/sp0A39/sp0A39.h new file mode 100644 index 0000000..602c914 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/camera/sp0A39/sp0A39.h @@ -0,0 +1,9 @@ +#ifndef SP0A39_H +#define SP0A39_H + +#define SP0A39_I2C_ADDR 0x21 + +uint16_t sp0a39GetRegCnt(char* regName); + +#endif + diff --git a/PLAT/driver/board/ec618_0h00/inc/eeprom/eepRom.h b/PLAT/driver/board/ec618_0h00/inc/eeprom/eepRom.h new file mode 100644 index 0000000..a398128 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/eeprom/eepRom.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * + * Copy right: 2020-, Copyrigths of AirM2M Ltd. + * File name: eepRom.h + * Description: EC618 eepRom driver file + * History: Rev1.0 2020-12-17 + * + ****************************************************************************/ + +#ifndef _EEPROM_EC618_H +#define _EEPROM_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" +#include "oneWire.h" + +/** + \addtogroup eepRom_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + + +/******************************************************************************* + * API + ******************************************************************************/ + + #ifdef __cplusplus + extern "C" { +#endif + + +/** \brief ROM Operation Command */ +#define ROM_READ_CMD 0x33 +#define ROM_MATCH_CMD 0x55 +#define ROM_SKIP_CMD 0xCC +#define ROM_SEARCH_CMD 0xF0 + +/** \brief Memory Operation Command */ +#define MEM_READ_CMD 0xF0 +#define SCRATCHPAD_READ_CMD 0xAA +#define SCRATCHPAD_WRITE_CMD 0x0F +#define SCRATCHPAD_COPY_CMD 0x55 + +/** \brief EEPROM Status */ +#define EEPROMDRV_OK (0) +#define EEPROMDRV_RESET_ERR (-1) +#define EEPROMDRV_RESETPD_ERR (-2) +#define EEPROMDRV_ROMREAD_ERR (-3) +#define EEPROMDRV_ROMMATCH_ERR (-4) +#define EEPROMDRV_ROMSKIP_ERR (-5) +#define EEPROMDRV_ROMSEARCH_ERR (-6) +#define EEPROMDRV_MEMREAD_ERR (-7) +#define EEPROMDRV_SCRATCHPADREAD_ERR (-8) +#define EEPROMDRV_SCRATCHPADWRITE_ERR (-9) +#define EEPROMDRV_SCRATCHPADCOPY_ERR (-10) + +/** + \fn int32_t eePromReadRom(uint8_t* romCode) + \brief EEPROM read ROM code + \param[out] romCode ROM infomation read back. + \return read ROM status + */ +int32_t eePromReadRom(uint8_t* romCode); + +/** + \fn eePromReadMem(uint8_t targetAddr, uint8_t len, uint8_t* buffer) + \brief EEPROM read memory. + \param[in] targetAddr The target address of EEPROM. + \param[in] len Length of this read. + \param[out] buffer Data read back. + \return read memory status + */ +int32_t eePromReadMem(uint8_t targetAddr, uint8_t len, uint8_t* buffer); + +/** + \fn int32_t eePromWriteMem(uint8_t targetAddr, uint8_t len, uint8_t* buffer) + \brief EEPROM write memory + \param[in] targetAddr The target address of EEPROM. + \param[in] len Length of this write. + \param[in] buffer Data needs to write into memory. + \return Write memory status + */ +int32_t eePromWriteMem(uint8_t targetAddr, uint8_t len, uint8_t* buffer); + +void eepRomInit(OwModeSel_e mode); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/PLAT/driver/board/ec618_0h00/inc/lcd/ST7571/st7571.h b/PLAT/driver/board/ec618_0h00/inc/lcd/ST7571/st7571.h new file mode 100644 index 0000000..7814a6f --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/lcd/ST7571/st7571.h @@ -0,0 +1,70 @@ +#include "stdint.h" +#include "bsp.h" + +#define SPI_INSTANCE SPI0 +#define SPI_APB_CLOCK PCLK_SPI0 +#define SPI_FUNC_CLOCK FCLK_SPI0 +#define SPI_DMA_TX_REQID DMA_REQUEST_SPI0_TX // DMA SPI Request ID +#define LCD_DMA_DESCRIPTOR_CHAIN_NUM 20 // 30w pixel +#define LCD_TRANSFER_SIZE_ONCE 480//7680 // less than 8k + + + +#define HEIGHT (129) +#define WIDTH (128) + +#define SPI_BUS_SPEED (1000000) // 13M + +#define SPI_FLAG_TIMEOUT (0x1000) + + +// SPI cs pin definition +#define CS_GPIO_INSTANCE (0) +#define CS_GPIO_PIN (8) +#define CS_GPIO_ADDR (23) +#define CS_PAD_ALT_FUNC (PAD_MUX_ALT0) + +// SPI clk pin definition +#define CLK_GPIO_INSTANCE (0) +#define CLK_GPIO_PIN (11) +#define CLK_GPIO_ADDR (26) +#define CLK_PAD_ALT_FUNC (PAD_MUX_ALT1) + +// SPI mosi pin definition +#define MOSI_GPIO_INSTANCE (0) +#define MOSI_GPIO_PIN (9) +#define MOSI_GPIO_ADDR (24) +#define MOSI_PAD_ALT_FUNC (PAD_MUX_ALT1) + +// SPI miso pin definition +#define MISO_GPIO_INSTANCE (0) +#define MISO_GPIO_PIN (10) +#define MISO_GPIO_ADDR (25) +#define MISO_PAD_ALT_FUNC (PAD_MUX_ALT1) + + +// LCD rst pin definition +#define RST_GPIO_INSTANCE (1) +#define RST_GPIO_PIN (4) +#define RST_GPIO_ADDR (40) +#define RST_PAD_ALT_FUNC (PAD_MUX_ALT0) + +// LCD ds pin definition +#define DS_GPIO_INSTANCE (1) +#define DS_GPIO_PIN (12) +#define DS_GPIO_ADDR (48) +#define DS_PAD_ALT_FUNC (PAD_MUX_ALT0) + +// LCD en pin definition +#define EN_GPIO_INSTANCE (1) +#define EN_GPIO_PIN (5) +#define EN_GPIO_ADDR (41) +#define EN_PAD_ALT_FUNC (PAD_MUX_ALT0) + + +void st7571_init(void); +void displayPic_60x80(uint8_t *p); +void st7571CleanScreen(void); + + + diff --git a/PLAT/driver/board/ec618_0h00/inc/lcd/ST7789V2/st7789v2.h b/PLAT/driver/board/ec618_0h00/inc/lcd/ST7789V2/st7789v2.h new file mode 100644 index 0000000..005b94a --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/lcd/ST7789V2/st7789v2.h @@ -0,0 +1,68 @@ +#include "stdint.h" +#include "bsp.h" + +#define SPI_INSTANCE SPI0 +#define SPI_APB_CLOCK PCLK_SPI0 +#define SPI_FUNC_CLOCK FCLK_SPI0 +#define SPI_DMA_TX_REQID DMA_REQUEST_SPI0_TX // DMA SPI Request ID +#define LCD_DMA_DESCRIPTOR_CHAIN_NUM 20 // 30w pixel +#define LCD_TRANSFER_SIZE_ONCE 480//7680 // less than 8k + + + + + +#define SPI_BUS_SPEED (1000000) // 13M + +#define SPI_FLAG_TIMEOUT (0x1000) + +#define HEIGHT (320) +#define WIDTH (240) +#define RED (0xf800) +#define GREEN (0x07e0) +#define BLUE (0x001f) +#define YELLOW (0xffe0) +#define WHITE (0xffff) +#define BLACK (0x0000) +#define PURPLE (0xf81f) + + +// SPI cs pin definition +#define CS_GPIO_INSTANCE (0) +#define CS_GPIO_PIN (8) +#define CS_GPIO_ADDR (23) +#define CS_PAD_ALT_FUNC (PAD_MUX_ALT0) + +// SPI clk pin definition +#define CLK_GPIO_INSTANCE (0) +#define CLK_GPIO_PIN (11) +#define CLK_GPIO_ADDR (26) +#define CLK_PAD_ALT_FUNC (PAD_MUX_ALT1) + +// SPI mosi pin definition +#define MOSI_GPIO_INSTANCE (0) +#define MOSI_GPIO_PIN (9) +#define MOSI_GPIO_ADDR (24) +#define MOSI_PAD_ALT_FUNC (PAD_MUX_ALT1) + +// SPI miso pin definition +#define MISO_GPIO_INSTANCE (0) +#define MISO_GPIO_PIN (10) +#define MISO_GPIO_ADDR (25) +#define MISO_PAD_ALT_FUNC (PAD_MUX_ALT1) + + +// LCD rst pin definition +#define RST_GPIO_INSTANCE (1) +#define RST_GPIO_PIN (1) +#define RST_GPIO_ADDR (32) +#define RST_PAD_ALT_FUNC (PAD_MUX_ALT0) + +// LCD ds pin definition +#define DS_GPIO_INSTANCE (1) +#define DS_GPIO_PIN (0) +#define DS_GPIO_ADDR (31) +#define DS_PAD_ALT_FUNC (PAD_MUX_ALT0) + +void st7789v2_init(void); + diff --git a/PLAT/driver/board/ec618_0h00/inc/lcd/imageProcess.h b/PLAT/driver/board/ec618_0h00/inc/lcd/imageProcess.h new file mode 100644 index 0000000..2551d82 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/lcd/imageProcess.h @@ -0,0 +1,85 @@ +#ifndef IMAGE_PROCESS_H +#define IMAGE_PROCESS_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" +#include + + +/** + \brief Convert yuv422 to rgb565, used in color screen. + \param[in] inbuf source memory. + \param[out] outbuf output memory. + \param[in] width source picture width. + \param[in] height source picture height. + \return +*/ +void yuv422ToRgb565(const void* inbuf, void* outbuf, int width, int height); + +/** + \brief Scale the picture. Now this api can only zoom out the picture. + \param[in] ratio Zoom out ratio. + \param[in] inPtr Data source. + \param[in] width Source data width. + \param[in] height Source data height. + \param[out] outPtr Output data address. + \return +*/ +void scalePic(uint8_t ratio, uint8_t* inPtr, uint16_t width, uint16_t height, uint8_t *outPtr); + +/** + \brief Clockwise rotate 90 degree. + \param[in,out] mem Data source. + \param[in] width Source picture width. + \param[in] height Source picture height. + \return +*/ +void imageRotate(uint8_t* mem, uint32_t width, uint32_t height); + +/** + \brief Organize the bytes as horizontal or vertical. + \param[in] inPut Src data. + \param[in] pageLen The pageNum you want for these data, this param is set by you. + \param[in] width The width you want for these data, this param is set by you. + \param[out] outPut Output buffer. + \param[in] horizotal These data you want to array them as horizontal or vertical. + \return +*/ +void storeByteIntoArray(uint8_t *inPut, uint8_t pageLen, uint16_t width, uint8_t *outPut, bool horizotal); + +/** + \brief Merge 8bytes into one byte, used in 1-bit LCD. + \param[in] p Src data. + \param[out] outPut Output buffer. + \param[in] width Source data width. + \param[out] height Source data height. + \param[in] horizotal Fetch the data by row or by column. + \param[in] inByteRevert Within the byte, positive or reverse the bit sequence. + \return index How many bytes has been returned, for debug use +*/ +uint16_t merge8Bytes2OneByte(uint8_t* p, uint8_t *outPut, uint16_t width, uint16_t height, bool horizotal, bool inByteRevert); + +/** + \brief Binary the source picture. + \param[in] inPut Src data. + \param[in] width Source picture width. + \param[in] height Source picture height. + \param[out] outPut Output buffer. + \return +*/ +void calBinary(uint8_t* inPut, uint16_t width, uint16_t height, uint8_t* outPut); + + + + +#ifdef __cplusplus +} +#endif +#endif /* IMAGE_PROCESS_H */ + + diff --git a/PLAT/driver/board/ec618_0h00/inc/lcd/lcdDrv.h b/PLAT/driver/board/ec618_0h00/inc/lcd/lcdDrv.h new file mode 100644 index 0000000..79bc4ce --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/lcd/lcdDrv.h @@ -0,0 +1,114 @@ +#ifndef BSP_LCD_H +#define BSP_LCD_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + +// Only need to choose which LCD you use +#define ST7789V2_ENABLE 0 +#define ST7571_ENABLE 1 + + + + +#if (ST7789V2_ENABLE) +#include "st7789v2.h" +#endif + +#if (ST7571_ENABLE) +#include "st7571.h" +#endif + + + +#define SPI SPI_INSTANCE +#define SPI_CS_LOW do {GPIO_pinWrite(SPI_CS_GPIO_INSTANCE, 1 << SPI_CS_GPIO_PIN, 0);}while(0) +#define SPI_CS_HIGH do {GPIO_pinWrite(SPI_CS_GPIO_INSTANCE, 1 << SPI_CS_GPIO_PIN, 1 << SPI_CS_GPIO_PIN);}while(0) +#define LCD_DS_LOW do {GPIO_pinWrite(LCD_DS_GPIO_INSTANCE, 1 << LCD_DS_GPIO_PIN, 0);}while(0) +#define LCD_DS_HIGH do {GPIO_pinWrite(LCD_DS_GPIO_INSTANCE, 1 << LCD_DS_GPIO_PIN, 1 << LCD_DS_GPIO_PIN);}while(0) +#define LCD_RST_LOW do {GPIO_pinWrite(LCD_RST_GPIO_INSTANCE, 1 << LCD_RST_GPIO_PIN, 0);}while(0) +#define LCD_RST_HIGH do {GPIO_pinWrite(LCD_RST_GPIO_INSTANCE, 1 << LCD_RST_GPIO_PIN, 1 << LCD_RST_GPIO_PIN);}while(0) + +#define SPI_SEND_DATA(data) do {SPI->DR = data;}while(0) +#define SPI_READ_DATA (SPI->DR) +#define SPI_WAIT_TX_DONE do {}while(!((SPI->SR & (SPI_SR_BSY_Msk | SPI_SR_TFE_Msk)) == SPI_SR_TFE_Msk)) +#define SPI_IS_BUSY do {}while((SPI->SR & SPI_SR_BSY_Msk) == SPI_SR_BSY_Msk) + +#define SPI_START_DMA_CHANNEL(channel) do {*((uint32_t*)(0x4d1f0000 + (channel << 2))) |= 0x80000000;}while(0) +#define SPI_STOP_DMA_CHANNEL(channel) do {*((uint32_t*)(0x4d1f0000 + (channel << 2))) &= ~0x80000000;}while(0) +#define SPI_ENABLE_TX_DMA do {SPI->DMACR |= SPI_DMACR_TXDMAE_Msk;}while(0) + +// Spi cs pin +#define SPI_CS_GPIO_INSTANCE (CS_GPIO_INSTANCE) +#define SPI_CS_GPIO_PIN (CS_GPIO_PIN) +#define SPI_CS_PAD_ADDR (CS_GPIO_ADDR) +#define SPI_CS_PAD_ALT_FUNC (CS_PAD_ALT_FUNC) + +// Spi clk pin +#define SPI_CLK_GPIO_INSTANCE (CLK_GPIO_INSTANCE) +#define SPI_CLK_GPIO_PIN (CLK_GPIO_PIN) +#define SPI_CLK_PAD_ADDR (CLK_GPIO_ADDR) +#define SPI_CLK_PAD_ALT_FUNC (CLK_PAD_ALT_FUNC) + +// Spi mosi pin +#define SPI_MOSI_GPIO_INSTANCE (MOSI_GPIO_INSTANCE) +#define SPI_MOSI_GPIO_PIN (MOSI_GPIO_PIN) +#define SPI_MOSI_PAD_ADDR (MOSI_GPIO_ADDR) +#define SPI_MOSI_PAD_ALT_FUNC (MOSI_PAD_ALT_FUNC) + +// Spi miso pin +#define SPI_MISO_GPIO_INSTANCE (MISO_GPIO_INSTANCE) +#define SPI_MISO_GPIO_PIN (MISO_GPIO_PIN) +#define SPI_MISO_PAD_ADDR (MISO_GPIO_ADDR) +#define SPI_MISO_PAD_ALT_FUNC (MISO_PAD_ALT_FUNC) + + +// Lcd rst pin +#define LCD_RST_GPIO_INSTANCE (RST_GPIO_INSTANCE) +#define LCD_RST_GPIO_PIN (RST_GPIO_PIN) +#define LCD_RST_PAD_ADDR (RST_GPIO_ADDR) +#define LCD_RST_PAD_ALT_FUNC (RST_PAD_ALT_FUNC) + +// Lcd ds pin +#define LCD_DS_GPIO_INSTANCE (DS_GPIO_INSTANCE) +#define LCD_DS_GPIO_PIN (DS_GPIO_PIN) +#define LCD_DS_PAD_ADDR (DS_GPIO_ADDR) +#define LCD_DS_PAD_ALT_FUNC (DS_PAD_ALT_FUNC) + +#if (ST7571_ENABLE) +// Lcd en pin +#define LCD_EN_GPIO_INSTANCE (EN_GPIO_INSTANCE) +#define LCD_EN_GPIO_PIN (EN_GPIO_PIN) +#define LCD_EN_PAD_ADDR (EN_GPIO_ADDR) +#define LCD_EN_PAD_ALT_FUNC (EN_PAD_ALT_FUNC) +#endif + +typedef void (*pTxCb)(uint32_t event); + +uint8_t lcdReadData(void); +void lcdReadId(void); +void lcdWriteCmd(uint8_t cmd); +void lcdWriteData(uint8_t data); +void lcdInit(pTxCb txCb); +void mDelay(uint32_t mDelay); +//void lcdWriteData16(uint16_t data); +//void lcdDispColor(uint16_t color); +void lcdDispWindows(void); +//void lcdWriteDataDma(uint16_t color); +void lcdWriteSetup(uint8_t * dataBuf, uint16_t dataCnt); +void lcdWriteCtrl(bool startOrStop); +void lcdClearScreen(); +void lcdDispPic(uint8_t * pic); + + + +#ifdef __cplusplus +} +#endif +#endif /* BSP_LCD_H */ + diff --git a/PLAT/driver/board/ec618_0h00/inc/ntc/ntc.h b/PLAT/driver/board/ec618_0h00/inc/ntc/ntc.h new file mode 100644 index 0000000..0bf8485 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/ntc/ntc.h @@ -0,0 +1,40 @@ +#ifndef _NTC_H +#define _NTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Get NTC temperature + + Vref(AIO1 output 1200000 uV) + v + | + | + +-+ + | | + | | R = 10 Kohm + | | + +-+ + |--------->(AIO2) + +-+ + | | + | | Rntc + | | + +-+ + | + ----- + --- (GND) + - + + \param[in] adcInputVoltage ADC input voltage in unit of uV + \return temperature in unit of mili degree centigrade + */ +int32_t ntcGetTemperature(int32_t adcInputVoltage); + +#ifdef __cplusplus +} +#endif + +#endif /* _NTC_H */ diff --git a/PLAT/driver/board/ec618_0h00/inc/plat_config.h b/PLAT/driver/board/ec618_0h00/inc/plat_config.h new file mode 100644 index 0000000..222da29 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/inc/plat_config.h @@ -0,0 +1,506 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: plat_config.h + * Description: platform configuration header file + * History: Rev1.0 2019-01-18 + * Rev1.1 2019-11-27 Reimplement file operations with OSA APIs(LFS wrapper), not directly using LFS APIs in case of file system replacement + * Rev1.2 2020-01-01 Separate plat config into two parts, FS and raw flash + * + ****************************************************************************/ + +#ifndef _PLAT_CONFIG_H +#define _PLAT_CONFIG_H + +#include "Driver_Common.h" +#include "cmsis_compiler.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FS_PLAT_CONFIG_FILE_CURRENT_VERSION (0) + +#define RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION (1) + + + /** \brief config file header typedef */ +__PACKED_STRUCT _config_file_header +{ + uint16_t fileBodySize; /**< size of file body, in unit of byte */ + uint8_t version; /**< file version, this field shall be updated when file structure is changed */ + uint8_t checkSum; /**< check sum value of file body */ +}; +typedef struct _config_file_header config_file_header_t; + +/** \brief typedef of platform configuration stored in fs */ +typedef __PACKED_UNION _EPAT_atPortFrameFormat +{ + uint32_t wholeValue; + __PACKED_STRUCT _config + { + uint32_t dataBits : 3; + uint32_t parity : 2; + uint32_t stopBits : 2; + uint32_t flowControl : 3; + } config; +} atPortFrameFormat_t; + + + +// ulg port enum +typedef enum +{ + PLAT_CFG_ULG_PORT_USB=0, + PLAT_CFG_ULG_PORT_UART, + PLAT_CFG_ULG_PORT_MIX, + PLAT_CFG_ULG_PORT_MAX +} PlatCfgUlgPort_e; + + + +/** \brief typedef of platform configuration stored in fs */ +typedef __PACKED_STRUCT _NVM_EPAT_plat_config +{ + /** PM on/off flag + * valid value: + * 0x504D5544 -- PM is disabled, "PMUD" + * 0x504D5545 -- PM is enabled, "PMUE" + */ + uint32_t enablePM; + + /** sleep mode + * valid value: + * 0 -- dummy + * 1 -- dummy + */ + uint8_t sleepMode; + + /** wait n ms before sleep, when wakeup from pad + * valid value: + * 0 -- do not wait + * x -- wait x ms + */ + uint32_t slpWaitTime; + + /** AT baudrate,for AP only + * should be equal to 'atPortBaudRate' in struct plat_config_raw_flash_t + */ + uint32_t atPortBaudRate; + + /** AT port frame format*/ + atPortFrameFormat_t atPortFrameFormat; + + /** ECQSCLK config + * valid value: + * 0 -- ECQSCLK set to 0 + * 1 -- ECQSCLK set to 1 + */ + uint8_t ecSclkCfg; +} plat_config_fs_t; + + +/** \brief typedef of platform configuration stored in raw flash --old v0*/ +__PACKED_STRUCT _plat_config_raw_flash_v0 +{ + /** action to perform when assert or hard fault occurs + * valid value: + * 0 -- dump full exception info to flash and EPAT tool then trapped in endless loop(while(1)) + * 1 -- print necessary exception info then reset + * 2 -- dump full exception info to flash then reset + * 3 -- dump full exception info to flash and EPAT tool then reset + * 4 -- reset directly + * 10 -- enable uart help dump and dump full exception info to flash and EPAT tool then trapped in endless loop(while(1)) + * 13 -- enable uart help dump and dump full exception info to flash and EPAT tool, and then reset + */ + uint8_t faultAction; + + /** port select for dump info output when exception occurs + * valid value: + * 0,1,2,3,(4) -- specify which port + * 0xff -- disable this function + */ + uint8_t uartDumpPort; + + /** WDT start/stop control + * valid value: + * 0 -- stop WDT + * 1 -- start WDT + */ + uint8_t startWDT; + + /** unilog on/off flag + * valid value: + * 0 -- unilog is disabled + * 1 -- only sw log is enabled + * 2 -- All log is enabled + */ + uint8_t logControl; + + /** uart baudrate for unilog output */ + uint32_t uartBaudRate; + + /** debug trace log level setting, refer to 'DebugTraceLevelType_e' */ + uint32_t logLevel; + + /** unilog output port select + * valid value: + * 0 -- USB + * 1 -- UART + * 2 -- MIX(for future use UART/USB dynamic select) + **/ + PlatCfgUlgPort_e logPortSel; + + /** RNDIS enum control + * valid value: + * 0 -- enable USB init and enum RNDIS + * 1 -- enable USB init but not enum RNDIS + * 2 -- disable USB init + */ + uint8_t usbCtrl; + + /** usb software trace control + * valid value: + * 0 -- disable all usb software trace + * 1 -- enable all usb software trace + * others -- misc usb software trace + */ + uint8_t usbSwTrace; + + + + /** USB sleep mask + * valid value: + * 0 -- usb should vote to enter sleep + * 1 -- do not consider usb vote before sleep + */ + uint8_t usbSlpMask; + + /** USB sleep thd + * valid value: + * set the minimal time to sleep, when usbSlpMask=1 + */ + uint16_t usbSlpThd; + + /** pwrkey mode + * valid value: + * 1 power key mode + * 0 normal key mode + */ + uint8_t pwrKeyMode; +}; + +// fota urc port type +typedef enum +{ + PLAT_CFG_FOTA_URC_PORT_USB=0, + PLAT_CFG_FOTA_URC_PORT_UART, + PLAT_CFG_FOTA_URC_PORT_MAXTYPE +} PlatCfgFotaUrcPortType_e; + +#define PLAT_CFG_FOTA_URC_USB_PORT_IDX_MIN 0 +#define PLAT_CFG_FOTA_URC_USB_PORT_IDX_MAX 2 + +#define PLAT_CFG_FOTA_URC_UART_PORT_IDX_MIN 0 +#define PLAT_CFG_FOTA_URC_UART_PORT_IDX_MAX 1 + + +#define PLAT_CFG_RAW_FLASH_RSVD_SIZE 21 + +/** \brief typedef of platform configuration stored in raw flash */ +__PACKED_STRUCT _plat_config_raw_flash +{ + /** action to perform when assert or hard fault occurs + * valid value: + * 0 -- dump full exception info to flash and EPAT tool then trapped in endless loop(while(1)) + * 1 -- print necessary exception info then reset + * 2 -- dump full exception info to flash then reset + * 3 -- dump full exception info to flash and EPAT tool then reset + * 4 -- reset directly + * 10 -- enable uart help dump and dump full exception info to flash and EPAT tool then trapped in endless loop(while(1)) + * 13 -- enable uart help dump and dump full exception info to flash and EPAT tool, and then reset + */ + uint8_t faultAction; + + /** port select for dump info output when exception occurs + * valid value: + * 0,1,2,3,(4) -- specify which port + * 0xff -- disable this function + */ + uint8_t uartDumpPort; + + + /** WDT start/stop control + * valid value: + * 0 -- stop WDT + * 1 -- start WDT + */ + uint8_t startWDT; + + /** unilog on/off flag + * valid value: + * 0 -- unilog is disabled + * 1 -- only sw log is enabled + * 2 -- All log is enabled + */ + uint8_t logControl; + + /** uart baudrate for unilog output */ + uint32_t uartBaudRate; + + /** debug trace log level setting, refer to 'DebugTraceLevelType_e' */ + uint32_t logLevel; + + /** unilog output port select + * valid value: + * 0 -- USB + * 1 -- UART + * 2 -- MIX(for future use UART/USB dynamic select) + **/ + PlatCfgUlgPort_e logPortSel; + + /** RNDIS enum control + * valid value: + * 0 -- enable USB init and enum RNDIS + * 1 -- enable USB init but not enum RNDIS + * 2 -- disable USB init + */ + uint8_t usbCtrl; + + /** usb software trace control + * valid value: + * 0 -- disable all usb software trace + * 1 -- enable all usb software trace + * others -- misc usb software trace + */ + uint8_t usbSwTrace; + + + + /** USB sleep mask + * valid value: + * 0 -- usb should vote to enter sleep + * 1 -- do not consider usb vote before sleep + */ + uint8_t usbSlpMask; + + /** USB sleep thd + * valid value: + * set the minimal time to sleep, when usbSlpMask=1 + */ + uint16_t usbSlpThd; + + /** pwrkey mode + * valid value: + * 1 power key mode + * 0 normal key mode + */ + uint8_t pwrKeyMode; + + /** USB VBUS MODE Enable,Disable Flag + * valid value: + * 0 -- usb vbus mode disable + * 1 -- usb vbus mode enable + */ + uint8_t usbVBUSModeEn; + + /** USB VBUS MODE Wakup Pad Index + * valid value: + * 0,1,2,3,4,5 PAD IDX FOR USB VBUS WKUP PAD + */ + uint8_t usbVBUSWkupPad; + + /** USB NET IF SEL + * valid value: + * 0----RNDIS,default + * 1----ECM + */ + uint8_t usbNet; + + /** USB VCOM EN bitmap + * valid value: + * bit0---vcom0 + * bit1---vcom1 + * ---- + * ---- + */ + uint8_t usbVcomEnBitMap; + + /** AT/fotaURC baudrate, for AP & BL*/ + uint32_t atPortBaudRate; + + /** FOTA URC output port select + * valid value(Bit4-7): + * 0 -- USB + * 1 -- UART + ** + * valid value(Bit0-3): + * 0-2 -- USB + * 0-1 -- UART + **/ + uint8_t fotaUrcPortSel; + + /** pmuInCdrx + * valid value: + * 0---- + * 1---- + */ + uint8_t pmuInCdrx; + + /** slpLimitEn + * valid value: + * 0---- disable + * 1---- enable + */ + uint8_t slpLimitEn; + + /** slpLimitTime + * valid value: + * 0---0xFFFFFFFF + */ + uint32_t slpLimitTime; + + /* 'PLAT_CFG_RAW_FLASH_RSVD_SIZE' bytes rsvd for future */ + uint8_t resv[PLAT_CFG_RAW_FLASH_RSVD_SIZE]; +}; + +typedef struct _plat_config_raw_flash plat_config_raw_flash_t;//current +typedef struct _plat_config_raw_flash_v0 plat_config_raw_flash_v0_t;//old v0 + +/** \brief typedef of platform info layout stored in raw flash */ +__PACKED_STRUCT _plat_info_layout +{ + config_file_header_t header; /**< raw flash plat config header */ + plat_config_raw_flash_t config; /**< raw flash plat config body */ + uint32_t fsAssertCount; /**< count for monitoring FS assert, when it reaches specific number, FS region will be re-formated */ +}; +typedef struct _plat_info_layout plat_info_layout_t; + +/** @brief List of platform configuration items used to set/get sepecific setting */ +typedef enum _plat_config_id +{ + PLAT_CONFIG_ITEM_FAULT_ACTION = 0, /**< faultAction item */ + PLAT_CONFIG_ITEM_UART_DUMP_PORT, /**< uartDumpPort item */ + PLAT_CONFIG_ITEM_START_WDT, /**< startWDT item */ + PLAT_CONFIG_ITEM_LOG_CONTROL, /**< logControl item */ + PLAT_CONFIG_ITEM_LOG_BAUDRATE, /**< uart baudrate for log output */ + PLAT_CONFIG_ITEM_LOG_LEVEL, /**< logLevel item */ + PLAT_CONFIG_ITEM_ENABLE_PM, /**< enablePM item */ + PLAT_CONFIG_ITEM_SLEEP_MODE, /**< sleepMode item */ + PLAT_CONFIG_ITEM_WAIT_SLEEP, /**< wait ms before sleep */ + PLAT_CONFIG_ITEM_AT_PORT_BAUDRATE, /**< AT port baudrate */ + PLAT_CONFIG_ITEM_AT_PORT_FRAME_FORMAT, /**< AT port frame format */ + PLAT_CONFIG_ITEM_ECSCLK_CFG, /**< ECSCLK config */ + PLAT_CONFIG_ITEM_LOG_PORT_SEL, /**< ULG output port select */ + PLAT_CONFIG_ITEM_USB_CTRL, /**< USB control */ + PLAT_CONFIG_ITEM_USB_SW_TRACE_FLAG, /**< USB control */ + PLAT_CONFIG_ITEM_USB_SLEEP_MASK, /**< USB Sleep Vote Mask */ + PLAT_CONFIG_ITEM_USB_SLEEP_THD, /**< USB Sleep Thread */ + PLAT_CONFIG_ITEM_PWRKEY_MODE, /**< PWRKEY Mode */ + PLAT_CONFIG_ITEM_USB_VBUS_MODE_EN, /**< USB VBUS MODE ENABLE, DISABLE*/ + PLAT_CONFIG_ITEM_USB_VBUS_WKUP_PAD, /**< USB VBUS MODE WKUP PAD INDEX*/ + PLAT_CONFIG_ITEM_USB_NET, /**< USB NET Select*/ + PLAT_CONFIG_ITEM_USB_VCOM_EN_BMP, /**< USB VCOM Enabled Bitmap*/ + PLAT_CONFIG_ITEM_FOTA_URC_PORT_SEL, /**< FOTA URC Port Select*/ + PLAT_CONFIG_ITEM_PMUINCDRX, /**< PMUINCDRX Select*/ + PLAT_CONFIG_ITEM_SLP_LIMIT_EN, /**< enable sleep time limit*/ + PLAT_CONFIG_ITEM_SLP_LIMIT_TIME, /**< set maximum sleep time in mili second*/ + PLAT_CONFIG_ITEM_TOTAL_NUMBER /**< total number of items */ +} plat_config_id_t; + + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \fn void BSP_SavePlatConfigToFs(void) + \brief Save platform configuration into FS + \return void + */ +void BSP_SavePlatConfigToFs(void); + +/** + \fn void BSP_LoadPlatConfigFromFs(void) + \brief Load platform configuration from FS + \return void + */ +void BSP_LoadPlatConfigFromFs(void); + +/** + \fn plat_config_fs_t* BSP_GetFsPlatConfig(void) + \brief Get FS platform configuration variable pointer + \return pointer to internal platform configuration loaded from FS + */ +plat_config_fs_t* BSP_GetFsPlatConfig(void); + +/** + \fn void BSP_SavePlatConfigToRawFlash(void) + \brief Save platform configuration into raw flash + \return void + */ +void BSP_SavePlatConfigToRawFlash(void); + +/** + \fn void BSP_LoadPlatConfigFromRawFlash(void) + \brief Load platform configuration from raw flash + \return void + */ +void BSP_LoadPlatConfigFromRawFlash(void); + +/** + \fn plat_config_raw_flash_t* BSP_GetRawFlashPlatConfig(void) + \brief Get raw flash platform configuration variable pointer + \return pointer to internal platform configuration loaded from raw flash + */ +plat_config_raw_flash_t* BSP_GetRawFlashPlatConfig(void); + +/** + \fn uint32_t BSP_GetPlatConfigItemValue(plat_config_id_t id) + \brief Get value of specific platform configuration item + \param[in] id id of platform configuration item, \ref plat_config_id_t + \return value of current configuration item + */ +uint32_t BSP_GetPlatConfigItemValue(plat_config_id_t id); + +/** + \fn void BSP_SetPlatConfigItemValue(plat_config_id_t id, uint32_t value) + \brief Set value of specific platform configuration item + \param[in] id id of platform configuration item, \ref plat_config_id_t + \param[in] value value of configuration item to set + \return void + */ +void BSP_SetPlatConfigItemValue(plat_config_id_t id, uint32_t value); + +/** + \fn uint32_t BSP_GetFSAssertCount(void) + \brief Fetch current 'fsAssertCount' value from PLAT_INFO region + \return current fsAssertCount value + */ +uint32_t BSP_GetFSAssertCount(void); + +/** + \fn void BSP_SetFSAssertCount(uint32_t value); + \brief Update 'fsAssertCount' value + \param[in] value new value assigned to 'fsAssertCount' + \return void + \note Internal use only on FS assert occurs + */ +void BSP_SetFSAssertCount(uint32_t value); + +/** + \fn void BSP_SetFsPorDefaultValue(void); + \brief when por happened some data may retore to it's default + \return void + */ +void BSP_SetFsPorDefaultValue(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _PLAT_CONFIG_H */ diff --git a/PLAT/driver/board/ec618_0h00/src/audio/codec/codecDrv.c b/PLAT/driver/board/ec618_0h00/src/audio/codec/codecDrv.c new file mode 100644 index 0000000..c72dca6 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/audio/codec/codecDrv.c @@ -0,0 +1,172 @@ +#include "codecDrv.h" + +void delay_us(uint32_t us); + +extern ARM_DRIVER_I2C Driver_I2C0; +static ARM_DRIVER_I2C *i2cDrvInstance = &CREATE_SYMBOL(Driver_I2C, 0); + +void codecI2cInit() +{ + i2cDrvInstance->Initialize(NULL); + i2cDrvInstance->PowerControl(ARM_POWER_FULL); + i2cDrvInstance->Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_STANDARD); + i2cDrvInstance->Control(ARM_I2C_BUS_CLEAR, 0); +} + +void codecI2cWrite(char* codecName, uint8_t slaveAddr, i2sI2cCfg_t* i2cCfg) +{ + uint8_t cmd[2] = {0, 0}; + uint8_t regAddr = i2cCfg->regAddr; + uint16_t regData = i2cCfg->regVal; + + if (strcmp(codecName, "es8388") == 0) + { + cmd[0] = regAddr; + cmd[1] = regData & 0xff; + + } + else if (strcmp(codecName, "NAU88C22") == 0) + { + cmd[0] = (regAddr << 1) | ((regData & 0x100) >> 8); + cmd[1] = regData & 0xff; + } + else if(strcmp(codecName, "es8311") == 0) + { + cmd[0] = regAddr; + cmd[1] = regData & 0xff; + } + + i2cDrvInstance->MasterTransmit(slaveAddr, cmd, 2, false); + //delay_us(30 * 1000); // need to add delay in app layer which call it +} + +uint8_t codecI2cRead(uint8_t slaveAddr, uint8_t regAddr) +{ + uint8_t a; + a = regAddr; + uint8_t readData; + i2cDrvInstance->MasterTransmit(slaveAddr, (uint8_t *)&a, 1, true); + i2cDrvInstance->MasterReceive(slaveAddr, &readData, 1, false); + return readData; +} + +uint16_t es8388GetFs(void); +uint16_t es8311GetFs(void); + +uint16_t codecGetFs(codecType_e codecType) +{ + switch (codecType) + { + case ES8388: + return es8388GetFs(); + + case NAU88C22: + return 1; + + case ES7148: + return 1; + + case ES7149: + return 1; + + case ES8311: + return es8311GetFs(); + + } + + return 0; +} + +#if 0 +/** + \fn void codecCtrlVolume(uint8_t raise, uint8_t step) + \brief Raise or decrease volume. + \param[in] codecType codec type. + \param[in] raise true means raise volume; false means decrease volume. + \param[in] step Raise or decrease vlume'samplitude everytime. + \return none. +*/ +void codecCtrlVolume(codecType_e codecType, bool raise, uint8_t step) +{ + i2sI2cCfg_t i2cCfg = {0,0,0}; + + switch (codecType) + { + case ES8388: + { + i2cCfg.regAddr = 0x1b; + raise? (i2cCfg.regVal += step) : (i2cCfg.regVal -= step); + i2cCfg.delayMs = 1; + + codecI2cWrite("es8388", ES8388_IICADDR, (i2sI2cCfg_t*)&i2cCfg); // register27. Digital part + codecI2cWrite("es8388", ES8388_IICADDR, (i2sI2cCfg_t*)&i2cCfg); // register49. Analog part + return; + } + + case NAU88C22: + return; + + } +} +#endif + +void codecWriteVal(codecType_e codecType, uint8_t regAddr, uint16_t regVal) +{ + i2sI2cCfg_t i2cCfg; + + i2cCfg.regAddr = regAddr; + i2cCfg.regVal = regVal; + + switch (codecType) + { + case ES8388: + { + codecI2cWrite("es8388", ES8388_IICADDR, (i2sI2cCfg_t*)&i2cCfg); + return; + } + + case NAU88C22: + { + codecI2cWrite("NAU88C22", NAU88C22_IICADDR, (i2sI2cCfg_t*)&i2cCfg); + return; + } + case ES7148: + { + return; + } + case ES7149: + { + return; + } + case ES8311: + { + codecI2cWrite("es8311", ES8311_IICADDR, (i2sI2cCfg_t*)&i2cCfg); + return; + } + } +} + +uint8_t codecReadVal(codecType_e codecType, uint8_t regAddr) +{ + uint8_t dataRead = 0x55; + switch (codecType) + { + case ES8388: + { + dataRead = codecI2cRead(ES8388_IICADDR, regAddr); + break; + } + case ES8311: + { + dataRead = codecI2cRead(ES8311_IICADDR, regAddr); + break; + } + case ES7148: + case ES7149: + case NAU88C22: + break; + } + + return dataRead; +} + diff --git a/PLAT/driver/board/ec618_0h00/src/audio/codec/es8311/es8311.c b/PLAT/driver/board/ec618_0h00/src/audio/codec/es8311/es8311.c new file mode 100644 index 0000000..12d9901 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/audio/codec/es8311/es8311.c @@ -0,0 +1,155 @@ +#include "i2s.h" + +#define ES8311_FS_NUM 256 + + +i2sI2cCfg_t es8311_regInfo[] = +{ + + {0x45,0x00}, + {0x01,0x30}, + {0x02,0x10}, + + + //Ratio=MCLK/LRCK=256:12M288-48Kï¼›4M096-16K; 2M048-8K + {0x02,0x00},//MCLK DIV=1 + {0x03,0x10}, + {0x16,0x24}, + {0x04,0x20}, + {0x05,0x00}, + {0x06,(0<<5) + 4 -1},//(0x06,(SCLK_INV<<5) + SCLK_DIV -1); + {0x07,0x00}, + {0x08,0xFF}, + + + {0x09,(0<<7) + 0x00 + (0x00<<2)},//(0x09,(DACChannelSel<<7) + Format + (Format_Len<<2)); + {0x0A,0x00 + (0x00<<2)},//(0x0A,Format + (Format_Len<<2)); + + + + {0x0B,0x00}, + {0x0C,0x00}, + +// {0x10,(0x1C*0) + (0x60*0x01) + 0x03}, //(0x10,(0x1C*DACHPModeOn) + (0x60*VDDA_VOLTAGE) + 0x03); //VDDA_VOLTAGE=1.8V close es8311MasterInit 3.3PWR setting + {0x10,(0x1C*0) + (0x60*0x00) + 0x03}, //(0x10,(0x1C*DACHPModeOn) + (0x60*VDDA_VOLTAGE) + 0x03); //VDDA_VOLTAGE=3.3V open es8311MasterInit 3.3PWR setting + + {0x11,0x7F}, + + {0x00,0x80 + (0<<6)},//Slave Mode (0x00,0x80 + (MSMode_MasterSelOn<<6));//Slave Mode + + {0x0D,0x01}, + + {0x01,0x3F + (0x00<<7)},//(0x01,0x3F + (MCLK<<7)); + + {0x14,(0<<6) + (1<<4) + 0},//选择CH1输入+30DB GAIN (0x14,(Dmic_Selon<<6) + (ADCChannelSel<<4) + ADC_PGA_GAIN); + + {0x12,0x28}, + {0x13,0x00 + (0<<4)}, //(0x13,0x00 + (DACHPModeOn<<4)); + + {0x0E,0x02}, + {0x0F,0x44}, + {0x15,0x00}, + {0x1B,0x0A}, + {0x1C,0x6A}, + {0x37,0x48}, + {0x44,(0 <<7)}, //(0x44,(ADC2DAC_Sel <<7)); + {0x17,210},//(0x17,ADC_Volume); + {0x32,100},//(0x32,DAC_Volume); + + +}; + +uint16_t es8311GetRegCnt(char* regName) +{ + if (strcmp(regName, "es8311_master") == 0) + { + return (sizeof(es8311_regInfo) / sizeof(es8311_regInfo[0])); + } + else if (strcmp(regName, "es8311_slave") == 0) + { + return (sizeof(es8311_regInfo) / sizeof(es8311_regInfo[0])); + } + + return 0; +} + +void codecI2cInit(void); +void codecI2cWrite(char* codecName, uint8_t slaveAddr, i2sI2cCfg_t* i2sI2cCfg); +uint8_t codecI2cRead(uint8_t slaveAddr, uint8_t regAddr); + + + +void es8311MasterInit() +{ + uint8_t dataRead = 0xff; + //Codec PWR==3.3V,Set gpio to 3.3v first. + HAL_normalIOVoltSet(VOL_3_30V); + codecI2cInit(); + + for (int i = 0; i < es8311GetRegCnt("es8311_master"); i++) + { + codecI2cWrite("es8311", ES8311_IICADDR, (i2sI2cCfg_t*)&es8311_regInfo[i]); + delay_us(10000); + } + + +#if 1 + for (int i = 0; i < es8311GetRegCnt("es8311_master"); i++) + { + dataRead = codecI2cRead(ES8311_IICADDR, es8311_regInfo[i].regAddr); + printf("reg = 0x%02x, val = 0x%02x\n", es8311_regInfo[i].regAddr, dataRead); + } +#endif +} + +void es8311SlaveInit() +{ +// uint8_t dataRead = 0xff; + es8311MasterInit(); + + i2sI2cCfg_t i2sI2cCfg; + i2sI2cCfg.regAddr = 0x80; + i2sI2cCfg.regVal = 0<<6; // Bit7 --> 1: master(default); 0: slave + codecI2cWrite("es8311", ES8311_IICADDR, (i2sI2cCfg_t*)&i2sI2cCfg); + +#if 0 + for (int i = 0; i < es8311GetRegCnt("es8311_slave"); i++) + { + dataRead = codecI2cRead(ES8311_IICADDR, es8311_regInfo[i].regAddr); + printf("reg = 0x%02x, val = 0x%02x\n", es8311_regInfo[i].regAddr, dataRead); + } +#endif +} + + +uint16_t es8311GetFs() +{ + + return ES8311_FS_NUM; +} + +void es8311SetMode(i2sMode_e mode) +{ + uint8_t val = 0; + switch(mode) + { + case MSB_MODE: + val = 0x0F; + break; + + case I2S_MODE: + val = 0x0C; + + break; + + case LSB_MODE: + val = 0x0D; + break; + + case PCM_MODE: + val = 0x2F; + break; + } + codecWriteVal(CODEC_ES8311, 0x09, val); +} + diff --git a/PLAT/driver/board/ec618_0h00/src/audio/codec/es8388/es8388.c b/PLAT/driver/board/ec618_0h00/src/audio/codec/es8388/es8388.c new file mode 100644 index 0000000..8f32396 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/audio/codec/es8388/es8388.c @@ -0,0 +1,146 @@ +#include "i2s.h" + +#define ES8388_FS_NUM 256 + + +i2sI2cCfg_t es8388_regInfo[] = +{ + {0x00,0x80}, + {0x00,0x06}, + {0x02,0xf3}, + {0x35,0xa0}, + {0x36,0x08}, + + {0x08,0x84}, // Bit7: 1 means master(default); 0 means slave; 0x84: master 32bit; 0x86: master 16bit + {0x0d,0x02}, // 256 ratio + {0x18,0x02}, // 256 ratio + + {0x07,0x7c}, + {0x2b,0x80}, + {0x2d,0x10}, + {0x00,0x30}, + {0x01,0x00}, + {0x03,0x00}, + {0x06,0xff}, + {0x09,0x88}, // Analog PGA: +24dB + {0x0a,0xfc}, + {0x0b,0x02}, + {0x0c,0x0D}, // 0x0d: 16bit Left; 0x0c: 16bit I2S; 0x0e: 16bit Right; 0x0f: 16bit PCM; + {0x10,0x00}, // digital gain ADCL + {0x11,0x00}, // digital gain ADCR + {0x12,0x05}, + {0x17,0x1B}, // 0x1b: 16bit Left; 0x19: 16bit I2S; 0x1d: 16bit Right; 0x1f: 16bit PCM; + {0x19,0x76}, + {0x1a,0x45}, // digital gain DACL + {0x1b,0x00}, // digital gain DACR + {0x26,0x12}, + {0x2e,0x00}, + {0x2f,0x00}, + {0x30,0x00}, + {0x31,0x00}, + {0x02,0x00}, + {0x00,0x37}, + {0x01,0x20}, + {0x27,0xb8}, + {0x2a,0xb8}, + {0x04,0x3c}, + {0x00,0x36}, + {0x19,0x72}, + {0x2e,0x1e}, + {0x2f,0x1e}, + {0x30,0x1e}, + {0x31,0x1e}, +}; + +uint16_t es8388GetRegCnt(char* regName) +{ + if (strcmp(regName, "es8388_master") == 0) + { + return (sizeof(es8388_regInfo) / sizeof(es8388_regInfo[0])); + } + else if (strcmp(regName, "es8388_slave") == 0) + { + return (sizeof(es8388_regInfo) / sizeof(es8388_regInfo[0])); + } + + return 0; +} + +void codecI2cInit(void); +void codecI2cWrite(char* codecName, uint8_t slaveAddr, i2sI2cCfg_t* i2sI2cCfg); +uint8_t codecI2cRead(uint8_t slaveAddr, uint8_t regAddr); + + + +void es8388MasterInit() +{ + //uint8_t dataRead = 0xff; + + codecI2cInit(); + + for (int i = 0; i < es8388GetRegCnt("es8388_master"); i++) + { + codecI2cWrite("es8388", ES8388_IICADDR, (i2sI2cCfg_t*)&es8388_regInfo[i]); + //delay_us(10000); + } + +#if 0 + for (int i = 0; i < es8388GetRegCnt("es8388_master"); i++) + { + dataRead = codecI2cRead(ES8388_IICADDR, es8388_regInfo[i].regAddr); + printf("reg = 0x%02x, val = 0x%02x\n", es8388_regInfo[i].regAddr, dataRead); + } +#endif +} + +void es8388SlaveInit() +{ + //uint8_t dataRead = 0xff; + es8388MasterInit(); + + i2sI2cCfg_t i2sI2cCfg; + i2sI2cCfg.regAddr = 0x08; + i2sI2cCfg.regVal = 0<<7; // Bit7 --> 1: master(default); 0: slave + codecI2cWrite("es8388", ES8388_IICADDR, (i2sI2cCfg_t*)&i2sI2cCfg); + +#if 0 + for (int i = 0; i < es8388GetRegCnt("es8388_slave"); i++) + { + dataRead = codecI2cRead(ES8388_IICADDR, es8388_regInfo[i].regAddr); + printf("reg = 0x%02x, val = 0x%02x\n", es8388_regInfo[i].regAddr, dataRead); + } +#endif +} + + +uint16_t es8388GetFs() +{ + return ES8388_FS_NUM; +} + +void es8388SetMode(i2sMode_e mode) +{ + uint8_t val = 0; + + switch(mode) + { + case MSB_MODE: + val = 0x1b; + break; + + case I2S_MODE: + val = 0x19; + break; + + case LSB_MODE: + val = 0x1d; + break; + + case PCM_MODE: + val = 0x1f; + break; + } + + codecWriteVal(CODEC_ES8388, 0x17, val); +} + diff --git a/PLAT/driver/board/ec618_0h00/src/audio/codec/nau88c22/nau88c22.c b/PLAT/driver/board/ec618_0h00/src/audio/codec/nau88c22/nau88c22.c new file mode 100644 index 0000000..e8f5ea4 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/audio/codec/nau88c22/nau88c22.c @@ -0,0 +1,79 @@ +#include "i2s.h" + +#define NAU88C22_FS_NUM 256 + + +i2sI2cCfg_t NAU88C22_slaveRegInfo[] = +{ + {0x00,0x000}, + {0x01,0x1FD}, + {0x02,0x1BF}, + {0x03,0x1EF}, + //{0x04,0x008}, + {0x06,0x000}, + + {0x0A,0x008}, + //{0x0B,0x1FF}, + //{0x0C,0x1FF}, + + {0x2C,0x033}, + {0x2D,0x012}, + {0x2E,0x012}, + + {0x32,0x001}, + {0x33,0x001}, + {0x34,0x139}, + {0x35,0x139}, + +}; + +uint16_t NAU88C22GetRegCnt(char* regName) +{ + if (strcmp(regName, "NAU88C22_slave") == 0) + { + return (sizeof(NAU88C22_slaveRegInfo) / sizeof(NAU88C22_slaveRegInfo[0])); + } + else if (strcmp(regName, "NAU88C22_master") == 0) + { + return (sizeof(NAU88C22_slaveRegInfo) / sizeof(NAU88C22_slaveRegInfo[0])); + } + + return 0; +} + +void codecI2cInit(void); +void codecI2cWrite(char* codecName, uint8_t slaveAddr, i2sI2cCfg_t* i2sI2cCfg); +uint8_t codecI2cRead(uint8_t slaveAddr, uint8_t regAddr); + + +void nau88c22MasterInit() +{ + +} + +void nau88c22SlaveInit() +{ + uint8_t dataRead = 0xff; + + codecI2cInit(); + + for (int i = 0; i < NAU88C22GetRegCnt("NAU88C22_slave"); i++) + { + codecI2cWrite("NAU88C22", NAU88C22_IICADDR, (i2sI2cCfg_t*)&NAU88C22_slaveRegInfo[i]); + } + + for (int i = 0; i < NAU88C22GetRegCnt("NAU88C22_slave"); i++) + { + dataRead = codecI2cRead(NAU88C22_IICADDR, NAU88C22_slaveRegInfo[i].regAddr); + printf("reg = 0x%02x, val = 0x%02x\n", NAU88C22_slaveRegInfo[i].regAddr, dataRead); + } +} + +uint16_t NAU88C22GetFs() +{ + return NAU88C22_FS_NUM; +} + + + + diff --git a/PLAT/driver/board/ec618_0h00/src/bsp.c b/PLAT/driver/board/ec618_0h00/src/bsp.c new file mode 100644 index 0000000..b1f99cc --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/bsp.c @@ -0,0 +1,319 @@ +/**************************************************************************** + * + * Copy right: 2018 Copyrigths of AirM2M Ltd. + * File name: bsp.c + * Description: + * History: + * + ****************************************************************************/ +#include +#include +#include +#include "Driver_Common.h" +#include "clock.h" +#include "bsp.h" +#include "system_ec618.h" +#include DEBUG_LOG_HEADER_FILE +#include "ec_string.h" +#include "mem_map.h" +#if FEATURE_CCIO_ENABLE +#include "uart_device.h" +#endif +#include "dbversion.h" +#include "clock.h" +#include "hal_adcproxy.h" +#include "apmu_external.h" + +extern ARM_DRIVER_USART Driver_USART0; +extern ARM_DRIVER_USART Driver_USART1; + +ARM_DRIVER_USART *UsartPrintHandle = NULL; +ARM_DRIVER_USART *UsartUnilogHandle = NULL; +ARM_DRIVER_USART *UsartAtCmdHandle = NULL; + +static uint8_t OSState = 0; // OSState = 0 os not start, OSState = 1 os started +extern void trimAdcSetGolbalVar(void); + +void BSP_InitUartDriver(ARM_DRIVER_USART *drvHandler, + ARM_POWER_STATE powerMode, + uint32_t settings, + uint32_t baudRate, + ARM_USART_SignalEvent_t cb_event) +{ + if(drvHandler) + { + drvHandler->Initialize(cb_event); + drvHandler->PowerControl(powerMode); + drvHandler->Control(settings, baudRate); + } +} + +void BSP_DeinitUartDriver(ARM_DRIVER_USART *drvHandler) +{ + if(drvHandler) + { + drvHandler->PowerControl(ARM_POWER_OFF); + drvHandler->Uninitialize(); + } +} + +#if defined ( __GNUC__ ) + +/* + * retarget for _write implementation + * Parameter: ch: character will be out + */ +int io_putchar(int ch) +{ + if (UsartPrintHandle != NULL) + UsartPrintHandle->SendPolling((uint8_t*)&ch, 1); + return 0; +} + +/* + * retarget for _read implementation + * Parameter: ch: character will be read + */ +int io_getchar() +{ + uint8_t ch = 0; + if (UsartPrintHandle != NULL) + UsartPrintHandle->Receive(&ch, 1); + return (ch); +} + + +int fgetc(FILE *f) +{ + uint8_t ch = 0; + if (UsartPrintHandle != NULL) + UsartPrintHandle->Receive(&ch, 1); + return (ch); +} + +__attribute__((weak,noreturn)) +void __aeabi_assert (const char *expr, const char *file, int line) { + printf("Assert, expr:%s, file: %s, line: %d\r\n", expr, file, line); + while(1); +} + + +void __assert_func(const char *filename, int line, const char *assert_func, const char *expr) +{ + for(uint8_t i = 0; i<5; i++) + { + uniLogFlushOut(); + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, assert_func_1, P_ERROR, "Assert, expr:%s, file: %s, line: %d\r\n", expr, filename, line); + } + while(1); +} + + + +#elif defined (__CC_ARM) + +/* + * retarget for printf implementation + * Parameter: ch: character will be out + * f: not used + */ +int fputc(int ch, FILE *f) +{ + if (UsartPrintHandle != NULL) + UsartPrintHandle->SendPolling((uint8_t*)&ch,1); + return 0; +} + +/* + * retarget for scanf implementation + * Parameter: f: not used + */ +int fgetc(FILE *f) +{ + uint8_t ch = 0; + if (UsartPrintHandle != NULL) + UsartPrintHandle->Receive(&ch,1); + return (ch); +} + +__attribute__((weak,noreturn)) +void __aeabi_assert (const char *expr, const char *file, int line) { + printf("Assert, expr:%s, file: %s, line: %d\r\n", expr, file, line); + while(1); +} + +#endif + + + +uint32_t GET_PMU_RAWFLASH_OFFSET(void) +{ + return FLASH_MEM_BACKUP_ADDR; +} + + + +void setOSState(uint8_t state) +{ + OSState = state; +} + +PLAT_PA_RAMCODE uint8_t getOSState(void) //1 os started. 0 no OS or OS not started yet +{ + return OSState; +} + + +uint8_t* getBuildInfo(void) +{ + return (uint8_t *)BSP_HEADER; +} + +uint8_t* getVersionInfo(void) +{ + return (uint8_t *)VERSION_INFO; +} + +uint8_t* getATIVersionInfo(void) +{ + return (uint8_t *)ATI_VERSION_INFO; +} + +//move here since this is an common and opensource place +uint8_t* getDebugDVersion(void) +{ + return (uint8_t*)DB_VERSION_UNIQ_ID; +} + +#ifdef UINILOG_FEATURE_ENABLE +/** + \fn void logToolCommandHandle(uint8_t *atcmd_buffer, uint32_t len) + \brief handle downlink command sent from unilog tool EPAT + if need to handle more command in future, add command-handler table + \param[in] event UART event, note used in this function + \param[in] cmd_buffer command received from UART + \param[in] len command length + \returns void +*/ +void logToolCommandHandle(uint32_t event, uint8_t *cmd_buffer, uint32_t len) +{ + (void)event; + + uint8_t * LogDbVserion=getDebugDVersion(); + + if(ec_strnstr((const char *)cmd_buffer, "^logversion", len)) + { + + ECPLAT_PRINTF(UNILOG_PLA_INTERNAL_CMD, get_log_version, P_SIG, "LOGVERSION:%s",LogDbVserion); + + } + else + { + + ECPLAT_PRINTF(UNILOG_PLA_STRING, get_log_version_1, P_ERROR, "%s", "invalid command from EPAT"); + + } + + return; + +} + + +/** + * unilog entity is removed for the reason of BSP small image. + * for more implementation details, pls refer to + * gCustSerlEntity[CUST_ENTITY_UNILOG] in ccio_provider.c + */ + +/* + * set unilog uart port + * Parameter: port: for unilog + * Parameter: baudrate: uart baudrate + */ + void SetUnilogUart(usart_port_t port, uint32_t baudrate, bool startRecv) +{ + ARM_POWER_STATE powerMode = ARM_POWER_FULL; + uint32_t ctrlSetting = ARM_USART_MODE_ASYNCHRONOUS | ARM_USART_DATA_BITS_8 | \ + ARM_USART_PARITY_NONE | ARM_USART_STOP_BITS_1 | \ + ARM_USART_FLOW_CONTROL_NONE; + + if (port == PORT_USART_0) + { +#if (RTE_UART0) + UsartUnilogHandle = &CREATE_SYMBOL(Driver_USART, 0); +#endif + } + else if (port == PORT_USART_1) + { +#if (RTE_UART1) + UsartUnilogHandle = &CREATE_SYMBOL(Driver_USART, 1); +#endif + } + + if (UsartUnilogHandle == NULL) return; + +#ifdef FEATURE_CCIO_ENABLE + UartDevConf_t uartDevConf; + UartHwConf_t *uartHwConf = &uartDevConf.hwConf; + + memset(&uartDevConf, 0, sizeof(UartDevConf_t)); + + uartHwConf->powerMode = powerMode; + uartHwConf->ctrlSetting = ctrlSetting; + uartHwConf->baudRate = baudrate; + + uartDevConf.drvHandler = UsartUnilogHandle; + uartDevConf.mainUsage = CSIO_DT_DIAG; + uartDevConf.speedType = CCIO_ST_HIGH; + if(startRecv) + { + uartDevConf.bmCreateFlag = CCIO_TASK_FLAG_RX; + } + else + { + uartDevConf.bmCreateFlag = CCIO_TASK_FLAG_NONE; + } + + uartDevCreate(port, &uartDevConf); +#else + BSP_InitUartDriver(UsartUnilogHandle, powerMode, ctrlSetting, baudrate, NULL); +#endif +} + + +void FlushUnilogOutput(void) +{ + uniLogFlushOut(); + + if(UsartUnilogHandle == NULL) + return; + UsartUnilogHandle->Control(ARM_USART_CONTROL_FLUSH_TX, 0); +} +#endif + +void BSP_CommonInit(void) +{ + SystemCoreClockUpdate(); + + PAD_driverInit(); + + GPR_initialize(); + + trimAdcSetGolbalVar(); + + apmuInit(); + + //interrupt config + IC_PowupInit(); + + if(apmuGetAPBootFlag() == 0) // power on + { + apmuSetCPFastBoot(false); // set cp fast boot in case of cp dap wakeup + } + + cpADCInit(); // enable adc ref output, need stable time + + BOOT_TIMESTAMP_SET(1, 3); + +} + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/bf30a2/bf30a2.c b/PLAT/driver/board/ec618_0h00/src/camera/bf30a2/bf30a2.c new file mode 100644 index 0000000..78c0af5 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/bf30a2/bf30a2.c @@ -0,0 +1,121 @@ +#include "cameraDrv.h" + +camI2cCfg_t bf30a2_1sdrRegInfo[] = +{ + {0xf2,0x01},//soft reset + {0xcf,0xb0},//power up + {0x12,0x20},//MTK:20 ZX:10 RDA:40 + {0x15,0x80}, + {0x6b,0x71}, + {0x00,0x40}, + {0x04,0x00}, + {0x06,0x26}, + {0x08,0x07}, + {0x1c,0x12}, + {0x20,0x20}, + {0x21,0x20}, + {0x34,0x02}, + {0x35,0x02}, + {0x36,0x21}, + {0x37,0x13}, + {0xca,0x23}, + {0xcb,0x22}, + {0xcc,0x89}, + {0xcd,0x4c}, + {0xce,0x6b}, + {0xa0,0x8e}, + {0x01,0x1b}, + {0x02,0x1d}, + {0x13,0x08}, + {0x87,0x13}, + {0x8b,0x08}, + {0x70,0x1f}, + {0x71,0x40}, + {0x72,0x0a}, + {0x73,0x62}, + {0x74,0xa2}, + {0x75,0xbf}, + {0x76,0x02}, + {0x77,0xcc}, + {0x40,0x32}, + {0x41,0x28}, + {0x42,0x26}, + {0x43,0x1d}, + {0x44,0x1a}, + {0x45,0x14}, + {0x46,0x11}, + {0x47,0x0f}, + {0x48,0x0e}, + {0x49,0x0d}, + {0x4B,0x0c}, + {0x4C,0x0b}, + {0x4E,0x0a}, + {0x4F,0x09}, + {0x50,0x09}, + {0x24,0x50}, + {0x25,0x36}, + {0x80,0x00}, + {0x81,0x20}, + {0x82,0x40}, + {0x83,0x30}, + {0x84,0x50}, + {0x85,0x30}, + {0x86,0xD8}, + {0x89,0x45}, + {0x8a,0x33}, + {0x8f,0x81}, + {0x91,0xff}, + {0x92,0x08}, + {0x94,0x82}, + {0x95,0xfd}, + {0x9a,0x20}, + {0x9e,0xbc}, + {0xf0,0x8f}, + {0x51,0x06}, + {0x52,0x25}, + {0x53,0x2b}, + {0x54,0x0F}, + {0x57,0x2A}, + {0x58,0x22}, + {0x59,0x2c}, + {0x23,0x33}, + {0xa1,0x93}, + {0xa2,0x0f}, + {0xa3,0x2a}, + {0xa4,0x08}, + {0xa5,0x26}, + {0xa7,0x80}, + {0xa8,0x80}, + {0xa9,0x1e}, + {0xaa,0x19}, + {0xab,0x18}, + {0xae,0x50}, + {0xaf,0x04}, + {0xc8,0x10}, + {0xc9,0x15}, + {0xd3,0x0c}, + {0xd4,0x16}, + {0xee,0x06}, + {0xef,0x04}, + {0x55,0x34}, + {0x56,0x9c}, + {0xb1,0x98}, + {0xb2,0x98}, + {0xb3,0xc4}, + {0xb4,0x0C}, + {0xa0,0x8f}, + {0x13,0x07}, +}; + +uint16_t bf30a2GetRegCnt(char* regName) +{ + if (strcmp(regName, "bf30a2_1sdr") == 0) + { + return (sizeof(bf30a2_1sdrRegInfo) / sizeof(bf30a2_1sdrRegInfo[0])); + } + + + return 0; +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/camAT.c b/PLAT/driver/board/ec618_0h00/src/camera/camAT.c new file mode 100644 index 0000000..face700 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/camAT.c @@ -0,0 +1,99 @@ +#include "cameraDrv.h" +#include "quirc.h" + +static volatile bool isTransferDone; +extern void delay_us(uint32_t); +struct quirc *qr; +uint8_t* pic0Internal = NULL; + + +static void camRecvCb(uint32_t event) +{ + if(event & ARM_SPI_EVENT_TRANSFER_COMPLETE) + { + isTransferDone = true; + } +} + +bool decodeBegin(uint8_t* result) +{ + int num_codes=0, w, h; + struct quirc_code code; + struct quirc_data data; + quirc_decode_error_t err; + + quirc_begin(qr, &w, &h); + quirc_end(qr); + num_codes = quirc_count(qr); + + if (num_codes != 1) + { + return false; + } + + quirc_extract(qr, 0, &code); + /* Decoding stage */ + err = quirc_decode(&code, &data); + if (err) + { + return false; + //printf("D F2: %s\n", quirc_strerror(err)); + } + else + { + memcpy(result, data.payload, data.payload_len); + return true; + //printf("Data: %s\n", data.payload); + } +} + +void camPrepare(uint8_t* pic0) +{ + pic0Internal = pic0; + + // Camera register part + camRegCfg(); // Only need to init once + + // Quirc part + qr = quirc_new(); + quirc_init(qr, pic0, 320, 240); +} + +bool camBegin(bool start, uint8_t* result) +{ + uint32_t timeOut_ms = 5000; + + if (start) + { + camInit(camRecvCb); + + camStart(true); + camRecv(pic0Internal); + + do + { + delay_us(1000); + } + while((isTransferDone == false) && --timeOut_ms); + } + else + { + camStart(false); + return true; + } + + if (isTransferDone) + { + isTransferDone = false; + + return decodeBegin(result); + } + else + { + // Error: camera doesn't take picture fail + return false; + } +} + + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/cameraDrv.c b/PLAT/driver/board/ec618_0h00/src/camera/cameraDrv.c new file mode 100644 index 0000000..e4e8dc7 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/cameraDrv.c @@ -0,0 +1,400 @@ +#include "cameraDrv.h" + +extern cspiDrvInterface_t cspiDrvInterface0; +extern cspiDrvInterface_t cspiDrvInterface1; + +extern camI2cCfg_t sp0A39Cfg[]; +extern camI2cCfg_t sp0821Cfg[]; +extern camI2cCfg_t gc6123Cfg[]; +extern camI2cCfg_t gc032ACfg[]; +extern camI2cCfg_t bf30a2Cfg[]; +extern cspiCtrl_t cspiCtrl; +extern cspiIntCtrl_t cspiIntCtrl; +extern cspiDataFmt_t cspiDataFmt; + +extern ARM_DRIVER_I2C Driver_I2C0; +static ARM_DRIVER_I2C *i2cDrvInstance = &CREATE_SYMBOL(Driver_I2C, 0); + +#define EIGEN_CSPI(n) ((CSPI_TypeDef *) (MP_I2S0_BASE_ADDR + 0x1000*n)) + + +#if (CAMERA_ENABLE_SP0A39) + #if (SP0A39_2SDR) + char* regName = "sp0a39_2sdr"; + #elif (SP0A39_1SDR) + char* regName = "sp0a39_1sdr"; + #endif + +#elif (CAMERA_ENABLE_SP0821) + #if (SP0821_2SDR) + char* regName = "sp0821_2sdr"; + #elif (SP0821_1SDR) + char* regName = "sp0821_1sdr"; + #endif + +#elif (CAMERA_ENABLE_GC6123) + #if (GC6123_2SDR) + char* regName = "gc6123_2sdr"; + #elif (GC6123_1SDR) + char* regName = "gc6123_1sdr"; + #endif + +#elif (CAMERA_ENABLE_GC032A) + #if (GC032A_2SDR) + char* regName = "gc032a_2sdr"; + #elif (GC032A_1SDR) + char* regName = "gc032a_1sdr"; + #endif +#elif (CAMERA_ENABLE_BF30A2) + #if (BF30A2_1SDR) + char* regName = "bf30a2_1sdr"; + #endif +#elif (CAMERA_ENABLE_GC6153) + #if (GC6153_1SDR) + char* regName = "gc6153_1sdr"; + #endif +#endif + +static uint8_t slaveAddr; +static uint16_t regCnt; +static camI2cCfg_t* regInfo = NULL; + +#if (RTE_CSPI1 == 1) +static cspiDrvInterface_t *cspiDrv = &CREATE_SYMBOL(cspiDrvInterface, 1); +#else +static cspiDrvInterface_t *cspiDrv = &CREATE_SYMBOL(cspiDrvInterface, 0); +#endif +extern void delay_us(uint32_t us); + +void findRegInfo(char* regName, uint8_t* slaveAddr, uint16_t* regCnt, camI2cCfg_t** regInfo) +{ + if (strcmp(regName, "sp0a39_2sdr") == 0) + { + extern camI2cCfg_t sp0A39_2sdrRegInfo[]; + *regInfo = sp0A39_2sdrRegInfo; + *slaveAddr = SP0A39_I2C_ADDR; + *regCnt = sp0a39GetRegCnt(regName); + } + else if (strcmp(regName, "sp0a39_1sdr") == 0) + { + extern camI2cCfg_t sp0A39_1sdrRegInfo[]; + *regInfo = sp0A39_1sdrRegInfo; + *slaveAddr = SP0A39_I2C_ADDR; + *regCnt = sp0a39GetRegCnt(regName); + } + else if (strcmp(regName, "sp0821_2sdr") == 0) + { + extern camI2cCfg_t sp0821_2sdrRegInfo[]; + *regInfo = sp0821_2sdrRegInfo; + *slaveAddr = SP0821_I2C_ADDR; + *regCnt = sp0821GetRegCnt(regName); + } + else if (strcmp(regName, "sp0821_1sdr") == 0) + { + extern camI2cCfg_t sp0821_1sdrRegInfo[]; + *regInfo = sp0821_1sdrRegInfo; + *slaveAddr = SP0821_I2C_ADDR; + *regCnt = sp0821GetRegCnt(regName); + } + else if (strcmp(regName, "gc6123_2sdr") == 0) + { + extern camI2cCfg_t gc6123_2sdrRegInfo[]; + *regInfo = gc6123_2sdrRegInfo; + *slaveAddr = GC6123_I2C_ADDR; + *regCnt = gc6123GetRegCnt(regName); + } + else if (strcmp(regName, "gc6123_1sdr") == 0) + { + extern camI2cCfg_t gc6123_1sdrRegInfo[]; + *regInfo = gc6123_1sdrRegInfo; + *slaveAddr = GC6123_I2C_ADDR; + *regCnt = gc6123GetRegCnt(regName); + } + else if (strcmp(regName, "gc032a_2sdr") == 0) + { + extern camI2cCfg_t gc032A_2sdrRegInfo[]; + *regInfo = gc032A_2sdrRegInfo; + *slaveAddr = GC032A_I2C_ADDR; + *regCnt = gc032aGetRegCnt(regName); + } + else if (strcmp(regName, "gc032a_1sdr") == 0) + { + extern camI2cCfg_t gc032A_1sdrRegInfo[]; + *regInfo = gc032A_1sdrRegInfo; + *slaveAddr = GC032A_I2C_ADDR; + *regCnt = gc032aGetRegCnt(regName); + } + else if (strcmp(regName, "bf30a2_1sdr") == 0) + { + extern camI2cCfg_t bf30a2_1sdrRegInfo[]; + *regInfo = bf30a2_1sdrRegInfo; + *slaveAddr = BF30A2_I2C_ADDR; + *regCnt = bf30a2GetRegCnt(regName); + } + else if (strcmp(regName, "gc6153_1sdr") == 0) + { + extern camI2cCfg_t gc6153_1sdrRegInfo[]; + *regInfo = gc6153_1sdrRegInfo; + *slaveAddr = GC6153_I2C_ADDR; + *regCnt = gc6153GetRegCnt(regName); + } +} + + +void camI2cInit() +{ + i2cDrvInstance->Initialize(NULL); + i2cDrvInstance->PowerControl(ARM_POWER_FULL); + i2cDrvInstance->Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_STANDARD); + i2cDrvInstance->Control(ARM_I2C_BUS_CLEAR, 0); + + // Backup some info about this sensor + findRegInfo(regName, &slaveAddr, ®Cnt, ®Info); +} + +void camI2cWrite(uint8_t slaveAddr, uint8_t regAddr, uint8_t regData, uint32_t num) +{ + uint8_t tempBuffer[2]; + + tempBuffer[0] = regAddr; + tempBuffer[1] = regData; + i2cDrvInstance->MasterTransmit(slaveAddr, tempBuffer, num, false); +} + +uint8_t camI2cRead(uint8_t slaveAddr, uint8_t regAddr) +{ + uint8_t a; + a = regAddr; + uint8_t readData; + i2cDrvInstance->MasterTransmit(slaveAddr, (uint8_t *)&a, 1, true); + i2cDrvInstance->MasterReceive(slaveAddr, &readData, 1, false); + return readData; +} + +uint8_t camReadReg(uint8_t regAddr) +{ + uint8_t recvData; + + recvData = camI2cRead(slaveAddr, regAddr); + return recvData; +} + +void camWriteReg(camI2cCfg_t* regInfo) +{ + camI2cWrite(slaveAddr, regInfo->regAddr, regInfo->regVal, 2); +} + + + +void camRegCfg() +{ + //uint8_t dataRead; + + camI2cInit(); + + // Configure all the registers about this sensor + for (int i=0; i < regCnt; i++) + { + camI2cWrite(slaveAddr, regInfo[i].regAddr, regInfo[i].regVal, 2); + delay_us(10000); // delay 10ms + +#if 0 + dataRead = camI2cRead(slaveAddr, regInfo[i].regAddr); + printf("reg addr=0x%02x, reg val=0x%02x\n", regInfo[i].regAddr, dataRead); + delay_us(15000); +#endif + } +} + +void camInterfaceCfg(camParamCfg_t* config) +{ + cspiDataFmt.endianMode = config->endianMode; + cspiCtrl.rxWid = config->wireNum; + cspiCtrl.rxdSeq = config->rxSeq; + cspiCtrl.cpol = config->cpol; + cspiCtrl.cpha = config->cpha; + cspiCtrl.fillYonly = config->yOnly; + cspiCtrl.rowScaleRatio = config->rowScaleRatio; + cspiCtrl.colScaleRatio = config->colScaleRatio; + cspiCtrl.scaleBytes = config->scaleBytes; +} + +void camSetMemAddr(uint32_t dataAddr) +{ + cspiDrv->ctrl(CSPI_CTRL_MEM_ADDR , dataAddr); // register the recv memory +} + +void camInit(void* dataAddr, cspiCbEvent_fn cb) +{ + camResolution_e camResolution; + + // set all pin io to 2.7V since camera max voltage is 2.7V + GPR_clockEnable(PCLK_PMDIG); + *(uint32_t*)0x4d020018 = 1; + *(uint32_t*)0x4d040308 = 7; // 1:2.7V 7:3V + + + // Need to enable cspi first to make camera clock working + camParamCfg_t camParamCfg; + +#if (CAMERA_ENABLE_SP0A39) + #if (SP0A39_2SDR) + camParamCfg.wireNum = WIRE_2; + #elif (SP0A39_1SDR) + camParamCfg.wireNum = WIRE_1; + #endif + camParamCfg.endianMode = LSB_MODE; + camParamCfg.rxSeq = SEQ_0; + camParamCfg.cpha = 1; + camParamCfg.cpol = 0; + camResolution = CAM_CHAIN_COUNT; + +#elif (CAMERA_ENABLE_SP0821) + #if (SP0821_2SDR) + camParamCfg.wireNum = WIRE_2; + #elif (SP0821_1SDR) + camParamCfg.wireNum = WIRE_1; + #endif + camParamCfg.endianMode = LSB_MODE; + camParamCfg.rxSeq = SEQ_0; + camParamCfg.cpha = 1; + camParamCfg.cpol = 0; + camResolution = CAM_CHAIN_COUNT; + +#elif (CAMERA_ENABLE_GC6123) + #if (GC6123_2SDR) + camParamCfg.wireNum = WIRE_2; + #elif (GC6123_1SDR) + camParamCfg.wireNum = WIRE_1; + #endif + camParamCfg.endianMode = LSB_MODE; + camParamCfg.rxSeq = SEQ_1; + camParamCfg.cpha = 1; + camParamCfg.cpol = 0; + camParamCfg.yOnly = 1; + camParamCfg.rowScaleRatio = 0; + camParamCfg.colScaleRatio = 0; + camParamCfg.scaleBytes = 0; + camResolution = CAM_CHAIN_COUNT; + +#elif (CAMERA_ENABLE_GC032A) + #if (GC032A_2SDR) + camParamCfg.wireNum = WIRE_2; + #elif (GC032A_1SDR) + camParamCfg.wireNum = WIRE_1; + #endif + camParamCfg.endianMode = LSB_MODE; + camParamCfg.rxSeq = SEQ_0; + camParamCfg.cpha = 0; + camParamCfg.cpol = 0; + camResolution = CAM_CHAIN_COUNT; + if (camResolution == CAM_30W) + { + camParamCfg.yOnly = 0; + camParamCfg.rowScaleRatio = 0; + camParamCfg.colScaleRatio = 0; + camParamCfg.scaleBytes = 0; + } + else // CAM_8W + { + camParamCfg.yOnly = 1; + camParamCfg.rowScaleRatio = 1; + camParamCfg.colScaleRatio = 1; + camParamCfg.scaleBytes = 1; + } + +#elif (CAMERA_ENABLE_BF30A2) + #if (BF30A2_1SDR) + camParamCfg.wireNum = WIRE_1; + #endif + camParamCfg.endianMode = LSB_MODE; + camParamCfg.rxSeq = SEQ_0; + camParamCfg.cpha = 0; + camParamCfg.cpol = 0; + camParamCfg.yOnly = 1; + camParamCfg.rowScaleRatio = 0; + camParamCfg.colScaleRatio = 0; + camParamCfg.scaleBytes = 0; + camResolution = CAM_CHAIN_COUNT; +#elif (CAMERA_ENABLE_GC6153) + #if (GC6153_1SDR) + camParamCfg.wireNum = WIRE_1; + #endif + camParamCfg.endianMode = LSB_MODE; + camParamCfg.rxSeq = SEQ_1; + camParamCfg.cpha = 1; + camParamCfg.cpol = 0; + camParamCfg.yOnly = 1; + camParamCfg.rowScaleRatio = 0; + camParamCfg.colScaleRatio = 0; + camParamCfg.scaleBytes = 0; + camResolution = CAM_CHAIN_COUNT; +#endif + + camInterfaceCfg(&camParamCfg); + + cspiDrv->ctrl(CSPI_CTRL_MEM_ADDR , (uint32_t)dataAddr); // register the recv memory + cspiDrv->init(cb); + + cspiDrv->powerCtrl(CSPI_POWER_FULL); + cspiDrv->ctrl(CSPI_CTRL_DATA_FORMAT , 0); // control cspi + cspiDrv->ctrl(CSPI_CTRL_RXTOR , 0); + cspiDrv->ctrl(CSPI_CTRL_FRAME_INFO0 , 0); + cspiDrv->ctrl(CSPI_CTRL_INT_CTRL , 0); + + cspiDrv->ctrl(CSPI_CTRL_CSPICTL , 0); + cspiDrv->ctrl(CSPI_CTRL_DMA_CTRL , 0); + cspiDrv->ctrl(CSPI_CTRL_RESOLUTION_SET , camResolution); + cspiDrv->ctrl(CSPI_CTRL_BUS_SPEED, (camFrequence_e)CAM_25_5_M); // cspi working frequency +} + +void camStartStop(cspiStartStop_e startStop) +{ + cspiDrv->ctrl(CSPI_CTRL_START_STOP , (uint32_t)startStop); +} + +void cspiIntEnable(cspiIntEnable_e intEnable) +{ + cspiIntCtrl.frameStartIntEn = intEnable; + cspiDrv->ctrl(CSPI_CTRL_INT_CTRL , 0); // cspi interrupt enable or disable +} + +void camFlush() +{ + cspiDrv->ctrl(CSPI_CTRL_FLUSH_RX_FIFO , 0); // flush rx fifo +} + +void camRegisterIRQ(cspiInstance_e instance, camIrq_fn irqCb) +{ + IRQn_Type irqNum; + + if (instance == CSPI_0) + { + irqNum = PXIC0_I2S0_IRQn; + } + else + { + irqNum = PXIC0_I2S1_IRQn; + } + + XIC_SetVector(irqNum, irqCb); + XIC_EnableIRQ(irqNum); +} + +PLAT_FM_RAMCODE void camRecv(uint8_t * dataAddr) +{ + cspiDrv->ctrl(CSPI_CTRL_MEM_ADDR , (uint32_t)dataAddr); // register the recv memory + cspiDrv->recv(); +} + +uint32_t camGetCspiStats(cspiInstance_e instance) +{ + return EIGEN_CSPI(instance)->STAS; +} + +void camClearIntStats(cspiInstance_e instance, uint32_t mask) +{ + EIGEN_CSPI(instance)->STAS = mask; +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/gc032A/gc032A.c b/PLAT/driver/board/ec618_0h00/src/camera/gc032A/gc032A.c new file mode 100644 index 0000000..d167a52 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/gc032A/gc032A.c @@ -0,0 +1,666 @@ +#include "cameraDrv.h" + +camI2cCfg_t gc032A_2sdrRegInfo[] = +{ + {0xf3,0x83}, + {0xf5,0x0c}, + {0xf7,0x01},// gavin 20160820 + {0xf8,0x01}, + {0xf9,0x4e}, + {0xfa,0x10}, // gavin 20160820 + {0xfc,0x02}, + {0xfe,0x02}, + {0x81,0x03}, + {0xfe,0x00}, + {0x77,0x64}, + {0x78,0x40}, + {0x79,0x60}, + /*Analog&Cisctl*/ + {0xfe,0x00}, + {0x03,0x01}, + {0x04,0xc2}, + {0x05,0x01}, + {0x06,0xb8}, + {0x07,0x00}, + {0x08,0x08}, + {0x0a,0x00}, + {0x0c,0x00}, + {0x0d,0x01}, + {0x0e,0xe8}, + {0x0f,0x02}, + {0x10,0x88}, + {0x17,0x54}, + {0x19,0x08}, + {0x1a,0x0a}, + {0x1f,0x40}, + {0x20,0x30}, + {0x2e,0x80}, + {0x2f,0x2b}, + {0x30,0x1a}, + {0xfe,0x02}, + {0x03,0x02}, + {0x05,0xd7}, + {0x06,0x60}, + {0x08,0x80}, + {0x12,0x89}, + + /*SPI*/ + {0xfe,0x03}, + {0x51,0x01}, + {0x52,0x58}, // DDR Disable gavin 20160820 + {0x53,0x24}, // Disable CRC + {0x54,0x20}, + {0x55,0x00}, + {0x59,0x10}, + {0x5a,0x00}, + {0x5b,0x80}, + {0x5c,0x02}, + {0x5d,0xe0}, + {0x5e,0x01}, + {0x64,0x04}, //SCK Always OFF , gavin 20160820 + + /*blk*/ + {0xfe,0x00}, + {0x18,0x02}, + {0xfe,0x02}, + {0x40,0x22}, + {0x45,0x00}, + {0x46,0x00}, + {0x49,0x20}, + {0x4b,0x3c}, + {0x50,0x20}, + {0x42,0x10}, + + /*isp*/ + {0xfe,0x01}, + {0x0a,0xc5}, + {0x45,0x00}, + {0xfe,0x00}, + {0x40,0xff}, + {0x41,0x25}, + {0x42,0xcf}, + {0x43,0x10}, + {0x44,0x83}, + {0x46,0x22}, + {0x49,0x03}, + {0x52,0x02}, + {0x54,0x00}, + {0xfe,0x02}, + {0x22,0xf6}, + + /*Shading*/ + {0xfe,0x01}, + {0xc1,0x38}, + {0xc2,0x4c}, + {0xc3,0x00}, + {0xc4,0x32}, + {0xc5,0x24}, + {0xc6,0x16}, + {0xc7,0x08}, + {0xc8,0x08}, + {0xc9,0x00}, + {0xca,0x20}, + {0xdc,0x8a}, + {0xdd,0xa0}, + {0xde,0xa6}, + {0xdf,0x75}, + + /*AWB*//*20170110*/ + {0xfe, 0x01}, + {0x7c, 0x09}, + {0x65, 0x06}, + {0x7c, 0x08}, + {0x56, 0xf4}, + {0x66, 0x0f}, + {0x67, 0x84}, + {0x6b, 0x80}, + {0x6d, 0x12}, + {0x6e, 0xb0}, + {0xfe, 0x01}, + {0x90, 0x00}, + {0x91, 0x00}, + {0x92, 0xf4}, + {0x93, 0xd5}, + {0x95, 0x0f}, + {0x96, 0xf4}, + {0x97, 0x2d}, + {0x98, 0x0f}, + {0x9a, 0x2d}, + {0x9b, 0x0f}, + {0x9c, 0x59}, + {0x9d, 0x2d}, + {0x9f, 0x67}, + {0xa0, 0x59}, + {0xa1, 0x00}, + {0xa2, 0x00}, + {0x86, 0x00}, + {0x87, 0x00}, + {0x88, 0x00}, + {0x89, 0x00}, + {0xa4, 0x00}, + {0xa5, 0x00}, + {0xa6, 0xd4}, + {0xa7, 0x9f}, + {0xa9, 0xd4}, + {0xaa, 0x9f}, + {0xab, 0xac}, + {0xac, 0x9f}, + {0xae, 0xd4}, + {0xaf, 0xac}, + {0xb0, 0xd4}, + {0xb1, 0xa3}, + {0xb3, 0xd4}, + {0xb4, 0xac}, + {0xb5, 0x00}, + {0xb6, 0x00}, + {0x8b, 0x00}, + {0x8c, 0x00}, + {0x8d, 0x00}, + {0x8e, 0x00}, + {0x94, 0x50}, + {0x99, 0xa6}, + {0x9e, 0xaa}, + {0xa3, 0x0a}, + {0x8a, 0x00}, + {0xa8, 0x50}, + {0xad, 0x55}, + {0xb2, 0x55}, + {0xb7, 0x05}, + {0x8f, 0x00}, + {0xb8, 0xb3}, + {0xb9, 0xb6}, + + /*CC*/ + {0xfe,0x01}, + {0xd0,0x40}, + {0xd1,0xf8}, + {0xd2,0x00}, + {0xd3,0xfa}, + {0xd4,0x45}, + {0xd5,0x02}, + {0xd6,0x30}, + {0xd7,0xfa}, + {0xd8,0x08}, + {0xd9,0x08}, + {0xda,0x58}, + {0xdb,0x02}, + {0xfe,0x00}, + + /*Gamma*/ + {0xfe,0x00}, + {0xba,0x00}, + {0xbb,0x04}, + {0xbc,0x0a}, + {0xbd,0x0e}, + {0xbe,0x22}, + {0xbf,0x30}, + {0xc0,0x3d}, + {0xc1,0x4a}, + {0xc2,0x5d}, + {0xc3,0x6b}, + {0xc4,0x7a}, + {0xc5,0x85}, + {0xc6,0x90}, + {0xc7,0xa5}, + {0xc8,0xb5}, + {0xc9,0xc2}, + {0xca,0xcc}, + {0xcb,0xd5}, + {0xcc,0xde}, + {0xcd,0xea}, + {0xce,0xf5}, + {0xcf,0xff}, + + /*Auto Gamma*/ + {0xfe,0x00}, + {0x5a,0x08}, + {0x5b,0x0f}, + {0x5c,0x15}, + {0x5d,0x1c}, + {0x5e,0x28}, + {0x5f,0x36}, + {0x60,0x45}, + {0x61,0x51}, + {0x62,0x6a}, + {0x63,0x7d}, + {0x64,0x8d}, + {0x65,0x98}, + {0x66,0xa2}, + {0x67,0xb5}, + {0x68,0xc3}, + {0x69,0xcd}, + {0x6a,0xd4}, + {0x6b,0xdc}, + {0x6c,0xe3}, + {0x6d,0xf0}, + {0x6e,0xf9}, + {0x6f,0xff}, + + /*Gain*/ + {0xfe,0x00}, + {0x70,0x50}, + + /*AEC*/ + {0xfe,0x00}, + {0x4f,0x01}, + {0xfe,0x01}, + {0x0d,0x00},//08 add 20170110 + {0x12,0xa0}, + {0x13,0x3a}, + {0x44,0x04}, + {0x1f,0x30}, + {0x20,0x40}, + {0x26,0x9a}, + {0x3e,0x20}, + {0x3f,0x2d}, + {0x40,0x40}, + {0x41,0x5b}, + {0x42,0x82}, + {0x43,0xb7}, + {0x04,0x0a}, + {0x02,0x79}, + {0x03,0xc0}, + + /*measure window*/ + {0xfe,0x01}, + {0xcc,0x08}, + {0xcd,0x08}, + {0xce,0xa4}, + {0xcf,0xec}, + + /*DNDD*/ + {0xfe,0x00}, + {0x81,0xb8}, + {0x82,0x12}, + {0x83,0x0a}, + {0x84,0x01}, + {0x86,0x50}, + {0x87,0x18}, + {0x88,0x10}, + {0x89,0x70}, + {0x8a,0x20}, + {0x8b,0x10}, + {0x8c,0x08}, + {0x8d,0x0a}, + + /*Intpee*/ + {0xfe,0x00}, + {0x8f,0xaa}, + {0x90,0x9c}, + {0x91,0x52}, + {0x92,0x03}, + {0x93,0x03}, + {0x94,0x08}, + {0x95,0x44}, + {0x97,0x00}, + {0x98,0x00}, + + /*ASDE*/ + {0xfe,0x00}, + {0xa1,0x30}, + {0xa2,0x41}, + {0xa4,0x30}, + {0xa5,0x20}, + {0xaa,0x30}, + {0xac,0x32}, + + /*YCP*/ + {0xfe,0x00}, + {0xd1,0x3c}, + {0xd2,0x3c}, + {0xd3,0x38}, + {0xd6,0xf4}, + {0xd7,0x1d}, + {0xdd,0x73}, + {0xde,0x84}, + {0xfe,0x00}, + {0x05,0x01}, + {0x06,0xad}, + {0x07,0x00}, + {0x08,0x10}, + {0xfe,0x01}, + {0x25,0x00}, + {0x26,0x4d}, + {0x27,0x01}, + {0x28,0xce}, + {0x29,0x03}, + {0x2a,0x02}, + {0x2b,0x03}, + {0x2c,0x9c}, + {0x2d,0x04}, + {0x2e,0x36}, + {0x2f,0x04}, + {0x30,0xd0}, + {0x31,0x05}, + {0x32,0x6a}, + {0x33,0x06}, + {0x34,0x04}, + {0xfe,0x00}, +}; + +camI2cCfg_t gc032A_1sdrRegInfo[] = +{ + {0xf3,0x83}, //sync_output_en data_output_en + {0xf5,0x0c}, + {0xf7,0x01}, + {0xf8,0x01}, + {0xf9,0x4e}, + {0xfa,0x30}, + {0xfc,0x02}, + {0xfe,0x02}, + {0x81,0x03}, // doesn't show 0x81 addr + /*Analog*/ + {0xfe,0x00}, + {0x03,0x01}, // exposure high + {0x04,0xc2}, // exposure low + {0x05,0x01}, + {0x06,0x91}, + {0x07,0x00}, + {0x08,0x10}, + {0x0a,0x04}, + {0x0c,0x04}, + {0x0d,0x01}, + {0x0e,0xe8}, // height: 488 + {0x0f,0x02}, + {0x10,0x88}, // width: 652 VGA: 640*480 + {0x17,0x54}, + {0x19,0x04}, + {0x1a,0x0a}, + {0x1f,0x40}, + {0x20,0x30}, + {0x2e,0x80}, + {0x2f,0x2b}, + {0x30,0x1a}, + {0xfe,0x02}, + {0x03,0x02}, + {0x05,0xd7}, + {0x06,0x60}, + {0x08,0x80}, + {0x12,0x89}, + /*blk*/ + {0xfe,0x00}, + {0x18,0x02}, + {0xfe,0x02}, + {0x40,0x22}, + {0x45,0x00}, + {0x46,0x00}, + {0x49,0x20}, + {0x4b,0x3c}, + {0x50,0x20}, + {0x42,0x10}, + /*isp*/ + {0xfe,0x01}, + {0x0a,0xc5}, + {0x45,0x00}, + {0xfe,0x00}, + {0x40,0xff}, + {0x41,0x25}, + {0x42,0x83}, + {0x43,0x10}, + {0x44,0x83}, + {0x46,0x26}, + {0x49,0x03}, + {0x4f,0x01}, + {0xde,0x84}, + {0xfe,0x02}, + {0x22,0xf6}, + /*Shading*/ + {0xfe,0x00}, + {0x77,0x65}, + {0x78,0x40}, + {0x79,0x52}, + {0xfe,0x01}, + {0xc1,0x3c}, + {0xc2,0x50}, + {0xc3,0x00}, + {0xc4,0x32}, + {0xc5,0x24}, + {0xc6,0x16}, + {0xc7,0x08}, + {0xc8,0x08}, + {0xc9,0x00}, + {0xca,0x20}, + {0xdc,0x7a}, + {0xdd,0x7a}, + {0xde,0xa6}, + {0xdf,0x60}, + /*AWB*/ + {0xfe,0x01}, + {0x7c,0x09}, + {0x65,0x06}, + {0x7c,0x08}, + {0x56,0xf4}, + {0x66,0x0f}, + {0x67,0x84}, + {0x6b,0x80}, + {0x6d,0x12}, + {0x6e,0xb0}, + {0x86,0x00}, + {0x87,0x00}, + {0x88,0x00}, + {0x89,0x00}, + {0x8a,0x00}, + {0x8b,0x00}, + {0x8c,0x00}, + {0x8d,0x00}, + {0x8e,0x00}, + {0x8f,0x00}, + {0x90,0xef}, + {0x91,0xe1}, + {0x92,0x0c}, + {0x93,0xef}, + {0x94,0x65}, + {0x95,0x1f}, + {0x96,0x0c}, + {0x97,0x2d}, + {0x98,0x20}, + {0x99,0xaa}, + {0x9a,0x3f}, + {0x9b,0x2c}, + {0x9c,0x5f}, + {0x9d,0x3e}, + {0x9e,0xaa}, + {0x9f,0x67}, + {0xa0,0x60}, + {0xa1,0x00}, + {0xa2,0x00}, + {0xa3,0x0a}, + {0xa4,0xb6}, + {0xa5,0xac}, + {0xa6,0xc1}, + {0xa7,0xac}, + {0xa8,0x55}, + {0xa9,0xc3}, + {0xaa,0xa4}, + {0xab,0xba}, + {0xac,0xa8}, + {0xad,0x55}, + {0xae,0xc8}, + {0xaf,0xb9}, + {0xb0,0xd4}, + {0xb1,0xc3}, + {0xb2,0x55}, + {0xb3,0xd8}, + {0xb4,0xce}, + {0xb5,0x00}, + {0xb6,0x00}, + {0xb7,0x05}, + {0xb8,0xd6}, + {0xb9,0x8c}, + /*CC*/ + {0xfe,0x01}, + {0xd0,0x40}, + {0xd1,0xf8}, + {0xd2,0x00}, + {0xd3,0xfa}, + {0xd4,0x45}, + {0xd5,0x02}, + {0xd6,0x30}, + {0xd7,0xfa}, + {0xd8,0x08}, + {0xd9,0x08}, + {0xda,0x58}, + {0xdb,0x02}, + {0xfe,0x00}, + /*Gamma*/ + {0xfe,0x00}, + {0xba,0x00}, + {0xbb,0x04}, + {0xbc,0x0a}, + {0xbd,0x0e}, + {0xbe,0x22}, + {0xbf,0x30}, + {0xc0,0x3d}, + {0xc1,0x4a}, + {0xc2,0x5d}, + {0xc3,0x6b}, + {0xc4,0x7a}, + {0xc5,0x85}, + {0xc6,0x90}, + {0xc7,0xa5}, + {0xc8,0xb5}, + {0xc9,0xc2}, + {0xca,0xcc}, + {0xcb,0xd5}, + {0xcc,0xde}, + {0xcd,0xea}, + {0xce,0xf5}, + {0xcf,0xff}, + /*Auto Ga*/ + {0xfe,0x00}, + {0x5a,0x08}, + {0x5b,0x0f}, + {0x5c,0x15}, + {0x5d,0x1c}, + {0x5e,0x28}, + {0x5f,0x36}, + {0x60,0x45}, + {0x61,0x51}, + {0x62,0x6a}, + {0x63,0x7d}, + {0x64,0x8d}, + {0x65,0x98}, + {0x66,0xa2}, + {0x67,0xb5}, + {0x68,0xc3}, + {0x69,0xcd}, + {0x6a,0xd4}, + {0x6b,0xdc}, + {0x6c,0xe3}, + {0x6d,0xf0}, + {0x6e,0xf9}, + {0x6f,0xff}, + /*Gain*/ + {0xfe,0x00}, + {0x70,0x50}, + /*AEC*/ + {0xfe,0x00}, + {0x4f,0x01}, + {0xfe,0x01}, + {0x12,0xa0}, + {0x13,0x3a}, + {0x44,0x04}, + {0x1f,0x30}, + {0x20,0x40}, + {0x26,0x14}, + {0x27,0x01}, + {0x28,0xf4}, + {0x29,0x02}, + {0x2a,0x3a}, + {0x2b,0x02}, + {0x2c,0xac}, + {0x2d,0x02}, + {0x2e,0xf8}, + {0x2f,0x0b}, + {0x30,0x6e}, + {0x31,0x0e}, + {0x32,0x70}, + {0x33,0x12}, + {0x34,0x0c}, + {0x3c,0x00}, + {0x3e,0x20}, + {0x3f,0x2d}, + {0x40,0x40}, + {0x41,0x5b}, + {0x42,0x82}, + {0x43,0xb7}, + {0x04,0x0a}, + {0x02,0x79}, + {0x03,0xc0}, + /*measure*/ + {0xcc,0x08}, + {0xcd,0x08}, + {0xce,0xa4}, + {0xcf,0xec}, + /*DNDD*/ + {0xfe,0x00}, + {0x81,0xb8}, + {0x82,0x12}, + {0x83,0x0a}, + {0x84,0x01}, + {0x86,0x50}, + {0x87,0x18}, + {0x88,0x10}, + {0x89,0x70}, + {0x8a,0x20}, + {0x8b,0x10}, + {0x8c,0x08}, + {0x8d,0x0a}, + /*Intpee*/ + {0xfe,0x00}, + {0x8f,0xaa}, + {0x90,0x9c}, + {0x91,0x52}, + {0x92,0x03}, + {0x93,0x03}, + {0x94,0x08}, + {0x95,0x44}, + {0x97,0x00}, + {0x98,0x00}, + /*ASDE*/ + {0xfe,0x00}, + {0xa1,0x30}, + {0xa2,0x41}, + {0xa4,0x30}, + {0xa5,0x20}, + {0xaa,0x30}, + {0xac,0x32}, + /*YCP*/ + {0xfe,0x00}, + {0xd1,0x3c}, + {0xd2,0x3c}, + {0xd3,0x38}, + {0xd6,0xf4}, + {0xd7,0x1d}, + {0xdd,0x73}, + {0xde,0x84}, + /*SPI*/ + {0xfe,0x03}, // registers in REGF3 + {0x51,0x01}, + {0x52,0x0a}, // Y: 266 + {0x53,0x20}, // Ö»ÓÐ2bit£¬ÄÜÉè0x20? + {0x54,0x20}, // X: 0x220 = 544 + {0x55,0x00}, + {0x59,0x10}, + {0x5a,0x00}, // sync format£º + {0x5b,0x80}, + {0x5c,0x02}, // image width£º640 + {0x5d,0xe0}, + {0x5e,0x01}, // image height£º480 +}; + +uint16_t gc032aGetRegCnt(char* regName) +{ + if (strcmp(regName, "gc032a_2sdr") == 0) + { + return (sizeof(gc032A_2sdrRegInfo) / sizeof(gc032A_2sdrRegInfo[0])); + } + else if (strcmp(regName, "gc032a_1sdr") == 0) + { + return (sizeof(gc032A_1sdrRegInfo) / sizeof(gc032A_1sdrRegInfo[0])); + } + + return 0; +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/gc6123/gc6123.c b/PLAT/driver/board/ec618_0h00/src/camera/gc6123/gc6123.c new file mode 100644 index 0000000..dd8e9a2 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/gc6123/gc6123.c @@ -0,0 +1,360 @@ +#include "cameraDrv.h" + +camI2cCfg_t gc6123_2sdrRegInfo[] = +{ + {0xfe, 0xa0}, + {0xfe, 0xa0}, + {0xfe, 0xa0}, + {0xf1, 0x07}, //output enable + {0xf4, 0x00}, + //{0xf7, 0x00}, + //{0xfa, 0x00}, + {0xfc, 0x16}, //clock enable + + {0xfe , 0x00}, + + {0x08, 0x02}, //col start + {0x09, 0x01}, //window height + {0x0a, 0x48}, + {0x0b, 0x00}, //window width + {0x0c, 0xf4}, + {0x10, 0x48}, //sh_width + {0x11, 0x1d}, //tx_width + {0x14, 0x14}, //dark CFA + {0x15, 0x0a}, //sdark + {0x16, 0x04}, //AD pipe number + {0x18, 0xc2}, //rowsg_gap + {0x1a, 0x17}, //clk_delay_en + {0x1b, 0x1a}, //20121107 comv_r solve FPN-W/18 //70/adclk mode + {0x1c, 0x49}, //txhigh_en + {0x1d, 0xb0}, //vref + {0x1e, 0x52}, //20131231/53//20130306/52 //20121107 solve OBI/51 //ADC_r + //{0x1f, 0x3f}, + ///////////////////////////////////////////////////// + ////////////////////// ISP ////////////////////// + ///////////////////////////////////////////////////// + {0x20,0x5e}, + {0x21,0x38}, //autogray + {0x22,0x92}, //20121107 auto_DD_en/82 //02 + {0x24,0xa2}, //output_format + {0x26,0x03}, + {0x27,0x90}, //clock gating + {0x28,0x8c}, + {0x38,0x80}, //crop + {0x3b,0x01}, + {0x3c,0x40}, + {0x3d,0x00}, + {0x3e,0xf0}, + + ///////////////////////////////////////////////////// + ////////////////////// BLK ////////////////////// + ///////////////////////////////////////////////////// + {0x2a, 0x65}, //2f/BLK row select + {0x2c, 0x40}, //global offset + + ///////////////////////////////////////////////////// + ////////////////////// GAIN ///////////////////// + ///////////////////////////////////////////////////// + {0x3f, 0x12}, //20/global gain + + ///////////////////////////////////////////////////// + ////////////////////// DNDD ///////////////////// + ///////////////////////////////////////////////////// + {0x50, 0x45}, + {0x52, 0x4f}, //6c/DN b + {0x53, 0x81}, //a5/DN C + {0x58, 0x6f}, //20121107 dark_th 64 + {0xc3, 0x96}, //00 + + ///////////////////////////////////////////////////// + ////////////////////// ASDE ///////////////////// + ///////////////////////////////////////////////////// + {0xac, 0xb5}, + {0x5c, 0x80}, //60/OT_th + + ///////////////////////////////////////////////////// + ///////////////////// INTPEE //////////////////// + ///////////////////////////////////////////////////// + {0x63, 0x03}, //04/edge effect + {0x65, 0x23}, //43/42/edge max/min + + ///////////////////////////////////////////////////// + ///////////////////// GAMMA ///////////////////// + ///////////////////////////////////////////////////// + + ///////////////////////////////////////////////////// + ////////////////////// CC /////////////////////// + ///////////////////////////////////////////////////// + {0x66, 0x13}, + {0x67, 0x26}, + {0x68, 0x07}, + {0x69, 0xf5}, + {0x6a, 0xea}, + {0x6b, 0x21}, + {0x6c, 0x21}, + {0x6d, 0xe4}, + {0x6e, 0xfb}, + + ///////////////////////////////////////////////////// + ////////////////////// YCP ////////////////////// + ///////////////////////////////////////////////////// + {0x81, 0x48}, //38//cb + {0x82, 0x48}, //38//cr + {0x83, 0x4b}, //40/luma contrast + {0x84, 0x80}, //90/contrast center + {0x85, 0x00}, //06/luma offset + {0x86, 0xfb}, //skin cb + {0x87, 0x1d}, //skin cr + {0x88, 0x18}, //skin radius + {0x8d, 0x78}, //38/edge dec sa + {0x8e, 0x25}, //autogray + + ///////////////////////////////////////////////////// + ////////////////////// AEC ////////////////////// + ///////////////////////////////////////////////////// + {0xa4, 0x01}, + {0x9e, 0x01}, // increase fps + {0x9f, 0x90}, // 0x1c + {0xa0, 0x10}, + {0x90, 0x4a}, //0a //48 + {0x92, 0x40}, //40/target Y + {0xa2, 0x40}, //max_post_gain + {0xa3, 0x80}, //max_pre_gain + + ///////////////////////////////////////////////////// + ////////////////////// AWB ////////////////////// + ///////////////////////////////////////////////////// + {0xb0, 0xf8}, //f5/RGB high low + {0xb1, 0x24}, //18/Y to C + {0xb3, 0x20}, //0d/C max + {0xb4, 0x2d}, //22/C inter + {0xb5, 0x1b}, //22/C inter + {0xb6, 0x2e}, //C inter2 + {0xb7, 0x18}, //40/C inter3 + {0xb8, 0x13}, //20/number limit + {0xb9, 0x33}, + {0xba, 0x21}, + {0xbb, 0x61}, //42/speed & margin + {0xbf, 0x68}, //78/b limit + {0x4c, 0x08}, + {0x4d, 0x06}, + {0x4e, 0x7b}, + {0x4f, 0xa0}, + + {0xfe, 0x02}, + + {0x01, 0x03}, + {0x02, 0x02}, //LSB & Falling edge sample + //{0x03, 0x20}, //1-wire + {0x04, 0x20}, //[4] master_outformat + {0x05, 0x00}, + {0x09, 0x00}, //Reverse the high<->low byte. + {0x0a, 0x00}, //Data ID, 0x00-YUV422, 0x01-RGB565 + {0x13, 0xf0}, + + + ///////////////////////////////////////////////////// + ///////////////////// 2-wire //////////////////// + ///////////////////////////////////////////////////// + {0x03, 0x25}, //20 + {0xfd, 0x04}, + {0xf1, 0x07}, //00 + + + ///////////////////////////////////////////////////// + ///////////////////// 1-wire //////////////////// + ///////////////////////////////////////////////////// + //{0x03, 0x20}, //20 + //{0xfd, 0x00}, //00 + //{0xf1, 0x05}, + + {0xfe, 0x00}, +}; + +camI2cCfg_t gc6123_1sdrRegInfo[] = +{ + {0xfe, 0xa0}, + {0xfe, 0xa0}, + {0xfe, 0xa0}, + {0xf1, 0x07}, //output enable + {0xf4, 0x00}, + //{0xf7, 0x00}, + //{0xfa, 0x00}, + {0xfc, 0x16}, //clock enable + + {0xfe , 0x00}, + + {0x08, 0x02}, //col start + {0x09, 0x01}, //window height + {0x0a, 0x48}, + {0x0b, 0x00}, //window width + {0x0c, 0xf4}, + {0x10, 0x48}, //sh_width + {0x11, 0x1d}, //tx_width + {0x14, 0x14}, //dark CFA + {0x15, 0x0a}, //sdark + {0x16, 0x04}, //AD pipe number + {0x18, 0xc2}, //rowsg_gap + {0x1a, 0x17}, //clk_delay_en + {0x1b, 0x1a}, //20121107 comv_r solve FPN-W/18 //70/adclk mode + {0x1c, 0x49}, //txhigh_en + {0x1d, 0xb0}, //vref + {0x1e, 0x52}, //20131231/53//20130306/52 //20121107 solve OBI/51 //ADC_r + //{0x1f, 0x3f}, + ///////////////////////////////////////////////////// + ////////////////////// ISP ////////////////////// + ///////////////////////////////////////////////////// + {0x20,0x5e}, + {0x21,0x38}, //autogray + {0x22,0x92}, //20121107 auto_DD_en/82 //02 + {0x24,0xa2}, //output_format + {0x26,0x03}, + {0x27,0x90}, //clock gating + {0x28,0x8c}, + {0x38,0x80}, //crop + {0x3b,0x01}, + {0x3c,0x40}, + {0x3d,0x00}, + {0x3e,0xf0}, + + ///////////////////////////////////////////////////// + ////////////////////// BLK ////////////////////// + ///////////////////////////////////////////////////// + {0x2a, 0x65}, //2f/BLK row select + {0x2c, 0x40}, //global offset + + ///////////////////////////////////////////////////// + ////////////////////// GAIN ///////////////////// + ///////////////////////////////////////////////////// + {0x3f, 0x12}, //20/global gain + + ///////////////////////////////////////////////////// + ////////////////////// DNDD ///////////////////// + ///////////////////////////////////////////////////// + {0x50, 0x45}, + {0x52, 0x4f}, //6c/DN b + {0x53, 0x81}, //a5/DN C + {0x58, 0x6f}, //20121107 dark_th 64 + {0xc3, 0x96}, //00 + + ///////////////////////////////////////////////////// + ////////////////////// ASDE ///////////////////// + ///////////////////////////////////////////////////// + {0xac, 0xb5}, + {0x5c, 0x80}, //60/OT_th + + ///////////////////////////////////////////////////// + ///////////////////// INTPEE //////////////////// + ///////////////////////////////////////////////////// + {0x63, 0x03}, //04/edge effect + {0x65, 0x23}, //43/42/edge max/min + + ///////////////////////////////////////////////////// + ///////////////////// GAMMA ///////////////////// + ///////////////////////////////////////////////////// + + ///////////////////////////////////////////////////// + ////////////////////// CC /////////////////////// + ///////////////////////////////////////////////////// + {0x66, 0x13}, + {0x67, 0x26}, + {0x68, 0x07}, + {0x69, 0xf5}, + {0x6a, 0xea}, + {0x6b, 0x21}, + {0x6c, 0x21}, + {0x6d, 0xe4}, + {0x6e, 0xfb}, + + ///////////////////////////////////////////////////// + ////////////////////// YCP ////////////////////// + ///////////////////////////////////////////////////// + {0x81, 0x48}, //38//cb + {0x82, 0x48}, //38//cr + {0x83, 0x4b}, //40/luma contrast + {0x84, 0x80}, //90/contrast center + {0x85, 0x00}, //06/luma offset + {0x86, 0xfb}, //skin cb + {0x87, 0x1d}, //skin cr + {0x88, 0x18}, //skin radius + {0x8d, 0x78}, //38/edge dec sa + {0x8e, 0x25}, //autogray + + ///////////////////////////////////////////////////// + ////////////////////// AEC ////////////////////// + ///////////////////////////////////////////////////// + {0xa4, 0x01}, + {0x9e, 0x01}, // 0x02 + {0x9f, 0x90}, // 0x1c + {0xa0, 0x10}, + {0x90, 0x4a}, //0a //48 + {0x92, 0x40}, //40/target Y + {0xa2, 0x40}, //max_post_gain + {0xa3, 0x80}, //max_pre_gain + + ///////////////////////////////////////////////////// + ////////////////////// AWB ////////////////////// + ///////////////////////////////////////////////////// + {0xb0, 0xf8}, //f5/RGB high low + {0xb1, 0x24}, //18/Y to C + {0xb3, 0x20}, //0d/C max + {0xb4, 0x2d}, //22/C inter + {0xb5, 0x1b}, //22/C inter + {0xb6, 0x2e}, //C inter2 + {0xb7, 0x18}, //40/C inter3 + {0xb8, 0x13}, //20/number limit + {0xb9, 0x33}, + {0xba, 0x21}, + {0xbb, 0x61}, //42/speed & margin + {0xbf, 0x68}, //78/b limit + {0x4c, 0x08}, + {0x4d, 0x06}, + {0x4e, 0x7b}, + {0x4f, 0xa0}, + + {0xfe, 0x02}, + + {0x01, 0x03}, + {0x02, 0x02}, //LSB & Falling edge sample + //{0x03, 0x20}, //1-wire + {0x04, 0x20}, //[4] master_outformat + {0x05, 0x00}, + {0x09, 0x00}, //Reverse the high<->low byte. + {0x0a, 0x00}, //Data ID, 0x00-YUV422, 0x01-RGB565 + {0x13, 0xf0}, + + + ///////////////////////////////////////////////////// + ///////////////////// 2-wire //////////////////// + ///////////////////////////////////////////////////// + // {0x03, 0x25}, //20 + // {0xfd, 0x04}, + // {0xf1, 0x07}, //00 + + + ///////////////////////////////////////////////////// + ///////////////////// 1-wire //////////////////// + ///////////////////////////////////////////////////// + {0x03, 0x20}, //20 + {0xfd, 0x00}, //00 + {0xf1, 0x05}, + + {0xfe, 0x00}, + +}; + +uint16_t gc6123GetRegCnt(char* regName) +{ + if (strcmp(regName, "gc6123_2sdr") == 0) + { + return (sizeof(gc6123_2sdrRegInfo) / sizeof(gc6123_2sdrRegInfo[0])); + } + else if (strcmp(regName, "gc6123_1sdr") == 0) + { + return (sizeof(gc6123_1sdrRegInfo) / sizeof(gc6123_1sdrRegInfo[0])); + } + + return 0; +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/gc6153/gc6153.c b/PLAT/driver/board/ec618_0h00/src/camera/gc6153/gc6153.c new file mode 100644 index 0000000..5bae86f --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/gc6153/gc6153.c @@ -0,0 +1,171 @@ +#include "cameraDrv.h" + +camI2cCfg_t gc6153_1sdrRegInfo[] = +{ + // SYS + {0xfe, 0xa0}, + {0xfe, 0xa0}, + {0xfe, 0xa0}, + {0xfa, 0x11}, + {0xfc, 0x00}, + {0xf6, 0x00}, + {0xfc, 0x12}, + + // ANALOG & CISCTL + {0xfe, 0x00}, + {0x01, 0x40}, + {0x02, 0x12}, + {0x0d, 0x40}, + {0x14, 0x7c}, // 0x7e + {0x16, 0x05}, // 0x05 + {0x17, 0x18}, // 0x18 + {0x1c, 0x31}, + {0x1d, 0xbb}, + {0x1f, 0x3f}, + {0x73, 0x20}, + {0x74, 0x71}, + {0x77, 0x22}, + {0x7a, 0x08}, + {0x11, 0x18}, + {0x13, 0x48}, + {0x12, 0xc8}, + {0x70, 0xc8}, + {0x7b, 0x18}, + {0x7d, 0x30}, + {0x7e, 0x02}, + + {0xfe, 0x10}, + {0xfe, 0x00}, + {0xfe, 0x00}, + {0xfe, 0x00}, + {0xfe, 0x00}, + {0xfe, 0x00}, + {0xfe, 0x10}, + {0xfe, 0x00}, + + {0x49, 0x61}, + {0x4a, 0x40}, + {0x4b, 0x58}, + + /*ISP*/ + {0xfe, 0x00}, + {0x39, 0x02}, + {0x3a, 0x80}, + {0x20, 0x7e}, + {0x26, 0xa7}, + + /*BLK*/ + {0x33, 0x10}, + {0x37, 0x06}, + {0x2a, 0x21}, + + /*GAIN*/ + {0x3f, 0x16}, + + /*DNDD*/ + {0x52, 0xa6}, + {0x53, 0x81}, + {0x54, 0x43}, + {0x56, 0x78}, + {0x57, 0xaa}, + {0x58, 0xff}, + + /*ASDE*/ + {0x5b, 0x60}, + {0x5c, 0x50}, + {0xab, 0x2a}, + {0xac, 0xb5}, + + /*INTPEE*/ + {0x5e, 0x06}, + {0x5f, 0x06}, + {0x60, 0x44}, + {0x61, 0xff}, + {0x62, 0x69}, + {0x63, 0x13}, + + /*CC*/ + {0x65, 0x13}, + {0x66, 0x26}, + {0x67, 0x07}, + {0x68, 0xf5}, + {0x69, 0xea}, + {0x6a, 0x21}, + {0x6b, 0x21}, + {0x6c, 0xe4}, + {0x6d, 0xfb}, + + /*YCP*/ + {0x81, 0x3b}, // 0 + {0x82, 0x3b}, // 0 : uyvy ºÚ°× + {0x83, 0x4b}, + {0x84, 0x90}, + {0x86, 0xf0}, + {0x87, 0x1d}, + {0x88, 0x16}, + {0x8d, 0x74}, + {0x8e, 0x25}, + + /*AEC*/ + {0x90, 0x36}, + {0x92, 0x43}, + {0x9d, 0x32}, + {0x9e, 0x81}, + {0x9f, 0xf4}, + {0xa0, 0xa0}, + {0xa1, 0x04}, + {0xa3, 0x2d}, + {0xa4, 0x01}, + + /*AWB*/ + {0xb0, 0xc2}, + {0xb1, 0x1e}, + {0xb2, 0x10}, + {0xb3, 0x20}, + {0xb4, 0x2d}, + {0xb5, 0x1b}, + {0xb6, 0x2e}, + {0xb8, 0x13}, + {0xba, 0x60}, + {0xbb, 0x62}, + {0xbd, 0x78}, + {0xbe, 0x55}, + {0xbf, 0xa0}, + {0xc4, 0xe7}, + {0xc5, 0x15}, + {0xc6, 0x16}, + {0xc7, 0xeb}, + {0xc8, 0xe4}, + {0xc9, 0x16}, + {0xca, 0x16}, + {0xcb, 0xe9}, + {0x22, 0xf8}, + + /*SPI*/ + {0xfe, 0x02}, + {0x01, 0x01}, + {0x02, 0x02}, + {0x03, 0x20}, + {0x04, 0x20}, + {0x0a, 0x00}, + {0x13, 0x10}, + {0x24, 0x00}, + {0x28, 0x03}, + {0xfe, 0x00}, + + /*OUTPUT*/ + {0xf2, 0x03}, + {0xfe, 0x00}, +}; + +uint16_t gc6153GetRegCnt(char* regName) +{ + if (strcmp(regName, "gc6153_1sdr") == 0) + { + return (sizeof(gc6153_1sdrRegInfo) / sizeof(gc6153_1sdrRegInfo[0])); + } + + return 0; +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/i2cGpio.c b/PLAT/driver/board/ec618_0h00/src/camera/i2cGpio.c new file mode 100644 index 0000000..2694b7f --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/i2cGpio.c @@ -0,0 +1,149 @@ +#include "i2cGpio.h" + +// We only act as I2C master + +typedef enum +{ + INPUT, + OUTPUT, +}pinDirection_e; + +static void setSdaDirection(pinDirection_e direction) +{ + GpioPinConfig_t config; + + if (direction == INPUT) + { + config.pinDirection = GPIO_DIRECTION_INPUT; + config.misc.interruptConfig = GPIO_INTERRUPT_DISABLED; + GPIO_pinConfig(SDA_GPIO_INSTANCE, SDA_GPIO_PIN, &config); + } + else + { + config.pinDirection = GPIO_DIRECTION_OUTPUT; + //config.initOutput = 0; + GPIO_pinConfig(SDA_GPIO_INSTANCE, SDA_GPIO_PIN, &config); + } +} + +void i2cStart() +{ + I2C_SDA_1; + I2C_SCL_1; + delay_us(20); + I2C_SDA_0; + delay_us(19); + I2C_SCL_0; +} + +void i2cStop() +{ + setSdaDirection(OUTPUT); + + I2C_SDA_0; + I2C_SCL_1; + delay_us(18); + + I2C_SDA_1; + delay_us(18); +} + +static uint32_t i2cSdaRead() +{ + return (((((GPIO_TypeDef *) (MP_GPIO_BASE_ADDR + 0x1000*SDA_GPIO_INSTANCE))->DATA) >> SDA_GPIO_PIN) & 0x01); +} + +void i2cWritebyte(uint8_t byte) +{ + setSdaDirection(OUTPUT); + + for (uint8_t i=0; i<8; i++) + { + I2C_SCL_0; + delay_us(18); + + // Send data every bit + if (byte&0x80) + { + I2C_SDA_1; + } + else + { + I2C_SDA_0; + } + + byte <<= 1; + + I2C_SCL_1; + delay_us(18); + } + + I2C_SCL_0; + delay_us(18); + I2C_SDA_1; + delay_us(18); +} + +void i2cAck() +{ + uint8_t i = 0; + + setSdaDirection(INPUT); + I2C_SCL_1; + delay_us(18); + + while ((i2cSdaRead()==1) && (i<255)) + i++; + + I2C_SCL_0; + delay_us(18); + + setSdaDirection(OUTPUT); +} + +uint8_t i2cReadByte() +{ + uint8_t i, receveData = 0; + + setSdaDirection(INPUT); + delay_us(18); + + for (i = 0; i < 8; i++) + { + I2C_SCL_1; + delay_us(18); + receveData |= (i2cSdaRead() << (7-i)); + I2C_SCL_0; + delay_us(18); + } + + setSdaDirection(OUTPUT); + + return receveData; +} + + +void i2cGpioInit() +{ + PadConfig_t config; + + PAD_getDefaultConfig(&config); + + // scl pin + config.mux = SCL_PAD_ALT_FUNC; + PAD_setPinConfig(SCL_GPIO_ADDR, &config); + + GpioPinConfig_t gpioCfg; + gpioCfg.pinDirection = GPIO_DIRECTION_OUTPUT; + gpioCfg.misc.initOutput= 1; + GPIO_pinConfig(SCL_GPIO_INSTANCE, SCL_GPIO_PIN, &gpioCfg); + + // sda pin + config.mux = SDA_PAD_ALT_FUNC; + PAD_setPinConfig(SDA_GPIO_ADDR, &config); + + gpioCfg.pinDirection = GPIO_DIRECTION_OUTPUT; + gpioCfg.misc.initOutput= 1; + GPIO_pinConfig(SDA_GPIO_INSTANCE, SDA_GPIO_PIN, &gpioCfg); +} + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/sp0821/sp0821.c b/PLAT/driver/board/ec618_0h00/src/camera/sp0821/sp0821.c new file mode 100644 index 0000000..829455e --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/sp0821/sp0821.c @@ -0,0 +1,349 @@ +#include "cameraDrv.h" + +camI2cCfg_t sp0821_2sdrRegInfo[] = +{ + {0x30,0x01}, + {0x32,0x00}, + {0x03,0x00}, + {0x04,0x96}, + {0x24,0x13}, + {0x9b,0x32}, + {0xd7,0x00}, + {0xc5,0xc7}, + {0xc6,0xe2}, + {0xe7,0x03}, + {0x32,0x00}, + {0x32,0x01}, + {0x32,0x00}, + {0xbf,0x0f}, + {0xba,0x5a}, + {0xbb,0x69}, + {0xe7,0x00}, + {0x32,0x07}, + {0x31,0x03}, + {0x19,0x04}, + {0x2c,0x0f}, + {0x2e,0x3c}, + {0x30,0x01}, + {0x28,0x2e}, + {0x29,0x1f}, + {0x0f,0x30}, + {0x14,0xb0}, + {0x38,0x50}, + {0x39,0x52}, + {0x3a,0x60}, + {0x3b,0x10}, + {0x3c,0xe0}, + {0x85,0x01}, + {0xe0,0x02}, + {0xe5,0x60}, + {0xf5,0x02}, + {0xf1,0x03}, + {0xf3,0x40}, + {0x41,0x00}, + {0x05,0x00}, + {0x06,0x00}, + {0x07,0x00}, + {0x08,0x00}, + {0x09,0x00}, + {0x0a,0x34}, + {0x0D,0x01}, + {0xc8,0x10}, + {0x29,0x1e}, + {0xa2,0x26}, + {0xa3,0x02}, + {0xa4,0x32}, + {0xa5,0x00}, + {0xa8,0x32}, + {0xa9,0x00}, + {0xaa,0x01}, + {0xab,0x00}, + {0x4c,0x80}, + {0x4d,0x80}, + {0xa6,0xf0}, + {0xa7,0x20}, + {0xac,0xf0}, + {0xad,0x20}, + {0x8a,0x3e}, + {0x8b,0x30}, + {0x8c,0x2a}, + {0x8d,0x26}, + {0x8e,0x26}, + {0x8f,0x24}, + {0x90,0x24}, + {0x91,0x22}, + {0x92,0x22}, + {0x93,0x22}, + {0x94,0x20}, + {0x95,0x20}, + {0x96,0x20}, + {0x17,0x88}, + {0x18,0x80}, + {0x4e,0x78}, + {0x4f,0x78}, + {0x58,0x8a}, + {0x59,0xa8}, + {0x5a,0x80}, + {0xca,0x00}, + {0x86,0x08}, + {0x87,0x0f}, + {0x88,0x30}, + {0x89,0x45}, + {0x9e,0x94}, + {0x9f,0x88}, + {0x97,0x84}, + {0x98,0x88}, + {0x99,0x74}, + {0x9a,0x84}, + {0xa0,0x7c}, + {0xa1,0x78}, + {0x9d,0x09}, + {0xB1,0x04}, + {0xb3,0x00}, + {0x47,0x40}, + {0xb8,0x04}, + {0xb9,0x28}, + {0x3f,0x18}, + {0xc1,0xff}, + {0xc2,0x40}, + {0xc3,0xff}, + {0xc4,0x40}, + {0xc5,0xc7}, + {0xc6,0xe2}, + {0xc7,0xef}, + {0xc8,0x10}, + {0x50,0x2a}, + {0x51,0x2a}, + {0x52,0x2f}, + {0x53,0xcf}, + {0x54,0xd0}, + {0x5c,0x1e}, + {0x5d,0x21}, + {0x5e,0x1a}, + {0x5f,0xe9}, + {0x60,0x98}, + {0xcb,0x3f}, + {0xcc,0x3f}, + {0xcd,0x3f}, + {0xce,0x85}, + {0xcf,0xff}, + {0x79,0x5a}, + {0x7a,0xDC}, + {0x7b,0x0A}, + {0x7c,0xFD}, + {0x7d,0x46}, + {0x7e,0xFD}, + {0x7f,0xFD}, + {0x80,0xEF}, + {0x81,0x54}, + {0x1b,0x0a}, + {0x1c,0x0f}, + {0x1d,0x15}, + {0x1e,0x15}, + {0x1f,0x15}, + {0x20,0x1f}, + {0x21,0x2a}, + {0x22,0x2a}, + {0x56,0x49}, + {0x1a,0x14}, + {0x34,0x1f}, + {0x82,0x10}, + {0x83,0x00}, + {0x84,0xff}, + {0xd7,0x50}, + {0xd8,0x1a}, + {0xd9,0x20}, + {0xc9,0x1f}, + {0xbf,0x33}, + {0xba,0x37}, + {0xbb,0x38}, + + {0x19,0x04}, + {0x34,0x1f}, + {0x30,0x01}, + {0x2e,0x2c},//0x29 + {0x2c,0x0f}, + +}; + +camI2cCfg_t sp0821_1sdrRegInfo[] = +{ + {0x30,0x01}, + {0x32,0x00}, + {0x03,0x00}, + {0x04,0x96}, + {0x24,0x13}, + {0x9b,0x32}, + {0xd7,0x00}, + {0xc5,0xc7}, + {0xc6,0xe2}, + {0xe7,0x03}, + {0x32,0x00}, + {0x32,0x01}, + {0x32,0x00}, + {0xbf,0x0f}, + {0xba,0x5a}, + {0xbb,0x69}, + {0xe7,0x00}, + {0x32,0x07}, + {0x31,0x03}, + {0x19,0x04}, + {0x2c,0x0f}, + {0x2e,0x3c}, + {0x30,0x01}, + {0x28,0x2e}, + {0x29,0x1f}, + {0x0f,0x30}, + {0x14,0xb0}, + {0x38,0x50}, + {0x39,0x52}, + {0x3a,0x60}, + {0x3b,0x10}, + {0x3c,0xe0}, + {0x85,0x01}, + {0xe0,0x02}, + {0xe5,0x60}, + {0xf5,0x02}, + {0xf1,0x03}, + {0xf3,0x40}, + {0x41,0x00}, + {0x05,0x00}, + {0x06,0x00}, + {0x07,0x00}, + {0x08,0x00}, + {0x09,0x00}, + {0x0a,0x34}, + {0x0D,0x01}, + {0xc8,0x10}, + {0x29,0x1e}, + {0xa2,0x26}, + {0xa3,0x02}, + {0xa4,0x32}, + {0xa5,0x00}, + {0xa8,0x32}, + {0xa9,0x00}, + {0xaa,0x01}, + {0xab,0x00}, + {0x4c,0x80}, + {0x4d,0x80}, + {0xa6,0xf0}, + {0xa7,0x20}, + {0xac,0xf0}, + {0xad,0x20}, + {0x8a,0x3e}, + {0x8b,0x30}, + {0x8c,0x2a}, + {0x8d,0x26}, + {0x8e,0x26}, + {0x8f,0x24}, + {0x90,0x24}, + {0x91,0x22}, + {0x92,0x22}, + {0x93,0x22}, + {0x94,0x20}, + {0x95,0x20}, + {0x96,0x20}, + {0x17,0x88}, + {0x18,0x80}, + {0x4e,0x78}, + {0x4f,0x78}, + {0x58,0x8a}, + {0x59,0xa8}, + {0x5a,0x80}, + {0xca,0x00}, + {0x86,0x08}, + {0x87,0x0f}, + {0x88,0x30}, + {0x89,0x45}, + {0x9e,0x94}, + {0x9f,0x88}, + {0x97,0x84}, + {0x98,0x88}, + {0x99,0x74}, + {0x9a,0x84}, + {0xa0,0x7c}, + {0xa1,0x78}, + {0x9d,0x09}, + {0xB1,0x04}, + {0xb3,0x00}, + {0x47,0x40}, + {0xb8,0x04}, + {0xb9,0x28}, + {0x3f,0x18}, + {0xc1,0xff}, + {0xc2,0x40}, + {0xc3,0xff}, + {0xc4,0x40}, + {0xc5,0xc7}, + {0xc6,0xe2}, + {0xc7,0xef}, + {0xc8,0x10}, + {0x50,0x2a}, + {0x51,0x2a}, + {0x52,0x2f}, + {0x53,0xcf}, + {0x54,0xd0}, + {0x5c,0x1e}, + {0x5d,0x21}, + {0x5e,0x1a}, + {0x5f,0xe9}, + {0x60,0x98}, + {0xcb,0x3f}, + {0xcc,0x3f}, + {0xcd,0x3f}, + {0xce,0x85}, + {0xcf,0xff}, + {0x79,0x5a}, + {0x7a,0xDC}, + {0x7b,0x0A}, + {0x7c,0xFD}, + {0x7d,0x46}, + {0x7e,0xFD}, + {0x7f,0xFD}, + {0x80,0xEF}, + {0x81,0x54}, + {0x1b,0x0a}, + {0x1c,0x0f}, + {0x1d,0x15}, + {0x1e,0x15}, + {0x1f,0x15}, + {0x20,0x1f}, + {0x21,0x2a}, + {0x22,0x2a}, + {0x56,0x49}, + {0x1a,0x14}, + {0x34,0x1f}, + {0x82,0x10}, + {0x83,0x00}, + {0x84,0xff}, + {0xd7,0x50}, + {0xd8,0x1a}, + {0xd9,0x20}, + {0xc9,0x1f}, + {0xbf,0x33}, + {0xba,0x37}, + {0xbb,0x38}, + + {0x19,0x04}, + {0x34,0x1f}, + {0x30,0x01}, + {0x2e,0x2c},//0x29 + {0x2c,0x0f}, + +}; + +uint16_t sp0821GetRegCnt(char* regName) +{ + if (strcmp(regName, "sp0821_2sdr") == 0) + { + return (sizeof(sp0821_2sdrRegInfo) / sizeof(sp0821_2sdrRegInfo[0])); + } + else if (strcmp(regName, "sp0821_1sdr") == 0) + { + return (sizeof(sp0821_1sdrRegInfo) / sizeof(sp0821_1sdrRegInfo[0])); + } + + return 0; +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/camera/sp0A39/sp0A39.c b/PLAT/driver/board/ec618_0h00/src/camera/sp0A39/sp0A39.c new file mode 100644 index 0000000..bbaf15d --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/camera/sp0A39/sp0A39.c @@ -0,0 +1,740 @@ +#include "cameraDrv.h" + +camI2cCfg_t sp0A39_2sdrRegInfo[] = +{ + {0xfd,0x00}, + {0x1d,0x25}, + {0x31,0x04}, + {0x32,0x01}, + {0x30,0x01}, + {0xfd,0x01}, + {0x5d,0x01}, + {0x34,0xe3}, + {0x35,0x10}, + {0xfd,0x00}, + {0xf0,0xff}, + {0xf1,0xff}, + {0xf2,0xff}, + {0xf3,0xff}, + {0xfc,0x50}, + {0xfd,0x00}, + {0x03,0x00}, + {0x04,0xf0}, + {0x24,0x10}, + {0xef,0x40}, + {0x06,0x00}, + {0x09,0x00}, + {0x0a,0x46}, + {0x10,0x07}, + {0x11,0x04}, + {0x16,0x01}, + {0x19,0x22}, + {0x1e,0x58}, + {0x29,0x48}, + {0x13,0x37}, + {0x14,0x01}, + {0x25,0x01}, + {0x2a,0x06}, + {0x27,0x01}, + {0x54,0x00}, + {0x55,0x10}, + {0x58,0x38}, + {0x5d,0x12}, + {0x63,0x00}, + {0x64,0x00}, + {0x66,0x28}, + {0x68,0x2a}, + {0x72,0x3a}, + {0x73,0x0a}, + {0x75,0x48}, + {0x76,0x0a}, + {0x1f,0x77}, + {0x20,0x07}, + {0xfb,0x16}, + {0xfd,0x01}, + {0xf2,0x69}, + {0xf7,0x28}, + {0x02,0x10}, + {0x03,0x01}, + {0x06,0x28}, + {0x08,0x01}, + {0xfd,0x02}, + {0xb8,0x50}, + {0xb9,0xff}, + {0xba,0x40}, + {0xbb,0x45}, + {0xbc,0xc0}, + {0xbd,0x50}, + {0xbe,0x80}, + {0xbf,0x02}, + {0xd0,0x80}, + {0xd1,0x02}, + {0xfd,0x01}, + {0xc0,0x1f}, + {0xc1,0x18}, + {0xc2,0x15}, + {0xc3,0x13}, + {0xc4,0x13}, + {0xc5,0x12}, + {0xc6,0x12}, + {0xc7,0x11}, + {0xc8,0x11}, + {0xc9,0x11}, + {0xca,0x10}, + {0xf3,0x10}, + {0xf4,0x10}, + {0xfd,0x01}, + {0x04,0xff}, + {0x05,0x10}, + {0x0a,0x30}, + {0x0b,0x10}, + {0xfd,0x01}, + {0xcb,0x38}, + {0xcc,0x35}, + {0xcd,0x03}, + {0xce,0x05}, + {0xfd,0x00}, + {0xfb,0x16}, + {0x35,0xaa}, + {0xfd,0x01}, + {0x1e,0x00}, + {0x20,0x00}, + {0x84,0x25}, + {0x85,0x25}, + {0x86,0x1f}, + {0x87,0x23}, + {0x88,0x1c}, + {0x89,0x20}, + {0x8a,0x1a}, + {0x8b,0x15}, + {0x8c,0x15}, + {0x8d,0x1a}, + {0x8e,0x0a}, + {0x8f,0x13}, + {0x90,0x13}, + {0x91,0x00}, + {0x92,0x0a}, + {0x93,0x08}, + {0x94,0x12}, + {0x95,0x00}, + {0x96,0x0a}, + {0x97,0x08}, + {0x98,0x15}, + {0x99,0x00}, + {0x9a,0x0a}, + {0x9b,0x05}, + {0xe8,0x20}, + {0xe9,0x0f}, + {0xea,0x00}, + {0xfd,0x01}, + {0xa4,0x00}, + {0x0e,0x80}, + {0x18,0x80}, + {0x0f,0x20}, + {0x10,0x90}, + {0x11,0x80}, + {0x12,0x80}, + {0x13,0xa0}, + {0x14,0x80}, + {0x15,0x90}, + {0x16,0x85}, + {0x17,0x85}, + {0x6e,0x00}, + {0x6f,0x03}, + {0x70,0x07}, + {0x71,0x0d}, + {0x72,0x17}, + {0x73,0x29}, + {0x74,0x3d}, + {0x75,0x4f}, + {0x76,0x5f}, + {0x77,0x79}, + {0x78,0x8c}, + {0x79,0x9d}, + {0x7a,0xa9}, + {0x7b,0xb3}, + {0x7c,0xbe}, + {0x7d,0xc7}, + {0x7e,0xd0}, + {0x7f,0xd6}, + {0x80,0xde}, + {0x81,0xe4}, + {0x82,0xe9}, + {0x83,0xee}, + {0xfd,0x02}, + {0x09,0x06}, + {0x0d,0x1a}, + {0x1c,0x09}, + {0x1d,0x03}, + {0x1e,0x10}, + {0x1f,0x06}, + {0xfd,0x01}, + {0x32,0x00}, + {0xfd,0x02}, + {0x26,0xcb}, + {0x27,0xc2}, + {0x10,0x00}, + {0x11,0x00}, + {0x18,0x17}, + {0x19,0x36}, + {0x2a,0x01}, + {0x2b,0x10}, + {0x28,0xf8}, + {0x29,0x08}, + {0x66,0x5F}, + {0x67,0x7f}, + {0x68,0xE0}, + {0x69,0x10}, + {0x69,0x10}, + {0x6a,0xa6}, + {0x7c,0x4A}, + {0x7d,0x80}, + {0x7e,0x00}, + {0x7f,0x30}, + {0x80,0xaa}, + {0x70,0x32}, + {0x71,0x60}, + {0x72,0x30}, + {0x73,0x5a}, + {0x74,0xaa}, + {0x6b,0xff}, + {0x6c,0x50}, + {0x6d,0x40}, + {0x6e,0x60}, + {0x6f,0x6a}, + {0x61,0xff}, + {0x62,0x27}, + {0x63,0x51}, + {0x64,0x7f}, + {0x65,0x6a}, + {0x75,0x80}, + {0x76,0x09}, + {0x77,0x02}, + {0x0e,0x12}, + {0x3b,0x09}, + {0x48,0xea}, + {0x49,0xfc}, + {0x4a,0x05}, + {0x02,0x00}, + {0x03,0x88}, + {0xf5,0xfe}, + {0x22,0xfe}, + {0x20,0xfe}, + {0xf7,0xfe}, + {0xfd,0x02}, + {0xde,0x0f}, + {0xcf,0x0a}, + {0xd7,0x0a}, + {0xd8,0x12}, + {0xd9,0x14}, + {0xda,0x1a}, + {0xdc,0x07}, + {0xe8,0x60}, + {0xe9,0x40}, + {0xea,0x40}, + {0xeb,0x30}, + {0xec,0x60}, + {0xed,0x50}, + {0xee,0x40}, + {0xef,0x30}, + {0xd3,0x30}, + {0xd4,0xc0}, + {0xd5,0x50}, + {0xd6,0x0b}, + {0xf0,0x7f}, + {0xfd,0x01}, + {0xb1,0xf0}, + {0xfd,0x02}, + {0xdc,0x07}, + {0x05,0x08}, + {0xfd,0x01}, + {0x26,0x33}, + {0x27,0x99}, + {0x62,0xf0}, + {0x63,0x80}, + {0x64,0x80}, + {0x65,0x20}, + {0xfd,0x02}, + {0xdd,0xff}, + {0xfd,0x01}, + {0xa8,0x00}, + {0xa9,0x09}, + {0xaa,0x09}, + {0xab,0x0c}, + {0xd3,0x00}, + {0xd4,0x09}, + {0xd5,0x09}, + {0xd6,0x0c}, + {0xcf,0xff}, + {0xd0,0xf0}, + {0xd1,0x80}, + {0xd2,0x80}, + {0xdf,0xff}, + {0xe0,0xf0}, + {0xe1,0xd0}, + {0xe2,0x80}, + {0xe3,0xff}, + {0xe4,0xf0}, + {0xe5,0xd0}, + {0xe6,0x80}, + {0xfd,0x02}, + {0x15,0xe0}, + {0x16,0x95}, + {0xa0,0x9b}, + {0xa1,0xe4}, + {0xa2,0x01}, + {0xa3,0xf2}, + {0xa4,0x8f}, + {0xa5,0xff}, + {0xa6,0x01}, + {0xa7,0xdb}, + {0xa8,0xa4}, + {0xac,0x80}, + {0xad,0x21}, + {0xae,0xdf}, + {0xaf,0xf2}, + {0xb0,0xa0}, + {0xb1,0xee}, + {0xb2,0xea}, + {0xb3,0xd9}, + {0xb4,0xbd}, + {0xfd,0x01}, + {0xb3,0xb0}, + {0xb4,0x90}, + {0xb5,0x70}, + {0xb6,0x55}, + {0xb7,0xb0}, + {0xb8,0x90}, + {0xb9,0x70}, + {0xba,0x55}, + {0xfd,0x01}, + {0xbf,0xff}, + {0x00,0x00}, + {0xfd,0x01}, + {0xa4,0x00}, + {0xa5,0x1f}, + {0xa6,0x50}, + {0xa7,0x65}, + {0xfd,0x02}, + {0x30,0x38}, + {0x31,0x40}, + {0x32,0x40}, + {0x33,0xd0}, + {0x34,0x10}, + {0x35,0x60}, + {0x36,0x28}, + {0x37,0x07}, + {0x38,0x08}, + {0xe6,0x8F}, + {0xfd,0x01}, + {0x1b,0x15}, + {0x1c,0x1A}, + {0x1d,0x0c}, + {0xfd,0x01}, + {0x32,0x15}, + {0x33,0xef}, + {0x36,0x10}, + {0xf6,0xb0}, + {0xf5,0x10}, + {0xd7,0x3a}, + {0xd8,0x10}, + {0xd9,0x20}, + {0xda,0x10}, + {0xdb,0x7a}, + {0xdc,0x3a}, + {0xdd,0x30}, + {0xde,0x30}, + {0xe7,0x3a}, + {0x9c,0xaa}, + {0x9d,0xaa}, + {0x9e,0x55}, + {0x9f,0x55}, + {0xfd,0x00}, + {0x1c,0x00}, + {0xfd,0x00}, + + {0xfd,0x00}, + {0x30,0x0b}, + {0x1c,0xdc}, + {0x2c,0x1d}, // LSB + {0x2e,0xe1}, + + +}; + +camI2cCfg_t sp0A39_1sdrRegInfo[] = +{ + {0xfd,0x00}, + {0x1d,0x25}, + {0x31,0x04}, + {0x32,0x01}, + {0x30,0x01}, + {0xfd,0x01}, + {0x5d,0x01}, + {0x34,0xe3}, + {0x35,0x10}, + {0xfd,0x00}, + {0xf0,0xff}, + {0xf1,0xff}, + {0xf2,0xff}, + {0xf3,0xff}, + {0xfc,0x50}, + {0xfd,0x00}, + {0x03,0x03}, + {0x04,0x6c}, + {0x24,0x10}, + {0xef,0x40}, + {0x06,0x00}, + {0x09,0x00}, + {0x0a,0x80}, + {0x10,0x07}, + {0x11,0x04}, + {0x16,0x01}, + {0x19,0x22}, + {0x1e,0x58}, + {0x29,0x48}, + {0x13,0x37}, + {0x14,0x01}, + {0x25,0x01}, + {0x2a,0x06}, + {0x27,0x01}, + {0x54,0x00}, + {0x55,0x10}, + {0x58,0x38}, + {0x5d,0x12}, + {0x63,0x00}, + {0x64,0x00}, + {0x66,0x28}, + {0x68,0x2a}, + {0x72,0x3a}, + {0x73,0x0a}, + {0x75,0x48}, + {0x76,0x0a}, + {0x1f,0x77}, + {0x20,0x07}, + {0xfb,0x16}, + {0xfd,0x01}, + {0xf2,0x69}, + {0xf7,0x97}, + {0x02,0x08}, + {0x03,0x01}, + {0x06,0x8a}, + {0x08,0x01}, + {0xfd,0x02}, + {0xb8,0x50}, + {0xb9,0xff}, + {0xba,0x40}, + {0xbb,0x45}, + {0xbc,0xc0}, + {0xbd,0x50}, + {0xbe,0xb8}, + {0xbf,0x04}, + {0xd0,0xb8}, + {0xd1,0x04}, + {0xfd,0x01}, + {0xc0,0x1f}, + {0xc1,0x18}, + {0xc2,0x15}, + {0xc3,0x13}, + {0xc4,0x13}, + {0xc5,0x12}, + {0xc6,0x12}, + {0xc7,0x11}, + {0xc8,0x11}, + {0xc9,0x11}, + {0xca,0x10}, + {0xf3,0x10}, + {0xf4,0x10}, + {0xfd,0x01}, + {0x04,0xff}, + {0x05,0x10}, + {0x0a,0x30}, + {0x0b,0x10}, + {0xfd,0x01}, + {0xcb,0x38}, + {0xcc,0x35}, + {0xcd,0x03}, + {0xce,0x05}, + {0xfd,0x00}, + {0xfb,0x16}, + {0x35,0xaa}, + {0xfd,0x01}, + {0x1e,0x00}, + {0x20,0x00}, + {0x84,0x25}, + {0x85,0x25}, + {0x86,0x1f}, + {0x87,0x23}, + {0x88,0x1c}, + {0x89,0x20}, + {0x8a,0x1a}, + {0x8b,0x15}, + {0x8c,0x15}, + {0x8d,0x1a}, + {0x8e,0x0a}, + {0x8f,0x13}, + {0x90,0x13}, + {0x91,0x00}, + {0x92,0x0a}, + {0x93,0x08}, + {0x94,0x12}, + {0x95,0x00}, + {0x96,0x0a}, + {0x97,0x08}, + {0x98,0x15}, + {0x99,0x00}, + {0x9a,0x0a}, + {0x9b,0x05}, + {0xe8,0x20}, + {0xe9,0x0f}, + {0xea,0x00}, + {0xfd,0x01}, + {0xa4,0x00}, + {0x0e,0x80}, + {0x18,0x80}, + {0x0f,0x20}, + {0x10,0x90}, + {0x11,0x80}, + {0x12,0x80}, + {0x13,0xa0}, + {0x14,0x80}, + {0x15,0x90}, + {0x16,0x85}, + {0x17,0x85}, + {0x6e,0x00}, + {0x6f,0x03}, + {0x70,0x07}, + {0x71,0x0d}, + {0x72,0x17}, + {0x73,0x29}, + {0x74,0x3d}, + {0x75,0x4f}, + {0x76,0x5f}, + {0x77,0x79}, + {0x78,0x8c}, + {0x79,0x9d}, + {0x7a,0xa9}, + {0x7b,0xb3}, + {0x7c,0xbe}, + {0x7d,0xc7}, + {0x7e,0xd0}, + {0x7f,0xd6}, + {0x80,0xde}, + {0x81,0xe4}, + {0x82,0xe9}, + {0x83,0xee}, + {0xfd,0x02}, + {0x09,0x06}, + {0x0d,0x1a}, + {0x1c,0x09}, + {0x1d,0x03}, + {0x1e,0x10}, + {0x1f,0x06}, + {0xfd,0x01}, + {0x32,0x00}, + {0xfd,0x02}, + {0x26,0xcb}, + {0x27,0xc2}, + {0x10,0x00}, + {0x11,0x00}, + {0x18,0x17}, + {0x19,0x36}, + {0x2a,0x01}, + {0x2b,0x10}, + {0x28,0xf8}, + {0x29,0x08}, + {0x66,0x5F}, + {0x67,0x7f}, + {0x68,0xE0}, + {0x69,0x10}, + {0x69,0x10}, + {0x6a,0xa6}, + {0x7c,0x4A}, + {0x7d,0x80}, + {0x7e,0x00}, + {0x7f,0x30}, + {0x80,0xaa}, + {0x70,0x32}, + {0x71,0x60}, + {0x72,0x30}, + {0x73,0x5a}, + {0x74,0xaa}, + {0x6b,0xff}, + {0x6c,0x50}, + {0x6d,0x40}, + {0x6e,0x60}, + {0x6f,0x6a}, + {0x61,0xff}, + {0x62,0x27}, + {0x63,0x51}, + {0x64,0x7f}, + {0x65,0x6a}, + {0x75,0x80}, + {0x76,0x09}, + {0x77,0x02}, + {0x0e,0x12}, + {0x3b,0x09}, + {0x48,0xea}, + {0x49,0xfc}, + {0x4a,0x05}, + {0x02,0x00}, + {0x03,0x88}, + {0xf5,0xfe}, + {0x22,0xfe}, + {0x20,0xfe}, + {0xf7,0xfe}, + {0xfd,0x02}, + {0xde,0x0f}, + {0xcf,0x0a}, + {0xd7,0x0a}, + {0xd8,0x12}, + {0xd9,0x14}, + {0xda,0x1a}, + {0xdc,0x07}, + {0xe8,0x60}, + {0xe9,0x40}, + {0xea,0x40}, + {0xeb,0x30}, + {0xec,0x60}, + {0xed,0x50}, + {0xee,0x40}, + {0xef,0x30}, + {0xd3,0x30}, + {0xd4,0xc0}, + {0xd5,0x50}, + {0xd6,0x0b}, + {0xf0,0x7f}, + {0xfd,0x01}, + {0xb1,0xf0}, + {0xfd,0x02}, + {0xdc,0x07}, + {0x05,0x08}, + {0xfd,0x01}, + {0x26,0x33}, + {0x27,0x99}, + {0x62,0xf0}, + {0x63,0x80}, + {0x64,0x80}, + {0x65,0x20}, + {0xfd,0x02}, + {0xdd,0xff}, + {0xfd,0x01}, + {0xa8,0x00}, + {0xa9,0x09}, + {0xaa,0x09}, + {0xab,0x0c}, + {0xd3,0x00}, + {0xd4,0x09}, + {0xd5,0x09}, + {0xd6,0x0c}, + {0xcf,0xff}, + {0xd0,0xf0}, + {0xd1,0x80}, + {0xd2,0x80}, + {0xdf,0xff}, + {0xe0,0xf0}, + {0xe1,0xd0}, + {0xe2,0x80}, + {0xe3,0xff}, + {0xe4,0xf0}, + {0xe5,0xd0}, + {0xe6,0x80}, + {0xfd,0x02}, + {0x15,0xe0}, + {0x16,0x95}, + {0xa0,0x9b}, + {0xa1,0xe4}, + {0xa2,0x01}, + {0xa3,0xf2}, + {0xa4,0x8f}, + {0xa5,0xff}, + {0xa6,0x01}, + {0xa7,0xdb}, + {0xa8,0xa4}, + {0xac,0x80}, + {0xad,0x21}, + {0xae,0xdf}, + {0xaf,0xf2}, + {0xb0,0xa0}, + {0xb1,0xee}, + {0xb2,0xea}, + {0xb3,0xd9}, + {0xb4,0xbd}, + {0xfd,0x01}, + {0xb3,0xb0}, + {0xb4,0x90}, + {0xb5,0x70}, + {0xb6,0x55}, + {0xb7,0xb0}, + {0xb8,0x90}, + {0xb9,0x70}, + {0xba,0x55}, + {0xfd,0x01}, + {0xbf,0xff}, + {0x00,0x00}, + {0xfd,0x01}, + {0xa4,0x00}, + {0xa5,0x1f}, + {0xa6,0x50}, + {0xa7,0x65}, + {0xfd,0x02}, + {0x30,0x38}, + {0x31,0x40}, + {0x32,0x40}, + {0x33,0xd0}, + {0x34,0x10}, + {0x35,0x60}, + {0x36,0x28}, + {0x37,0x07}, + {0x38,0x08}, + {0xe6,0x8F}, + {0xfd,0x01}, + {0x1b,0x15}, + {0x1c,0x1A}, + {0x1d,0x0c}, + {0xfd,0x01}, + {0x32,0x15}, + {0x33,0xef}, + {0x36,0x10}, + {0xf6,0xb0}, + {0xf5,0x10}, + {0xd7,0x3a}, + {0xd8,0x10}, + {0xd9,0x20}, + {0xda,0x10}, + {0xdb,0x7a}, + {0xdc,0x3a}, + {0xdd,0x30}, + {0xde,0x30}, + {0xe7,0x3a}, + {0x9c,0xaa}, + {0x9d,0xaa}, + {0x9e,0x55}, + {0x9f,0x55}, + {0xfd,0x00}, + {0x1c,0x00}, + {0xfd,0x00}, + + {0xfd,0x00}, + {0x30,0x0c}, + {0x1c,0xde}, + {0x2c,0x1d}, //LSB + //{0x2c,0x15}, //MSB + {0x2e,0xf0}, + +}; + +uint16_t sp0a39GetRegCnt(char* regName) +{ + if (strcmp(regName, "sp0a39_2sdr") == 0) + { + return (sizeof(sp0A39_2sdrRegInfo) / sizeof(sp0A39_2sdrRegInfo[0])); + } + else if (strcmp(regName, "sp0a39_1sdr") == 0) + { + return (sizeof(sp0A39_1sdrRegInfo) / sizeof(sp0A39_1sdrRegInfo[0])); + } + + return 0; +} + diff --git a/PLAT/driver/board/ec618_0h00/src/eeprom/eepRom.c b/PLAT/driver/board/ec618_0h00/src/eeprom/eepRom.c new file mode 100644 index 0000000..0863f76 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/eeprom/eepRom.c @@ -0,0 +1,315 @@ +/**************************************************************************** + * + * Copy right: 2020-, Copyrigths of AirM2M Ltd. + * File name: eepRom.c + * Description: EC618 eepRom ds2431 driver source file + * History: Rev1.0 2020-12-17 + * + ****************************************************************************/ +#include "ec618.h" +#include "bsp.h" +#include "eepRom.h" +#include "oneWire.h" +#include "string.h" +#include "stdio.h" + +extern void delay_us(uint32_t us); + +static uint16_t crc16Maxim(uint8_t *data, uint16_t len) +{ + uint8_t i; + uint16_t crc = 0; + while (len--) + { + crc ^= *data++; + for (i=0; i<8; ++i) + { + if (crc&1) + { + crc = (crc>>1) ^ 0xA001; + } + else + { + crc = crc>>1; + } + } + } + return ~crc; +} + + +int32_t writeScratchpad(uint8_t addr, uint8_t data[8]) +{ + uint8_t crcSrcData[11]; + uint16_t crcCalResult; + uint8_t crcReadData[2]; + + if ((data == NULL) || (addr > 0x8F)) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + if (owResetPd() != 0) + { + return EEPROMDRV_RESET_ERR; + } + + delay_us(140); // delay 200us + + owWriteByte(ROM_SKIP_CMD); + owWriteByte(SCRATCHPAD_WRITE_CMD); + owWriteByte(addr); + owWriteByte(0x00); + + crcSrcData[0] = SCRATCHPAD_WRITE_CMD; // before are right + crcSrcData[1] = addr; + crcSrcData[2] = 0x00; + for (int i=0; i<8; i++) + { + owWriteByte(data[i]); + crcSrcData[i+3] = data[i]; + } + + crcCalResult = crc16Maxim(crcSrcData, 11); // before are right + + owReadByte(crcReadData); + owReadByte(crcReadData+1); + + if (((crcReadData[1]<<8) | crcReadData[0]) != crcCalResult) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + return EEPROMDRV_OK; +} + +void readScratchpad(uint8_t dataBack[13]) +{ + if (owResetPd() != 0) + { + return; + } + + delay_us(140); // delay 200us + + owWriteByte(ROM_SKIP_CMD); + owWriteByte(SCRATCHPAD_READ_CMD); + + // first 3 bytes are: TA1, TA2, ES; Then 8 bytes data; Last are 2 bytes crc + for (int i=0; i<13; i++) + { + owReadByte(dataBack+i); + } +} + +int32_t copyScratchpad2Mem(uint16_t addr) +{ + uint8_t readData; + + if (owResetPd() != 0) + { + return EEPROMDRV_RESET_ERR; + } + + delay_us(140); // delay 200us + + owWriteByte(ROM_SKIP_CMD); + owWriteByte(SCRATCHPAD_COPY_CMD); + owWriteByte(addr); + owWriteByte(0x00); + owWriteByte(0x07); + + delay_us(140); // delay 200us + + owReadByte(&readData); + if (readData != 0xAA) + { + return EEPROMDRV_SCRATCHPADCOPY_ERR; + } + + return EEPROMDRV_OK; +} + +uint8_t dataBack[13]={0}; +int32_t dataCmp(uint8_t targetAddr, uint8_t* buffer, uint8_t len) +{ + // compare the data read from scratchpad + if (dataBack[0] != targetAddr) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + if (dataBack[1] != 0) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + if (dataBack[2] != 0x7) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + for (int j=0; j>=1; + } + + uint8_t dataRead; + for (i=0; i<8; i++) + { + owReadBit(&dataRead); + dataRead <<=1; + } +#endif + +#if 1 + int32_t result = owWriteByte(ROM_READ_CMD); + if (result < 0) + { + return EEPROMDRV_ROMREAD_ERR; + } + + for (int32_t i=0; i<8; i++) + { + owReadByte(romCode+i); + } +#endif + + return EEPROMDRV_OK; +} + +int32_t eePromReadMem(uint8_t targetAddr, uint8_t len, uint8_t* buffer) +{ + delay_us(3000); // wait unitl former write operations finish + + if (owResetPd() != 0) + { + return EEPROMDRV_RESET_ERR; + } + + delay_us(140); // delay 200us + + if (owWriteByte(ROM_SKIP_CMD) < 0) + { + return EEPROMDRV_ROMREAD_ERR; + } + + if (owWriteByte(MEM_READ_CMD) < 0) + { + return EEPROMDRV_ROMREAD_ERR; + } + + // write addr low byte + if (owWriteByte(targetAddr) < 0) + { + return EEPROMDRV_ROMREAD_ERR; + } + + // write addr high byte + if (owWriteByte(0) < 0) + { + return EEPROMDRV_ROMREAD_ERR; + } + + for (int i=0; i 0x88) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + while (len > 8) + { + for (i=0; i<8; i++) + { + tmp[i] = buffer[i+index]; + } + + len -= 8; + writeSctStats = writeScratchpad(targetAddr+index, tmp); + delay_us(3000); + readScratchpad(dataBack); + if (dataCmp(targetAddr+index, buffer+index, 8) != 0) + { + return EEPROMDRV_SCRATCHPADWRITE_ERR; + } + + copyScratchpad2Mem(targetAddr+index); + delay_us(3000); + memset(dataBack, 0, 13); + + index += 8; + } + + for (i=0; i>4); + *(p+i) = data; + } +} + +/** + \brief Clear low 7bits. + \param[in/out] p Src/output mem. + \param[in] num source data num. + \return +*/ +void clearLow7bits(uint8_t* p, int num) +{ + for (int i = 0; i < num; i++) + { + *(p+i) = *(p+i) & 0x80; + } +} + + +/** + \brief Convert yuv422 to rgb565, used in color screen. + \param[in] inbuf source memory. + \param[out] outbuf output memory. + \param[in] width source picture width. + \param[in] height source picture height. + \return +*/ +#define RANGE_LIMIT(x) (x > 255 ? 255 : (x < 0 ? 0 : x)) +void yuv422ToRgb565(const void* inbuf, void* outbuf, int width, int height) +{ + int rows, cols; + int y, u, v, r, g, b; + unsigned char *yuv_buf; + unsigned short *rgb_buf; + int y_pos,u_pos,v_pos; + + yuv_buf = (unsigned char *)inbuf; + rgb_buf = (unsigned short *)outbuf; + + y_pos = 0; + u_pos = 1; + v_pos = 3; + + for (rows = 0; rows < height; rows++) + { + for (cols = 0; cols < width; cols++) + { + y = yuv_buf[y_pos]; + u = yuv_buf[u_pos] - 128; + v = yuv_buf[v_pos] - 128; + + // R = Y + 1.402*(V-128) + // G = Y - 0.34414*(U-128) + // B = Y + 1.772*(U-128) + r = RANGE_LIMIT(y + v + ((v * 103) >> 8)); + g = RANGE_LIMIT(y - ((u * 88) >> 8) - ((v * 183) >> 8)); + b = RANGE_LIMIT(y + u + ((u * 198) >> 8)); + + *rgb_buf++ = (((r & 0xf8) << 8) | ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); + + y_pos += 2; + + if (cols & 0x01) + { + u_pos += 4; + v_pos += 4; + } + } + } +} + + + diff --git a/PLAT/driver/board/ec618_0h00/src/lcd/lcdDrv.c b/PLAT/driver/board/ec618_0h00/src/lcd/lcdDrv.c new file mode 100644 index 0000000..3c48366 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/lcd/lcdDrv.c @@ -0,0 +1,272 @@ +#include "lcdDrv.h" + + +extern void delay_us(uint32_t us); +int8_t lcdDmaTxCh; // dma tx channel +DmaDescriptor_t __ALIGNED(16) lcdDmaTxDesc[HEIGHT]; +//uint8_t dmaTxData[WIDTH*2]; + +static DmaTransferConfig_t lcdDmaTxCfg = +{ + NULL, + (void *)&(SPI->DR), + DMA_FLOW_CONTROL_TARGET, + DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_ONE_BYTE, + DMA_BURST_8_BYTES, + WIDTH * 2 +}; + + + +void mDelay(uint32_t mDelay) +{ + delay_us(mDelay * 1000); +} + +void lcdWriteData(uint8_t data) +{ + SPI_CS_LOW; + LCD_DS_HIGH; + SPI_SEND_DATA(data); + //SPI_WAIT_TX_DONE; + SPI_IS_BUSY; + SPI_CS_HIGH; +} + + + +void lcdWriteCmd(uint8_t cmd) +{ + SPI_CS_LOW; + LCD_DS_LOW; + SPI_SEND_DATA(cmd); + SPI_WAIT_TX_DONE; + SPI_CS_HIGH; +} + +uint8_t lcdReadData() +{ + SPI_WAIT_TX_DONE; + SPI_SEND_DATA(0xff); // Dummy data + SPI_WAIT_TX_DONE; + uint8_t data = SPI_READ_DATA; + SPI_IS_BUSY; + return data; +} + +void lcdDispWindows() +{ + lcdWriteCmd(0x2A); + lcdWriteData(0x00); + lcdWriteData(0x00); + lcdWriteData(0x00); + lcdWriteData(0xEF); + + lcdWriteCmd(0x2B); + lcdWriteData(0x00); + lcdWriteData(0x00); + lcdWriteData(0x01); + lcdWriteData(0x3f); + lcdWriteCmd(0x2C); +} + +void lcdWriteSetup(uint8_t * dataBuf, uint16_t dataCnt) +{ + lcdDispWindows(); + + // Configure tx DMA and start it + lcdDmaTxCfg.sourceAddress = (void *)dataBuf; + //lcdDmaTxCfg.totalLength = dataCnt; // every descriptor transfer this trunk of data + + SPI_CS_LOW; + LCD_DS_HIGH; + DMA_buildDescriptorChain(lcdDmaTxDesc, &lcdDmaTxCfg, dataCnt / LCD_TRANSFER_SIZE_ONCE, false); + SPI_ENABLE_TX_DMA; +} + +void lcdWriteCtrl(bool startOrStop) +{ + if (startOrStop) + { + DMA_loadChannelDescriptorAndRun(DMA_INSTANCE_MP, lcdDmaTxCh, lcdDmaTxDesc); + } + else + { + extern void DMA_stopChannelNoWait(DmaInstance_e instance, uint32_t channel); + DMA_stopChannelNoWait(DMA_INSTANCE_MP, lcdDmaTxCh); + SPI_CS_HIGH; + } +} + +void lcdDispColor(uint16_t color) +{ + //lcdFillColorBuf(color); + + for (int i = 0; i < HEIGHT; i++) + { + lcdWriteCtrl(true); + } +} + + + +void lcdReadId() +{ + uint8_t id1, id2, id3; + + LCD_RST_HIGH; + mDelay(150); // Delay 200ms + LCD_RST_LOW; + mDelay(300); // Delay 400ms + LCD_RST_HIGH; + mDelay(400); // Delay 500ms + + lcdWriteData(0x04); + (void)lcdReadData(); // Dummy + id1 = lcdReadData(); + id2 = lcdReadData(); + id3 = lcdReadData(); + printf("LCD ID: %02x, %02x, %02x \r\n", id1, id2, id3); +} + +static void lcdGpioInit() +{ + PadConfig_t config; + + PAD_getDefaultConfig(&config); + + // Cs pin + config.mux = SPI_CS_PAD_ALT_FUNC; + PAD_setPinConfig(SPI_CS_PAD_ADDR, &config); + + GpioPinConfig_t gpioCfg; + gpioCfg.pinDirection = GPIO_DIRECTION_OUTPUT; + GPIO_pinConfig(SPI_CS_GPIO_INSTANCE, SPI_CS_GPIO_PIN, &gpioCfg); + + // Rst pin + config.mux = LCD_RST_PAD_ALT_FUNC; + PAD_setPinConfig(LCD_RST_PAD_ADDR, &config); + + gpioCfg.pinDirection = GPIO_DIRECTION_OUTPUT; + //gpioCfg.misc.initOutput = 1; + GPIO_pinConfig(LCD_RST_GPIO_INSTANCE, LCD_RST_GPIO_PIN, &gpioCfg); + + // Ds pin + config.mux = LCD_DS_PAD_ALT_FUNC; + PAD_setPinConfig(LCD_DS_PAD_ADDR, &config); + + gpioCfg.pinDirection = GPIO_DIRECTION_OUTPUT; + GPIO_pinConfig(LCD_DS_GPIO_INSTANCE, LCD_DS_GPIO_PIN, &gpioCfg); + +#if (ST7571_ENABLE) + *(uint32_t*)0x4d020018 = 0x1; // Normal gpio: 2.8V + *(uint32_t*)0x4d020054 = 0x1b; // AON IO: 3.35V, 2.8V + *(uint32_t*)0x4d020150 = 0x7; // Enable AON gpio as wakeup pin + *(uint32_t*)0x4d020170 = 0x1; // Enable AON IO + + // Lcd en pin + config.mux = LCD_EN_PAD_ALT_FUNC; + PAD_setPinConfig(LCD_EN_PAD_ADDR, &config); + + gpioCfg.pinDirection = GPIO_DIRECTION_OUTPUT; + gpioCfg.misc.initOutput = 1; + GPIO_pinConfig(LCD_EN_GPIO_INSTANCE, LCD_EN_GPIO_PIN, &gpioCfg); +#endif +} + +static void lcdSpiInit() +{ + PadConfig_t config; + + PAD_getDefaultConfig(&config); + + config.mux = SPI_CLK_PAD_ALT_FUNC; + PAD_setPinConfig(SPI_CLK_PAD_ADDR, &config); + + config.mux = SPI_MOSI_PAD_ALT_FUNC; + PAD_setPinConfig(SPI_MOSI_PAD_ADDR, &config); + + config.mux = SPI_MISO_PAD_ALT_FUNC; + PAD_setPinConfig(SPI_MISO_PAD_ADDR, &config); + + // Enable spi clock + GPR_clockEnable(SPI_APB_CLOCK); + GPR_clockEnable(SPI_FUNC_CLOCK); + + // Disable spi first + SPI->CR1 = 0; + + // Pol = 0; PHA = 0; Data width = 8 + SPI->CR0 = 0x7; + + // lcd spi clock choose 26M by default to speed up the fps. + CLOCK_clockEnable(CLK_HF51M); // open 51M + CLOCK_setClockSrc(FCLK_SPI0, FCLK_SPI0_SEL_51M); // choose 51M + SPI->CPSR = 2 & SPI_CPSR_CPSDVSR_Msk; // 2 division, to 26M + SPI->CR0 = (SPI->CR0 & ~SPI_CR0_SCR_Msk) | 0; + + // Enable spi + SPI->CR1 = SPI_CR1_SSE_Msk; +} + + + +void lcdWriteData16(uint16_t data) +{ + lcdWriteData(data >> 8); + lcdWriteData(data); +} + +void lcdDispPic(uint8_t * pic) +{ +#if (ST7789V2_ENABLE) + int i, j; + + lcdDispWindows(); + for (i = 0; i < HEIGHT; i++) + { + for (j = 0; j < WIDTH; j++) + { + lcdWriteData16(pic[j*2 + HEIGHT*i*2]); + } + } +#elif (ST7571_ENABLE) + displayPic_60x80(pic); +#endif +} + +void lcdClearScreen() +{ +#if (ST7571_ENABLE) + st7571CleanScreen(); +#endif +} + +void lcdInit(pTxCb txCb) +{ + lcdSpiInit(); + lcdGpioInit(); + + lcdReadId(); +#if (ST7789V2_ENABLE) + st7789v2_init(); +#endif + +#if (ST7571_ENABLE) + st7571_init(); + lcdClearScreen(); +#else + + // Tx config + DMA_init(DMA_INSTANCE_MP); + lcdDmaTxCh = DMA_openChannel(DMA_INSTANCE_MP); + + DMA_setChannelRequestSource(DMA_INSTANCE_MP, lcdDmaTxCh, (DmaRequestSource_e)SPI_DMA_TX_REQID); + DMA_rigisterChannelCallback(DMA_INSTANCE_MP, lcdDmaTxCh, txCb); + //DMA_transferSetup(DMA_INSTANCE_MP, lcdDmaTxCh, &lcdDmaTxCfg); + //DMA_transferSetup(DMA_INSTANCE_MP, lcdDmaTxCh, &lcdDmaConfig); +#endif +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/lcd/st7571/st7571.c b/PLAT/driver/board/ec618_0h00/src/lcd/st7571/st7571.c new file mode 100644 index 0000000..1cd1cbe --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/lcd/st7571/st7571.c @@ -0,0 +1,218 @@ +#include "lcdDrv.h" + +uint8_t clearScreen[128] = {0}; + +#define USE_DMA + +#ifdef USE_DMA +static DmaTransferConfig_t st7571DmaTxCfg = +{ + NULL, + (void *)&(SPI->DR), + DMA_FLOW_CONTROL_TARGET, + DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_ONE_BYTE, + DMA_BURST_8_BYTES, + 0 +}; +static DmaDescriptor_t __ALIGNED(16) st7571DmaTxDesc[1]; +int8_t st7571DmaTxCh; +bool isDMADone = false; +uint8_t st7571DmaSrc[128] = {0}; +uint8_t *pLcdData = NULL; + +static void st7571DmaEventCb(uint32_t event) +{ + switch(event) + { + case DMA_EVENT_END: + isDMADone = true; + SPI_CS_HIGH; + //DMA_stopChannel(DMA_INSTANCE_MP, st7571DmaTxCh, false); + + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + +void st7571DmaInit() +{ + // Tx config + DMA_init(DMA_INSTANCE_MP); + st7571DmaTxCh = DMA_openChannel(DMA_INSTANCE_MP); + + DMA_setChannelRequestSource(DMA_INSTANCE_MP, st7571DmaTxCh, (DmaRequestSource_e)SPI_DMA_TX_REQID); + DMA_rigisterChannelCallback(DMA_INSTANCE_MP, st7571DmaTxCh, st7571DmaEventCb); + SPI_ENABLE_TX_DMA; +} + +void st7571WriteCtrl(uint32_t totalLen) +{ + // Configure tx DMA and start it + st7571DmaTxCfg.sourceAddress = (void *)pLcdData; + st7571DmaTxCfg.totalLength = totalLen; // every descriptor transfer this trunk of data + + SPI_CS_LOW; + LCD_DS_HIGH; + DMA_buildDescriptorChain(st7571DmaTxDesc, &st7571DmaTxCfg, 1, true); + //SPI_ENABLE_TX_DMA; + + DMA_loadChannelDescriptorAndRun(DMA_INSTANCE_MP, st7571DmaTxCh, st7571DmaTxDesc); +} +#endif + + +void st7571_init() +{ + //--------------------------------ST7571 reset sequence------------------------------------// + LCD_RST_HIGH; + mDelay(50); //Delay 100ms + LCD_RST_LOW; + mDelay(150); //Delay 200ms + LCD_RST_HIGH; + mDelay(250); //Delay 500ms + + lcdWriteCmd(0xAE); + lcdWriteCmd(0xE2); + lcdWriteCmd(0x38); + + lcdWriteCmd(0xE1); + lcdWriteCmd(0xAB); + + lcdWriteCmd(0x54); + lcdWriteCmd(0x48); + lcdWriteCmd(0x80); + + + lcdWriteCmd(0xB8); + + lcdWriteCmd(0xA2); + lcdWriteCmd(0xA0); + lcdWriteCmd(0xc8); + + lcdWriteCmd(0x25); + lcdWriteCmd(0x81); + //lcdWriteCmd(v0); //////////////////////////////////////////// + lcdWriteCmd(0x23); + + + lcdWriteCmd(0x40);//START LINE + lcdWriteCmd(0x00); + + lcdWriteCmd(0x44);//START LINE + lcdWriteCmd(0x00); + + lcdWriteCmd(0x2c); mDelay(10); + lcdWriteCmd(0x2e); mDelay(10); + lcdWriteCmd(0x2F); mDelay(10); + + + + lcdWriteCmd(0xAF);//DISPLAY ON + + + lcdWriteCmd(0x7B); + lcdWriteCmd(0x11); // 0x11=black/white mode; 0x10=gray mode; + lcdWriteCmd(0x00); + + mDelay(10); + //disp_off(); + mDelay(50); + +#ifdef USE_DMA + st7571DmaInit(); +#endif +} + + +void lcdAddress(uint8_t page, uint8_t column) +{ + lcdWriteCmd(0xB0 + page); + lcdWriteCmd(((column >> 4) & 0x0f) + 0x10); // column addr MSB + lcdWriteCmd(column & 0x0f); // column addr LSB +} + +void st7571CleanScreen(void) +{ + uint8_t j; +#ifdef USE_DMA + pLcdData = clearScreen; +#else + uint8_t i; +#endif + + for(j = 0; j < 16; j++) + { + lcdAddress(j, 0); +#ifndef USE_DMA + for(i = 0; i < 128; i++) + { + lcdWriteData(0x00); + } +#else + st7571WriteCtrl(128); + + do + { + delay_us(1); + }while (isDMADone == false); + isDMADone = false; +#endif + } +} + +void displayPic_60x80(uint8_t *p) +{ +#ifndef USE_DMA + uint32_t k; +#endif + uint32_t n; + st7571CleanScreen(); + + for(n = 0; n < 10; n++) // 16 page + { + lcdAddress(n, 0); + +#ifndef USE_DMA + for(k = 0; k < 60; k++)// every page 64byte, total 1k + { + lcdWriteData(p[k + 60 * n]); + } +#else + pLcdData = p + 60 * n; + st7571WriteCtrl(60); + + do + { + delay_us(1); + }while (isDMADone == false); + isDMADone = false; +#endif + } +} + + + +void testResolution() +{ + st7571CleanScreen(); + + uint32_t k, n; + + for (n = 0; n < 16; n++) + { + lcdAddress(n, 0); // set page and initial column + for(k = 0; k < 64/4; k++)// every page 64byte, total 1k + { + lcdWriteData(0xff); // write one byte 1 + lcdWriteData(0xff); // write one byte 1 again + + lcdWriteData(0); // write one byte 0 + lcdWriteData(0); // write one byte 0 again + } + } +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/lcd/st7789v2/st7789v2.c b/PLAT/driver/board/ec618_0h00/src/lcd/st7789v2/st7789v2.c new file mode 100644 index 0000000..4ac8cf6 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/lcd/st7789v2/st7789v2.c @@ -0,0 +1,84 @@ +#include "lcdDrv.h" + +void st7789v2_init() +{ + //--------------------------------ST7789V reset sequence------------------------------------// + LCD_RST_HIGH; + mDelay(50); //Delay 100ms + LCD_RST_LOW; + mDelay(150); //Delay 200ms + LCD_RST_HIGH; + mDelay(250); //Delay 500ms + + //-------------------------------Color Mode---------------------------------------------// + lcdWriteCmd(0x11); + mDelay (120); //Delay 120ms + + //--------------------------------Display Setting------------------------------------------// + lcdWriteCmd(0x36); + lcdWriteData(0x00); + lcdWriteCmd(0x3a); + lcdWriteData(0x05); + + //--------------------------------ST7789V Frame rate setting----------------------------------// + lcdWriteCmd(0xb2); + lcdWriteData(0x0c); + lcdWriteData(0x0c); + lcdWriteData(0x00); + lcdWriteData(0x33); + lcdWriteData(0x33); + lcdWriteCmd(0xb7); + lcdWriteData(0x35); + + //--------------------------------ST7789V Power setting--------------------------------------// + lcdWriteCmd(0xbb); + lcdWriteData(0x20); + lcdWriteCmd(0xc0); + lcdWriteData(0x2c); + lcdWriteCmd(0xc2); + lcdWriteData(0x01); + lcdWriteCmd(0xc3); + lcdWriteData(0x0b); + lcdWriteCmd(0xc4); + lcdWriteData(0x20); + lcdWriteCmd(0xc6); + lcdWriteData(0x0f); + lcdWriteCmd(0xd0); + lcdWriteData(0xa4); + lcdWriteData(0xa1); + + //--------------------------------ST7789V gamma setting---------------------------------------// + lcdWriteCmd(0xe0); + lcdWriteData(0xd0); + lcdWriteData(0x03); + lcdWriteData(0x09); + lcdWriteData(0x0e); + lcdWriteData(0x11); + lcdWriteData(0x3d); + lcdWriteData(0x47); + lcdWriteData(0x55); + lcdWriteData(0x53); + lcdWriteData(0x1a); + lcdWriteData(0x16); + lcdWriteData(0x14); + lcdWriteData(0x1f); + lcdWriteData(0x22); + lcdWriteCmd(0xe1); + lcdWriteData(0xd0); + lcdWriteData(0x02); + lcdWriteData(0x08); + lcdWriteData(0x0d); + lcdWriteData(0x12); + lcdWriteData(0x2c); + lcdWriteData(0x43); + lcdWriteData(0x55); + lcdWriteData(0x53); + lcdWriteData(0x1e); + lcdWriteData(0x1b); + lcdWriteData(0x19); + lcdWriteData(0x20); + lcdWriteData(0x22); + lcdWriteCmd(0x29); +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/ntc/ntc.c b/PLAT/driver/board/ec618_0h00/src/ntc/ntc.c new file mode 100644 index 0000000..0046333 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/ntc/ntc.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * + * Copy right: 2018 Copyrigths of AirM2M Ltd. + * File name: ntc.c + * Description: + * History: + * + ****************************************************************************/ +#include +#include "ntc.h" + +#define NCP15XH103F03RC + +#if defined(NCP15XH103F03RC) +static const int32_t gNTCLut[65] = { + 253347, // T:253.35 Rntc:0.0k ADC code:0 Input voltage:0uV + 187444, // T:187.44 Rntc:0.159k ADC code:64 Input voltage:18750uV + 149195, // T:149.2 Rntc:0.323k ADC code:128 Input voltage:37500uV + 128368, // T:128.37 Rntc:0.492k ADC code:192 Input voltage:56250uV + 115301, // T:115.3 Rntc:0.667k ADC code:256 Input voltage:75000uV + 105493, // T:105.49 Rntc:0.847k ADC code:320 Input voltage:93750uV + 97670, // T:97.67 Rntc:1.034k ADC code:384 Input voltage:112500uV + 91187, // T:91.19 Rntc:1.228k ADC code:448 Input voltage:131250uV + 85596, // T:85.6 Rntc:1.429k ADC code:512 Input voltage:150000uV + 80693, // T:80.69 Rntc:1.636k ADC code:576 Input voltage:168750uV + 76336, // T:76.34 Rntc:1.852k ADC code:640 Input voltage:187500uV + 72403, // T:72.4 Rntc:2.075k ADC code:704 Input voltage:206250uV + 68803, // T:68.8 Rntc:2.308k ADC code:768 Input voltage:225000uV + 65478, // T:65.48 Rntc:2.549k ADC code:832 Input voltage:243750uV + 62389, // T:62.39 Rntc:2.8k ADC code:896 Input voltage:262500uV + 59508, // T:59.51 Rntc:3.061k ADC code:960 Input voltage:281250uV + 56829, // T:56.83 Rntc:3.333k ADC code:1024 Input voltage:300000uV + 54289, // T:54.29 Rntc:3.617k ADC code:1088 Input voltage:318750uV + 51869, // T:51.87 Rntc:3.913k ADC code:1152 Input voltage:337500uV + 49556, // T:49.56 Rntc:4.222k ADC code:1216 Input voltage:356250uV + 47337, // T:47.34 Rntc:4.545k ADC code:1280 Input voltage:375000uV + 45200, // T:45.2 Rntc:4.884k ADC code:1344 Input voltage:393750uV + 43135, // T:43.14 Rntc:5.238k ADC code:1408 Input voltage:412500uV + 41134, // T:41.13 Rntc:5.61k ADC code:1472 Input voltage:431250uV + 39186, // T:39.19 Rntc:6.0k ADC code:1536 Input voltage:450000uV + 37287, // T:37.29 Rntc:6.41k ADC code:1600 Input voltage:468750uV + 35433, // T:35.43 Rntc:6.842k ADC code:1664 Input voltage:487500uV + 33620, // T:33.62 Rntc:7.297k ADC code:1728 Input voltage:506250uV + 31842, // T:31.84 Rntc:7.778k ADC code:1792 Input voltage:525000uV + 30095, // T:30.1 Rntc:8.286k ADC code:1856 Input voltage:543750uV + 28377, // T:28.38 Rntc:8.824k ADC code:1920 Input voltage:562500uV + 26680, // T:26.68 Rntc:9.394k ADC code:1984 Input voltage:581250uV + 25000, // T:25.0 Rntc:10.0k ADC code:2048 Input voltage:600000uV + 23332, // T:23.33 Rntc:10.645k ADC code:2112 Input voltage:618750uV + 21675, // T:21.68 Rntc:11.333k ADC code:2176 Input voltage:637500uV + 20024, // T:20.02 Rntc:12.069k ADC code:2240 Input voltage:656250uV + 18382, // T:18.38 Rntc:12.857k ADC code:2304 Input voltage:675000uV + 16741, // T:16.74 Rntc:13.704k ADC code:2368 Input voltage:693750uV + 15100, // T:15.1 Rntc:14.615k ADC code:2432 Input voltage:712500uV + 13455, // T:13.46 Rntc:15.6k ADC code:2496 Input voltage:731250uV + 11801, // T:11.8 Rntc:16.667k ADC code:2560 Input voltage:750000uV + 10137, // T:10.14 Rntc:17.826k ADC code:2624 Input voltage:768750uV + 8454, // T:8.45 Rntc:19.091k ADC code:2688 Input voltage:787500uV + 6750, // T:6.75 Rntc:20.476k ADC code:2752 Input voltage:806250uV + 5022, // T:5.02 Rntc:22.0k ADC code:2816 Input voltage:825000uV + 3265, // T:3.27 Rntc:23.684k ADC code:2880 Input voltage:843750uV + 1472, // T:1.47 Rntc:25.556k ADC code:2944 Input voltage:862500uV + -361, // T:-0.36 Rntc:27.647k ADC code:3008 Input voltage:881250uV + -2238, // T:-2.24 Rntc:30.0k ADC code:3072 Input voltage:900000uV + -4171, // T:-4.17 Rntc:32.667k ADC code:3136 Input voltage:918750uV + -6170, // T:-6.17 Rntc:35.714k ADC code:3200 Input voltage:937500uV + -8248, // T:-8.25 Rntc:39.231k ADC code:3264 Input voltage:956250uV + -10419, // T:-10.42 Rntc:43.333k ADC code:3328 Input voltage:975000uV + -12711, // T:-12.71 Rntc:48.182k ADC code:3392 Input voltage:993750uV + -15137, // T:-15.14 Rntc:54.0k ADC code:3456 Input voltage:1012500uV + -17727, // T:-17.73 Rntc:61.111k ADC code:3520 Input voltage:1031250uV + -20519, // T:-20.52 Rntc:70.0k ADC code:3584 Input voltage:1050000uV + -23562, // T:-23.56 Rntc:81.429k ADC code:3648 Input voltage:1068750uV + -26937, // T:-26.94 Rntc:96.667k ADC code:3712 Input voltage:1087500uV + -30762, // T:-30.76 Rntc:118.0k ADC code:3776 Input voltage:1106250uV + -35224, // T:-35.22 Rntc:150.0k ADC code:3840 Input voltage:1125000uV + -40677, // T:-40.68 Rntc:203.333k ADC code:3904 Input voltage:1143750uV + -47755, // T:-47.76 Rntc:310.0k ADC code:3968 Input voltage:1162500uV + -57225, // T:-57.23 Rntc:630.0k ADC code:4032 Input voltage:1181250uV + -69859, // T:-69.86 Rntc:10000.0k ADC code:4096 Input voltage:1200000uV +}; +#elif defined(NCP15WF104F03RC) +static const int32_t gNTCLut[65] = { + 175093, // T:175.09 Rntc:0.0k ADC code:0 Input voltage:0uV + 140197, // T:140.2 Rntc:1.587k ADC code:64 Input voltage:18750uV + 116573, // T:116.57 Rntc:3.226k ADC code:128 Input voltage:37500uV + 102838, // T:102.84 Rntc:4.918k ADC code:192 Input voltage:56250uV + 93457, // T:93.46 Rntc:6.667k ADC code:256 Input voltage:75000uV + 86333, // T:86.33 Rntc:8.475k ADC code:320 Input voltage:93750uV + 80598, // T:80.6 Rntc:10.345k ADC code:384 Input voltage:112500uV + 75787, // T:75.79 Rntc:12.281k ADC code:448 Input voltage:131250uV + 71646, // T:71.65 Rntc:14.286k ADC code:512 Input voltage:150000uV + 67994, // T:67.99 Rntc:16.364k ADC code:576 Input voltage:168750uV + 64720, // T:64.72 Rntc:18.519k ADC code:640 Input voltage:187500uV + 61757, // T:61.76 Rntc:20.755k ADC code:704 Input voltage:206250uV + 59039, // T:59.04 Rntc:23.077k ADC code:768 Input voltage:225000uV + 56524, // T:56.52 Rntc:25.49k ADC code:832 Input voltage:243750uV + 54178, // T:54.18 Rntc:28.0k ADC code:896 Input voltage:262500uV + 51977, // T:51.98 Rntc:30.612k ADC code:960 Input voltage:281250uV + 49898, // T:49.9 Rntc:33.333k ADC code:1024 Input voltage:300000uV + 47928, // T:47.93 Rntc:36.17k ADC code:1088 Input voltage:318750uV + 46050, // T:46.05 Rntc:39.13k ADC code:1152 Input voltage:337500uV + 44250, // T:44.25 Rntc:42.222k ADC code:1216 Input voltage:356250uV + 42521, // T:42.52 Rntc:45.455k ADC code:1280 Input voltage:375000uV + 40853, // T:40.85 Rntc:48.837k ADC code:1344 Input voltage:393750uV + 39240, // T:39.24 Rntc:52.381k ADC code:1408 Input voltage:412500uV + 37676, // T:37.68 Rntc:56.098k ADC code:1472 Input voltage:431250uV + 36155, // T:36.16 Rntc:60.0k ADC code:1536 Input voltage:450000uV + 34671, // T:34.67 Rntc:64.103k ADC code:1600 Input voltage:468750uV + 33220, // T:33.22 Rntc:68.421k ADC code:1664 Input voltage:487500uV + 31797, // T:31.8 Rntc:72.973k ADC code:1728 Input voltage:506250uV + 30400, // T:30.4 Rntc:77.778k ADC code:1792 Input voltage:525000uV + 29025, // T:29.03 Rntc:82.857k ADC code:1856 Input voltage:543750uV + 27669, // T:27.67 Rntc:88.235k ADC code:1920 Input voltage:562500uV + 26328, // T:26.33 Rntc:93.939k ADC code:1984 Input voltage:581250uV + 24999, // T:25.0 Rntc:100.0k ADC code:2048 Input voltage:600000uV + 23681, // T:23.68 Rntc:106.452k ADC code:2112 Input voltage:618750uV + 22370, // T:22.37 Rntc:113.333k ADC code:2176 Input voltage:637500uV + 21064, // T:21.06 Rntc:120.69k ADC code:2240 Input voltage:656250uV + 19760, // T:19.76 Rntc:128.571k ADC code:2304 Input voltage:675000uV + 18455, // T:18.46 Rntc:137.037k ADC code:2368 Input voltage:693750uV + 17148, // T:17.15 Rntc:146.154k ADC code:2432 Input voltage:712500uV + 15835, // T:15.84 Rntc:156.0k ADC code:2496 Input voltage:731250uV + 14513, // T:14.51 Rntc:166.667k ADC code:2560 Input voltage:750000uV + 13179, // T:13.18 Rntc:178.261k ADC code:2624 Input voltage:768750uV + 11830, // T:11.83 Rntc:190.909k ADC code:2688 Input voltage:787500uV + 10463, // T:10.46 Rntc:204.762k ADC code:2752 Input voltage:806250uV + 9074, // T:9.07 Rntc:220.0k ADC code:2816 Input voltage:825000uV + 7658, // T:7.66 Rntc:236.842k ADC code:2880 Input voltage:843750uV + 6211, // T:6.21 Rntc:255.556k ADC code:2944 Input voltage:862500uV + 4728, // T:4.73 Rntc:276.471k ADC code:3008 Input voltage:881250uV + 3202, // T:3.2 Rntc:300.0k ADC code:3072 Input voltage:900000uV + 1626, // T:1.63 Rntc:326.667k ADC code:3136 Input voltage:918750uV + -6, // T:-0.01 Rntc:357.143k ADC code:3200 Input voltage:937500uV + -1710, // T:-1.71 Rntc:392.308k ADC code:3264 Input voltage:956250uV + -3495, // T:-3.5 Rntc:433.333k ADC code:3328 Input voltage:975000uV + -5376, // T:-5.38 Rntc:481.818k ADC code:3392 Input voltage:993750uV + -7371, // T:-7.37 Rntc:540.0k ADC code:3456 Input voltage:1012500uV + -9506, // T:-9.51 Rntc:611.111k ADC code:3520 Input voltage:1031250uV + -11819, // T:-11.82 Rntc:700.0k ADC code:3584 Input voltage:1050000uV + -14354, // T:-14.35 Rntc:814.286k ADC code:3648 Input voltage:1068750uV + -17179, // T:-17.18 Rntc:966.667k ADC code:3712 Input voltage:1087500uV + -20397, // T:-20.4 Rntc:1180.0k ADC code:3776 Input voltage:1106250uV + -24176, // T:-24.18 Rntc:1500.0k ADC code:3840 Input voltage:1125000uV + -28836, // T:-28.84 Rntc:2033.333k ADC code:3904 Input voltage:1143750uV + -35053, // T:-35.05 Rntc:3100.0k ADC code:3968 Input voltage:1162500uV + -44840, // T:-44.84 Rntc:6300.0k ADC code:4032 Input voltage:1181250uV + -63302, // T:-63.3 Rntc:100000.0k ADC code:4096 Input voltage:1200000uV +}; + +#else +#error "NTC type is not defined" +#endif + + +int32_t ntcGetTemperature(int32_t adcInputVoltage) +{ + if(adcInputVoltage <= 1200000) + { + int32_t step = 1200000 >> 6; + int32_t i = adcInputVoltage / step; + return gNTCLut[i] + ((int32_t)((gNTCLut[i + 1] - gNTCLut[i]) * (adcInputVoltage - (i * step))) / step); + } + else + { + return -256000; + } +} + + diff --git a/PLAT/driver/board/ec618_0h00/src/plat_config.c b/PLAT/driver/board/ec618_0h00/src/plat_config.c new file mode 100644 index 0000000..4a2e640 --- /dev/null +++ b/PLAT/driver/board/ec618_0h00/src/plat_config.c @@ -0,0 +1,844 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: plat_config.c + * Description: platform configuration source file + * History: + * + ****************************************************************************/ + +#include +#include +#include +#include "plat_config.h" +#include "exception_process.h" +#ifdef FEATURE_BOOTLOADER_PROJECT_ENABLE +#include "debug_trace.h" +#include "common.h" +#else +#include DEBUG_LOG_HEADER_FILE +#include "osasys.h" + +#define PLAT_CONFIG_FS_ENABLE +#endif + +/** \brief config file version + * \note when the order of struct \ref plat_config_fs_t and \ref plat_config_raw_flash_t field has changed, + * for example, from 1,2,3 to 1,3,2, update version to refresh flash, + * in other cases(add more fields or remove some fields from struct \ref plat_config_fs_t), it's not a must to update + */ + +// external API declarations +extern uint8_t BSP_QSPI_Erase_Safe(uint32_t SectorAddress, uint32_t Size); +extern uint8_t BSP_QSPI_Write_Safe(uint8_t* pData, uint32_t WriteAddr, uint32_t Size); +extern uint8_t BSP_QSPI_Erase_Sector(uint32_t BlockAddress); +extern uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size); +extern uint8_t getOSState(void); + + +/** + \fn uint8_t BSP_CalcCrcValue(const uint8_t *buf, uint16_t bufSize) + \brief Calculate the "CRC" value of data buffer + \param[in] buf buffer pointer + \param[in] bufSize buffer size + \returns crcValue +*/ +static uint8_t BSP_CalcCrcValue(const uint8_t *buf, uint16_t bufSize) +{ + uint32_t i = bufSize; + uint32_t a = 1, b = 0; + + EC_ASSERT(buf != NULL && bufSize > 0, buf, bufSize, 0); + + for (i = bufSize; i > 0; ) + { + a += (uint32_t)(buf[--i]); + b += a; + } + + return (uint8_t)(((a>>24)&0xFF)^((a>>16)&0xFF)^((a>>8)&0xFF)^((a)&0xFF)^ + ((b>>24)&0xFF)^((b>>16)&0xFF)^((b>>8)&0xFF)^((b)&0xFF)^ + (bufSize&0xFF)); +} + + +#ifdef PLAT_CONFIG_FS_ENABLE +static uint8_t g_fsPlatConfigInitFlag = 0; +static plat_config_fs_t g_fsPlatConfig; + +/** + \fn void BSP_SetDefaultFsPlatConfig(void) + \brief set default value of "g_fsPlatConfig" + \return void +*/ +static void BSP_SetDefaultFsPlatConfig(void) +{ + g_fsPlatConfigInitFlag = 1; + + memset(&g_fsPlatConfig, 0x0, sizeof(g_fsPlatConfig)); + g_fsPlatConfig.atPortBaudRate = 115200; +} + +void BSP_LoadPlatConfigFromFs(void) +{ + OSAFILE fp = PNULL; + UINT32 readCount = 0; + UINT8 crcCheck = 0; + config_file_header_t fileHeader; + + /* + * open NVM file + */ + fp = OsaFopen("plat_config", "rb"); //read only + if (fp == PNULL) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_LoadPlatConfig_1, P_ERROR, + "Can't open 'plat_config' file, use the defult value"); + + BSP_SetDefaultFsPlatConfig(); + BSP_SavePlatConfigToFs(); + + return; + } + + /* + * read file header + */ + readCount = OsaFread(&fileHeader, sizeof(config_file_header_t), 1, fp); + if (readCount != 1) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_LoadPlatConfig_2, P_ERROR, + "Can't read 'plat_config' file header, use the defult value"); + + OsaFclose(fp); + + BSP_SetDefaultFsPlatConfig(); + BSP_SavePlatConfigToFs(); + + return; + } + + /* + * read file body, check validation and handle compatiblity issue + */ + if(fileHeader.version != FS_PLAT_CONFIG_FILE_CURRENT_VERSION) + { + if(fileHeader.version == 0) + { + } + // handle future version below + else if(0) + { + + } + else + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_LoadPlatConfig_5, P_ERROR, + "'plat_config' version:%d not right, use the defult value", fileHeader.version); + + OsaFclose(fp); + + BSP_SetDefaultFsPlatConfig(); + BSP_SavePlatConfigToFs(); + } + } + else + { + if(fileHeader.fileBodySize != sizeof(g_fsPlatConfig)) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_LoadPlatConfig_3, P_ERROR, + "'plat_config' version:%d file body size not right: (%u/%u), use the defult value", + fileHeader.version, fileHeader.fileBodySize, sizeof(plat_config_fs_t)); + + OsaFclose(fp); + + BSP_SetDefaultFsPlatConfig(); + BSP_SavePlatConfigToFs(); + } + else + { + readCount = OsaFread(&g_fsPlatConfig, sizeof(g_fsPlatConfig), 1, fp); + crcCheck = BSP_CalcCrcValue((uint8_t *)&g_fsPlatConfig, sizeof(g_fsPlatConfig)); + + OsaFclose(fp); + + if (readCount != 1 || crcCheck != fileHeader.checkSum) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_LoadPlatConfig_4, P_ERROR, + "Can't read 'plat_config' version:%d file body, or body not right, (%u/%u), use the defult value", + fileHeader.version, crcCheck, fileHeader.checkSum); + + BSP_SetDefaultFsPlatConfig(); + BSP_SavePlatConfigToFs(); + } + else + { + g_fsPlatConfigInitFlag = 1; + } + } + + } + + return; +} + + +void BSP_SetFsPorDefaultValue(void) +{ + bool fsCfgChanged = false; + if(g_fsPlatConfig.ecSclkCfg != 0) + { + g_fsPlatConfig.ecSclkCfg = 0; + fsCfgChanged = true; + } + if(fsCfgChanged) + { + BSP_SavePlatConfigToFs(); + } +} + + + +void BSP_SavePlatConfigToFs(void) +{ + OSAFILE fp = PNULL; + UINT32 writeCount = 0; + config_file_header_t fileHeader; + + /* + * open the config file + */ + fp = OsaFopen("plat_config", "wb"); //write & create + if (fp == PNULL) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfig_1, P_ERROR, + "Can't open/create 'plat_config' file, save plat_config failed"); + + return; + } + + /* + * write the header + */ + fileHeader.fileBodySize = sizeof(g_fsPlatConfig); + fileHeader.version = FS_PLAT_CONFIG_FILE_CURRENT_VERSION; + fileHeader.checkSum = BSP_CalcCrcValue((uint8_t *)&g_fsPlatConfig, sizeof(g_fsPlatConfig)); + + writeCount = OsaFwrite(&fileHeader, sizeof(config_file_header_t), 1, fp); + if (writeCount != 1) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfig_2, P_ERROR, + "Write 'plat_config' file header failed"); + + OsaFclose(fp); + return; + } + + /* + * write the file body + */ + writeCount = OsaFwrite(&g_fsPlatConfig, sizeof(g_fsPlatConfig), 1, fp); + if (writeCount != 1) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfig_3, P_ERROR, + "Write 'plat_config' file body failed"); + } + + OsaFclose(fp); + return; + +} + +plat_config_fs_t* BSP_GetFsPlatConfig(void) +{ + return &g_fsPlatConfig; +} + +uint32_t BSP_GetFSAssertCount(void) +{ + plat_info_layout_t platInfo; + + // read + memcpy((uint8_t*)&platInfo, (void*)FLASH_MEM_PLAT_INFO_ADDR, sizeof(plat_info_layout_t)); + + return platInfo.fsAssertCount; +} + +void BSP_SetFSAssertCount(uint32_t value) +{ + plat_info_layout_t platInfo; + + // read + memcpy((uint8_t*)&platInfo, (void*)FLASH_MEM_PLAT_INFO_ADDR, sizeof(plat_info_layout_t)); + + // modify + platInfo.fsAssertCount = value; + + // erase + if(BSP_QSPI_Erase_Safe(FLASH_MEM_PLAT_INFO_NONXIP_ADDR, FLASH_MEM_PLAT_INFO_SIZE) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SetFSAssertCount_0, P_ERROR, "Erase flash error!!!"); + return; + } + + // write back + if(BSP_QSPI_Write_Safe((uint8_t*)&platInfo, FLASH_MEM_PLAT_INFO_NONXIP_ADDR, sizeof(plat_info_layout_t)) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SetFSAssertCount_1, P_ERROR, "Update fsAssertCount value error!!!"); + } + +} + +#endif + + +plat_config_raw_flash_t g_rawFlashPlatConfig; + +/** + \fn void BSP_SetDefaultRawFlashPlatConfig(void) + \brief set default value of "g_rawFlashPlatConfig" + \return void +*/ +static void BSP_SetDefaultRawFlashPlatConfig(void) +{ + +#ifdef SDK_REL_BUILD + g_rawFlashPlatConfig.faultAction = 4;//silent anable + g_rawFlashPlatConfig.startWDT = 1;//start wdt +#else + g_rawFlashPlatConfig.faultAction = 0; + g_rawFlashPlatConfig.startWDT = 0; +#endif + g_rawFlashPlatConfig.uartDumpPort = 1; // default at port + + g_rawFlashPlatConfig.logControl = 0x2; + + g_rawFlashPlatConfig.uartBaudRate = 3000000; + + g_rawFlashPlatConfig.logLevel = P_DEBUG; + + g_rawFlashPlatConfig.logPortSel = PLAT_CFG_ULG_PORT_MIX;//default MIX mode + + g_rawFlashPlatConfig.usbCtrl = 0;//all en + + g_rawFlashPlatConfig.usbSlpMask = 0; // no mask + + g_rawFlashPlatConfig.usbSlpThd = 0; + + g_rawFlashPlatConfig.pwrKeyMode = 0; + + g_rawFlashPlatConfig.usbVBUSModeEn = 0; + + g_rawFlashPlatConfig.usbVBUSWkupPad = 1; + + g_rawFlashPlatConfig.usbNet = 0; + + g_rawFlashPlatConfig.usbVcomEnBitMap = 0; + +#ifdef PLAT_CONFIG_FS_ENABLE + g_rawFlashPlatConfig.atPortBaudRate = g_fsPlatConfigInitFlag ? g_fsPlatConfig.atPortBaudRate : 115200; +#else + g_rawFlashPlatConfig.atPortBaudRate = 115200; +#endif + g_rawFlashPlatConfig.fotaUrcPortSel = (PLAT_CFG_FOTA_URC_PORT_USB << 4) | 0; + + g_rawFlashPlatConfig.slpLimitEn = 0; + + g_rawFlashPlatConfig.slpLimitTime = 0; + + memset(g_rawFlashPlatConfig.resv, 0x0,PLAT_CFG_RAW_FLASH_RSVD_SIZE); +} + +void BSP_SavePlatConfigToRawFlash(void) +{ + plat_info_layout_t platInfo; + + // read + memcpy((uint8_t*)&platInfo, (void*)FLASH_MEM_PLAT_INFO_ADDR, sizeof(plat_info_layout_t)); + + // modify start // + // header part + platInfo.header.fileBodySize = sizeof(plat_config_raw_flash_t); + platInfo.header.version = RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION; + platInfo.header.checkSum = BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)); + + // body part + platInfo.config = g_rawFlashPlatConfig; + // modify end // + + // write back + +#ifndef FEATURE_BOOTLOADER_PROJECT_ENABLE + if(1 == getOSState()) + { + if(BSP_QSPI_Erase_Safe(FLASH_MEM_PLAT_INFO_NONXIP_ADDR, FLASH_MEM_PLAT_INFO_SIZE) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfigToRawFlash_1, P_ERROR, "Erase flash error!!!"); + return; + } + + if(BSP_QSPI_Write_Safe((uint8_t*)&platInfo, FLASH_MEM_PLAT_INFO_NONXIP_ADDR, sizeof(plat_info_layout_t)) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfigToRawFlash_2, P_ERROR, "Save plat config to raw flash error!!!"); + } + } + else +#endif + { + if(BSP_QSPI_Erase_Sector(FLASH_MEM_PLAT_INFO_NONXIP_ADDR) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfigToRawFlash_3, P_ERROR, "Erase flash error!!!"); + return; + } + + if(BSP_QSPI_Write((uint8_t*)&platInfo, FLASH_MEM_PLAT_INFO_NONXIP_ADDR, sizeof(plat_info_layout_t)) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SavePlatConfigToRawFlash_4, P_ERROR, "Save plat config to raw flash error!!!"); + } + } + +} + +static void BSP_WriteToRawFlash(uint8_t* pBuffer, uint32_t bufferSize) +{ + if(pBuffer == NULL || bufferSize == 0) + { + return; + } + +#ifndef FEATURE_BOOTLOADER_PROJECT_ENABLE + if(1 == getOSState()) + { + if(BSP_QSPI_Erase_Safe(FLASH_MEM_PLAT_INFO_NONXIP_ADDR, FLASH_MEM_PLAT_INFO_SIZE) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_WriteToRawFlash_1, P_ERROR, "Erase flash error!!!"); + return; + } + + if(BSP_QSPI_Write_Safe(pBuffer, FLASH_MEM_PLAT_INFO_NONXIP_ADDR, bufferSize) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_WriteToRawFlash_2, P_ERROR, "Save plat config to raw flash error!!!"); + } + } + else +#endif + { + if(BSP_QSPI_Erase_Sector(FLASH_MEM_PLAT_INFO_NONXIP_ADDR) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_WriteToRawFlash_3, P_ERROR, "Erase flash error!!!"); + return; + } + + if(BSP_QSPI_Write(pBuffer, FLASH_MEM_PLAT_INFO_NONXIP_ADDR, bufferSize) != 0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_WriteToRawFlash_4, P_ERROR, "Save plat config to raw flash error!!!"); + } + } + +} + +void BSP_LoadPlatConfigFromRawFlash(void) +{ + plat_info_layout_t platInfo; + config_file_header_t header; + uint32_t fsAssertCount; + + /* + * read file header + */ + memcpy((uint8_t*)&header, (void*)FLASH_MEM_PLAT_INFO_ADDR, sizeof(header)); + + if(header.version != RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION) + { + if(header.version == 0) + { + plat_config_raw_flash_v0_t v0Config; + + BSP_SetDefaultRawFlashPlatConfig(); + + // migrate from old version + if(header.fileBodySize == sizeof(plat_config_raw_flash_v0_t)) + { + memcpy((uint8_t*)&v0Config, (void*)(FLASH_MEM_PLAT_INFO_ADDR + sizeof(config_file_header_t)), sizeof(v0Config)); + memcpy((uint8_t*)&fsAssertCount, (void*)(FLASH_MEM_PLAT_INFO_ADDR + sizeof(config_file_header_t) + sizeof(v0Config)), sizeof(fsAssertCount)); + + g_rawFlashPlatConfig.faultAction = v0Config.faultAction; + g_rawFlashPlatConfig.uartDumpPort = v0Config.uartDumpPort; + g_rawFlashPlatConfig.startWDT = v0Config.startWDT; + g_rawFlashPlatConfig.logControl = v0Config.logControl; + g_rawFlashPlatConfig.uartBaudRate = v0Config.uartBaudRate; + g_rawFlashPlatConfig.logLevel = v0Config.logLevel; + g_rawFlashPlatConfig.logPortSel = v0Config.logPortSel; + g_rawFlashPlatConfig.usbCtrl = v0Config.usbCtrl; + g_rawFlashPlatConfig.usbSwTrace = v0Config.usbSwTrace; + g_rawFlashPlatConfig.usbSlpMask = v0Config.usbSlpMask; + g_rawFlashPlatConfig.usbSlpThd = v0Config.usbSlpThd; + g_rawFlashPlatConfig.pwrKeyMode = v0Config.pwrKeyMode; + + platInfo.header.fileBodySize = sizeof(plat_config_raw_flash_t); + platInfo.header.version = RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION; + platInfo.header.checkSum = BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)); + + platInfo.config = g_rawFlashPlatConfig; + + platInfo.fsAssertCount = fsAssertCount; + + } + // version matches but size is wrong, use default value + else + { + platInfo.header.fileBodySize = sizeof(plat_config_raw_flash_t); + platInfo.header.version = RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION; + platInfo.header.checkSum = BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)); + + platInfo.config = g_rawFlashPlatConfig; + platInfo.fsAssertCount = 0; + } + + BSP_WriteToRawFlash((uint8_t*)&platInfo, sizeof(platInfo)); + + } + else if(0) + { + // handle future version + } + else + { + // version is invalid + + BSP_SetDefaultRawFlashPlatConfig(); + + platInfo.header.fileBodySize = sizeof(plat_config_raw_flash_t); + platInfo.header.version = RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION; + platInfo.header.checkSum = BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)); + + platInfo.config = g_rawFlashPlatConfig; + platInfo.fsAssertCount = 0; + + BSP_WriteToRawFlash((uint8_t*)&platInfo, sizeof(platInfo)); + + } + } + else + { + // file body check + memcpy((uint8_t*)&g_rawFlashPlatConfig, (void*)(FLASH_MEM_PLAT_INFO_ADDR + sizeof(config_file_header_t)), sizeof(g_rawFlashPlatConfig)); + + if((header.fileBodySize != sizeof(plat_config_raw_flash_t)) || + (header.checkSum != BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)))) + { + + BSP_SetDefaultRawFlashPlatConfig(); + + platInfo.header.fileBodySize = sizeof(plat_config_raw_flash_t); + platInfo.header.version = RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION; + platInfo.header.checkSum = BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)); + + platInfo.config = g_rawFlashPlatConfig; + platInfo.fsAssertCount = 0; + + BSP_WriteToRawFlash((uint8_t*)&platInfo, sizeof(platInfo)); + } + else + { + #ifdef PLAT_CONFIG_FS_ENABLE + if(g_fsPlatConfigInitFlag && g_fsPlatConfig.atPortBaudRate != g_rawFlashPlatConfig.atPortBaudRate) + { + g_rawFlashPlatConfig.atPortBaudRate = g_fsPlatConfig.atPortBaudRate; + + memcpy((uint8_t*)&fsAssertCount, (void*)(FLASH_MEM_PLAT_INFO_ADDR + sizeof(config_file_header_t) + sizeof(g_rawFlashPlatConfig)), sizeof(fsAssertCount)); + platInfo.header.fileBodySize = sizeof(plat_config_raw_flash_t); + platInfo.header.version = RAW_FLASH_PLAT_CONFIG_FILE_CURRENT_VERSION; + platInfo.header.checkSum = BSP_CalcCrcValue((uint8_t *)&g_rawFlashPlatConfig, sizeof(g_rawFlashPlatConfig)); + + platInfo.config = g_rawFlashPlatConfig; + platInfo.fsAssertCount = fsAssertCount; + + BSP_WriteToRawFlash((uint8_t*)&platInfo, sizeof(platInfo)); + } + #else + /* do nothing! */ + #endif + } + + + } + +} + +plat_config_raw_flash_t* BSP_GetRawFlashPlatConfig(void) +{ + return &g_rawFlashPlatConfig; +} + +uint32_t BSP_GetPlatConfigItemValue(plat_config_id_t id) +{ + switch(id) + { + case PLAT_CONFIG_ITEM_FAULT_ACTION: + return g_rawFlashPlatConfig.faultAction; + + case PLAT_CONFIG_ITEM_UART_DUMP_PORT: + return g_rawFlashPlatConfig.uartDumpPort; + + case PLAT_CONFIG_ITEM_START_WDT: + return g_rawFlashPlatConfig.startWDT; + + case PLAT_CONFIG_ITEM_LOG_CONTROL: + return g_rawFlashPlatConfig.logControl; + + case PLAT_CONFIG_ITEM_LOG_BAUDRATE: + return g_rawFlashPlatConfig.uartBaudRate; + + case PLAT_CONFIG_ITEM_LOG_LEVEL: + return g_rawFlashPlatConfig.logLevel; + + case PLAT_CONFIG_ITEM_ENABLE_PM: + #ifdef PLAT_CONFIG_FS_ENABLE + return g_fsPlatConfig.enablePM; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_GET_PLAT_CFG_0, P_ERROR, "Get enablePM unsupported yet!"); + return 0; + #endif + + case PLAT_CONFIG_ITEM_SLEEP_MODE: + #ifdef PLAT_CONFIG_FS_ENABLE + return g_fsPlatConfig.sleepMode; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_GET_PLAT_CFG_1, P_ERROR, "Get sleepMode unsupported yet!"); + return 0; + #endif + + case PLAT_CONFIG_ITEM_WAIT_SLEEP: + #ifdef PLAT_CONFIG_FS_ENABLE + return g_fsPlatConfig.slpWaitTime; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_GET_PLAT_CFG_2, P_ERROR, "Get slpWaitTime unsupported yet!"); + return 0; + #endif + + case PLAT_CONFIG_ITEM_AT_PORT_BAUDRATE: + #ifdef PLAT_CONFIG_FS_ENABLE + #if 0 + EC_ASSERT(g_fsPlatConfig.atPortBaudRate == g_rawFlashPlatConfig.atPortBaudRate, + g_fsPlatConfig.atPortBaudRate, g_rawFlashPlatConfig.atPortBaudRate, 0); + #else + if(g_fsPlatConfig.atPortBaudRate != g_rawFlashPlatConfig.atPortBaudRate) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_GET_PLAT_CFG_3, P_WARNING, "non-identical baud between fs(%d) & raw(%d)!", + g_fsPlatConfig.atPortBaudRate, g_rawFlashPlatConfig.atPortBaudRate); + } + #endif + return g_fsPlatConfig.atPortBaudRate; + #else + return g_rawFlashPlatConfig.atPortBaudRate; + #endif + + case PLAT_CONFIG_ITEM_AT_PORT_FRAME_FORMAT: + #ifdef PLAT_CONFIG_FS_ENABLE + return g_fsPlatConfig.atPortFrameFormat.wholeValue; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_GET_PLAT_CFG_4, P_ERROR, "Get atPortFrameFormat unsupported yet!"); + return 0; + #endif + + case PLAT_CONFIG_ITEM_ECSCLK_CFG: + #ifdef PLAT_CONFIG_FS_ENABLE + return g_fsPlatConfig.ecSclkCfg; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_GET_PLAT_CFG_5, P_ERROR, "Get ecSclkCfg unsupported yet!"); + return 0; + #endif + + case PLAT_CONFIG_ITEM_LOG_PORT_SEL: + return g_rawFlashPlatConfig.logPortSel; + + case PLAT_CONFIG_ITEM_USB_CTRL: + return g_rawFlashPlatConfig.usbCtrl; + + case PLAT_CONFIG_ITEM_USB_SW_TRACE_FLAG: + return g_rawFlashPlatConfig.usbSwTrace; + + case PLAT_CONFIG_ITEM_USB_SLEEP_MASK: + return g_rawFlashPlatConfig.usbSlpMask; + + case PLAT_CONFIG_ITEM_USB_SLEEP_THD: + return g_rawFlashPlatConfig.usbSlpThd; + + case PLAT_CONFIG_ITEM_USB_VBUS_MODE_EN: + return g_rawFlashPlatConfig.usbVBUSModeEn; + + case PLAT_CONFIG_ITEM_USB_VBUS_WKUP_PAD: + return g_rawFlashPlatConfig.usbVBUSWkupPad; + + case PLAT_CONFIG_ITEM_PWRKEY_MODE: + return g_rawFlashPlatConfig.pwrKeyMode; + + case PLAT_CONFIG_ITEM_USB_NET: + return g_rawFlashPlatConfig.usbNet; + + case PLAT_CONFIG_ITEM_USB_VCOM_EN_BMP: + return g_rawFlashPlatConfig.usbVcomEnBitMap; + + case PLAT_CONFIG_ITEM_FOTA_URC_PORT_SEL: + return g_rawFlashPlatConfig.fotaUrcPortSel; + + case PLAT_CONFIG_ITEM_PMUINCDRX: + return g_rawFlashPlatConfig.pmuInCdrx; + + case PLAT_CONFIG_ITEM_SLP_LIMIT_EN: + return g_rawFlashPlatConfig.slpLimitEn; + + case PLAT_CONFIG_ITEM_SLP_LIMIT_TIME: + return g_rawFlashPlatConfig.slpLimitTime; + + default: + return 0; + } +} + +void BSP_SetPlatConfigItemValue(plat_config_id_t id, uint32_t value) +{ + switch(id) + { + case PLAT_CONFIG_ITEM_FAULT_ACTION: + if(value <= (EXCEP_OPTION_MAX -1)) + g_rawFlashPlatConfig.faultAction = value; + break; + + case PLAT_CONFIG_ITEM_UART_DUMP_PORT: + g_rawFlashPlatConfig.uartDumpPort = value; + break; + + case PLAT_CONFIG_ITEM_START_WDT: + if(value <= 1) + g_rawFlashPlatConfig.startWDT = value; + break; + + case PLAT_CONFIG_ITEM_LOG_CONTROL: + if(value <= 2) + g_rawFlashPlatConfig.logControl = value; + break; + + case PLAT_CONFIG_ITEM_LOG_BAUDRATE: + g_rawFlashPlatConfig.uartBaudRate = value; + break; + + case PLAT_CONFIG_ITEM_LOG_LEVEL: + if(value <= P_ERROR) + g_rawFlashPlatConfig.logLevel = (DebugTraceLevelType_e)value; + break; + + case PLAT_CONFIG_ITEM_ENABLE_PM: + #ifdef PLAT_CONFIG_FS_ENABLE + g_fsPlatConfig.enablePM = value; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SET_PLAT_CFG_0, P_ERROR, "Set enablePM unsupported yet!"); + #endif + break; + + case PLAT_CONFIG_ITEM_SLEEP_MODE: + #ifdef PLAT_CONFIG_FS_ENABLE + if(value <= 4) g_fsPlatConfig.sleepMode = value; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SET_PLAT_CFG_1, P_ERROR, "Set sleepMode unsupported yet!"); + #endif + break; + + case PLAT_CONFIG_ITEM_WAIT_SLEEP: + #ifdef PLAT_CONFIG_FS_ENABLE + g_fsPlatConfig.slpWaitTime = value; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SET_PLAT_CFG_2, P_ERROR, "Set slpWaitTime unsupported yet!"); + #endif + break; + + case PLAT_CONFIG_ITEM_AT_PORT_BAUDRATE: + g_rawFlashPlatConfig.atPortBaudRate = value; + #ifdef PLAT_CONFIG_FS_ENABLE + g_fsPlatConfig.atPortBaudRate = value; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SET_PLAT_CFG_3, P_ERROR, "Set atPortBaudRate unsupported yet!"); + #endif + break; + + case PLAT_CONFIG_ITEM_AT_PORT_FRAME_FORMAT: + #ifdef PLAT_CONFIG_FS_ENABLE + g_fsPlatConfig.atPortFrameFormat.wholeValue = value; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SET_PLAT_CFG_4, P_ERROR, "Set atPortFrameFormat unsupported yet!"); + #endif + break; + + case PLAT_CONFIG_ITEM_ECSCLK_CFG: + #ifdef PLAT_CONFIG_FS_ENABLE + g_fsPlatConfig.ecSclkCfg = value; + #else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_SET_PLAT_CFG_5, P_ERROR, "Set ecSclkCfg unsupported yet!"); + #endif + break; + + case PLAT_CONFIG_ITEM_LOG_PORT_SEL: + g_rawFlashPlatConfig.logPortSel = (PlatCfgUlgPort_e)value; + break; + + case PLAT_CONFIG_ITEM_USB_CTRL: + g_rawFlashPlatConfig.usbCtrl = value; + break; + + case PLAT_CONFIG_ITEM_USB_SW_TRACE_FLAG: + g_rawFlashPlatConfig.usbSwTrace = value; + break; + + case PLAT_CONFIG_ITEM_USB_SLEEP_MASK: + g_rawFlashPlatConfig.usbSlpMask = value; + break; + + case PLAT_CONFIG_ITEM_USB_SLEEP_THD: + g_rawFlashPlatConfig.usbSlpThd = value; + break; + + case PLAT_CONFIG_ITEM_USB_VBUS_MODE_EN: + g_rawFlashPlatConfig.usbVBUSModeEn = value; + break; + + case PLAT_CONFIG_ITEM_USB_VBUS_WKUP_PAD: + g_rawFlashPlatConfig.usbVBUSWkupPad = value; + break; + + case PLAT_CONFIG_ITEM_PWRKEY_MODE: + g_rawFlashPlatConfig.pwrKeyMode = value; + break; + + case PLAT_CONFIG_ITEM_USB_NET: + g_rawFlashPlatConfig.usbNet = value; + break; + + case PLAT_CONFIG_ITEM_USB_VCOM_EN_BMP: + g_rawFlashPlatConfig.usbVcomEnBitMap = value; + break; + + case PLAT_CONFIG_ITEM_FOTA_URC_PORT_SEL: + g_rawFlashPlatConfig.fotaUrcPortSel = value; + break; + + case PLAT_CONFIG_ITEM_PMUINCDRX: + g_rawFlashPlatConfig.pmuInCdrx = value; + break; + + case PLAT_CONFIG_ITEM_SLP_LIMIT_EN: + g_rawFlashPlatConfig.slpLimitEn = value; + break; + + case PLAT_CONFIG_ITEM_SLP_LIMIT_TIME: + g_rawFlashPlatConfig.slpLimitTime = value; + break; + + default: + break; + } + return; + +} + + diff --git a/PLAT/driver/chip/ec618/ap/inc/adc.h b/PLAT/driver/chip/ec618/ap/inc/adc.h new file mode 100644 index 0000000..aff5637 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/adc.h @@ -0,0 +1,182 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: adc.h + * Description: EC618 adc driver header file + * History: + ****************************************************************************/ + +#ifndef _ADC_EC618_H +#define _ADC_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup adc_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief List of ADC clock source divider */ +typedef enum +{ + ADC_CLOCK_DIV_4 = 0U, /**< ADC clock is divided by 4 from input clock */ + ADC_CLOCK_DIV_8 = 1U, /**< ADC clock is divided by 8 from input clock */ + ADC_CLOCK_DIV_16 = 2U, /**< ADC clock is divided by 16 from input clock */ +} AdcClockDivider_e; + +/** \brief List of ADC channels */ +typedef enum +{ + ADC_CHANNEL_THERMAL = 0U, /**< ADC Thermal channel */ + ADC_CHANNEL_VBAT = 1U, /**< ADC VBAT channel */ + ADC_CHANNEL_AIO4 = 2U, /**< ADC AIO4 channel */ + ADC_CHANNEL_AIO3 = 3U, /**< ADC AIO3 channel */ + ADC_CHANNEL_AIO2 = 4U, /**< ADC AIO2 channel */ + ADC_CHANNEL_AIO1 = 5U, /**< ADC AIO1 channel */ +} AdcChannel_e; + +/** \brief List of AIO resdiv select options */ +typedef enum +{ + ADC_AIO_RESDIV_RATIO_1 = 0U, /**< ADC AIO RESDIV select as VIN */ + ADC_AIO_RESDIV_RATIO_14OVER16 = 1U, /**< ADC AIO RESDIV select as 14/16 VIN */ + ADC_AIO_RESDIV_RATIO_12OVER16 = 2U, /**< ADC AIO RESDIV select as 12/16 VIN */ + ADC_AIO_RESDIV_RATIO_10OVER16 = 3U, /**< ADC AIO RESDIV select as 10/16 VIN */ + ADC_AIO_RESDIV_RATIO_8OVER16 = 4U, /**< ADC AIO RESDIV select as 8/16 VIN */ + ADC_AIO_RESDIV_RATIO_7OVER16 = 5U, /**< ADC AIO RESDIV select as 7/16 VIN */ + ADC_AIO_RESDIV_RATIO_6OVER16 = 6U, /**< ADC AIO RESDIV select as 6/16 VIN */ + ADC_AIO_RESDIV_RATIO_5OVER16 = 7U, /**< ADC AIO RESDIV select as 5/16 VIN */ + ADC_AIO_RESDIV_RATIO_4OVER16 = 8U, /**< ADC AIO RESDIV select as 4/16 VIN */ + ADC_AIO_RESDIV_RATIO_3OVER16 = 9U, /**< ADC AIO RESDIV select as 3/16 VIN */ + ADC_AIO_RESDIV_RATIO_2OVER16 = 10U, /**< ADC AIO RESDIV select as 2/16 VIN */ + ADC_AIO_RESDIV_RATIO_1OVER16 = 11U, /**< ADC AIO RESDIV select as 1/16 VIN */ + ADC_AIO_RESDIV_BYPASS = 12U, /**< BYPASS the whole ADC AIO RESDIV network(direct input) */ +} AdcAioResDiv_e; + +/** \brief List of VBAT resdiv select options */ +typedef enum +{ + ADC_VBAT_RESDIV_RATIO_8OVER16 = 0U, /**< ADC AIO RESDIV select as 8/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_7OVER16 = 1U, /**< ADC AIO RESDIV select as 7/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_6OVER16 = 2U, /**< ADC AIO RESDIV select as 6/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_5OVER16 = 3U, /**< ADC AIO RESDIV select as 5/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_4OVER16 = 4U, /**< ADC AIO RESDIV select as 4/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_3OVER16 = 5U, /**< ADC AIO RESDIV select as 3/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_2OVER16 = 6U, /**< ADC AIO RESDIV select as 2/16 VBAT */ + ADC_VBAT_RESDIV_RATIO_1OVER16 = 7U, /**< ADC AIO RESDIV select as 1/16 VBAT */ +} AdcVbatResdiv_e; + +/** \brief ADC channel configuration */ +typedef union +{ + AdcAioResDiv_e aioResDiv; /**< resdiv setting, valid only for AIO channel */ + AdcVbatResdiv_e vbatResDiv; /**< resdiv setting, valid only for VBAT channel */ +} AdcChannelConfig_t; + +/** \brief ADC configuration structure */ +typedef struct +{ + AdcClockDivider_e clockDivider; /**< ADC work clock source divider setting */ + AdcChannelConfig_t channelConfig; /**< ADC channel configuration */ +} AdcConfig_t; + +/** \brief List of ADC channel users, used to compose logical channel combining with ADC physical channel + each channel can be occupied by these users at the same time, conversion request gets serviced one by one in FIFO ordering. + */ +typedef enum +{ + ADC_USER_PHY = 0U, /**< Internal user ID for PHY */ + ADC_USER_PLAT = 1U, /**< Internal user ID for PLAT */ + ADC_USER_APP = 2U, /**< user ID for APP */ + ADC_USER_MAX /**< Total number of users for one channel */ +} AdcUser_t; + + +/** + \brief Defines callback function prototype. + Callback function will be called in ADC interrupt service routine after sample completes + \param result ADC sample result + */ +typedef void (*adcCallback_t)(uint32_t result); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \name ADC Configuration */ +/** \{ */ + +/** + \fn void ADC_getDefaultConfig(AdcConfig_t *config) + \brief Gets the ADC default configuartion. + This function sets the configuration structure to default values as below: + \code + config->clockDivider = ADC_CLOCK_DIV_4; + config->channalConfig.aioResDiv = ADC_AIO_RESDIV_BYPASS; // Note: channelConfig field is union + \endcode + + \param[in] config Pointer to ADC configuration structure + */ +void ADC_getDefaultConfig(AdcConfig_t *config); + +/** + \fn int32_t ADC_channelInit(AdcChannel_e channel, const AdcConfig_t *config, adcCallback_t callback) + \brief Initialize ADC specific channel + \param[in] channel ADC physical channel to be configured + \param[in] userID user ID of specific channel, customer user is assigned with ADC_USER_APP, used to compose logical channel combining with channel parameter + \param[in] config Pointer to ADC configuration + \param[in] callback Function to be called when ADC conversion completes + \return 0 on success, -1 for parameter check error, -2 for AIO1 channel conflict(vref output has been enabled) + */ +int32_t ADC_channelInit(AdcChannel_e channel, AdcUser_t userID, const AdcConfig_t *config, adcCallback_t callback); + +/** + \fn void ADC_channelDeInit(AdcChannel_e channel) + \brief Deinitialize ADC channel + \param[in] channel physical channel to be de-initialized, configuration of specific logical channel is invalid after this API call. + \param[in] userID user ID of specific channel, customer user is assigned with ADC_USER_APP, used to compose logical channel combining with channel parameter + */ +void ADC_channelDeInit(AdcChannel_e channel, AdcUser_t userID); + +/** + \fn void ADC_startConversion(uint32_t channels) + \brief Starts ADC conversion. Conversion is performed imediately when ADC is free, otherwise, the start request is put into a request queue and will be serviced later. + + \param[in] channel ADC physical channel to converse + \param[in] userID user ID of specific channel, customer user is assigned with ADC_USER_APP, used to compose logical channel combining with channel parameter + \return 0 on success, -1 if request queue is full, -2 if channel has not been initialized yet + */ +int32_t ADC_startConversion(AdcChannel_e channel, AdcUser_t userID); + +/** + \fn int32_t ADC_enableVrefOutput(void) + \brief Enable vref output through AIO1 + \return 0 on success, -2 for AIO1 channel conflict(AIO1 input has been enabled) + \note this feature and AIO1 input is mutual exclusive + */ +int32_t ADC_enableVrefOutput(void); + +/** + \fn void ADC_disableVrefOutput(void) + \brief Disable vref output through AIO1 + */ +void ADC_disableVrefOutput(void); + +/** \} */ + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ADC_EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/alarm.h b/PLAT/driver/chip/ec618/ap/inc/alarm.h new file mode 100644 index 0000000..3c0a5a2 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/alarm.h @@ -0,0 +1,117 @@ + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: alarm.h +* +* Description: header of alarm.c, hw config for hal_alarm +* +* History: 2021.05.12 initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ +#ifndef CHIP_ALARM_H +#define CHIP_ALARM_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** +* @brief alarmVBatHwInit +* @details configure and start vbat alarm +* +* @param voltThd100: set the threshold +* @return null +*/ +void alarmVBatHwInit(uint16_t voltThd100); +/** +* @brief alarmThmHwInit +* @details configure and start themral alarm +* +* @param thmThd: set the threshold +* @param range: set the hysteresis range +* @return null +*/ +void alarmThmHwInit(uint8_t thmThd, uint8_t range); +/** +* @brief alarmVBatHwDeinit +* @details stop vbat alarm + +* @return null +*/ +void alarmVBatHwDeinit(void); +/** +* @brief alarmThmHwDeinit +* @details stop thermal alarm + +* @return null +*/ +void alarmThmHwDeinit(void); +/** +* @brief alarmVBatGetIntIndicate +* @details stop thermal alarm + +* @return 1: high 0: low +*/ +uint8_t alarmVBatGetIntIndicate(void); +/** +* @brief alarmThmGetIntIndicate +* @details stop thermal alarm + +* @return 1: high 0: low +*/ +uint8_t alarmThmGetIntIndicate(void); +/** +* @brief alarmThmDisableInAdc +* @details stop thermal alarm, call in auxadc when sample the thm channel + +* @return 1: disable operation down 0: do nothing +*/ +bool alarmThmDisableInAdc(void); +/** +* @brief alarmThmEnableInAdc +* @details restart thermal alarm, call in auxadc when sample the thm channel + +* @return 1: enable operation down 0: do nothing +*/ +bool alarmThmEnableInAdc(void); + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/PLAT/driver/chip/ec618/ap/inc/apmu2Peripheral.h b/PLAT/driver/chip/ec618/ap/inc/apmu2Peripheral.h new file mode 100644 index 0000000..7f26ccd --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/apmu2Peripheral.h @@ -0,0 +1,34 @@ + +#ifndef _APMU_PERIPHERAL_ +#define _APMU_PERIPHERAL_ + +#include +#include + +void apmuPeriUsbEnterStartProc(bool forceCfgPwrDown); + +void apmuPeriUsbEnterAbortProc(bool forceCfgPwrDown); + +void apmuPeriUsbSusp2VbusTblGuardDlyChk(uint32_t cur_tick); + +void apmuPeriUsbSusp2HibGuardDlyChk(uint32_t cur_tick); + +void apmuPeriUsbSleep1LateRecoverFlow(bool sleepSuccess); + +void apmuPeriUsbSleep1PreRecoverFlow(bool sleepSuccess); + +bool apmuPeriLpuartPreSleepProcess(void); + +bool apmuPeriLpuartIsRxActive(void); + +void apmuPeriStartWFITimer(uint32_t ms); + +void apmuPeriDeleteWFITimer(void); + +void apmuPeriDeleteCPTimer(void); + +void apmuPeriClearCPTimerInterrupt(void); + +void apmuPeriStartCPTimer(uint32_t cpStartTime, void* expFunc); + +#endif diff --git a/PLAT/driver/chip/ec618/ap/inc/cache.h b/PLAT/driver/chip/ec618/ap/inc/cache.h new file mode 100644 index 0000000..6c602a4 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/cache.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: cache.h + * Description: EC618 cache controller driver header file + * History: Rev1.0 2018-07-12 + * + ****************************************************************************/ + +#ifndef _CACHE_EC618_H +#define _CACHE_EC618_H +#include "Driver_Common.h" + + /** + \addtogroup icache_interface_gr + \{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \fn void EnableICache(void) + \brief Enables Instrution cache + \return void + */ +void EnableICache(void); +/** + \fn void DisableICache(void) + \brief Disables Instrution cache + \return void + */ +void DisableICache(void); +/** + \fn bool IsICacheEnabled(void) + \brief Check whether cache is enabled + \return enabled or not + */ +bool IsICacheEnabled(void); + + /** \}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _CACHE_EC618_H */ + diff --git a/PLAT/driver/chip/ec618/ap/inc/charge.h b/PLAT/driver/chip/ec618/ap/inc/charge.h new file mode 100644 index 0000000..9755161 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/charge.h @@ -0,0 +1,87 @@ + + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: charge.h +* +* Description: header of charge.c. api for charge status detect +* +* History: 2021.05.07 initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ + +#ifndef CHARGE_H +#define CHARGE_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ +typedef enum +{ + CHARGE_STATUS_DISCONNECT = 0, + CHARGE_STATUS_CHARGING = 1, + CHARGE_STATUS_FINISH = 2, +}chargeStatus_e; + +typedef void(* chargeStatusCb)(chargeStatus_e status); + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** +* @brief chargeGetCurStatus +* @details Get current charge status +* +* @return charge status: + CHARGE_STATUS_DISCONNECT = 0, + CHARGE_STATUS_CHARGING = 1, + CHARGE_STATUS_FINISH = 2, +*/ +chargeStatus_e chargeGetCurStatus(void); +/** +* @brief chargeHwInit +* @details init hardware +* +* @return null +*/ +void chargeHwInit(void); +/** +* @brief chargeHwDeinit +* @details deinit hardware +* +* @return null +*/ +void chargeHwDeinit(void); + + + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/PLAT/driver/chip/ec618/ap/inc/clock.h b/PLAT/driver/chip/ec618/ap/inc/clock.h new file mode 100644 index 0000000..1608b6c --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/clock.h @@ -0,0 +1,509 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: clock.h + * Description: EC618 clock driver header file + * History: Rev1.0 2019-02-20 + * + ****************************************************************************/ + +#ifndef _CLOCK_EC618_H +#define _CLOCK_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + + +/** + \addtogroup clock_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef __CLOCK_DECLARATION_DEFINED__ +#define __CLOCK_DECLARATION_DEFINED__ + +#include "gpr_common.h" + +typedef enum +{ + /* clock ID with clock source select start */ + CLK_CC = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 0), + CLK_APB_MP = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 1), + CLK_APB_XP = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 2), + CLK_SMP = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 3), + CLK_SYSTICK = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 4), + + FCLK_UART0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 0, 5), + FCLK_UART1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 1, 6), + FCLK_UART2 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 2, 7), + FCLK_SPI0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 3, 8), + FCLK_SPI1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 4, 9), + FCLK_I2S0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 5, 10), + FCLK_I2S1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_FCLK_EN_REG_INDEX, 6, 11), + + FCLK_WDG = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 0, 12), + FCLK_TIMER0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 1, 13), + FCLK_TIMER1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 2, 14), + FCLK_TIMER2 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 3, 15), + FCLK_TIMER3 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 4, 16), + FCLK_TIMER4 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 5, 17), + FCLK_TIMER5 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 6, 18), + FCLK_I2C0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 7, 19), + FCLK_I2C1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 8, 20), + FCLK_USIM0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 9, 21), + FCLK_USIM1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 10, 22), + FCLK_KPC = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_FCLK_EN_REG_INDEX, 11, 23), + + CLK_FLASH = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 9, 24), + CLK_PSRAM = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 10, 25), + + CLK_CLKCAL = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_AP_CLKEN_REG_INDEX, 5, 26), + + /* clock ID with clock source select end */ + + /* root clock */ + CLK_MF = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 27), + CLK_32K = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 28), + CLK_HF408M = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 29), + + CLK_HF204M = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 0, 30), + CLK_HF102M = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 1, 31), + CLK_HF51M = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 2, 32), + CLK_32K_GATED = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 3, 33), + CLK_MF_GATED = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 4, 34), + CLK_CC_MP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 5, 35), + CLK_CC_AP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 6, 36), + CLK_CC_CP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 7, 37), + CLK_AON = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 8, 38), + + CLK_SMP_MP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 11, 39), + + MFAB_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 16, 40), + AFBBR_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 17, 41), + + MSMB_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 19, 42), + FLASH_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 20, 43), + PSRAM_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 21, 44), + ULOG_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 22, 45), + UTFC_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 23, 46), + ULDP_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 24, 47), + + USBC_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 26, 48), + USBC_PMU_HCLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 27, 49), + USBC_REF_CLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 28, 50), + USBP_REF_CLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 29, 51), + USBC_UTMI_CLK = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_MP_CLKEN_REG_INDEX, 30, 52), + + + CLK_DAP_AP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_AP_CLKEN_REG_INDEX, 0, 53), + CLK_TRACE_AP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_AP_CLKEN_REG_INDEX, 1, 54), + CLK_SYSTICK_AP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_AP_CLKEN_REG_INDEX, 2, 55), + CLK_APB_AP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_AP_CLKEN_REG_INDEX, 3, 56), + CLK_SMP_AP = CONSTRUCT_CLOCK_ID(APB_GPR_TOP_AP_CLKEN_REG_INDEX, 4, 57), + + PCLK_SIPC = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 1, 58), + PCLK_AON = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 2, 59), + PCLK_CPMU = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 3, 60), + PCLK_PMDIG = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 4, 61), + PCLK_RFDIG = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 5, 62), + PCLK_PAD = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 6, 63), + PCLK_GPIO = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 7, 64), + PCLK_FUSE = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 8, 65), + PCLK_TRNG = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 9, 66), + PCLK_USBP = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 10, 67), + PCLK_LPUC = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 11, 68), + PCLK_UART0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 12, 69), + PCLK_UART1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 13, 70), + PCLK_UART2 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 14, 71), + PCLK_SPI0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 15, 72), + PCLK_SPI1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 16, 73), + PCLK_I2S0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 17, 74), + PCLK_I2S1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_MP_PCLK_EN_REG_INDEX, 18, 75), + + + PCLK_WDG = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 0, 76), + PCLK_TIMER0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 1, 77), + PCLK_TIMER1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 2, 78), + PCLK_TIMER2 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 3, 79), + PCLK_TIMER3 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 4, 80), + PCLK_TIMER4 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 5, 81), + PCLK_TIMER5 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 6, 82), + PCLK_IPC = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 7, 83), + PCLK_I2C0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 8, 84), + PCLK_I2C1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 9, 85), + PCLK_USIM0 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 10, 86), + PCLK_USIM1 = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 11, 87), + PCLK_KPC = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 12, 88), + PCLK_ONEW = CONSTRUCT_CLOCK_ID(APB_GPR_APB_AP_PCLK_EN_REG_INDEX, 13, 89), + + + TOP_PBRG_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_TOP_CLKEN_REG_INDEX, 0, 90), + TOP_PBRG_PCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_TOP_CLKEN_REG_INDEX, 1, 91), + TOP_GPR_PCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_TOP_CLKEN_REG_INDEX, 2, 92), + + TRACE_CLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 1, 93), + ETM_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 2, 94), + ROMTABLE_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 3, 95), + TPIU_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 4, 96), + CACHE_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 5, 97), + FABSUB_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 6, 98), + SBU_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 7, 99), + PBRG_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 8, 100), + SPIS_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 9, 101), + XIC_RMI_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 10, 102), + ULOG_RMI_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 11, 103), + TMU_RMI_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 12, 104), + SCT_RMI_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 13, 105), + + UTFC_RMI_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 16, 106), + ULDP_RMI_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 17, 107), + SCT_HCLK = CONSTRUCT_CLOCK_ID(RMI_GPR_XPSYS_CLKEN_REG_INDEX, 18, 108), + + INVALID_CLK = CONSTRUCT_CLOCK_ID(CLKEN_REG_INDEX_MAX, 0, 109) +} ClockId_e; + + +/** \brief List of all configurable module's functional clock sources */ +typedef enum +{ + // top clk sel + + /** Core clock sourced from 26M */ + CLK_CC_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_CC), 0, CLK_MF), + /** Core clock sourced from 204M */ + CLK_CC_SEL_204M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_CC), 1, CLK_HF204M), + /** Core clock sourced from 102M */ + CLK_CC_SEL_102M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_CC), 2, CLK_HF102M), + /** Core clock sourced from 32K */ + CLK_CC_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_CC), 3, CLK_32K), + + + /** APB MP clock sourced from 26M */ + CLK_APB_MP_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_APB_MP), 0, CLK_MF), + /** APB MP clock sourced from 51M */ + CLK_APB_MP_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_APB_MP), 1U, CLK_HF51M), + + /** APB XP clock sourced from 26M */ + CLK_APB_XP_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_APB_XP), 0, CLK_MF), + /** APB XP sourced from 51M */ + CLK_APB_XP_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_APB_XP), 1U, CLK_HF51M), + + /** Systick clock sourced from 32K */ + CLK_SYSTICK_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_SYSTICK), 0, CLK_32K), + /** Systick clock sourced from 26M */ + CLK_SYSTICK_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(CLK_SYSTICK), 1U, CLK_MF), + + // apb mp func clk sel + + /** UART0 clock sourced from 26M */ + FCLK_UART0_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_UART0), 0, CLK_MF_GATED), + /** UART0 clock sourced from 51M */ + FCLK_UART0_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_UART0), 1U, CLK_HF51M), + + /** UART1 clock sourced from 26M */ + FCLK_UART1_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_UART1), 0, CLK_MF_GATED), + /** UART1 clock sourced from 51M */ + FCLK_UART1_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_UART1), 1U, CLK_HF51M), + + /** UART2 clock sourced from 26M */ + FCLK_UART2_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_UART2), 0, CLK_MF_GATED), + /** UART2 clock sourced from 51M */ + FCLK_UART2_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_UART2), 1U, CLK_HF51M), + + /** SPI0 clock sourced from 26M */ + FCLK_SPI0_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_SPI0), 0, CLK_MF_GATED), + /** SPI0 clock sourced from 51M */ + FCLK_SPI0_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_SPI0), 1U, CLK_HF51M), + + /** SPI1 clock sourced from 26M */ + FCLK_SPI1_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_SPI1), 0, CLK_MF_GATED), + /** SPI1 clock sourced from 51M */ + FCLK_SPI1_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_SPI1), 1U, CLK_HF51M), + + /** I2S0 clock sourced from 26M */ + FCLK_I2S0_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2S0), 0, CLK_MF_GATED), + /** I2S0 clock sourced from 51M */ + FCLK_I2S0_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2S0), 1U, CLK_HF51M), + + /** I2S1 clock sourced from 26M */ + FCLK_I2S1_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2S1), 0, CLK_MF_GATED), + /** I2S1 clock sourced from 51M */ + FCLK_I2S1_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2S1), 1U, CLK_HF51M), + + // apb ap func clk sel + + /** WDG clock sourced from 32K */ + FCLK_WDG_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_WDG), 0, CLK_32K_GATED), + /** WDG clock sourced from 26M */ + FCLK_WDG_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_WDG), 1U, CLK_MF_GATED), + + /** TIMER0 clock sourced from 32K */ + FCLK_TIMER0_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER0), 0, CLK_32K_GATED), + /** TIMER0 clock sourced from 26M */ + FCLK_TIMER0_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER0), 1U, CLK_MF_GATED), + + /** TIMER1 clock sourced from 32K */ + FCLK_TIMER1_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER1), 0, CLK_32K_GATED), + /** TIMER1 clock sourced from 26M */ + FCLK_TIMER1_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER1), 1U, CLK_MF_GATED), + + /** TIMER2 clock sourced from 32K */ + FCLK_TIMER2_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER2), 0, CLK_32K_GATED), + /** TIMER2 clock sourced from 26M */ + FCLK_TIMER2_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER2), 1U, CLK_MF_GATED), + + /** TIMER3 clock sourced from 32K */ + FCLK_TIMER3_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER3), 0, CLK_32K_GATED), + /** TIMER3 clock sourced from 26M */ + FCLK_TIMER3_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER3), 1U, CLK_MF_GATED), + + /** TIMER4 clock sourced from 32K */ + FCLK_TIMER4_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER4), 0, CLK_32K_GATED), + /** TIMER4 clock sourced from 26M */ + FCLK_TIMER4_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER4), 1U, CLK_MF_GATED), + + /** TIMER5 clock sourced from 32K */ + FCLK_TIMER5_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER5), 0, CLK_32K_GATED), + /** TIMER5 clock sourced from 26M */ + FCLK_TIMER5_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER5), 1U, CLK_MF_GATED), + + /** I2C0 clock sourced from 26M */ + FCLK_I2C0_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2C0), 0, CLK_MF_GATED), + /** I2C0 clock sourced from 51M */ + FCLK_I2C0_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2C0), 1U, CLK_HF51M), + + /** I2C1 clock sourced from 26M */ + FCLK_I2C1_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2C1), 0, CLK_MF_GATED), + /** I2C1 clock sourced from 51M */ + FCLK_I2C1_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_I2C1), 1U, CLK_HF51M), + + /** USIM0 clock sourced from 26M */ + FCLK_USIM0_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_USIM0), 0, CLK_MF_GATED), + /** USIM0 clock sourced from 51M */ + FCLK_USIM0_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_USIM0), 1U, CLK_HF51M), + + /** USIM1 clock sourced from 26M */ + FCLK_USIM1_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_USIM1), 0, CLK_MF_GATED), + /** USIM1 clock sourced from 51M */ + FCLK_USIM1_SEL_51M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_USIM1), 1U, CLK_HF51M), + + /** KPC clock sourced from 26M */ + FCLK_KPC_SEL_32K = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_KPC), 0, CLK_32K_GATED), + /** KPC clock sourced from 51M */ + FCLK_KPC_SEL_26M = MAKE_CLOCK_SEL_VALUE(GET_INDEX_FROM_CLOCK_ID(FCLK_KPC), 1U, CLK_MF_GATED), + +} ClockSelect_e; + + +#endif //__CLOCK_DECLARATION_DEFINED__ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + + +/** \name Clock Configuration */ +/* \{ */ + +/** + \fn int32_t CLOCK_clockEnable(ClockId_e id) + \brief Enable clock for selected module + \param[in] id clock item to enable + \return ARM_DRIVER_OK if the setting is successful + ARM_DRIVER_ERROR_PARAMETER on parameter check failure(setting is not available for specified clock id) + */ +int32_t CLOCK_clockEnable(ClockId_e id); + +/** + \fn void CLOCK_clockReset(ClockId_e id) + \brief Reset clock for selected module + \param[in] id clock item to reset + */ +void CLOCK_clockReset(ClockId_e id); + +/** + \fn void CLOCK_updateClockTreeElement(ClockId_e id, ClockId_e parentId, uint8_t enableCount) + \brief Update clock tree node item value, interrnal used only + \param[in] id clock item to update + \param[in] parentId parent clock id + \param[in] enableCount new enable count + */ +void CLOCK_updateClockTreeElement(ClockId_e id, ClockId_e parentId, uint8_t enableCount); + +/** + \fn void CLOCK_clockDisable(ClockId_e id) + \brief Disable clock for selected module + \param[in] id clock item to disable + */ +void CLOCK_clockDisable(ClockId_e id); + +/** + \fn int32_t CLOCK_setClockSrc(ClockId_e id, ClockSelect_e select) + \brief Set clock source for selected module + \param[in] id clock item to set + \param[in] select select one of clock sources \ref ClockSelect_e + \return ARM_DRIVER_OK if the setting is successful + ARM_DRIVER_ERROR_PARAMETER on parameter check failure(setting is not available for specified clock id) + ARM_DRIVER_ERROR if specific clock has been enabled + */ +int32_t CLOCK_setClockSrc(ClockId_e id, ClockSelect_e select); + +/** + \fn int32_t CLOCK_setClockDiv(ClockId_e id, uint32 div) + \brief Set clock divider for selected module + \param[in] id clock item to set + \param[in] div divider value + \return ARM_DRIVER_OK if the setting is successful + ARM_DRIVER_ERROR_PARAMETER on parameter check failure(setting is not available for specified clock id or div value is set to 0) + ARM_DRIVER_ERROR if specific clock has been enabled + */ +int32_t CLOCK_setClockDiv(ClockId_e id, uint32_t div); + +/** + \fn uint32_t CLOCK_getClockFreq(ClockId_e id) + \brief Get clock frequency for selected module + \param[in] id clock item to get + \return clock frequency in unit of HZ + */ +uint32_t CLOCK_getClockFreq(ClockId_e id); + +/** + \fn int32_t CLOCK_setFracDivConfig(FracDivConfig_t * config) + \brief fracdiv clock config + \param[in] config pointer to fracdiv setting + \return ARM_DRIVER_OK if the setting is successful + ARM_DRIVER_ERROR_PARAMETER on parameter check failure + */ +int32_t CLOCK_setFracDivConfig(FracDivConfig_t * config); + +/** + \fn void CLOCK_fracDivOutCLkEnable(FracDivOutClkId_e id) + \brief fracdiv out clock enable + \param[in] id fracdiv out clock id + */ +void CLOCK_fracDivOutCLkEnable(FracDivOutClkId_e id); + +/** + \fn void CLOCK_fracDivOutClkDisable(FracDivOutClkId_e id) + \brief fracdiv out clock disable + \param[in] id fracdiv out clock id + */ +void CLOCK_fracDivOutClkDisable(FracDivOutClkId_e id); + +/** + \fn void CLOCK_setFracDivOutClkDiv(FracDivOutClkId_e id, uint8_t div) + \brief set fracdiv out clock divider + \param[in] id fracdiv out clock id + \param[in] div divider ratio to set + */ +void CLOCK_setFracDivOutClkDiv(FracDivOutClkId_e id, uint8_t div); + +/** + \fn void CLOCK_setBclkSrc(BclkId_e id, BclkSrc_e src) + \brief select bclk source + \param[in] id bclk id + \param[in] src clock source to set + */ +void CLOCK_setBclkSrc(BclkId_e id, BclkSrc_e src); + +/** + \fn void CLOCK_setBclkDiv(BclkId_e id, uint8_t div) + \brief set bclk divider + \param[in] id bclk id + \param[in] div divider ratio to set + */ +void CLOCK_setBclkDiv(BclkId_e id, uint8_t div); + +/** + \fn void CLOCK_bclkEnable(BclkId_e id) + \brief enable bclk + \param[in] id bclk id + */ +void CLOCK_bclkEnable(BclkId_e id); + + +/** + \fn void CLOCK_setMclkSrc(MclkId_e id, MclkSrc_e src) + \brief select mclk source + \param[in] id mclk id + \param[in] src clock source to set + */ +void CLOCK_setMclkSrc(MclkId_e id, MclkSrc_e src); + +/** + \fn void CLOCK_mclkEnable(MclkId_e id) + \brief mclk enable + \param[in] id mclk id + */ +void CLOCK_mclkEnable(MclkId_e id); + +/** + \fn void CLOCK_mclkDisable(MclkId_e id) + \brief mclk disable + \param[in] id mclk id + */ +void CLOCK_mclkDisable(MclkId_e id); + +/** + \fn void CLOCK_setMclkDiv(MclkId_e id, uint8_t div) + \brief set mclk divider + \param[in] id mclk id + \param[in] div divider ratio to set + */ +void CLOCK_setMclkDiv(MclkId_e id, uint8_t div); +/** \} */ + +/** \name HAL Driver declaration */ +/* \{ */ + +extern int32_t GPR_setClockSrc(ClockId_e id, ClockSelect_e select); +extern int32_t GPR_setClockDiv(ClockId_e id, uint32_t div); +extern void GPR_clockEnable(ClockId_e id); +extern void GPR_clockDisable(ClockId_e id); +extern uint32_t GPR_getClockFreq(ClockId_e id); + +extern void GPR_setFracDivConfig(FracDivConfig_t * config); +extern void GPR_fracDivOutCLkEnable(FracDivOutClkId_e id); +extern void GPR_fracDivOutClkDisable(FracDivOutClkId_e id); +extern void GPR_setFracDivOutClkDiv(FracDivOutClkId_e id, uint8_t div); + +extern void GPR_setBclkSrc(BclkId_e id, BclkSrc_e src); +extern void GPR_setBclkDiv(BclkId_e id, uint8_t div); +extern void GPR_BclkEnable(BclkId_e id); + + +extern void GPR_setMclkSrc(MclkId_e id, MclkSrc_e src); +extern void GPR_mclkEnable(MclkId_e id); +extern void GPR_mclkDisable(MclkId_e id); +extern void GPR_setMclkDiv(MclkId_e id, uint8_t div); + +extern void GPR_swReset(ClockResetId_e id); +extern void GPR_swResetModule(const ClockResetVector_t *v); +extern void GPR_initialize(void); +extern void GPR_setApbGprAcg( void ); +extern void GPR_lockUpActionCtrl(bool enable); +extern uint32_t GPR_getCPLockUpResetCtrl(void); +extern ApRstSource_e GPR_apGetRstSrc(void); +extern CpRstSource_e GPR_cpGetRstSrc(void); +extern void GPR_cpResetCfgSet(bool wdtRstEn, bool sysRstApb, bool lockupRstEn, bool cpAPmuRst); +extern void GPR_setApbGprAcg( void ); +extern void GPR_bootSetting( void ); +void CLOCK_AssertChkBeforeSlp(void); + +/** \} */ + + +#ifdef __cplusplus +} +#endif + +/** \}*/ + +#endif diff --git a/PLAT/driver/chip/ec618/ap/inc/cpxip.h b/PLAT/driver/chip/ec618/ap/inc/cpxip.h new file mode 100644 index 0000000..7121945 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/cpxip.h @@ -0,0 +1,44 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename:cpxip.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#ifndef CP_XIP_H +#define CP_XIP_H + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ + +void CPXIP_Enable(void); +uint8_t CPXIP_QSPI_Erase_Sector(uint32_t SectorAddress); +uint8_t CPXIP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size); +uint8_t CPXIP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size); + + +#endif + diff --git a/PLAT/driver/chip/ec618/ap/inc/cspi.h b/PLAT/driver/chip/ec618/ap/inc/cspi.h new file mode 100644 index 0000000..4f82333 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/cspi.h @@ -0,0 +1,262 @@ +#ifndef BSP_CSPI_H +#define BSP_CSPI_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + +#define CSPI_TRANSFER_TRUNK_SIZE 7680 ///< Each DMA descriptor data size, fixed to 7680byte + + +typedef void (*cspiCbEvent_fn) (uint32_t event); ///< cspi callback event. + + +/** \brief CSPI flags */ +#define CSPI_FLAG_INITIALIZED (1UL << 0) ///< CSPI initialized +#define CSPI_FLAG_POWERED (1UL << 1) ///< CSPI powered on + + +/** \brief CSPI DMA */ +typedef struct +{ + DmaInstance_e rxInstance; ///< Receive DMA instance number + int8_t rxCh; ///< Receive channel number + uint8_t rxReq; ///< Receive DMA request number + void (*rxCb)(uint32_t event); ///< Receive callback + DmaDescriptor_t *descriptor; ///< Rx descriptor +} cspiDma_t; + +// CSPI PINS +typedef const struct +{ + PIN *mclk; ///< Main clk Pin identifier + PIN *pclk; ///< Pixel clk Pin identifier + PIN *cs; ///< Cs Pin identifier + PIN *sdo0; ///< Din Pin identifier + PIN *sdo1; ///< Dout Pin identifier +} cspiPins_t; + +typedef struct +{ + uint8_t busy; ///< Transmitter/Receiver busy flag +} cspiRteStats_t; + +typedef enum +{ + CAM_8W = 10, ///< 8w use 10 dma descriptor chain + CAM_30W = 40, ///< 30w use 40 dma descriptor chain +}camResolution_e; + +typedef enum +{ + CAM_6_5_M = 0, ///< camera 6.5M HZ + CAM_13_M = 1, ///< camera 13M HZ + CAM_25_5_M = 2, ///< camera 25.5M HZ + CAM_24_M = 3, ///< camera 24M HZ + CAM_20_M = 4, ///< camera 20M HZ +}camFrequence_e; + + +// CSPI information (Run-time) +typedef struct +{ + cspiCbEvent_fn cbEvent; ///< Event callback + cspiRteStats_t status; ///< CSPI status flags + uint8_t flags; ///< CSPI driver flags + uint32_t busSpeed; ///< CSPI bus speed + uint8_t dataWidth; ///< CSPI data bits select in unit of byte + uint32_t targetAddr; ///< CSPI target address + camResolution_e resolution; ///< Camera resolution +} cspiInfo_t; + + +// SPI Resources definition +typedef struct +{ + CSPI_TypeDef *reg; ///< SPI register pointer + cspiPins_t pins; ///< SPI PINS configuration + cspiDma_t *dma; ///< SPI DMA configuration pointer + cspiInfo_t *info; ///< Run-Time Information +} cspiRes_t; + + +/** +\brief General power states +*/ +typedef enum +{ + CSPI_POWER_OFF, ///< Power off: no operation possible + CSPI_POWER_FULL ///< Power on: full operation at maximum performance +} cspiPowerState_e; + +typedef struct +{ + uint32_t slaveModeEn : 1; ///< Slave Mode Enable + uint32_t slotSize : 5; ///< Slot Size + uint32_t wordSize : 5; ///< Word Size + uint32_t alignMode : 1; ///< Align Mode + uint32_t endianMode : 1; ///< Endian Mode + uint32_t dataDly : 2; ///< Data Delay + uint32_t txPad : 2; ///< Tx padding + uint32_t rxSignExt : 1; ///< Rx Sign Entension + uint32_t txPack : 2; ///< Tx Pack + uint32_t rxPack : 2; ///< Rx Pack + uint32_t txFifoEndianMode : 1; ///< Tx Fifo Endian Mode + uint32_t rxFifoEndianMode : 1; ///< Rx Fifo Endian Mode +}cspiDataFmt_t; + +typedef struct +{ + uint32_t slotEn : 3; ///< Slot Enable + uint32_t slotNum : 8; ///< Slot Num +}cspiSlotCtrl_t; + +typedef struct +{ + uint32_t bclkPolarity : 1; ///< Bclk Polarity + uint32_t fsPolarity : 1; ///< Frame Synchronization Polarity + uint32_t fsWidth : 6; ///< Frame Synchronization Width +}cspiBclkFsCtrl_t; + +typedef struct +{ + uint32_t rxDmaReqEn : 1; ///< Rx Dma Req Enable + uint32_t txDmaReqEn : 1; ///< Tx Dma Req Enable + uint32_t rxDmaTimeOutEn : 1; ///< Rx Dma Timeout Enable + uint32_t dmaWorkWaitCycle : 5; ///< Dma Work Wait Cycle + uint32_t rxDmaBurstSizeSub1 : 4; ///< Rx Dma Burst Size subtract 1 + uint32_t txDmaBurstSizeSub1 : 4; ///< Tx Dma Burst Size subtract 1 + uint32_t rxDmaThreadHold : 4; ///< Rx Dma Threadhold + uint32_t txDmaThreadHold : 4; ///< Tx Dma Threadhold + uint32_t rxFifoFlush : 1; ///< Rx Fifo flush + uint32_t txFifoFlush : 1; ///< Tx Fifo flush +}cspiDmaCtrl_t; + +typedef struct +{ + uint32_t txUnderRunIntEn : 1; ///< Tx Underrun interrupt Enable + uint32_t txDmaErrIntEn : 1; ///< Tx Dma Err Interrupt Enable + uint32_t txDatIntEn : 1; ///< Tx Data Interrupt Enable + uint32_t rxOverFlowIntEn : 1; ///< Rx Overflow Interrupt Enable + uint32_t rxDmaErrIntEn : 1; ///< Rx Dma Err Interrupt Enable + uint32_t rxDatIntEn : 1; ///< Rx Data Interrupt Enable + uint32_t rxTimeOutIntEn : 1; ///< Rx Timeout Interrupt Enable + uint32_t fsErrIntEn : 1; ///< Frame Start Interrupt Enable + uint32_t frameStartIntEn : 1; ///< Frame End Interrupt Enable + uint32_t frameEndIntEn : 1; ///< Frame End Interrupt Enable + uint32_t cspiBusTimeOutIntEn : 1; ///< Not use + uint32_t txIntThreshHold : 4; ///< Tx Interrupt Threadhold + uint32_t rxIntThreshHold : 4; ///< Rx Interrupt Threadhold +}cspiIntCtrl_t; + +typedef struct +{ + uint32_t rxTimeOutCycle : 24; ///< Rx Timeout Cycle +}cspiTimeOutCycle_t; + + +typedef struct +{ + uint32_t txUnderRun : 1; ///< Tx Underrun + uint32_t txDmaErr : 1; ///< Tx Dma Err + uint32_t txDataRdy : 1; ///< Tx Data ready, readOnly + uint32_t rxOverFlow : 1; ///< Rx OverFlow + uint32_t rxDmaErr : 1; ///< Rx Dma Err + uint32_t rxDataRdy : 1; ///< Rx Data ready, readOnly + uint32_t rxFifoTimeOut : 1; ///< Rx Fifo timeout + uint32_t fsErr : 4; ///< Frame synchronization Err + uint32_t frameStart : 1; ///< Frame start + uint32_t frameEnd : 1; ///< Frame end + uint32_t txFifoLevel : 6; ///< Tx Fifo Level, readOnly + uint32_t rxFifoLevel : 6; ///< Rx Fifo level, readOnly + uint32_t cspiBusTimeOut : 1; ///< Cspi Bus timeout +}cspiStats_t; + +typedef struct +{ + uint32_t enable : 1; ///< Enable + uint32_t csEn : 1; ///< CS signal check + uint32_t rxWid : 1; ///< Rx Width + uint32_t rxdSeq : 1; ///< Rx Sequence + uint32_t cpol : 1; ///< SPI polarity + uint32_t cpha : 1; ///< SPI phase + uint32_t frameProcEn : 1; ///< Frame Process Enable + uint32_t fillYonly : 1; ///< Fill Y Only + uint32_t hwInitEn : 1; ///< HW Init Enable + uint32_t lsCheckEn : 1; ///< Line Start Check Enable + uint32_t dpCheckEn : 1; ///< Data Pcket Check Enable + uint32_t frameProcInitEn : 1; ///< Frame Process Init Enable + uint32_t rowScaleRatio : 4; ///< Row Scale Ratio + uint32_t colScaleRatio : 4; ///< Column Scale Ratio + uint32_t scaleBytes : 2; ///< Scale Bytes +}cspiCtrl_t; + +typedef struct +{ + uint32_t autoCgEn : 1; ///< Auto Configure Enable +}cspiAutoCgCtrl_t; + +typedef struct +{ + uint32_t cspiBusTimeOutCycle : 24; ///< Cspi Bus Timeout Cycle + uint32_t dataId : 8; ///< Data Indication, readOnly +}cspiFrameInfo0_t; + + +typedef struct +{ + uint32_t cspiInit : 1; ///< Cspi Init +}cspiInit_t; + + + + + +/** +\brief Cspi control bits. +*/ +#define CSPI_CTRL_TRANSABORT (1UL << 0) ///< CSPI trans abort +#define CSPI_CTRL_BUS_SPEED (1UL << 1) ///< CSPI trans abort +#define CSPI_CTRL_DATA_BITS (1UL << 2) ///< CSPI trans abort +#define CSPI_CTRL_DATA_FORMAT (1UL << 3) ///< CSPI data format +#define CSPI_CTRL_SLOT_CTRL (1UL << 4) ///< CSPI slot ctrl +#define CSPI_CTRL_BCLK_FS_CTRL (1UL << 5) ///< CSPI bclk fs ctrl +#define CSPI_CTRL_DMA_CTRL (1UL << 6) ///< CSPI dma ctrl +#define CSPI_CTRL_INT_CTRL (1UL << 7) ///< CSPI int ctrl +#define CSPI_CTRL_TIMEOUT_CYCLE (1UL << 8) ///< CSPI timeout cycle +#define CSPI_CTRL_STATUS (1UL << 9) ///< CSPI status +#define CSPI_CTRL_CSPICTL (1UL << 10) ///< CSPI control +#define CSPI_CTRL_AUTO_CG_CTRL (1UL << 11) ///< CSPI auto cg ctrl +#define CSPI_CTRL_FRAME_INFO0 (1UL << 12) ///< CSPI frame info0 +#define CSPI_CTRL_INIT (1UL << 13) ///< CSPI init +#define CSPI_CTRL_RXTOR (1UL << 14) ///< CSPI rx timeout cycle +#define CSPI_CTRL_MEM_ADDR (1UL << 15) ///< CSPI memory addr set +#define CSPI_CTRL_FLUSH_RX_FIFO (1UL << 16) ///< Flush rx fifo +#define CSPI_CTRL_START_STOP (1UL << 17) ///< Start or stop cspi +#define CSPI_CTRL_RESOLUTION_SET (1UL << 18) ///< Camera resolution set + + + +/** +\brief Access structure of the CSPI Driver. +*/ +typedef struct +{ + int32_t (*init) (cspiCbEvent_fn cb_event); ///< Initialize CSPI Interface. + int32_t (*deInit) (void); ///< De-initialize CSPI Interface. + int32_t (*powerCtrl) (cspiPowerState_e state); ///< Control CSPI Interface Power. + int32_t (*recv) (void); ///< Open dma to receive data. + int32_t (*ctrl) (uint32_t control, uint32_t arg); ///< Control CSPI Interface. +} const cspiDrvInterface_t; + + + +#ifdef __cplusplus +} +#endif +#endif + diff --git a/PLAT/driver/chip/ec618/ap/inc/dma.h b/PLAT/driver/chip/ec618/ap/inc/dma.h new file mode 100644 index 0000000..4c1dff9 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/dma.h @@ -0,0 +1,333 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: dma.h + * Description: EC618 dma controller driver header file + * History: Rev1.0 2018-08-08 + * + ****************************************************************************/ + +#ifndef _DMA_EC618_H +#define _DMA_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup dma_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief List of DMA source/target address increment control options */ +typedef enum +{ + DMA_ADDRESS_INCREMENT_NONE = 0, /**< Increment neither source or target address */ + DMA_ADDRESS_INCREMENT_SOURCE = 1U, /**< Increment source address */ + DMA_ADDRESS_INCREMENT_TARGET = 2U, /**< Increment target address */ + DMA_ADDRESS_INCREMENT_BOTH = 3U, /**< Increment both source and target address */ +} DmaAddressIncrement_e; + +/** \brief List of DMA flow control options */ +typedef enum +{ + DMA_FLOW_CONTROL_NONE = 0U, /**< No flow control */ + DMA_FLOW_CONTROL_SOURCE = 1U, /**< Only source */ + DMA_FLOW_CONTROL_TARGET = 2U, /**< Only target */ +} DmaFlowControl_e; + +/** \brief List of DMA transfer data width in peripheral involved case */ +typedef enum +{ + DMA_DATA_WIDTH_NO_USE = 0, /**< Data width is set to 0 in memory to memory transfer */ + DMA_DATA_WIDTH_ONE_BYTE = 1U, /**< Data widath is 1 byte in peripheral involved transfer */ + DMA_DATA_WIDTH_TWO_BYTES = 2U, /**< Data widath is 2 bytes in peripheral involved transfer */ + DMA_DATA_WIDTH_FOUR_BYTES = 3U, /**< Data widath is 4 bytes in peripheral involved transfer */ +} DmaDataWidth_e; + +/** \brief Maximum burst size of each data transfer */ +typedef enum +{ + DMA_BURST_4_BYTES = 0, /**< Burst size is set to reserved */ + DMA_BURST_8_BYTES = 1U, /**< Burst size is set to 8 bytes */ + DMA_BURST_16_BYTES = 2U, /**< Burst size is set to 16 bytes */ + DMA_BURST_32_BYTES = 3U, /**< Burst size is set to 32 bytes */ + DMA_BURST_64_BYTES = 4U, /**< Burst size is set to 64 bytes */ +} DmaBurstSize_e; + +/** \brief DMA transfer configuration structure */ +typedef struct +{ + void *sourceAddress; /**< Source address */ + void *targetAddress; /**< Target address */ + DmaFlowControl_e flowControl; /**< Flow control setting */ + DmaAddressIncrement_e addressIncrement; /**< Address increment setting */ + DmaDataWidth_e dataWidth; /**< Data width setting */ + DmaBurstSize_e burstSize; /**< Burst size setting */ + uint32_t totalLength; /**< Transfer length onetime, less than 8k bytes. In descriptor chain it means every transfer's size */ + } DmaTransferConfig_t; + +/** \brief DMA descriptor extra configuration structure for descriptor-chain mode */ +typedef struct +{ + void *nextDesriptorAddress; /**< Next descriptor address */ + bool stopDecriptorFetch; /**< Indicate whether this is the last descriptor */ + bool enableStartInterrupt; /**< Start interrupt control */ + bool enableEndInterrupt; /**< End interrupt control */ +} DmaExtraConfig_t; + +/** \brief DMA descriptor structure */ +typedef struct +{ + uint32_t DAR; /**< DMA Descriptor Address */ + uint32_t SAR; /**< DMA Source Address */ + uint32_t TAR; /**< DMA Target Address */ + uint32_t CMDR; /**< DMA Command */ +} DmaDescriptor_t; + +/** \brief List of DMA interrupt sources */ +typedef enum +{ + /** Stop interrupt enable, when enabled, interrupt is triggered after the channel stops */ + DMA_STOP_INTERRUPT_ENABLE = (1U << 29U), + /** EOR interrupt enable, when enabled, interrupt is triggered on End-Of-Receive condition */ + DMA_EOR_INTERRUPT_ENABLE = (1U << 28U), + /** Start interrupt enable, when enabled, interrupt is triggered as soon as descriptor is loaded, valid for descriptor-chain-mode */ + DMA_START_INTERRUPT_ENABLE = (1U << 22U), + /** End interrupt enable, when enabled, interrupt is triggered when transfer length decrements to 0 */ + DMA_END_INTERRUPT_ENABLE = (1U << 21U), +} DmaInterruptEnable_e; + +/** \brief List of DMA available intances */ +typedef enum +{ + DMA_INSTANCE_AP, + DMA_INSTANCE_MP, + DMA_INSTANCE_MAX, +} DmaInstance_e; + +/** DMA specific error codes */ +#define ARM_DMA_ERROR_CHANNEL_ALLOC (ARM_DRIVER_ERROR_SPECIFIC - 1) /**< No free channel any more */ +#define ARM_DMA_ERROR_CHANNEL_NOT_OPEN (ARM_DRIVER_ERROR_SPECIFIC - 2) /**< Specific channel not open */ +#define ARM_DMA_ERROR_CHANNEL_NOT_STOPPED (ARM_DRIVER_ERROR_SPECIFIC - 3) /**< Specific channel not stopped */ +#define ARM_DMA_ERROR_ADDRESS_NOT_ALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 4) /**< Address alignment check failure */ + + +/** List of events reported to application */ +#define DMA_EVENT_ERROR (1) /**< Bus error */ +#define DMA_EVENT_START (2) /**< Descriptor load successfully */ +#define DMA_EVENT_END (3) /**< Transaction end */ +#define DMA_EVENT_EOR (4) /**< Receive EOR signal */ +#define DMA_EVENT_STOP (5) /**< Channel has stopped */ + +/** + \brief Defines callback function prototype. + Callback function will be called in DMA interrupt service routine after a transaction is complete + \param event transaction event for the current transaction, application can get the tansaction + result from this paramter, available events: DMA_EVENT_ERROR, DMA_EVENT_START, DMA_EVENT_END, DMA_EVENT_EOR, DMA_EVENT_STOP + */ +typedef void (*dma_callback_t)(uint32_t event); + +/** \brief timeout value when stopping channel */ +#define DMA_STOP_TIMEOUT (5000U) + +/******************************************************************************* + * API + ******************************************************************************/ + + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \fn void DMA_init(DmaInstance_e instance) + \brief Intialize DMA hareware and internal used structure, call this function before any other DMA APIs + */ +void DMA_init(DmaInstance_e instance); + +/** \name DMA Channel operation API */ +/** \{ */ + +/** + \fn int32_t DMA_openChannel(DmaInstance_e instance) + \brief Opens a DMA channel + \return Channel on successful allocate + ARM_DMA_ERROR_CHANNEL_ALLOC when no free channel is found + \note Caller shall check the return code + */ +int32_t DMA_openChannel(DmaInstance_e instance); + +/** + \fn int32_t DMA_closeChannel(DmaInstance_e instance, uint32_t channel) + \brief Closes a DMA channel + \param[in] instance + \param[in] channel DMA channel number + \return ARM_DRIVER_OK if no error happens + ARM_DMA_ERROR_CHANNEL_NOT_OPEN when channel is not open + \note This API will call \ref DMA_stopChannel to stop channel first if channel is running before close + */ +int32_t DMA_closeChannel(DmaInstance_e instance, uint32_t channel); + +/** + \fn void DMA_startChannel(DmaInstance_e instance, uint32_t channel) + \brief Activates the DMA channel + \param[in] instance + \param[in] channel DMA channel number + */ +void DMA_startChannel(DmaInstance_e instance, uint32_t channel); + +/** + \fn int32_t DMA_stopChannel(uint32_t channel, bool waitForStop) + \brief Stops the DMA channel from running + \param[in] channel DMA channel number + \param[in] waitForStop whether to wait channel to fully stop or not + \return ARM_DRIVER_OK if stops successfully + ARM_DMA_ERROR_CHANNEL_NOT_STOPPED if channel fails to stop until timeout expires + \note staus and interrupt flags will be cleared in this function call + */ +int32_t DMA_stopChannel(DmaInstance_e instance, uint32_t channel, bool waitForStop); + +/** + \fn void DMA_resetChannel(uint32_t channel) + + \brief Put the DMA channel to reset state + \param[in] channel DMA channel number + \note Make sure DMA is stopped before calling this function + */ +void DMA_resetChannel(DmaInstance_e instance, uint32_t channel); + +/** + \fn void DMA_rigisterChannelCallback(uint32_t channel, dma_callback_t callback) + \brief Registers a DMA callback + \param[in] channel DMA channel number + \param[in] callback Given by the application and will be called in DMA interrupt service routine + */ +void DMA_rigisterChannelCallback(DmaInstance_e instance, uint32_t channel, dma_callback_t callback); + +/** + \fn void DMA_enableChannelInterrupts(uint32_t channel, uint32_t mask) + \brief Enables DMA interrupts + \param[in] channel DMA channel number + \param[in] mask Mask of interrupt source to be set, can be ORed by items list in \ref DmaInterruptEnable_e + \note In no-descriptor-fetch mode, all interrupt sources can be enabled by calling this API, however, in descritor-fetch + mode, only \ref DMA_STOP_INTERRUPT_ENABLE \ref DMA_EOR_INTERRUPT_ENABLE can be done by this function call, + the \ref DMA_START_INTERRUPT_ENABLE and \ref DMA_END_INTERRUPT_ENABLE is controlled by setting in \ref DmaExtraConfig_t respectively. + */ +void DMA_enableChannelInterrupts(DmaInstance_e instance, uint32_t channel, uint32_t mask); + +/** + \fn void DMA_disableChannelInterrupts(uint32_t channel, uint32_t mask) + \brief Disables DMA interrupts + \param[in] channel DMA channel number + \param[in] mask Mask of interrupt source to be disabled, can be ORed by items list in \ref DmaInterruptEnable_e + \note In no-descriptor-fetch mode, all interrupt sources can be disabled by calling this API, however, in descritor-fetch + mode, only \ref DMA_STOP_INTERRUPT_ENABLE \ref DMA_EOR_INTERRUPT_ENABLE can be done by this function call , + the \ref DMA_START_INTERRUPT_ENABLE and \ref DMA_END_INTERRUPT_ENABLE is controlled by setting in \ref DmaExtraConfig_t respectively. + */ +void DMA_disableChannelInterrupts(DmaInstance_e instance, uint32_t channel, uint32_t mask); + +/** + \fn uint32_t DMA_getEnabledInterrupts(uint32_t channel) + \brief Gets current enabled DMA channel interrupts + \param[in] channel DMA channel number + \return The logical OR of members of the enumeration \ref DmaInterruptEnable_e + */ +uint32_t DMA_getEnabledInterrupts(DmaInstance_e instance, uint32_t channel); + +/** + \fn uint32_t DMA_getChannelCount(uint32_t channel) + \brief Obtains courrent transferred data length of a transaction in unit of byte + \param[in] channel DMA channel number + \return Size of data has been transferred + \note In descritor-fetch mode, Start Interrupt shall be enabled by enableStartInterrupt setting in \ref DmaExtraConfig_t + so that driver can load total transfer number for calculation before transferring. + */ +uint32_t DMA_getChannelCount(DmaInstance_e instance, uint32_t channel); + +/** + \fn void DMA_setChannelRequestSource(uint32_t channel, DmaRequestSource_e request) + \brief Configures DMA request source + \param[in] channel DMA channel number + \param[in] request DMA request binded to this channel + */ +void DMA_setChannelRequestSource(DmaInstance_e instance, uint32_t channel, DmaRequestSource_e request); + +/** \} */ + +/** \name DMA register mode API */ +/** \{ */ + +/** + \fn void DMA_transferSetup(DmaInstance_e instance, uint32_t channel, const DmaTransferConfig_t* config) + \brief Setups DMA channel according to user's transfer configuration, usded for register mode + \param[in] instance + \param[in] channel DMA channel number + \param[in] config Pointer to transfer configuration + \note user configuration shall be retaining(global variable) for it will be used again after exit from low power + */ +void DMA_transferSetup(DmaInstance_e instance, uint32_t channel, const DmaTransferConfig_t* config); +/** \} */ + +/** \name DMA descriptor chain mode API */ +/** \{ */ + +/** + \fn void DMA_buildDescriptor(DmaDescriptor_t* descriptor, const DmaTransferConfig_t* config, const DmaExtraConfig_t* extraConfig) + \brief Builds a descritor for DMA mode use + \param[out] descriptor Pointer to DMA descriptor instance + \param[in] config Pointer to transfer configuration + \param[in] extraConfig Pointer to extra configuration which is invalid in descriptor-chain-mode only + \note descriptor shall be retaining(global variable) for it will be used again after exit from low power + */ + +void DMA_buildDescriptor(DmaDescriptor_t* descriptor, const DmaTransferConfig_t* config, const DmaExtraConfig_t* extraConfig); + +/** + \fn void DMA_buildDescriptorChain(DmaDescriptor_t* descriptorArray, const DmaTransferConfig_t* config, const uint16_t chainCnt) + \brief Builds a descritor for DMA chain mode use + \param[out] descriptorArray Pointer to DMA descriptor chain array, should aligned with 16byte + \param[in] config Pointer to transfer configuration + \param[in] chainCnt The count of descriptor chain + \param[in] needStop Need cycling transfer data or not + \note descriptor shall be retaining(global variable) for it will be used again after exit from low power + */ + +void DMA_buildDescriptorChain(DmaDescriptor_t* descriptorArray, const DmaTransferConfig_t* config, const uint16_t chainCnt, bool needStop); + +/** + \fn int32_t DMA_loadChannelFirstDescriptor(DmaInstance_e instance, uint32_t channel, void* descriptorAddress) + \brief Loads first descritor + \param[in] instance + \param[in] channel DMA channel number + \param[in] descriptorAddress Address of descriptor from which to load, shall be aligend on a 16-byte boundary in memory + \return ARM_DRIVER_OK if success + ARM_DMA_ERROR_ADDRESS_NOT_ALIGNED on address alignment check failure + */ +int32_t DMA_loadChannelFirstDescriptor(DmaInstance_e instance, uint32_t channel, void* descriptorAddress); + +/** + \fn void DMA_loadChannelDescriptorAndRun(DmaInstance_e instance, uint32_t channel, void* descriptorAddress) + \brief Loads first descritor and run + \param[in] instance + \param[in] channel DMA channel number + \param[in] descriptorAddress Address of descriptor from which to load, shall be aligend on a 16-byte boundary in memory + \return ARM_DRIVER_OK if success + ARM_DMA_ERROR_ADDRESS_NOT_ALIGNED on address alignment check failure + */ +void DMA_loadChannelDescriptorAndRun(DmaInstance_e instance, uint32_t channel, void* descriptorAddress); + + +/** \} */ + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/PLAT/driver/chip/ec618/ap/inc/ec618.h b/PLAT/driver/chip/ec618/ap/inc/ec618.h new file mode 100644 index 0000000..f14b422 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/ec618.h @@ -0,0 +1,3143 @@ +/** + ***************************************************************************** + * @brief Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for EC618 chip. + * + * @file ec618.h + * @author + * @date 12/Nov/2018 + ***************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * © COPYRIGHT 2018 AirM2M Technologies Ltd. + * + ***************************************************************************** + */ + +#ifndef EC618_H +#define EC618_H + +#ifdef __cplusplus + extern "C" { +#endif +#include "commontypedef.h" +//#include "ec618_addrComm.h" + + + +/* Start of section using anonymous unions and disabling warnings */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +//#include "AP_Arm_Common.h" +/** @addtogroup Interrupt_number_definiton Interrupt Number Definition + * @{ + */ + +#ifndef APIRQ_NUMBER_DEFINED +#define APIRQ_NUMBER_DEFINED + +typedef enum IRQn +{ + /* Cortex-M3 Processor Exceptions Numbers */ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + + /* ARMCM3 Specific Interrupt Numbers */ + PadWakeup0_IRQn = 0, /**< Pad Wakeup0 Interrupt */ + PadWakeup1_IRQn = 1, /**< Pad Wakeup1 Interrupt */ + PadWakeup2_IRQn = 2, /**< Pad Wakeup2 Interrupt */ + PadWakeup3_IRQn = 3, /**< Pad Wakeup3 Interrupt */ + PadWakeup4_IRQn = 4, /**< Pad Wakeup4 Interrupt */ + PadWakeup5_IRQn = 5, /**< Pad Wakeup5 Interrupt */ + LpuartWakeup_IRQn = 6, /**< Lpuart Wakeup Interrupt */ + LpusbWakeup_IRQn = 7, /**< Lpusb Wakeup Interrupt */ + PwrkeyWakeup_IRQn = 8, /**< Power Key Wakeup Interrupt */ + ChrgpadWakeup_IRQn = 9, /**< Charge Pad Wakeup Interrupt */ + RtcWakeup_IRQn = 10, /**< RTC Wakeup Interrupt */ + Usb_IRQn = 11, /**< USB Interrupt */ + APXIC0_Normal_IRQn = 12, /**< AP XIC0 Interrupt */ + APXIC1_Normal_IRQn = 13, /**< AP XIC1 Interrupt */ + APXIC2_Normal_IRQn = 14, /**< AP XIC2 Interrupt */ + APXIC3_Normal_IRQn = 15, /**< AP XIC3 Interrupt */ + + /* AP XIC0 for IPC/APB */ + PXIC0_OVF_IRQn = 32, /**< SW or HW Error Interrupt */ + PXIC0_PM_VBAT_LOW_IRQn = 33, /**< SW or HW Error Interrupt */ + PXIC0_I2S1_IRQn = 34, /**< I2S1 Interrupt */ + PXIC0_I2S0_IRQn = 35, /**< I2S0 Interrupt */ + PXIC0_SSP1_IRQn = 36, /**< SSP1 Interrupt */ + PXIC0_SSP0_IRQn = 37, /**< SSP0 Interrupt */ + PXIC0_UART2_IRQn = 38, /**< UART2 Interrupt */ + PXIC0_UART1_IRQn = 39, /**< UART1 Interrupt */ + PXIC0_UART0_IRQn = 40, /**< UART0 Interrupt */ + PXIC0_LPUC_IRQn = 41, /**< LPUC Interrupt */ + PXIC0_TIMER5_IRQn = 42, /**< TIMER5 Interrupt */ + PXIC0_TIMER4_IRQn = 43, /**< TIMER4 Interrupt */ + PXIC0_TIMER3_IRQn = 44, /**< TIMER3 Interrupt */ + PXIC0_TIMER2_IRQn = 45, /**< TIMER2 Interrupt */ + PXIC0_TIMER1_IRQn = 46, /**< TIMER1 Interrupt */ + PXIC0_TIMER0_IRQn = 47, /**< TIMER0 Interrupt */ + PXIC0_KPC_DIRECT_IRQn = 48, /**< KPC DIRECT Interrupt */ + PXIC0_KPC_KEYPAD_IRQn = 49, /**< KPC KEYPAD Interrupt */ + PXIC0_ONEW_IRQn = 50, /**< ONEW Interrupt */ + PXIC0_I2C1_IRQn = 51, /**< I2C1 Interrupt */ + PXIC0_I2C0_IRQn = 52, /**< I2C0 Interrupt */ + PXIC0_USIM1_IRQn = 53, /**< USIM1 Interrupt */ + PXIC0_USIM0_IRQn = 54, /**< USIM0 Interrupt */ + PXIC0_UTFC_ERR_IRQn = 55, /**< UTFC ERR Interrupt */ + PXIC0_RESV1_IRQn = 56, /**< RESV Interrupt */ + PXIC0_RESV2_IRQn = 57, /**< RESV Interrupt */ + PXIC0_RESV3_IRQn = 58, /**< RESV Interrupt */ + PXIC0_USB_IRQn = 59, /**< USB Interrupt */ + PXIC0_IPC_Merge_IRQn = 60, /**< IPC MERGE Interrupt */ + PXIC0_IPC_Alone1_IRQn = 61, /**< IPC ALONE1 Interrupt */ + PXIC0_IPC_Alone0_IRQn = 62, /**< IPC ALONE0 Interrupt */ + PXIC0_Sipc_IRQn = 63, /**< IPC SIPC Interrupt */ + + + /* AP XIC1 for APB/AHB */ + PXIC1_OVF_IRQn = 64, /**< SW or HW Error Interrupt */ + PXIC1_CPMU_SLEEP_END_IRQn = 65, /**< CPMU SLEEP END Interrupt */ + PXIC1_CPMU_WAKEUP_END_IRQn = 66, /**< CPMU WAKEUP END Interrupt */ + PXIC1_CPMU_ASSIST_REQ_IRQn = 67, /**< CPMU ASSIST REQ Interrupt */ + PXIC1_CP_CPU_RST_REQ_IRQn = 68, /**< CP CPU RST REQ Interrupt */ + PXIC1_SCT_CH0_IRQn = 69, /**< SCT CH0 Interrupt */ + PXIC1_SCT_CH1_IRQn = 70, /**< SCT CH1 Interrupt */ + PXIC1_SCT_CH2_IRQn = 71, /**< SCT CH2 Interrupt */ + PXIC1_SCT_CH3_IRQn = 72, /**< SCT CH3 Interrupt */ + PXIC1_SCT_CH4_IRQn = 73, /**< SCT CH4 Interrupt */ + PXIC1_SCT_CH5_IRQn = 74, /**< SCT CH5 Interrupt */ + PXIC1_SCT_ERR_IRQn = 75, /**< SCT ERR Interrupt */ + PXIC1_TMU_BASECNT_CP_RT_IRQn = 76, /**< TMU BASECNT CP RT Interrupt */ + PXIC1_TMU_BASECNT_CP_BC_IRQn = 77, /**< TMU BASECNT CP BC Interrupt */ + PXIC1_TMU_BASECNT_AP_BC_IRQn = 78, /**< TMU BASECNT AP BC Interrupt */ + PXIC1_TMU_BASECNT_BC_LD_IRQn = 79, /**< TMU BASECNT BC LD Interrupt */ + PXIC1_TMU_CALCAL_LTCH_IRQn = 80, /**< TMU CALCAL LTCH Interrupt */ + PXIC1_RFFE_CP_IRQn = 81, /**< RFFE CP Interrupt */ + PXIC1_FUSE_FAIL_IRQn = 82, /**< FUSE FAIL Interrupt */ + PXIC1_FUSE_BURN_IRQn = 83, /**< FUSE BURN Interrupt */ + PXIC1_FUSE_READ_IRQn = 84, /**< FUSE READ Interrupt */ + PXIC1_DMA_AP_IRQn = 85, /**< DMA AP Interrupt */ + PXIC1_DMA_CP_IRQn = 86, /**< DMA CP Interrupt */ + PXIC1_DMA_MP_IRQn = 87, /**< DMA MP Interrupt */ + PXIC1_GPIO_IRQn = 88, /**< GPIO Interrupt */ + PXIC1_TRNG_IRQn = 89, /**< TRNG Interrupt */ + PXIC1_PSRAM_IRQn = 90, /**< PSRAM Interrupt */ + PXIC1_FLASH_IRQn = 91, /**< FLASH Interrupt */ + PXIC1_ULOG_ERR_IRQn = 92, /**< ULOG ERR Interrupt */ + PXIC1_ULOG_IRQn = 93, /**< ULOG Interrupt */ + PXIC1_THM_HI_IRQn = 94, /**< THM HI Interrupt */ + PXIC1_AUXADC_IRQn = 95, /**< AUXADC Interrupt */ + +} IRQn_Type; + +#endif + +/** + * @} + */ /* end of group Interrupt_number_definiton */ + +/** @addtogroup Cortex_core_configuration Processor and Core Peripherals configuration + * @{ + */ + +#define __CM3_REV 0x0201U /**< Core revision r2p1 */ +#define __MPU_PRESENT 1U /**< MPU present */ +#define __VTOR_PRESENT 1U /**< VTOR present or not */ +#define __NVIC_PRIO_BITS 3U /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /**< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" + +#include "system_ec618.h" + +/** + * @} + */ /* end of group Cortex_core_configuration */ + +/** @addtogroup Device_peripheral_access Device Peripheral Access + * @{ + */ + + +/** @addtogroup BASE_ADDR Peripheral instance base addresses + * @{ + */ + +/** + * @brief AP XIC base address + * + */ +#define APXIC_BASE_ADDR ((unsigned int)0x40020000) + +#define APXIC0_BASE_ADDR (APXIC_BASE_ADDR+0x0000) /**< APXIC0(manage APB/IPC interrupt) base address */ +#define APXIC1_BASE_ADDR (APXIC_BASE_ADDR+0x1000) /**< APXIC1(manage AHB/APB interupt) base address */ +#define APXIC2_BASE_ADDR (APXIC_BASE_ADDR+0x2000) /**< APXIC2(manage ULDP interupt) base address */ +#define APXIC3_BASE_ADDR (APXIC_BASE_ADDR+0x3000) /**< APXIC3(manage USB interupt) base address */ + +/** + * @brief AP APB base address + * + */ +#define APB_AP_PERIPH_BASE ((unsigned int)0x4C000000) /**< APB AP peripheral base address */ +#define RMI_AP_PERIPH_BASE ((unsigned int)0x40000000) /**< RMI AP peripheral base address */ + +/** + * @brief CP APB base address + * + */ +#define APB_CP_PERIPH_BASE ((unsigned int)0x5C000000) /**< APB CP peripheral base address */ +#define RMI_CP_PERIPH_BASE ((unsigned int)0x50000000) /**< RMI CP peripheral base address */ + +/** + * @brief MP APB base address + * + */ +#define APB_MP_PERIPH_BASE ((unsigned int)0x4D000000) /**< APB MP peripheral base address */ + + + +/** + * @brief APB AP Address + * + */ +#define AP_WDG_BASE_ADDR (APB_AP_PERIPH_BASE + 0x010000) /**< AP WDG base address */ +#define AP_TIMER0_BASE_ADDR (APB_AP_PERIPH_BASE + 0x020000) /**< AP TIMER0 base address */ +#define AP_TIMER1_BASE_ADDR (APB_AP_PERIPH_BASE + 0x021000) /**< AP TIMER1 base address */ +#define AP_TIMER2_BASE_ADDR (APB_AP_PERIPH_BASE + 0x022000) /**< AP TIMER2 base address */ +#define AP_TIMER3_BASE_ADDR (APB_AP_PERIPH_BASE + 0x023000) /**< AP TIMER3 base address */ +#define AP_TIMER4_BASE_ADDR (APB_AP_PERIPH_BASE + 0x024000) /**< AP TIMER4 base address */ +#define AP_TIMER5_BASE_ADDR (APB_AP_PERIPH_BASE + 0x025000) /**< AP TIMER5 base address */ +#define AP_IPC_BASE_ADDR (APB_AP_PERIPH_BASE + 0x030000) /**< AP IPC base address */ +#define AP_I2C0_BASE_ADDR (APB_AP_PERIPH_BASE + 0x060000) /**< AP I2C0 base address */ +#define AP_I2C1_BASE_ADDR (APB_AP_PERIPH_BASE + 0x061000) /**< AP I2C1 base address */ +#define AP_USIM0_BASE_ADDR (APB_AP_PERIPH_BASE + 0x070000) /**< AP USIM0 base address */ +#define AP_USIM1_BASE_ADDR (APB_AP_PERIPH_BASE + 0x071000) /**< AP USIM1 base address */ +#define AP_KPC_BASE_ADDR (APB_AP_PERIPH_BASE + 0x080000) /**< AP KPC base address */ +#define AP_ONEWIRE_BASE_ADDR (APB_AP_PERIPH_BASE + 0x090000) /**< AP ONEWIRE base address */ + + + +/** + * @brief APB MP Address + * + */ +#define MP_GPR_BASE_ADDR (APB_MP_PERIPH_BASE + 0x000000) /**< MP GPR base address */ +#define MP_GPR_SC_BASE_ADDR (APB_MP_PERIPH_BASE + 0x000100) /**< MP GPR SC base address */ +#define MP_SIPC_BASE_ADDR (APB_MP_PERIPH_BASE + 0x010000) /**< MP SIPC base address */ +#define MP_AON_BASE_ADDR (APB_MP_PERIPH_BASE + 0x020000) /**< MP AON base address */ +#define MP_CPMU_BASE_ADDR (APB_MP_PERIPH_BASE + 0x030000) /**< MP CPMU base address */ +#define MP_PMDIG_BASE_ADDR (APB_MP_PERIPH_BASE + 0x040000) /**< MP RFDIG base address */ +#define MP_RFDIG_BASE_ADDR (APB_MP_PERIPH_BASE + 0x050000) /**< MP RFDIG base address */ +#define MP_PAD_BASE_ADDR (APB_MP_PERIPH_BASE + 0x060000) /**< MP PAD base address */ +#define MP_GPIO_BASE_ADDR (APB_MP_PERIPH_BASE + 0x070000) /**< MP GPIO base address */ +#define MP_FUSE_BASE_ADDR (APB_MP_PERIPH_BASE + 0x090000) /**< MP FUSE base address */ +#define MP_TRNG_BASE_ADDR (APB_MP_PERIPH_BASE + 0x0A0000) /**< MP TRNG base address */ +#define MP_USB_BASE_ADDR (APB_MP_PERIPH_BASE + 0x0B0000) /**< MP USB base address */ +#define MP_LPUART_BASE_ADDR (APB_MP_PERIPH_BASE + 0x100040) /**< MP LPUART base address */ +#define MP_UART0_BASE_ADDR (APB_MP_PERIPH_BASE + 0x110000) /**< MP UART0 base address */ +#define MP_UART1_BASE_ADDR (APB_MP_PERIPH_BASE + 0x111000) /**< MP UART1 base address */ +#define MP_UART2_BASE_ADDR (APB_MP_PERIPH_BASE + 0x112000) /**< MP UART2 base address */ +#define MP_SSP0_BASE_ADDR (APB_MP_PERIPH_BASE + 0x120000) /**< MP SSP0 base address */ +#define MP_SSP1_BASE_ADDR (APB_MP_PERIPH_BASE + 0x121000) /**< MP SSP1 base address */ +#define MP_I2S0_BASE_ADDR (APB_MP_PERIPH_BASE + 0x130000) /**< MP I2S0 base address */ +#define MP_I2S1_BASE_ADDR (APB_MP_PERIPH_BASE + 0x131000) /**< MP I2S1 base address */ +#define MP_DMA_BASE_ADDR (APB_MP_PERIPH_BASE + 0x1F0000) /**< MP DMA base address */ + +#define LPUSARTAON_BASE_ADDR (MP_AON_BASE_ADDR + 0x000154) /**< LPUSART AON base address */ + +/** + * @} + */ /* end of group BASE_ADDR */ + + +/** @addtogroup ADC ADC(Analog-to-Digital converter) + * @{ + */ + +/** + * @brief ADC register layout typedef + * + */ +typedef struct { + __IO uint32_t CTRL; /**< ADC control Register, offset: 0x0 */ + __IO uint32_t CFG; /**< ADC configuration Register, offset: 0x4 */ + __IO uint32_t AIOCFG; /**< AIO configuration Register, offset: 0x8 */ + __I uint32_t STATUS; /**< ADC status Register, offset: 0xC */ + __I uint32_t RESULT; /**< ADC data result Register, offset: 0x10 */ +} ADC_TypeDef; + +/** @name CTRL - ADC_CTRL register */ +/** @{ */ +#define ADC_CTRL_RSTN_Pos (0) +#define ADC_CTRL_RSTN_Msk (0x1UL << ADC_CTRL_RSTN_Pos) + +#define ADC_CTRL_EN_Pos (1) +#define ADC_CTRL_EN_Msk (0x1UL << ADC_CTRL_EN_Pos) + +#define ADC_CTRL_LDO_EN_Pos (2) +#define ADC_CTRL_LDO_EN_Msk (0x1UL << ADC_CTRL_LDO_EN_Pos) +/** @} */ + +/** @name CFG - ADC_CFG register */ +/** @{ */ +#define ADC_CFG_WAIT_CTRL_Pos (1) +#define ADC_CFG_WAIT_CTRL_Msk (0x3UL << ADC_CFG_WAIT_CTRL_Pos) + +#define ADC_CFG_OFFSET_CTRL_Pos (3) +#define ADC_CFG_OFFSET_CTRL_Msk (0x7UL << ADC_CFG_OFFSET_CTRL_Pos) + +#define ADC_CFG_SAMPLE_AVG_Pos (6) +#define ADC_CFG_SAMPLE_AVG_Msk (0x1UL << ADC_CFG_SAMPLE_AVG_Pos) + +#define ADC_CFG_CLKIN_DIV_Pos (7) +#define ADC_CFG_CLKIN_DIV_Msk (0x3UL << ADC_CFG_CLKIN_DIV_Pos) + +#define ADC_CFG_VREF_BS_Pos (9) +#define ADC_CFG_VREF_BS_Msk (0x1UL << ADC_CFG_VREF_BS_Pos) + +#define ADC_CFG_VREF_SEL_Pos (10) +#define ADC_CFG_VREF_SEL_Msk (0x7UL << ADC_CFG_VREF_SEL_Pos) + +#define ADC_CFG_LDO_SEL_Pos (13) +#define ADC_CFG_LDO_SEL_Msk (0x7UL << ADC_CFG_LDO_SEL_Pos) + +#define ADC_CFG_IBIAS_SEL_Pos (16) +#define ADC_CFG_IBIAS_SEL_Msk (0x3UL << ADC_CFG_IBIAS_SEL_Pos) +/** @} */ + +/** @name AIOCFG - ADC_AIOCFG register */ +/** @{ */ +#define ADC_AIOCFG_THM_SEL_Pos (0) +#define ADC_AIOCFG_THM_SEL_Msk (0x3UL << ADC_AIOCFG_THM_SEL_Pos) + +#define ADC_AIOCFG_VBATSEN_RDIV_Pos (2) +#define ADC_AIOCFG_VBATSEN_RDIV_Msk (0x7UL << ADC_AIOCFG_VBATSEN_RDIV_Pos) + +#define ADC_AIOCFG_RDIV_Pos (5) +#define ADC_AIOCFG_RDIV_Msk (0x7UL << ADC_AIOCFG_RDIV_Pos) + +#define ADC_AIOCFG_RDIV_BYP_Pos (8) +#define ADC_AIOCFG_RDIV_BYP_Msk (0x1UL << ADC_AIOCFG_RDIV_BYP_Pos) + +#define ADC_AIOCFG_THM_EN_Pos (9) +#define ADC_AIOCFG_THM_EN_Msk (0x1UL << ADC_AIOCFG_THM_EN_Pos) + +#define ADC_AIOCFG_BATSENS_EN_Pos (10) +#define ADC_AIOCFG_BATSENS_EN_Msk (0x1UL << ADC_AIOCFG_BATSENS_EN_Pos) + +#define ADC_AIOCFG_AIO4_EN_Pos (11) +#define ADC_AIOCFG_AIO4_EN_Msk (0x1UL << ADC_AIOCFG_AIO4_EN_Pos) + +#define ADC_AIOCFG_AIO3_EN_Pos (12) +#define ADC_AIOCFG_AIO3_EN_Msk (0x1UL << ADC_AIOCFG_AIO3_EN_Pos) + +#define ADC_AIOCFG_AIO2_EN_Pos (13) +#define ADC_AIOCFG_AIO2_EN_Msk (0x1UL << ADC_AIOCFG_AIO2_EN_Pos) + +#define ADC_AIOCFG_AIO1_EN_Pos (14) +#define ADC_AIOCFG_AIO1_EN_Msk (0x1UL << ADC_AIOCFG_AIO1_EN_Pos) + +#define ADC_AIOCFG_AIO4_NO_DIVR_EN_Pos (15) +#define ADC_AIOCFG_AIO4_NO_DIVR_EN_Msk (0x1UL << ADC_AIOCFG_AIO4_NO_DIVR_EN_Pos) + +#define ADC_AIOCFG_AIO3_NO_DIVR_EN_Pos (16) +#define ADC_AIOCFG_AIO3_NO_DIVR_EN_Msk (0x1UL << ADC_AIOCFG_AIO3_NO_DIVR_EN_Pos) + +#define ADC_AIOCFG_AIO2_NO_DIVR_EN_Pos (17) +#define ADC_AIOCFG_AIO2_NO_DIVR_EN_Msk (0x1UL << ADC_AIOCFG_AIO2_NO_DIVR_EN_Pos) + +#define ADC_AIOCFG_AIO1_NO_DIVR_EN_Pos (18) +#define ADC_AIOCFG_AIO1_NO_DIVR_EN_Msk (0x1UL << ADC_AIOCFG_AIO1_NO_DIVR_EN_Pos) + +#define ADC_AIOCFG_VREF2AIO1_EN_Pos (19) +#define ADC_AIOCFG_VREF2AIO1_EN_Msk (0x1UL << ADC_AIOCFG_VREF2AIO1_EN_Pos) +/** @} */ + +/** @name STATUS - ADC_STATUS register */ +/** @{ */ +#define ADC_STATUS_DATA_VALID_Pos (0) +#define ADC_STATUS_DATA_VALID_Msk (0x1UL << ADC_STATUS_DATA_VALID_Pos) +/** @} */ + +/** @name RESULT - ADC_RESULT register */ +/** @{ */ +#define ADC_RESULT_DATA_Pos (0) +#define ADC_RESULT_DATA_Msk (0xFFFUL << ADC_RESULT_DATA_Pos) +/** @} */ + +/** Peripheral ADC base pointer */ +#define ADC_BASE_ADDR (MP_RFDIG_BASE_ADDR + 0x600) +#define ADC ((ADC_TypeDef *)ADC_BASE_ADDR) + +/** + * @} + */ /* end of group ADC */ + + +/** @addtogroup GPIO GPIO + * @{ + */ + +/** + * @brief GPIO register layout typedef + * + */ +typedef struct { + __IO uint32_t DATA; /**< Data Input Register, offset: 0x0 */ + __IO uint32_t DATAOUT; /**< Data Output Register, offset: 0x4 */ + uint32_t RESERVED_0[2]; + __IO uint32_t OUTENSET; /**< Output Enable Set Register, offset: 0x10 */ + __IO uint32_t OUTENCLR; /**< Output Enable Clear Register, offset: 0x14 */ + uint32_t RESERVED_1[2]; + __IO uint32_t INTENSET; /**< Interrupt Enable Set Register, offset: 0x20 */ + __IO uint32_t INTENCLR; /**< Interrupt Enable Clear Register, offset: 0x24 */ + __IO uint32_t INTTYPESET; /**< Interrupt Type set Register, offset: 0x28 */ + __IO uint32_t INTTYPECLR; /**< Interrupt Type Clear Register, offset: 0x2C */ + __IO uint32_t INTPOLSET; /**< Interrupt Polarity Set Register, offset: 0x30 */ + __IO uint32_t INTPOLCLR; /**< Interrupt Polarity Clear Register, offset: 0x34 */ + __IO uint32_t INTSTATUS; /**< Interrupt Status Register, offset: 0x38 */ + uint32_t RESERVED_3[241]; + __IO uint32_t MASKLOWBYTE[256]; /**< Lower Eight Bits Masked Access Register, array offset: 0x400, array step: 0x4 */ + __IO uint32_t MASKHIGHBYTE[256]; /**< Higher Eight Bits Masked Access Register, array offset: 0x800, array step: 0x4 */ +} GPIO_TypeDef; + +/** @name DATA - GPIO_DATA register */ +/** @{ */ +#define GPIO_DATA_DVAL_Pos (0) +#define GPIO_DATA_DVAL_Msk (0xFFFFUL << GPIO_DATA_DVAL_Pos) +/** @} */ + +/** @name DATAOUT - GPIO_DATAOUT register */ +/** @{ */ +#define GPIO_DATAOUT_DOVAL_Pos (0) +#define GPIO_DATAOUT_DOVAL_Msk (0xFFFFUL << GPIO_DATAOUT_DOVAL_Pos) +/** @} */ + +/** @name OUTENSET - GPIO_OUTENSET register */ +/** @{ */ +#define GPIO_OUTENSET_OEN_Pos (0) +#define GPIO_OUTENSET_OEN_Msk (0xFFFFUL << GPIO_OUTENSET_OEN_Pos) +/** @} */ + +/** @name OUTENCLR - GPIO_OUTENCLR register */ +/** @{ */ +#define GPIO_OUTENCLR_OCLR_Pos (0) +#define GPIO_OUTENCLR_OCLR_Msk (0xFFFFUL << GPIO_OUTENCLR_OCLR_Pos) +/** @} */ + +/** @name INTENSET - GPIO_INTENSET register */ +/** @{ */ +#define GPIO_INTENSET_INEN_Pos (0) +#define GPIO_INTENSET_INEN_Msk (0xFFFFUL << GPIO_INTENSET_INEN_Pos) +/** @} */ + +/** @name INTENCLR - GPIO_INTENCLR register */ +/** @{ */ +#define GPIO_INTENCLR_INCLR_Pos (0) +#define GPIO_INTENCLR_INCLR_Msk (0xFFFFUL << GPIO_INTENCLR_INCLR_Pos) +/** @} */ + +/** @name INTTYPESET - GPIO_INTTYPESET register */ +/** @{ */ +#define GPIO_INTTYPESET_INTYPE_Pos (0) +#define GPIO_INTTYPESET_INTYPE_Msk (0xFFFFUL << GPIO_INTTYPESET_INTYPE_Pos) +/** @} */ + +/** @name INTTYPECLR - GPIO_INTTYPECLR register */ +/** @{ */ +#define GPIO_INTTYPECLR_INTYPECLR_Pos (0) +#define GPIO_INTTYPECLR_INTYPECLR_Msk (0xFFFFUL << GPIO_INTTYPECLR_INTYPECLR_Pos) +/** @} */ + +/** @name INTPOLSET - GPIO_INTPOLSET register */ +/** @{ */ +#define GPIO_INTPOLSET_INPOL_Pos (0) +#define GPIO_INTPOLSET_INPOL_Msk (0xFFFFUL << GPIO_INTPOLSET_INPOL_Pos) +/** @} */ + +/** @name INTPOLCLR - GPIO_INTPOLCLR register */ +/** @{ */ +#define GPIO_INTPOLCLR_INPOLCLR_Pos (0) +#define GPIO_INTPOLCLR_INPOLCLR_Msk (0xFFFFUL << GPIO_INTPOLCLR_INPOLCLR_Pos) +/** @} */ + +/** @name INTSTATUS - GPIO_INTSTATUS register */ +/** @{ */ +#define GPIO_INTSTATUS_INSTAT_Pos (0) +#define GPIO_INTSTATUS_INSTAT_Msk (0xFFFFUL << GPIO_INTSTATUS_INSTAT_Pos) +/** @} */ + +/** @name MASKLOWBYTE - GPIO_MASKLOWBYTE N register */ +/** @{ */ +#define GPIO_MASKLOWBYTE_MASK_Pos (0) +#define GPIO_MASKLOWBYTE_MASK_Msk (0xFFFFUL << GPIO_MASKLOWBYTE_MASK_Pos) +/** @} */ + +/** @name MASKHIGHBYTE - GPIO_MASKHIGHBYTE N register */ +/** @{ */ +#define GPIO_MASKHIGHBYTE_MASK_Pos (0) +#define GPIO_MASKHIGHBYTE_MASK_Msk (0xFFFFUL << GPIO_MASKHIGHBYTE_MASK_Pos) +/** @} */ + +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE_ADDR (MP_GPIO_BASE_ADDR + 0x0000) + +/** Peripheral GPIO0 base pointer */ +#define GPIO_0 ((GPIO_TypeDef *) GPIO0_BASE_ADDR) + +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE_ADDR (MP_GPIO_BASE_ADDR + 0x1000) + +/** Peripheral GPIO1 base pointer */ +#define GPIO_1 ((GPIO_TypeDef *) GPIO1_BASE_ADDR) + +/** @brief GPIO peripheral instance number */ +#define GPIO_INSTANCE_NUM (2) + +/** + * @} + */ /* end of group ADC */ + + +/** @addtogroup I2C I2C + * @{ + */ + +/** + * @brief I2C register layout typedef + * + */ +typedef struct { + __IO uint32_t MCR; /**< Main Control Register, offset: 0x0 */ + __IO uint32_t SCR; /**< Secondary Control Register, offset: 0x4 */ + __IO uint32_t SAR; /**< Slave Address Register, offset: 0x8 */ + __IO uint32_t TPR; /**< Timing Parameter Register, offset: 0xC */ + union{ + __IO uint32_t TDR; /**< Transmit Data Register, offset: 0x10 */ + __IO uint32_t RDR; /**< Receive Data Register, offset: 0x10 */ + }; + __IO uint32_t TOR; /**< Timeout Register, offset: 0x14 */ + __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ + __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0x20 */ + __IO uint32_t STR; /**< Status Register, offset: 0x24 */ + __IO uint32_t FSR; /**< FIFO Status Register, offset: 0x28 */ +} I2C_TypeDef; + +/** @name MCR - I2C_MCR register */ +/** @{ */ +#define I2C_MCR_I2C_EN_Pos (0) +#define I2C_MCR_I2C_EN_Msk (0x1UL << I2C_MCR_I2C_EN_Pos) + +#define I2C_MCR_DISABLE_SCL_STRETCH_Pos (1) +#define I2C_MCR_DISABLE_SCL_STRETCH_Msk (0x1UL << I2C_MCR_DISABLE_SCL_STRETCH_Pos) + +#define I2C_MCR_START_BYTE_EN_Pos (2) +#define I2C_MCR_START_BYTE_EN_Msk (0x1UL << I2C_MCR_START_BYTE_EN_Pos) + +#define I2C_MCR_CONTROL_MODE_Pos (3) +#define I2C_MCR_CONTROL_MODE_Msk (0x1UL << I2C_MCR_CONTROL_MODE_Pos) + +#define I2C_MCR_TX_DMA_EN_Pos (4) +#define I2C_MCR_TX_DMA_EN_Msk (0x1UL << I2C_MCR_TX_DMA_EN_Pos) + +#define I2C_MCR_RX_DMA_EN_Pos (5) +#define I2C_MCR_RX_DMA_EN_Msk (0x1UL << I2C_MCR_RX_DMA_EN_Pos) + +#define I2C_MCR_AGGRESSIVE_MASTER_Pos (6) +#define I2C_MCR_AGGRESSIVE_MASTER_Msk (0x1UL << I2C_MCR_AGGRESSIVE_MASTER_Pos) + +#define I2C_MCR_AUTOCG_EN_Pos (7) +#define I2C_MCR_AUTOCG_EN_Msk (0x1UL << I2C_MCR_AUTOCG_EN_Pos) + +#define I2C_MCR_DISABLE_MASTER_Pos (8) +#define I2C_MCR_DISABLE_MASTER_Msk (0x1UL << I2C_MCR_DISABLE_MASTER_Pos) + +#define I2C_MCR_TX_FIFO_THRESHOLD_Pos (16) +#define I2C_MCR_TX_FIFO_THRESHOLD_Msk (0xFUL << I2C_MCR_TX_FIFO_THRESHOLD_Pos) + +#define I2C_MCR_RX_FIFO_THRESHOLD_Pos (20) +#define I2C_MCR_RX_FIFO_THRESHOLD_Msk (0xFUL << I2C_MCR_RX_FIFO_THRESHOLD_Pos) +/** @} */ + +/** @name SCR - I2C_SCR register */ +/** @{ */ +#define I2C_SCR_TARGET_SLAVE_ADDR_Pos (0) +#define I2C_SCR_TARGET_SLAVE_ADDR_Msk (0x3FFUL << I2C_SCR_TARGET_SLAVE_ADDR_Pos) + +#define I2C_SCR_TARGET_SLAVE_ADDR_MODE_Pos (13) +#define I2C_SCR_TARGET_SLAVE_ADDR_MODE_Msk (0x1UL << I2C_SCR_TARGET_SLAVE_ADDR_MODE_Pos) + +#define I2C_SCR_TARGET_RWN_Pos (14) +#define I2C_SCR_TARGET_RWN_Msk (0x1UL << I2C_SCR_TARGET_RWN_Pos) + +#define I2C_SCR_START_Pos (15) +#define I2C_SCR_START_Msk (0x1UL << I2C_SCR_START_Pos) + +#define I2C_SCR_RESTART_Pos (16) +#define I2C_SCR_RESTART_Msk (0x1UL << I2C_SCR_RESTART_Pos) + +#define I2C_SCR_STOP_Pos (17) +#define I2C_SCR_STOP_Msk (0x1UL << I2C_SCR_STOP_Pos) + +#define I2C_SCR_ACK_Pos (18) +#define I2C_SCR_ACK_Msk (0x1UL << I2C_SCR_ACK_Pos) + +#define I2C_SCR_ACK_VALUE_Pos (19) +#define I2C_SCR_ACK_VALUE_Msk (0x1UL << I2C_SCR_ACK_VALUE_Pos) + +#define I2C_SCR_FLUSH_TX_FIFO_Pos (20) +#define I2C_SCR_FLUSH_TX_FIFO_Msk (0x1UL << I2C_SCR_FLUSH_TX_FIFO_Pos) + +#define I2C_SCR_FLUSH_RX_FIFO_Pos (21) +#define I2C_SCR_FLUSH_RX_FIFO_Msk (0x1UL << I2C_SCR_FLUSH_RX_FIFO_Pos) + +#define I2C_SCR_BYTE_NUM_UNKNOWN_Pos (22) +#define I2C_SCR_BYTE_NUM_UNKNOWN_Msk (0x1UL << I2C_SCR_BYTE_NUM_UNKNOWN_Pos) + +#define I2C_SCR_BYTE_NUM_Pos (23) +#define I2C_SCR_BYTE_NUM_Msk (0x1FFUL << I2C_SCR_BYTE_NUM_Pos) +/** @} */ + +/** @name SAR - I2C_SAR register */ +/** @{ */ +#define I2C_SAR_SLAVE_ADDR_Pos (0) +#define I2C_SAR_SLAVE_ADDR_Msk (0x3FFUL << I2C_SAR_SLAVE_ADDR_Pos) + +#define I2C_SAR_SLAVE_ADDR_EN_Pos (12) +#define I2C_SAR_SLAVE_ADDR_EN_Msk (0x1UL << I2C_SAR_SLAVE_ADDR_EN_Pos) + +#define I2C_SAR_SLAVE_ADDR_MODE_Pos (13) +#define I2C_SAR_SLAVE_ADDR_MODE_Msk (0x1UL << I2C_SAR_SLAVE_ADDR_MODE_Pos) + +#define I2C_SAR_GENERAL_CALL_EN_Pos (16) +#define I2C_SAR_GENERAL_CALL_EN_Msk (0x1UL << I2C_SAR_GENERAL_CALL_EN_Pos) +/** @} */ + +/** @name TPR - I2C_TPR register */ +/** @{ */ +#define I2C_TPR_SCLL_Pos (0) +#define I2C_TPR_SCLL_Msk (0xFFUL << I2C_TPR_SCLL_Pos) + +#define I2C_TPR_SCLH_Pos (8) +#define I2C_TPR_SCLH_Msk (0xFFUL << I2C_TPR_SCLH_Pos) + +#define I2C_TPR_SDA_SETUP_TIME_Pos (16) +#define I2C_TPR_SDA_SETUP_TIME_Msk (0x7UL << I2C_TPR_SDA_SETUP_TIME_Pos) + +#define I2C_TPR_SDA_HOLD_TIME_Pos (20) +#define I2C_TPR_SDA_HOLD_TIME_Msk (0x7UL << I2C_TPR_SDA_HOLD_TIME_Pos) + +#define I2C_TPR_SPIKE_FILTER_CNUM_Pos (24) +#define I2C_TPR_SPIKE_FILTER_CNUM_Msk (0xFUL << I2C_TPR_SPIKE_FILTER_CNUM_Pos) +/** @} */ + +/** @name TDR - I2C_TDR register */ +/** @{ */ +#define I2C_TDR_TX_DATA_Pos (0) +#define I2C_TDR_TX_DATA_Msk (0xFFUL << I2C_TDR_TX_DATA_Pos) +/** @} */ + +/** @name RDR - I2C_RDR register */ +/** @{ */ +#define I2C_RDR_RX_DATA_Pos (0) +#define I2C_RDR_RX_DATA_Msk (0xFFUL << I2C_RDR_RX_DATA_Pos) +/** @} */ + +/** @name TOR - I2C_TOR register */ +/** @{ */ +#define I2C_TOR_WAIT_IDLE_TIMEOUT_TIME_Pos (0) +#define I2C_TOR_WAIT_IDLE_TIMEOUT_TIME_Msk (0x3FFUL << I2C_TOR_WAIT_IDLE_TIMEOUT_TIME_Pos) + +#define I2C_TOR_SCL_STRETCH_TIMEOUT_TIME_Pos (16) +#define I2C_TOR_SCL_STRETCH_TIMEOUT_TIME_Msk (0x3FFUL << I2C_TOR_SCL_STRETCH_TIMEOUT_TIME_Pos) +/** @} */ + +/** @name ISR - I2C_ISR register */ +/** @{ */ +#define I2C_ISR_TX_FIFO_EMPTY_Pos (0) +#define I2C_ISR_TX_FIFO_EMPTY_Msk (0x1UL << I2C_ISR_TX_FIFO_EMPTY_Pos) + +#define I2C_ISR_TX_FIFO_UNDERRUN_Pos (1) +#define I2C_ISR_TX_FIFO_UNDERRUN_Msk (0x1UL << I2C_ISR_TX_FIFO_UNDERRUN_Pos) + +#define I2C_ISR_TX_FIFO_OVERFLOW_Pos (2) +#define I2C_ISR_TX_FIFO_OVERFLOW_Msk (0x1UL << I2C_ISR_TX_FIFO_OVERFLOW_Pos) + +#define I2C_ISR_RX_FIFO_FULL_Pos (3) +#define I2C_ISR_RX_FIFO_FULL_Msk (0x1UL << I2C_ISR_RX_FIFO_FULL_Pos) + +#define I2C_ISR_RX_FIFO_OVERFLOW_Pos (4) +#define I2C_ISR_RX_FIFO_OVERFLOW_Msk (0x1UL << I2C_ISR_RX_FIFO_OVERFLOW_Pos) + +#define I2C_ISR_TX_ONE_DATA_Pos (5) +#define I2C_ISR_TX_ONE_DATA_Msk (0x1UL << I2C_ISR_TX_ONE_DATA_Pos) + +#define I2C_ISR_RX_ONE_DATA_Pos (6) +#define I2C_ISR_RX_ONE_DATA_Msk (0x1UL << I2C_ISR_RX_ONE_DATA_Pos) + +#define I2C_ISR_RX_NACK_Pos (7) +#define I2C_ISR_RX_NACK_Msk (0x1UL << I2C_ISR_RX_NACK_Pos) + +#define I2C_ISR_SLAVE_ADDR_MATCHED_Pos (8) +#define I2C_ISR_SLAVE_ADDR_MATCHED_Msk (0x1UL << I2C_ISR_SLAVE_ADDR_MATCHED_Pos) + +#define I2C_ISR_TRANSFER_DONE_Pos (9) +#define I2C_ISR_TRANSFER_DONE_Msk (0x1UL << I2C_ISR_TRANSFER_DONE_Pos) + +#define I2C_ISR_DETECT_STOP_Pos (10) +#define I2C_ISR_DETECT_STOP_Msk (0x1UL << I2C_ISR_DETECT_STOP_Pos) + +#define I2C_ISR_BUS_ERROR_Pos (11) +#define I2C_ISR_BUS_ERROR_Msk (0x1UL << I2C_ISR_BUS_ERROR_Pos) + +#define I2C_ISR_ARBITRATATION_LOST_Pos (12) +#define I2C_ISR_ARBITRATATION_LOST_Msk (0x1UL << I2C_ISR_ARBITRATATION_LOST_Pos) + +#define I2C_ISR_WAIT_TX_FIFO_Pos (13) +#define I2C_ISR_WAIT_TX_FIFO_Msk (0x1UL << I2C_ISR_WAIT_TX_FIFO_Pos) + +#define I2C_ISR_WAIT_RX_FIFO_Pos (14) +#define I2C_ISR_WAIT_RX_FIFO_Msk (0x1UL << I2C_ISR_WAIT_RX_FIFO_Pos) + +#define I2C_ISR_WAIT_FOR_BUS_IDLE_TIMEOUT_Pos (15) +#define I2C_ISR_WAIT_FOR_BUS_IDLE_TIMEOUT_Msk (0x1UL << I2C_ISR_WAIT_FOR_BUS_IDLE_TIMEOUT_Pos) + +#define I2C_ISR_STRETCH_SCL_TIMEOUT_Pos (16) +#define I2C_ISR_STRETCH_SCL_TIMEOUT_Msk (0x1UL << I2C_ISR_STRETCH_SCL_TIMEOUT_Pos) + +#define I2C_ISR_DEDICATE_POINT_Pos (17) +#define I2C_ISR_DEDICATE_POINT_Msk (0x1UL << I2C_ISR_DEDICATE_POINT_Pos) +/** @} */ + +/** @name IER - I2C_IER register */ +/** @{ */ +#define I2C_IER_TX_FIFO_EMPTY_Pos (0) +#define I2C_IER_TX_FIFO_EMPTY_Msk (0x1UL << I2C_IER_TX_FIFO_EMPTY_Pos) + +#define I2C_IER_TX_FIFO_UNDERRUN_Pos (1) +#define I2C_IER_TX_FIFO_UNDERRUN_Msk (0x1UL << I2C_IER_TX_FIFO_UNDERRUN_Pos) + +#define I2C_IER_TX_FIFO_OVERFLOW_Pos (2) +#define I2C_IER_TX_FIFO_OVERFLOW_Msk (0x1UL << I2C_IER_TX_FIFO_OVERFLOW_Pos) + +#define I2C_IER_RX_FIFO_FULL_Pos (3) +#define I2C_IER_RX_FIFO_FULL_Msk (0x1UL << I2C_IER_RX_FIFO_FULL_Pos) + +#define I2C_IER_RX_FIFO_OVERFLOW_Pos (4) +#define I2C_IER_RX_FIFO_OVERFLOW_Msk (0x1UL << I2C_IER_RX_FIFO_OVERFLOW_Pos) + +#define I2C_IER_TX_ONE_DATA_Pos (5) +#define I2C_IER_TX_ONE_DATA_Msk (0x1UL << I2C_IER_TX_ONE_DATA_Pos) + +#define I2C_IER_RX_ONE_DATA_Pos (6) +#define I2C_IER_RX_ONE_DATA_Msk (0x1UL << I2C_IER_RX_ONE_DATA_Pos) + +#define I2C_IER_RX_NACK_Pos (7) +#define I2C_IER_RX_NACK_Msk (0x1UL << I2C_IER_RX_NACK_Pos) + +#define I2C_IER_SLAVE_ADDR_MATCHED_Pos (8) +#define I2C_IER_SLAVE_ADDR_MATCHED_Msk (0x1UL << I2C_IER_SLAVE_ADDR_MATCHED_Pos) + +#define I2C_IER_TRANSFER_DONE_Pos (9) +#define I2C_IER_TRANSFER_DONE_Msk (0x1UL << I2C_IER_TRANSFER_DONE_Pos) + +#define I2C_IER_DETECT_STOP_Pos (10) +#define I2C_IER_DETECT_STOP_Msk (0x1UL << I2C_IER_DETECT_STOP_Pos) + +#define I2C_IER_BUS_ERROR_Pos (11) +#define I2C_IER_BUS_ERROR_Msk (0x1UL << I2C_IER_BUS_ERROR_Pos) + +#define I2C_IER_ARBITRATATION_LOST_Pos (12) +#define I2C_IER_ARBITRATATION_LOST_Msk (0x1UL << I2C_IER_ARBITRATATION_LOST_Pos) + +#define I2C_IER_WAIT_TX_FIFO_Pos (13) +#define I2C_IER_WAIT_TX_FIFO_Msk (0x1UL << I2C_IER_WAIT_TX_FIFO_Pos) + +#define I2C_IER_WAIT_RX_FIFO_Pos (14) +#define I2C_IER_WAIT_RX_FIFO_Msk (0x1UL << I2C_IER_WAIT_RX_FIFO_Pos) + +#define I2C_IER_WAIT_FOR_BUS_IDLE_TIMEOUT_Pos (15) +#define I2C_IER_WAIT_FOR_BUS_IDLE_TIMEOUT_Msk (0x1UL << I2C_IER_WAIT_FOR_BUS_IDLE_TIMEOUT_Pos) + +#define I2C_IER_STRETCH_SCL_TIMEOUT_Pos (16) +#define I2C_IER_STRETCH_SCL_TIMEOUT_Msk (0x1UL << I2C_IER_STRETCH_SCL_TIMEOUT_Pos) + +#define I2C_IER_DEDICATE_POINT_Pos (17) +#define I2C_IER_DEDICATE_POINT_Msk (0x1UL << I2C_IER_DEDICATE_POINT_Pos) +/** @} */ + +/** @name IMR - I2C_IMR register */ +/** @{ */ +#define I2C_IMR_TX_FIFO_EMPTY_Pos (0) +#define I2C_IMR_TX_FIFO_EMPTY_Msk (0x1UL << I2C_IMR_TX_FIFO_EMPTY_Pos) + +#define I2C_IMR_TX_FIFO_UNDERRUN_Pos (1) +#define I2C_IMR_TX_FIFO_UNDERRUN_Msk (0x1UL << I2C_IMR_TX_FIFO_UNDERRUN_Pos) + +#define I2C_IMR_TX_FIFO_OVERFLOW_Pos (2) +#define I2C_IMR_TX_FIFO_OVERFLOW_Msk (0x1UL << I2C_IMR_TX_FIFO_OVERFLOW_Pos) + +#define I2C_IMR_RX_FIFO_FULL_Pos (3) +#define I2C_IMR_RX_FIFO_FULL_Msk (0x1UL << I2C_IMR_RX_FIFO_FULL_Pos) + +#define I2C_IMR_RX_FIFO_OVERFLOW_Pos (4) +#define I2C_IMR_RX_FIFO_OVERFLOW_Msk (0x1UL << I2C_IMR_RX_FIFO_OVERFLOW_Pos) + +#define I2C_IMR_TX_ONE_DATA_Pos (5) +#define I2C_IMR_TX_ONE_DATA_Msk (0x1UL << I2C_IMR_TX_ONE_DATA_Pos) + +#define I2C_IMR_RX_ONE_DATA_Pos (6) +#define I2C_IMR_RX_ONE_DATA_Msk (0x1UL << I2C_IMR_RX_ONE_DATA_Pos) + +#define I2C_IMR_RX_NACK_Pos (7) +#define I2C_IMR_RX_NACK_Msk (0x1UL << I2C_IMR_RX_NACK_Pos) + +#define I2C_IMR_SLAVE_ADDR_MATCHED_Pos (8) +#define I2C_IMR_SLAVE_ADDR_MATCHED_Msk (0x1UL << I2C_IMR_SLAVE_ADDR_MATCHED_Pos) + +#define I2C_IMR_TRANSFER_DONE_Pos (9) +#define I2C_IMR_TRANSFER_DONE_Msk (0x1UL << I2C_IMR_TRANSFER_DONE_Pos) + +#define I2C_IMR_DETECT_STOP_Pos (10) +#define I2C_IMR_DETECT_STOP_Msk (0x1UL << I2C_IMR_DETECT_STOP_Pos) + +#define I2C_IMR_BUS_ERROR_Pos (11) +#define I2C_IMR_BUS_ERROR_Msk (0x1UL << I2C_IMR_BUS_ERROR_Pos) + +#define I2C_IMR_ARBITRATATION_LOST_Pos (12) +#define I2C_IMR_ARBITRATATION_LOST_Msk (0x1UL << I2C_IMR_ARBITRATATION_LOST_Pos) + +#define I2C_IMR_WAIT_TX_FIFO_Pos (13) +#define I2C_IMR_WAIT_TX_FIFO_Msk (0x1UL << I2C_IMR_WAIT_TX_FIFO_Pos) + +#define I2C_IMR_WAIT_RX_FIFO_Pos (14) +#define I2C_IMR_WAIT_RX_FIFO_Msk (0x1UL << I2C_IMR_WAIT_RX_FIFO_Pos) + +#define I2C_IMR_WAIT_FOR_BUS_IDLE_TIMEOUT_Pos (15) +#define I2C_IMR_WAIT_FOR_BUS_IDLE_TIMEOUT_Msk (0x1UL << I2C_IMR_WAIT_FOR_BUS_IDLE_TIMEOUT_Pos) + +#define I2C_IMR_STRETCH_SCL_TIMEOUT_Pos (16) +#define I2C_IMR_STRETCH_SCL_TIMEOUT_Msk (0x1UL << I2C_IMR_STRETCH_SCL_TIMEOUT_Pos) + +#define I2C_IMR_DEDICATE_POINT_Pos (17) +#define I2C_IMR_DEDICATE_POINT_Msk (0x1UL << I2C_IMR_DEDICATE_POINT_Pos) +/** @} */ + +/** @name STR - I2C_STR register */ +/** @{ */ +#define I2C_STR_BUSY_Pos (0) +#define I2C_STR_BUSY_Msk (0x1UL << I2C_STR_BUSY_Pos) + +#define I2C_STR_ADDRESS_PHASE_Pos (1) +#define I2C_STR_ADDRESS_PHASE_Msk (0x1UL << I2C_STR_ADDRESS_PHASE_Pos) + +#define I2C_STR_DATA_PHASE_Pos (2) +#define I2C_STR_DATA_PHASE_Msk (0x1UL << I2C_STR_DATA_PHASE_Pos) + +#define I2C_STR_SLAVE_ADDRESSED_FLAG_Pos (8) +#define I2C_STR_SLAVE_ADDRESSED_FLAG_Msk (0x1UL << I2C_STR_SLAVE_ADDRESSED_FLAG_Pos) + +#define I2C_STR_SLAVE_ADDRESSED_IND_Pos (9) +#define I2C_STR_SLAVE_ADDRESSED_IND_Msk (0x1UL << I2C_STR_SLAVE_ADDRESSED_IND_Pos) + +#define I2C_STR_SLAVE_RWN_Pos (10) +#define I2C_STR_SLAVE_RWN_Msk (0x1UL << I2C_STR_SLAVE_RWN_Pos) + +#define I2C_STR_TXRX_DATA_NUM_Pos (16) +#define I2C_STR_TXRX_DATA_NUM_Msk (0x1FFUL << I2C_STR_TXRX_DATA_NUM_Pos) +/** @} */ + +/** @name FSR - I2C_FSR register */ +/** @{ */ +#define I2C_FSR_TX_FIFO_FREE_NUM_Pos (0) +#define I2C_FSR_TX_FIFO_FREE_NUM_Msk (0x1FUL << I2C_FSR_TX_FIFO_FREE_NUM_Pos) + +#define I2C_FSR_RX_FIFO_DATA_NUM_Pos (8) +#define I2C_FSR_RX_FIFO_DATA_NUM_Msk (0x1FUL << I2C_FSR_RX_FIFO_DATA_NUM_Pos) +/** @} */ + +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_TypeDef *)AP_I2C0_BASE_ADDR) + +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_TypeDef *)AP_I2C1_BASE_ADDR) + +/** @brief I2C peripheral instance number */ +#define I2C_INSTANCE_NUM (2) + +/** + * @} + */ /* end of group I2C */ + +/** @addtogroup I2S I2S + * @{ + */ + +/** + * @brief I2S register layout typedef + * + */ +typedef struct { + __IO uint32_t DFMT; /**< Data Format Register, offset: 0x0 */ + __IO uint32_t SLOTCTL; /**< Slot Control Register, offset: 0x4 */ + __IO uint32_t CLKCTL; /**< Clock Control Register, offset: 0x8 */ + __IO uint32_t DMACTL; /**< DMA Control Register, offset: 0xC */ + __IO uint32_t INTCTL; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t TIMEOUTCTL; /**< Timeout Control Register, offset: 0x14 */ + __IO uint32_t STAS; /**< Status Register, offset: 0x18 */ + __IO uint32_t RFIFO; /**< Rx Buffer Register, offset: 0x1c */ + __IO uint32_t TFIFO; /**< Tx Buffer Register, offset: 0x20 */ + __IO uint32_t I2SCTL; /**< I2S Control Register, offset: 0x24 */ +} I2S_TypeDef; + +/** @name DFMT - I2S_DFMT register */ +/** @{ */ +#define I2S_DFMT_SLAVE_MODE_EN_Pos (0) +#define I2S_DFMT_SLAVE_MODE_EN_Msk (0x1UL << I2S_DFMT_SLAVE_MODE_EN_Pos) + +#define I2S_DFMT_SLOT_SIZE_Pos (1) +#define I2S_DFMT_SLOT_SIZE_Msk (0x1FUL << I2S_DFMT_SLOT_SIZE_Pos) + +#define I2S_DFMT_WORD_SIZE_Pos (6) +#define I2S_DFMT_WORD_SIZE_Msk (0x1FUL << I2S_DFMT_WORD_SIZE_Pos) + +#define I2S_DFMT_ALIGN_MODE_Pos (11) +#define I2S_DFMT_ALIGN_MODE_Msk (0x1UL << I2S_DFMT_ALIGN_MODE_Pos) + +#define I2S_DFMT_ENDIAN_MODE_Pos (12) +#define I2S_DFMT_ENDIAN_MODE_Msk (0x1UL << I2S_DFMT_ENDIAN_MODE_Pos) + +#define I2S_DFMT_DATA_DLY_Pos (13) +#define I2S_DFMT_DATA_DLY_Msk (0x3UL << I2S_DFMT_DATA_DLY_Pos) + +#define I2S_DFMT_TX_PAD_Pos (15) +#define I2S_DFMT_TX_PAD_Msk (0x3UL << I2S_DFMT_TX_PAD_Pos) + +#define I2S_DFMT_RX_SIGN_EXT_Pos (17) +#define I2S_DFMT_RX_SIGN_EXT_Msk (0x1UL << I2S_DFMT_RX_SIGN_EXT_Pos) + +#define I2S_DFMT_TX_PACK_Pos (18) +#define I2S_DFMT_TX_PACK_Msk (0x3UL << I2S_DFMT_TX_PACK_Pos) + +#define I2S_DFMT_RX_PACK_Pos (20) +#define I2S_DFMT_RX_PACK_Msk (0x3UL << I2S_DFMT_RX_PACK_Pos) + +#define I2S_DFMT_TX_FIFO_ENDIAN_MODE_Pos (22) +#define I2S_DFMT_TX_FIFO_ENDIAN_MODE_Msk (0x1UL << I2S_DFMT_TX_FIFO_ENDIAN_MODE_Pos) + +#define I2S_DFMT_RX_FIFO_ENDIAN_MODE_Pos (23) +#define I2S_DFMT_RX_FIFO_ENDIAN_MODE_Msk (0x1UL << I2S_DFMT_RX_FIFO_ENDIAN_MODE_Pos) +/** @} */ + +/** @name SLOTCTL - I2S_SLOTCTL register */ +/** @{ */ +#define I2S_SLOTCTL_SLOT_EN_Pos (0) +#define I2S_SLOTCTL_SLOT_EN_Msk (0xFFUL << I2S_SLOTCTL_SLOT_EN_Pos) + +#define I2S_SLOTCTL_SLOT_NUM_Pos (8) +#define I2S_SLOTCTL_SLOT_NUM_Msk (0x7UL << I2S_SLOTCTL_SLOT_NUM_Pos) +/** @} */ + +/** @name CLKCTL - I2S_CLKCTL register */ +/** @{ */ +#define I2S_CLKCTL_BCLK_POLARITY_Pos (0) +#define I2S_CLKCTL_BCLK_POLARITY_Msk (0x1UL << I2S_CLKCTL_BCLK_POLARITY_Pos) + +#define I2S_CLKCTL_FS_POLARITY_Pos (1) +#define I2S_CLKCTL_FS_POLARITY_Msk (0x1UL << I2S_CLKCTL_FS_POLARITY_Pos) + +#define I2S_CLKCTL_FS_WIDTH_Pos (2) +#define I2S_CLKCTL_FS_WIDTH_Msk (0x3FUL << I2S_CLKCTL_FS_WIDTH_Pos) +/** @} */ + +/** @name DMA_CTRL - I2S_DMA_CTRL register */ +/** @{ */ +#define I2S_DMA_CTRL_RX_DMA_REQ_EN_Pos (0) +#define I2S_DMA_CTRL_RX_DMA_REQ_EN_Msk (0x1UL << I2S_DMA_CTRL_RX_DMA_REQ_EN_Pos) + +#define I2S_DMA_CTRL_TX_DMA_REQ_EN_Pos (1) +#define I2S_DMA_CTRL_TX_DMA_REQ_EN_Msk (0x1UL << I2S_DMA_CTRL_TX_DMA_REQ_EN_Pos) + +#define I2S_DMA_CTRL_RX_DMA_TIMEOUT_EN_Pos (2) +#define I2S_DMA_CTRL_RX_DMA_TIMEOUT_EN_Msk (0x1UL << I2S_DMA_CTRL_RX_DMA_TIMEOUT_EN_Pos) + +#define I2S_DMA_CTRL_DMA_WORK_WAIT_CYCLE_Pos (3) +#define I2S_DMA_CTRL_DMA_WORK_WAIT_CYCLE_Msk (0x1FUL << I2S_DMA_CTRL_DMA_WORK_WAIT_CYCLE_Pos) + +#define I2S_DMA_CTRL_RX_DMA_BURST_SIZE_SUB1_Pos (8) +#define I2S_DMA_CTRL_RX_DMA_BURST_SIZE_SUB1_Msk (0xFUL << I2S_DMA_CTRL_RX_DMA_BURST_SIZE_SUB1_Pos) + +#define I2S_DMA_CTRL_TX_DMA_BURST_SIZE_SUB1_Pos (12) +#define I2S_DMA_CTRL_TX_DMA_BURST_SIZE_SUB1_Msk (0xFUL << I2S_DMA_CTRL_TX_DMA_BURST_SIZE_SUB1_Pos) + +#define I2S_DMA_CTRL_RX_DMA_THRESHOLD_Pos (16) +#define I2S_DMA_CTRL_RX_DMA_THRESHOLD_Msk (0xFUL << I2S_DMA_CTRL_RX_DMA_THRESHOLD_Pos) + +#define I2S_DMA_CTRL_TX_DMA_THRESHOLD_Pos (20) +#define I2S_DMA_CTRL_TX_DMA_THRESHOLD_Msk (0xFUL << I2S_DMA_CTRL_TX_DMA_THRESHOLD_Pos) + +#define I2S_DMA_CTRL_RX_FIFO_FLUSH_Pos (24) +#define I2S_DMA_CTRL_RX_FIFO_FLUSH_Msk (0x1UL << I2S_DMA_CTRL_RX_FIFO_FLUSH_Pos) + +#define I2S_DMA_CTRL_TX_FIFO_FLUSH_Pos (25) +#define I2S_DMA_CTRL_TX_FIFO_FLUSH_Msk (0x1UL << I2S_DMA_CTRL_TX_FIFO_FLUSH_Pos) +/** @} */ + + +/** @name INT_CTRL - I2S_INT_CTRL register */ +/** @{ */ +#define I2S_INT_CTRL_TX_UNDERRUN_INT_EN_Pos (0) +#define I2S_INT_CTRL_TX_UNDERRUN_INT_EN_Msk (0x1UL << I2S_INT_CTRL_TX_UNDERRUN_INT_EN_Pos) + +#define I2S_INT_CTRL_TX_DMA_ERR_INT_EN_Pos (1) +#define I2S_INT_CTRL_TX_DMA_ERR_INT_EN_Msk (0x1UL << I2S_INT_CTRL_TX_DMA_ERR_INT_EN_Pos) + +#define I2S_INT_CTRL_TX_DAT_INT_EN_Pos (2) +#define I2S_INT_CTRL_TX_DAT_INT_EN_Msk (0x1UL << I2S_INT_CTRL_TX_DAT_INT_EN_Pos) + +#define I2S_INT_CTRL_RX_OVERFLOW_INT_EN_Pos (3) +#define I2S_INT_CTRL_RX_OVERFLOW_INT_EN_Msk (0x1UL << I2S_INT_CTRL_RX_OVERFLOW_INT_EN_Pos) + +#define I2S_INT_CTRL_RX_DMA_ERR_INT_EN_Pos (4) +#define I2S_INT_CTRL_RX_DMA_ERR_INT_EN_Msk (0x1UL << I2S_INT_CTRL_RX_DMA_ERR_INT_EN_Pos) + +#define I2S_INT_CTRL_RX_DAT_INT_EN_Pos (5) +#define I2S_INT_CTRL_RX_DAT_INT_EN_Msk (0x1UL << I2S_INT_CTRL_RX_DAT_INT_EN_Pos) + +#define I2S_INT_CTRL_RX_TIMEOUT_INT_EN_Pos (6) +#define I2S_INT_CTRL_RX_TIMEOUT_INT_EN_Msk (0x1UL << I2S_INT_CTRL_RX_TIMEOUT_INT_EN_Pos) + +#define I2S_INT_CTRL_FS_ERR_INT_EN_Pos (7) +#define I2S_INT_CTRL_FS_ERR_INT_EN_Msk (0x1UL << I2S_INT_CTRL_FS_ERR_INT_EN_Pos) + +#define I2S_INT_CTRL_FRAME_START_INT_EN_Pos (8) +#define I2S_INT_CTRL_FRAME_START_INT_EN_Msk (0x1UL << I2S_INT_CTRL_FRAME_START_INT_EN_Pos) + +#define I2S_INT_CTRL_FRAME_END_INT_EN_Pos (9) +#define I2S_INT_CTRL_FRAME_END_INT_EN_Msk (0x1UL << I2S_INT_CTRL_FRAME_END_INT_EN_Pos) + +#define I2S_INT_CTRL_CSPI_BUS_TIMEOUT_INT_EN_Pos (10) +#define I2S_INT_CTRL_CSPI_BUS_TIMEOUT_INT_EN_Msk (0x1UL << I2S_INT_CTRL_CSPI_BUS_TIMEOUT_INT_EN_Pos) + +#define I2S_INT_CTRL_RSVD1_Pos (11) +#define I2S_INT_CTRL_RSVD1_Msk (0x1UL << I2S_INT_CTRL_RSVD1_Pos) + +#define I2S_INT_CTRL_RSVD2_Pos (12) +#define I2S_INT_CTRL_RSVD2_Msk (0x1UL << I2S_INT_CTRL_RSVD2_Pos) + +#define I2S_INT_CTRL_RSVD3_Pos (13) +#define I2S_INT_CTRL_RSVD3_Msk (0x1UL << I2S_INT_CTRL_RSVD3_Pos) + +#define I2S_INT_CTRL_RSVD4_Pos (14) +#define I2S_INT_CTRL_RSVD4_Msk (0x1UL << I2S_INT_CTRL_RSVD4_Pos) + +#define I2S_INT_CTRL_RSVD5_Pos (15) +#define I2S_INT_CTRL_RSVD5_Msk (0x1UL << I2S_INT_CTRL_RSVD5_Pos) + +#define I2S_INT_CTRL_TX_INT_THREASHOLD_Pos (16) +#define I2S_INT_CTRL_TX_INT_THREASHOLD_Msk (0xFUL << I2S_INT_CTRL_TX_INT_THREASHOLD_Pos) + +#define I2S_INT_CTRL_RX_INT_THREASHOLD_Pos (20) +#define I2S_INT_CTRL_RX_INT_THREASHOLD_Msk (0xFUL << I2S_INT_CTRL_RX_INT_THREASHOLD_Pos) +/** @} */ + +/** @name TIMEOUT_CYCLE - I2S_TIMEOUT_CYCLE register */ +/** @{ */ +#define I2S_TIMEOUT_CYCLE_RX_TIMEOUT_CYCLE_Pos (0) +#define I2S_TIMEOUT_CYCLE_RX_TIMEOUT_CYCLE_Msk (0xFFFFFFUL << I2S_TIMEOUT_CYCLE_RX_TIMEOUT_CYCLE_Pos) +/** @} */ + + + +/** @name STATS_CTRL - I2S_STATS_CTRL register */ +/** @{ */ +#define I2S_STATS_CTRL_TX_UNDERRUN_RUN_Pos (0) +#define I2S_STATS_CTRL_TX_UNDERRUN_RUN_Msk (0x1UL << I2S_STATS_CTRL_TX_UNDERRUN_RUN_Pos) + +#define I2S_STATS_CTRL_TX_DMA_ERR_Pos (1) +#define I2S_STATS_CTRL_TX_DMA_ERR_Msk (0x1UL << I2S_STATS_CTRL_TX_DMA_ERR_Pos) + +#define I2S_STATS_CTRL_TX_DAT_RDY_Pos (2) +#define I2S_STATS_CTRL_TX_DAT_RDY_Msk (0x1UL << I2S_STATS_CTRL_TX_DAT_RDY_Pos) + +#define I2S_STATS_CTRL_RX_OVERFLOW_Pos (3) +#define I2S_STATS_CTRL_RX_OVERFLOW_Msk (0x1UL << I2S_STATS_CTRL_RX_OVERFLOW_Pos) + +#define I2S_STATS_CTRL_RX_DMA_ERR_Pos (4) +#define I2S_STATS_CTRL_RX_DMA_ERR_Msk (0x1UL << I2S_STATS_CTRL_RX_DMA_ERR_Pos) + +#define I2S_STATS_CTRL_RX_DAT_RDY_Pos (5) +#define I2S_STATS_CTRL_RX_DAT_RDY_Msk (0x1UL << I2S_STATS_CTRL_RX_DAT_RDY_Pos) + +#define I2S_STATS_CTRL_RX_FIFO_TIMEOUT_Pos (6) +#define I2S_STATS_CTRL_RX_FIFO_TIMEOUT_Msk (0x1UL << I2S_STATS_CTRL_RX_FIFO_TIMEOUT_Pos) + +#define I2S_STATS_CTRL_FS_ERR_Pos (7) +#define I2S_STATS_CTRL_FS_ERR_Msk (0xFUL << I2S_STATS_CTRL_FS_ERR_Pos) + +#define I2S_STATS_CTRL_FRAME_START_Pos (11) +#define I2S_STATS_CTRL_FRAME_START_Msk (0x1UL << I2S_STATS_CTRL_FRAME_START_Pos) + +#define I2S_STATS_CTRL_FRAME_END_Pos (12) +#define I2S_STATS_CTRL_FRAME_END_Msk (0x1UL << I2S_STATS_CTRL_FRAME_END_Pos) + +#define I2S_STATS_CTRL_TX_FIFO_LEVEL_Pos (13) +#define I2S_STATS_CTRL_TX_FIFO_LEVEL_Msk (0x3FUL << I2S_STATS_CTRL_TX_FIFO_LEVEL_Pos) + +#define I2S_STATS_CTRL_RX_FIFO_LEVEL_Pos (19) +#define I2S_STATS_CTRL_RX_FIFO_LEVEL_Msk (0x3FUL << I2S_STATS_CTRL_RX_FIFO_LEVEL_Pos) + +#define I2S_STATS_CTRL_CSPI_BUS_TIMEOUT_Pos (25) +#define I2S_STATS_CTRL_CSPI_BUS_TIMEOUT_Msk (0x1UL << I2S_STATS_CTRL_CSPI_BUS_TIMEOUT_Pos) +/** @} */ + + +/** @name RFIFO - I2S_RFIFO register */ +/** @{ */ +#define I2S_RFIFO_DATA_Pos (0) +#define I2S_RFIFO_DATA_Msk (0xFFFFFFFFUL << I2S_RFIFO_DATA_Pos) +/** @} */ + +/** @name TFIFO - I2S_TFIFO register */ +/** @{ */ +#define I2S_TFIFO_DAT_Pos (0) +#define I2S_TFIFO_DAT_Msk (0xFFFFFFFFUL << I2S_TFIFO_DAT_Pos) +/** @} */ + +/** @name I2SCTL - I2S_CTL register */ +/** @{ */ +#define I2S_CTL_MODE_Pos (0) +#define I2S_CTL_MODE_Msk (0x3UL << I2S_CTL_MODE_Pos) +/** @} */ + +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_TypeDef *)MP_I2S0_BASE_ADDR) + +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_TypeDef *)MP_I2S1_BASE_ADDR) + +/** @brief SPI peripheral instance number */ +#define I2S_INSTANCE_NUM (2) + + +/** + * @} + */ /* end of group I2S */ + + /** @addtogroup CSPI CSPI + * @{ + */ + +/** + * @brief CSPI register layout typedef + * + */ +typedef struct { + __IO uint32_t DFMT; /**< Data Format Register, offset: 0x0 */ + __IO uint32_t SLOTCTL; /**< Slot Control Register, offset: 0x4 */ + __IO uint32_t CLKCTL; /**< Clock Control Register, offset: 0x8 */ + __IO uint32_t DMACTL; /**< DMA Control Register, offset: 0xC */ + __IO uint32_t INTCTL; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t TIMEOUTCTL; /**< Timeout Control Register, offset: 0x14 */ + __IO uint32_t STAS; /**< Status Register, offset: 0x18 */ + __IO uint32_t RFIFO; /**< Rx Buffer Register, offset: 0x1c */ + __IO uint32_t TFIFO; /**< Tx Buffer Register, offset: 0x20 */ + __IO uint32_t RSVD; /**< Reserved, offset: 0x24 */ + __IO uint32_t CSPICTL; /**< Camera SPI Control Register, offset: 0x28 */ + __IO uint32_t CCTL; /**< Auto Cg Control Register, offset: 0x2c */ + __IO uint32_t CSPIINFO0; /**< Cspi Frame info0 Register, offset: 0x30 */ + __IO uint32_t CSPIINFO1; /**< Cspi Frame info1 Register, offset: 0x34 */ + __IO uint32_t CSPIDBG; /**< Cspi Debug Register, offset: 0x38 */ + __IO uint32_t CSPINIT; /**< Cspi Init Register, offset: 0x3c */ + __IO uint32_t CLSP; /**< Cspi Line Start Register, offset: 0x40 */ + __IO uint32_t CDATP; /**< Cspi Data Packet Register, offset: 0x44 */ + __IO uint32_t CLINFO; /**< Cspi Line Info Register, offset: 0x48 */ +} CSPI_TypeDef; + +/** @name DFMT - CSPI_DFMT register */ +/** @{ */ +#define CSPI_DFMT_SLAVE_MODE_EN_Pos (0) +#define CSPI_DFMT_SLAVE_MODE_EN_Msk (0x1UL << CSPI_DFMT_SLAVE_MODE_EN_Pos) + +#define CSPI_DFMT_SLOT_SIZE_Pos (1) +#define CSPI_DFMT_SLOT_SIZE_Msk (0x1FUL << CSPI_DFMT_SLOT_SIZE_Pos) + +#define CSPI_DFMT_WORD_SIZE_Pos (6) +#define CSPI_DFMT_WORD_SIZE_Msk (0x1FUL << CSPI_DFMT_WORD_SIZE_Pos) + +#define CSPI_DFMT_ALIGN_MODE_Pos (11) +#define CSPI_DFMT_ALIGN_MODE_Msk (0x1UL << CSPI_DFMT_ALIGN_MODE_Pos) + +#define CSPI_DFMT_ENDIAN_MODE_Pos (12) +#define CSPI_DFMT_ENDIAN_MODE_Msk (0x1UL << CSPI_DFMT_ENDIAN_MODE_Pos) + +#define CSPI_DFMT_DATA_DLY_Pos (13) +#define CSPI_DFMT_DATA_DLY_Msk (0x3UL << CSPI_DFMT_DATA_DLY_Pos) + +#define CSPI_DFMT_TX_PAD_Pos (15) +#define CSPI_DFMT_TX_PAD_Msk (0x3UL << CSPI_DFMT_TX_PAD_Pos) + +#define CSPI_DFMT_RX_SIGN_EXT_Pos (17) +#define CSPI_DFMT_RX_SIGN_EXT_Msk (0x1UL << CSPI_DFMT_RX_SIGN_EXT_Pos) + +#define CSPI_DFMT_TX_PACK_Pos (18) +#define CSPI_DFMT_TX_PACK_Msk (0x3UL << CSPI_DFMT_TX_PACK_Pos) + +#define CSPI_DFMT_RX_PACK_Pos (20) +#define CSPI_DFMT_RX_PACK_Msk (0x3UL << CSPI_DFMT_RX_PACK_Pos) + +#define CSPI_DFMT_TX_FIFO_ENDIAN_MODE_Pos (22) +#define CSPI_DFMT_TX_FIFO_ENDIAN_MODE_Msk (0x1UL << CSPI_DFMT_TX_FIFO_ENDIAN_MODE_Pos) + +#define CSPI_DFMT_RX_FIFO_ENDIAN_MODE_Pos (23) +#define CSPI_DFMT_RX_FIFO_ENDIAN_MODE_Msk (0x1UL << CSPI_DFMT_RX_FIFO_ENDIAN_MODE_Pos) +/** @} */ + +/** @name SLOTCTL - CSPI_SLOTCTL register */ +/** @{ */ +#define CSPI_SLOTCTL_SLOT_EN_Pos (0) +#define CSPI_SLOTCTL_SLOT_EN_Msk (0xFFUL << CSPI_SLOTCTL_SLOT_EN_Pos) + +#define CSPI_SLOTCTL_SLOT_NUM_Pos (8) +#define CSPI_SLOTCTL_SLOT_NUM_Msk (0x7UL << CSPI_SLOTCTL_SLOT_NUM_Pos) +/** @} */ + +/** @name CLKCTL - CSPI_CLKCTL register */ +/** @{ */ +#define CSPI_CLKCTL_BCLK_POLARITY_Pos (0) +#define CSPI_CLKCTL_BCLK_POLARITY_Msk (0x1UL << CSPI_CLKCTL_BCLK_POLARITY_Pos) + +#define CSPI_CLKCTL_FS_POLARITY_Pos (1) +#define CSPI_CLKCTL_FS_POLARITY_Msk (0x1UL << CSPI_CLKCTL_FS_POLARITY_Pos) + +#define CSPI_CLKCTL_FS_WIDTH_Pos (2) +#define CSPI_CLKCTL_FS_WIDTH_Msk (0x3FUL << CSPI_CLKCTL_FS_WIDTH_Pos) +/** @} */ + +/** @name DMA_CTRL - CSPI_DMA_CTRL register */ +/** @{ */ +#define CSPI_DMA_CTRL_RX_DMA_REQ_EN_Pos (0) +#define CSPI_DMA_CTRL_RX_DMA_REQ_EN_Msk (0x1UL << CSPI_DMA_CTRL_RX_DMA_REQ_EN_Pos) + +#define CSPI_DMA_CTRL_TX_DMA_REQ_EN_Pos (1) +#define CSPI_DMA_CTRL_TX_DMA_REQ_EN_Msk (0x1UL << CSPI_DMA_CTRL_TX_DMA_REQ_EN_Pos) + +#define CSPI_DMA_CTRL_RX_DMA_TIMEOUT_EN_Pos (2) +#define CSPI_DMA_CTRL_RX_DMA_TIMEOUT_EN_Msk (0x1UL << CSPI_DMA_CTRL_RX_DMA_TIMEOUT_EN_Pos) + +#define CSPI_DMA_CTRL_DMA_WORK_WAIT_CYCLE_Pos (3) +#define CSPI_DMA_CTRL_DMA_WORK_WAIT_CYCLE_Msk (0x1FUL << CSPI_DMA_CTRL_DMA_WORK_WAIT_CYCLE_Pos) + +#define CSPI_DMA_CTRL_RX_DMA_BURST_SIZE_SUB1_Pos (8) +#define CSPI_DMA_CTRL_RX_DMA_BURST_SIZE_SUB1_Msk (0xFUL << CSPI_DMA_CTRL_RX_DMA_BURST_SIZE_SUB1_Pos) + +#define CSPI_DMA_CTRL_TX_DMA_BURST_SIZE_SUB1_Pos (12) +#define CSPI_DMA_CTRL_TX_DMA_BURST_SIZE_SUB1_Msk (0xFUL << CSPI_DMA_CTRL_TX_DMA_BURST_SIZE_SUB1_Pos) + +#define CSPI_DMA_CTRL_RX_DMA_THRESHOLD_Pos (16) +#define CSPI_DMA_CTRL_RX_DMA_THRESHOLD_Msk (0xFUL << CSPI_DMA_CTRL_RX_DMA_THRESHOLD_Pos) + +#define CSPI_DMA_CTRL_TX_DMA_THRESHOLD_Pos (20) +#define CSPI_DMA_CTRL_TX_DMA_THRESHOLD_Msk (0xFUL << CSPI_DMA_CTRL_TX_DMA_THRESHOLD_Pos) + +#define CSPI_DMA_CTRL_RX_FIFO_FLUSH_Pos (24) +#define CSPI_DMA_CTRL_RX_FIFO_FLUSH_Msk (0x1UL << CSPI_DMA_CTRL_RX_FIFO_FLUSH_Pos) + +#define CSPI_DMA_CTRL_TX_FIFO_FLUSH_Pos (25) +#define CSPI_DMA_CTRL_TX_FIFO_FLUSH_Msk (0x1UL << CSPI_DMA_CTRL_TX_FIFO_FLUSH_Pos) +/** @} */ + + +/** @name INT_CTRL - CSPI_INT_CTRL register */ +/** @{ */ +#define CSPI_INT_CTRL_TX_UNDERRUN_INT_EN_Pos (0) +#define CSPI_INT_CTRL_TX_UNDERRUN_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_TX_UNDERRUN_INT_EN_Pos) + +#define CSPI_INT_CTRL_TX_DMA_ERR_INT_EN_Pos (1) +#define CSPI_INT_CTRL_TX_DMA_ERR_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_TX_DMA_ERR_INT_EN_Pos) + +#define CSPI_INT_CTRL_TX_DAT_INT_EN_Pos (2) +#define CSPI_INT_CTRL_TX_DAT_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_TX_DAT_INT_EN_Pos) + +#define CSPI_INT_CTRL_RX_OVERFLOW_INT_EN_Pos (3) +#define CSPI_INT_CTRL_RX_OVERFLOW_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_RX_OVERFLOW_INT_EN_Pos) + +#define CSPI_INT_CTRL_RX_DMA_ERR_INT_EN_Pos (4) +#define CSPI_INT_CTRL_RX_DMA_ERR_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_RX_DMA_ERR_INT_EN_Pos) + +#define CSPI_INT_CTRL_RX_DAT_INT_EN_Pos (5) +#define CSPI_INT_CTRL_RX_DAT_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_RX_DAT_INT_EN_Pos) + +#define CSPI_INT_CTRL_RX_TIMEOUT_INT_EN_Pos (6) +#define CSPI_INT_CTRL_RX_TIMEOUT_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_RX_TIMEOUT_INT_EN_Pos) + +#define CSPI_INT_CTRL_FS_ERR_INT_EN_Pos (7) +#define CSPI_INT_CTRL_FS_ERR_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_FS_ERR_INT_EN_Pos) + +#define CSPI_INT_CTRL_FRAME_START_INT_EN_Pos (8) +#define CSPI_INT_CTRL_FRAME_START_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_FRAME_START_INT_EN_Pos) + +#define CSPI_INT_CTRL_FRAME_END_INT_EN_Pos (9) +#define CSPI_INT_CTRL_FRAME_END_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_FRAME_END_INT_EN_Pos) + +#define CSPI_INT_CTRL_BUS_TIMEOUT_INT_EN_Pos (10) +#define CSPI_INT_CTRL_BUS_TIMEOUT_INT_EN_Msk (0x1UL << CSPI_INT_CTRL_BUS_TIMEOUT_INT_EN_Pos) + +#define CSPI_INT_CTRL_TX_INT_THREASHOLD_Pos (16) +#define CSPI_INT_CTRL_TX_INT_THREASHOLD_Msk (0xFUL << CSPI_INT_CTRL_TX_INT_THREASHOLD_Pos) + +#define CSPI_INT_CTRL_RX_INT_THREASHOLD_Pos (20) +#define CSPI_INT_CTRL_RX_INT_THREASHOLD_Msk (0xFUL << CSPI_INT_CTRL_RX_INT_THREASHOLD_Pos) +/** @} */ + +/** @name TIMEOUT_CYCLE - CSPI_TIMEOUT_CYCLE register */ +/** @{ */ +#define CSPI_TIMEOUT_CYCLE_RX_TIMEOUT_CYCLE_Pos (0) +#define CSPI_TIMEOUT_CYCLE_RX_TIMEOUT_CYCLE_Msk (0xFFFFFFUL << CSPI_TIMEOUT_CYCLE_RX_TIMEOUT_CYCLE_Pos) +/** @} */ + +/** @name STATS_CTRL -CSPI_STATS_CTRL register */ +/** @{ */ +#define CSPI_STATS_CTRL_TX_UNDERRUN_RUN_Pos (0) +#define CSPI_STATS_CTRL_TX_UNDERRUN_RUN_Msk (0x1UL << CSPI_STATS_CTRL_TX_UNDERRUN_RUN_Pos) + +#define CSPI_STATS_CTRL_TX_DMA_ERR_Pos (1) +#define CSPI_STATS_CTRL_TX_DMA_ERR_Msk (0x1UL << CSPI_STATS_CTRL_TX_DMA_ERR_Pos) + +#define CSPI_STATS_CTRL_TX_DAT_RDY_Pos (2) +#define CSPI_STATS_CTRL_TX_DAT_RDY_Msk (0x1UL << CSPI_STATS_CTRL_TX_DAT_RDY_Pos) + +#define CSPI_STATS_CTRL_RX_OVERFLOW_Pos (3) +#define CSPI_STATS_CTRL_RX_OVERFLOW_Msk (0x1UL << CSPI_STATS_CTRL_RX_OVERFLOW_Pos) + +#define CSPI_STATS_CTRL_RX_DMA_ERR_Pos (4) +#define CSPI_STATS_CTRL_RX_DMA_ERR_Msk (0x1UL << CSPI_STATS_CTRL_RX_DMA_ERR_Pos) + +#define CSPI_STATS_CTRL_RX_DAT_RDY_Pos (5) +#define CSPI_STATS_CTRL_RX_DAT_RDY_Msk (0x1UL << CSPI_STATS_CTRL_RX_DAT_RDY_Pos) + +#define CSPI_STATS_CTRL_RX_FIFO_TIMEOUT_Pos (6) +#define CSPI_STATS_CTRL_RX_FIFO_TIMEOUT_Msk (0x1UL << CSPI_STATS_CTRL_RX_FIFO_TIMEOUT_Pos) + +#define CSPI_STATS_CTRL_FS_ERR_Pos (7) +#define CSPI_STATS_CTRL_FS_ERR_Msk (0xFUL << CSPI_STATS_CTRL_FS_ERR_Pos) + +#define CSPI_STATS_CTRL_FRAME_START_Pos (11) +#define CSPI_STATS_CTRL_FRAME_START_Msk (0x1UL << CSPI_STATS_CTRL_FRAME_START_Pos) + +#define CSPI_STATS_CTRL_FRAME_END_Pos (12) +#define CSPI_STATS_CTRL_FRAME_END_Msk (0x1UL << CSPI_STATS_CTRL_FRAME_END_Pos) + +#define CSPI_STATS_CTRL_TX_FIFO_LEVEL_Pos (13) +#define CSPI_STATS_CTRL_TX_FIFO_LEVEL_Msk (0x3FUL << CSPI_STATS_CTRL_TX_FIFO_LEVEL_Pos) + +#define CSPI_STATS_CTRL_RX_FIFO_LEVEL_Pos (19) +#define CSPI_STATS_CTRL_RX_FIFO_LEVEL_Msk (0x3FUL << CSPI_STATS_CTRL_RX_FIFO_LEVEL_Pos) + +#define CSPI_STATS_CTRL_CSPI_BUS_TIMEOUT_Pos (25) +#define CSPI_STATS_CTRL_CSPI_BUS_TIMEOUT_Msk (0x1UL << CSPI_STATS_CTRL_CSPI_BUS_TIMEOUT_Pos) +/** @} */ + + +/** @name RFIFO - CSPI_RFIFO register */ +/** @{ */ +#define CSPI_RFIFO_DATA_Pos (0) +#define CSPI_RFIFO_DATA_Msk (0xFFFFFFFFUL << CSPI_RFIFO_DATA_Pos) +/** @} */ + +/** @name TFIFO - CSPI_TFIFO register */ +/** @{ */ +#define CSPI_TFIFO_DAT_Pos (0) +#define CSPI_TFIFO_DAT_Msk (0xFFFFFFFFUL << CSPI_TFIFO_DAT_Pos) +/** @} */ + +/** @name SPI_CTRL - CAMERA_SPI_CTRL register */ +/** @{ */ +#define CSPI_ENABLE_Pos (0) +#define CSPI_ENABLE_Msk (0x1UL << CSPI_ENABLE_Pos) + +#define CSPI_CS_EN_Pos (1) +#define CSPI_CS_EN_Msk (0x1UL << CSPI_CS_EN_Pos) + +#define CSPI_RXD_WID_Pos (2) +#define CSPI_RXD_WID_Msk (0x1UL << CSPI_RXD_WID_Pos) + +#define CSPI_RXD_SEQ_Pos (3) +#define CSPI_RXD_SEQ_Msk (0x1UL << CSPI_RXD_SEQ_Pos) + +#define CSPI_CPOL_Pos (4) +#define CSPI_CPOL_Msk (0x1UL << CSPI_CPOL_Pos) + +#define CSPI_CPHA_Pos (5) +#define CSPI_CPHA_Msk (0x1UL << CSPI_CPHA_Pos) + +#define CSPI_FRAME_PROC_EN_Pos (6) +#define CSPI_FRAME_PROC_EN_Msk (0x1UL << CSPI_FRAME_PROC_EN_Pos) + +#define CSPI_FILL_Y_ONLY_Pos (7) +#define CSPI_FILL_Y_ONLY_Msk (0x1UL << CSPI_FILL_Y_ONLY_Pos) + +#define CSPI_HW_INIT_EN_Pos (8) +#define CSPI_HW_INIT_EN_Msk (0x1UL << CSPI_HW_INIT_EN_Pos) + +#define CSPI_LS_CHECK_EN_Pos (9) +#define CSPI_LS_CHECK_EN_Msk (0x1UL << CSPI_LS_CHECK_EN_Pos) + +#define CSPI_DP_CHECK_EN_Pos (10) +#define CSPI_DP_CHECK_EN_Msk (0x1UL << CSPI_DP_CHECK_EN_Pos) + +#define CSPI_FRAME_PROC_INIT_EN_Pos (11) +#define CSPI_FRAME_PROC_INIT_EN_Msk (0x1UL << CSPI_FRAME_PROC_INIT_EN_Pos) + +#define CSPI_ROW_SCALE_RATIO_Pos (12) +#define CSPI_ROW_SCALE_RATIO_Msk (0xFUL << CSPI_ROW_SCALE_RATIO_Pos) + +#define CSPI_COL_SCALE_RATIO_Pos (16) +#define CSPI_COL_SCALE_RATIO_Msk (0xFUL << CSPI_COL_SCALE_RATIO_Pos) + +#define CSPI_SCALE_BYTES_Pos (20) +#define CSPI_SCALE_BYTES_Msk (0x3UL << CSPI_SCALE_BYTES_Pos) +/** @} */ + +/** @name CG_CTRL - AUTO_CG_CTRL register */ +/** @{ */ +#define AUTO_CG_CTRL_AUTOCG_EN_Pos (0) +#define AUTO_CG_CTRL_AUTOCG_EN_Msk (0x1UL << AUTO_CG_CTRL_AUTOCG_EN_Pos) +/** @} */ + +/** @name FRAME_INFO0 - CSPI_FRAME_INFO0 register */ +/** @{ */ +#define CSPI_FRAME_INFO0_BUS_TIMEOUT_CYCLE_Pos (0) +#define CSPI_FRAME_INFO0_BUS_TIMEOUT_CYCLE_Msk (0xFFFFFFUL << CSPI_FRAME_INFO0_BUS_TIMEOUT_CYCLE_Pos) + +#define CSPI_FRAME_INFO0_DATA_ID_Pos (24) +#define CSPI_FRAME_INFO0_DATA_ID_Msk (0xFFUL << CSPI_FRAME_INFO0_DATA_ID_Pos) +/** @} */ + +/** @name FRAME_INFO1 - CSPI_FRAME_INFO1 register */ +/** @{ */ +#define CSPI_FRAME_INFO1_IMAGE_HEIGHT_Pos (0) +#define CSPI_FRAME_INFO1_IMAGE_HEIGHT_Msk (0xFFFFUL << CSPI_FRAME_INFO1_IMAGE_HEIGHT_Pos) + +#define CSPI_FRAME_INFO1_IMAGE_WIDTH_Pos (16) +#define CSPI_FRAME_INFO1_IMAGE_WIDTH_Msk (0xFFFFUL << CSPI_FRAME_INFO1_IMAGE_WIDTH_Pos) +/** @} */ + +/** @name DEBUG_INFO - CSPI_DEBUG_INFO register */ +/** @{ */ +#define CSPI_DEBUG_INFO_CSPI_DEBUG_LINE_CNT_Pos (0) +#define CSPI_DEBUG_INFO_CSPI_DEBUG_LINE_CNT_Msk (0xFFFFUL << CSPI_DEBUG_INFO_CSPI_DEBUG_LINE_CNT_Pos) + +#define CSPI_DEBUG_INFO_CSPI_CS_Pos (16) +#define CSPI_DEBUG_INFO_CSPI_CS_Msk (0x7UL << CSPI_DEBUG_INFO_CSPI_CS_Pos) +/** @} */ + +/** @name INIT - CSPI_INIT register */ +/** @{ */ +#define CSPI_INIT_CSPI_INIT_Pos (0) +#define CSPI_INIT_CSPI_INIT_Msk (0x1UL << CSPI_INIT_CSPI_INIT_Pos) +/** @} */ + +/** @name LS_PACKET - CSPI_LS_PACKET register */ +/** @{ */ +#define CSPI_LS_PACKET_LS_PACKET_Pos (0) +#define CSPI_LS_PACKET_LS_PACKET_Msk (0xFFFFFFFFUL << CSPI_LS_PACKET_LS_PACKET_Pos) +/** @} */ + +/** @name DAT_PACKET - CSPI_DAT_PACKET register */ +/** @{ */ +#define CSPI_DAT_PACKET_DAT_PACKET_Pos (0) +#define CSPI_DAT_PACKET_DAT_PACKET_Msk (0xFFFFFFFFUL << CSPI_DAT_PACKET_DAT_PACKET_Pos) +/** @} */ + +/** @name LINE_INFO - CSPI_LINE_INFO register */ +/** @{ */ +#define CSPI_LINE_INFO_DP_SIZE_Pos (0) +#define CSPI_LINE_INFO_DP_SIZE_Msk (0xFFFFUL << CSPI_LINE_INFO_DP_SIZE_Pos) + +#define CSPI_LINE_INFO_LINE_ID_Pos (16) +#define CSPI_LINE_INFO_LINE_ID_Msk (0xFFFFUL << CSPI_LINE_INFO_LINE_ID_Pos) +/** @} */ + +/** Peripheral CSPI0 base pointer */ +#define CSPI0 ((CSPI_TypeDef *)MP_I2S0_BASE_ADDR) + +/** Peripheral CSPI1 base pointer */ +#define CSPI1 ((CSPI_TypeDef *)MP_I2S1_BASE_ADDR) + +/** @brief SPI peripheral instance number */ +#define CSPI_INSTANCE_NUM (2) + + +/** + * @} + */ /* end of group CSPI */ + +/** @addtogroup KPC KPC + * @{ + */ + +/** + * @brief KPC register layout typedef + * + */ +typedef struct { + __IO uint32_t DEBCTL; /**< Debounce Control Register, offset: 0x0 */ + __IO uint32_t KPCTL; /**< Keypad Control Register, offset: 0x4 */ + __IO uint32_t DICTL; /**< Direct Input Control Register, offset: 0x8 */ + __IO uint32_t KPENCTL; /**< Keypad Enable Register, offset: 0xC */ + __IO uint32_t DIENCTL; /**< Direct Input Enable Register, offset: 0x10 */ + __IO uint32_t AUTOCG; /**< Auto Gate Enable Register, offset: 0x14 */ + __IO uint32_t CLRCTL; /**< Direct Input Clear Control Register, offset: 0x18 */ + __I uint32_t KPSTAT; /**< Keypad Status Register, offset: 0x1C */ + __I uint32_t DISTAT; /**< Direct Input Status Register, offset: 0x20 */ +} KPC_TypeDef; + +/** @name DEBCTL - KPC_DEBCTL register */ +/** @{ */ +#define KPC_DEBCTL_DEBOUNCER_DEPTH_Pos (0) +#define KPC_DEBCTL_DEBOUNCER_DEPTH_Msk (0xFUL << KPC_DEBCTL_DEBOUNCER_DEPTH_Pos) + +#define KPC_DEBCTL_DEBOUNCER_TO0_THRD_Pos (4) +#define KPC_DEBCTL_DEBOUNCER_TO0_THRD_Msk (0xFUL << KPC_DEBCTL_DEBOUNCER_TO0_THRD_Pos) + +#define KPC_DEBCTL_DEBOUNCER_TO1_THRD_Pos (8) +#define KPC_DEBCTL_DEBOUNCER_TO1_THRD_Msk (0xFUL << KPC_DEBCTL_DEBOUNCER_TO1_THRD_Pos) + +#define KPC_DEBCTL_DEBOUNCER_TO_MCLK_RATIO_Pos (12) +#define KPC_DEBCTL_DEBOUNCER_TO_MCLK_RATIO_Msk (0xFUL << KPC_DEBCTL_DEBOUNCER_TO_MCLK_RATIO_Pos) +/** @} */ + +/** @name KPCTL - KPC_KPCTL register */ +/** @{ */ +#define KPC_KPCTL_POLARITY_Pos (0) +#define KPC_KPCTL_POLARITY_Msk (0x1UL << KPC_KPCTL_POLARITY_Pos) + +#define KPC_KPCTL_ROW_VLD_BITMAP_Pos (1) +#define KPC_KPCTL_ROW_VLD_BITMAP_Msk (0x1FUL << KPC_KPCTL_ROW_VLD_BITMAP_Pos) + +#define KPC_KPCTL_COL_VLD_BITMAP_Pos (6) +#define KPC_KPCTL_COL_VLD_BITMAP_Msk (0x1FUL << KPC_KPCTL_COL_VLD_BITMAP_Pos) + +#define KPC_KPCTL_SCAN_TO_DEBOUNCE_RATIO_Pos (11) +#define KPC_KPCTL_SCAN_TO_DEBOUNCE_RATIO_Msk (0x7UL << KPC_KPCTL_SCAN_TO_DEBOUNCE_RATIO_Pos) +/** @} */ + +/** @name DICTL - KPC_DICTL register */ +/** @{ */ +#define KPC_DICTL_INT_MODE_Pos (0) +#define KPC_DICTL_INT_MODE_Msk (0x3UL << KPC_DICTL_INT_MODE_Pos) + +#define KPC_DICTL_INT_EN_Pos (2) +#define KPC_DICTL_INT_EN_Msk (0x3FFUL << KPC_DICTL_INT_EN_Pos) +/** @} */ + +/** @name KPENCTL - KPC_KPENCTL register */ +/** @{ */ +#define KPC_KPENCTL_ENABLE_Pos (0) +#define KPC_KPENCTL_ENABLE_Msk (0x1UL << KPC_KPENCTL_ENABLE_Pos) +/** @} */ + +/** @name DIENCTL - KPC_DIENCTL register */ +/** @{ */ +#define KPC_DIENCTL_ENABLE_Pos (0) +#define KPC_DIENCTL_ENABLE_Msk (0x1UL << KPC_DIENCTL_ENABLE_Pos) +/** @} */ + +/** @name AUTOCG - KPC_AUTOCG register */ +/** @{ */ +#define KPC_AUTOCG_ENABLE_Pos (0) +#define KPC_AUTOCG_ENABLE_Msk (0x1UL << KPC_AUTOCG_ENABLE_Pos) +/** @} */ + +/** @name CLRCTL - KPC_CLRCTL register */ +/** @{ */ +#define KPC_CLRCTL_INPUT_INT_CLR_Pos (0) +#define KPC_CLRCTL_INPUT_INT_CLR_Msk (0x3FFUL << KPC_CLRCTL_INPUT_INT_CLR_Pos) + +#define KPC_CLRCTL_DEBOUNCER_CLR_Pos (10) +#define KPC_CLRCTL_DEBOUNCER_CLR_Msk (0x3FFUL << KPC_CLRCTL_DEBOUNCER_CLR_Pos) +/** @} */ + +/** @name KPSTAT - KPC_KPSTAT register */ +/** @{ */ +#define KPC_KPSTAT_STATUS_Pos (0) +#define KPC_KPSTAT_STATUS_Msk (0x1FFFFFFUL << KPC_KPSTAT_STATUS_Pos) +/** @} */ + +/** @name DISTAT - KPC_DISTAT register */ +/** @{ */ +#define KPC_DISTAT_INPUT_INT_NEG_STATUS_Pos (0) +#define KPC_DISTAT_INPUT_INT_NEG_STATUS_Msk (0x3FFUL << KPC_DISTAT_INPUT_INT_NEG_STATUS_Pos) + +#define KPC_DISTAT_INPUT_INT_POS_STATUS_Pos (10) +#define KPC_DISTAT_INPUT_INT_POS_STATUS_Msk (0x3FFUL << KPC_DISTAT_INPUT_INT_POS_STATUS_Pos) + +#define KPC_DISTAT_INPUT_STATUS_Pos (20) +#define KPC_DISTAT_INPUT_STATUS_Msk (0x3FFUL << KPC_DISTAT_INPUT_STATUS_Pos) +/** @} */ + +/** Peripheral KPC base pointer */ +#define KPC ((KPC_TypeDef *) AP_KPC_BASE_ADDR) + +/** + * @} + */ /* end of group KPC */ + +/** @addtogroup LPUSART LPUSART + * @{ + */ + +/** + * @brief LPUSART CORE part register layout typedef + * + */ +typedef struct { + __IO uint32_t CSR; /**< Control and Status Register, offset: 0x0 */ + __IO uint32_t TCR; /**< Timeout Control Register, offset: 0x4 */ + __I uint32_t RBR; /**< Receive Buffer Register, offset: 0x8 */ + __IO uint32_t FCSR; /**< FIFO Control and Status Register, offset: 0xC */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t IIR; /**< Interrupt Identification Register, offset: 0x14 */ + __IO uint32_t DCR; /**< DMA Control Register, offset: 0x18 */ + __IO uint32_t TSR; /**< Timeout Status Register, offset: 0x1C */ +} LPUSARTCORE_TypeDef; + +/** + * @brief LPUSART AON part register layout typedef + * + */ +typedef struct { + __IO uint32_t CR0; /**< Control Register 0, offset: 0x0 */ + uint32_t RESERVED_0[138]; + __IO uint32_t CR1; /**< Control Register 1, offset: 0x0 */ + __IO uint32_t DLR; /**< Divisor Latch Register, offset: 0x4 */ + __IO uint32_t LCR; /**< Line Control Register, offset: 0x8 */ + __IO uint32_t SCR; /**< Stop Control Register, offset: 0xC */ + __IO uint32_t FSR; /**< FIFO Status Register, offset: 0x10 */ + __IO uint32_t IIR; /**< Interrupt Identification Register, offset: 0x14 */ + __IO uint32_t SR; /**< Status Register, offset: 0x18 */ +} LPUSARTAON_TypeDef; + +/** @name CSR - LPUSART_CSR register */ +/** @{ */ +#define LPUSARTCORE_CSR_AON_EN_Pos (0) +#define LPUSARTCORE_CSR_AON_EN_Msk (0x1UL << LPUSARTCORE_CSR_AON_EN_Pos) + +#define LPUSARTCORE_CSR_AUTO_CG_EN_Pos (1) +#define LPUSARTCORE_CSR_AUTO_CG_EN_Msk (0x1UL << LPUSARTCORE_CSR_AUTO_CG_EN_Pos) +/** @} */ + +/** @name TCR - LPUSARTCORE_TCR register */ +/** @{ */ +#define LPUSARTCORE_TCR_TIMEOUT_THRLD_Pos (0) +#define LPUSARTCORE_TCR_TIMEOUT_THRLD_Msk (0xFFFFFUL << LPUSARTCORE_TCR_TIMEOUT_THRLD_Pos) + +#define LPUSARTCORE_TCR_TOCNT_SWCLR_Pos (30) +#define LPUSARTCORE_TCR_TOCNT_SWCLR_Msk (0x1UL << LPUSARTCORE_TCR_TOCNT_SWCLR_Pos) + +#define LPUSARTCORE_TCR_TOCNT_SWTRG_Pos (31) +#define LPUSARTCORE_TCR_TOCNT_SWTRG_Msk (0x1UL << LPUSARTCORE_TCR_TOCNT_SWTRG_Pos) +/** @} */ + +/** @name RBR - LPUSARTCORE_RBR register */ +/** @{ */ +#define LPUSARTCORE_RBR_RX_BUF_Pos (0) +#define LPUSARTCORE_RBR_RX_BUF_Msk (0xFFUL << LPUSARTCORE_RBR_RX_BUF_Pos) +/** @} */ + +/** @name FCSR - LPUSARTCORE_FCSR register */ +/** @{ */ +#define LPUSARTCORE_FCSR_FLUSH_RXFIFO_Pos (0) +#define LPUSARTCORE_FCSR_FLUSH_RXFIFO_Msk (0x1UL << LPUSARTCORE_FCSR_FLUSH_RXFIFO_Pos) + +#define LPUSARTCORE_FCSR_RXFIFO_EMPTY_Pos (1) +#define LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk (0x1UL << LPUSARTCORE_FCSR_RXFIFO_EMPTY_Pos) + +#define LPUSARTCORE_FCSR_RXFIFO_FULL_Pos (2) +#define LPUSARTCORE_FCSR_RXFIFO_FULL_Msk (0x1UL << LPUSARTCORE_FCSR_RXFIFO_FULL_Pos) + +#define LPUSARTCORE_FCSR_AON_RX_BUSY_Pos (3) +#define LPUSARTCORE_FCSR_AON_RX_BUSY_Msk (0x1UL << LPUSARTCORE_FCSR_AON_RX_BUSY_Pos) + +#define LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Pos (4) +#define LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk (0x1UL << LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Pos) + +#define LPUSARTCORE_FCSR_AON_RXFIFO_FULL_Pos (5) +#define LPUSARTCORE_FCSR_AON_RXFIFO_FULL_Msk (0x1UL << LPUSARTCORE_FCSR_AON_RXFIFO_FULL_Pos) + +#define LPUSARTCORE_FCSR_AON_STOP_FLAG_Pos (6) +#define LPUSARTCORE_FCSR_AON_STOP_FLAG_Msk (0x1UL << LPUSARTCORE_FCSR_AON_STOP_FLAG_Pos) + +#define LPUSARTCORE_FCSR_RXFIFO_NUM_Pos (8) +#define LPUSARTCORE_FCSR_RXFIFO_NUM_Msk (0x7FUL << LPUSARTCORE_FCSR_RXFIFO_NUM_Pos) + +#define LPUSARTCORE_FCSR_RXFIFO_THRLD_Pos (16) +#define LPUSARTCORE_FCSR_RXFIFO_THRLD_Msk (0x3FUL << LPUSARTCORE_FCSR_RXFIFO_THRLD_Pos) +/** @} */ + +/** @name IER - LPUSARTCORE_IER register */ +/** @{ */ +#define LPUSARTCORE_IER_AON_RX_OVERRUN_Pos (1) +#define LPUSARTCORE_IER_AON_RX_OVERRUN_Msk (0x1UL << LPUSARTCORE_IER_AON_RX_OVERRUN_Pos) + +#define LPUSARTCORE_IER_AON_RX_PARITY_Pos (2) +#define LPUSARTCORE_IER_AON_RX_PARITY_Msk (0x1UL << LPUSARTCORE_IER_AON_RX_PARITY_Pos) + +#define LPUSARTCORE_IER_AON_RX_FRMERR_Pos (3) +#define LPUSARTCORE_IER_AON_RX_FRMERR_Msk (0x1UL << LPUSARTCORE_IER_AON_RX_FRMERR_Pos) + +#define LPUSARTCORE_IER_RX_DATA_AVAIL_Pos (9) +#define LPUSARTCORE_IER_RX_DATA_AVAIL_Msk (0x1UL << LPUSARTCORE_IER_RX_DATA_AVAIL_Pos) + +#define LPUSARTCORE_IER_RX_TIMEOUT_Pos (10) +#define LPUSARTCORE_IER_RX_TIMEOUT_Msk (0x1UL << LPUSARTCORE_IER_RX_TIMEOUT_Pos) + +#define LPUSARTCORE_IER_RX_OVERRUN_Pos (11) +#define LPUSARTCORE_IER_RX_OVERRUN_Msk (0x1UL << LPUSARTCORE_IER_RX_OVERRUN_Pos) +/** @} */ + +/** @name IIR - LPUSARTCORE_IIR register */ +/** @{ */ +#define LPUSARTCORE_IIR_CLR_Pos (0) +#define LPUSARTCORE_IIR_CLR_Msk (0x1UL << LPUSARTCORE_IIR_CLR_Pos) + +#define LPUSARTCORE_IIR_AON_RX_OVERRUN_Pos (1) +#define LPUSARTCORE_IIR_AON_RX_OVERRUN_Msk (0x1UL << LPUSARTCORE_IIR_AON_RX_OVERRUN_Pos) + +#define LPUSARTCORE_IIR_AON_RX_PARITY_Pos (2) +#define LPUSARTCORE_IIR_AON_RX_PARITY_Msk (0x1UL << LPUSARTCORE_IIR_AON_RX_PARITY_Pos) + +#define LPUSARTCORE_IIR_AON_RX_FRMERR_Pos (3) +#define LPUSARTCORE_IIR_AON_RX_FRMERR_Msk (0x1UL << LPUSARTCORE_IIR_AON_RX_FRMERR_Pos) + +#define LPUSARTCORE_IIR_RX_DATA_AVAIL_Pos (9) +#define LPUSARTCORE_IIR_RX_DATA_AVAIL_Msk (0x1UL << LPUSARTCORE_IIR_RX_DATA_AVAIL_Pos) + +#define LPUSARTCORE_IIR_RX_TIMEOUT_Pos (10) +#define LPUSARTCORE_IIR_RX_TIMEOUT_Msk (0x1UL << LPUSARTCORE_IIR_RX_TIMEOUT_Pos) + +#define LPUSARTCORE_IIR_RX_OVERRUN_Pos (11) +#define LPUSARTCORE_IIR_RX_OVERRUN_Msk (0x1UL << LPUSARTCORE_IIR_RX_OVERRUN_Pos) +/** @} */ + +/** @name DCR - LPUSARTCORE_DCR register */ +/** @{ */ +#define LPUSARTCORE_DCR_RX_REQ_EN_Pos (0) +#define LPUSARTCORE_DCR_RX_REQ_EN_Msk (0x1UL << LPUSARTCORE_DCR_RX_REQ_EN_Pos) + +#define LPUSARTCORE_DCR_RX_BUSY_Pos (1) +#define LPUSARTCORE_DCR_RX_BUSY_Msk (0x1UL << LPUSARTCORE_DCR_RX_BUSY_Pos) +/** @} */ + +/** @name TSR - LPUSARTCORE_TSR register */ +/** @{ */ +#define LPUSARTCORE_TSR_TOCNT_Pos (0) +#define LPUSARTCORE_TSR_TOCNT_Msk (0xFFFFFUL << LPUSARTCORE_TSR_TOCNT_Pos) + +#define LPUSARTCORE_TSR_TOCNT_REACH_Pos (31) +#define LPUSARTCORE_TSR_TOCNT_REACH_Msk (0x1UL << LPUSARTCORE_TSR_TOCNT_REACH_Pos) +/** @} */ + +/** @name CR0 - LPUSARTAON_CR0 register */ +/** @{ */ +#define LPUSARTAON_CR0_RX_ENABLE_Pos (0) +#define LPUSARTAON_CR0_RX_ENABLE_Msk (0x1UL << LPUSARTAON_CR0_RX_ENABLE_Pos) + +#define LPUSARTAON_CR0_CLK_ENABLE_Pos (1) +#define LPUSARTAON_CR0_CLK_ENABLE_Msk (0x1UL << LPUSARTAON_CR0_CLK_ENABLE_Pos) +/** @} */ + +/** @name CR1 - LPUSARTAON_CR1 register */ +/** @{ */ +#define LPUSARTAON_CR1_ENABLE_Pos (0) +#define LPUSARTAON_CR1_ENABLE_Msk (0x1UL << LPUSARTAON_CR1_ENABLE_Pos) + +#define LPUSARTAON_CR1_ACG_EN_Pos (1) +#define LPUSARTAON_CR1_ACG_EN_Msk (0x1UL << LPUSARTAON_CR1_ACG_EN_Pos) + +#define LPUSARTAON_CR1_AUTO_ADJ_Pos (2) +#define LPUSARTAON_CR1_AUTO_ADJ_Msk (0x1UL << LPUSARTAON_CR1_AUTO_ADJ_Pos) +/** @} */ + +/** @name DLR - LPUSARTAON_DLR register */ +/** @{ */ +#define LPUSARTAON_DLR_DIVISOR_Pos (0) +#define LPUSARTAON_DLR_DIVISOR_Msk (0xFFFUL << LPUSARTAON_DLR_DIVISOR_Pos) +/** @} */ + +/** @name LCR - LPUSARTAON_LCR register */ +/** @{ */ +#define LPUSARTAON_LCR_CHAR_LEN_Pos (0) +#define LPUSARTAON_LCR_CHAR_LEN_Msk (0x3UL << LPUSARTAON_LCR_CHAR_LEN_Pos) + +#define LPUSARTAON_LCR_STOPBIT_DETECT_EN_Pos (2) +#define LPUSARTAON_LCR_STOPBIT_DETECT_EN_Msk (0x1UL << LPUSARTAON_LCR_STOPBIT_DETECT_EN_Pos) + +#define LPUSARTAON_LCR_PARITY_EN_Pos (3) +#define LPUSARTAON_LCR_PARITY_EN_Msk (0x1UL << LPUSARTAON_LCR_PARITY_EN_Pos) + +#define LPUSARTAON_LCR_EVEN_PARITY_Pos (4) +#define LPUSARTAON_LCR_EVEN_PARITY_Msk (0x1UL << LPUSARTAON_LCR_EVEN_PARITY_Pos) +/** @} */ + +/** @name SCR - LPUSARTAON_SCR register */ +/** @{ */ +#define LPUSARTAON_SCR_STOP_SW_SET_Pos (0) +#define LPUSARTAON_SCR_STOP_SW_SET_Msk (0x1UL << LPUSARTAON_SCR_STOP_SW_SET_Pos) + +#define LPUSARTAON_SCR_STOP_SW_CLR_Pos (1) +#define LPUSARTAON_SCR_STOP_SW_CLR_Msk (0x1UL << LPUSARTAON_SCR_STOP_SW_CLR_Pos) + +#define LPUSARTAON_SCR_STOP_FLAG_Pos (3) +#define LPUSARTAON_SCR_STOP_FLAG_Msk (0x1UL << LPUSARTAON_SCR_STOP_FLAG_Pos) +/** @} */ + +/** @name FSR - LPUSARTAON_FSR register */ +/** @{ */ +#define LPUSARTAON_FSR_RXFIFO_EMPTY_Pos (1) +#define LPUSARTAON_FSR_RXFIFO_EMPTY_Msk (0x1UL << LPUSARTAON_FSR_RXFIFO_EMPTY_Pos) + +#define LPUSARTAON_FSR_RXFIFO_FULL_Pos (2) +#define LPUSARTAON_FSR_RXFIFO_FULL_Msk (0x1UL << LPUSARTAON_FSR_RXFIFO_FULL_Pos) + +#define LPUSARTAON_FSR_RX_BUSY_Pos (3) +#define LPUSARTAON_FSR_RX_BUSY_Msk (0x1UL << LPUSARTAON_FSR_RX_BUSY_Pos) + +#define LPUSARTAON_FSR_RXFIFO_NUM_Pos (8) +#define LPUSARTAON_FSR_RXFIFO_NUM_Msk (0xFUL << LPUSARTAON_FSR_RXFIFO_NUM_Pos) +/** @} */ + +/** @name IIR - LPUSARTAON_IIR register */ +/** @{ */ +#define LPUSARTAON_IIR_RXFIFO_OVERRUN_Pos (1) +#define LPUSARTAON_IIR_RXFIFO_OVERRUN_Msk (0x1UL << LPUSARTAON_IIR_RXFIFO_OVERRUN_Pos) + +#define LPUSARTAON_IIR_PARITY_ERR_Pos (2) +#define LPUSARTAON_IIR_PARITY_ERR_Msk (0x1UL << LPUSARTAON_IIR_PARITY_ERR_Pos) + +#define LPUSARTAON_IIR_FRAME_ERR_Pos (3) +#define LPUSARTAON_IIR_FRAME_ERR_Msk (0x1UL << LPUSARTAON_IIR_FRAME_ERR_Pos) +/** @} */ + +/** @name LSR - LPUSARTAON_LSR register */ +/** @{ */ +#define LPUSARTAON_LSR_STATUS_Pos (0) +#define LPUSARTAON_LSR_STATUS_Msk (0xFFFFFFFFUL << LPUSARTAON_LSR_STATUS_Pos) +/** @} */ + +/** Peripheral LPUART base pointer */ +#define LPUSART_AON ((LPUSARTAON_TypeDef *) LPUSARTAON_BASE_ADDR) +#define LPUSART_CORE ((LPUSARTCORE_TypeDef *) MP_LPUART_BASE_ADDR) +/** + * @} + */ /* end of group LPUSART */ + +/** @addtogroup OWC OWC + * @{ + */ + +/** + * @brief OWC register layout typedef + * + */ +typedef struct { + __IO uint32_t ECR; /**< Enable Control Register, offset: 0x0 */ + __IO uint32_t CDR; /**< Clock Divider Register, offset: 0x4 */ + __IO uint32_t IOR; /**< IO Control/Status Register, offset: 0x8 */ + __IO uint32_t DFR; /**< Data Format Register, offset: 0xC */ + __IO uint32_t OCR; /**< Operation Command Register, offset: 0x10 */ + __IO uint32_t TBR; /**< Transmit Buffer Register, offset: 0x14 */ + __IO uint32_t RBR; /**< Receive Buffer Register, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ + __IO uint32_t IIR; /**< Interrupt Identification Register, offset: 0x20 */ + __IO uint32_t CSR; /**< Control Status Register, offset: 0x24 */ + __IO uint32_t RTCR; /**< Reset Timing Control Register, offset: 0x28 */ + __IO uint32_t ATCR; /**< Access Timing Control Register, offset: 0x2C */ +} OWC_TypeDef; + + +/** @name ECR - OWC_ECR register */ +/** @{ */ +#define OWC_ECR_ENABLE_Pos (0) +#define OWC_ECR_ENABLE_Msk (0x1UL << OWC_ECR_ENABLE_Pos) + +#define OWC_ECR_CLK_EN_Pos (1) +#define OWC_ECR_CLK_EN_Msk (0x1UL << OWC_ECR_CLK_EN_Pos) + +#define OWC_ECR_AUTO_CGEN_Pos (2) +#define OWC_ECR_AUTO_CGEN_Msk (0x1UL << OWC_ECR_AUTO_CGEN_Pos) + +#define OWC_ECR_RXD_MJR_Pos (3) +#define OWC_ECR_RXD_MJR_Msk (0x1UL << OWC_ECR_RXD_MJR_Pos) +/** @} */ + +/** @name CDR - OWC_CDR register */ +/** @{ */ +#define OWC_CDR_CLKUS_DIVIDER_Pos (0) +#define OWC_CDR_CLKUS_DIVIDER_Msk (0xFFUL << OWC_CDR_CLKUS_DIVIDER_Pos) +/** @} */ + +/** @name IOR - OWC_IOR register */ +/** @{ */ +#define OWC_IOR_SWMODE_EN_Pos (0) +#define OWC_IOR_SWMODE_EN_Msk (0x1UL << OWC_IOR_SWMODE_EN_Pos) + +#define OWC_IOR_SWOEN_Pos (1) +#define OWC_IOR_SWOEN_Msk (0x1UL << OWC_IOR_SWOEN_Pos) + +#define OWC_IOR_SWOUT_Pos (2) +#define OWC_IOR_SWOUT_Msk (0x1UL << OWC_IOR_SWOUT_Pos) + +#define OWC_IOR_SWIN_Pos (3) +#define OWC_IOR_SWIN_Msk (0x1UL << OWC_IOR_SWIN_Pos) + +#define OWC_IOR_SWIN_SYNC_Pos (4) +#define OWC_IOR_SWIN_SYNC_Msk (0x1UL << OWC_IOR_SWIN_SYNC_Pos) +/** @} */ + +/** @name DFR - OWC_DFR register */ +/** @{ */ +#define OWC_DFR_MODE_Pos (0) +#define OWC_DFR_MODE_Msk (0x1UL << OWC_DFR_MODE_Pos) + +#define OWC_DFR_BYTE_ENDIAN_Pos (1) +#define OWC_DFR_BYTE_ENDIAN_Msk (0x1UL << OWC_DFR_BYTE_ENDIAN_Pos) + +#define OWC_DFR_POLARITY_Pos (2) +#define OWC_DFR_POLARITY_Msk (0x1UL << OWC_DFR_POLARITY_Pos) +/** @} */ + +/** @name OCR - OWC_OCR register */ +/** @{ */ +#define OWC_OCR_FLUSH_Pos (0) +#define OWC_OCR_FLUSH_Msk (0x1UL << OWC_OCR_FLUSH_Pos) + +#define OWC_OCR_RESET_Pos (1) +#define OWC_OCR_RESET_Msk (0x1UL << OWC_OCR_RESET_Pos) + +#define OWC_OCR_WRITE_Pos (2) +#define OWC_OCR_WRITE_Msk (0x1UL << OWC_OCR_WRITE_Pos) + +#define OWC_OCR_READ_Pos (3) +#define OWC_OCR_READ_Msk (0x1UL << OWC_OCR_READ_Pos) +/** @} */ + +/** @name TBR - OWC_TBR register */ +/** @{ */ +#define OWC_TBR_TX_BUF_Pos (0) +#define OWC_TBR_TX_BUF_Msk (0xFFUL << OWC_TBR_TX_BUF_Pos) +/** @} */ + +/** @name RBR - OWC_RBR register */ +/** @{ */ +#define OWC_RBR_RX_BUF_Pos (0) +#define OWC_RBR_RX_BUF_Msk (0xFFUL << OWC_RBR_RX_BUF_Pos) +/** @} */ + +/** @name IER - OWC_IER register */ +/** @{ */ +#define OWC_IER_RESET_Pos (1) +#define OWC_IER_RESET_Msk (0x1UL << OWC_IER_RESET_Pos) + +#define OWC_IER_RESET_PD_Pos (2) +#define OWC_IER_RESET_PD_Msk (0x1UL << OWC_IER_RESET_PD_Pos) + +#define OWC_IER_WRITE_Pos (3) +#define OWC_IER_WRITE_Msk (0x1UL << OWC_IER_WRITE_Pos) + +#define OWC_IER_READ_Pos (4) +#define OWC_IER_READ_Msk (0x1UL << OWC_IER_READ_Pos) +/** @} */ + +/** @name IIR - OWC_IIR register */ +/** @{ */ +#define OWC_IIR_INT_CLR_Pos (0) +#define OWC_IIR_INT_CLR_Msk (0x1UL << OWC_IIR_INT_CLR_Pos) + +#define OWC_IIR_RESET_Pos (1) +#define OWC_IIR_RESET_Msk (0x1UL << OWC_IIR_RESET_Pos) + +#define OWC_IIR_RESET_PD_Pos (2) +#define OWC_IIR_RESET_PD_Msk (0x1UL << OWC_IIR_RESET_PD_Pos) + +#define OWC_IIR_WRITE_Pos (3) +#define OWC_IIR_WRITE_Msk (0x1UL << OWC_IIR_WRITE_Pos) + +#define OWC_IIR_READ_Pos (4) +#define OWC_IIR_READ_Msk (0x1UL << OWC_IIR_READ_Pos) + +#define OWC_IIR_RESET_PD_RES_Pos (7) +#define OWC_IIR_RESET_PD_RES_Msk (0x1UL << OWC_IIR_RESET_PD_RES_Pos) +/** @} */ + +/** @name CSR - OWC_CSR register */ +/** @{ */ +#define OWC_CSR_SFTREG_Pos (0) +#define OWC_CSR_SFTREG_Msk (0xFFUL << OWC_CSR_SFTREG_Pos) + +#define OWC_CSR_SFTCNT_Pos (8) +#define OWC_CSR_SFTCNT_Msk (0x7UL << OWC_CSR_SFTCNT_Pos) + +#define OWC_CSR_FSM_Pos (12) +#define OWC_CSR_FSM_Msk (0x7UL << OWC_CSR_FSM_Pos) + +#define OWC_CSR_USCNT_Pos (16) +#define OWC_CSR_USCNT_Msk (0x3FFUL << OWC_CSR_USCNT_Pos) + +#define OWC_CSR_MODE_Pos (28) +#define OWC_CSR_MODE_Msk (0x3UL << OWC_CSR_MODE_Pos) + +#define OWC_CSR_USCLK_ENABLE_Pos (31) +#define OWC_CSR_USCLK_ENABLE_Msk (0x1UL << OWC_CSR_USCLK_ENABLE_Pos) +/** @} */ + +/** @name RTCR - OWC_RTCR register */ +/** @{ */ +#define OWC_RTCR_SEND_DIV10_Pos (0) +#define OWC_RTCR_SEND_DIV10_Msk (0x7FUL << OWC_RTCR_SEND_DIV10_Pos) + +#define OWC_RTCR_WAIT_DIV10_Pos (8) +#define OWC_RTCR_WAIT_DIV10_Msk (0x7FUL << OWC_RTCR_WAIT_DIV10_Pos) + +#define OWC_RTCR_RDDLY_MIN_Pos (16) +#define OWC_RTCR_RDDLY_MIN_Msk (0x3FUL << OWC_RTCR_RDDLY_MIN_Pos) + +#define OWC_RTCR_RDDLY_MAX_DIV10_Pos (24) +#define OWC_RTCR_RDDLY_MAX_DIV10_Msk (0x1FUL << OWC_RTCR_RDDLY_MAX_DIV10_Pos) +/** @} */ + +/** @name ATCR - OWC_ATCR register */ +/** @{ */ +#define OWC_ATCR_RECO_Pos (0) +#define OWC_ATCR_RECO_Msk (0x7UL << OWC_ATCR_RECO_Pos) + +#define OWC_ATCR_SLOT_DIV10_Pos (8) +#define OWC_ATCR_SLOT_DIV10_Msk (0xFUL << OWC_ATCR_SLOT_DIV10_Pos) + +#define OWC_ATCR_START_Pos (12) +#define OWC_ATCR_START_Msk (0x7UL << OWC_ATCR_START_Pos) + +#define OWC_ATCR_WRDLY_Pos (16) +#define OWC_ATCR_WRDLY_Msk (0x1FUL << OWC_ATCR_WRDLY_Pos) + +#define OWC_ATCR_RDDLY_Pos (24) +#define OWC_ATCR_RDDLY_Msk (0x1FUL << OWC_ATCR_RDDLY_Pos) +/** @} */ + +/** Peripheral OWC base pointer */ +#define OWC ((OWC_TypeDef *) AP_ONEWIRE_BASE_ADDR) + +/** + * @} + */ /* end of group OWC */ + + +/** @addtogroup PAD PAD + * @{ + */ + +/** max number of addr in PAD */ +#define PAD_ADDR_MAX_NUM (61U) + +/** + * @brief PAD register layout typedef + * + */ +typedef struct { + __IO uint32_t PCR[PAD_ADDR_MAX_NUM]; /**< PAD Control Register n, array offset: 0x0, array step:0x4 */ +} PAD_TypeDef; + +/** @name PCR - PAD_PCR register */ +/** @{ */ +#define PAD_PCR_MUX_Pos (4) +#define PAD_PCR_MUX_Msk (0x7UL << PAD_PCR_MUX_Pos) + +#define PAD_PCR_PULL_UP_ENABLE_Pos (8) +#define PAD_PCR_PULL_UP_ENABLE_Msk (0x1UL << PAD_PCR_PULL_UP_ENABLE_Pos) + +#define PAD_PCR_PULL_DOWN_ENABLE_Pos (9) +#define PAD_PCR_PULL_DOWN_ENABLE_Msk (0x1UL << PAD_PCR_PULL_DOWN_ENABLE_Pos) + +#define PAD_PCR_PULL_SELECT_Pos (10) +#define PAD_PCR_PULL_SELECT_Msk (0x1UL << PAD_PCR_PULL_SELECT_Pos) + +#define PAD_PCR_INPUT_BUFFER_ENABLE_Pos (13) +#define PAD_PCR_INPUT_BUFFER_ENABLE_Msk (0x1UL << PAD_PCR_INPUT_BUFFER_ENABLE_Pos) +/** @} */ + +/** Peripheral PAD base pointer */ +#define PAD ((PAD_TypeDef *) MP_PAD_BASE_ADDR) + +/** + * @} + */ /* end of group PAD */ + +/** @addtogroup SPI SPI + * @{ + */ + +/** + * @brief SPI register layout typedef + * + */ +typedef struct { + __IO uint32_t CR0; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CR1; /**< Control Register 1, offset: 0x4 */ + __IO uint32_t DR; /**< Data Register, offset: 0x8 */ + __IO uint32_t SR; /**< Status Register, offset: 0xC */ + __IO uint32_t CPSR; /**< Clock Prescale Register, offset: 0x10 */ + __IO uint32_t IMSC; /**< Interrupt Mask Set or Clear Register, offset: 0x14 */ + __IO uint32_t RIS; /**< Raw Interrupt Status Register, offset: 0x18 */ + __IO uint32_t MIS; /**< Masked Interrupt Status Register, offset: 0x1C */ + __IO uint32_t ICR; /**< Interrupt Clear Register, offset: 0x20 */ + __IO uint32_t DMACR; /**< DMA Control Register, offset: 0x24 */ +} SPI_TypeDef; + +/** @name CR0 - SPI_CR0 register */ +/** @{ */ +#define SPI_CR0_DSS_Pos (0) +#define SPI_CR0_DSS_Msk (0xFUL << SPI_CR0_DSS_Pos) + +#define SPI_CR0_FRF_Pos (4) +#define SPI_CR0_FRF_Msk (0x3UL << SPI_CR0_FRF_Pos) + +#define SPI_CR0_SPO_Pos (6) +#define SPI_CR0_SPO_Msk (0x1UL << SPI_CR0_SPO_Pos) + +#define SPI_CR0_SPH_Pos (7) +#define SPI_CR0_SPH_Msk (0x1UL << SPI_CR0_SPH_Pos) + +#define SPI_CR0_SCR_Pos (8) +#define SPI_CR0_SCR_Msk (0xFFUL << SPI_CR0_SCR_Pos) +/** @} */ + +/** @name CR1 - SPI_CR1 register */ +/** @{ */ +#define SPI_CR1_LBM_Pos (0) +#define SPI_CR1_LBM_Msk (0x1UL << SPI_CR1_LBM_Pos) + +#define SPI_CR1_SSE_Pos (1) +#define SPI_CR1_SSE_Msk (0x1UL << SPI_CR1_SSE_Pos) + +#define SPI_CR1_MS_Pos (2) +#define SPI_CR1_MS_Msk (0x1UL << SPI_CR1_MS_Pos) + +#define SPI_CR1_SOD_Pos (3) +#define SPI_CR1_SOD_Msk (0x1UL << SPI_CR1_SOD_Pos) +/** @} */ + +/** @name DR - SPI_DR register */ +/** @{ */ +#define SPI_DR_DATA_Pos (0) +#define SPI_DR_DATA_Msk (0xFFFFUL << SPI_DR_DATA_Pos) +/** @} */ + +/** @name SR - SPI_SR register */ +/** @{ */ +#define SPI_SR_TFE_Pos (0) +#define SPI_SR_TFE_Msk (0x1UL << SPI_SR_TFE_Pos) + +#define SPI_SR_TNF_Pos (1) +#define SPI_SR_TNF_Msk (0x1UL << SPI_SR_TNF_Pos) + +#define SPI_SR_RNE_Pos (2) +#define SPI_SR_RNE_Msk (0x1UL << SPI_SR_RNE_Pos) + +#define SPI_SR_RFF_Pos (3) +#define SPI_SR_RFF_Msk (0x1UL << SPI_SR_RFF_Pos) + +#define SPI_SR_BSY_Pos (4) +#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) +/** @} */ + +/** @name CPSR - SPI_CPSR register */ +/** @{ */ +#define SPI_CPSR_CPSDVSR_Pos (0) +#define SPI_CPSR_CPSDVSR_Msk (0xFFUL << SPI_CPSR_CPSDVSR_Pos) +/** @} */ + +/** @name IMSC - SPI_IMSC register */ +/** @{ */ +#define SPI_IMSC_RORIM_Pos (0) +#define SPI_IMSC_RORIM_Msk (0x1UL << SPI_IMSC_RORIM_Pos) + +#define SPI_IMSC_RTIM_Pos (1) +#define SPI_IMSC_RTIM_Msk (0x1UL << SPI_IMSC_RTIM_Pos) + +#define SPI_IMSC_RXIM_Pos (2) +#define SPI_IMSC_RXIM_Msk (0x1UL << SPI_IMSC_RXIM_Pos) + +#define SPI_IMSC_TXIM_Pos (3) +#define SPI_IMSC_TXIM_Msk (0x1UL << SPI_IMSC_TXIM_Pos) +/** @} */ + +/** @name RIS - SPI_RIS register */ +/** @{ */ +#define SPI_RIS_RORRIS_Pos (0) +#define SPI_RIS_RORRIS_Msk (0x1UL << SPI_RIS_RORRIS_Pos) + +#define SPI_RIS_RTRIS_Pos (1) +#define SPI_RIS_RTRIS_Msk (0x1UL << SPI_RIS_RTRIS_Pos) + +#define SPI_RIS_RXRIS_Pos (2) +#define SPI_RIS_RXRIS_Msk (0x1UL << SPI_RIS_RXRIS_Pos) + +#define SPI_RIS_TXRIS_Pos (3) +#define SPI_RIS_TXRIS_Msk (0x1UL << SPI_RIS_TXRIS_Pos) +/** @} */ + +/** @name MIS - SPI_MIS register */ +/** @{ */ +#define SPI_MIS_RORMIS_Pos (0) +#define SPI_MIS_RORMIS_Msk (0x1UL << SPI_MIS_RORMIS_Pos) + +#define SPI_MIS_RTMIS_Pos (1) +#define SPI_MIS_RTMIS_Msk (0x1UL << SPI_MIS_RTMIS_Pos) + +#define SPI_MIS_RXMIS_Pos (2) +#define SPI_MIS_RXMIS_Msk (0x1UL << SPI_MIS_RXMIS_Pos) + +#define SPI_MIS_TXMIS_Pos (3) +#define SPI_MIS_TXMIS_Msk (0x1UL << SPI_MIS_TXMIS_Pos) +/** @} */ + +/** @name ICR - SPI_ICR register */ +/** @{ */ +#define SPI_ICR_RORIC_Pos (0) +#define SPI_ICR_RORIC_Msk (0x1UL << SPI_ICR_RORIC_Pos) + +#define SPI_ICR_RTIC_Pos (1) +#define SPI_ICR_RTIC_Msk (0x1UL << SPI_ICR_RTIC_Pos) +/** @} */ + +/** @name DMACR - SPI_DMACR register */ +/** @{ */ +#define SPI_DMACR_RXDMAE_Pos (0) +#define SPI_DMACR_RXDMAE_Msk (0x1UL << SPI_DMACR_RXDMAE_Pos) + +#define SPI_DMACR_TXDMAE_Pos (1) +#define SPI_DMACR_TXDMAE_Msk (0x1UL << SPI_DMACR_TXDMAE_Pos) +/** @} */ + +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_TypeDef *)MP_SSP0_BASE_ADDR) + +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_TypeDef *)MP_SSP1_BASE_ADDR) + +/** @brief SPI peripheral instance number */ +#define SPI_INSTANCE_NUM (2) + +/** + * @} + */ /* end of group SPI */ + +/** @addtogroup TIMER Timer + * @{ + */ + +/** + * @brief TIMER register layout typedef + * + */ +typedef struct { + __IO uint32_t TCCR; /**< Timer Clock Control Register, offset: 0x0 */ + __IO uint32_t TCTLR; /**< Timer Control Register, offset: 0x4 */ + __IO uint32_t TSR; /**< Timer Status Register, offset: 0x8 */ + __IO uint32_t TIVR; /**< Timer Init Value Register, offset: 0xC */ + __IO uint32_t TMR[3]; /**< Timer Match N Register, array offset: 0x10, array step: 0x4 */ + __I uint32_t TCR; /**< Timer Counter Register, offset: 0x1C */ + __IO uint32_t TCLR; /**< Timer Counter Latch Register, offset: 0x20 */ + __I uint32_t TCAR; /**< Timer Counter Actual Register, offset: 0x24 */ +} TIMER_TypeDef; + +/** @name TCCR - TIMER_TCCR register */ +/** @{ */ +#define TIMER_TCCR_ENABLE_Pos (0) +#define TIMER_TCCR_ENABLE_Msk (0x1UL << TIMER_TCCR_ENABLE_Pos) +/** @} */ + +/** @name TCTLR - TIMER_TCTLR register */ +/** @{ */ +#define TIMER_TCTLR_MODE_Pos (0) +#define TIMER_TCTLR_MODE_Msk (0x1UL << TIMER_TCTLR_MODE_Pos) + +#define TIMER_TCTLR_MCS_Pos (1) +#define TIMER_TCTLR_MCS_Msk (0x3UL << TIMER_TCTLR_MCS_Pos) + +#define TIMER_TCTLR_IE_0_Pos (3) +#define TIMER_TCTLR_IE_0_Msk (0x1UL << TIMER_TCTLR_IE_0_Pos) + +#define TIMER_TCTLR_IE_1_Pos (4) +#define TIMER_TCTLR_IE_1_Msk (0x1UL << TIMER_TCTLR_IE_1_Pos) + +#define TIMER_TCTLR_IE_2_Pos (5) +#define TIMER_TCTLR_IE_2_Msk (0x1UL << TIMER_TCTLR_IE_1_Pos) + +#define TIMER_TCTLR_IT_0_Pos (6) +#define TIMER_TCTLR_IT_0_Msk (0x1UL << TIMER_TCTLR_IT_0_Pos) + +#define TIMER_TCTLR_IT_1_Pos (7) +#define TIMER_TCTLR_IT_1_Msk (0x1UL << TIMER_TCTLR_IT_1_Pos) + +#define TIMER_TCTLR_IT_2_Pos (8) +#define TIMER_TCTLR_IT_2_Msk (0x1UL << TIMER_TCTLR_IT_2_Pos) + +#define TIMER_TCTLR_PWMOUT_Pos (9) +#define TIMER_TCTLR_PWMOUT_Msk (0x1UL << TIMER_TCTLR_PWMOUT_Pos) +/** @} */ + +/** @name TSR - TIMER_TSR register */ +/** @{ */ +#define TIMER_TSR_ICLR_0_Pos (0) +#define TIMER_TSR_ICLR_0_Msk (0x1UL << TIMER_TSR_ICLR_0_Pos) + +#define TIMER_TSR_ICLR_1_Pos (1) +#define TIMER_TSR_ICLR_1_Msk (0x1UL << TIMER_TSR_ICLR_1_Pos) + +#define TIMER_TSR_ICLR_2_Pos (2) +#define TIMER_TSR_ICLR_2_Msk (0x1UL << TIMER_TSR_ICLR_2_Pos) +/** @} */ + +/** @name TIVR - TIMER_TIVR register */ +/** @{ */ +#define TIMER_TIVR_VALUE_Pos (0) +#define TIMER_TIVR_VALUE_Msk (0xFFFFFFFFUL << TIMER_TIVR_VALUE_Pos) +/** @} */ + +/** @name TMR - TIMER_TMR N register */ +/** @{ */ +#define TIMER_TMR_MATCH_Pos (0) +#define TIMER_TMR_MATCH_Msk (0xFFFFFFFFUL << TIMER_TMR_MATCH_Pos) +/** @} */ + +/** @name TCR - TIMER_TCR register */ +/** @{ */ +#define TIMER_TCR_VALUE_Pos (0) +#define TIMER_TCR_VALUE_Msk (0xFFFFFFFFUL << TIMER_TCR_VALUE_Pos) +/** @} */ + +/** @name TCLR - TIMER_TCLR register */ +/** @{ */ +#define TIMER_TCLR_LATCH_Pos (0) +#define TIMER_TCLR_LATCH_Msk (0x1UL << TIMER_TCLR_LATCH_Pos) +/** @} */ + + +/** @brief TIMER peripheral instance number */ +#define TIMER_INSTANCE_NUM (6) + +/** + * @} + */ /* end of group TIMER */ + + +/** @addtogroup USART USART + * @{ + */ + +/** + * @brief USART register layout typedef + * + */ +typedef struct { + union{ + __IO uint32_t RBR; /**< Receive Buffer Register, offset: 0x0 */ + __IO uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */ + __IO uint32_t DLL; /**< Divisor Latch Low, offset: 0x0 */ + }; + union{ + __IO uint32_t DLH; /**< Divisor Latch High, offset: 0x4 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */ + }; + union{ + __IO uint32_t IIR; /**< Interrupt Identification Register, offset: 0x8 */ + __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ + }; + __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */ + __IO uint32_t MCR; /**< Modem Control Register, offset: 0x10 */ + __IO uint32_t LSR; /**< Line Status Register, offset: 0x14 */ + __IO uint32_t MSR; /**< Modem Status Register, offset: 0x18 */ + __IO uint32_t SCR; /**< Scratchpad Register, offset: 0x1C */ + __IO uint32_t MFCR; /**< Main Function Control Register, offset: 0x20 */ + __IO uint32_t EFCR; /**< Extended Function Control Register, offset: 0x24 */ + __IO uint32_t LPDR; /**< SIR Divisor Register, offset: 0x28 */ + __IO uint32_t FCNR; /**< Tx and Rx FIFO Character Number Register, offset: 0x2C */ + __IO uint32_t ADCR; /**< Auto-baud Detect Control Register, offset: 0x30 */ + __IO uint32_t ADRR; /**< Auto-baud Detect Result Register, offset: 0x34 */ + __IO uint32_t ISR; /**< Interrupt Status Register, offset: 0x38 */ + __IO uint32_t ICR; /**< Interrupt Clear Register, offset: 0x3C */ +} USART_TypeDef; + +/** @name RBR - USART_RBR register */ +/** @{ */ +#define USART_RBR_RX_BUF_Pos (0) +#define USART_RBR_RX_BUF_Msk (0xFFUL << USART_RBR_RX_BUF_Pos) +/** @} */ + +/** @name THR - USART_THR register */ +/** @{ */ +#define USART_THR_TX_HOLDING_Pos (0) +#define USART_THR_TX_HOLDING_Msk (0xFFUL << USART_THR_TX_HOLDING_Pos) +/** @} */ + +/** @name DLL - USART_DLL register */ +/** @{ */ +#define USART_DLL_DLL_Pos (0) +#define USART_DLL_DLL_Msk (0xFFUL << USART_DLL_DLL_Pos) +/** @} */ + +/** @name DLH - USART_DLH register */ +/** @{ */ +#define USART_DLH_DLH_Pos (0) +#define USART_DLH_DLH_Msk (0xFFUL << USART_DLH_DLH_Pos) +/** @} */ + +/** @name IER - USART_IER register */ +/** @{ */ +#define USART_IER_RX_DATA_REQ_Pos (0) +#define USART_IER_RX_DATA_REQ_Msk (0x1UL << USART_IER_RX_DATA_REQ_Pos) + +#define USART_IER_TX_DATA_REQ_Pos (1) +#define USART_IER_TX_DATA_REQ_Msk (0x1UL << USART_IER_TX_DATA_REQ_Pos) + +#define USART_IER_RX_LINE_STATUS_Pos (2) +#define USART_IER_RX_LINE_STATUS_Msk (0x1UL << USART_IER_RX_LINE_STATUS_Pos) + +#define USART_IER_MODEM_STATUS_Pos (3) +#define USART_IER_MODEM_STATUS_Msk (0x1UL << USART_IER_MODEM_STATUS_Pos) + +#define USART_IER_RX_TIMEOUT_Pos (4) +#define USART_IER_RX_TIMEOUT_Msk (0x1UL << USART_IER_RX_TIMEOUT_Pos) +/** @} */ + +/** @name IIR - USART_IIR register */ +/** @{ */ +#define USART_IIR_INT_PENDING_Pos (0) +#define USART_IIR_INT_PENDING_Msk (0x1UL << USART_IIR_INT_PENDING_Pos) + +#define USART_IIR_INT_ID_Pos (1) +#define USART_IIR_INT_ID_Msk (0xFUL << USART_IIR_INT_ID_Pos) +/** @} */ + +/** @name FCR - USART_FCR register */ +/** @{ */ +#define USART_FCR_FIFO_EN_Pos (0) +#define USART_FCR_FIFO_EN_Msk (0x1UL << USART_FCR_FIFO_EN_Pos) + +#define USART_FCR_RESET_RX_FIFO_Pos (1) +#define USART_FCR_RESET_RX_FIFO_Msk (0x1UL << USART_FCR_RESET_RX_FIFO_Pos) + +#define USART_FCR_RESET_TX_FIFO_Pos (2) +#define USART_FCR_RESET_TX_FIFO_Msk (0x1UL << USART_FCR_RESET_TX_FIFO_Pos) + +#define USART_FCR_DMA_MODE_Pos (3) +#define USART_FCR_DMA_MODE_Msk (0x1UL << USART_FCR_DMA_MODE_Pos) + +#define USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos (4) +#define USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Msk (0x3UL << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos) + +#define USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos (6) +#define USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Msk (0x3UL << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos) +/** @} */ + +/** @name LCR - USART_LCR register */ +/** @{ */ +#define USART_LCR_CHAR_LEN_Pos (0) +#define USART_LCR_CHAR_LEN_Msk (0x3UL << USART_LCR_CHAR_LEN_Pos) + +#define USART_LCR_STOP_BIT_NUM_Pos (2) +#define USART_LCR_STOP_BIT_NUM_Msk (0x1UL << USART_LCR_STOP_BIT_NUM_Pos) + +#define USART_LCR_PARITY_EN_Pos (3) +#define USART_LCR_PARITY_EN_Msk (0x1UL << USART_LCR_PARITY_EN_Pos) + +#define USART_LCR_EVEN_PARITY_Pos (4) +#define USART_LCR_EVEN_PARITY_Msk (0x1UL << USART_LCR_EVEN_PARITY_Pos) + +#define USART_LCR_STICKY_PARITY_Pos (5) +#define USART_LCR_STICKY_PARITY_Msk (0x1UL << USART_LCR_STICKY_PARITY_Pos) + +#define USART_LCR_SET_BREAK_Pos (6) +#define USART_LCR_SET_BREAK_Msk (0x1UL << USART_LCR_SET_BREAK_Pos) + +#define USART_LCR_ACCESS_DIVISOR_LATCH_Pos (7) +#define USART_LCR_ACCESS_DIVISOR_LATCH_Msk (0x1UL << USART_LCR_ACCESS_DIVISOR_LATCH_Pos) +/** @} */ + +/** @name MCR - USART_MCR register */ +/** @{ */ +#define USART_MCR_DTR_Pos (0) +#define USART_MCR_DTR_Msk (0x1UL << USART_MCR_DTR_Pos) + +#define USART_MCR_RTS_Pos (1) +#define USART_MCR_RTS_Msk (0x1UL << USART_MCR_RTS_Pos) + +#define USART_MCR_OUT1_Pos (2) +#define USART_MCR_OUT1_Msk (0x1UL << USART_MCR_OUT1_Pos) + +#define USART_MCR_OUT2_Pos (3) +#define USART_MCR_OUT2_Msk (0x1UL << USART_MCR_OUT2_Pos) + +#define USART_MCR_LOOPBACK_MODE_Pos (4) +#define USART_MCR_LOOPBACK_MODE_Msk (0x1UL << USART_MCR_LOOPBACK_MODE_Pos) +/** @} */ + +/** @name LSR - USART_LSR register */ +/** @{ */ +#define USART_LSR_RX_DATA_READY_Pos (0) +#define USART_LSR_RX_DATA_READY_Msk (0x1UL << USART_LSR_RX_DATA_READY_Pos) + +#define USART_LSR_RX_OVERRUN_ERROR_Pos (1) +#define USART_LSR_RX_OVERRUN_ERROR_Msk (0x1UL << USART_LSR_RX_OVERRUN_ERROR_Pos) + +#define USART_LSR_RX_PARITY_ERROR_Pos (2) +#define USART_LSR_RX_PARITY_ERROR_Msk (0x1UL << USART_LSR_RX_PARITY_ERROR_Pos) + +#define USART_LSR_RX_FRAME_ERROR_Pos (3) +#define USART_LSR_RX_FRAME_ERROR_Msk (0x1UL << USART_LSR_RX_FRAME_ERROR_Pos) + +#define USART_LSR_RX_BREAK_Pos (4) +#define USART_LSR_RX_BREAK_Msk (0x1UL << USART_LSR_RX_BREAK_Pos) + +#define USART_LSR_TX_DATA_REQ_Pos (5) +#define USART_LSR_TX_DATA_REQ_Msk (0x1UL << USART_LSR_TX_DATA_REQ_Pos) + +#define USART_LSR_TX_EMPTY_Pos (6) +#define USART_LSR_TX_EMPTY_Msk (0x1UL << USART_LSR_TX_EMPTY_Pos) + +#define USART_LSR_RX_FIFO_ERROR_Pos (7) +#define USART_LSR_RX_FIFO_ERROR_Msk (0x1UL << USART_LSR_RX_FIFO_ERROR_Pos) + +#define USART_LSR_RX_BUSY_Pos (10) +#define USART_LSR_RX_BUSY_Msk (0x1UL << USART_LSR_RX_FIFO_ERROR_Pos) + +/** @} */ + +/** @name MSR - USART_MSR register */ +/** @{ */ +#define USART_MSR_CTS_CHANGED_Pos (0) +#define USART_MSR_CTS_CHANGED_Msk (0x1UL << USART_MSR_CTS_CHANGED_Pos) + +#define USART_MSR_DSR_CHANGED_Pos (1) +#define USART_MSR_DSR_CHANGED_Msk (0x1UL << USART_MSR_DSR_CHANGED_Pos) + +#define USART_MSR_RI_CHANGED_Pos (2) +#define USART_MSR_RI_CHANGED_Msk (0x1UL << USART_MSR_RI_CHANGED_Pos) + +#define USART_MSR_DCD_CHANGED_Pos (3) +#define USART_MSR_DCD_CHANGED_Msk (0x1UL << USART_MSR_DCD_CHANGED_Pos) + +#define USART_MSR_CTS_Pos (4) +#define USART_MSR_CTS_Msk (0x1UL << USART_MSR_CTS_Pos) + +#define USART_MSR_DSR_Pos (5) +#define USART_MSR_DSR_Msk (0x1UL << USART_MSR_DSR_Pos) + +#define USART_MSR_RI_Pos (6) +#define USART_MSR_RI_Msk (0x1UL << USART_MSR_RI_Pos) + +#define USART_MSR_DCD_Pos (7) +#define USART_MSR_DCD_Msk (0x1UL << USART_MSR_DCD_Pos) +/** @} */ + +/** @name SCR - USART_SCR register */ +/** @{ */ +#define USART_SCR_SCRATCH_Pos (0) +#define USART_SCR_SCRATCH_Msk (0xFFUL << USART_SCR_SCRATCH_Pos) +/** @} */ + +/** @name MFCR - USART_MFCR register */ +/** @{ */ +#define USART_MFCR_UART_EN_Pos (0) +#define USART_MFCR_UART_EN_Msk (0x1UL << USART_MFCR_UART_EN_Pos) + +#define USART_MFCR_NRZ_CODING_Pos (1) +#define USART_MFCR_NRZ_CODING_Msk (0x1UL << USART_MFCR_NRZ_CODING_Pos) + +#define USART_MFCR_DMA_EN_Pos (2) +#define USART_MFCR_DMA_EN_Msk (0x1UL << USART_MFCR_DMA_EN_Pos) + +#define USART_MFCR_AUTO_FLOW_RTS_EN_Pos (4) +#define USART_MFCR_AUTO_FLOW_RTS_EN_Msk (0x1UL << USART_MFCR_AUTO_FLOW_RTS_EN_Pos) + +#define USART_MFCR_AUTO_FLOW_CTS_EN_Pos (5) +#define USART_MFCR_AUTO_FLOW_CTS_EN_Msk (0x1UL << USART_MFCR_AUTO_FLOW_CTS_EN_Pos) + +#define USART_MFCR_PRESCALE_FACTOR_Pos (8) +#define USART_MFCR_PRESCALE_FACTOR_Msk (0x3UL << USART_MFCR_PRESCALE_FACTOR_Pos) + +/** @} */ + +/** @name EFCR - USART_EFCR register */ +/** @{ */ +#define USART_EFCR_TX_MODE_Pos (0) +#define USART_EFCR_TX_MODE_Msk (0x1UL << USART_EFCR_TX_MODE_Pos) + +#define USART_EFCR_RX_MODE_Pos (1) +#define USART_EFCR_RX_MODE_Msk (0x1UL << USART_EFCR_RX_MODE_Pos) + +#define USART_EFCR_SIR_LOW_POWER_Pos (2) +#define USART_EFCR_SIR_LOW_POWER_Msk (0x1UL << USART_EFCR_SIR_LOW_POWER_Pos) + +#define USART_EFCR_TX_POLARITY_Pos (3) +#define USART_EFCR_TX_POLARITY_Msk (0x1UL << USART_EFCR_TX_POLARITY_Pos) + +#define USART_EFCR_RX_POLARITY_Pos (4) +#define USART_EFCR_RX_POLARITY_Msk (0x1UL << USART_EFCR_RX_POLARITY_Pos) + +#define USART_EFCR_FRAC_DIVISOR_Pos (8) +#define USART_EFCR_FRAC_DIVISOR_Msk (0xFUL << USART_EFCR_FRAC_DIVISOR_Pos) +/** @} */ + +/** @name LPDR - USART_LPDR register */ +/** @{ */ +#define USART_LPDR_SIR_DIVISOR_Pos (0) +#define USART_LPDR_SIR_DIVISOR_Msk (0xFFFFUL << USART_LPDR_SIR_DIVISOR_Pos) +/** @} */ + +/** @name FCNR - USART_FCNR register */ +/** @{ */ +#define USART_FCNR_TX_FIFO_NUM_Pos (0) +#define USART_FCNR_TX_FIFO_NUM_Msk (0xFFUL << USART_FCNR_TX_FIFO_NUM_Pos) + +#define USART_FCNR_RX_FIFO_NUM_Pos (16) +#define USART_FCNR_RX_FIFO_NUM_Msk (0xFFUL << USART_FCNR_RX_FIFO_NUM_Pos) +/** @} */ + +/** @name ADCR - USART_ADCR register */ +/** @{ */ +#define USART_ADCR_AUTO_BAUD_EN_Pos (0) +#define USART_ADCR_AUTO_BAUD_EN_Msk (0x1UL << USART_ADCR_AUTO_BAUD_EN_Pos) + +#define USART_ADCR_AUTO_BAUD_INT_EN_Pos (1) +#define USART_ADCR_AUTO_BAUD_INT_EN_Msk (0x1UL << USART_ADCR_AUTO_BAUD_INT_EN_Pos) + +#define USART_ADCR_AUTO_BAUD_PROG_SEL_Pos (2) +#define USART_ADCR_AUTO_BAUD_PROG_SEL_Msk (0x1UL << USART_ADCR_AUTO_BAUD_PROG_SEL_Pos) +/** @} */ + +/** @name ADRR - USART_ADRR register */ +/** @{ */ +#define USART_ADRR_AUTO_BAUD_INTE_Pos (0) +#define USART_ADRR_AUTO_BAUD_INTE_Msk (0xFFFFUL << USART_ADRR_AUTO_BAUD_INTE_Pos) + +#define USART_ADRR_AUTO_BAUD_FRAC_Pos (16) +#define USART_ADRR_AUTO_BAUD_FRAC_Msk (0xFUL << USART_ADRR_AUTO_BAUD_FRAC_Pos) +/** @} */ + +/** @name ISR - USART_ISR register */ +/** @{ */ +#define USART_ISR_RX_DATA_REQ_Pos (0) +#define USART_ISR_RX_DATA_REQ_Msk (0x1UL << USART_ISR_RX_DATA_REQ_Pos) + +#define USART_ISR_RX_TIMEOUT_Pos (1) +#define USART_ISR_RX_TIMEOUT_Msk (0x1UL << USART_ISR_RX_TIMEOUT_Pos) + +#define USART_ISR_TX_DATA_REQ_Pos (2) +#define USART_ISR_TX_DATA_REQ_Msk (0x1UL << USART_ISR_TX_DATA_REQ_Pos) + +#define USART_ISR_MODEM_STATUS_Pos (3) +#define USART_ISR_MODEM_STATUS_Msk (0x1UL << USART_ISR_MODEM_STATUS_Pos) + +#define USART_ISR_RX_LINE_STATUS_Pos (4) +#define USART_ISR_RX_LINE_STATUS_Msk (0x1UL << USART_ISR_RX_LINE_STATUS_Pos) + +#define USART_ISR_LCR_BUSY_Pos (5) +#define USART_ISR_LCR_BUSY_Msk (0x1UL << USART_ISR_LCR_BUSY_Pos) + +#define USART_ISR_AUTO_BAUD_Pos (6) +#define USART_ISR_AUTO_BAUD_Msk (0x1UL << USART_ISR_AUTO_BAUD_Pos) +/** @} */ + +/** @name ICR - USART_ICR register */ +/** @{ */ +#define USART_ICR_RX_DATA_REQ_Pos (0) +#define USART_ICR_RX_DATA_REQ_Msk (0x1UL << USART_ICR_RX_DATA_REQ_Pos) + +#define USART_ICR_RX_TIMEOUT_Pos (1) +#define USART_ICR_RX_TIMEOUT_Msk (0x1UL << USART_ICR_RX_TIMEOUT_Pos) + +#define USART_ICR_TX_DATA_REQ_Pos (2) +#define USART_ICR_TX_DATA_REQ_Msk (0x1UL << USART_ICR_TX_DATA_REQ_Pos) + +#define USART_ICR_MODEM_STATUS_Pos (3) +#define USART_ICR_MODEM_STATUS_Msk (0x1UL << USART_ICR_MODEM_STATUS_Pos) + +#define USART_ICR_RX_LINE_STATUS_Pos (4) +#define USART_ICR_RX_LINE_STATUS_Msk (0x1UL << USART_ICR_RX_LINE_STATUS_Pos) + +#define USART_ICR_LCR_BUSY_Pos (5) +#define USART_ICR_LCR_BUSY_Msk (0x1UL << USART_ICR_LCR_BUSY_Pos) + +#define USART_ICR_AUTO_BAUD_Pos (6) +#define USART_ICR_AUTO_BAUD_Msk (0x1UL << USART_ICR_AUTO_BAUD_Pos) +/** @} */ + + +/** Peripheral USART_0 base pointer */ +#define USART_0 ((USART_TypeDef *)MP_UART0_BASE_ADDR) + +/** Peripheral USART_1 base pointer */ +#define USART_1 ((USART_TypeDef *)MP_UART1_BASE_ADDR) + +/** Peripheral USART_2 base pointer */ +#define USART_2 ((USART_TypeDef *)MP_UART2_BASE_ADDR) + + +/** @brief USART peripheral instance number */ +#define USART_INSTANCE_NUM (3) + +/** + * @} + */ /* end of group USART */ + +/** @addtogroup WDT Watchdog + * @{ + */ + +/** + * @brief WDT register layout typedef + * + */ +typedef struct { + __IO uint32_t CTRL; /**< WDT Control Register, offset: 0x0 */ + __IO uint32_t TOVR; /**< WDT Timerout Value Register, offset: 0x4 */ + __O uint32_t CCR; /**< WDT Counter Clear Register, offset: 0x8 */ + __O uint32_t ICR; /**< WDT Interrupt Clear Register, offset: 0xC */ + __O uint32_t LOCK; /**< WDT Lock Register, offset: 0x10 */ + __I uint32_t STAT; /**< WDT Status Register, offset: 0x14 */ +} WDT_TypeDef; + +/** @name CTRL - WDT_CTRL register */ +/** @{ */ +#define WDT_CTRL_ENABLE_Pos (0) +#define WDT_CTRL_ENABLE_Msk (0x1UL << WDT_CTRL_ENABLE_Pos) + +#define WDT_CTRL_MODE_Pos (1) +#define WDT_CTRL_MODE_Msk (0x1UL << WDT_CTRL_MODE_Pos) +/** @} */ + +/** @name TOVR - WDT_TOVR register */ +/** @{ */ +#define WDT_TOVR_VAL_Pos (0) +#define WDT_TOVR_VAL_Msk (0xFFFFUL << WDT_TOVR_VAL_Pos) +/** @} */ + +/** @name CCR - WDT_CCR register */ +/** @{ */ +#define WDT_CCR_CNT_CLR_Pos (0) +#define WDT_CCR_CNT_CLR_Msk (0x1UL << WDT_CCR_CNT_CLR_Pos) +/** @} */ + +/** @name ICR - WDT_ICR register */ +/** @{ */ +#define WDT_ICR_ICLR_Pos (0) +#define WDT_ICR_ICLR_Msk (0x1UL << WDT_ICR_ICLR_Pos) +/** @} */ + +/** @name LOCK - WDT_LOCK register */ +/** @{ */ +#define WDT_LOCK_LOCK_VAL_Pos (0) +#define WDT_LOCK_LOCK_VAL_Msk (0xFFFFUL << WDT_LOCK_LOCK_VAL_Pos) +/** @} */ + +/** @name STAT - WDT_STAT register */ +/** @{ */ +#define WDT_STAT_CV_Pos (0) +#define WDT_STAT_CV_Msk (0xFFFFUL << WDT_STAT_CV_Pos) + +#define WDT_STAT_ISTAT_Pos (16) +#define WDT_STAT_ISTAT_Msk (0x1UL << WDT_STAT_ISTAT_Pos) +/** @} */ + +/** Peripheral WDT base pointer */ +#define WDT ((WDT_TypeDef *)AP_WDG_BASE_ADDR) + +/** + * @} + */ /* end of group WDT */ + + +/** @addtogroup oneWire + * @{ + */ + +/** + * @brief oneWire register layout typedef + * + */ +typedef struct { + __IO uint32_t ECR; /**< OW Enable Control Register, offset: 0x0 */ + __IO uint32_t CDR; /**< OW Clock Divider Register, offset: 0x4 */ + __IO uint32_t IOR; /**< OW IO Control/Status Register, offset: 0x8 */ + __IO uint32_t DFR; /**< OW Data Format Register, offset: 0xC */ + __IO uint32_t OCR; /**< OW Operation Cmd Register, offset: 0x10 */ + __IO uint32_t TBR; /**< OW Transmit Buffer Register, offset: 0x14 */ + __IO uint32_t RBR; /**< OW Receive Buffer Register, offset: 0x18 */ + __IO uint32_t IER; /**< OW Interrupt Enable Register, offset: 0x1C */ + __IO uint32_t IIR; /**< OW Interrupt Identification Register, offset: 0x20 */ + __IO uint32_t CSR; /**< OW Control Status Register, offset: 0x24 */ + __IO uint32_t RTCR; /**< OW Reset Timing Control Register, offset: 0x28 */ + __IO uint32_t ATCR; /**< OW Access(write/read) Timing Control Register, offset: 0x2C */ +} OW_TypeDef; + +/** @name ECR - OW_ECR register */ +/** @{ */ +#define OW_ECR_ENABLE_Pos (0) +#define OW_ECR_ENABLE_Msk (0x1UL << OW_ECR_ENABLE_Pos) + +#define OW_ECR_CLK_EN_Pos (1) +#define OW_ECR_CLK_EN_Msk (0x1UL << OW_ECR_CLK_EN_Pos) + +#define OW_ECR_AUTO_CGEN_Pos (2) +#define OW_ECR_AUTO_CGEN_Msk (0x1UL << OW_ECR_AUTO_CGEN_Pos) + +#define OW_ECR_RXD_MJR_Pos (3) +#define OW_ECR_RXD_MJR_Msk (0x1UL << OW_ECR_RXD_MJR_Pos) +/** @} */ + +/** @name CDR - OW_CDR register */ +/** @{ */ +#define OW_CDR_CLKUS_DIV_SUB1_Pos (0) +#define OW_CDR_CLKUS_DIV_SUB1_Msk (0xFFUL << OW_CDR_CLKUS_DIV_SUB1_Pos) +/** @} */ + +/** @name IOR - OW_IOR register */ +/** @{ */ +#define OW_IOR_IO_SWMODE_Pos (0) +#define OW_IOR_IO_SWMODE_Msk (0x1UL << OW_IOR_IO_SWMODE_Pos) + +#define OW_IOR_IO_SWOEN_Pos (1) +#define OW_IOR_IO_SWOEN_Msk (0x1UL << OW_IOR_IO_SWOEN_Pos) + +#define OW_IOR_IO_SWOUT_Pos (2) +#define OW_IOR_IO_SWOUT_Msk (0x1UL << OW_IOR_IO_SWOUT_Pos) + +#define OW_IOR_IO_SWIN_Pos (3) +#define OW_IOR_IO_SWIN_Msk (0x1UL << OW_IOR_IO_SWIN_Pos) + +#define OW_IOR_IO_SWIN_SYNC_Pos (4) +#define OW_IOR_IO_SWIN_SYNC_Msk (0x1UL << OW_IOR_IO_SWIN_SYNC_Pos) +/** @} */ + +/** @name DFR - OW_DFR register */ +/** @{ */ +#define OW_DFR_MODE_BYTE_Pos (0) +#define OW_DFR_MODE_BYTE_Msk (0x1UL << OW_DFR_MODE_BYTE_Pos) + +#define OW_DFR_MODE_ENDIAN_Pos (1) +#define OW_DFR_MODE_ENDIAN_Msk (0x1UL << OW_DFR_MODE_ENDIAN_Pos) + +#define OW_DFR_MODE_POLARITY_Pos (2) +#define OW_DFR_MODE_POLARITY_Msk (0x1UL << OW_DFR_MODE_POLARITY_Pos) +/** @} */ + +/** @name OCR - OW_OCR register */ +/** @{ */ +#define OW_OCR_CMD_FLUSH_Pos (0) +#define OW_OCR_CMD_FLUSH_Msk (0x1UL << OW_OCR_CMD_FLUSH_Pos) + +#define OW_OCR_CMD_RESET_Pos (1) +#define OW_OCR_CMD_RESET_Msk (0x1UL << OW_OCR_CMD_RESET_Pos) + +#define OW_OCR_CMD_WRITE_Pos (2) +#define OW_OCR_CMD_WRITE_Msk (0x1UL << OW_OCR_CMD_WRITE_Pos) + +#define OW_OCR_CMD_READ_Pos (3) +#define OW_OCR_CMD_READ_Msk (0x1UL << OW_OCR_CMD_READ_Pos) +/** @} */ + +/** @name TBR - OW_TBR register */ +/** @{ */ +#define OW_TBR_TX_BUF_Pos (0) +#define OW_TBR_TX_BUF_Msk (0xFFUL << OW_TBR_TX_BUF_Pos) +/** @} */ + +/** @name RBR - OW_RBR register */ +/** @{ */ +#define OW_RBR_RX_BUF_Pos (0) +#define OW_RBR_RX_BUF_Msk (0xFFUL << OW_RBR_RX_BUF_Pos) +/** @} */ + +/** @name IER - OW_IER register */ +/** @{ */ +#define OW_IER_INTEN_RESET_Pos (1) +#define OW_IER_INTEN_RESET_Msk (0x1UL << OW_IER_INTEN_RESET_Pos) + +#define OW_IER_INTEN_RESET_PD_Pos (2) +#define OW_IER_INTEN_RESET_PD_Msk (0x1UL << OW_IER_INTEN_RESET_PD_Pos) + +#define OW_IER_INTEN_WRITE_Pos (3) +#define OW_IER_INTEN_WRITE_Msk (0x1UL << OW_IER_INTEN_WRITE_Pos) + +#define OW_IER_INTEN_READ_Pos (4) +#define OW_IER_INTEN_READ_Msk (0x1UL << OW_IER_INTEN_READ_Pos) +/** @} */ + +/** @name IIR - OW_IIR register */ +/** @{ */ +#define OW_IIR_INT_CLR_Pos (0) +#define OW_IIR_INT_CLR_Msk (0x1UL << OW_IIR_INT_CLR_Pos) + +#define OW_IIR_INT_RESET_Pos (1) +#define OW_IIR_INT_RESET_Msk (0x1UL << OW_IIR_INT_RESET_Pos) + +#define OW_IIR_INT_RESET_PD_Pos (2) +#define OW_IIR_INT_RESET_PD_Msk (0x1UL << OW_IIR_INT_RESET_PD_Pos) + +#define OW_IIR_INT_WRITE_Pos (3) +#define OW_IIR_INT_WRITE_Msk (0x1UL << OW_IIR_INT_WRITE_Pos) + +#define OW_IIR_INT_READ_Pos (4) +#define OW_IIR_INT_READ_Msk (0x1UL << OW_IIR_INT_READ_Pos) + +#define OW_IIR_RESET_PD_RES_Pos (7) +#define OW_IIR_RESET_PD_RES_Msk (0x1UL << OW_IIR_RESET_PD_RES_Pos) +/** @} */ + +/** @name CSR - OW_CSR register */ +/** @{ */ +#define OW_CSR_STATUS_SFTREG_Pos (0) +#define OW_CSR_STATUS_SFTREG_Msk (0xFFUL << OW_CSR_STATUS_SFTREG_Pos) + +#define OW_CSR_STATUS_SFTCNT_Pos (8) +#define OW_CSR_STATUS_SFTCNT_Msk (0x7UL << OW_CSR_STATUS_SFTCNT_Pos) + +#define OW_CSR_STATUS_FSM_Pos (12) +#define OW_CSR_STATUS_FSM_Msk (0x7UL << OW_CSR_STATUS_FSM_Pos) + +#define OW_CSR_STATUS_USCNT_Pos (16) +#define OW_CSR_STATUS_USCNT_Msk (0x3FFUL << OW_CSR_STATUS_USCNT_Pos) + +#define OW_CSR_STATUS_MODE_Pos (28) +#define OW_CSR_STATUS_MODE_Msk (0x3UL << OW_CSR_STATUS_MODE_Pos) + +#define OW_CSR_STATUS_USCLK_ENABLE_Pos (31) +#define OW_CSR_STATUS_USCLK_ENABLE_Msk (0x1UL << OW_CSR_STATUS_USCLK_ENABLE_Pos) +/** @} */ + +/** @name RTCR - OW_RTCR register */ +/** @{ */ +#define OW_RTCR_RESET_SEND_DIV10_Pos (0) +#define OW_RTCR_RESET_SEND_DIV10_Msk (0x7FUL << OW_RTCR_RESET_SEND_DIV10_Pos) + +#define OW_RTCR_RESET_WAIT_DIV10_Pos (8) +#define OW_RTCR_RESET_WAIT_DIV10_Msk (0x7FUL << OW_RTCR_RESET_WAIT_DIV10_Pos) + +#define OW_RTCR_RESET_RDDLY_MIN_Pos (16) +#define OW_RTCR_RESET_RDDLY_MIN_Msk (0x3FUL << OW_RTCR_RESET_RDDLY_MIN_Pos) + +#define OW_RTCR_RESET_RDDLY_MAX_DIV10_Pos (24) +#define OW_RTCR_RESET_RDDLY_MAX_DIV10_Msk (0x1FUL << OW_RTCR_RESET_RDDLY_MAX_DIV10_Pos) + +/** @} */ + +/** @name ATCR - OW_ATCR register */ +/** @{ */ +#define OW_ATCR_WRRD_RECO_Pos (0) +#define OW_ATCR_WRRD_RECO_Msk (0x7UL << OW_ATCR_WRRD_RECO_Pos) + +#define OW_ATCR_WRRD_SLOT_DIV10_Pos (8) +#define OW_ATCR_WRRD_SLOT_DIV10_Msk (0xFUL << OW_ATCR_WRRD_SLOT_DIV10_Pos) + +#define OW_ATCR_WRRD_START_Pos (12) +#define OW_ATCR_WRRD_START_Msk (0x7UL << OW_ATCR_WRRD_START_Pos) + +#define OW_ATCR_WRRD_WRDLY_Pos (16) +#define OW_ATCR_WRRD_WRDLY_Msk (0x1FUL << OW_ATCR_WRRD_WRDLY_Pos) + +#define OW_ATCR_WRRD_RDDLY_Pos (24) +#define OW_ATCR_WRRD_RDDLY_Msk (0x1FUL << OW_ATCR_WRRD_RDDLY_Pos) + +/** @} */ + + +/** Peripheral OW base pointer */ +#define OW ((OW_TypeDef *)AP_ONEWIRE_BASE_ADDR) + +/** + * @} + */ /* end of group OW */ + + +/** @addtogroup XIC XIC(external interrupt controller) + * @{ + */ + + + +/** + * @brief XIC register layout typedef + * + */ +typedef struct { + __IO uint32_t LATCHIRQ; /**< Latch IRQ Register, offset: 0x0 */ + __IO uint32_t IRQSTATUS; /**< IRQ Status Register, offset: 0x4 */ + __IO uint32_t MASK; /**< IRQ Mask Register, offset: 0x8 */ + __IO uint32_t PEND; /**< Pend Register, offset: 0xC */ + __IO uint32_t SWGENIRQ; /**< Software Generat IRQ Register, offset: 0x10 */ + __IO uint32_t CLRIRQ; /**< IRQ Clear Register, offset: 0x14 */ + __IO uint32_t CLROVF; /**< Clear IRQ Overflow Register, offset: 0x18 */ + __IO uint32_t OVFSTATUS; /**< IRQ Overflow Status Register, offset: 0x1C */ +} XIC_TypeDef; + +/** AP XIC_0 for IPC/APB base pointer */ +#define APXIC_0 ((XIC_TypeDef *)APXIC0_BASE_ADDR) + +/** AP XIC_1 for APB/AHB base pointer */ +#define APXIC_1 ((XIC_TypeDef *)APXIC1_BASE_ADDR) + +/** AP ULDP XIC_2 base pointer */ +#define APXIC_2 ((XIC_TypeDef *)APXIC2_BASE_ADDR) + +/** AP USB XIC_3 base pointer */ +#define APXIC_3 ((XIC_TypeDef *)APXIC3_BASE_ADDR) + + +/** + * @} + */ /* end of group XIC */ +/** @addtogroup DMA DMA + * @{ + */ + +/** @brief Number of DMA channel */ +#define DMA_NUMBER_OF_HW_CHANNEL_SUPPORTED (8U) + +/** @brief List of DMA request sources */ +typedef enum +{ + DMA_MEMORY_TO_MEMORY = -1, /**< Dummy for memory to memory transfer */ + DMA_REQUEST_LPUSART_RX = 4, /**< LPUSART RX */ + DMA_REQUEST_USART0_TX, /**< USART0 TX */ + DMA_REQUEST_USART0_RX, /**< USART0 RX */ + DMA_REQUEST_USART1_TX, /**< USART1 TX */ + DMA_REQUEST_USART1_RX, /**< USART1 RX */ + DMA_REQUEST_USART2_TX, /**< USART2 TX */ + DMA_REQUEST_USART2_RX, /**< USART2 RX */ + DMA_REQUEST_SPI0_TX, /**< SPI0 TX */ + DMA_REQUEST_SPI0_RX, /**< SPI0 RX */ + DMA_REQUEST_SPI1_TX, /**< SPI1 TX */ + DMA_REQUEST_SPI1_RX, /**< SPI1 RX */ + DMA_REQUEST_I2S0_TX, /**< I2S0 TX */ + DMA_REQUEST_I2S0_RX, /**< I2S0 RX */ + DMA_REQUEST_I2S1_TX, /**< I2S1 TX */ + DMA_REQUEST_I2S1_RX, /**< I2S1 RX */ + + + DMA_REQUEST_I2C0_TX = 3, /**< I2C0 TX */ + DMA_REQUEST_I2C0_RX, /**< I2C0 RX */ + DMA_REQUEST_I2C1_TX, /**< I2C1 TX */ + DMA_REQUEST_I2C1_RX, /**< I2C1 RX */ + DMA_REQUEST_USIM0_TX, /**< USIM0 TX */ + DMA_REQUEST_USIM0_RX, /**< USIM0 RX */ + DMA_REQUEST_USIM1_TX, /**< USIM1 TX */ + DMA_REQUEST_USIM1_RX, /**< USIM1 RX */ + + DMA_REQUEST_FLASH_TX = 44, /**< FLASH TX */ + DMA_REQUEST_FLASH_RX, /**< FLASH RX */ + DMA_REQUEST_PSRAM_TX, + DMA_REQUEST_PSRAM_RX, + DMA_REQUEST_UNILOG_TX, /**< UNILOG TX */ +} DmaRequestSource_e; + +/** @brief DMA channel mapping */ +#define UNILOG_TX_CHANNEL (0) + +/** + * @} + */ /* end of group DMA */ + + +/* End of section using anonymous unions and disabling warnings */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/** @addtogroup Bit_Field_Access_Macros Macros for use with bit field definitions (xxx_Pos, xxx_Msk) + * @{ + */ + +/** + * @brief Mask and shift a bit field value for use in a register bit range + * + * @param[in] field Name of the register bit field + * @param[in] value Value of the bit field + * @return Masked and shifted value + */ +#define EIGEN_VAL2FLD(field, value) (((value) << field ## _Pos) & field ## _Msk) + +/** + * @brief Mask and shift a register value to extract a bit filed value + * + * @param[in] field Name of the register bit field + * @param[in] value Value of register + * @return Masked and shifted bit field value +*/ +#define EIGEN_FLD2VAL(field, value) (((value) & field ## _Msk) >> field ## _Pos) + +/** + * @} + */ /* end of group Bit_Field_Access_Macros */ + +/** + * @} + */ /* end of group Device_peripheral_access */ + +#ifdef __cplusplus +} +#endif + +#endif /* EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/flash_rt.h b/PLAT/driver/chip/ec618/ap/inc/flash_rt.h new file mode 100644 index 0000000..fe2bfb7 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/flash_rt.h @@ -0,0 +1,80 @@ +/****************************************************************************** + + *(C) Copyright 2018 AirM2M International Ltd. + + * All Rights Reserved + + ****************************************************************************** + * Filename:flash_rt.h + * + * Description:EC618 flash header file + * + * History: + * + * Notes: + * + ******************************************************************************/ + + +#ifndef _FLASH_EC618_RT_H +#define _FLASH_EC618_RT_H +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +/* QSPI Error codes */ +#define QSPI_OK ((uint8_t)0x00) +#define QSPI_ERROR ((uint8_t)0x01) +#define QSPI_BUSY ((uint8_t)0x02) +#define QSPI_NOT_SUPPORTED ((uint8_t)0x04) +#define QSPI_SUSPENDED ((uint8_t)0x08) + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ +typedef enum +{ + QSPI_OP_ERASE = 0, + QSPI_OP_WRITE, +}QSPI_OpType_e; + + +/** + \brief definition of the flash operation callback, register using BSP_QSPI_Reg_Operation_Cb + call when flash erase and write happens. + \param[in] result the QSPI Error codes, listed above + \param[in] type to indicate erase or write + \param[in] address operation address + \param[in] size operation size + \return null +*/ +typedef void (*BSP_QSPI_OperCallback_t)(uint8_t result, QSPI_OpType_e type, uint32_t address, uint32_t size); + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ + +uint8_t BSP_QSPI_Cfg_Gran_Size(uint16_t WriteGranSize); +uint8_t BSP_QSPI_Erase_Safe(uint32_t SectorAddress, uint32_t Size); +uint8_t BSP_QSPI_Write_Safe(uint8_t* pData, uint32_t WriteAddr, uint32_t Size); +uint8_t BSP_QSPI_Read_Safe(uint8_t* pData, uint32_t WriteAddr, uint32_t Size); + +/** + \fn void BSP_QSPI_Reg_Operation_Cb(BSP_QSPI_OperCallback_t cb); + \brief register a user callback to get flash operation info. No time consuming operation allowed in this callback. +*/ +void BSP_QSPI_Reg_Operation_Cb(BSP_QSPI_OperCallback_t cb); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/PLAT/driver/chip/ec618/ap/inc/gpio.h b/PLAT/driver/chip/ec618/ap/inc/gpio.h new file mode 100644 index 0000000..e069618 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/gpio.h @@ -0,0 +1,192 @@ + /**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: gpio.h + * Description: EC618 gpio driver header file + * History: + * + ****************************************************************************/ + +#ifndef _GPIO_EC618_H +#define _GPIO_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup gpio_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief GPIO pin direction */ +typedef enum +{ + GPIO_DIRECTION_INPUT = 0U, /**< Set pin as input */ + GPIO_DIRECTION_OUTPUT = 1U, /**< Set pin as output */ +} GpioPinDirection_e; + +/** \brief GPIO pin interrupt configuration */ +typedef enum +{ + GPIO_INTERRUPT_DISABLED = 0U, /**< Disable interrupt */ + GPIO_INTERRUPT_LOW_LEVEL = 1U, /**< Low-level interrupt */ + GPIO_INTERRUPT_HIGH_LEVEL = 2U, /**< High-level interrupt */ + GPIO_INTERRUPT_FALLING_EDGE = 3U, /**< Falling edge interrupt */ + GPIO_INTERRUPT_RISING_EDGE = 4U, /**< Rising edge interrupt */ +} GpioInterruptConfig_e; + +/** \brief GPIO pin configuration structure */ +typedef struct +{ + GpioPinDirection_e pinDirection; /**< GPIO direction, input or output */ + union + { + GpioInterruptConfig_e interruptConfig; /**< Pin's interrupt configuration, valid when pinDirection is input */ + uint32_t initOutput; /**< Initial pin output value, valid when pinDirection is output*/ + } misc; +} GpioPinConfig_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \name GPIO Driver Initialization */ +/** \{ */ + +/** + \fn void GPIO_driverInit(void); + \brief Intialize GPIO driver internal data + \note It is not necessarty to call this function before using GPIO driver since it has been + called in \ref GPIO_pinConfig() api. + */ +void GPIO_driverInit(void); + +/** + \fn void GPIO_driverDeInit(void); + \brief De-Intialize GPIO driver, disable GPIO clock and perform some clearups + */ +void GPIO_driverDeInit(void); + +/** \} */ + +/** \name GPIO Configuration */ +/** \{ */ + +/** + \fn void GPIO_pinConfig(uint32_t port, uint16_t pin, const GpioPinConfig_t *config); + \brief Configure a GPIO pin + \param[in] port GPIO number (0, 1, ...) + \param[in] pin GPIO pin number + \param[in] config Pointer to GPIO pin configuration + */ +void GPIO_pinConfig(uint32_t port, uint16_t pin, const GpioPinConfig_t *config); + +/** + \fn void GPIO_interruptConfig(uint32_t port, uint16_t pin, GpioInterruptConfig_e config); + \brief Configure a GPIO pin's interrupt type(valid when this pin has been set as input) + \param[in] port GPIO number (0, 1, ...) + \param[in] pin GPIO pin number + \param[in] config GPIO interrupt configuration + */ +void GPIO_interruptConfig(uint32_t port, uint16_t pin, GpioInterruptConfig_e config); + +/** \} */ + +/** \name GPIO Output Operations */ +/** \{ */ + +/** + \fn void GPIO_pinWrite(uint32_t port, uint16_t pinMask, uint16_t output); + \brief Sets output level of multiple GPIO pins to logic 1 or 0 + + \code + Example to set bits[15,1:0] to 1 and clear bits[12:11, 7:6] + + // pinMask shall be b10011000 11000011 = 0x98C3 + // output shall be b10000000 00000011 = 0x8003 + GPIO_pinWrite(0, 0x98C3, 0x8003); + // To set a single pin, let's say, pin 12 of GPIO0 + GPIO_pinWrite(0, 1 << 12, 1 << 12); + // To clear a single pin, let's say, pin 12 of GPIO0 + GPIO_pinWrite(0, 1 << 12, 0); + + \endcode + + \param[in] port GPIO number (0, 1, ...) + \param[in] pinMask GPIO pin mask to set + \param[in] output GPIO pin output logic level. + - 0: corresponding pin output low-logic level. + - 1: corresponding pin output high-logic level. + */ +void GPIO_pinWrite(uint32_t port, uint16_t pinMask, uint16_t output); + +/** \} */ + +/** \name GPIO Input Operations */ +/** \{ */ + +/** + \fn uint32_t GPIO_pinRead(uint32_t port, uint16_t pin) + \brief Reads current input value of GPIO specific pin + \param[in] port GPIO number (0, 1, ...) + \param[in] pin GPIO pin number + \return GPIO corresponding pin input value + */ +uint32_t GPIO_pinRead(uint32_t port, uint16_t pin); + +/** \} */ + +/** \name GPIO Interrupt */ +/** \{ */ + +/** + \fn uint16_t GPIO_getInterruptFlags(uint32_t port) + \brief Reads GPIO port interrupt status flags + \param[in] port GPIO number (0, 1, ...) + \return current GPIO interrupt status flag + */ +uint16_t GPIO_getInterruptFlags(uint32_t port); + +/** + \fn void GPIO_clearInterruptFlags(uint32_t port, uint16_t mask) + \brief Clears multiple GPIO pin interrupt status flags + \param[in] port GPIO number (0, 1, ...) + \param[in] mask GPIO pin number macro + */ +void GPIO_clearInterruptFlags(uint32_t port, uint16_t mask); + +/** + \fn uint16_t GPIO_saveAndSetIrqMask(uint32_t port) + \brief Reads GPIO port interrupt enable mask and diables whole port interrupts + \param[in] port GPIO number (0, 1, ...) + \return current GPIO port interrupt enable mask + \note Used in GPIO ISR to disable GPIO interrupts temporarily + */ +uint16_t GPIO_saveAndSetIrqMask(uint32_t port); + +/** + \fn void GPIO_restoreIrqMask(uint32_t port, uint16_t mask) + \brief Restore GPIO port interrupt enable setting + \param[in] port GPIO number (0, 1, ...) + \param[in] mask GPIO interrupt enable mask + \note Used in GPIO ISR to restore GPIO enable setting upon exit + */ +void GPIO_restoreIrqMask(uint32_t port, uint16_t mask); + +/** \} */ + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/gpr_common.h b/PLAT/driver/chip/ec618/ap/inc/gpr_common.h new file mode 100644 index 0000000..d48dbc6 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/gpr_common.h @@ -0,0 +1,310 @@ +#define RMI_GPR_TOP_CLKEN_REG_INDEX (0) +#define RMI_GPR_XPSYS_CLKEN_REG_INDEX (1) + +#define APB_GPR_TOP_MP_CLKEN_REG_INDEX (2) +#define APB_GPR_TOP_AP_CLKEN_REG_INDEX (3) + +#define APB_GPR_APB_MP_PCLK_EN_REG_INDEX (4) +#define APB_GPR_APB_AP_PCLK_EN_REG_INDEX (5) + +#define APB_GPR_APB_MP_FCLK_EN_REG_INDEX (6) +#define APB_GPR_APB_AP_FCLK_EN_REG_INDEX (7) + +#define APB_GPR_TOP_ALL_CLKEN_REG_INDEX (8) + +#define CLKEN_REG_INDEX_MAX (0xF) + +/** +|-----registerAccessIndex-----|-----bitPosition-----|---------index---------| +|------------4 bit------------|--------5 bit--------|---------8 bit---------| +*/ +#define CONSTRUCT_CLOCK_ID(registerAccessIndex, bitPosition, index) \ + (((registerAccessIndex) << 13) | ((bitPosition) << 8) | (index)) + + +/** Macro to extract index from clock id value */ +#define GET_INDEX_FROM_CLOCK_ID(value) ((value) & 0xFFU) + +/** Macro to extract bitPosition from clock id value */ +#define GET_BP_FROM_CLOCK_ID(value) ((value >> 8U) & 0x1FU) + +/** Macro to extract registerAccessIndex from clock id value */ +#define GET_RAI_FROM_CLOCK_ID(value) ((value >> 13U) & 0xFU) + +/** + |-----clockIdIndex-----|-----value-----|-----parentClockId-----| + |---------8 bit--------|-----4 bit-----|--------17 bit---------| + */ +/** Macro to compose clock select value */ +#define MAKE_CLOCK_SEL_VALUE(clockIdIndex, value, parentClockId) \ + ((clockIdIndex << 21U) | value << 17U | parentClockId) + +/** Macro to extract clockId from clock select value */ +#define GET_CLOCKIDINDEX_FROM_CLOCK_SEL_VALUE(value) ((value >> 21U) & 0xFFUL) + +/** Macro to extract value from clock select value */ +#define GET_VALUE_FROM_CLOCK_SEL_VALUE(value) ((value >> 17U) & 0xFUL) + +/** Macro to extract parentClockId from clock select value */ +#define GET_PARENTCLOCKID_FROM_CLOCK_SEL_VALUE(value) (value & 0x1FFFFUL) + + +#define APB_GPR_TOP_AP_RST_REQ_REG_INDEX (0) +#define APB_GPR_APB_MP_PRST_REQ_REG_INDEX (1) + +#define APB_GPR_APB_AP_PRST_REQ_REG_INDEX (2) +#define APB_GPR_APB_MP_FRST_REQ_REG_INDEX (3) +#define APB_GPR_APB_AP_FRST_REQ_REG_INDEX (4) + +#define RMI_GPR_TOP_RSTREQ_REG_INDEX (5) +#define RMI_GPR_XPSYS_RSTREQ_REG_INDEX (6) + + +/** +|-----registerAccessIndex-----|-----bitPosition-----| +|------------4 bit------------|--------8 bit--------| +*/ +#define CONSTRUCT_CLOCK_RESET_ID(registerAccessIndex, bitPosition) \ + (((registerAccessIndex) << 8) | (bitPosition)) + +/** Macro to extract bitPosition from clock reset id value */ +#define GET_BP_FROM_CLOCK_RESET_ID(value) ((value) & 0xFFU) + +/** Macro to extract registerAccessIndex from clock reset id value */ +#define GET_RAI_FROM_CLOCK_RESET_ID(value) ((value >> 8U) & 0xFU) + + +/** \brief List of IDs used for sw reset control */ +typedef enum +{ + /* Top AP Reset */ + RST_AP_FABSYS_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 0), /**< Ap fab sys AHB reset */ + RST_AP_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 1), /**< Ap RMI AHB reset */ + RST_MFAB_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 2), /**< MFAB AHB reset */ + RST_AFBBR_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 3), /**< AFBBR AHB reset */ + RST_CFBBR_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 4), /**< CFBBR AHB reset */ + RST_MSMB_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 5), /**< MSMB AHB reset */ + RST_FLASH_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 6), /**< Flash AHB reset */ + RST_PSRAM_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 7), /**< Psram AHB reset */ + RST_ULOG_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 8), /**< Unilog AHB reset */ + RST_USBC_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 9), /**< Usbc AHB reset */ + RST_CLK_FLASH = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 10), /**< Flash Func reset */ + RST_CLK_PSRAM = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 11), /**< Psram Func reset */ + RST_AONIF = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 12), /**< Aonif reset */ + RST_LPUA = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 13), /**< Lpua reset */ + RST_CLK_FRACDIV = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 14), /**< Fracdiv reset */ + RST_ULOG_SMP = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 15), /**< Unilog Smp reset */ + RST_FCLK_FUSE = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 16), /**< Fuse Func reset */ + RST_UTFC_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 17), /**< UTfc AHB reset */ + RST_ULDP_HCLK = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 18), /**< Uldp AHB reset */ + // reserved = 19~26, + RST_USBC_PHY = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 27), /**< Usbc PHY reset */ + RST_USBP_POR = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 28), /**< USBP Por reset */ + RST_USBP_UTMI = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_TOP_AP_RST_REQ_REG_INDEX, 29), /**< USBP Utmi reset */ + + /* APB MP Reset */ + // reserved = 0, + RST_PCLK_SIPC = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 1), /**< Sipc APB reset */ + RST_PCLK_AON = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 2), /**< Aon APB reset */ + RST_PCLK_CPMU = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 3), /**< Cpmu APB reset */ + RST_PCLK_PMDIG = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 4), /**< Pmdig APBreset */ + RST_PCLK_RFDIG = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 5), /**< Rfdig APB reset */ + RST_PCLK_PAD = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 6), /**< Pad APB reset */ + RST_PCLK_GPIO = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 7), /**< Gpio APB reset */ + RST_PCLK_FUSE = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 8), /**< Fuse APB reset */ + RST_PCLK_TRNG = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 9), /**< Trng APB reset */ + RST_PCLK_USBP = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 10), /**< Usbp APB reset */ + RST_PCLK_LPUC = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 11), /**< Lpuc APB reset */ + RST_PCLK_UART0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 12), /**< Uart0 APB reset */ + RST_PCLK_UART1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 13), /**< Uart1 APB reset */ + RST_PCLK_UART2 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 14), /**< Uart2 APB reset */ + RST_PCLK_SPI0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 15), /**< Ssp 0 APB reset */ + RST_PCLK_SPI1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 16), /**< Ssp 1 APB reset */ + RST_PCLK_I2S0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 17), /**< I2s 0 APB reset */ + RST_PCLK_I2S1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_PRST_REQ_REG_INDEX, 18), /**< I2s 1 APB reset */ + + /* APB AP Reset */ + RST_PCLK_WDG = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 0), /**< WDG APB reset */ + RST_PCLK_TIMER0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 1), /**< Timer0 APB reset */ + RST_PCLK_TIMER1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 2), /**< Timer1 APBreset */ + RST_PCLK_TIMER2 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 3), /**< Timer2 APB reset */ + RST_PCLK_TIMER3 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 4), /**< Timer3 APB reset */ + RST_PCLK_TIMER4 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 5), /**< Timer4 APB reset */ + RST_PCLK_TIMER5 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 6), /**< Timer5 APB reset */ + RST_PCLK_IPC = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 7), /**< IPC APB reset */ + RST_PCLK_I2C0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 8), /**< I2C0 APB reset */ + RST_PCLK_I2C1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 9), /**< I2C1 APB reset */ + RST_PCLK_USIM0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 10), /**< USIM0 APB reset */ + RST_PCLK_USIM1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 11), /**< USIM1 APB reset */ + RST_PCLK_KPC = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 12), /**< KPC APB reset */ + RST_PCLK_ONEW = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_PRST_REQ_REG_INDEX, 13), /**< ONEW APB reset */ + + + /* APB MP Func Reset */ + RST_FCLK_UART0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 0), /**< Uart0 Func reset */ + RST_FCLK_UART1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 1), /**< Uart1 Func reset */ + RST_FCLK_UART2 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 2), /**< Uart2 Func reset */ + RST_FCLK_SPI0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 3), /**< SSP0 Func reset */ + RST_FCLK_SPI1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 4), /**< SSP1 Func reset */ + RST_FCLK_I2S0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 5), /**< I2S0 Func reset */ + RST_FCLK_I2S1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_MP_FRST_REQ_REG_INDEX, 6), /**< I2S1 Func reset */ + + /* APB AP Func Reset */ + RST_FCLK_WDG = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 0), /**< WDG Func reset */ + RST_FCLK_TIMER0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 1), /**< TIMER0 Func reset */ + RST_FCLK_TIMER1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 2), /**< TIMER1 Func reset */ + RST_FCLK_TIMER2 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 3), /**< TIMER2 Func reset */ + RST_FCLK_TIMER3 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 4), /**< TIMER3 Func reset */ + RST_FCLK_TIMER4 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 5), /**< TIMER4 Func reset */ + RST_FCLK_TIMER5 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 6), /**< TIMER5 Func reset */ + RST_FCLK_I2C0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 7), /**< I2C0 Func reset */ + RST_FCLK_I2C1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 8), /**< I2C1 Func reset */ + RST_FCLK_USIM0 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 9), /**< USIM0 Func reset */ + RST_FCLK_USIM1 = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 10), /**< USIM1 Func reset */ + RST_FCLK_KPC = CONSTRUCT_CLOCK_RESET_ID(APB_GPR_APB_AP_FRST_REQ_REG_INDEX, 11), /**< KPC Func reset */ + + /* RMI TOP Reset */ + RST_TOP_PBRG_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_TOP_RSTREQ_REG_INDEX, 0), /**< DMA AHB domain reset */ + RST_TOP_PBRG_PCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_TOP_RSTREQ_REG_INDEX, 1), /**< DMA APB domain reset */ + RST_TOP_GPR_PCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_TOP_RSTREQ_REG_INDEX, 2), /**< GPR APB domain reset */ + + /* RMI XPSYS Reset */ + RST_CACHE_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 0), /**< GPR CACHE AHB domain reset */ + RST_FABSUB_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 1), /**< GPR FABSUB AHB domain reset */ + RST_SBU_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 2), /**< GPR SBU AHB domain reset */ + RST_PBRG_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 3), /**< GPR PDMA AHB domain reset */ + RST_SPIS_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 4), /**< GPR SPIS AHB domain reset */ + RST_XIC_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 5), /**< GPR XIC AHB domain reset */ + RST_ULOG_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 6), /**< GPR ULOG AHB domain reset */ + RST_TMU_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 7), /**< GPR TMU AHB domain reset */ + RST_SCT_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 8), /**< GPR SCT AHB domain reset */ + + RST_UTFC_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 11), /**< GPR UTFC AHB domain reset */ + RST_ULDP_RMI_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 12), /**< GPR ULDP AHB domain reset */ + RST_SCT_HCLK = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 13), /**< GPR SCT AHB reset */ + RST_PCLK_DMA = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 15), /**< GPR PDMA APB reset */ + RST_TMU_SMP = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 16), /**< GPR TMU SMP reset */ + RST_TMU_CLKCAL = CONSTRUCT_CLOCK_RESET_ID(RMI_GPR_XPSYS_RSTREQ_REG_INDEX, 17), /**< GPR TMU CLKCAL reset */ +} ClockResetId_e; + +/** \brief typedef for reset whole module */ +typedef struct +{ + uint32_t idNumber; /**< number of ids this module contains */ + uint32_t delayCpuCycles; /**< the cycles need to delay after release */ + const ClockResetId_e* resetReleaseQueue; /**< pointer to the queue(array) of ids, reset & release operation sequence + depends on the position of id in the array, so arrange it properly */ +} ClockResetVector_t; + +#define RESET_RELEASE_DELAY_US (204) + +#define MAKE_RESET_VECTOR(delay, ...) \ + { \ + (sizeof((ClockResetId_e [])__VA_ARGS__) / sizeof(ClockResetId_e)), \ + (delay), \ + (const ClockResetId_e [])__VA_ARGS__ \ + } + +#define RESET_VECTOR_PTR(v) ((ClockResetVector_t [])v) + +#define UART0_RESET_VECTOR MAKE_RESET_VECTOR(RESET_RELEASE_DELAY_US, {RST_PCLK_UART0, RST_FCLK_UART0, RST_PCLK_UART0, RST_FCLK_UART0}) +#define UART1_RESET_VECTOR MAKE_RESET_VECTOR(RESET_RELEASE_DELAY_US, {RST_PCLK_UART1, RST_FCLK_UART1, RST_PCLK_UART1, RST_FCLK_UART1}) +#define UART2_RESET_VECTOR MAKE_RESET_VECTOR(RESET_RELEASE_DELAY_US, {RST_PCLK_UART2, RST_FCLK_UART2, RST_PCLK_UART2, RST_FCLK_UART2}) + +#define SPI0_RESET_VECTOR MAKE_RESET_VECTOR(RESET_RELEASE_DELAY_US, {RST_PCLK_SPI0, RST_FCLK_SPI0, RST_PCLK_SPI0, RST_FCLK_SPI0}) +#define SPI1_RESET_VECTOR MAKE_RESET_VECTOR(RESET_RELEASE_DELAY_US, {RST_PCLK_SPI1, RST_FCLK_SPI1, RST_PCLK_SPI1, RST_FCLK_SPI1}) + +#define KPC_RESET_VECTOR MAKE_RESET_VECTOR(RESET_RELEASE_DELAY_US, {RST_PCLK_KPC, RST_FCLK_KPC, RST_PCLK_KPC, RST_FCLK_KPC}) + +typedef enum +{ + FRACDIV_ROOT_CLK_26M, + FRACDIC_ROOT_CLK_408M +} FracDivRootClk_e; + +typedef struct +{ + FracDivRootClk_e source; + uint32_t fracDiv0DivRatioInteger; + uint32_t fracDiv0DivRatioFrac; + uint32_t fracDiv1DivRatioInteger; + uint32_t fracDiv1DivRatioFrac; +} FracDivConfig_t; + +typedef enum +{ + FRACDIV0_OUT0, + FRACDIV0_OUT1, + FRACDIV0_OUT2, + FRACDIV0_OUT3, + + FRACDIV1_OUT0, + FRACDIV1_OUT1, + FRACDIV1_OUT2, + FRACDIV1_OUT3 +} FracDivOutClkId_e; + +typedef enum +{ + BCLK0, + BCLK1 +} BclkId_e; + +typedef enum +{ + MCLK0, + MCLK1, + MCLK2 +} MclkId_e; + +typedef enum +{ + BCLK_SRC_FRACDIV0_OUT0 = 1, + BCLK_SRC_FRACDIV0_OUT1 = 2, + BCLK_SRC_FRACDIV0_OUT2 = 3, + BCLK_SRC_FRACDIV0_OUT3 = 4, + + BCLK_SRC_FRACDIV1_OUT0 = 5, + BCLK_SRC_FRACDIV1_OUT1 = 6, + BCLK_SRC_FRACDIV1_OUT2 = 7, + BCLK_SRC_FRACDIV1_OUT3 = 8, + BCLK_SRC_CLK_MFG = 9, + BCLK_SRC_19P2M = 10 +} BclkSrc_e; + +typedef enum +{ + MCLK_SRC_FRACDIV0_OUT0 = 1, + MCLK_SRC_FRACDIV0_OUT1 = 2, + MCLK_SRC_FRACDIV0_OUT2 = 3, + MCLK_SRC_FRACDIV0_OUT3 = 4, + + MCLK_SRC_FRACDIV1_OUT0 = 5, + MCLK_SRC_FRACDIV1_OUT1 = 6, + MCLK_SRC_FRACDIV1_OUT2 = 7, + MCLK_SRC_FRACDIV1_OUT3 = 8, + MCLK_SRC_CLK_MFG = 9, + MCLK_SRC_19P2M = 10, + MCLK_SRC_CLK_SMP = 11, + MCLK_SRC_CLK_USBP_12M = 12, + MCLK_SRC_CLK_USBP_48M = 13, + MCLK_SRC_CLK_USBC_PHY = 14, +} MclkSrc_e; + +typedef enum +{ + GPR_APRST_SWRST = 0, + GPR_APRST_WDG, + GPR_APRST_LOCKUP, + GPR_APRST_INVALID, +}ApRstSource_e; + +typedef enum +{ + GPR_CPRST_SWRST = 0, + GPR_CPRST_WDG, + GPR_CPRST_LOCKUP, + GPR_CPRST_INVALID, +}CpRstSource_e; + + diff --git a/PLAT/driver/chip/ec618/ap/inc/i2s.h b/PLAT/driver/chip/ec618/ap/inc/i2s.h new file mode 100644 index 0000000..9e2e4dc --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/i2s.h @@ -0,0 +1,315 @@ +#ifndef BSP_I2S_H +#define BSP_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" +#include "hal_i2s.h" // To use some of typedef in this H file and the macro of DMA_CHAIN_NUM(can dynamic array in C99?) + +#define POLLING_MODE 0x1 +#define DMA_MODE 0x2 + + +////////////////////////////////////////////////////////////////////////////////////////////// +// I2S Setting field Start +// All the I2S's parameters that need user to set are all put here +////////////////////////////////////////////////////////////////////////////////////////////// +#define ES8388_IICADDR 0x11 +#define NAU88C22_IICADDR 0x1A +#define ES8311_IICADDR 0x18 + +// Sample rate that 618 supports +#define SAMPLE_RATE_8K 0x1 +#define SAMPLE_RATE_16K 0x2 +#define SAMPLE_RATE_32K 0x3 +#define SAMPLE_RATE_22_05K 0x4 +#define SAMPLE_RATE_44_1K 0x5 +#define SAMPLE_RATE_48K 0x6 +#define SAMPLE_RATE_96K 0x7 + + +// I2S0 Configuration +#define RTE_I2S0 1 +#define RTE_I2S0_IO_MODE DMA_MODE + +#define RTE_I2S0_MCLK_PAD_ADDR 39 +#define RTE_I2S0_MCLK_FUNC PAD_MUX_ALT1 + +#define RTE_I2S0_BCLK_PAD_ADDR 35 +#define RTE_I2S0_BCLK_FUNC PAD_MUX_ALT1 + +#define RTE_I2S0_LRCK_PAD_ADDR 36 +#define RTE_I2S0_LRCK_FUNC PAD_MUX_ALT1 + +#define RTE_I2S0_DIN_PAD_ADDR 37 +#define RTE_I2S0_DIN_FUNC PAD_MUX_ALT1 + +#define RTE_I2S0_DOUT_PAD_ADDR 38 +#define RTE_I2S0_DOUT_FUNC PAD_MUX_ALT1 + +// I2S1 Configuration +#define RTE_I2S1 0 +#define RTE_I2S1_IO_MODE DMA_MODE + +#define RTE_I2S1_MCLK_PAD_ADDR 18 +#define RTE_I2S1_MCLK_FUNC PAD_MUX_ALT1 + +#define RTE_I2S1_BCLK_PAD_ADDR 19 +#define RTE_I2S1_BCLK_FUNC PAD_MUX_ALT1 + +#define RTE_I2S1_LRCK_PAD_ADDR 20 +#define RTE_I2S1_LRCK_FUNC PAD_MUX_ALT1 + +#define RTE_I2S1_DIN_PAD_ADDR 21 +#define RTE_I2S1_DIN_FUNC PAD_MUX_ALT1 + +#define RTE_I2S1_DOUT_PAD_ADDR 22 +#define RTE_I2S1_DOUT_FUNC PAD_MUX_ALT1 + +////////////////////////////////////////////////////////////////////////////////////////////// +// I2S Setting field End +////////////////////////////////////////////////////////////////////////////////////////////// + +/****** I2S Event *****/ +#define I2S_EVENT_TRANSFER_COMPLETE (1UL << 0) // Data Transfer completed +#define I2S_EVENT_DATA_LOST (1UL << 1) // Data lost: Receive overflow / Transmit underflow +#define I2S_EVENT_MODE_FAULT (1UL << 2) // Master Mode Fault (SS deactivated when Master) + +// DMA I2S0 Request ID +#define RTE_I2S0_DMA_TX_REQID DMA_REQUEST_I2S0_TX +#define RTE_I2S0_DMA_RX_REQID DMA_REQUEST_I2S0_RX + +// DMA I2S1 Request ID +#define RTE_I2S1_DMA_TX_REQID DMA_REQUEST_I2S1_TX +#define RTE_I2S1_DMA_RX_REQID DMA_REQUEST_I2S1_RX + +typedef void (*i2sCbEvent_fn) (uint32_t event, uint32_t arg); // i2s callback event. + + +// I2S IRQ +typedef struct +{ + IRQn_Type irqNum; // I2S IRQ Number + IRQ_Callback_t cbIrq; +} i2sIrq_t; + +// I2S DMA +typedef struct +{ + DmaInstance_e txInstance; // Transmit DMA instance number + int8_t txCh; // Transmit channel number + uint8_t txReq; // Transmit DMA request number + void (*txCb)(uint32_t event); // Transmit callback + DmaDescriptor_t *txDescriptor; // Tx descriptor + DmaInstance_e rxInstance; // Receive DMA instance number + int8_t rxCh; // Receive channel number + uint8_t rxReq; // Receive DMA request number + void (*rxCb)(uint32_t event); // Receive callback + DmaDescriptor_t *rxDescriptor; // Rx descriptor +} i2sDma_t; + + +// I2S PINS +typedef const struct +{ + PIN *mclk; // main clk Pin identifier + PIN *bclk; // pixel clk Pin identifier + PIN *lrck; // cs Pin identifier + PIN *din; // din Pin identifier + PIN *dout; // dout Pin identifier +} i2sPins_t; + + +typedef struct +{ + uint8_t busy; // Transmitter/Receiver busy flag + uint8_t dataLost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint8_t modeFault; // Mode fault detected; optional (cleared on start of transfer operation) +} i2sStatus_t; + +// I2S Transfer Information (Run-Time) +typedef struct +{ + uint32_t num; // Total number of transfers + uint8_t *rxBuf; // Pointer to in data buffer + uint8_t *txBuf; // Pointer to out data buffer + uint32_t rxCnt; // Number of data received + uint32_t txCnt; // Number of data sent + uint32_t dumpVal; // Variable for dumping DMA data + uint16_t defVal; // Default transfer value +} i2sTransferInfo_t; + +// I2S information (Run-time) +typedef struct +{ + i2sCbEvent_fn txCbEvent; // tx event callback + i2sCbEvent_fn rxCbEvent; // rx event callback + uint32_t mode; // I2S mode + uint32_t busSpeed; // I2S bus speed + uint16_t chainCnt; + uint32_t totalNum; // Total length of audio source +} i2sInfo_t; + + +// I2S Resources definition +typedef struct +{ + I2S_TypeDef *reg; // I2S register pointer + i2sPins_t pins; // I2S PINS configuration + i2sDma_t *dma; // I2S DMA configuration pointer + i2sIrq_t *irq; // I2S IRQ configuration pointer + i2sInfo_t *info; // Run-Time Information +} i2sResources_t; + +/** +\brief General power states +*/ +typedef enum +{ + I2S_POWER_OFF, // Power off: no operation possible + I2S_POWER_FULL // Power on: full operation at maximum performance +} i2sPowerState_e; + + +/** +\brief Access structure of the I2S Driver. +*/ +typedef struct +{ + int32_t (*init) (i2sCbEvent_fn txCbEvent, i2sCbEvent_fn rxCbEvent); // Initialize I2S Interface. + int32_t (*deInit) (void); // De-initialize I2S Interface. + int32_t (*powerCtrl) (i2sPowerState_e state); // Control I2S Interface Power. + int32_t (*send) (void *data, uint32_t chunkNum); // Start sending data from I2S Interface. + int32_t (*recv) (void *data, uint32_t chunkNum); // Start receiving data from I2S Interface. + int32_t (*ctrl) (uint32_t control, uint32_t arg); // Control I2S Interface. + uint32_t (*getTotalCnt) (void); +} const i2sDrvInterface_t; + +typedef struct +{ + uint32_t slaveModeEn : 1; // Slave Mode Enable + uint32_t slotSize : 5; // Slot Size + uint32_t wordSize : 5; // Word Size + uint32_t alignMode : 1; // Align Mode + uint32_t endianMode : 1; // Endian Mode + uint32_t dataDly : 2; // Data Delay + uint32_t txPad : 2; // Tx Padding + uint32_t rxSignExt : 1; // Rx Sign extention + uint32_t txPack : 2; // Tx Pack + uint32_t rxPack : 2; // Rx Pack + uint32_t txFifoEndianMode : 1; // Tx Fifo Endian Mode + uint32_t rxFifoEndianMode : 1; // Rx Fifo Endian Mode +}i2sDataFmt_t; + +/** \brief I2S Slot Control */ +typedef struct +{ + uint32_t slotEn : 8; // Slot Enable + uint32_t slotNum : 3; // Slot number per frame synchronization +}i2sSlotCtrl_t; + +/** \brief I2S Bclk Frame Synchronization Control */ +typedef struct +{ + uint32_t bclkPolarity : 1; // Bclk Polarity + uint32_t fsPolarity : 1; // Frame Synchronization Polarity + uint32_t fsWidth : 6; // Frame Synchronization width +}i2sBclkFsCtrl_t; + +/** \brief I2S DMA Control */ +typedef struct +{ + uint32_t rxDmaReqEn : 1; // Rx Dma Req Enable + uint32_t txDmaReqEn : 1; // Tx Dma Req Enable + uint32_t rxDmaTimeOutEn : 1; // Rx Dma Timeout Enable + uint32_t dmaWorkWaitCycle : 5; // Dma Work Wait Cycle + uint32_t rxDmaBurstSizeSub1 : 4; // Rx Dma Burst Size subtract 1 + uint32_t txDmaBurstSizeSub1 : 4; // Tx Dma Burst Size subtract 1 + uint32_t rxDmaThreadHold : 4; // Rx Dma Threadhold + uint32_t txDmaThreadHold : 4; // Tx Dma Threadhold + uint32_t rxFifoFlush : 1; // Rx Fifo flush + uint32_t txFifoFlush : 1; // Tx Fifo flush +}i2sDmaCtrl_t; + +/** \brief I2S Interrupt Control */ +typedef struct +{ + uint32_t txUnderRunIntEn : 1; // Tx Underrun interrupt Enable + uint32_t txDmaErrIntEn : 1; // Tx Dma Err Interrupt Enable + uint32_t txDatIntEn : 1; // Tx Data Interrupt Enable + uint32_t rxOverFlowIntEn : 1; // Rx Overflow Interrupt Enable + uint32_t rxDmaErrIntEn : 1; // Rx Dma Err Interrupt Enable + uint32_t rxDatIntEn : 1; // Rx Data Interrupt Enable + uint32_t rxTimeOutIntEn : 1; // Rx Timeout Interrupt Enable + uint32_t fsErrIntEn : 1; // Frame Start Interrupt Enable + uint32_t frameStartIntEn : 1; // Frame End Interrupt Enable + uint32_t frameEndIntEn : 1; // Frame End Interrupt Enable + uint32_t cspiBusTimeOutIntEn : 1; // Not use + uint32_t txIntThreshHold : 4; // Tx Interrupt Threadhold + uint32_t rxIntThreshHold : 4; // Rx Interrupt Threadhold +}i2sIntCtrl_t; + +/** \brief I2S Timeout Cycle */ +typedef struct +{ + uint32_t rxTimeOutCycle : 24; // Rx Timeout cycle +}i2sTimeOutCycle_t; + +/** \brief I2S Status */ +typedef struct +{ + uint32_t txUnderRun : 1; // Tx Underrun + uint32_t txDmaErr : 1; // Tx Dma Err + uint32_t txDataRdy : 1; // Tx Data ready, readOnly + uint32_t rxOverFlow : 1; // Rx OverFlow + uint32_t rxDmaErr : 1; // Rx Dma Err + uint32_t rxDataRdy : 1; // Rx Data ready, readOnly + uint32_t rxFifoTimeOut : 1; // Rx Fifo timeout + uint32_t fsErr : 4; // Frame synchronization Err + uint32_t frameStart : 1; // Frame start + uint32_t frameEnd : 1; // Frame end + uint32_t txFifoLevel : 6; // Tx Fifo Level, readOnly + uint32_t rxFifoLevel : 6; // Rx Fifo level, readOnly + uint32_t cspiBusTimeOut : 1; // Not use +}i2sStats_t; + +/** \brief I2S Control */ +typedef struct +{ + uint32_t i2sMode : 2; // I2S Mode +}i2sCtrl_t; + +/** \brief I2S Auto Configure Control */ +typedef struct +{ + uint32_t autoCgEn : 1; // Auto Configure Enable +}i2sAutoCgCtrl_t; + +/** +\brief I2S control bits. +*/ +#define I2S_CTRL_TRANSABORT (1UL << 0) // I2S trans abort +#define I2S_CTRL_SAMPLE_RATE_SLAVE (1UL << 1) // I2S sample rate setting, used in ec618 slave mode +#define I2S_CTRL_SAMPLE_RATE_MASTER (1UL << 2) // I2S sample rate setting, used in ec618 master mode +#define I2S_CTRL_SET_TOTAL_NUM (1UL << 3) // Audio source total num +#define I2S_CTRL_DATA_FORMAT (1UL << 4) // I2S data format +#define I2S_CTRL_SLOT_CTRL (1UL << 5) // I2S slot ctrl +#define I2S_CTRL_BCLK_FS_CTRL (1UL << 6) // I2S bclk fs ctrl +#define I2S_CTRL_DMA_CTRL (1UL << 7) // I2S dma ctrl +#define I2S_CTRL_INT_CTRL (1UL << 8) // I2S int ctrl +#define I2S_CTRL_TIMEOUT_CYCLE (1UL << 9) // I2S timeout cycle +#define I2S_CTRL_STATUS (1UL << 10) // I2S status +#define I2S_CTRL_I2SCTL (1UL << 11) // I2S control +#define I2S_CTRL_AUTO_CG_CTRL (1UL << 12) // I2S auto cg ctrl +#define I2S_CTRL_INIT (1UL << 13) // I2S init +#define I2S_CTRL_START_STOP (1UL << 14) // I2S audio play start/stop ctrl + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_I2S_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/ic.h b/PLAT/driver/chip/ec618/ap/inc/ic.h new file mode 100644 index 0000000..608385c --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/ic.h @@ -0,0 +1,147 @@ +/**************************************************************************** + * + * Copy right: 2018-, Copyrigths of AirM2M Ltd. + * File name: ic.h + * Description: EC618 interrupt controller header file + * History: Rev1.0 2018-11-15 + * + ****************************************************************************/ + +#ifndef _IC_EC618_H +#define _IC_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup xic_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define NUM_APXIC_MODULE (4U) /**< number of XIC module */ +#define NUM_APXIC0_INT (32U) /**< number of interrupts in XIC0 */ +#define NUM_APXIC1_INT (32U) /**< number of interrupts in XIC1 */ +#define NUM_APXIC2_INT (32U) /**< number of interrupts in XIC2 */ +#define NUM_APXIC3_INT (32U) /**< number of interrupts in XIC3 */ + +/** ISR function type define */ +typedef void ( *ISRFunc_T )(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \fn void IC_PowupInit(void) + \brief Initialize the interrupt controller, including HW configuration and ISR initialization, + called when POR or wakeup from Hibernate, in which the SRAM contents have been lost. + */ +void IC_PowupInit(void); +/** + \fn void IC_Powoff(void) + \brief DeInitialize the interrupt controller, including HW configuration and ISR initialization. + */ +void IC_Powoff(void); +/** + \fn void XIC_SetVector(IRQn_Type IRQn, ISRFunc_T vector) + \brief Sets an XIC interrupt vector in SRAM based interrupt vector table. + Use this function to bind the XIC interrupt and application ISR. + \param[in] IRQn Interrupt number + \param[in] vector Address of interrupt handler function + \note The interrupt number must be positive + */ +void XIC_SetVector(IRQn_Type IRQn, ISRFunc_T vector); + +/** + \fn void XIC_EnableIRQ(IRQn_Type IRQn) + \brief Enables a device specific interrupt in the XIC interrupt controller. + \param[in] IRQn Interrupt number + \note The interrupt number must be positive + */ +void XIC_EnableIRQ(IRQn_Type IRQn); + +/** + \fn void XIC_DisableIRQ(IRQn_Type IRQn) + \brief Disables a device specific interrupt in the XIC interrupt controller. + \param[in] IRQn Interrupt number + \note The interrupt number must be positive + */ +void XIC_DisableIRQ(IRQn_Type IRQn); + +/** + \fn void XIC_BackupIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array) + + \brief backup the interrupt mask and ovf setting before sleep + \param[out] mask_array mask0, mask1, clrovf0 to store the irq mask and ovf setting + \param[out] clrovf_array + \note + */ + +void XIC_BackupIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array); + +/** + \fn void XIC_RestoreIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array) + + \brief restore the interrupt mask and ovf setting after sleep + \param[in] mask_array mask0, mask1, clrovf0 is the stored value before sleep + \param[out] clrovf_array + \note + */ +void XIC_RestoreIRQSetting(uint32_t *mask_array, uint32_t *clrovf_array); + +/** + \fn void XIC_SetPendingIRQ(IRQn_Type IRQn) + \brief Sets the pending bit of a device specific interrupt in the XIC pending register, + mainly used for SW generating interrupt. + \param[in] IRQn Interrupt number + \note The interrupt number must be positive + */ +void XIC_SetPendingIRQ(IRQn_Type IRQn); + +/** + \fn void XIC_ClearPendingIRQ(IRQn_Type IRQn) + \brief Clears the pending bit of a device specific interrupt in the XIC pending register. + \param[in] IRQn Interrupt number + \note The interrupt number must be positive + */ +void XIC_ClearPendingIRQ(IRQn_Type IRQn); + +/** + \fn uint32_t XIC_LatchIRQ(XIC_TypeDef* xic) + \brief Latch the pending interrupt status to the latch register and read out. + \param[in] xic Pointer to XIC instance + \return Interrupt status + */ +uint32_t XIC_LatchIRQ(XIC_TypeDef* xic); + +/** + \fn void XIC_SuppressOvfIRQ(IRQn_Type IRQn) + \brief Suppress overflow IRQ + \param[in] IRQn Interrupt number + \note The interrupt number must be positive + */ +void XIC_SuppressOvfIRQ(IRQn_Type IRQn); + +/** + \fn void XIC_ClearAllPendingIRQ(XIC_TypeDef* xic) + \brief Clears all pending bits of a XIC interrupt controller. + \param[in] xic Pointer to XIC instance + */ +void XIC_ClearAllPendingIRQ(XIC_TypeDef* xic); + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/PLAT/driver/chip/ec618/ap/inc/kpc.h b/PLAT/driver/chip/ec618/ap/inc/kpc.h new file mode 100644 index 0000000..c9a8560 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/kpc.h @@ -0,0 +1,233 @@ +/**************************************************************************** + * + * Copy right: 2020-, Copyrigths of AirM2M Ltd. + * File name: kpc_ec618.h + * Description: EC618 kpc driver header file + * History: Rev1.0 2021-07-23 + * + ****************************************************************************/ + +#ifndef _KPC_EC618_H +#define _KPC_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup kpc_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief List of debounce clock divider ratio */ +typedef enum +{ + KPC_DEBOUNCE_CLK_DIV_RATIO_2 = 1U, /**< KPC debounce clock divider ratio select as 2 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_4 = 2U, /**< KPC debounce clock divider ratio select as 4 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_8 = 3U, /**< KPC debounce clock divider ratio select as 8 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_16 = 4U, /**< KPC debounce clock divider ratio select as 16 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_32 = 5U, /**< KPC debounce clock divider ratio select as 32 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_64 = 6U, /**< KPC debounce clock divider ratio select as 64 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_128 = 7U, /**< KPC debounce clock divider ratio select as 128 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_256 = 8U, /**< KPC debounce clock divider ratio select as 256 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_512 = 9U, /**< KPC debounce clock divider ratio select as 512 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_1024 = 10U, /**< KPC debounce clock divider ratio select as 1024 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_2048 = 11U, /**< KPC debounce clock divider ratio select as 2048 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_4096 = 12U, /**< KPC debounce clock divider ratio select as 4096 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_8192 = 13U, /**< KPC debounce clock divider ratio select as 8192 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_16384 = 14U, /**< KPC debounce clock divider ratio select as 16384 */ + KPC_DEBOUNCE_CLK_DIV_RATIO_32768 = 15U, /**< KPC debounce clock divider ratio select as 32768 */ +} KpcDebounceClkDivRatio_t; + +/** \brief List of debounce width */ +typedef enum +{ + KPC_DEBOUNCE_WIDTH_5_CYCLES = 5U, /**< KPC debounce width is 5 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_6_CYCLES = 6U, /**< KPC debounce width is 6 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_7_CYCLES = 7U, /**< KPC debounce width is 7 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_8_CYCLES = 8U, /**< KPC debounce width is 8 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_9_CYCLES = 9U, /**< KPC debounce width is 9 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_10_CYCLES = 10U, /**< KPC debounce width is 10 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_11_CYCLES = 11U, /**< KPC debounce width is 11 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_12_CYCLES = 12U, /**< KPC debounce width is 12 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_13_CYCLES = 13U, /**< KPC debounce width is 13 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_14_CYCLES = 14U, /**< KPC debounce width is 14 Cycles of debounce clock */ + KPC_DEBOUNCE_WIDTH_15_CYCLES = 15U, /**< KPC debounce width is 15 Cycles of debounce clock */ +} KpcDebounceWidth_t; + +/** \brief List of key scan polarity */ +typedef enum +{ + KPC_SCAN_POLARITY_0 = 0U, /**< KPC outputs low level scan waveform for active row while other valid rows is high */ + KPC_SCAN_POLARITY_1 = 1U, /**< KPC outputs high level scan waveform for active row while other valid rows is low */ +} KpcScanPolarity_t; + +/** \brief List of key scan divider ratio */ +typedef enum +{ + KPC_SCAN_DIV_RATIO_2 = 1U, /**< KPC scan frequence divider ratio set as 2 */ + KPC_SCAN_DIV_RATIO_4 = 2U, /**< KPC scan frequence divider ratio set as 4 */ + KPC_SCAN_DIV_RATIO_8 = 3U, /**< KPC scan frequence divider ratio set as 8 */ + KPC_SCAN_DIV_RATIO_16 = 4U, /**< KPC scan frequence divider ratio set as 16 */ + KPC_SCAN_DIV_RATIO_32 = 5U, /**< KPC scan frequence divider ratio set as 32 */ + KPC_SCAN_DIV_RATIO_64 = 6U, /**< KPC scan frequence divider ratio set as 64 */ + KPC_SCAN_DIV_RATIO_128 = 7U, /**< KPC scan frequence divider ratio set as 128 */ +} KpcScanDivRatio_t; + +/** \brief List of debounce width */ +typedef enum +{ + KPC_ROW_0 = 1U, /**< KPC row0 enable mask */ + KPC_ROW_1 = 2U, /**< KPC row1 enable mask */ + KPC_ROW_2 = 4U, /**< KPC row2 enable mask */ + KPC_ROW_3 = 8U, /**< KPC row3 enable mask */ + KPC_ROW_4 = 16U, /**< KPC row4 enable mask */ + KPC_ROW_ALL = 0x1FU /**< KPC all rows enable mask */ +} KpcRow_t; + +/** \brief List of debounce width */ +typedef enum +{ + KPC_COLUMN_0 = 1U, /**< KPC column0 enable mask */ + KPC_COLUMN_1 = 2U, /**< KPC column1 enable mask */ + KPC_COLUMN_2 = 4U, /**< KPC column2 enable mask */ + KPC_COLUMN_3 = 8U, /**< KPC column3 enable mask */ + KPC_COLUMN_4 = 16U, /**< KPC column4 enable mask */ + KPC_COLUMN_ALL = 0x1FU /**< KPC all columns enable mask */ +} KpcColumn_t; + +/** \brief KPC debounce configuration, decounce exits when consecutive debounceWidth scans give the same result */ +typedef struct +{ + KpcDebounceClkDivRatio_t debounceClkDivRatio; /**< debounce clock divider ratio */ + KpcDebounceWidth_t debounceWidth; /**< debounce width */ +} KpcDebounceConfig_t; + +/** \brief KPC auto repeat configuration */ +typedef struct +{ + uint8_t enable; /**< enable auto repeat or not */ + uint8_t delay; /**< auto repeat delay cycles of scan period, if scan period is 50ms and this value is set as 10, + then autorepeat event will start to be reported 500ms later after key press is detected and key press keeps hold */ + + uint8_t period; /**< auto repeat report interval of scan period, if scan period is 50ms and this value is set as 2, + then autorepeat event will be reported in interval of 100ms until key is released */ +} KpcAutoRepeatConfig_t; + +/** \brief KPC configuration structure */ +typedef struct +{ + uint8_t validRowMask; /**< Bitmap of valid rows */ + uint8_t validColumnMask; /**< Bitmap of valid columns */ + KpcDebounceConfig_t debounceConfig; /**< KPC debounce configuration */ + KpcAutoRepeatConfig_t autoRepeat; /**< KPC auto repeat configuration */ + KpcScanPolarity_t scanPolarity; /**< KPC scan polarity */ + KpcScanDivRatio_t scanDivRatio; /**< KPC scan divider ratio */ +} KpcConfig_t; + +/** \brief List of kpc report key value */ +typedef enum +{ + KPC_REPORT_KEY_RELEASE = 0U, /**< Key is released */ + KPC_REPORT_KEY_PRESS = 1U, /**< Key is pressed */ + KPC_REPORT_KEY_REPEAT = 2U, /**< Key holds pressed */ +} KpcReportValue_t; + +typedef struct +{ + uint8_t value : 2; /**< Key value */ + uint8_t column : 3; /**< Key column */ + uint8_t row : 3; /**< Key row */ +} KpcReportEvent_t; + +/** + \brief Defines callback function prototype. + Callback function will be called in KPC interrupt service routine + \param report key event value + */ + +typedef void (*kpc_callback_t)(KpcReportEvent_t event); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \name KPC Configuration */ +/** \{ */ + +/** + \fn void KPC_getDefaultConfig(KpcConfig_t *config) + \brief Gets the KPC default configuartion. + This function sets the configuration structure to default values as below: + \code + config->debounceConfig.debounceClkDivRatio = KPC_DEBOUNCE_CLK_DIV_RATIO_16384; + config->debounceConfig.debounceWidth = KPC_DEBOUNCE_WIDTH_7_CYCLES; + + config->validRowMask = KPC_ROW_ALL; + config->validColumnMask = KPC_COLUMN_ALL; + + config->scanPolarity = KPC_SCAN_POLARITY_0; + config->scanDivRatio = KPC_SCAN_DIV_RATIO_16; + + config->autoRepeat.enable = 1; + config->autoRepeat.delay = 10; + config->autoRepeat.period = 1; + + \endcode + + \details debouncer and scan setting explaination: + KPC input clock is 26M, if debouncer divider is set as KPC_DEBOUNCE_CLK_DIV_RATIO_16384, then one cycle is 16384/26M = 630us, + debouncer depth set as 7, means we can filter out 630*7us(4.4ms) jitter + + scan clock is sourced from debouncer clock, which means if scan frequency divider ratio is set as KPC_SCAN_DIV_RATIO_16 and + when 5 rows are enabled, the scan frequency is 26M/16384/16/5 = 20HZ, each row scan signal width will be 1/20/5 = 10ms + + \param[in] config Pointer to KPC configuration structure + */ +void KPC_getDefaultConfig(KpcConfig_t *config); + +/** + \fn void KPC_init(const KpcConfig_t *config, kpc_callback_t callback) + \brief Initialize KPC + \param[in] config Pointer to KPC configuration + \param[in] callback Function to be called when KPC interrupt occurs + \return ARM_DRIVER_OK if the setting is successful + ARM_DRIVER_ERROR_PARAMETER on parameter check failure + */ +int32_t KPC_init(const KpcConfig_t *config, kpc_callback_t callback); + +/** + \fn void KPC_deInit(void) + \brief Deinitialize KPC + */ +void KPC_deInit(void); + +/** + \fn void KPC_startScan(void) + \brief Starts KPC scan + */ +void KPC_startScan(void); + +/** + \fn void KPC_stopScan(void) + \brief Stops KPC scan + */ +void KPC_stopScan(void); + + +/** \} */ + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _KPC_EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/oneWire.h b/PLAT/driver/chip/ec618/ap/inc/oneWire.h new file mode 100644 index 0000000..84e117d --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/oneWire.h @@ -0,0 +1,143 @@ +/**************************************************************************** + * + * Copy right: 2020-, Copyrigths of AirM2M Ltd. + * File name: oneWire.h + * Description: EC618 one wire bus driver file + * History: Rev1.0 2020-12-17 + * + ****************************************************************************/ + +#ifndef _ONEWIRE_EC618_H +#define _ONEWIRE_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup onewire_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief OW Mode Select */ +typedef enum +{ + STANDARD = 0, /**< Stand speed of onewire */ + OVERDRIVE /**< High speed of onewire */ +}OwModeSel_e; + +/** \brief OW Status */ +typedef enum +{ + OW_IDLE = 0x0, + OW_RESET_SUCCESS = 0x2, + OW_RESETPD_SUCCESS = 0x4, + OW_READ_SUCCESS = 0x8, + OW_WRITE_SUCCESS = 0x10, + OW_TIMEOUT = 0x20, +}OwStats_e; + +typedef struct +{ + uint8_t *dataWrite; + uint8_t *dataRead; + uint8_t mode; +}OwRes_t; + +#define OWDRV_OK (0) +#define OWDRV_RESET_ERR (-1) +#define OWDRV_RESETPD_ERR (-2) +#define OWDRV_READ_ERR (-3) +#define OWDRV_WRITE_ERR (-4) +#define OWDRV_TIMEOUT (-5) + + +/******************************************************************************* + * API + ******************************************************************************/ +#ifdef __cplusplus + extern "C" { +#endif + +/** + \fn void owInit() + \brief Initialize ow + */ +void owInit(void); + +/** + \fn void owDeInit() + \brief DeInitialize ow + */ +void owDeInit(void); + + +/** + \fn void owSetMode(OwModeSel_e mode) + \brief ow set mode + \param[in] mode ow mode + */ +void owSetMode(OwModeSel_e mode); + +/** + \fn int32_t owReset() + \brief ow reset + \return ow reset status + */ +int32_t owReset(void); + +/** + \fn int32_t owResetPd() + \brief ow reset for presence detect + \return ow reset presence detect status + */ +int32_t owResetPd(void); + +/** + \fn int32_t owWriteBit(uint8_t data) + \brief write 1bit data to ow + \param[in] data data to write to ow, LSB is effective + \return ow write 1 bit status + */ +int32_t owWriteBit(uint8_t data); + +/** + \fn int32_t owWriteByte(uint8_t data) + \brief write 1byte data to ow + \param[in] data 1 byte data to write to ow + \return ow write 1 byte status + */ +int32_t owWriteByte(uint8_t data); + +/** + \fn int32_t owReadBit() + \brief read 1bit data + \return ow read 1 bit status + */ +int32_t owReadBit(uint8_t * dataRead); + +/** + \fn int32_t owReadByte() + \brief ow read 1 byte + \return ow read 1 byte status + */ +int32_t owReadByte(uint8_t * dataRead); + +/** + \fn int32_t owTouchByte(uint8_t data) + \brief read and write ow at the same time + \return ow touch 1 byte status + */ +int32_t owTouchByte(uint8_t data); + +/** \} */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/PLAT/driver/chip/ec618/ap/inc/pad.h b/PLAT/driver/chip/ec618/ap/inc/pad.h new file mode 100644 index 0000000..97815bd --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/pad.h @@ -0,0 +1,173 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: pad.h + * Description: EC618 pad driver header file + * History: + * + ****************************************************************************/ + +#ifndef _PAD_EC618_H_ +#define _PAD_EC618_H_ + +#include "ec618.h" +#include "Driver_Common.h" + + +/** + \addtogroup pad_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief PAD pin mux selection */ +typedef enum +{ + PAD_MUX_ALT0 = 0U, /**< Chip-specific */ + PAD_MUX_ALT1 = 1U, /**< Chip-specific */ + PAD_MUX_ALT2 = 2U, /**< Chip-specific */ + PAD_MUX_ALT3 = 3U, /**< Chip-specific */ + PAD_MUX_ALT4 = 4U, /**< Chip-specific */ + PAD_MUX_ALT5 = 5U, /**< Chip-specific */ + PAD_MUX_ALT6 = 6U, /**< Chip-specific */ + PAD_MUX_ALT7 = 7U, /**< Chip-specific */ +} PadMux_e; + + +/** \brief Internal pull-up resistor configuration */ +typedef enum +{ + PAD_PULL_UP_DISABLE = 0U, /**< Internal pull-up resistor is disabled */ + PAD_PULL_UP_ENABLE = 1U, /**< Internal pull-up resistor is enabled */ +} PadPullUp_e; + +/** \brief Internal pull-down resistor configuration */ +typedef enum +{ + PAD_PULL_DOWN_DISABLE = 0U, /**< Internal pull-down resistor is disabled */ + PAD_PULL_DOWN_ENABLE = 1U, /**< Internal pull-down resistor is enabled */ +} PadPullDown_e; + +/** \brief Pull feature selection */ +typedef enum +{ + PAD_PULL_AUTO = 0U, /**< Pull up/down is controlled by muxed alt function */ + PAD_PULL_INTERNAL = 1U, /**< Use internal pull-up/down resistor */ +} PadPullSel_e; + +/** \brief Input buffer enable/disable */ +typedef enum +{ + PAD_INPUT_BUFFER_DISABLE = 0U, /**< Input Buffer is disabled */ + PAD_INPUT_BUFFER_ENABLE = 1U, /**< Input Buffer is enabled */ +} PadInputBuffer_e; + +/** \brief Configures pull feature */ +typedef enum +{ + PAD_INTERNAL_PULL_UP = 0U, /**< select internal pull up */ + PAD_INTERNAL_PULL_DOWN = 1U, /**< select internal pull down */ + PAD_AUTO_PULL = 2U, /**< Pull up/down is controlled by muxed alt function */ +} PadPullConfig_e; + +/** \brief PAD configuration structure */ +typedef struct +{ + uint32_t : 4; + uint32_t mux : 3; /**< Pad mux configuration */ + uint32_t : 1; + uint32_t pullUpEnable : 1; /**< Enable pull-up */ + uint32_t pullDownEnable : 1; /**< Enable pull-down */ + uint32_t pullSelect : 1; /**< Pull select, external or internal control */ + uint32_t : 2; + uint32_t inputBufferEnable : 1; /**< Enable/disable input buffer */ + uint32_t : 18; +} PadConfig_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \name PAD Driver Initialization */ +/** \{ */ + +/** + \fn void PAD_driverInit(void); + \brief Intialize PAD driver internal data, must be called before any other APIs + */ +void PAD_driverInit(void); + +/** + \fn void PAD_driverInit(void); + \brief De-Intialize PAD driver, disable PAD clock and perform some clearups + */ +void PAD_driverDeInit(void); + +/** \} */ + +/** \name Configuration */ +/* \{ */ + +/** + \fn void PAD_getDefaultConfig(PadConfig_t *config) + \brief Gets the PAD default configuartion + This function sets the configuration structure to default values as below: + \code + config->mux = PAD_MUX_ALT0; + config->inputBufferEnable = PAD_INPUT_BUFFER_DISABLE; + config->pullSelect = PAD_PULL_AUTO; + config->pullUpEnable = PAD_PULL_UP_DISABLE; + config->pullDownEnable = PAD_PULL_DOWN_DISABLE; + \endcode + \param config Pointer to PAD configuration structure + */ +void PAD_getDefaultConfig(PadConfig_t *config); + +/** + \fn void PAD_setPinConfig(uint32_t pin, const PadConfig_t *config) + \brief Sets the pad PCR register + \param pin PAD pin number + \param config Pointer to PAD configuration structure + */ +void PAD_setPinConfig(uint32_t paddr, const PadConfig_t *config); + +/** + \fn void PAD_setPinMux(uint32_t pin, PadMux_e mux) + \brief Configures pin mux + \param pin PAD pin number + \param mux pin signal source selection + */ +void PAD_setPinMux(uint32_t paddr, PadMux_e mux); + +/** + \fn void PAD_enablePinInputBuffer(uint32_t pin, bool enable) + \brief Enable/disable pin's input buffer + \param pin PAD pin number + \param enable true to enable, false to disable + */ +void PAD_enablePinInputBuffer(uint32_t paddr, bool enable); + +/** + \fn void PAD_setPinPullConfig(uint32_t pin, PadPullConfig_e config) + \brief Configures pin's pull feature + \param pin PAD pin number + \param config PAD pin pull configuration + */ +void PAD_setPinPullConfig(uint32_t paddr, PadPullConfig_e config); + +/** \} */ + +/** \}*/ + +#if defined(__cplusplus) +} +#endif + +#endif /* _PAD_EC618_H_ */ diff --git a/PLAT/driver/chip/ec618/ap/inc/pwrkey.h b/PLAT/driver/chip/ec618/ap/inc/pwrkey.h new file mode 100644 index 0000000..619280d --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/pwrkey.h @@ -0,0 +1,167 @@ + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: pwrkey.h +* +* Description: header of pwrkey.c, power on/off and software debounce +* +* History: 2021.04.29 initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ +#ifndef PWR_KEY_H +#define PWR_KEY_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +#define KEY_BUF_SIZE 8 + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ +typedef struct +{ + int16_t longPressTimeout; + int16_t repeatTimeout; + int16_t pwrOffTimeout; +}pwrKeyDly_t; + +typedef enum +{ + PWRKEY_PWRON_MODE = 0, + PWRKEY_WAKEUP_LOWACTIVE_MODE, + PWRKEY_WAKEUP_HIGHACTIVE_MODE, + PWRKEY_UNKNOW_MODE, +}pwrKeyWorkMode; + +/* +typedef enum +{ + PWRKEY_SYSTEM_ON = 0, + PWRKEY_SYSTEM_OFF, +}pwrKeySysStatus; +*/ + +typedef enum +{ + PWRKEY_RELEASE = 0, + PWRKEY_PRESS, + PWRKEY_LONGPRESS, + PWRKEY_REPEAT, +}pwrKeyPressStatus; + +typedef struct +{ + bool negEdgeEn; + bool posEdgeEn; +}pwrKeyWakeupCfg_t; + + +typedef void(* pwrKeyCallback_t)(pwrKeyPressStatus status); + +typedef struct +{ + pwrKeyWorkMode workMode; + pwrKeyWakeupCfg_t wakeupCfg; + pwrKeyDly_t delayCfg; + pwrKeyCallback_t pwrKeyCallback; + pwrKeyPressStatus curStatus; + pwrKeyPressStatus keyBuf[KEY_BUF_SIZE]; + uint8_t bufOffset; +}pwrKeyInfo_t; + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** +* @brief pwrKeyPushKey +* @details push a key to power key buffer +* +* @param pwrKeyInfo + @param status + +* @return null +*/ +void pwrKeyPushKey(pwrKeyInfo_t *pwrKeyInfo, pwrKeyPressStatus status); +/** +* @brief pwrKeyPopKey +* @details pop a key from power key buffer and return the key status +* +* @param pwrKeyInfo +* @return null +*/ +pwrKeyPressStatus pwrKeyPopKey(pwrKeyInfo_t *pwrKeyInfo); +/** +* @brief pwrKeyStartPowerOff +* @details force to enter power off status +* +* @return null +*/ +void pwrKeyStartPowerOff(void); +/** +* @brief pwrkeyPwrOnDebounce +* @details power on debounce flow according to the configures +* +* @param tmpDelay in ms +* @return null +*/ +void pwrkeyPwrOnDebounce(int16_t tmpDelay); +/** +* @brief pwrKeyHwInit +* @details power key hardware init +* +* @param pullUpEn +* @return null +*/ +void pwrKeyHwInit(bool pullUpEn); +/** +* @brief pwrKeyHwDeinit +* @details power key hardware deinit +* +* @param pullUpEn +* @return null +*/ +void pwrKeyHwDeinit(bool pullUpEn); +/** +* @brief pwrKeyGetPinLevel +* @details get power key pin value +* +* @return null +*/ +bool pwrKeyGetPinLevel(void); +/** +* @brief pwrKeyGetPwrKeyMode +* @details get power key mode in bootloader +* +* @return null +*/ +pwrKeyWorkMode pwrKeyGetPwrKeyMode(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/PLAT/driver/chip/ec618/ap/inc/rng.h b/PLAT/driver/chip/ec618/ap/inc/rng.h new file mode 100644 index 0000000..c08b7ec --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/rng.h @@ -0,0 +1,87 @@ +#ifndef __RNG_EC618_H__ +#define __RNG_EC618_H__ + +#include "ec618.h" +#include "Driver_Common.h" +#include "clock.h" +#include "ic.h" +#include "string.h" + +#define RNG_DEBUG_USING_PRINTF 0 +#define RNG_DEBUG_USING_UNILOG 0 + +#define RNG_IRQ_MODE 0 + +#define RNG_MAX_POLL_DELAY_US (8000*2) +#define RNG_MAX_TRY_NUM 10 +#define RNG ((RngDesc_t*)MP_TRNG_BASE_ADDR) +#define RNG_R_MAGIC 0xf45a97d4 + + + +#if (RNG_DEBUG_USING_UNILOG == 1) +#include DEBUG_LOG_HEADER_FILE +#endif + +#ifdef PM_FEATURE_ENABLE +#include "slpman.h" +#endif + + +#if RNG_DEBUG_USING_PRINTF +#define RNGDEBUG(...) printf(__VA_ARGS__) +#else +#define RNGDEBUG(...) +#endif + + + +typedef struct +{ + __IM uint32_t rsvd1[64]; + __IO uint32_t imrReg; //Interrupt mask reg ,0x100 + __IO uint32_t isrReg; //Interrupt status reg + __OM uint32_t icrReg; //Interrupt clear reg + __IO uint32_t cfgReg; //Configuration reg + __IM uint32_t validReg; //Valid reg + __IM uint32_t dataReg[6]; + __IO uint32_t srcEnableReg; //Random source enable reg + __IO uint32_t sampleCntReg; //Sample Count reg + __IO uint32_t autoCorrReg; //Auto correlation reg + __IM uint32_t debugCtrlReg; //Debug Control reg + __IM uint32_t rsvd2; + __OM uint32_t swRstReg; //Reset reg + __IM uint32_t rsvd3[29]; + __IM uint32_t busyReg; //Busy reg + __OM uint32_t rstBitsCntReg; //Reset bits counter reg + __IM uint32_t rsvd4[8]; + __IM uint32_t bistCntReg[3]; //BIST Counter reg + __IO uint32_t rsvd5[5]; +}RngDesc_t; + +typedef enum +{ + RNG_SRC_SHORT_TEST_TYPE = 0, + RNG_SRC_SHORT_TYPE = 1, + RNG_SRC_LONG_TYPE = 2, + RNG_SRC_LONGEST_TYPE = 3, +}RngSrcSelType_e; + +#define RNGDRV_OK (0) +#define RNGDRV_IntErr (-1) +#define RNGDRV_TimeOutErr (-2) + +typedef enum{ + RNG_EHR_VALID_TYPE = 1, + RNG_AUTO_CORR_ERR_TYPE = 2, + RNG_CRNGT_ERR_TYPE = 4, + RNG_VN_ERR_TYPE = 8 +}RngIntStatType_e; + +/** + \brief When rand is null, means generate random number to efuse. If rand isn't null, means generate to this parameter. + \param[out] rand Memory address to receive generated random number. + \return status +*/ +int32_t rngGenRandom(uint8_t rand[24]); +#endif diff --git a/PLAT/driver/chip/ec618/ap/inc/sctreg.h b/PLAT/driver/chip/ec618/ap/inc/sctreg.h new file mode 100644 index 0000000..c404e5e --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/sctreg.h @@ -0,0 +1,543 @@ +#ifndef __SCT_REG_H__ +#define __SCT_REG_H__ + +/****************************************************************************** + ****************************************************************************** + Copy right: 2017-, Copyrigths of AirM2M Ltd. + File name: sctreg.h + Description: SCT register, Security Top is a HW use to do: + * 1) cipher & integrity check + * 2) AES/SHA + * 3) PPP escape & CRC + * 4) USB TX + History: 2020/12/04 Originated by Jason + ****************************************************************************** +******************************************************************************/ +#include "ec618.h" + +#if defined(__CC_ARM) +#pragma anon_unions +#endif + +/****************************************************************************** + ****************************************************************************** + * SCT control registers + ****************************************************************************** +******************************************************************************/ + +/* + * Cipher 0x4005-0000~0x4005-FFFF (64KB) +*/ +#define SCT_REG_ADDR 0x40050000 + + +/****************************************************************************** + * SCT enable/disable register +******************************************************************************/ + +#define SCT_EN_CTRL_REG ((__IO UINT32 *)SCT_REG_ADDR) + + +/* + * __IO UINT32 SCTEN; + * Bit WIDTH DESP + * 0 1 0 - SCT disable (reset value) + * 1- SCT enable + * 1:31 31 RSVD +*/ +#define ENABLE_SCT() ((*(SCT_EN_CTRL_REG)) = 1) +#define DISABLE_SCT() ((*(SCT_EN_CTRL_REG)) = 0) + + +/****************************************************************************** + ****************************************************************************** + * SCT RNDIS/PPP config register + ****************************************************************************** +******************************************************************************/ + +/* + * SctRndisCrcCfgReg RNDIS_CRC_CFG + * Bit WIDTH DESP + * 0 1 rndis_crc_in_bit_swap, + * 0 - CRC calc from bit: inByte[0] + * 1 - CRC calc from bit: inByte[7] (reset value) + * 1 1 rndis_crc_comple_out + * 0 - CRC out bit not comple + * 1 - CRC out bit comple (reset value) + * 2 1 rndis_crc_out_bit_swap + * 0 - CRC out bit not swap + * 1 - CRC out bit swap (reset value) + * 3:6 4 rndis_crc_comple_in_num, how many input bytes need to be compled + * +*/ +typedef union +{ + struct { + UINT32 crcInBitSwap : 1; + UINT32 crcCompleOut : 1; + UINT32 crcOutBitSwap : 1; + UINT32 crcCompleInNum : 4; + UINT32 : 25; + }; + + UINT32 value32; +}SctRndisCrcCfgReg; + + +/* + * SctPPPCrcInitReg PPP_CRC_INIT + * Bit WIDTH DESP + * 0:15 16 PPP CRC init value, reset value: 0xFFFF +*/ +typedef union +{ + struct { + UINT32 crcInitValue : 16; + UINT32 : 16; + }; + + UINT32 value32; +}SctPPPCrcInitReg; + + +/* + * SctPPPCrcCfgReg PPP_CRC_CFG + * Bit WIDTH DESP + * 0 1 ppp_crc_in_bit_swap + * 0 - CRC calc from bit: inByte[0], (reset value) + * 1 - CRC calc from bit: inByte[7] + * 1 1 ppp_crc_comple_out + * 0 - CRC out bit not comple + * 1 - CRC out bit comple, (reset value) + * 2 1 ppp_crc_out_bit_swap + * 0 - CRC out bit not swap + * 1 - CRC out bit swap (reset value) + * +*/ +typedef union +{ + struct { + UINT32 crcInBitSwap : 1; + UINT32 crcCompleOut : 1; + UINT32 crcOutBitSwap : 1; + UINT32 : 29; + }; + + UINT32 value32; +}SctPPPCrcCfgReg; + +/* + * PPP escape/deescape bitmap table +*/ +#define SCT_PPP_ESCP_BITMAP_WORD_NUM 8 +#define SCT_PPP_DE_ESCP_BITMAP_WORD_NUM 8 + + +/* + * SCT RNDIS PPP config register struct +*/ +typedef struct SctRndisPPPCfgReg_Tag +{ + __IO UINT32 RNDIS_CRC_INIT; /* RNDIS (802.3) CRC init value, reset value: 0, offset: 0x04 */ + __IO SctRndisCrcCfgReg RNDIS_CRC_CFG; /* RNDIS (802.3) CRC config. offset: 0x08 */ + __IO SctPPPCrcInitReg PPP_CRC_INIT; /* PPP CRC init value, reset value: 0xFFFF, offset: 0x0C */ + __IO SctPPPCrcCfgReg PPP_CRC_CFG; /* PPP CRC config, offset: 0x10 */ + + __IO UINT32 PPP_ESCP_BITMAP[SCT_PPP_ESCP_BITMAP_WORD_NUM]; /* PPP escape bitmap, offset: 0x14 */ + __IO UINT32 PPP_DE_ESCP_BITMAP[SCT_PPP_DE_ESCP_BITMAP_WORD_NUM];/* PPP de-escape bitmap, offset: 0x34 */ +}SctRndisPPPCfgReg; + +/* + * SCT RNDIS PPP config register start address +*/ +#define SCT_RNDIS_PPP_CTRL_REG_ADDR (SCT_REG_ADDR + 0x04) + +/* + * SCT RNDIS PPP register pointer +*/ +#define SCT_RNDIS_PPP_CFG_REG ((SctRndisPPPCfgReg *)SCT_RNDIS_PPP_CTRL_REG_ADDR) + + + +/****************************************************************************** + ****************************************************************************** + * SCT (cipher/integrity) common config register + ****************************************************************************** +******************************************************************************/ + +/* + * SctCommCfgWord0 COMM_CFG0 + * Bit WIDTH DESP + * 0 1 sct_cfg_acg_en_rmi_acg + * 0 - not enable auto gate, (reset value) + * 1 - enable auto gate + * 1 1 sct_cfg_acg_en_ahb_acg + * 0 - not enable auto gate, (reset value) + * 1 - enable auto gate + * 16 1 sct_cfg_unilog_SCT_ChainStart + * 0 - no unilog output, (reset value) + * 1 - unilog output + * 17 1 sct_cfg_unilog_SCT_Descriptor_done + * 0 - no unilog output, (reset value) + * 1 - unilog output + * 18 1 sct_cfg_unilog_SCT_ChainEnd + * 0 - no unilog output, (reset value) + * 1 - unilog output + * 19 1 sct_cfg_unilog_error_int + * 0 - no unilog output, (reset value) + * 1 - unilog output + * 20 1 sct_usb_lb_ind, USB Tx big/Little endian output + * 0 - little endian, (reset value) + * 1 - big endian + * 24:31 8 sct_cfg_high_addr_offst + * +*/ +typedef union +{ + struct { + UINT32 rmiAcg : 1; + UINT32 ahbAcg : 1; + UINT32 : 14; + UINT32 chainStartUnilog : 1; + UINT32 descDoneUnilog : 1; + UINT32 chainEndUnilog : 1; + UINT32 errorIntUnilog : 1; + UINT32 usbLBEndianInd : 1; + UINT32 : 3; + UINT32 memHighAddrOffset : 8; + }; + + UINT32 value32; +}SctCommCfgWord0; + + +/* + * SctCommCfgWord1 COMM_CFG1 + * Bit WIDTH DESP + * 0:19 20 sct_cfg_d_max_time, (reset value: 0) + * descriptor max process time, in unit of 32K ticks, if timeout, tigger interrupt: sct_dscrpt_time_out + * +*/ +typedef union +{ + struct { + UINT32 descMaxProcTickTime : 20; + UINT32 : 12; + }; + + UINT32 value32; +}SctCommCfgWord1; + + +/* + * SCT common config register struct +*/ +typedef struct SctCommCfgReg_Tag +{ + __IO SctCommCfgWord0 COMM_CFG0; /* SCT common CFG0, offset: 0x54 */ + __IO SctCommCfgWord1 COMM_CFG1; /* SCT common CFG1, offset: 0x58 */ +}SctCommCfgReg; + +/* + * SCT common control register start address +*/ +#define SCT_COMM_CFG_REG_ADDR (SCT_REG_ADDR + 0x54) + +/* + * SCT RNDIS PPP register pointer +*/ +#define SCT_COMM_CFG_REG ((SctCommCfgReg *)SCT_COMM_CFG_REG_ADDR) + + +/****************************************************************************** + ****************************************************************************** + * SCT (cipher/integrity) channel config register + ****************************************************************************** +******************************************************************************/ + +/* + * + * Bit WIDTH DESP + * 0:7 8 sct_fifo_len_ch0 + * Chain FIFO length, MAX set to 255, (reset value: 0) + * 8 1 sct_chain_int_en_ch0, (reset value: 0) + * Generate interrupt when each chain in this channel is finished + * 9 1 sct_fifo_empty_int_en_ch0, (reset value: 0) + * FIFO empty interrupt enable, Generate interrupt when chain FIFO is empty (all done) + * 10 1 sct_fifo_full_int_en_ch0, (reset value: 0) + * FIFI full interrupt enable, Generate interrupt when chain FIFO is full (>sct_fifo_len_ch0) + * 11 1 sct_ck_bl_ch0, input CK is big/little endian + * 0 - little endian, (reset value: 0) + * 1 - big endian + * 12 1 sct_aes_iv_bl_ch0, input AES IV is big/little endian + * 0 - little endian, (reset value: 0) + * 1 - big endian + * 13 1 sct_ck_opt_dis_ch0, whether disable CK optimization, whether need to re-load CK from SRAM, when process descriptors in the same chain + * 0 - enable CK opt, (reset value: 0) + * 1 - disable CK opt + * 16:17 1 comm_crc_poly_len_ch0, common CRC poly length + * 0 ¨C 8 bits CRC, (reset value: 0) + * 1 ¨C 16 bits CRC + * 2 ¨C 24 bits CRC + * 3 ¨C 32 bits CRC + * 19 1 comm_crc_comple_out_ch0 + * 0 - CRC output not need to comple, (reset value: 0) + * 1 - CRC output need to comple + * 20:23 4 comm_crc_comple_in_num_ch0, how many input bytes need to comple, before start CRC, + * 24 1 comm_crc_out_bit_swap_ch0 + * 0 ¨C crcbyte from s[x] to s[x+7], s[x+7] is placed in LSB, (reset value: 0) + * 1 ¨C crcbyte from s[x+7] to s[x], s[x+7] is placed in MSB + * 25 1 comm_crc_in_bit_swap_ch0 + * 0 ¨C CRC start from bit[0] of input byte, (reset value: 0) + * 1 ¨C CRC start from bit[7] of input byte + * +*/ +typedef union +{ + struct { + UINT32 fifoLen : 8; + UINT32 chainIntEn : 1; + UINT32 chainEmptyIntEn : 1; + UINT32 chainFullIntEn : 1; + UINT32 ckBLEndian : 1; + UINT32 aesIvBLEndian : 1; /* bit: 12 */ + UINT32 ckOptDis : 1; /* bit: 13 */ + UINT32 : 2; + UINT32 crcPolyLen : 2; /* bit: 16:17 */ + UINT32 : 1; + UINT32 crcOutComple : 1; /* bit: 19 */ + UINT32 crcInCompleByteNum : 4; /* bit: 20:23 */ + UINT32 crcOutBitSwap : 1; /* bit: 24 */ + UINT32 crcInBitSwap : 1; /* bit: 25 */ + UINT32 : 6; + }; + + UINT32 value32; +}SctChCfgWord0; + +/* + * UINT32 CHA_BASE_ADDR + * Chain Base Address. Chain FIFO start address, should be 4 bytes aligned, and with length: 4*CHAINFIFOLEN +*/ + +/* + * UINT32 CK_BASE_ADDR, EEA/EIA CK Base Address + * 1. Should be 4 bytes aligned + * 2. one CK/IK 16 bytes + * 3. Total 8 CK/IK keys, so total byte length: 8*16 = 128 +*/ + +/* + * SctChCtrlReg CH_CTRL //write only + * Bit WIDTH DESP + * 0 1 sct_chain_trigger_ch0 + * Set 1, Chain trigger, a chain already insert into the chain list, and trigger SCT to process + * 1 1 sct_channel_reset_ch0 + * Set 1, to reset current channel + * +*/ +typedef union +{ + struct { + UINT32 chainTrg : 1; + UINT32 chnReset : 1; + UINT32 : 30; + }; + + UINT32 value32; +}SctChCtrlReg; + +/* + * SCT channel config register struct +*/ +typedef struct SctChannelCfgReg_Tag +{ + __IO SctChCfgWord0 CH_CFG0; /* SCT channel CFG0, offset: 0x5C */ + __IO UINT32 CHA_BASE_ADDR; /* SCT channel chain base address, offset: 0x60 */ + __IO UINT32 CK_BASE_ADDR; /* SCT channel CK/IK base address, offset: 0x64 */ + __IO UINT32 CRC_POLY; /* SCT channel common CRC poly, offset: 0x68 */ + __IO UINT32 CRC_INIT; /* SCT channel common CRC init value, offset: 0x6C */ + __O SctChCtrlReg CH_CTRL; /* SCT channel control register, write only, offset: 0x70 */ +}SctChannelCfgReg; + +/* + * SCT totoal channel number: 6 +*/ +#define SCT_CHANNEL_NUM 6 + +/* + * SCT channels config register struct +*/ +typedef struct SctCHSCfgReg_Tag +{ + SctChannelCfgReg chCfg[SCT_CHANNEL_NUM]; +}SctCHSCfgReg; + + +/* + * SCT channels config register start address +*/ +#define SCT_CHANNEL_CFG_REG_ADDR (SCT_REG_ADDR + 0x5C) + + +/* + * SCT channels config register pointer +*/ +#define SCT_CHANNELS_CFG_REG ((SctCHSCfgReg *)SCT_CHANNEL_CFG_REG_ADDR) + + +/****************************************************************************** + ****************************************************************************** + * SCT memory guard register + ****************************************************************************** +******************************************************************************/ + +typedef struct +{ + __IO UINT32 hAddr0; /*sct_mpr_addr_h0, offset: 0xEC */ + __IO UINT32 lAddr0; /*sct_mpr_addr_l0, offset: 0xF0 */ + __IO UINT32 hAddr1; /*sct_mpr_addr_h1, offset: 0xF4 */ + __IO UINT32 lAddr1; /*sct_mpr_addr_l1, offset: 0xF8 */ + __IO UINT32 hAddr2; /*sct_mpr_addr_h2, offset: 0xFC */ + __IO UINT32 lAddr2; /*sct_mpr_addr_l2, offset: 0x100 */ + __IO UINT32 hAddr3; /*sct_mpr_addr_h3, offset: 0x104 */ + __IO UINT32 lAddr3; /*sct_mpr_addr_l3, offset: 0x108 */ +}SctMemGuardReg; + +/* + * SCT memory guard register start address +*/ +#define SCT_MEM_GUARD_REG_ADDR (SCT_REG_ADDR + 0xEC) + +/* + * SCT memory guard register pointer +*/ +#define SCT_MEM_GUARD_CFG_REG ((SctMemGuardReg *)SCT_MEM_GUARD_REG_ADDR) + + + +/****************************************************************************** + ****************************************************************************** + * SCT channel state register + ****************************************************************************** +******************************************************************************/ + +/* + * SCT channel state register + * Bit WIDTH DESP + * 0:7 8 sct_cfg_fifo_idx_ch0, Channel next configure index + * a) reset/init value: 0 + * b) increase 1, when chain triggered. + * c) Range: [0: fifoLen-1] + * 8:15 8 sct_done_fifo_idx_ch0, Channel next done index + * a) reset/init value: 0 + * b) increase 1, when one chain process done. + * c) Range: [0: fifoLen-1] + * 16:23 8 sct_free_fifo_space_ch0 + * Channel FIFO free space + * 24 1 sct_fifo_full_ch0 + * Whether chain full (overflow), 0 - not, 1 - full + * 25 1 sct_fifo_empty_ch0 + * Whether chain empty (all done), 0 - not, 1 - empty + * 26 1 sct_dscrpt_act_ch0 + * Whether channel is activate, if descriptor in current channel is ongoing, then set 1, so only one channel could be set to 1 + * 27 1 sct_rst_done_ch0, Whether channel reset done. + * a) SW: "SctChCtrlReg->chnReset" set 1, tigger SCT reset current channel + * b) HW: SCT should stop current descriptor, and ignore all the pending chain request + * c) HW: After reset done, SCT set this flag, and trigger ISR + * d) SW: when process this ISR, if need to write USB EP in this channel, need to reflush/reset USB + * e) HW: When this channel config/trigger again (SctChCtrlReg->chainTrg = 1), SCT clear this flag + * 28 1 sct_dscrpt_time_out_ch0, whether SCT process this descriptor time out + * a) HW: SCT start a guard timer, when start processing a descriptor, and stop it when done + * b) HW: When timeout, SCT set this flag, and trigger ISR + * c) HW: when SW reset current channel (SctChCtrlReg->chnReset = 1), SCT clear this flag + * + * +*/ +typedef union +{ + struct { + UINT32 chaNextCfgIdx : 8; + UINT32 chaNextDoneIdx : 8; + UINT32 chnFreeLen : 8; + UINT32 chnBeFull : 1; + UINT32 chnBeEmpty : 1; + UINT32 chnBeAct : 1; + UINT32 chnBeRstDone : 1; + UINT32 descBeTimeOut : 1; + + UINT32 : 3; + }; + + UINT32 value32; +}SctChannelStateReg; + +/* + * SCT channels state registers +*/ +typedef struct +{ + __I SctChannelStateReg chState[SCT_CHANNEL_NUM]; /* SCT channel state, read only, offset: 0x120 */ +}SctCHSStateReg; + +/* + * SCT channels state register start address +*/ +#define SCT_CHS_STATE_REG_ADDR (SCT_REG_ADDR + 0x120) + +/* + * SCT channels state register pointer +*/ +#define SCT_CHS_STATE_REG ((SctCHSStateReg *)SCT_CHS_STATE_REG_ADDR) + + + +/****************************************************************************** + ****************************************************************************** + * SCT error status register + ****************************************************************************** +******************************************************************************/ + +/* + * SctErrStatusWord0 errStatus + * Bit WIDTH DESP + * 0:5 6 master error (AHB error) + * 6:11 6 memory guard error + * 12:17 6 descriptor info error (PPP/CRC not byte aligned) + * +*/ +typedef union +{ + struct { + UINT32 masterErr : 6; + UINT32 mgrErr : 6; + UINT32 descErr : 6; + UINT32 : 14; + }; + + UINT32 value32; +}SctErrStatusWord0; + + +/* + * SCT error status register struct +*/ +typedef struct +{ + __I SctErrStatusWord0 errStatus; /* sct_err_status, read only, offset: 0x138 */ + __I UINT32 rdErrMem; /* sct_err_mpr_rd, SCT read error address, offset: 0x13C */ + __I UINT32 wtErrMem; /* sct_err_mpr_wt, SCT write error address, offset: 0x140 */ +}SctErrStatusReg; + +/* + * SCT error status register start address +*/ +#define SCT_ERR_STATUS_REG_ADDR (SCT_REG_ADDR + 0x138) + +/* + * SCT error status register pointer +*/ +#define SCT_ERR_STATUS_REG ((SctErrStatusReg *)SCT_ERR_STATUS_REG_ADDR) + +#endif + diff --git a/PLAT/driver/chip/ec618/ap/inc/timer.h b/PLAT/driver/chip/ec618/ap/inc/timer.h new file mode 100644 index 0000000..6708126 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/timer.h @@ -0,0 +1,282 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: timer.h + * Description: EC618 timer driver header file + * History: + * + ****************************************************************************/ + +#ifndef _TIMER_EC618_H +#define _TIMER_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup timer_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief List of TIMER clock source */ +typedef enum +{ + TIMER_INTERNAL_CLOCK = 0U, /**< Internal clock */ + TIMER_EXTERNAL_CLOCK = 1U, /**< External clock */ +} TimerClockSource_t; + +/** \brief List of TIMER match value select */ +typedef enum +{ + TIMER_MATCH0_SELECT = 0U, /**< Select Match0 */ + TIMER_MATCH1_SELECT = 1U, /**< Select Match1 */ + TIMER_MATCH2_SELECT = 2U, /**< Select Match2 */ +} TimerMatchSelect_t; + +/** \brief List of TIMER reload option, counter will be reloaded to init value upon reach it */ +typedef enum +{ + TIMER_RELOAD_DISABLE = 0U, /**< Counter will run freely */ + TIMER_RELOAD_ON_MATCH0 = 1U, /**< Counter will be reloaded on reaching match0 value */ + TIMER_RELOAD_ON_MATCH1 = 2U, /**< Counter will be reloaded on reaching match1 value */ + TIMER_RELOAD_ON_MATCH2 = 3U, /**< Counter will be reloaded on reaching match1 value */ +} TimerReloadOption_t; + +/** \brief PWM configuration structure */ +typedef struct +{ + uint32_t pwmFreq_HZ; /**< PWM signal frequency in HZ */ + uint32_t srcClock_HZ; /**< TIMER counter clock in HZ */ + uint32_t dutyCyclePercent; /**< PWM pulse width, the valid range is 0 to 100 */ +} TimerPwmConfig_t; + +/** \brief TIMER configuration structure */ +typedef struct +{ + TimerClockSource_t clockSource; /**< Clock source */ + TimerReloadOption_t reloadOption; /**< Reload option */ + uint32_t initValue; /**< Counter init value */ + uint32_t match0; /**< Match0 value */ + uint32_t match1; /**< Match1 value */ + uint32_t match2; /**< Match2 value */ +} TimerConfig_t; + +/** \brief TIMER interrupt configuration */ +typedef enum +{ + TIMER_INTERRUPT_DISABLED = 0U, /**< Disable interrupt */ + TIMER_INTERRUPT_LEVEL = 1U, /**< Level interrupt, a high level interrupt signal is generated */ + TIMER_INTERRUPT_PULSE = 2U, /**< Pulse interrupt, a pulse of one clock width + is generated after counter matches */ +} TimerInterruptConfig_t; + + +/** \brief List of TIMER interrupts */ +typedef enum +{ + TIMER_MATCH0_INTERRUPT_ENABLE = TIMER_TCTLR_IE_0_Msk, /**< Match0 interrupt */ + TIMER_MATCH1_INTERRUPT_ENABLE = TIMER_TCTLR_IE_1_Msk, /**< Match1 interrupt */ + TIMER_MATCH2_INTERRUPT_ENABLE = TIMER_TCTLR_IE_2_Msk, /**< Match2 interrupt */ +} TimerInterruptEnable_t; + +/** \brief List of TIMER interrupt flags */ +typedef enum +{ + TIMER_MATCH0_INTERRUPT_FLAG = TIMER_TSR_ICLR_0_Msk, /**< Match0 interrupt flag */ + TIMER_MATCH1_INTERRUPT_FLAG = TIMER_TSR_ICLR_1_Msk, /**< Match1 interrupt flag */ + TIMER_MATCH2_INTERRUPT_FLAG = TIMER_TSR_ICLR_2_Msk, /**< Match2 interrupt flag */ +} TimerInterruptFlags_t; + + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \name TIMER Driver Initialization */ +/** \{ */ + +/** + \fn void TIMER_driverInit(void); + \brief Intialize TIMER driver internal data, must be called before any other APIs + */ +void TIMER_driverInit(void); + +/** \} */ + +/** \name TIMER Configuration */ +/** \{ */ + +/** + \fn void TIMER_getDefaultConfig(TimerConfig_t *config) + \brief Gets the TIMER default configuartion. + This function sets the configuration structure to default values as below: + \code + config->clockSource = TIMER_INTERNAL_CLOCK; + config->reloadOption = TIMER_RELOAD_ON_MATCH1; + config->initValue = 0; + config->match0 = 0x10000 >> 1; + config->match1 = 0x10000; + config->match2 = 0xFFFFFFFF; + \endcode + + \param[in] config Pointer to TIMER configuration structure + */ +void TIMER_getDefaultConfig(TimerConfig_t *config); + +/** + \fn void TIMER_init(uint32_t instance, const TimerConfig_t *config) + \brief Intialize TIMER + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] config Pointer to TIMER configuration + \note PWM out is disabled after this function's call, use \ref TIMER_setupPwm function to eable PWM + */ +void TIMER_init(uint32_t instance, const TimerConfig_t *config); + +/** + \fn void TIMER_deInit(uint32_t instance) + \brief Deintialize TIMER + \param[in] instance TIMER instance number (0, 1, ...) + */ +void TIMER_deInit(uint32_t instance); + +/** + \fn void TIMER_setMatch(uint32_t instance, TimerMatchSelect_t match) + \brief Sets one of TIMER match values + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] matchNum TIMER match select + \param[in] matchValue TIMER match value + */ +void TIMER_setMatch(uint32_t instance, TimerMatchSelect_t matchNum, uint32_t matchValue); + +/** + \fn void TIMER_setMatch(uint32_t instance, TimerMatchSelect_t match) + \brief Sets TIMER counter initial value + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] initValue TIMER initial value + */ +void TIMER_setInitValue(uint32_t instance, uint32_t initValue); + +/** + \fn void TIMER_setMatch(uint32_t instance, TimerMatchSelect_t match) + \brief Sets TIMER counter reload option + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] option TIMER counter reload option + */ +void TIMER_setReloadOption(uint32_t instance, TimerReloadOption_t option); + +/** \} */ + +/** \name TIMER Counter */ +/** \{ */ + +/** + \fn void TIMER_start(uint32_t instance) + \brief Starts TIMER counter + \param[in] instance TIMER instance number (0, 1, ...) + */ +void TIMER_start(uint32_t instance); + +/** + \fn void TIMER_stop(uint32_t instance) + \brief Stops TIMER counter + \param[in] instance TIMER instance number (0, 1, ...) + */ +void TIMER_stop(uint32_t instance); + +/** + \fn uint32_t TIMER_getCount(uint32_t instance) + \brief Reads current TIMER counter value + \param[in] instance TIMER instance number (0, 1, ...) + \return current TIMER counter value + */ +uint32_t TIMER_getCount(uint32_t instance); + +/** \} */ + +/** \name TIMER PWM */ +/** \{ */ + +/** + \fn int32_t TIMER_setupPwm(uint32_t instance, const TimerPwmConfig_t *config) + \brief Configures the PWM signals period, mode, etc. + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] config Pointer to PWM parameter + \return ARM_DRIVER_OK if the PWM setup is successful + ARM_DRIVER_ERROR_PARAMETER on parameter check failure + */ +int32_t TIMER_setupPwm(uint32_t instance, const TimerPwmConfig_t *config); + +/** + \fn void TIMER_updatePwmDutyCycle(uint32_t instance, uint32_t dutyCyclePercent) + \brief Updates the duty cycle of PWM signal + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] dutyCyclePercent New PWM pulse width, value shall be between 0 to 100, + if the value exceeds 100, dutyCyclePercent is set to 100. + */ +void TIMER_updatePwmDutyCycle(uint32_t instance, uint32_t dutyCyclePercent); + +/** \} */ + +/** \name TIMER Interrupt */ +/** \{ */ + +/** + \fn void TIMER_interruptConfig(uint32_t instance, TimerMatchSelect_t match, TimerInterruptConfig_t config) + \brief Configures the selected TIMER interrupt + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] match TIMER match select + \param[in] config TIMER interrupt configuration + */ +void TIMER_interruptConfig(uint32_t instance, TimerMatchSelect_t match, TimerInterruptConfig_t config); + +/** + \fn TimerInterruptConfig_t TIMER_getInterruptConfig(uint32_t instance, TimerMatchSelect_t match) + \brief Gets current configuration of the selected TIMER interrupt + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] match TIMER match select + \return Current TIMER interrupt configuration + */ +TimerInterruptConfig_t TIMER_getInterruptConfig(uint32_t instance, TimerMatchSelect_t match); + +/** + \fn uint32_t TIMER_getInterruptFlags(uint32_t instance) + \brief Reads TIMER interrupt status flags + \param[in] instance TIMER instance number (0, 1, ...) + \return Interrupt flags. This is the logical OR of members of the + enumeration \ref TimerInterruptFlags_t + */ +uint32_t TIMER_getInterruptFlags(uint32_t instance); + +/** + \fn void TIMER_clearInterruptFlags(uint32_t instance, uint32_t mask) + \brief Clears TIMER interrupt flags + \param[in] instance TIMER instance number (0, 1, ...) + \param[in] mask Interrupt flags to clear. This is a logic OR of members of the + enumeration \ref TimerInterruptFlags_t + */ +void TIMER_clearInterruptFlags(uint32_t instance, uint32_t mask); + +/** + \fn void TIMER_netlightEnable(uint32_t instance) + \brief Set Netlight Enable, called by user in bsp_custom.c to define specific timer instance for netlight + \param[in] instance TIMER instance number (0, 1, ...) + */ +void TIMER_netlightEnable(uint8_t instance); + +/** \} */ + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TIMER_EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/tls.h b/PLAT/driver/chip/ec618/ap/inc/tls.h new file mode 100644 index 0000000..18213b0 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/tls.h @@ -0,0 +1,252 @@ +#ifndef __TLS_H__ +#define __TLS_H__ + +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + +#define SCT_BASE_ADDR (0x40050000) + +#define AES_SHA_CH4_CFG_REG (SCT_BASE_ADDR + 0xbc) // AES/SHA uses sct channel4 +#define AES_SHA_CH4_STATE_REG (SCT_BASE_ADDR + 0x130) + +#define SCT_ENABLE_REG (SCT_BASE_ADDR + 0x00) +#define SCT_COMM_CFG0_REG (SCT_BASE_ADDR + 0x54) +#define SCT_COMM_CFG1_REG (SCT_BASE_ADDR + 0x58) +#define SCT_MEM_GUARD_REG (SCT_BASE_ADDR + 0xec) + + + +typedef enum +{ + SHA_TYPE_1, + SHA_TYPE_224, + SHA_TYPE_256, +}shaType_e; + +typedef struct +{ + uint32_t length : 16; + uint32_t dir : 1; // 0 - Encryption, 1 - Decryption + uint32_t aesMode : 2; // 0 ¨C ECB, 1 ¨C CBC, 2 ¨C CTR + uint32_t paddingMode : 3; + uint32_t ckLen : 2; // 0 ¨C 128, 1 ¨C 192, 2 ¨C 256 + uint32_t aesCkSel : 1; // 0 ¨C from configured CK address, 1 ¨C from efuse + uint32_t : 2; + uint32_t subType : 2; // 0 ¨C AES descriptor; 1 ¨C SHA descriptor + uint32_t type : 3; // Default 101 +}aesField_t; + +typedef struct +{ + uint32_t length : 16; // sha can handle 64k data one time + uint32_t shaMode : 2; // 0: sha1; 1: sha224; 2: sha256 + uint32_t shaBls : 1; // sha output endian. 0: LE; 1: BE + uint32_t rcs : 1; // 0: current is last data; 1: current data is continuous + uint32_t outEn : 1; // open output + uint32_t : 6; + uint32_t subType : 2; // // 0: aes; 1:sha + uint32_t type : 3; // Default 101 +}shaField_t; + + +typedef struct +{ + uint32_t headLen : 16; + uint32_t : 16; +}shaHeadLen_t; + +typedef struct +{ + union firstWord + { + aesField_t aesField; + shaField_t shaField; + }u1; + + uint32_t srcAddr; + uint32_t dstAddr; + + union secondWord + { + uint32_t aesCkAddr; + uint32_t shaHeaderAddr; + }u2; + + union thirdWord + { + uint32_t aesIvAddr; + shaHeadLen_t shaHeadLen; + }u3; +}sctDescCfg_t; + +typedef struct +{ + uint32_t trigger : 1; + uint32_t reset : 1; + uint32_t : 30; +}sctChanCfg_t; + + +typedef union { + struct + { + uint32_t fifoLen : 8; // chain fifo length, max is 255 + uint32_t chainIntEn : 1; + uint32_t chainEmptyIntEn : 1; + uint32_t chainFullIntEn : 1; + uint32_t ckBLEndian : 1; + uint32_t aesIvBLEndian : 1; // bit: 12 + uint32_t ckOptDis : 1; // bit: 13 + uint32_t : 2; + uint32_t crcPolyLen : 2; // bit: 16:17 + uint32_t : 1; + uint32_t crcOutComple : 1; // bit: 19 + uint32_t crcInCompleByteNum: 4; // bit: 20:23 + uint32_t crcOutBitSwap : 1; // bit: 24 + uint32_t crcInBitSwap : 1; // bit: 25 + uint32_t : 6; + }; + uint32_t val; +}chanCfgWord0_t; + +typedef struct +{ + chanCfgWord0_t chanCfgWord0; + uint32_t chanCfgWord1; // First desc addr + uint32_t rsvd[3]; + sctChanCfg_t chanCfgWord5; +}sctCfgWord_t; + +typedef struct +{ + uint32_t chaNextCfgIdx : 8; + uint32_t chaNextDoneIdx : 8; + uint32_t chaFreeLen : 8; + uint32_t chaBeFull : 1; + uint32_t chaBeEmpty : 1; + uint32_t chaBeAct : 1; + uint32_t chaBeRstDone : 1; + uint32_t descBeTimeout : 1; + uint32_t : 3; +}sctChaState_t; + +typedef struct +{ + uint32_t hAddr0; + uint32_t lAddr0; + uint32_t hAddr1; + uint32_t lAddr1; + uint32_t hAddr2; + uint32_t lAddr2; + uint32_t hAddr3; + uint32_t lAddr3; +}sctMemGuard_t; + +typedef union +{ + struct + { + uint32_t rmiAcg : 1; + uint32_t ahbAcg : 1; + uint32_t : 14; + uint32_t chainStartUnilog : 1; + uint32_t descDoneUnilog : 1; + uint32_t chainEndUnilog : 1; + uint32_t errorIntUnilog : 1; + uint32_t usbEndianInd : 1; + uint32_t : 3; + uint32_t memHighAddrOffset : 8; + }; + uint32_t val; +}sctCfgWord0_t; + +typedef struct +{ + uint32_t descMaxProcTickTime : 20; // descriptor handle max timeout + uint32_t : 12; +}sctCfgWord1_t; + + +typedef struct +{ + uint32_t dir : 1; // 0: encrypt, 1: decrypt + uint32_t aesMode : 2; // 0: ecb, 1:cbc, 2:ctr + uint32_t paddingMode : 3; // 0: no padding, 1: PKCS7, 2: paddingOneZeros, 3: paddingZerosLen, 4: paddingZeros + uint32_t ckLen : 2; // 0:128, 1:192, 2:256 + uint32_t aesCkSel : 1; // 0: from memory, 1: from efuse + uint32_t ckBLEndian : 1; // Ignore it if key is from efuse. If key is from memory, 0: little; 1: big + uint32_t aesIvBLEndian : 1; // input AES IV is big/little endian. 0: little; 1: big + uint32_t : 23; +}aesCtrl_t; + +typedef struct +{ + uint32_t ivAddr; + uint32_t srcAddr; + uint32_t dstAddr; + uint32_t aesCkAddr; + uint32_t length; + aesCtrl_t aesCtrl; +}aesInfo_t; + +/* + * SCT memory guard address + * SCT could only access MSMB: 0x00400000 ~ 0x0053FFFF +*/ +#define MGR_LOW_ADDR 0x00400000 +#define MGR_HIGH_ADDR 0x0053FFFF + +/* + * SCT memory guard address + * USB TX FIFO: 0x00400000 ~ 0x0053FFFF +*/ +#define MGR_LOW_ADDR1 0x1A000000 +#define MGR_HIGH_ADDR1 0x1AFFFFFF + +/* + * AP flash, 4M: 0x0080-0000~0x00BF-FFFF +*/ +#define MGR_LOW_ADDR2 0x00800000 +#define MGR_HIGH_ADDR2 0x00BFFFFF + + +/* + * CP flash, 1M: 0x0880-0000~0x088F-FFFF +*/ +#define MGR_LOW_ADDR3 0x08800000 +#define MGR_HIGH_ADDR3 0x088FFFFF + + + +#define SCTDRV_OK (0) +#define SCTDRV_BUSY (-1) +#define SCTDRV_TIMEOUT (-2) +#define SCTDRV_PAMERR (-5) + +/** + \brief SCT module init. + \return +*/ +void sctInit(); + +/** + \brief Aes operation + \param[in] aesInfo Aes information. + \return status +*/ +int32_t aesUpdate(aesInfo_t* aesInfo); + +/** + \brief Sha operation. + \param[in] shaMode Choose SHA1, SHA224, SHA256. + \param[in] srcAddr SHA input address. + \param[in] dstAddr SHA output address. + \param[in] length SHA input length. + \param[in] lastFlag If you need to loop call this api, "lastFlag" should be 0 for intermediate steps, and last step it should be 1. + \return status +*/ +int32_t shaUpdate(shaType_e shaMode, uint32_t srcAddr, uint32_t dstAddr, uint32_t length, uint32_t lastFlag); + +#endif diff --git a/PLAT/driver/chip/ec618/ap/inc/uart.h b/PLAT/driver/chip/ec618/ap/inc/uart.h new file mode 100644 index 0000000..4ea19ce --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/uart.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: uart.h + * Description: EC618 uart driver header file + * History: + * + ****************************************************************************/ + +#ifndef _UART_EC618_H +#define _UART_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup uart_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** + \fn void UART_init(uint32_t instance, uint32_t baudrate, bool enableFlowCtrl) + \brief Initialize UART with specific baudrate + \param[in] instance UART instance number (0, 1, ...) + \param[in] baudrate The desired baudrate + \param[in] enableFlowCtrl Enable flow control or not + */ +void UART_init(uint32_t instance, uint32_t baudrate, bool enableFlowCtrl); + +/** + \fn uint32_t UART_send(uint32_t instance, const uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief Start sending data to USART transmitter in polling way + \param[in] instance UART instance number (0, 1, ...) + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \param[in] timeout_us timeout value in unit of us + \return num of data items sent in the internal of timeout + */ +uint32_t UART_send(uint32_t instance, const uint8_t *data, uint32_t num, uint32_t timeout_us); + +/** + \fn uint32_t UART_receive(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief Start receiving data from USART receiver in polling way + \param[in] instance UART instance number (0, 1, ...) + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \param[in] timeout_us timeout value in unit of us + \return num of data items received in the internal of timeout + */ +uint32_t UART_receive(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us); + +/** + \fn void UART_printf(uint32_t instance, const char* fmt, ...) + \brief Print formated data to USART transmitter + \param[in] instance UART instance number (0, 1, ...) + \param[in] fmt C string that contains the text to be sent to UART + \param[in] ... __VA__ARGS + */ +void UART_printf(uint32_t instance, const char* fmt, ...); + +void UART_flush(uint32_t instance); +void UART_purgeRx(uint32_t instance); + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _UART_EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc/unilog.h b/PLAT/driver/chip/ec618/ap/inc/unilog.h new file mode 100644 index 0000000..8607b1b --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/unilog.h @@ -0,0 +1,83 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ + +#ifndef _UNILOG_API_H +#define _UNILOG_API_H +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +#define UNILOG_TRACE_MAX_MODULE_VALUE (1024) + +#define UNILOG_DMA_REQ_MODE_USB (0x3) +#define UNILOG_DMA_REQ_MODE_UART (0x0) + +#define UNILOG_ID_CONSTRUCT(ownerId, moduleId, subId) ((ownerId << 28) | (moduleId << 21) | (subId << 11)) + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +typedef enum +{ + UART_0_FOR_UNILOG = 0, + UART_1_FOR_UNILOG = 1, + UART_2_FOR_UNILOG = 2, +// SPI_0_FOR_UNILOG = 3, +// SPI_1_FOR_UNILOG = 4, + USB_FOR_UNILOG = 5 +} UnilogPeripheralType_e; + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +void uniLogModuleAllowTraces(uint16_t moduleID); +void uniLogModuleDisableTraces(uint16_t moduleID); +void uniLogModuleAllowAllTraces(void); +void uniLogModuleDisableAllTraces(void); +bool uniLogTraceAllowCheck(uint8_t debugLevel); +void uniLogFlushOut(void); +void uniLogForceOut(bool waitFifoOut); +void uniLogStop(void); +void uniLogStopHwLog(void); +bool uniLogIsInitialized(void); +void uniLogGetSettingFromFlash(void); +void swLogExcep(uint32_t swLogID, uint8_t debugLevel, ...); +void swLogPrintf(uint32_t swLogID, uint8_t debugLevel, ...); +void swLogDump(uint32_t swLogID, uint8_t debugLevel, uint32_t dumpLen, const uint8_t*pDump); +void swLogPrintfPolling(uint32_t swLogID, uint8_t debugLevel, ...); +void swLogDumpPolling(uint32_t swLogID, uint8_t debugLevel, uint32_t dumpLen, const uint8_t*pDump); +void uniLogSetPherType(UnilogPeripheralType_e periphType); +UnilogPeripheralType_e uniLogGetPherType(void); +bool unilogSwitch2UartLog(void); +bool unilogSwitch2UsbLog(void); +bool uniLogGetDumpRdyFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif//_UNILOG_API_H + diff --git a/PLAT/driver/chip/ec618/ap/inc/wdt.h b/PLAT/driver/chip/ec618/ap/inc/wdt.h new file mode 100644 index 0000000..eb5557d --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc/wdt.h @@ -0,0 +1,160 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: wdt.h + * Description: EC618 wdt driver header file + * History: + * + ****************************************************************************/ + +#ifndef _WDT_EC618_H +#define _WDT_EC618_H + +#include "ec618.h" +#include "Driver_Common.h" + +/** + \addtogroup wdt_interface_gr + \{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/** \brief List of WDT mode */ +typedef enum +{ + WDT_INTERRUPT_ONLY_MODE = 0U, /**< Only generate an interrupt upon timeout */ + WDT_INTERRUPT_RESET_MODE = 1U, /**< Reset upon timeout if the first interrupt is not cleared */ +} WdtMode_e; + +/** \brief WDT configuration structure */ +typedef struct +{ + WdtMode_e mode; + uint16_t timeoutValue; +} WdtConfig_t; + +/** \brief List of WDT interrupt flags */ +typedef enum +{ + WDT_INTERRUPT_FLAG = WDT_STAT_ISTAT_Msk, /**< Wdt interrupt flag */ +} WdtInterruptFlags_e; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \name WDT Configuration */ +/** \{ */ + +/** + \fn void WDT_getDefaultConfig(WdtConfig_t *config) + \brief Gets the WDT default configuartion. + This function sets the configuration structure to default values as below: + \code + config->mode = WDT_INTERRUPT_ONLY_MODE; + config->timeoutValue = 0xFFFF; + \endcode + + \param[in] config Pointer to WDT configuration structure + */ +void WDT_getDefaultConfig(WdtConfig_t *config); + +/** + \fn void WDT_init(const WdtConfig_t *config) + \brief Initialize WDT + \param[in] config Pointer to WDT configuration + */ +void WDT_init(const WdtConfig_t *config); + +/** + \fn void WDT_deInit(void) + \brief Deinitialize WDT + */ +void WDT_deInit(void); + +/** \} */ + +/** \name WDT Unlock and Kick */ +/** \{ */ + +/** + \fn void WDT_unlock(void) + \brief Unlocks the WDT register written + */ +void WDT_unlock(void); + +/** + \fn void WDT_kick(void) + \brief Refreshes WDT counter + */ +void WDT_kick(void); + +/** \} */ + +/** \name WDT Start and Stop */ +/** \{ */ + +/** + \fn void WDT_start(void) + \brief Starts WDT counter + */ +void WDT_start(void); + +/** + \fn void WDT_stop(void) + \brief Stops WDT counter + */ +void WDT_stop(void); + +/** \} */ + +/** \name WDT Interrupt and Status */ +/** \{ */ + +/** + \fn uint32_t WDT_getInterruptFlags(void) + \brief Reads WDT interrupt status flags + \return Interrupt flags. This is the logical OR of members of the + enumeration \ref WdtInterruptFlags_e + */ +uint32_t WDT_getInterruptFlags(void); + +/** + \fn void WDTclearInterruptFlags(uint32_t mask) + \brief Clears WDT interrupt flags + \param[in] mask Interrupt flags to clear. This is a logic OR of members of the + enumeration \ref WdtInterruptFlags_e + */ +void WDTclearInterruptFlags(uint32_t mask); + +/** + \fn WdtMode_e WDT_getMode(void) + \brief Gets current WDT mode + \return WDT mode, see \ref WdtMode_e + */ +WdtMode_e WDT_getMode(void); + +/** + \fn bool WDT_getStartStatus(void) + \brief Checks if WDT is started or stopped + \return true if WDT is counting + false if WDT is stopped + */ +bool WDT_getStartStatus(void); + +/** \} */ + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_EC618_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_Common.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_Common.h new file mode 100644 index 0000000..38bd959 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_Common.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.0 + * + * Project: Common Driver definitions + */ + +/* History: + * Version 2.0 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_COMMON_H_ +#define DRIVER_COMMON_H_ + +#include +#include +#include +#include +#include "sctdef.h" +#ifdef FEATURE_OS_ENABLE +#include "exception_process.h" +#endif + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +typedef struct _PIN { + uint8_t pinNum; + uint8_t funcNum; +} PIN; + +#ifndef ASSERT +#ifdef FEATURE_OS_ENABLE +#define ASSERT(X) EC_ASSERT(X,0,0,0) +#else +#define ASSERT(X) assert(X) +#endif +#endif + +#ifndef BIT +#define BIT(n) ((unsigned int) 1 << (n)) +#define BITS2(m,n) (BIT(m) | BIT(n)) +#define BITS(m,n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) +#endif + + +#ifndef MIN +#define MIN(a,b) (((a)<(b) ? (a) : (b))) +#endif + +#endif /* DRIVER_COMMON_H_ */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_I2C.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_I2C.h new file mode 100644 index 0000000..a30c2fe --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_I2C.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.3 + * + * Project: I2C (Inter-Integrated Circuit) Driver definitions + */ + +/* History: + * Version 2.3 + * ARM_I2C_STATUS made volatile + * Version 2.2 + * Removed function ARM_I2C_MasterTransfer in order to simplify drivers + * and added back parameter "xfer_pending" to functions + * ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Version 2.1 + * Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending" + * from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Added function ARM_I2C_GetDataCount + * Removed flag "address_nack" from ARM_I2C_STATUS + * Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE + * with event ARM_I2C_EVENT_TRANSFER_DONE + * Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE + * Removed parameter "arg" from function ARM_I2C_SignalEvent + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_I2C_H_ +#define DRIVER_I2C_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ + + +/****** I2C Control Codes *****/ + +#define ARM_I2C_OWN_ADDRESS (0x01) ///< Set Own Slave Address; arg = address +#define ARM_I2C_BUS_SPEED (0x02) ///< Set Bus Speed; arg = speed +#define ARM_I2C_BUS_CLEAR (0x03) ///< Execute Bus clear: send nine clock pulses +#define ARM_I2C_ABORT_TRANSFER (0x04) ///< Abort Master/Slave Transmit/Receive + +/*----- I2C Bus Speed -----*/ +#define ARM_I2C_BUS_SPEED_STANDARD (0x01) ///< Standard Speed (100kHz) +#define ARM_I2C_BUS_SPEED_FAST (0x02) ///< Fast Speed (400kHz) +#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03) ///< Fast+ Speed ( 1MHz) +#define ARM_I2C_BUS_SPEED_HIGH (0x04) ///< High Speed (3.4MHz) + + +/****** I2C Address Flags *****/ + +#define ARM_I2C_ADDRESS_10BIT (0x0400) ///< 10-bit address flag +#define ARM_I2C_ADDRESS_GC (0x8000) ///< General Call flag + + +/** +\brief I2C Status +*/ +typedef volatile struct _ARM_I2C_STATUS { + uint32_t busy : 1; ///< Busy flag + uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master + uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver + uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation) + uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation) + uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation) + uint32_t rx_nack : 1; ///< NACK detected (cleared on start of next Master/Slave operation) + uint32_t reserved : 25; +} ARM_I2C_STATUS; + + +/****** I2C Event *****/ +#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished +#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer +#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Addressed as Slave Transmitter but transmit operation is not set. +#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Addressed as Slave Receiver but receive operation is not set. +#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave +#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< Slave addressed with general call address +#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration +#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) +#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_I2C_CAPABILITIES + + \fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) + \brief Initialize I2C Interface. + \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_I2C_Uninitialize (void) + \brief De-initialize I2C Interface. + \return \ref execution_status + + \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state) + \brief Control I2C Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start transmitting data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[in] data Pointer to buffer with data to transmit to I2C Slave + \param[in] num Number of data bytes to transmit + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num) + \brief Start transmitting data as I2C Slave. + \param[in] data Pointer to buffer with data to transmit to I2C Master + \param[in] num Number of data bytes to transmit + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num) + \brief Start receiving data as I2C Slave. + \param[out] data Pointer to buffer for data to receive from I2C Master + \param[in] num Number of data bytes to receive + \return \ref execution_status + + \fn int32_t ARM_I2C_GetDataCount (void) + \brief Get transferred data count. + \return number of data bytes transferred; -1 when Slave is not addressed by Master + + \fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg) + \brief Control I2C Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return \ref execution_status + + \fn ARM_I2C_STATUS ARM_I2C_GetStatus (void) + \brief Get I2C status. + \return I2C status \ref ARM_I2C_STATUS + + \fn void ARM_I2C_SignalEvent (uint32_t event) + \brief Signal I2C Events. + \param[in] event \ref I2C_events notification mask +*/ + +typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event. + + +/** +\brief I2C Driver Capabilities. +*/ +typedef struct _ARM_I2C_CAPABILITIES { + uint32_t address_10_bit : 1; ///< supports 10-bit addressing + uint32_t reserved : 31; ///< Reserved (must be zero) +} ARM_I2C_CAPABILITIES; + + +/** +\brief Access structure of the I2C Driver. +*/ +typedef struct _ARM_DRIVER_I2C { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version. + ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power. + int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master. + int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master. + int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave. + int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave. + int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface. + ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status. +} const ARM_DRIVER_I2C; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_I2C_H_ */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_SPI.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_SPI.h new file mode 100644 index 0000000..61b4d80 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_SPI.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.2 + * + * Project: SPI (Serial Peripheral Interface) Driver definitions + */ + +/* History: + * Version 2.2 + * ARM_SPI_STATUS made volatile + * Version 2.1 + * Renamed status flag "tx_rx_busy" to "busy" + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Half-duplex Modes + * Configurable number of data bits + * Support for TI Mode and Microwire + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added "send_done_event" to Capabilities + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_SPI_H_ +#define DRIVER_SPI_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */ + + +/****** SPI Control Codes *****/ + +#define ARM_SPI_CONTROL_Pos 0 +#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos) + +/*----- SPI Control Codes: Mode -----*/ +#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive +#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps +#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI) +#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps +#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO) + +/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/ +#define ARM_SPI_FRAME_FORMAT_Pos 8 +#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos) +#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default) +#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1 +#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0 +#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1 +#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format +#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Microwire Frame Format + +/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_SPI_DATA_BITS_Pos 12 +#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos) +#define ARM_SPI_DATA_BITS(n) (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits + +/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/ +#define ARM_SPI_BIT_ORDER_Pos 18 +#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos) +#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default) +#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB + +/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/ +#define ARM_SPI_SS_MASTER_MODE_Pos 19 +#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos) +#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default) +#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled +#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output +#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input +#define ARM_SPI_SS_SLAVE_MODE_Pos 21 +#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) +#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default) +#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled + + +/*----- SPI Control Codes: Miscellaneous Controls -----*/ +#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value +#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps +#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value +#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active +#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer + + +/****** SPI Slave Select Signal definitions *****/ +#define ARM_SPI_SS_INACTIVE 0 ///< SPI Slave Select Signal Inactive +#define ARM_SPI_SS_ACTIVE 1 ///< SPI Slave Select Signal Active + + +/****** SPI specific error codes *****/ +#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported +#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported +#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported + + +/** +\brief SPI Status +*/ +typedef volatile struct _ARM_SPI_STATUS { + uint32_t busy : 1; ///< Transmitter/Receiver busy flag + uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation) + uint32_t reserved : 29; +} ARM_SPI_STATUS; + + +/****** SPI Event *****/ +#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed +#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow +#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_SPI_CAPABILITIES + + \fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event) + \brief Initialize SPI Interface. + \param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_SPI_Uninitialize (void) + \brief De-initialize SPI Interface. + \return \ref execution_status + + \fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state) + \brief Control SPI Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_SPI_Send (const void *data, uint32_t num) + \brief Start sending data to SPI transmitter. + \param[in] data Pointer to buffer with data to send to SPI transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_SPI_Receive (void *data, uint32_t num) + \brief Start receiving data from SPI receiver. + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_SPI_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from SPI transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_SPI_GetDataCount (void) + \brief Get transferred data count. + \return number of data items transferred + + \fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg) + \brief Control SPI Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref spi_execution_status + + \fn ARM_SPI_STATUS ARM_SPI_GetStatus (void) + \brief Get SPI status. + \return SPI status \ref ARM_SPI_STATUS + + \fn void ARM_SPI_SignalEvent (uint32_t event) + \brief Signal SPI Events. + \param[in] event \ref SPI_events notification mask + \return none +*/ + +typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event. + + +/** +\brief SPI Driver Capabilities. +*/ +typedef struct _ARM_SPI_CAPABILITIES { + uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave) + uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface + uint32_t microwire : 1; ///< supports Microwire Interface + uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT + uint32_t reserved : 28; ///< Reserved (must be zero) +} ARM_SPI_CAPABILITIES; + + +/** +\brief Access structure of the SPI Driver. +*/ +typedef struct _ARM_DRIVER_SPI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version. + ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI. + uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface. + ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status. +} const ARM_DRIVER_SPI; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_SPI_H_ */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_USART.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_USART.h new file mode 100644 index 0000000..824878a --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/Driver_USART.h @@ -0,0 +1,358 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.3 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + */ + +/* History: + * Version 2.3 + * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile + * Version 2.2 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.1 + * Removed optional argument parameter from Signal Event + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_USART_H_ +#define DRIVER_USART_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer +#define ARM_USART_CONTROL_FLUSH_TX (0x1BUL << ARM_USART_CONTROL_Pos) ///< FLUSH TX FIFO +#define ARM_USART_CONTROL_PURGE_COMM (0x1CUL << ARM_USART_CONTROL_Pos) ///< Purge communition(clear rx & tx fifo) + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef volatile struct _ARM_USART_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) + uint32_t is_send_block : 1; ///< Whether Send API works in blocking way + uint32_t reserved : 24; +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef volatile struct _ARM_USART_MODEM_STATUS { + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive + uint32_t reserved : 28; +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) +#define ARM_USART_EVENT_AUTO_BAUDRATE_DONE (1UL << 14) ///< Auto baudrate dection completed + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn uint32_t ARM_USART_GetBaudRate (void) + \brief Get current baud rate. + \return current baud rate + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none + + \fn int32_t ARM_USART_SendPolling (const void *data, uint32_t num) + \brief Start sending data to USART transmitter in polling way. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI + uint32_t reserved : 11; ///< Reserved (must be zero) +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. + uint32_t (*GetBaudRate) (void); ///< Pointer to \ref ARM_USART_GetBaudRate : Get current baud rate. + int32_t (*SendPolling) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_SendPolling : Start sending data to USART transmitter in polling way. This is an extended API not inlcuded in original CMSIS driver version. +} const ARM_DRIVER_USART; + + + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_USART_H_ */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_i2c.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_i2c.h new file mode 100644 index 0000000..f77595f --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_i2c.h @@ -0,0 +1,93 @@ +#ifndef BSP_I2C_H +#define BSP_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + + +// I2C Driver state flags +#define I2C_FLAG_INIT BIT(0) // Driver initialized +#define I2C_FLAG_POWER BIT(1) // Driver power on +#define I2C_FLAG_SETUP BIT(2) // Master configured, clock set +#define I2C_FLAG_MASTER_TX BIT(3) // Master tx +#define I2C_FLAG_MASTER_RX BIT(4) // Master rx +#define I2C_FLAG_SLAVE_TX BIT(5) // Slave tx +#define I2C_FLAG_SLAVE_RX BIT(6) // Slave rx + +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (I2C_SCR_STOP_Msk) +#define I2C_GENERATE_START_READ (I2C_SCR_START_Msk | I2C_SCR_TARGET_RWN_Msk) +#define I2C_GENERATE_START_WRITE (I2C_SCR_START_Msk) +#define I2C_GENERATE_RESTART_READ (I2C_SCR_RESTART_Msk | I2C_SCR_TARGET_RWN_Msk) +#define I2C_GENERATE_RESTART_WRITE (I2C_SCR_RESTART_Msk) + + +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) + +#define I2C_AUTOMATIC_MODE1 (0x01) // byte_num_unknown = 0 +#define I2C_AUTOMATIC_MODE2 (0x02) // byte_num_unknown = 1 +#define I2C_DEDICATED_MODE (0x03) + +// I2C IRQ +typedef const struct _I2C_IRQ { + IRQn_Type irq_num; // I2C IRQ Number + IRQ_Callback_t cb_irq; +} I2C_IRQ; + +// I2C PINS +typedef const struct _I2C_PIN { + PIN *pin_scl; // SCL Pin identifier + PIN *pin_sda; // SDA Pin identifier +} I2C_PINS; + +// I2C DMA +typedef struct _I2C_DMA { + DmaInstance_e tx_instance; // Transmit DMA instance + int8_t tx_ch; // Transmit channel number + uint8_t tx_req; // Transmit DMA request number + void (*tx_callback)(uint32_t event); // Transmit callback + DmaInstance_e rx_instance; // Receive DMA instance + int8_t rx_ch; // Receive channel number + uint8_t rx_req; // Receive DMA request number + void (*rx_callback)(uint32_t event); // Receive callback +} I2C_DMA; + + +// I2C Control Information +typedef struct { + ARM_I2C_SignalEvent_t cb_event; // Event callback + ARM_I2C_STATUS status; // Status flags + uint8_t flags; // Control and state flags + uint8_t sla_rw; // Slave address and RW bit + bool pending; // Transfer pending (no STOP) + uint8_t stalled; // Stall mode status flags + uint8_t con_aa; // I2C slave CON flag + uint32_t cnt; // Master transfer count + uint8_t *data; // Master data to transfer + uint32_t num; // Number of bytes to transfer + uint8_t *sdata; // Slave data to transfer + uint32_t snum; // Number of bytes to transfer +} I2C_CTRL; + + +// I2C Resources definition +typedef struct { + I2C_TypeDef *reg; // I2C peripheral register interface + I2C_PINS pins; // I2C PINS config + I2C_DMA* dma; // I2C DMA configuration + I2C_IRQ* irq; // I2C IRQ + I2C_CTRL *ctrl; // Run-Time control information +} const I2C_RESOURCES; + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_I2C_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_lpusart.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_lpusart.h new file mode 100644 index 0000000..771e249 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_lpusart.h @@ -0,0 +1,116 @@ +#ifndef BSP_LPUSART_H +#define BSP_LPUSART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "ec618.h" +#include "bsp.h" + + +// LPUSART flags +#define LPUSART_FLAG_INITIALIZED (1U << 0) // LPUSARTinitialized +#define LPUSART_FLAG_POWER_FULL (1U << 1) // LPUSART powered FULL +#define LPUSART_FLAG_POWER_LOW (1U << 2) // LPUSART powered LOW +#define LPUSART_FLAG_CONFIGURED (1U << 3) // LPUSART configured +#define LPUSART_FLAG_TX_ENABLED (1U << 4) // LPUSART TX enabled +#define LPUSART_FLAG_RX_ENABLED (1U << 5) // LPUSART RX enabled +#define LPUSART_FLAG_SEND_ACTIVE (1U << 6) // LPUSART send active + +#define LPUSART_FLAG_POWER_MSK (LPUSART_FLAG_POWER_LOW | LPUSART_FLAG_POWER_FULL) + +// LPUSART IRQ +typedef const struct _LPUSART_IRQ { + IRQn_Type irq_num; // LPUSART IRQ Number + IRQ_Callback_t cb_irq; +} LPUSART_IRQ; + +// LPUSART TX DMA +typedef struct _LPUSART_TX_DMA { + DmaInstance_e instance; // DMA instance + int8_t channel; // Channel number + uint8_t request; // DMA request number + void (*callback)(uint32_t event); // Tx callback +} LPUSART_TX_DMA; + +// LPUSART RX DMA +typedef struct _LPUSART_RX_DMA { + DmaInstance_e instance; // DMA instance + int8_t channel; // Channel number + uint8_t request; // DMA request number + DmaDescriptor_t *descriptor; // Rx descriptor + void (*callback)(uint32_t event); // Rx callback +} LPUSART_RX_DMA; + +// LPUSART PINS +typedef const struct _LPUSART_PIN { + const PIN *pin_tx; // TX Pin identifier + const PIN *pin_rx; // RX Pin identifier + const PIN *pin_cts; // CTS Pin identifier + const PIN *pin_rts; // RTS Pin identifier +} LPUSART_PINS; + + +typedef struct _LPUSART_TRANSFER_INFO { + uint32_t rx_num; // Total number of receive data + uint32_t tx_num; // Total number of transmit data + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint16_t tx_def_val; // Default transmit value + uint16_t rx_dump_val; // Receive dump value + uint8_t send_active; // Send active flag + uint32_t sync_mode; // Synchronous mode flag +} LPUSART_TRANSFER_INFO; + +typedef struct _LPUSART_STATUS { + uint8_t rx_busy; // Receiver busy flag + uint8_t rx_dma_triggered; // Receive DMA transfer triggered (cleared on start of next receive operation) + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) + uint8_t aon_rx_overflow; // AON FIFO receive data overflow detected (cleared on start of next receive operation) + uint8_t rx_break; // Break detected on receive (cleared on start of next receive operation) + uint8_t rx_framing_error; // Framing error detected on receive (cleared on start of next receive operation) + uint8_t rx_parity_error; // Parity error detected on receive (cleared on start of next receive operation) +} LPUSART_STATUS; + +typedef struct _LPUSART_INFO { + ARM_USART_SignalEvent_t cb_event; // Event Callback + LPUSART_STATUS rx_status; // Recieve Status flags + LPUSART_TRANSFER_INFO xfer; // LPUSART transfer information + uint8_t flags; // Current LPUSART flags + uint32_t frame_code; // Current LPUSART frame setting code + uint32_t baudrate; // Baudrate +} LPUSART_INFO; + +// LPUSART Resources definition +typedef const struct { + USART_TypeDef *co_usart_regs; // LPUSART cooperating uart registers pointer + LPUSARTAON_TypeDef *aon_regs; // LPUSART AON part registers pointer + LPUSARTCORE_TypeDef *core_regs; // LPUSART CORE part registers pointer + LPUSART_PINS pins; // LPUSART PINS config + LPUSART_RX_DMA *dma_rx; // LPUSART DMA register interface + LPUSART_TX_DMA *co_usart_dma_tx; // LPUSART DMA register interface + LPUSART_RX_DMA *co_usart_dma_rx; // LPUSART DMA register interface + LPUSART_IRQ *irq; // LPUSART IRQ + LPUSART_IRQ *co_usart_irq; // LPUSART cooperating uart IRQ + LPUSART_INFO *info; // Run-Time Information +} LPUSART_RESOURCES; + + +void LPUSART_ClearStopFlag(void); +void LPUSART_SetStopFlag(void); +/* + * Check whether rx is ongoing, return true if rx is ongoing at this moment, otherwise false + */ +bool LPUSART_IsRxActive(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_LPLPUSART_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_spi.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_spi.h new file mode 100644 index 0000000..3a6457d --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_spi.h @@ -0,0 +1,89 @@ +#ifndef BSP_SPI_H +#define BSP_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + + +// SPI flags +#define SPI_FLAG_INITIALIZED (1UL << 0) // SPI initialized +#define SPI_FLAG_POWERED (1UL << 1) // SPI powered on +#define SPI_FLAG_CONFIGURED (1UL << 2) // SPI configured +#define SPI_FLAG_DATA_LOST (1UL << 3) // SPI data lost occurred +#define SPI_FLAG_MODE_FAULT (1UL << 4) // SPI mode fault occurred + +// SPI IRQ +typedef const struct _SPI_IRQ { + IRQn_Type irq_num; // SPI IRQ Number + IRQ_Callback_t cb_irq; +} SPI_IRQ; + +// SPI DMA +typedef struct _SPI_DMA { + DmaInstance_e tx_instance; // Transmit DMA instance number + int8_t tx_ch; // Transmit channel number + uint8_t tx_req; // Transmit DMA request number + void (*tx_callback)(uint32_t event); // Transmit callback + DmaInstance_e rx_instance; // Receive DMA instance number + int8_t rx_ch; // Receive channel number + uint8_t rx_req; // Receive DMA request number + void (*rx_callback)(uint32_t event); // Receive callback +} SPI_DMA; + +// SPI PINS +typedef const struct _SPI_PIN { + const PIN *pin_sclk; // SCLK Pin identifier + const PIN *pin_ssn; // SSn Pin identifier + const PIN *pin_mosi; // MOSI Pin identifier + const PIN *pin_miso; // MISO Pin identifier +} SPI_PINS; + +typedef struct _SPI_STATUS { + uint8_t busy; // Transmitter/Receiver busy flag + uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) +} SPI_STATUS; + +// SPI Transfer Information (Run-Time) +typedef struct _SPI_TRANSFER_INFO { + uint32_t num; // Total number of transfers + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint32_t dump_val; // Variable for dumping DMA data + uint16_t def_val; // Default transfer value +} SPI_TRANSFER_INFO; + +// SPI information (Run-time) +typedef struct _SPI_INFO { + ARM_SPI_SignalEvent_t cb_event; // event callback + SPI_STATUS status; // SPI status flags + SPI_TRANSFER_INFO xfer; // SPI transfer information + uint8_t flags; // SPI driver flags + uint32_t mode; // SPI mode + uint32_t bus_speed; // SPI bus speed + uint8_t data_width; // SPI data bits select in unit of byte +} SPI_INFO; + + +// SPI Resources definition +typedef struct { + SPI_TypeDef *reg; // SPI register pointer + SPI_PINS pins; // SPI PINS configuration + SPI_DMA *dma; // SPI DMA configuration pointer + SPI_IRQ *irq; // SPI IRQ configuration pointer + SPI_INFO *info; // Run-Time Information +} SPI_RESOURCES; + + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_SPI_H */ diff --git a/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_usart.h b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_usart.h new file mode 100644 index 0000000..bd51a27 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/inc_cmsis/bsp_usart.h @@ -0,0 +1,108 @@ +#ifndef BSP_USART_H +#define BSP_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdio.h" +#include "string.h" +#include "ec618.h" +#include "bsp.h" + + +// USART flags +#define USART_FLAG_INITIALIZED (1U << 0) // USARTinitialized +#define USART_FLAG_POWERED (1U << 1) // USART powered on +#define USART_FLAG_CONFIGURED (1U << 2) // USART configured +#define USART_FLAG_TX_ENABLED (1U << 3) // USART TX enabled +#define USART_FLAG_RX_ENABLED (1U << 4) // USART RX enabled +#define USART_FLAG_SEND_ACTIVE (1U << 5) // USART send active + +#define USART_TFE_INT (0x2<CTRL |= ADC_CTRL_LDO_EN_Msk; \ + *(uint32_t*)(LDO_AIO_CTRL_REG_ADDR) = 1; \ + while((*(uint32_t*)(LDO_AIO_CTRL_REG_ADDR)) == 0); \ + } while(0) + +#define ADC_DISABLE() do \ + { \ + ADC->CTRL &= ~ADC_CTRL_LDO_EN_Msk; \ + *(uint32_t*)(LDO_AIO_CTRL_REG_ADDR) = 0; \ + while((*(uint32_t*)(LDO_AIO_CTRL_REG_ADDR)) == 1); \ + } while(0) + +#define ADC_CHANNEL_NUMBER (6) + +#ifdef PM_FEATURE_ENABLE +#define LOCK_SLEEP() do \ + { \ + slpManDrvVoteSleep(SLP_VOTE_ADC, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define UNLOCK_SLEEP() do \ + { \ + slpManDrvVoteSleep(SLP_VOTE_ADC, SLP_SLP1_STATE); \ + } \ + while(0) +#endif + +#define ADC_DEFAULT_CLOCK_DIVIDER (ADC_CLOCK_DIV_8) + +#define ADC_CHANNEL_ENABLE_BIT_POSITION (ADC_AIOCFG_THM_EN_Pos) + +/** + \brief size of ADC request queue, value shall be integer power of 2 for fast calcualtion of MOD. + \note The valid number of requests is (this_macro_value - 1) + */ +#define ADC_REQUEST_QUEUE_SIZE (8) +#define ADC_REQUEST_QUEUE_SIZE_MASK (ADC_REQUEST_QUEUE_SIZE - 1) + +/** + \brief ADC conversion request queue typedef + */ +typedef struct +{ + uint32_t requestArray[ADC_REQUEST_QUEUE_SIZE]; + uint32_t head; + uint32_t tail; +} AdcReqeustQueue_t; + +static AdcReqeustQueue_t gAdcRequestqueue; + +/** + \brief variable for keeping track the index of current request bitmap, see below bitmap layout + */ +static volatile uint32_t gCurrentRequestIndex; + +/** \brief Internal used data structure */ +typedef struct +{ + struct + { + uint32_t AIOCFG; /**< AIO configuration Register */ + uint32_t CFG; /**< ADC configuration Register */ + } configRegisters; + + adcCallback_t eventCallback; /**< Callback function passed in by application */ +} AdcChannelDatabase_t; + +/** + ****************************** Bitmap layout ***************************** + * + * 18 17 15 14 12 11 9 8 6 5 3 2 0 + *+-----------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + *| VREF OUT | CH AIO1 | CH AIO2 | CH AIO3 | CH AIO4 | CH Vbat | CH thermal| + *+-----------+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * / \ + * / \ + * / \ + * |APP | PLAT | PHY| + */ +#define CHANNEL_ID_TO_INDEX(channel, userID) ((userID & 0x3U) + (channel & 0x7U) * 3U) + +#define ADC_MAX_LOGIC_CHANNELS (ADC_CHANNEL_NUMBER * ADC_USER_MAX) + +/** \brief Internal used data structure */ +typedef struct +{ + uint32_t channelConfigValidBitMap; /**< Bitmap of channel configuration valid flag */ + AdcChannelDatabase_t channelDataBase[ADC_MAX_LOGIC_CHANNELS]; /**< Array of channel database, each element represents one configuration */ +} AdcDatabase_t; + +static AdcDatabase_t g_adcDataBase = {0}; +void delay_us(uint32_t us); + +static void ADC_requestQueueInit(void) +{ + gAdcRequestqueue.head = 0; + gAdcRequestqueue.tail = 0; + gCurrentRequestIndex = ADC_MAX_LOGIC_CHANNELS; +} + +// no need to perform atomic access since this function is called only in ISR +static int32_t ADC_requestQueueRead(uint32_t *request) +{ + if(gAdcRequestqueue.tail == gAdcRequestqueue.head) + { + // queue is empty + return -1; + } + + *request = gAdcRequestqueue.requestArray[gAdcRequestqueue.head]; + gAdcRequestqueue.head = (gAdcRequestqueue.head + 1) & ADC_REQUEST_QUEUE_SIZE_MASK; + + return 0; + +} + +static int32_t ADC_requestQueueWrite(uint32_t *request) +{ + uint32_t mask; + + mask = SaveAndSetIRQMask(); + if(((gAdcRequestqueue.tail + 1) & ADC_REQUEST_QUEUE_SIZE_MASK) == gAdcRequestqueue.head) + { + // queue is full + RestoreIRQMask(mask); + return -1; + } + + gAdcRequestqueue.requestArray[gAdcRequestqueue.tail] = *request; + gAdcRequestqueue.tail = (gAdcRequestqueue.tail + 1) & ADC_REQUEST_QUEUE_SIZE_MASK; + + RestoreIRQMask(mask); + + return 0; +} + +static void ADC_loadConfigAndStartConversion(uint32_t requestIndex) +{ + uint32_t aiocfg; + // clear status first + // LDO has been enabled during initialization phase, here we shall keep this bit set + ADC->CTRL = ADC_CTRL_LDO_EN_Msk | ADC_CTRL_EN_Msk; + + // Protect VREF2AIO1 control bit, take care not to overwrite!!! + aiocfg = (ADC->AIOCFG & ADC_AIOCFG_VREF2AIO1_EN_Msk) | g_adcDataBase.channelDataBase[requestIndex].configRegisters.AIOCFG; + +#ifdef PM_FEATURE_ENABLE + // thermmal comparator close when sample thm channel + if(aiocfg & ADC_AIOCFG_THM_EN_Msk) + { + alarmThmDisableInAdc(); + } +#endif + // Protect VREF2AIO1 control bit, take care not to overwrite!!! + ADC->AIOCFG = aiocfg; + ADC->CFG = g_adcDataBase.channelDataBase[requestIndex].configRegisters.CFG; + +#ifdef PM_FEATURE_ENABLE + // thermal channel closed + if((ADC->AIOCFG & ADC_AIOCFG_THM_EN_Msk) == 0) + { + if(alarmThmEnableInAdc() == false) + { + delay_us(10); + } + } + else +#endif + delay_us(10); + + // start conversion + ADC->CTRL = (ADC_CTRL_LDO_EN_Msk | ADC_CTRL_EN_Msk | ADC_CTRL_RSTN_Msk); +} + + +static void ADC_interruptHandler(void) +{ + uint32_t requestIndex; + + int32_t ret; + + ADC->AIOCFG &= ~(ADC_AIOCFG_THM_EN_Msk | ADC_AIOCFG_BATSENS_EN_Msk | ADC_AIOCFG_AIO4_EN_Msk | + ADC_AIOCFG_AIO3_EN_Msk | ADC_AIOCFG_AIO2_EN_Msk | ADC_AIOCFG_AIO1_EN_Msk | + ADC_AIOCFG_AIO4_NO_DIVR_EN_Msk | ADC_AIOCFG_AIO3_NO_DIVR_EN_Msk | + ADC_AIOCFG_AIO2_NO_DIVR_EN_Msk | ADC_AIOCFG_AIO1_NO_DIVR_EN_Msk); + + if(g_adcDataBase.channelDataBase[gCurrentRequestIndex].eventCallback != NULL) + { + g_adcDataBase.channelDataBase[gCurrentRequestIndex].eventCallback(ADC->RESULT); + } + + // Shall check config validation here since config could be changed in user callback(Deinit is called) + /* + R1 R2 R1 (3 request at once) R1 deInit R2 deInit (validBitMap change to 0 and ADC is disabled) + APP ------------------------------------\ /--------------\ /------------\ + | | | | x + v | v | x + --------- --------- xxxxxxxxxxxxxxxxxxxxxxxxxxxx + ADC ISR R1 R2 R1 is still in queue, stuck here(interrupt never occurs) + */ + + + if(g_adcDataBase.channelConfigValidBitMap != 0) + { + ret = ADC_requestQueueRead(&requestIndex); + + // Start next round conversion + if(ret == 0) + { + // there is pending request + gCurrentRequestIndex = requestIndex; + + ADC_loadConfigAndStartConversion(gCurrentRequestIndex); + } + else + { + gCurrentRequestIndex = ADC_MAX_LOGIC_CHANNELS; +#ifdef PM_FEATURE_ENABLE + alarmThmEnableInAdc(); + UNLOCK_SLEEP(); +#endif + } + + } + else + { + ADC_requestQueueInit(); +#ifdef PM_FEATURE_ENABLE + alarmThmEnableInAdc(); + UNLOCK_SLEEP(); +#endif + } + +} + +void ADC_getDefaultConfig(AdcConfig_t *config) +{ + ASSERT(config); + + config->clockDivider = ADC_DEFAULT_CLOCK_DIVIDER; + config->channelConfig.aioResDiv = ADC_AIO_RESDIV_BYPASS; +} + +int32_t ADC_channelInit(AdcChannel_e channel, AdcUser_t userID, const AdcConfig_t *config, adcCallback_t callback) +{ + uint32_t mask, configValue, requestIndex; + + configValue = 0; + + requestIndex = CHANNEL_ID_TO_INDEX(channel, userID); + + if(requestIndex >= ADC_MAX_LOGIC_CHANNELS) + { + return -1; + } + + mask = SaveAndSetIRQMask(); + + // AIO1 conflict check + if((channel == ADC_CHANNEL_AIO1) && ((g_adcDataBase.channelConfigValidBitMap & (1 << ADC_MAX_LOGIC_CHANNELS)) != 0)) + { + RestoreIRQMask(mask); + return -2; + } + + // First Initialization + if(g_adcDataBase.channelConfigValidBitMap == 0) + { + // enable ADC + ADC_ENABLE(); + XIC_SetVector(PXIC1_AUXADC_IRQn, ADC_interruptHandler); + XIC_EnableIRQ(PXIC1_AUXADC_IRQn); + ADC_requestQueueInit(); + } + g_adcDataBase.channelConfigValidBitMap |= ( 1 << requestIndex); + RestoreIRQMask(mask); + + configValue |= ( EIGEN_VAL2FLD(ADC_CFG_WAIT_CTRL, 1) | \ + EIGEN_VAL2FLD(ADC_CFG_OFFSET_CTRL, 5) | \ + EIGEN_VAL2FLD(ADC_CFG_SAMPLE_AVG, 0) | \ + EIGEN_VAL2FLD(ADC_CFG_CLKIN_DIV, config ? config->clockDivider : ADC_DEFAULT_CLOCK_DIVIDER) | \ + EIGEN_VAL2FLD(ADC_CFG_VREF_BS, 1) | \ + EIGEN_VAL2FLD(ADC_CFG_VREF_SEL, 4) | \ + EIGEN_VAL2FLD(ADC_CFG_LDO_SEL, 4) | \ + EIGEN_VAL2FLD(ADC_CFG_IBIAS_SEL, 1) + ); + g_adcDataBase.channelDataBase[requestIndex].configRegisters.CFG = configValue; + + configValue = 0; + + switch(channel) + { + case ADC_CHANNEL_THERMAL: + configValue = 1 << (channel + ADC_CHANNEL_ENABLE_BIT_POSITION) | EIGEN_VAL2FLD(ADC_AIOCFG_THM_SEL, 2); + break; + + case ADC_CHANNEL_VBAT: + configValue = (1 << (channel + ADC_CHANNEL_ENABLE_BIT_POSITION)) | EIGEN_VAL2FLD(ADC_AIOCFG_VBATSEN_RDIV, config->channelConfig.vbatResDiv); + break; + + case ADC_CHANNEL_AIO1: + case ADC_CHANNEL_AIO2: + case ADC_CHANNEL_AIO3: + case ADC_CHANNEL_AIO4: + + if(config->channelConfig.aioResDiv == ADC_AIO_RESDIV_BYPASS) + { + configValue = 1 << (channel + ADC_CHANNEL_ENABLE_BIT_POSITION + 4); + } + else if(config->channelConfig.aioResDiv < ADC_AIO_RESDIV_RATIO_8OVER16) + { + configValue = (1 << (channel + ADC_CHANNEL_ENABLE_BIT_POSITION)) | ADC_AIOCFG_RDIV_BYP_Msk | EIGEN_VAL2FLD(ADC_AIOCFG_RDIV, config->channelConfig.aioResDiv); + } + else + { + configValue = (1 << (channel + ADC_CHANNEL_ENABLE_BIT_POSITION)) | (EIGEN_VAL2FLD(ADC_AIOCFG_RDIV, (config->channelConfig.aioResDiv - ADC_AIO_RESDIV_RATIO_8OVER16))); + } + break; + default: + break; + } + + g_adcDataBase.channelDataBase[requestIndex].configRegisters.AIOCFG = configValue; + g_adcDataBase.channelDataBase[requestIndex].eventCallback = callback; + + return 0; +} + +void ADC_channelDeInit(AdcChannel_e channel, AdcUser_t userID) +{ + uint32_t mask = SaveAndSetIRQMask(); + + g_adcDataBase.channelConfigValidBitMap &= ~(1 << CHANNEL_ID_TO_INDEX(channel, userID)); + + if(g_adcDataBase.channelConfigValidBitMap == 0) + { + // diable ADC + ADC->CTRL = ADC->CTRL & ADC_CTRL_LDO_EN_Msk; + // disable clock + ADC_DISABLE(); + XIC_DisableIRQ(PXIC1_AUXADC_IRQn); + } + + RestoreIRQMask(mask); +} + +int32_t ADC_startConversion(AdcChannel_e channel, AdcUser_t userID) +{ + uint32_t mask, requestIndex; + int32_t ret; + + requestIndex = CHANNEL_ID_TO_INDEX(channel, userID); + + ASSERT(requestIndex < ADC_MAX_LOGIC_CHANNELS); + + mask = SaveAndSetIRQMask(); + + // validation check + if((g_adcDataBase.channelConfigValidBitMap & (1 << requestIndex)) == 0) + { + RestoreIRQMask(mask); + return -2; + } + + // A conversion is ongoing, pending the request + if(gCurrentRequestIndex != ADC_MAX_LOGIC_CHANNELS) + { + RestoreIRQMask(mask); + + ret = ADC_requestQueueWrite(&requestIndex); + + if(ret != 0) + { + // request queue is full + return ret; + } + } + else + { + gCurrentRequestIndex = requestIndex; + ADC_loadConfigAndStartConversion(gCurrentRequestIndex); + RestoreIRQMask(mask); + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(); +#endif + + } + + return 0; + +} + +int32_t ADC_enableVrefOutput(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + // AIO1 conflict check + if((g_adcDataBase.channelConfigValidBitMap & (0x7 << (ADC_CHANNEL_AIO1*3U))) != 0) + { + RestoreIRQMask(mask); + return -2; + } + + // First Initialization + if(g_adcDataBase.channelConfigValidBitMap == 0) + { + // enable ADC + ADC_ENABLE(); + XIC_SetVector(PXIC1_AUXADC_IRQn, ADC_interruptHandler); + XIC_EnableIRQ(PXIC1_AUXADC_IRQn); + ADC_requestQueueInit(); + } + ADC->AIOCFG |= ADC_AIOCFG_VREF2AIO1_EN_Msk; + g_adcDataBase.channelConfigValidBitMap |= ( 1 << ADC_MAX_LOGIC_CHANNELS); + + RestoreIRQMask(mask); + + return 0; +} + +void ADC_disableVrefOutput(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + g_adcDataBase.channelConfigValidBitMap &= ~(1 << ADC_MAX_LOGIC_CHANNELS); + + ADC->AIOCFG &= ~ADC_AIOCFG_VREF2AIO1_EN_Msk; + + if(g_adcDataBase.channelConfigValidBitMap == 0) + { + // diable ADC + ADC->CTRL = ADC->CTRL & ADC_CTRL_LDO_EN_Msk; + // disable clock + ADC_DISABLE(); + XIC_DisableIRQ(PXIC1_AUXADC_IRQn); + } + + RestoreIRQMask(mask); + +} + + diff --git a/PLAT/driver/chip/ec618/ap/src/apmu2Peripheral.c b/PLAT/driver/chip/ec618/ap/src/apmu2Peripheral.c new file mode 100644 index 0000000..8acbf11 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/apmu2Peripheral.c @@ -0,0 +1,235 @@ +#include "ic.h" +#include "apmu2Peripheral.h" +#ifdef __USER_CODE__ +#include "RTE_Device.h" +#else +#include "RTE_Device.h" +#endif +#include "timer.h" +#include "clock.h" +#include DEBUG_LOG_HEADER_FILE +#if (RTE_USB_EN == 1) +void usblpw_enter_start_proc(bool force_cfg_pwr_down); +void usblpw_enter_abort_proc(bool force_cfg_pwr_down); +void usblpw_susp2vbustbl_guard_dlychk(uint32_t cur_tick); +void usblpw_susp2hib_guard_dlychk(uint32_t cur_tick); +void usblpw_retwkup_sleep1_later_recovery(void); +void usblpw_retwkup_sleep1_pre_recovery(void); +#endif + +#if (RTE_LPUART_EN == 1) +#include "bsp_lpusart.h" +#endif + +// to wakeup in paging wfi for hib timer, should only use in paging.(timer4 can use in app) +#define AP_NEARHIBTIME_INSTANCE (4) +#define AP_NEARHIBTIME_IRQ (PXIC0_TIMER4_IRQn) +#define AP_NEARHIBTIME_MAXIMUM (4294967) // 0xffffffff/1000 ms + +// do not use timer5 in app +#define CP_STARTTIME_INSTANCE (5) +#define CP_STARTTIME_IRQ (PXIC0_TIMER5_IRQn) +#define CP_STARTTIME_MAXIMUM (4294967) // 0xffffffff/1000 ms + +void apmuPeriUsbEnterStartProc(bool forceCfgPwrDown) +{ +#if (RTE_USB_EN == 1) + usblpw_enter_start_proc(forceCfgPwrDown); +#endif +} + +void apmuPeriUsbEnterAbortProc(bool forceCfgPwrDown) +{ +#if (RTE_USB_EN == 1) + usblpw_enter_abort_proc(forceCfgPwrDown); +#endif +} + +void apmuPeriUsbSusp2VbusTblGuardDlyChk(uint32_t cur_tick) +{ +#if (RTE_USB_EN == 1) + usblpw_susp2vbustbl_guard_dlychk(cur_tick); +#endif +} + +void apmuPeriUsbSusp2HibGuardDlyChk(uint32_t cur_tick) +{ +#if (RTE_USB_EN == 1) + usblpw_susp2hib_guard_dlychk(cur_tick); +#endif +} + +void apmuPeriUsbSleep1LateRecoverFlow(bool sleepSuccess) +{ +#if (RTE_USB_EN == 1) + if(sleepSuccess) + { + usblpw_retwkup_sleep1_later_recovery(); + } +#endif +} + +void apmuPeriUsbSleep1PreRecoverFlow(bool sleepSuccess) +{ +#if (RTE_USB_EN == 1) + if(sleepSuccess) + { + usblpw_retwkup_sleep1_pre_recovery(); + } +#endif +} + +bool apmuPeriLpuartPreSleepProcess(void) +{ +#if (RTE_LPUART_EN == 1) + LPUSART_SetStopFlag(); + if(LPUSART_IsRxActive()) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, apmuPeriLpuartPreSleepProcess_1, P_WARNING, "lpuart status, iir: 0x%x, fcsr: 0x%x, tcr: 0x%x, tsr: 0x%x", LPUSART_CORE->IIR, LPUSART_CORE->FCSR, LPUSART_CORE->TCR, LPUSART_CORE->TSR); + LPUSART_ClearStopFlag(); + return true; + } + else + { + extern void AonRegSetWakeupEdge(uint8_t index, bool posEnable, bool negEnable); + AonRegSetWakeupEdge(6, false, true); + NVIC_EnableIRQ(LpuartWakeup_IRQn); + } + LPUSART_ClearStopFlag(); + return false; +#else + return false; +#endif +} + +bool apmuPeriLpuartIsRxActive(void) +{ +#if (RTE_LPUART_EN == 1) + return LPUSART_IsRxActive(); +#else + return false; +#endif +} + +static void apmuPeriWFITimerExp(void) +{ + ECPLAT_PRINTF(UNILOG_PMU, apmu2PeriWFITimerExp_0, P_VALUE, "apmu2PeriWFITimerExp Enter"); + if (TIMER_getInterruptFlags(CP_STARTTIME_INSTANCE) & TIMER_MATCH0_INTERRUPT_FLAG) + { + TIMER_clearInterruptFlags(CP_STARTTIME_INSTANCE, TIMER_MATCH0_INTERRUPT_FLAG); + } + TIMER_stop(AP_NEARHIBTIME_INSTANCE); + TIMER_deInit(AP_NEARHIBTIME_INSTANCE); +} + + +void apmuPeriStartWFITimer(uint32_t ms) +{ + int32_t clkRet1,clkRet2; + if(ms<10) + return; + + CLOCK_clockReset(FCLK_TIMER4); // to protect setClock error + + // TIMER config + // Config TIMER clock, source from 26MHz and divide by 1 + clkRet1 = CLOCK_setClockSrc(FCLK_TIMER4, FCLK_TIMER4_SEL_26M); + clkRet2 = CLOCK_setClockDiv(FCLK_TIMER4, 26); + + if((clkRet1 != 0) || (clkRet2 != 0)) + { + ECPLAT_PRINTF(UNILOG_PMU, apmuPeriStartWFITimer_0, P_ERROR, "clkRet1=%d, clkRet2=%d, CLKFREQ=0x%x", clkRet1, clkRet2, CLOCK_getClockFreq(FCLK_TIMER4)); + EC_ASSERT(0, clkRet1, clkRet2, CLOCK_getClockFreq(FCLK_TIMER4)); + } + + TimerConfig_t timerConfig; + TIMER_getDefaultConfig(&timerConfig); + timerConfig.reloadOption = TIMER_RELOAD_ON_MATCH0; + + if(ms > AP_NEARHIBTIME_MAXIMUM) + { + ms = AP_NEARHIBTIME_MAXIMUM; + } + timerConfig.match0 = (ms-5)*1000; + + ECPLAT_PRINTF(UNILOG_PMU, apmuPeriStartWFITimer_1, P_VALUE, "apmuPeriStartWFITimer set to %u ms", (ms-5)); + + TIMER_init(AP_NEARHIBTIME_INSTANCE, &timerConfig); + + TIMER_interruptConfig(AP_NEARHIBTIME_INSTANCE, TIMER_MATCH0_SELECT, TIMER_INTERRUPT_LEVEL); + TIMER_interruptConfig(AP_NEARHIBTIME_INSTANCE, TIMER_MATCH1_SELECT, TIMER_INTERRUPT_DISABLED); + TIMER_interruptConfig(AP_NEARHIBTIME_INSTANCE, TIMER_MATCH2_SELECT, TIMER_INTERRUPT_DISABLED); + + // Enable TIMER IRQ + XIC_SetVector(AP_NEARHIBTIME_IRQ, apmuPeriWFITimerExp); + XIC_EnableIRQ(AP_NEARHIBTIME_IRQ); + + TIMER_start(AP_NEARHIBTIME_INSTANCE); +} + +void apmuPeriDeleteWFITimer(void) +{ + TIMER_stop(AP_NEARHIBTIME_INSTANCE); + TIMER_deInit(AP_NEARHIBTIME_INSTANCE); +} + +void apmuPeriDeleteCPTimer(void) +{ + TIMER_stop(CP_STARTTIME_INSTANCE); + TIMER_deInit(CP_STARTTIME_INSTANCE); +} + +void apmuPeriClearCPTimerInterrupt(void) +{ + if (TIMER_getInterruptFlags(CP_STARTTIME_INSTANCE) & TIMER_MATCH0_INTERRUPT_FLAG) + { + TIMER_clearInterruptFlags(CP_STARTTIME_INSTANCE, TIMER_MATCH0_INTERRUPT_FLAG); + } +} + +void apmuPeriStartCPTimer(uint32_t cpStartTime, void* expFunc) +{ + int32_t clkRet1,clkRet2; + + CLOCK_clockReset(FCLK_TIMER5); // to protect setClock error, can not reproduce easily + + // TIMER config + // Config TIMER clock, source from 26MHz and divide by 1 + clkRet1 = CLOCK_setClockSrc(FCLK_TIMER5, FCLK_TIMER5_SEL_26M); + clkRet2 = CLOCK_setClockDiv(FCLK_TIMER5, 26); + + if((clkRet1 != 0) || (clkRet2 != 0)) + { + ECPLAT_PRINTF(UNILOG_PMU, apmuPeriStartCPTimer_0, P_ERROR, "clkRet1=%d, clkRet2=%d, CLKFREQ=0x%x", clkRet1, clkRet2, CLOCK_getClockFreq(FCLK_TIMER5)); + EC_ASSERT(0, clkRet1, clkRet2, CLOCK_getClockFreq(FCLK_TIMER5)); + } + TimerConfig_t timerConfig; + TIMER_getDefaultConfig(&timerConfig); + timerConfig.reloadOption = TIMER_RELOAD_ON_MATCH0; + + if(cpStartTime > CP_STARTTIME_MAXIMUM) + { + cpStartTime = CP_STARTTIME_MAXIMUM; + } + timerConfig.match0 = (cpStartTime-1)*1000; + + ECPLAT_PRINTF(UNILOG_PMU, apmuPeriStartCPTimer_1, P_VALUE, "apmuCreateModemStartTimer set to %u ms", (cpStartTime-1)); + + TIMER_init(CP_STARTTIME_INSTANCE, &timerConfig); + + TIMER_interruptConfig(CP_STARTTIME_INSTANCE, TIMER_MATCH0_SELECT, TIMER_INTERRUPT_LEVEL); + TIMER_interruptConfig(CP_STARTTIME_INSTANCE, TIMER_MATCH1_SELECT, TIMER_INTERRUPT_DISABLED); + TIMER_interruptConfig(CP_STARTTIME_INSTANCE, TIMER_MATCH2_SELECT, TIMER_INTERRUPT_DISABLED); + + // Enable TIMER IRQ + XIC_SetVector(CP_STARTTIME_IRQ, expFunc); + XIC_EnableIRQ(CP_STARTTIME_IRQ); + TIMER_start(CP_STARTTIME_INSTANCE); + + +} + + + + + diff --git a/PLAT/driver/chip/ec618/ap/src/clock.c b/PLAT/driver/chip/ec618/ap/src/clock.c new file mode 100644 index 0000000..b3f93ea --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/clock.c @@ -0,0 +1,469 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: clock.c + * Description: EC618 clock driver source file + * History: Rev1.0 2019-02-20 + * + ****************************************************************************/ + +#include "clock.h" +#include +#include +#include "Driver_Common.h" +#ifdef PM_FEATURE_ENABLE +#include DEBUG_LOG_HEADER_FILE +#endif + +extern bool GPR_clockEnableCheck(ClockId_e id); +extern ClockId_e CLOCK_checkClkID(void); + + +/** \brief support clock driver full feature or not */ +#define ENABLE_CLK_TREE_PARENT + +/** \brief definition of clk tree element for clock management */ +typedef struct _clk_tree_element +{ + uint32_t enableCount : 8; /**< counter of each clk has been enabled */ + uint32_t parentId : 17; /**< id of this clock's parent clk */ + uint32_t hasExtraDependency : 1; /**< whether or not this clock has extra dependent clock */ + uint32_t canChangeSrcForcely : 1; /**< whether or not the source of this clock can be changed in enabled state */ +} ClkTreeElement_t; + +/** \brief clock tree Array */ +static ClkTreeElement_t g_clkTreeArray[] = +{ + + [GET_INDEX_FROM_CLOCK_ID(CLK_CC)] = {1, CLK_MF, 0, 1}, + [GET_INDEX_FROM_CLOCK_ID(CLK_APB_MP)] = {1, CLK_MF, 0, 1}, + [GET_INDEX_FROM_CLOCK_ID(CLK_APB_XP)] = {1, CLK_MF, 0, 1}, + [GET_INDEX_FROM_CLOCK_ID(CLK_SMP)] = {1, INVALID_CLK, 0, 1}, + [GET_INDEX_FROM_CLOCK_ID(CLK_SYSTICK)] = {1, CLK_32K, 0, 1}, + + + [GET_INDEX_FROM_CLOCK_ID(FCLK_UART0)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_UART1)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_UART2)] = {0, CLK_MF_GATED, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(FCLK_SPI0)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_SPI1)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_I2S0)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_I2S1)] = {0, CLK_MF_GATED, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(FCLK_WDG)] = {0, CLK_32K_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER0)] = {0, CLK_32K_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER1)] = {0, CLK_32K_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER2)] = {0, CLK_32K_GATED, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER3)] = {0, CLK_32K_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER4)] = {0, CLK_32K_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_TIMER5)] = {0, CLK_32K_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_I2C0)] = {0, CLK_MF_GATED, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(FCLK_I2C1)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_USIM0)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_USIM1)] = {0, CLK_MF_GATED, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FCLK_KPC)] = {0, CLK_32K_GATED, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(CLK_FLASH)] = {1, CLK_MF, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_PSRAM)] = {0, CLK_MF, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_MF)] = {1, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_32K)] = {1, INVALID_CLK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(CLK_HF408M)] = {1, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_HF204M)] = {1, CLK_HF408M, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_HF102M)] = {0, CLK_HF204M, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_HF51M)] = {0, CLK_HF102M, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(CLK_32K_GATED)] = {1, CLK_32K, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_MF_GATED)] = {1, CLK_MF, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_CC_MP)] = {1, CLK_CC, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_CC_AP)] = {1, CLK_CC, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(CLK_CC_CP)] = {1, CLK_CC, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_AON)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_SMP_MP)] = {0, CLK_SMP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(MFAB_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(AFBBR_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(MSMB_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FLASH_HCLK)] = {0, INVALID_CLK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PSRAM_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(ULOG_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(UTFC_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(ULDP_HCLK)] = {0, INVALID_CLK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(USBC_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(USBC_PMU_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(USBC_REF_CLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(USBP_REF_CLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(USBC_UTMI_CLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_DAP_AP)] = {1, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_TRACE_AP)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_SYSTICK_AP)] = {0, CLK_SYSTICK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(CLK_APB_AP)] = {1, CLK_APB_XP, 1, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_SMP_AP)] = {1, CLK_SMP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CLK_CLKCAL)] = {0, CLK_MF, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_SIPC)] = {0, CLK_APB_MP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PCLK_AON)] = {1, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_CPMU)] = {1, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_PMDIG)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_RFDIG)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_PAD)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_GPIO)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_FUSE)] = {1, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_TRNG)] = {0, CLK_APB_MP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PCLK_USBP)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_LPUC)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_UART0)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_UART1)] = {0, CLK_APB_MP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PCLK_UART2)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_SPI0)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_SPI1)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_I2S0)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_I2S1)] = {0, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_WDG)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_TIMER0)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_TIMER1)] = {0, CLK_APB_AP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PCLK_TIMER2)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_TIMER3)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_TIMER4)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_TIMER5)] = {0, CLK_APB_AP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PCLK_IPC)] = {1, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_I2C0)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_I2C1)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_USIM0)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_USIM1)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_KPC)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(PCLK_ONEW)] = {0, CLK_APB_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(TOP_PBRG_HCLK)] = {1, CLK_CC_MP, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(TOP_PBRG_PCLK)] = {1, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(TOP_GPR_PCLK)] = {1, CLK_APB_MP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(TRACE_CLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(ETM_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(ROMTABLE_HCLK)] = {0, INVALID_CLK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(TPIU_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(CACHE_HCLK)] = {1, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(FABSUB_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(SBU_HCLK)] = {0, INVALID_CLK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(PBRG_HCLK)] = {1, CLK_CC_AP, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(SPIS_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(XIC_RMI_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(ULOG_RMI_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(TMU_RMI_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(SCT_RMI_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(UTFC_RMI_HCLK)] = {0, INVALID_CLK, 0, 0}, + [GET_INDEX_FROM_CLOCK_ID(ULDP_RMI_HCLK)] = {0, INVALID_CLK, 0, 0}, + + [GET_INDEX_FROM_CLOCK_ID(SCT_HCLK)] = {0, INVALID_CLK, 0, 0}, + +}; + + +PLAT_PA_RAMCODE void CLOCK_Trace(ClockId_e id, bool isEnable, void *func) +{ +#ifdef PM_FEATURE_ENABLE + ClockId_e checkId = CLOCK_checkClkID(); + uint32_t indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + + if(id == checkId) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CLOCK_Trace_1, P_WARNING, "Clock Trace, id=0x%x isEnable=%d counter=%d, funcPtr=%x", id, isEnable, g_clkTreeArray[indexFromId].enableCount, func); + } + + if (g_clkTreeArray[indexFromId].enableCount > 128) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CLOCK_Trace_2, P_WARNING, "Clock Trace, id=0x%x counter=%d may overflow, funcPtr=%x", id, g_clkTreeArray[indexFromId].enableCount, func); + } +#endif +} + +void CLOCK_AssertChkBeforeSlp(void) +{ +#ifdef PM_FEATURE_ENABLE + if(CLOCK_checkClkID() == INVALID_CLK) + return; + uint32_t indexFromId = GET_INDEX_FROM_CLOCK_ID(CLOCK_checkClkID()); + if(g_clkTreeArray[indexFromId].enableCount != 0) + EC_ASSERT(0, g_clkTreeArray[indexFromId].enableCount, indexFromId, 0); +#endif + +} + +PLAT_PA_RAMCODE int32_t CLOCK_clockEnable(ClockId_e id) +{ + +#if defined(ENABLE_CLK_TREE_PARENT) + int32_t ret; +#endif + + uint32_t mask, indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + + if(indexFromId > GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return ARM_DRIVER_ERROR_PARAMETER; + else if(indexFromId == GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return ARM_DRIVER_OK; + + mask = SaveAndSetIRQMask(); + + CLOCK_Trace(id, true, __GET_RETURN_ADDRESS()); + + if(g_clkTreeArray[indexFromId].enableCount++ == 0) + { + GPR_clockEnable(id); + RestoreIRQMask(mask); + +#if defined(ENABLE_CLK_TREE_PARENT) + if(g_clkTreeArray[indexFromId].hasExtraDependency) + { + ret = CLOCK_clockEnable(PBRG_HCLK); + ASSERT(ret == ARM_DRIVER_OK); + } + + ret = CLOCK_clockEnable((ClockId_e)g_clkTreeArray[indexFromId].parentId); + ASSERT(ret == ARM_DRIVER_OK); +#endif + } + else + { + if(GPR_clockEnableCheck(id) == false) + { + #ifdef PM_FEATURE_ENABLE + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CLOCK_clockEnable_1, P_WARNING, "Clock Enable Failed, id=0x%x counter=%d", id, g_clkTreeArray[indexFromId].enableCount); + #endif + ASSERT(0); + } + + RestoreIRQMask(mask); + } + + return ARM_DRIVER_OK; +} + +PLAT_PA_RAMCODE void CLOCK_clockDisable(ClockId_e id) +{ + uint32_t mask, indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + + if(indexFromId >= GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return; + + mask = SaveAndSetIRQMask(); + + CLOCK_Trace(id, false, __GET_RETURN_ADDRESS()); + + if(g_clkTreeArray[indexFromId].enableCount == 0) + { + RestoreIRQMask(mask); + +#ifdef PM_FEATURE_ENABLE + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CLOCK_clockDisable_0, P_WARNING, "Clock Disable check failed, id=0x%x", id); +#endif + ASSERT(0); + + return; + } + + if(!(--g_clkTreeArray[indexFromId].enableCount)) + { + GPR_clockDisable(id); + + RestoreIRQMask(mask); + +#if defined(ENABLE_CLK_TREE_PARENT) + if(g_clkTreeArray[indexFromId].hasExtraDependency) + { + CLOCK_clockDisable(PBRG_HCLK); + } + CLOCK_clockDisable((ClockId_e)g_clkTreeArray[indexFromId].parentId); +#endif + + } + else + { + RestoreIRQMask(mask); + } +} + +PLAT_PA_RAMCODE void CLOCK_clockReset(ClockId_e id) +{ + uint32_t mask, indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + uint8_t count = 0; + if(indexFromId >= GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return; + + mask = SaveAndSetIRQMask(); + + count = g_clkTreeArray[indexFromId].enableCount; + + g_clkTreeArray[indexFromId].enableCount = 0; + + GPR_clockDisable(id); + + RestoreIRQMask(mask); + + /* here, maybe not right */ +#if defined(ENABLE_CLK_TREE_PARENT) + if(count > 0) + { + CLOCK_clockDisable((ClockId_e)g_clkTreeArray[indexFromId].parentId); + } +#endif + + return; +} + +int32_t CLOCK_setClockSrc(ClockId_e id, ClockSelect_e select) +{ + int32_t ret, mask, indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + + if(indexFromId >= GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return ARM_DRIVER_ERROR_PARAMETER; + + mask = SaveAndSetIRQMask(); + + if((g_clkTreeArray[indexFromId].enableCount == 0) || (g_clkTreeArray[indexFromId].canChangeSrcForcely == 1)) + { + ret = GPR_setClockSrc(id, select); + if(ret == ARM_DRIVER_OK) + { + g_clkTreeArray[indexFromId].parentId = (ClockId_e)(GET_PARENTCLOCKID_FROM_CLOCK_SEL_VALUE(select)); + } + + RestoreIRQMask(mask); + + return ret; + } + + RestoreIRQMask(mask); + + return ARM_DRIVER_ERROR; +} + +int32_t CLOCK_setClockDiv(ClockId_e id, uint32_t div) +{ + int32_t mask, indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + + if(indexFromId >= GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return ARM_DRIVER_ERROR_PARAMETER; + + mask = SaveAndSetIRQMask(); + + if(g_clkTreeArray[indexFromId].enableCount == 0) + { + RestoreIRQMask(mask); + return GPR_setClockDiv(id, div); + } + + RestoreIRQMask(mask); + + return ARM_DRIVER_ERROR; + +} + +uint32_t CLOCK_getClockFreq(ClockId_e id) +{ + return GPR_getClockFreq(id); +} + +int32_t CLOCK_setFracDivConfig(FracDivConfig_t * config) +{ + if(config == NULL) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + else + { + if((config->fracDiv0DivRatioInteger == 256) && (config->fracDiv0DivRatioFrac != 0)) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if((config->fracDiv1DivRatioInteger == 256) && (config->fracDiv1DivRatioFrac != 0)) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + GPR_setFracDivConfig(config); + + return ARM_DRIVER_OK; + } + +} + +void CLOCK_bclkEnable(BclkId_e id) +{ + GPR_BclkEnable(id); +} + + +void CLOCK_fracDivOutCLkEnable(FracDivOutClkId_e id) +{ + GPR_fracDivOutCLkEnable(id); +} + +void CLOCK_fracDivOutClkDisable(FracDivOutClkId_e id) +{ + GPR_fracDivOutClkDisable(id); +} + +void CLOCK_setFracDivOutClkDiv(FracDivOutClkId_e id, uint8_t div) +{ + GPR_setFracDivOutClkDiv(id, div); +} + +void CLOCK_setBclkSrc(BclkId_e id, BclkSrc_e src) +{ + GPR_setBclkSrc(id, src); +} + +void CLOCK_setBclkDiv(BclkId_e id, uint8_t div) +{ + GPR_setBclkDiv(id, div); +} + +void CLOCK_setMclkSrc(MclkId_e id, MclkSrc_e src) +{ + GPR_setMclkSrc(id, src); +} + +void CLOCK_mclkEnable(MclkId_e id) +{ + GPR_mclkEnable(id); +} + +void CLOCK_mclkDisable(MclkId_e id) +{ + GPR_mclkDisable(id); +} + +void CLOCK_setMclkDiv(MclkId_e id, uint8_t div) +{ + GPR_setMclkDiv(id, div); +} + +void CLOCK_updateClockTreeElement(ClockId_e id, ClockId_e parentId, uint8_t enableCount) +{ + int32_t mask, indexFromId = GET_INDEX_FROM_CLOCK_ID(id); + + if(indexFromId >= GET_INDEX_FROM_CLOCK_ID(INVALID_CLK)) + return; + + mask = SaveAndSetIRQMask(); + + g_clkTreeArray[indexFromId].parentId = parentId; + g_clkTreeArray[indexFromId].enableCount = enableCount; + + RestoreIRQMask(mask); +} + diff --git a/PLAT/driver/chip/ec618/ap/src/cspi.c b/PLAT/driver/chip/ec618/ap/src/cspi.c new file mode 100644 index 0000000..9fc33c1 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/cspi.c @@ -0,0 +1,878 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: cspi.c + * Description: Dedicated spi for camera use in EC618. The interface is similar with CMSIS Driver API V2.0. + * History: Rev1.0 2021-03-18 + * + ****************************************************************************/ +#include "cspi.h" +#include "slpman.h" +#include "cameraDrv.h" + +////////////////////////////////////////////////////////////////////////////////////////////// +// CSPI Setting field Start +// All the CSPI's parameters that need user to set are all put here +////////////////////////////////////////////////////////////////////////////////////////////// +static DmaTransferConfig_t g_dmaRxConfig = +{ + NULL, + NULL, + DMA_FLOW_CONTROL_SOURCE, + DMA_ADDRESS_INCREMENT_TARGET, + DMA_DATA_WIDTH_FOUR_BYTES, + DMA_BURST_32_BYTES, + 0 +}; + +#if (RTE_CSPI0) +static PIN cspi0PinMCLK = {RTE_CSPI0_MCLK_PAD_ADDR, RTE_CSPI0_MCLK_FUNC}; +static PIN cspi0PinPCLK = {RTE_CSPI0_PCLK_PAD_ADDR, RTE_CSPI0_PCLK_FUNC}; +static PIN cspi0PinCS = {RTE_CSPI0_CS_PAD_ADDR, RTE_CSPI0_CS_FUNC}; +static PIN cspi0PinSdo0 = {RTE_CSPI0_SDO0_PAD_ADDR, RTE_CSPI0_SDO0_FUNC}; +static PIN cspi0PinSdo1 = {RTE_CSPI0_SDO1_PAD_ADDR, RTE_CSPI0_SDO1_FUNC}; + +#elif (RTE_CSPI1) +static PIN cspi1PinMCLK = {RTE_CSPI1_MCLK_PAD_ADDR, RTE_CSPI1_MCLK_FUNC}; +static PIN cspi1PinPCLK = {RTE_CSPI1_PCLK_PAD_ADDR, RTE_CSPI1_PCLK_FUNC}; +static PIN cspi1PinCS = {RTE_CSPI1_CS_PAD_ADDR, RTE_CSPI1_CS_FUNC}; +static PIN cspi1PinSdo0 = {RTE_CSPI1_SDO0_PAD_ADDR, RTE_CSPI1_SDO0_FUNC}; +static PIN cspi1PinSdo1 = {RTE_CSPI1_SDO1_PAD_ADDR, RTE_CSPI1_SDO1_FUNC}; +#endif + +// Data Format +cspiDataFmt_t cspiDataFmt = +{ + .slaveModeEn = 1, + .slotSize = 7, + .wordSize = 7, + .alignMode = 0, + .endianMode = 0, // 0:LSB 1: MSB. + .dataDly = 0, + .txPad = 0, + .rxSignExt = 0, + .txPack = 0, + .rxPack = 2, + .txFifoEndianMode = 0, + .rxFifoEndianMode = 0 +}; + +// Frame Info0 +cspiFrameInfo0_t cspiFrameInfo0 = +{ + .cspiBusTimeOutCycle = 0x1000, + .dataId = 0, // readOnly +}; + +// RX Fifo timeout Cycle +cspiTimeOutCycle_t cspiRxTimeOutCycle = +{ + .rxTimeOutCycle = 20, +}; + +// INT Control +cspiIntCtrl_t cspiIntCtrl = +{ + .txUnderRunIntEn = 0, + .txDmaErrIntEn = 0, + .txDatIntEn = 0, + .rxOverFlowIntEn = 0, + .rxDmaErrIntEn = 0, + .rxDatIntEn = 0, + .rxTimeOutIntEn = 0, + .fsErrIntEn = 0, + .frameStartIntEn = 0, + .frameEndIntEn = 0, + .cspiBusTimeOutIntEn = 0, + .txIntThreshHold = 8, + .rxIntThreshHold = 8, +}; + + +// DMA Control +cspiDmaCtrl_t cspiDmaCtrl = +{ + .rxDmaReqEn = 1, + .txDmaReqEn = 0, + .rxDmaTimeOutEn = 0, + .dmaWorkWaitCycle = 31, + .rxDmaBurstSizeSub1 = 7, + .txDmaBurstSizeSub1 = 7, + .rxDmaThreadHold = 7, + .txDmaThreadHold = 8, + .rxFifoFlush = 0, + .txFifoFlush = 0 +}; + +cspiCtrl_t cspiCtrl = +{ + .enable = 0, + .csEn = 0, + .rxWid = 1, // 0: 1bit; 1: 2bit + .rxdSeq = 1, // gc032a 0, sp0a39 1 + .cpol = 0, + .cpha = 1, + .frameProcEn = 1, + .fillYonly = 1, + .hwInitEn = 1, + .lsCheckEn = 1, + .dpCheckEn = 1, + .frameProcInitEn = 0, + .rowScaleRatio = 0, + .colScaleRatio = 0, + .scaleBytes = 0, +}; + +////////////////////////////////////////////////////////////////////////////////////////////// +// CSPI Setting field End +////////////////////////////////////////////////////////////////////////////////////////////// + + + +static CSPI_TypeDef* const cspiInstance[CSPI_INSTANCE_NUM] = {CSPI0, CSPI1}; + +static ClockId_e cspiClk[CSPI_INSTANCE_NUM * 2] = +{ + PCLK_I2S0, + FCLK_I2S0, + PCLK_I2S1, + FCLK_I2S1 +}; + +static ClockResetId_e cspiRstClk[CSPI_INSTANCE_NUM * 2] = +{ + RST_PCLK_I2S0, + RST_FCLK_I2S0, + RST_PCLK_I2S1, + RST_FCLK_I2S1 +}; + +#ifdef PM_FEATURE_ENABLE +/** + \brief spi initialization counter, for lower power callback register/de-register + */ +static uint32_t cspiInitCnt = 0; + +/** + \brief Bitmap of CSPI working status, each instance is assigned 2 bits representing tx and rx status, + when all CSPI instances are not working, we can vote to enter to low power state. + */ +static uint32_t cspiWorkingStats = 0; + +/** \brief Internal used data structure */ +typedef struct +{ + bool isInited; /**< Whether spi has been initialized */ + struct + { + __IO uint32_t DFMT; /**< Data Format Register, offset: 0x0 */ + __IO uint32_t SLOTCTL; /**< Slot Control Register, offset: 0x4 */ + __IO uint32_t CLKCTL; /**< Clock Control Register, offset: 0x8 */ + __IO uint32_t DMACTL; /**< DMA Control Register, offset: 0xC */ + __IO uint32_t INTCTL; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t TIMEOUTCTL; /**< Timeout Control Register, offset: 0x14 */ + __IO uint32_t STAS; /**< Status Register, offset: 0x18 */ + __IO uint32_t RFIFO; /**< Rx Buffer Register, offset: 0x1c */ + __IO uint32_t TFIFO; /**< Tx Buffer Register, offset: 0x20 */ + __IO uint32_t CSPICTL; /**< Camera SPI Control Register, offset: 0x28 */ + __IO uint32_t CCTL; /**< Auto Cg Control Register, offset: 0x2c */ + __IO uint32_t CSPIINFO0; /**< Cspi Frame info0 Register, offset: 0x30 */ + __IO uint32_t CSPIINFO1; /**< Cspi Frame info1 Register, offset: 0x34 */ + __IO uint32_t CSPIDBG; /**< Cspi Debug Register, offset: 0x38 */ + __IO uint32_t CSPINIT; /**< Cspi Init Register, offset: 0x3c */ + __IO uint32_t CLSP; /**< Cspi Line Start Register, offset: 0x40 */ + __IO uint32_t CDATP; /**< Cspi Data Packet Register, offset: 0x44 */ + __IO uint32_t CLINFO; /**< Cspi Line Info Register, offset: 0x48 */ + }regsBackup; +} cspiDataBase_t; + +static cspiDataBase_t cspiDataBase[CSPI_INSTANCE_NUM] = {0}; + +/** + \fn static void cspiEnterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, CSPI hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void cspiEnterLpStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < CSPI_INSTANCE_NUM; i++) + { + if(cspiDataBase[i].isInited == true) + { + cspiDataBase[i].regsBackup.DFMT = cspiInstance[i]->DFMT; + cspiDataBase[i].regsBackup.SLOTCTL = cspiInstance[i]->SLOTCTL; + cspiDataBase[i].regsBackup.CLKCTL = cspiInstance[i]->CLKCTL; + cspiDataBase[i].regsBackup.DMACTL = cspiInstance[i]->DMACTL; + cspiDataBase[i].regsBackup.INTCTL = cspiInstance[i]->INTCTL; + cspiDataBase[i].regsBackup.TIMEOUTCTL = cspiInstance[i]->TIMEOUTCTL; + cspiDataBase[i].regsBackup.STAS = cspiInstance[i]->STAS; + cspiDataBase[i].regsBackup.CSPICTL = cspiInstance[i]->CSPICTL; + cspiDataBase[i].regsBackup.CCTL = cspiInstance[i]->CCTL; + cspiDataBase[i].regsBackup.CSPIINFO0 = cspiInstance[i]->CSPIINFO0; + cspiDataBase[i].regsBackup.CSPIINFO1 = cspiInstance[i]->CSPIINFO1; + cspiDataBase[i].regsBackup.CSPIDBG = cspiInstance[i]->CSPIDBG; + cspiDataBase[i].regsBackup.CSPINIT = cspiInstance[i]->CSPINIT; + cspiDataBase[i].regsBackup.CLSP = cspiInstance[i]->CLSP; + cspiDataBase[i].regsBackup.CDATP = cspiInstance[i]->CDATP; + cspiDataBase[i].regsBackup.CLINFO = cspiInstance[i]->CLINFO; + } + } + break; + default: + break; + } +} + +/** + \fn static void cspiExitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, CSPI hareware is repowered, we restore user's configurations + by aidding of the stored registers. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void cspiExitLpStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < CSPI_INSTANCE_NUM; i++) + { + if(cspiDataBase[i].isInited == true) + { + GPR_clockEnable(cspiClk[2*i]); + GPR_clockEnable(cspiClk[2*i+1]); + + cspiInstance[i]->DFMT = cspiDataBase[i].regsBackup.DFMT; + cspiInstance[i]->SLOTCTL = cspiDataBase[i].regsBackup.SLOTCTL; + cspiInstance[i]->CLKCTL = cspiDataBase[i].regsBackup.CLKCTL; + cspiInstance[i]->DMACTL = cspiDataBase[i].regsBackup.DMACTL; + cspiInstance[i]->INTCTL = cspiDataBase[i].regsBackup.INTCTL; + cspiInstance[i]->TIMEOUTCTL = cspiDataBase[i].regsBackup.TIMEOUTCTL; + cspiInstance[i]->STAS = cspiDataBase[i].regsBackup.STAS; + cspiInstance[i]->CSPICTL = cspiDataBase[i].regsBackup.CSPICTL; + cspiInstance[i]->CCTL = cspiDataBase[i].regsBackup.CCTL; + cspiInstance[i]->CSPIINFO0 = cspiDataBase[i].regsBackup.CSPIINFO0; + cspiInstance[i]->CSPIINFO1 = cspiDataBase[i].regsBackup.CSPIINFO1; + cspiInstance[i]->CSPIDBG = cspiDataBase[i].regsBackup.CSPIDBG; + cspiInstance[i]->CSPINIT = cspiDataBase[i].regsBackup.CSPINIT; + cspiInstance[i]->CLSP = cspiDataBase[i].regsBackup.CLSP; + cspiInstance[i]->CDATP = cspiDataBase[i].regsBackup.CDATP; + cspiInstance[i]->CLINFO = cspiDataBase[i].regsBackup.CLINFO; + } + } + break; + + default: + break; + } +} + +#define LOCK_SLEEP(instance) \ + do \ + { \ + cspiWorkingStats |= (1U << instance); \ + slpManDrvVoteSleep(SLP_VOTE_I2S, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define CHECK_TO_UNLOCK_SLEEP(instance) \ + do \ + { \ + cspiWorkingStats &= ~(1U << instance); \ + if(cspiWorkingStats == 0) \ + slpManDrvVoteSleep(SLP_VOTE_I2S, SLP_SLP1_STATE); \ + } \ + while(0) +#endif + +#if (RTE_CSPI0) +static cspiInfo_t cspi0Info = {0}; +void cspi0DmaRxEvent(uint32_t event); +static DmaDescriptor_t __ALIGNED(16) cspi0DmaRxDesc[CAM_CHAIN_COUNT]; +static cspiDma_t cspi0Dma = +{ + DMA_INSTANCE_MP, + -1, + RTE_CSPI0_DMA_RX_REQID, + cspi0DmaRxEvent, + cspi0DmaRxDesc +}; + +static cspiRes_t cspi0Res = { + CSPI0, + { + &cspi0PinMCLK, + &cspi0PinPCLK, + &cspi0PinCS, + &cspi0PinSdo0, + &cspi0PinSdo1, + }, + &cspi0Dma, + &cspi0Info +}; +#endif + +#if (RTE_CSPI1) +static cspiInfo_t cspi1Info = {0}; +void cspi1DmaRxEvent(uint32_t event); +static DmaDescriptor_t __ALIGNED(16) cspi1DmaRxDesc[CAM_CHAIN_COUNT]; +static cspiDma_t cspi1Dma = +{ + DMA_INSTANCE_MP, + -1, + RTE_CSPI1_DMA_RX_REQID, + cspi1DmaRxEvent, + cspi1DmaRxDesc +}; + +static cspiRes_t cspi1Res = { + CSPI1, + { + &cspi1PinMCLK, + &cspi1PinPCLK, + &cspi1PinCS, + &cspi1PinSdo0, + &cspi1PinSdo1, + }, + &cspi1Dma, + &cspi1Info +}; +#endif + +/** + \fn static uint32_t cspiGetInstanceNum(cspiRes_t *cspi) + \brief Get instance number + \param[in] spi Pointer to CSPI resources + \returns instance number +*/ +static uint32_t cspiGetInstanceNum(cspiRes_t *cspi) +{ + return ((uint32_t)cspi->reg - (uint32_t)CSPI0) >> 12U; +} + +/** + \fn static int32_t cspiSetBusSpeed(uint32_t bps, cspiRes_t *cspi) + \brief Set bus speed + \param[in] bps bus speed to set + \param[in] spi Pointer to SPI resources + \return \ref execution_status +*/ +static int32_t cspiSetBusSpeed(camFrequence_e freq, cspiRes_t *cspi) +{ + uint32_t instance = cspiGetInstanceNum(cspi); + uint32_t freqDivInteger = 0; + uint32_t freqDivRatio = 0; + + switch(freq) + { + case CAM_6_5_M: + freqDivInteger = 0x40; + freqDivRatio = 0; + break; + + case CAM_13_M: + freqDivInteger = 0x20; + freqDivRatio = 0; + break; + + case CAM_25_5_M: + freqDivInteger = 0x10; + freqDivRatio = 0; + break; + + case CAM_24_M: + freqDivInteger = 0x11; + freqDivRatio = 0; + break; + + case CAM_20_M: + freqDivInteger = 0x14; + freqDivRatio = 0x666666; + break; + + default: + break; + } + + if (instance == 0) // i2s0 + { + GPR_clockEnable(FCLK_I2S0); + + GPR_fracDivOutCLkEnable(FRACDIV0_OUT0); // Fracdiv1_en + GPR_setFracDivOutClkDiv(FRACDIV0_OUT0, 1); // 4 div, from 408M -> 102M + #if 1 + GPR_setMclkSrc(MCLK0, MCLK_SRC_FRACDIV0_OUT0); // Bmclk_sel1 + GPR_mclkEnable(MCLK0); // Mclk_oe1 + #else + GPR_setMclkSrc(MCLK2, MCLK_SRC_FRACDIV1_OUT0); // Bmclk_sel1 + GPR_mclkEnable(MCLK2); + #endif + GPR_setClockSrc(CLK_CC, CLK_CC_SEL_204M); // 0x4d000020 = 0x201 + + // Fracdiv clk selects 408M and set frac and integer clk + FracDivConfig_t fracdivCfg; + fracdivCfg.source = FRACDIC_ROOT_CLK_408M; + fracdivCfg.fracDiv0DivRatioInteger = freqDivInteger;//0x10;//51M 0x10; // 25.5M + fracdivCfg.fracDiv0DivRatioFrac = freqDivRatio; + GPR_setFracDivConfig(&fracdivCfg); + } + else // i2s1 + { + GPR_clockEnable(FCLK_I2S1); + GPR_fracDivOutCLkEnable(FRACDIV1_OUT0); // Fracdiv1_en + GPR_setFracDivOutClkDiv(FRACDIV1_OUT0, 1); // 4 div, from 408M -> 102M + #if 1 + GPR_setMclkSrc(MCLK1, MCLK_SRC_FRACDIV1_OUT0); // Bmclk_sel1 + GPR_mclkEnable(MCLK1); // Mclk_oe1 + #else + GPR_setMclkSrc(MCLK2, MCLK_SRC_FRACDIV1_OUT0); // Bmclk_sel1 + GPR_mclkEnable(MCLK2); + #endif + GPR_setClockSrc(CLK_CC, CLK_CC_SEL_204M); // 0x4d000020 = 0x201 + + // Fracdiv clk selects 408M and set frac and integer clk + FracDivConfig_t fracdivCfg; + fracdivCfg.source = FRACDIC_ROOT_CLK_408M; + fracdivCfg.fracDiv1DivRatioInteger = freqDivInteger;//0x10;//51M 0x10; // 25.5M + fracdivCfg.fracDiv1DivRatioFrac = freqDivRatio; + GPR_setFracDivConfig(&fracdivCfg); + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t cspiInit(cspiCbEvent_fn cbEvent, cspiRes_t *cspi) + \brief Initialize SPI Interface. + \param[in] cbEvent Pointer to \ref cspiCbEvent_fn + \param[in] spi Pointer to CSPI resources + \return \ref execution_status +*/ +int32_t cspiInit(cspiCbEvent_fn cbEvent, cspiRes_t *cspi) +{ + int32_t returnCode; + PadConfig_t config; + uint32_t instance = cspiGetInstanceNum(cspi); + +#ifdef PM_FEATURE_ENABLE + cspiDataBase[instance].isInited = true; +#endif + + // Initialize CSPI PINS + PAD_getDefaultConfig(&config); + #if 1 // I2S1 + config.mux = cspi->pins.mclk->funcNum; + PAD_setPinConfig(cspi->pins.mclk->pinNum, &config); + #else // MCLK2 + config.mux = PAD_MUX_ALT1; + PAD_setPinConfig(14, &config); + #endif + config.mux = cspi->pins.pclk->funcNum; + PAD_setPinConfig(cspi->pins.pclk->pinNum, &config); + config.mux = cspi->pins.cs->funcNum; + PAD_setPinConfig(cspi->pins.cs->pinNum, &config); + config.mux = cspi->pins.sdo0->funcNum; + PAD_setPinConfig(cspi->pins.sdo0->pinNum, &config); + config.mux = cspi->pins.sdo1->funcNum; + PAD_setPinConfig(cspi->pins.sdo1->pinNum, &config); + + // Initialize SPI run-time resources + cspi->info->cbEvent = cbEvent; + + // Configure DMA if necessary + if (cspi->dma) + { + DMA_init(cspi->dma->rxInstance); + returnCode = DMA_openChannel(cspi->dma->rxInstance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + cspi->dma->rxCh = returnCode; + + DMA_setChannelRequestSource(cspi->dma->rxInstance, cspi->dma->rxCh, (DmaRequestSource_e)cspi->dma->rxReq); + DMA_rigisterChannelCallback(cspi->dma->rxInstance, cspi->dma->rxCh, cspi->dma->rxCb); + + // Configure rx DMA and start it + g_dmaRxConfig.sourceAddress = (void *)&(cspiInstance[instance]->RFIFO); + g_dmaRxConfig.totalLength = CSPI_TRANSFER_TRUNK_SIZE; + + DMA_enableChannelInterrupts(cspi->dma->rxInstance, cspi->dma->rxCh, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(cspi->dma->rxInstance, cspi->dma->rxCh); + } + +#ifdef PM_FEATURE_ENABLE + cspiInitCnt++; + + if(cspiInitCnt == 1U) + { + cspiWorkingStats = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_I2S_MODULE, cspiEnterLpStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_I2S_MODULE, cspiExitLpStateRestore, NULL); + } +#endif + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t cspiDeInit(cspiRes_t *cspi) + \brief De-initialize CSPI Interface. + \param[in] spi Pointer to CSPI resources + \return \ref execution_status +*/ +int32_t cspiDeInit(cspiRes_t *cspi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; + + instance = cspiGetInstanceNum(cspi); + + cspiDataBase[instance].isInited = false; + + cspiInitCnt--; + + if(cspiInitCnt == 0) + { + cspiWorkingStats = 0; + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_I2S_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_I2S_MODULE); + } +#endif + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t cspiPowerControl(cspiPowerState_e state, cspiRes_t *cspi) + \brief Control CSPI Interface Power. + \param[in] state Power state + \param[in] cspi Pointer to CSPI resources + \return \ref execution_status +*/ +int32_t cspiPowerCtrl(cspiPowerState_e state, cspiRes_t *cspi) +{ + uint32_t instance = cspiGetInstanceNum(cspi); + + switch (state) + { + case CSPI_POWER_OFF: + // DMA disable + if(cspi->dma) + { + DMA_stopChannel(cspi->dma->rxInstance, cspi->dma->rxCh, true); + } + + // Reset register values + if (instance == 0) + { + CLOCK_setClockSrc(FCLK_I2S0, FCLK_I2S0_SEL_26M); + GPR_swReset(RST_PCLK_I2S0); + } + else + { + CLOCK_setClockSrc(FCLK_I2S1, FCLK_I2S1_SEL_26M); + GPR_swReset(RST_PCLK_I2S1); + } + + + // Disable CSPI clock + GPR_clockDisable(cspiClk[instance*2]); + GPR_clockDisable(cspiClk[instance*2+1]); + + cspi->info->flags &= ~CSPI_FLAG_POWERED; + break; + + case CSPI_POWER_FULL: + //if ((cspi->info->flags & CSPI_FLAG_INITIALIZED) == 0) + //return ARM_DRIVER_ERROR; + + if (cspi->info->flags & CSPI_FLAG_POWERED) + return ARM_DRIVER_OK; + + // Enable CSPI clock + GPR_clockEnable(cspiClk[instance*2]); + GPR_clockEnable(cspiClk[instance*2+1]); + + GPR_swReset(cspiRstClk[instance*2]); + GPR_swReset(cspiRstClk[instance*2+1]); + + // Set power flag + cspi->info->flags |= CSPI_FLAG_POWERED; + + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +/** + \fn int32_t cspiReceive(void *data, uint32_t num, cspiRes_t *cspi) + \brief Start receiving data from SPI receiver. + \param[out] dataIn Pointer to buffer for data to receive from CSPI receiver + \param[in] num Number of data items to receive + \param[in] cspi Pointer to CSPI resources + \return \ref execution_status +*/ +int32_t cspiRecv(cspiRes_t *cspi) +{ + DMA_buildDescriptorChain(cspi->dma->descriptor, &g_dmaRxConfig, cspi->info->resolution, true); + DMA_loadChannelDescriptorAndRun(cspi->dma->rxInstance, cspi->dma->rxCh, cspi->dma->descriptor); + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t cspiControl(uint32_t control, uint32_t arg, cspiRes_t *cspi) + \brief Control CSPI Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \param[in] cspi Pointer to CSPI resources + \return common \ref execution_status and driver specific \ref spi_execution_status +*/ +int32_t cspiControl(uint32_t control, uint32_t arg, cspiRes_t *cspi) +{ + uint32_t instance = cspiGetInstanceNum(cspi); + + switch(control & 0xFFFFFFFF) + { + // Set transport abort + case CSPI_CTRL_TRANSABORT: + { + // If DMA mode, disable DMA channel + if(cspi->dma) + { + DMA_stopChannel(cspi->dma->rxInstance, cspi->dma->rxCh, true); + } + + // clear SPI run-time resources + cspi->reg->CSPICTL &= ~CSPI_ENABLE_Msk; + + break; + } + + // Set Bus Speed in bps; arg = value + case CSPI_CTRL_BUS_SPEED: + { + if(cspiSetBusSpeed((camFrequence_e)arg, cspi) != ARM_DRIVER_OK) + { + return ARM_DRIVER_ERROR; + } + break; + } + + // Set Data Format + case CSPI_CTRL_DATA_FORMAT: + { + memcpy((void*)&(cspiInstance[instance]->DFMT), &cspiDataFmt, sizeof(cspiDataFmt_t)); + break; + } + + // Flush rx fifo + case CSPI_CTRL_FLUSH_RX_FIFO: + { + cspiInstance[instance]->DMACTL |= 0x1000000; + break; + } + + + // Set Int En + case CSPI_CTRL_INT_CTRL: + { + memcpy((void*)&(cspiInstance[instance]->INTCTL), &cspiIntCtrl, sizeof(cspiIntCtrl_t)); + break; + } + + // Set recv mem addr + case CSPI_CTRL_MEM_ADDR: + { + g_dmaRxConfig.targetAddress = (void*)arg; // dma gloval val. After this need call "CSPI_CTRL_DMA_CTRL" + break; + } + + // Set Rx Timeout Cycle + case CSPI_CTRL_RXTOR: + { + memcpy((void*)&(cspiInstance[instance]->TIMEOUTCTL), &cspiRxTimeOutCycle, sizeof(cspiTimeOutCycle_t)); + break; + } + + // Set DMA Control + case CSPI_CTRL_DMA_CTRL: + { + //dmaInit(cspi); + memcpy((void*)&(cspiInstance[instance]->DMACTL), &cspiDmaCtrl, sizeof(cspiDmaCtrl_t)); + break; + } + + // Set CSPI Control + case CSPI_CTRL_CSPICTL: + { + memcpy((void*)&(cspiInstance[instance]->CSPICTL), &cspiCtrl, sizeof(cspiCtrl_t)); + break; + } + + // Enable or disable cspi + case CSPI_CTRL_START_STOP: + { + if (arg > 0) + { + cspiInstance[instance]->CSPICTL |= CSPI_ENABLE_Msk; + } + else + { + cspiInstance[instance]->CSPICTL &= ~CSPI_ENABLE_Msk; + } + break; + } + + // Set Frame Info0 + case CSPI_CTRL_FRAME_INFO0: + { + memcpy((void*)&(cspiInstance[instance]->CSPIINFO0), &cspiFrameInfo0, sizeof(cspiFrameInfo0_t)); + break; + } + + // Camera resolution set + case CSPI_CTRL_RESOLUTION_SET: + { + cspi->info->resolution = (camResolution_e)arg; // this will interface the dma descriptor chain count + break; + } + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + + +/** + \fn void cspiDmaRxEvent(uint32_t event, cspiRes_t *cspi) + \brief CSPI DMA Rx Event handler. + \param[in] event DMA Rx Event + \param[in] spi Pointer to CSPI resources +*/ +void cspiDmaRxEvent(uint32_t event, cspiRes_t *cspi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = cspiGetInstanceNum(cspi); +#endif + + switch(event) + { + case DMA_EVENT_END: + //cspi->reg->CSPICTL &= ~CSPI_ENABLE_Msk; // must close cspi here + + if(cspi->info->cbEvent) + { + cspi->info->cbEvent(ARM_SPI_EVENT_TRANSFER_COMPLETE); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + break; + + default: + break; + } +} + +#if (RTE_CSPI0) + +static int32_t cspi0Init(cspiCbEvent_fn cbEvent) +{ + return cspiInit(cbEvent, &cspi0Res); +} +static int32_t cspi0Deinit(void) +{ + return cspiDeInit(&cspi0Res); +} +static int32_t cspi0PowerCtrl(cspiPowerState_e state) +{ + return cspiPowerCtrl(state, &cspi0Res); +} + +static int32_t cspi0Recv(void) +{ + return cspiRecv(&cspi0Res); +} + +static int32_t cspi0Ctrl(uint32_t control, uint32_t arg) +{ + return cspiControl(control, arg, &cspi0Res); +} + +void cspi0DmaRxEvent(uint32_t event) +{ + cspiDmaRxEvent(event, &cspi0Res); +} + +// CSPI0 Driver Control Block +cspiDrvInterface_t cspiDrvInterface0 = { + cspi0Init, + cspi0Deinit, + cspi0PowerCtrl, + cspi0Recv, + cspi0Ctrl, +}; + +#endif + +#if (RTE_CSPI1) +static int32_t cspi1Init(cspiCbEvent_fn cbEvent) +{ + return cspiInit(cbEvent, &cspi1Res); +} +static int32_t cspi1Deinit(void) +{ + return cspiDeInit(&cspi1Res); +} +static int32_t cspi1PowerCtrl(cspiPowerState_e state) +{ + return cspiPowerCtrl(state, &cspi1Res); +} + +static int32_t cspi1Recv(void) +{ + return cspiRecv(&cspi1Res); +} + +static int32_t cspi1Ctrl(uint32_t control, uint32_t arg) +{ + return cspiControl(control, arg, &cspi1Res); +} + +void cspi1DmaRxEvent(uint32_t event) +{ + cspiDmaRxEvent(event, &cspi1Res); +} + +// CSPI1 Driver Control Block +cspiDrvInterface_t cspiDrvInterface1 = { + cspi1Init, + cspi1Deinit, + cspi1PowerCtrl, + cspi1Recv, + cspi1Ctrl, +}; + +#endif + diff --git a/PLAT/driver/chip/ec618/ap/src/gpio.c b/PLAT/driver/chip/ec618/ap/src/gpio.c new file mode 100644 index 0000000..897f294 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/gpio.c @@ -0,0 +1,199 @@ + /**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: gpio.c + * Description: EC618 gpio driver source file + * History: + * + ****************************************************************************/ + +#include "gpio.h" +#include "clock.h" +#include "slpman.h" + +#define EIGEN_GPIO(n) ((GPIO_TypeDef *) (MP_GPIO_BASE_ADDR + 0x1000*n)) + +/** + \brief GPIO stutas flag + */ +static uint32_t gGpioStatus = 0; + +#ifdef PM_FEATURE_ENABLE +/** + \fn void GPIO_enterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Backup gpio configurations before sleep. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +void GPIO_enterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + return; +} + +/** + \fn void GPIO_exitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore gpio configurations after exit from sleep. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +void GPIO_exitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + if(gGpioStatus & 0x1U) + { + GPR_clockEnable(PCLK_GPIO); + } + + break; + + default: + break; + } + +} +#endif + +void GPIO_driverInit(void) +{ + if((gGpioStatus & 0x1U) == 0) + { + +#ifdef PM_FEATURE_ENABLE + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_GPIO_MODULE, GPIO_enterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_GPIO_MODULE, GPIO_exitLowPowerStateRestore, NULL); +#endif + CLOCK_clockEnable(PCLK_GPIO); + + gGpioStatus = 0x1U; + + } + +} + +void GPIO_driverDeInit(void) +{ + gGpioStatus = 0; + + // disable clock + CLOCK_clockDisable(PCLK_GPIO); + +#ifdef PM_FEATURE_ENABLE + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_GPIO_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_GPIO_MODULE); +#endif +} + + +void GPIO_pinConfig(uint32_t port, uint16_t pin, const GpioPinConfig_t *config) +{ + ASSERT(port < GPIO_INSTANCE_NUM); + + uint16_t pinMask = 0x1U << pin; + GPIO_TypeDef *base = EIGEN_GPIO(port); + + GPIO_driverInit(); + + switch(config->pinDirection) + { + case GPIO_DIRECTION_INPUT: + + base->OUTENCLR = pinMask; + + GPIO_interruptConfig(port, pin, config->misc.interruptConfig); + + break; + case GPIO_DIRECTION_OUTPUT: + + GPIO_pinWrite(port, pinMask, ((uint16_t)config->misc.initOutput) << pin); + + base->OUTENSET = pinMask; + + break; + default: + break; + } + +} + +void GPIO_interruptConfig(uint32_t port, uint16_t pin, GpioInterruptConfig_e config) +{ + uint16_t pinMask = 0x1U << pin; + GPIO_TypeDef *base = EIGEN_GPIO(port); + + switch(config) + { + case GPIO_INTERRUPT_DISABLED: + + base->INTENCLR = pinMask; + + break; + case GPIO_INTERRUPT_LOW_LEVEL: + + base->INTPOLCLR = pinMask; + base->INTTYPECLR = pinMask; + base->INTENSET = pinMask; + + break; + case GPIO_INTERRUPT_HIGH_LEVEL: + + base->INTPOLSET = pinMask; + base->INTTYPECLR = pinMask; + base->INTENSET = pinMask; + + break; + case GPIO_INTERRUPT_FALLING_EDGE: + + base->INTPOLCLR = pinMask; + base->INTTYPESET = pinMask; + base->INTENSET = pinMask; + + break; + case GPIO_INTERRUPT_RISING_EDGE: + + base->INTPOLSET = pinMask; + base->INTTYPESET = pinMask; + base->INTENSET = pinMask; + + break; + default : + break; + } +} + +void GPIO_pinWrite(uint32_t port, uint16_t pinMask, uint16_t output) +{ + EIGEN_GPIO(port)->MASKLOWBYTE[pinMask & 0xFFU] = output; + EIGEN_GPIO(port)->MASKHIGHBYTE[pinMask >> 8U] = output; +} + +uint32_t GPIO_pinRead(uint32_t port, uint16_t pin) +{ + return (((EIGEN_GPIO(port)->DATA) >> pin) & 0x01U); +} + +uint16_t GPIO_getInterruptFlags(uint32_t port) +{ + return EIGEN_GPIO(port)->INTSTATUS; +} + +void GPIO_clearInterruptFlags(uint32_t port, uint16_t mask) +{ + EIGEN_GPIO(port)->INTSTATUS = mask; +} + +uint16_t GPIO_saveAndSetIrqMask(uint32_t port) +{ + uint16_t mask = EIGEN_GPIO(port)->INTENSET; + EIGEN_GPIO(port)->INTENCLR = 0xFFFFU; + return mask; +} + +void GPIO_restoreIrqMask(uint32_t port, uint16_t mask) +{ + EIGEN_GPIO(port)->INTENSET = mask; +} + diff --git a/PLAT/driver/chip/ec618/ap/src/i2s.c b/PLAT/driver/chip/ec618/ap/src/i2s.c new file mode 100644 index 0000000..1298a05 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/i2s.c @@ -0,0 +1,897 @@ + /**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: i2s.c + * Description: Audio use in EC618. The interface is similar with CMSIS Driver API V2.0. + * History: Rev1.0 2021-06-23 + * + ****************************************************************************/ +#include "i2s.h" +#include "slpman.h" + +////////////////////////////////////////////////////////////////////////////////////////////// +// I2S Setting field Start +// All the I2S's parameters that need user to set are all put here +////////////////////////////////////////////////////////////////////////////////////////////// +static DmaTransferConfig_t g_dmaTxConfig = +{ + NULL, + NULL, + DMA_FLOW_CONTROL_TARGET, + DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_TWO_BYTES, + DMA_BURST_8_BYTES, + 0 +}; + +static DmaTransferConfig_t g_dmaRxConfig = +{ + NULL, + NULL, + DMA_FLOW_CONTROL_SOURCE, + DMA_ADDRESS_INCREMENT_TARGET, + DMA_DATA_WIDTH_TWO_BYTES, + DMA_BURST_8_BYTES, + 0 +}; + + +#if (RTE_I2S0) +static PIN i2s0PinMCLK = {RTE_I2S0_MCLK_PAD_ADDR, RTE_I2S0_MCLK_FUNC}; +static PIN i2s0PinBCLK = {RTE_I2S0_BCLK_PAD_ADDR, RTE_I2S0_BCLK_FUNC}; +static PIN i2s0PinLRCK = {RTE_I2S0_LRCK_PAD_ADDR, RTE_I2S0_LRCK_FUNC}; +static PIN i2s0PinDin = {RTE_I2S0_DIN_PAD_ADDR, RTE_I2S0_DIN_FUNC}; +static PIN i2s0PinDout = {RTE_I2S0_DOUT_PAD_ADDR, RTE_I2S0_DOUT_FUNC}; +#elif (RTE_I2S1) +static PIN i2s1PinMCLK = {RTE_I2S1_MCLK_PAD_ADDR, RTE_I2S1_MCLK_FUNC}; +static PIN i2s1PinBCLK = {RTE_I2S1_BCLK_PAD_ADDR, RTE_I2S1_BCLK_FUNC}; +static PIN i2s1PinLRCK = {RTE_I2S1_LRCK_PAD_ADDR, RTE_I2S1_LRCK_FUNC}; +static PIN i2s1PinDin = {RTE_I2S1_DIN_PAD_ADDR, RTE_I2S1_DIN_FUNC}; +static PIN i2s1PinDout = {RTE_I2S1_DOUT_PAD_ADDR, RTE_I2S1_DOUT_FUNC}; +#endif + + +// Sample rate, fs, fracdiv part, integer part. Generate MClk accoding to the sample rate. +const uint32_t i2sSampleRateTbl[][4] = +{ + {SAMPLE_RATE_8K, 256, 0xCE0000, 0x31}, // 256fs, 8k + {SAMPLE_RATE_16K, 256, 0xE70000, 0x18}, // 256fs, 16k + {SAMPLE_RATE_32K, 256, 0x738000, 0x0C}, // 256fs, 32k + {SAMPLE_RATE_22_05K,256, 0x11D9B0, 0x12}, // 256fs, 22.05k + {SAMPLE_RATE_44_1K, 256, 0x08ECD8, 0x09}, // 256fs, 44.1k + {SAMPLE_RATE_48K, 256, 0x4D0000, 0x08}, // 256fs, 48k + {SAMPLE_RATE_96K, 256, 0x268000, 0x04}, // 256fs, 96k +}; + + +// Data Format +i2sDataFmt_t i2sDataFmt = +{ + .slaveModeEn = 0x1, // 0:Master; 1:Slave mode + .slotSize = 0xf, // Slot size + .wordSize = 0xf, // Real word size + .alignMode = 0, // 1: Right alignment; 0: Left alignment + .endianMode = 0x1, // 1: MSB; 0: LSB + .dataDly = 0, // Used by I2S format + .txPad = 0, // Tx padding + .rxSignExt = 0, // Rx sign external + .txPack = 0, // 0: not compress; 1: 1word; 2: 2word + .rxPack = 0, // 0: not compress; 1: 1word; 2: 2word + .txFifoEndianMode = 0, // I2s use or cspi use? + .rxFifoEndianMode = 0, // I2s use or cspi use? +}; + +// Slot Control +i2sSlotCtrl_t i2sSlotCtrl = +{ + .slotEn = 0x1, // Total 8 channels + .slotNum = 0x1 // For I2S, this value should be 1; For PCM, it can change +}; + +// BclkFs Control +i2sBclkFsCtrl_t i2sBclkFsCtrl = +{ + .bclkPolarity = 1, // 0: Rising edge send, falling edge sample; 1: falling edge send, rising edge sample + .fsPolarity = 0, // 0: rising edge start; 1: falling edge start + .fsWidth = 0xf // fsWidth = slotNum * slotSize +}; + +// I2S Control +i2sCtrl_t i2sCtrl = +{ + .i2sMode = 1, // 0: disable; 1: Only send; 2: Only receive; 3: Send and Receive +}; + +// DMA Control +i2sDmaCtrl_t i2sDmaCtrl = +{ + .rxDmaReqEn = 0, // rx dma enable + .txDmaReqEn = 1, // tx dma enable + .rxDmaTimeOutEn = 0, // rx dma timeout enable + .dmaWorkWaitCycle = 31, // dma wait cycle number + .rxDmaBurstSizeSub1 = 7, // rx dma burst size -1 + .txDmaBurstSizeSub1 = 7, // tx dma burst size -1 + .rxDmaThreadHold = 8, // rx dma threshold + .txDmaThreadHold = 8, // tx dma threshold + .rxFifoFlush = 0, // flush rx fifo + .txFifoFlush = 0 // flush tx fifo +}; + + +////////////////////////////////////////////////////////////////////////////////////////////// +// I2S Setting field End +////////////////////////////////////////////////////////////////////////////////////////////// +#if (RTE_I2S0) +static i2sInfo_t i2s0Info = {0}; +void i2s0DmaRxEvent(uint32_t event); +void i2s0DmaTxEvent(uint32_t event); +DmaDescriptor_t __ALIGNED(16) i2s0DmaTxDesc[I2S_DMA_TX_DESCRIPTOR_CHAIN_NUM]; +DmaDescriptor_t __ALIGNED(16) i2s0DmaRxDesc[I2S_DMA_RX_DESCRIPTOR_CHAIN_NUM]; + +#if (RTE_I2S0_IO_MODE == DMA_MODE) +static i2sDma_t i2s0Dma = +{ + DMA_INSTANCE_MP, + -1, + RTE_I2S0_DMA_TX_REQID, + i2s0DmaTxEvent, + i2s0DmaTxDesc, + + DMA_INSTANCE_MP, + -1, + RTE_I2S0_DMA_RX_REQID, + i2s0DmaRxEvent, + i2s0DmaRxDesc +}; +#endif + +static i2sResources_t i2s0Res = { + I2S0, + { + &i2s0PinMCLK, + &i2s0PinBCLK, + &i2s0PinLRCK, + &i2s0PinDin, + &i2s0PinDout, + }, +#if (RTE_I2S0_IO_MODE == DMA_MODE) + &i2s0Dma, +#else + NULL, +#endif + NULL, + &i2s0Info +}; +#endif + +#if (RTE_I2S1) + +static i2sInfo_t i2s1Info = {0}; +void i2s1DmaRxEvent(uint32_t event); +void i2s1DmaTxEvent(uint32_t event); +static DmaDescriptor_t __ALIGNED(16) i2s1DmaTxDesc[I2S_DMA_DESCRIPTOR_CHAIN_NUM]; +static DmaDescriptor_t __ALIGNED(16) i2s1DmaRxDesc[I2S_DMA_DESCRIPTOR_CHAIN_NUM]; + +static i2sDma_t i2s1Dma = +{ + DMA_INSTANCE_MP, + -1, + RTE_I2S1_DMA_TX_REQID, + i2s1DmaTxEvent, + &i2s1DmaTxDesc, + + DMA_INSTANCE_MP, + -1, + RTE_I2S1_DMA_RX_REQID, + i2s1DmaRxEvent, + &i2s1DmaRxDesc +}; + +static i2sResources_t i2s1Res = { + I2S1, + { + &i2s1PinMCLK, + &i2s1PinBCLK, + &i2s1PinLRCK, + &i2s1PinDin, + &i2s1PinDout, + }, +#if (RTE_I2S1_IO_MODE == DMA_MODE) + &i2s1Dma, +#else + NULL, +#endif + NULL, + &i2s1Info +}; +#endif + + +static I2S_TypeDef* const i2sInstance[I2S_INSTANCE_NUM] = {I2S0, I2S1}; + +static ClockId_e i2sClk[I2S_INSTANCE_NUM * 2] = +{ + PCLK_I2S0, + FCLK_I2S0, + PCLK_I2S1, + FCLK_I2S1 +}; + +static ClockResetId_e i2sRstClk[I2S_INSTANCE_NUM * 2] = +{ + RST_PCLK_I2S0, + RST_FCLK_I2S0, + RST_PCLK_I2S1, + RST_FCLK_I2S1 +}; + + +#ifdef PM_FEATURE_ENABLE + +/** \brief Internal used data structure */ +typedef struct +{ + bool isInited; /**< Whether spi has been initialized */ + struct + { + __IO uint32_t DFMT; /**< Data Format Register, offset: 0x0 */ + __IO uint32_t SLOTCTL; /**< Slot Control Register, offset: 0x4 */ + __IO uint32_t CLKCTL; /**< Clock Control Register, offset: 0x8 */ + __IO uint32_t DMACTL; /**< DMA Control Register, offset: 0xC */ + __IO uint32_t INTCTL; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t TIMEOUTCTL; /**< Timeout Control Register, offset: 0x14 */ + __IO uint32_t STAS; /**< Status Register, offset: 0x18 */ + __IO uint32_t RFIFO; /**< Rx Buffer Register, offset: 0x1c */ + __IO uint32_t TFIFO; /**< Tx Buffer Register, offset: 0x20 */ + __IO uint32_t I2SCTL; /**< I2S Control Register, offset: 0x28 */ + }regsBackup; +} i2sDataBase_t; + +static i2sDataBase_t i2sDataBase[I2S_INSTANCE_NUM] = {0}; +/** + \brief i2s initialization counter, for lower power callback register/de-register + */ +static uint32_t i2sInitCnt = 0; + +/** + \brief Bitmap of I2S working status, each instance is assigned 2 bits representing tx and rx status, + when all I2S instances are not working, we can vote to enter to low power state. + */ + +volatile uint32_t i2sWorkingStats = 0; + + +/** + \fn static void i2sEnterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, I2S hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void i2sEnterLpStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < I2S_INSTANCE_NUM; i++) + { + if(i2sDataBase[i].isInited == true) + { + i2sDataBase[i].regsBackup.DFMT = i2sInstance[i]->DFMT; + i2sDataBase[i].regsBackup.SLOTCTL = i2sInstance[i]->SLOTCTL; + i2sDataBase[i].regsBackup.CLKCTL = i2sInstance[i]->CLKCTL; + i2sDataBase[i].regsBackup.DMACTL = i2sInstance[i]->DMACTL; + i2sDataBase[i].regsBackup.INTCTL = i2sInstance[i]->INTCTL; + i2sDataBase[i].regsBackup.TIMEOUTCTL = i2sInstance[i]->TIMEOUTCTL; + i2sDataBase[i].regsBackup.STAS = i2sInstance[i]->STAS; + i2sDataBase[i].regsBackup.I2SCTL = i2sInstance[i]->I2SCTL; + } + } + break; + default: + break; + } +} + +/** + \fn static void i2sExitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, I2S hareware is repowered, we restore user's configurations + by aidding of the stored registers. + + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void i2sExitLpStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < I2S_INSTANCE_NUM; i++) + { + if(i2sDataBase[i].isInited == true) + { + CLOCK_clockEnable(i2sClk[i*2]); + CLOCK_clockEnable(i2sClk[i*2 + 1]); + + i2sInstance[i]->DFMT = i2sDataBase[i].regsBackup.DFMT; + i2sInstance[i]->SLOTCTL = i2sDataBase[i].regsBackup.SLOTCTL; + i2sInstance[i]->CLKCTL = i2sDataBase[i].regsBackup.CLKCTL; + i2sInstance[i]->DMACTL = i2sDataBase[i].regsBackup.DMACTL; + i2sInstance[i]->INTCTL = i2sDataBase[i].regsBackup.INTCTL; + i2sInstance[i]->TIMEOUTCTL = i2sDataBase[i].regsBackup.TIMEOUTCTL; + i2sInstance[i]->STAS = i2sDataBase[i].regsBackup.STAS; + i2sInstance[i]->I2SCTL = i2sDataBase[i].regsBackup.I2SCTL; + } + } + break; + + default: + break; + } +} + +#define LOCK_SLEEP(instance) \ + do \ + { \ + i2sWorkingStats |= (1U << instance); \ + slpManDrvVoteSleep(SLP_VOTE_I2S, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define CHECK_TO_UNLOCK_SLEEP(instance) \ + do \ + { \ + i2sWorkingStats &= ~(1U << instance); \ + if(i2sWorkingStats == 0) \ + slpManDrvVoteSleep(SLP_VOTE_I2S, SLP_SLP1_STATE); \ + } \ + while(0) +#endif + +static uint32_t i2sGetInstanceNum(i2sResources_t *i2s) +{ + return ((uint32_t)i2s->reg - (uint32_t)I2S0) >> 12U; +} + +int32_t i2sInit(i2sCbEvent_fn txCbEvent, i2sCbEvent_fn rxCbEvent, i2sResources_t *i2s) +{ + int32_t returnCode; + PadConfig_t config; + +#ifdef PM_FEATURE_ENABLE + uint32_t instance = i2sGetInstanceNum(i2s); + i2sDataBase[instance].isInited = true; +#endif + + // Initialize I2S PINS + PAD_getDefaultConfig(&config); + config.mux = i2s->pins.mclk->funcNum; + PAD_setPinConfig(i2s->pins.mclk->pinNum, &config); + config.mux = i2s->pins.bclk->funcNum; + PAD_setPinConfig(i2s->pins.bclk->pinNum, &config); + config.mux = i2s->pins.lrck->funcNum; + PAD_setPinConfig(i2s->pins.lrck->pinNum, &config); + config.mux = i2s->pins.din->funcNum; + PAD_setPinConfig(i2s->pins.din->pinNum, &config); + config.mux = i2s->pins.dout->funcNum; + PAD_setPinConfig(i2s->pins.dout->pinNum, &config); + + // Initialize I2S run-time resources + i2s->info->txCbEvent = txCbEvent; + i2s->info->rxCbEvent = rxCbEvent; + + // Configure DMA if necessary + if (i2s->dma) + { + // Tx config + DMA_init(i2s->dma->txInstance); + returnCode = DMA_openChannel(i2s->dma->txInstance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + i2s->dma->txCh = returnCode; + + DMA_setChannelRequestSource(i2s->dma->txInstance, i2s->dma->txCh, (DmaRequestSource_e)i2s->dma->txReq); + DMA_rigisterChannelCallback(i2s->dma->txInstance, i2s->dma->txCh, i2s->dma->txCb); + + // Rx config + DMA_init(i2s->dma->rxInstance); + returnCode = DMA_openChannel(i2s->dma->rxInstance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + i2s->dma->rxCh = returnCode; + + DMA_setChannelRequestSource(i2s->dma->rxInstance, i2s->dma->rxCh, (DmaRequestSource_e)i2s->dma->rxReq); + DMA_rigisterChannelCallback(i2s->dma->rxInstance, i2s->dma->rxCh, i2s->dma->rxCb); + } + +#ifdef PM_FEATURE_ENABLE + i2sInitCnt++; + + if(i2sInitCnt == 1U) + { + i2sWorkingStats = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_I2S_MODULE, i2sEnterLpStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_I2S_MODULE, i2sExitLpStateRestore, NULL); + } +#endif + + return ARM_DRIVER_OK; +} + + +int32_t i2sDeInit(i2sResources_t *i2s) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = i2sGetInstanceNum(i2s); + i2sDataBase[instance].isInited = false; + + i2sInitCnt--; + + if(i2sInitCnt == 0) + { + i2sWorkingStats = 0; + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_I2S_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_I2S_MODULE); + } +#endif + + return ARM_DRIVER_OK; +} + +int32_t i2sPowerCtrl(i2sPowerState_e state, i2sResources_t *i2s) +{ + uint32_t instance = i2sGetInstanceNum(i2s); + + switch (state) + { + case I2S_POWER_OFF: + if(i2s->dma) + { + DMA_stopChannel(i2s->dma->txInstance, i2s->dma->txCh, true); + } + + // Reset register values + if (instance == 0) + { + CLOCK_setClockSrc(FCLK_I2S0, FCLK_I2S0_SEL_26M); + GPR_swReset(RST_PCLK_I2S0); + } + else + { + CLOCK_setClockSrc(FCLK_I2S1, FCLK_I2S1_SEL_26M); + GPR_swReset(RST_PCLK_I2S1); + } + + // Disable I2S clock + CLOCK_clockDisable(i2sClk[instance*2]); + CLOCK_clockDisable(i2sClk[instance*2+1]); + + break; + + case I2S_POWER_FULL: + + // Enable I2S clock + CLOCK_clockEnable(i2sClk[instance*2]); // pclk + CLOCK_clockEnable(i2sClk[instance*2+1]); // fclk + + GPR_swReset(i2sRstClk[instance*2]); // pclk + GPR_swReset(i2sRstClk[instance*2+1]); // fclk + + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +int32_t i2sSend(const void *data, uint32_t chunkNum, i2sResources_t *i2s) +{ + uint32_t instance = i2sGetInstanceNum(i2s); + + if ((data == NULL) || (chunkNum == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + + // dma mode + if(i2s->dma) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + + // Configure tx DMA and start it + g_dmaTxConfig.sourceAddress = (void *)data; + g_dmaTxConfig.targetAddress = (void *)&(i2sInstance[instance]->TFIFO); + g_dmaTxConfig.totalLength = chunkNum; + DMA_buildDescriptorChain(i2s->dma->txDescriptor, &g_dmaTxConfig, I2S_DMA_TX_DESCRIPTOR_CHAIN_NUM, false/*true*/); + DMA_loadChannelDescriptorAndRun(i2s->dma->txInstance, i2s->dma->txCh, i2s->dma->txDescriptor); + } + // polling mode + else + { + for (int i = 0; i < chunkNum; i++) + { + // Flow control. Make sure TX have empty fifo + while (((16 - (i2s->reg->STAS & I2S_STATS_CTRL_TX_FIFO_LEVEL_Msk)) + >> I2S_STATS_CTRL_TX_FIFO_LEVEL_Pos) == 0){}; + + i2s->reg->TFIFO = *(uint32_t*)data; + } + } + + return ARM_DRIVER_OK; +} + + +int32_t i2sRecv(void *data, uint32_t chunkNum, i2sResources_t *i2s) +{ + uint32_t instance = i2sGetInstanceNum(i2s);; + + if ((data == NULL) || (chunkNum == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + + // dma mode + if(i2s->dma) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + + // Configure rx DMA and start it + g_dmaRxConfig.sourceAddress = (void *)&(i2sInstance[instance]->RFIFO); + g_dmaRxConfig.targetAddress = (void *)data; + g_dmaRxConfig.totalLength = chunkNum; + DMA_buildDescriptorChain(i2s->dma->rxDescriptor, &g_dmaRxConfig, I2S_DMA_RX_DESCRIPTOR_CHAIN_NUM, true); + DMA_loadChannelDescriptorAndRun(i2s->dma->rxInstance, i2s->dma->rxCh, i2s->dma->rxDescriptor); + } + // polling mode + else + { + for (int i = 0; i < chunkNum; i++) + { + while (((i2s->reg->STAS >> I2S_STATS_CTRL_RX_DAT_RDY_Pos) & 0x1) == 0); // Wait until RxFifo have data + *((uint32_t*)data + i) = i2s->reg->RFIFO; + } + } + + return ARM_DRIVER_OK; +} + + +/** + \fn static int32_t i2sSetBusSpeed(uint32_t bps, i2sResources_t *i2s) + \brief Set bus speed + \param[in] bps bus speed to set + \param[in] spi Pointer to SPI resources + \return \ref execution_status +*/ +static int32_t i2sSetSampleRate(uint32_t bps, i2sResources_t *i2s, i2sRole_e i2sRole) +{ + uint32_t instance = i2sGetInstanceNum(i2s); + + if (instance == 0) // i2s0 + { + CLOCK_clockEnable(FCLK_I2S0); + } + else // i2s1 + { + CLOCK_clockEnable(FCLK_I2S1); + } + + CLOCK_setClockSrc(CLK_CC, CLK_CC_SEL_204M); // Core clk selects 204M + + CLOCK_fracDivOutCLkEnable(FRACDIV0_OUT0); // Fracdiv0 out0 enable + CLOCK_setMclkSrc(MCLK0, MCLK_SRC_FRACDIV0_OUT0); // Choose Fracdiv0 out0 as MClk source + CLOCK_mclkEnable(MCLK0); // Mclk enable + CLOCK_setFracDivOutClkDiv(FRACDIV0_OUT0, 4); // First step to generate MClk clock. 4 div, from 408M -> 102M + + // need to add gpr api for fracdiv + int sampleRateIdx; + for (sampleRateIdx = 0; sampleRateIdx < sizeof(i2sSampleRateTbl) / sizeof(i2sSampleRateTbl[0]); sampleRateIdx++) + { + if (bps == i2sSampleRateTbl[sampleRateIdx][0]) + { + // Fracdiv clk selects 408M and set frac and integer clk + FracDivConfig_t fracdivCfg; + memset(&fracdivCfg, 0, sizeof(FracDivConfig_t)); + fracdivCfg.source = FRACDIC_ROOT_CLK_408M; + fracdivCfg.fracDiv0DivRatioInteger = i2sSampleRateTbl[sampleRateIdx][3]; + fracdivCfg.fracDiv0DivRatioFrac = i2sSampleRateTbl[sampleRateIdx][2]; + CLOCK_setFracDivConfig(&fracdivCfg); // Second step to generate MClk + } + } + + // I2S master mode need to genetate LRCLK by MCU + if (i2sRole == CODEC_SLAVE_MODE) // I2S controller act as master, codec is slave + { + CLOCK_fracDivOutCLkEnable(FRACDIV0_OUT1); // Enable fracdiv0 out1 + CLOCK_setBclkSrc(BCLK0, BCLK_SRC_FRACDIV0_OUT1); // Use fracdiv0 out1 to generate bclk + CLOCK_setFracDivOutClkDiv(FRACDIV0_OUT1, 8); // First step to generate BClk clock. 8 div, from 408M->51M + CLOCK_setBclkDiv(BCLK0, 4); // Second step to generate BClk clock. Bclk enable and divide by 4(256fs) + CLOCK_bclkEnable(BCLK0); // Enable bclk + } + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t i2sControl(uint32_t control, uint32_t arg, i2sRes_t *i2s) + \brief Control I2S Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \param[in] i2s Pointer to I2S resources + \return common \ref execution_status and driver specific \ref spi_execution_status +*/ +int32_t i2sControl(uint32_t control, uint32_t arg, i2sResources_t *i2s) +{ + uint32_t instance = i2sGetInstanceNum(i2s); + + switch(control & 0xFFFF) + { + // Set transport abort + case I2S_CTRL_TRANSABORT: + { + // If DMA mode, disable DMA channel + if(i2s->dma) + { + DMA_stopChannel(i2s->dma->txInstance, i2s->dma->txCh, true); + } + + break; + } + + case I2S_CTRL_SET_TOTAL_NUM: + { + i2s->info->totalNum = arg; + } + + // Set Bus Speed in bps; arg = value + case I2S_CTRL_SAMPLE_RATE_SLAVE: + { + if(i2sSetSampleRate(arg, i2s, CODEC_MASTER_MODE) != ARM_DRIVER_OK) + { + return ARM_DRIVER_ERROR; + } + break; + } + + case I2S_CTRL_SAMPLE_RATE_MASTER: + { + if(i2sSetSampleRate(arg, i2s, CODEC_SLAVE_MODE) != ARM_DRIVER_OK) + { + return ARM_DRIVER_ERROR; + } + break; + } + + // Set Data Format + case I2S_CTRL_DATA_FORMAT: + { + memcpy((void*)&(i2sInstance[instance]->DFMT), &i2sDataFmt, sizeof(i2sDataFmt_t)); + break; + } + + // Set Slot + case I2S_CTRL_SLOT_CTRL: + { + memcpy((void*)&(i2sInstance[instance]->SLOTCTL), &i2sSlotCtrl, sizeof(i2sSlotCtrl_t)); + break; + } + + // Set DMA Control + case I2S_CTRL_DMA_CTRL: + { + memcpy((void*)&(i2sInstance[instance]->DMACTL), &i2sDmaCtrl, sizeof(i2sDmaCtrl_t)); + break; + } + + // Set I2S Control + case I2S_CTRL_I2SCTL: + { + memcpy((void*)&(i2sInstance[instance]->I2SCTL), &i2sCtrl, sizeof(i2sCtrl_t)); + break; + } + + // Set Frame Info0 + case I2S_CTRL_BCLK_FS_CTRL: + { + memcpy((void*)&(i2sInstance[instance]->CLKCTL), &i2sBclkFsCtrl, sizeof(i2sBclkFsCtrl_t)); + break; + } + + // Start or stop audio play + case I2S_CTRL_START_STOP: + { + i2sInstance[instance]->I2SCTL = arg; // 0: disable i2s; 1: enable send; 2: enable recv; 3: enable send/recv + break; + } + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +void i2sDmaRxEvent(uint32_t event, i2sResources_t *i2s) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = i2sGetInstanceNum(i2s); +#endif + + switch(event) + { + case DMA_EVENT_END: + //DMA_stopChannel(i2s->dma->rxInstance, i2s->dma->rxCh, true); + //i2s->reg->I2SCTL &= ~I2S_CTL_MODE_Msk; + + if(i2s->info->rxCbEvent) + { + i2s->info->rxCbEvent(I2S_EVENT_TRANSFER_COMPLETE, 0); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + break; + + default: + break; + } +} + +void i2sDmaTxEvent(uint32_t event, i2sResources_t *i2s) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = i2sGetInstanceNum(i2s); +#endif + + switch(event) + { + case DMA_EVENT_END: +#if 0 // If you want to loop the audio, don't stop DMA here + DMA_stopChannel(i2s->dma->txInstance, i2s->dma->txCh, true); + i2s->info->status.busy = 0; + i2s->reg->I2SCTL &= ~I2S_CTL_MODE_Msk; +#endif + if(i2s->info->txCbEvent) + { + i2s->info->txCbEvent(I2S_EVENT_TRANSFER_COMPLETE, i2s->info->totalNum); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + break; + + default: + break; + } +} + +uint32_t i2sGetTotalCnt(i2sResources_t *i2s) +{ + return i2s->info->totalNum; +} + + +#if (RTE_I2S0) + +static int32_t i2s0Init(i2sCbEvent_fn txCbEvent, i2sCbEvent_fn rxCbEvent) +{ + return i2sInit(txCbEvent, rxCbEvent, &i2s0Res); +} +static int32_t i2s0Deinit(void) +{ + return i2sDeInit(&i2s0Res); +} +static int32_t i2s0PowerCtrl(i2sPowerState_e state) +{ + return i2sPowerCtrl(state, &i2s0Res); +} + +static int32_t i2s0Send(void *data, uint32_t num) +{ + return i2sSend(data, num, &i2s0Res); +} + +static int32_t i2s0Recv(void *data, uint32_t num) +{ + return i2sRecv(data, num, &i2s0Res); +} + +static int32_t i2s0Ctrl(uint32_t control, uint32_t arg) +{ + return i2sControl(control, arg, &i2s0Res); +} + +void i2s0DmaTxEvent(uint32_t event) +{ + i2sDmaTxEvent(event, &i2s0Res); +} + +void i2s0DmaRxEvent(uint32_t event) +{ + i2sDmaRxEvent(event, &i2s0Res); +} + +uint32_t i2s0GetTotalCnt(void) +{ + return i2sGetTotalCnt(&i2s0Res); +} + +// I2S0 Driver Control Block +i2sDrvInterface_t i2sDrvInterface0 = +{ + i2s0Init, + i2s0Deinit, + i2s0PowerCtrl, + i2s0Send, + i2s0Recv, + i2s0Ctrl, + i2s0GetTotalCnt, +}; +#endif + +#if (RTE_I2S1) +static int32_t i2s1Init(i2sCbEvent_fn txCbEvent, i2sCbEvent_fn rxCbEvent) +{ + return i2sInit(txCbEvent, rxCbEvent, &i2s1Res); +} +static int32_t i2s1Deinit(void) +{ + return i2sDeInit(&i2s1Res); +} +static int32_t i2s1PowerCtrl(i2sPowerState_e state) +{ + return i2sPowerCtrl(state, &i2s1Res); +} + +static int32_t i2s1Send(void *data, uint32_t num) +{ + return i2sSend(data, num, &i2s1Res); +} + +static int32_t i2s1Recv(void *data, uint32_t num) +{ + return i2sRecv(data, num, &i2s1Res); +} + +static int32_t i2s1Ctrl(uint32_t control, uint32_t arg) +{ + return i2sControl(control, arg, &i2s1Res); +} + +uint32_t i2s1GetTotalCnt(void) +{ + return i2sGetTotalCnt(&i2s1Res); +} + +void i2s1DmaRxEvent(uint32_t event) +{ + i2sDmaRxEvent(event, &i2s1Res); +} + +// I2S1 Driver Control Block +i2sDrvInterface_t i2sDrvInterface1 = +{ + i2s1Init, + i2s1Deinit, + i2s1PowerCtrl, + i2s1Send, + i2s1Recv, + i2s1Ctrl, + i2s1GetTotalCnt, +}; +#endif + diff --git a/PLAT/driver/chip/ec618/ap/src/kpc.c b/PLAT/driver/chip/ec618/ap/src/kpc.c new file mode 100644 index 0000000..47802ac --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/kpc.c @@ -0,0 +1,414 @@ +/**************************************************************************** + * + * Copy right: 2020-, Copyrigths of AirM2M Ltd. + * File name: kpc_ec616.c + * Description: EC618 kpc driver source file + * History: Rev1.0 2021-07-23 + * + ****************************************************************************/ + +#include "kpc.h" +#include "ic.h" +#include "clock.h" +#include "slpman.h" + +//#define KPC_DEBUG + +/** \brief Internal used data structure */ +typedef struct +{ + uint8_t isInited; /**< flag indicating intialized or not */ + + uint8_t scanState; /**< For key release detect */ + + uint8_t enableAutoRepeat; /**< autorepeat feature is enabled */ + + uint8_t padding0; + + uint32_t keyEnableMask; /**< Bitmap of enabled keys */ + uint32_t keyState; /**< Bitmap of key state, 0-release, 1-press */ + + struct + { + uint32_t repeatCount; /**< counter for autorepeat */ + uint8_t delay; /**< autorepeat event delay */ + uint8_t period; /**< autorepeat event period */ + uint16_t padding1; + } autoRepeat; + + struct + { + uint32_t DEBCTL; /**< Debounce Control Register */ + uint32_t KPCTL; /**< Keypad Control Register */ + uint32_t DICTL; /**< Direct Input Control Register */ + uint32_t KPENCTL; /**< Keypad Enable Register */ + uint32_t DIENCTL; /**< Direct Input Enable Register */ + } configRegisters; + + kpc_callback_t eventCallback; /**< Callback function passed in by application */ +} KpcDataBase_t; + +static KpcDataBase_t gKpcDataBase = {0}; + + +#ifdef PM_FEATURE_ENABLE +/** + \fn void KPC_enterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Backup KPC configurations before sleep. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +void KPC_enterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + switch(state) + { + case SLPMAN_SLEEP1_STATE: + + if(gKpcDataBase.isInited == 1) + { + gKpcDataBase.configRegisters.DEBCTL = KPC->DEBCTL; + gKpcDataBase.configRegisters.KPCTL = KPC->KPCTL; + gKpcDataBase.configRegisters.DICTL = KPC->DICTL; + gKpcDataBase.configRegisters.KPENCTL = KPC->KPENCTL; + gKpcDataBase.configRegisters.DIENCTL = KPC->DIENCTL; + } + + break; + + default: + break; + } + +} + +/** + \fn void KPC_exitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore KPC configurations after exit from sleep. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +void KPC_exitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + switch(state) + { + case SLPMAN_SLEEP1_STATE: + + if(gKpcDataBase.isInited == 1) + { + KPC->DEBCTL = gKpcDataBase.configRegisters.DEBCTL; + KPC->KPCTL = gKpcDataBase.configRegisters.KPCTL; + KPC->DICTL = gKpcDataBase.configRegisters.DICTL; + KPC->KPENCTL = gKpcDataBase.configRegisters.KPENCTL; + KPC->DIENCTL = gKpcDataBase.configRegisters.DIENCTL; + } + + break; + + default: + break; + } + +} +#endif + + +static __FORCEINLINE uint32_t KPC_findFirstSet(uint32_t value) +{ + return __CLZ(__RBIT(value)); +} + +/** + construct key enable bitmap + + 24 20 19 15 14 10 9 5 4 0 + +------------------+------------------+------------------+------------------+------------------+ + | row 4, col[4:0] | row 3, col[4:0] | row 2, col[4:0] | row 1,col[4:0] | row 0, col[4:0] | + +------------------+------------------+------------------+------------------+------------------+ + + */ +static void KPC_setKeyMask(uint32_t rowMask, uint32_t colMask, uint32_t* keyEnableMask, uint32_t* rowMsb, uint32_t* rowCounts) +{ + uint32_t keyMask = 0; + uint32_t rowIndex = 0; + uint32_t cnt = 0; + + // Max 5x5 matrix keypad + rowMask &= 0x1f; + colMask &= 0x1f; + + while(rowMask) + { + rowIndex = KPC_findFirstSet(rowMask); + keyMask |= (colMask << (rowIndex * 5)); + rowMask &= (rowMask - 1); + cnt++; + } + + *keyEnableMask = keyMask; + *rowMsb = rowIndex; + *rowCounts = cnt; +} + +static void KPC_eventReport(void) +{ + uint32_t lsb, keyScanResult, keyScanResultBackup, changed, report = 0; + + KpcReportEvent_t event; + + // Get current key scan result + keyScanResult = KPC->KPSTAT & gKpcDataBase.keyEnableMask; + + keyScanResultBackup = keyScanResult; + + // Find out changed key + changed = keyScanResult ^ gKpcDataBase.keyState; + +#ifdef KPC_DEBUG + printf("report: [%x]-[%x]-[%x]\r\n", keyScanResult, gKpcDataBase.keyState, changed); +#endif + + // First to handle key release + if(changed) + { + lsb = KPC_findFirstSet(changed); + + // Check key released during two consecutive rounds of scan + if((keyScanResultBackup & ( 1 << lsb)) == 0) + { + event.row = lsb / 5; + event.column = lsb % 5; + event.value = KPC_REPORT_KEY_RELEASE; + + gKpcDataBase.autoRepeat.repeatCount = 0; + + if(gKpcDataBase.eventCallback) + { + gKpcDataBase.eventCallback(event); + } + + } + } + + // Check key press + if(keyScanResult) + { + lsb = KPC_findFirstSet(keyScanResult); + + // repeat key? + if((gKpcDataBase.keyState & (1 << lsb)) && (gKpcDataBase.enableAutoRepeat == 1)) + { + gKpcDataBase.autoRepeat.repeatCount++; + + if((gKpcDataBase.autoRepeat.repeatCount >= gKpcDataBase.autoRepeat.delay) && ((gKpcDataBase.autoRepeat.repeatCount - gKpcDataBase.autoRepeat.delay) % gKpcDataBase.autoRepeat.period == 0)) + { + event.row = lsb / 5; + event.column = lsb % 5; + event.value = KPC_REPORT_KEY_REPEAT; + report = 1; + } + } + else + { + event.row = lsb / 5; + event.column = lsb % 5; + event.value = KPC_REPORT_KEY_PRESS; + gKpcDataBase.autoRepeat.repeatCount = 0; + report = 1; + } + + if(gKpcDataBase.eventCallback && report) + { + gKpcDataBase.eventCallback(event); + } + } + + // save current result + gKpcDataBase.keyState = keyScanResultBackup; +} + +static void KPC_keyPadModeIsr(void) +{ + KPC_eventReport(); + + // If any key is pressed, enable direct input interrupt which works as a periodic timer for key release detect purpose + KPC->DIENCTL = KPC_DIENCTL_ENABLE_Msk; + KPC->KPENCTL = KPC_KPENCTL_ENABLE_Msk; + + gKpcDataBase.scanState = 1; // Indicating at least one key is pressed + +} + +// Enter at the end of one round of scan period +static void KPC_directInputModeIsr(void) +{ + KPC->CLRCTL = KPC_CLRCTL_INPUT_INT_CLR_Msk; + + // Check if all keys are released + if((KPC->KPSTAT == 0) && (gKpcDataBase.scanState == 2)) + { + KPC->DIENCTL = 0; + gKpcDataBase.scanState = 0; + +#ifdef KPC_DEBUG + printf("release,%x\r\n", KPC->DISTAT); +#endif + KPC_eventReport(); + } + + gKpcDataBase.scanState = 2; + +} + +void KPC_getDefaultConfig(KpcConfig_t *config) +{ + ASSERT(config); + + config->debounceConfig.debounceClkDivRatio = KPC_DEBOUNCE_CLK_DIV_RATIO_16384; + config->debounceConfig.debounceWidth = KPC_DEBOUNCE_WIDTH_7_CYCLES; + + config->validRowMask = KPC_ROW_ALL; + config->validColumnMask = KPC_COLUMN_ALL; + + config->scanPolarity = KPC_SCAN_POLARITY_0; + config->scanDivRatio = KPC_SCAN_DIV_RATIO_16; + + config->autoRepeat.enable = 1; + config->autoRepeat.delay = 10; + config->autoRepeat.period = 1; +} + +int32_t KPC_init(const KpcConfig_t *config, kpc_callback_t callback) +{ + ASSERT(config); + + uint32_t mask, validRowCounts, msbOfValidRows; + + mask = SaveAndSetIRQMask(); + + // Initialization + if(gKpcDataBase.isInited == 0) + { + CLOCK_setClockSrc(FCLK_KPC, FCLK_KPC_SEL_26M); + + CLOCK_clockEnable(FCLK_KPC); + CLOCK_clockEnable(PCLK_KPC); + + GPR_swResetModule(RESET_VECTOR_PTR(KPC_RESET_VECTOR)); + + // enable KPC IRQ + XIC_SetVector(PXIC0_KPC_DIRECT_IRQn, KPC_directInputModeIsr); + XIC_EnableIRQ(PXIC0_KPC_DIRECT_IRQn); + + XIC_SetVector(PXIC0_KPC_KEYPAD_IRQn, KPC_keyPadModeIsr); + XIC_EnableIRQ(PXIC0_KPC_KEYPAD_IRQn); + + } + else + { + RestoreIRQMask(mask); + return ARM_DRIVER_OK; + } + + RestoreIRQMask(mask); + + KPC_setKeyMask(config->validRowMask, config->validColumnMask, &gKpcDataBase.keyEnableMask, &msbOfValidRows, &validRowCounts); + + if(validRowCounts < 2) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + KPC->DEBCTL = EIGEN_VAL2FLD(KPC_DEBCTL_DEBOUNCER_DEPTH, config->debounceConfig.debounceWidth) | \ + EIGEN_VAL2FLD(KPC_DEBCTL_DEBOUNCER_TO0_THRD, config->debounceConfig.debounceWidth) | \ + EIGEN_VAL2FLD(KPC_DEBCTL_DEBOUNCER_TO1_THRD, config->debounceConfig.debounceWidth) | \ + EIGEN_VAL2FLD(KPC_DEBCTL_DEBOUNCER_TO_MCLK_RATIO, config->debounceConfig.debounceClkDivRatio); + + KPC->KPCTL = EIGEN_VAL2FLD(KPC_KPCTL_POLARITY, config->scanPolarity) | \ + EIGEN_VAL2FLD(KPC_KPCTL_ROW_VLD_BITMAP, config->validRowMask & 0x1FU) | \ + EIGEN_VAL2FLD(KPC_KPCTL_COL_VLD_BITMAP, config->validColumnMask & 0x1FU) | \ + EIGEN_VAL2FLD(KPC_KPCTL_SCAN_TO_DEBOUNCE_RATIO, config->scanDivRatio); + + // Enable rising/falling edge interrupt of ending row for key release detect + if(config->scanPolarity == KPC_SCAN_POLARITY_0) + { + KPC->DICTL = EIGEN_VAL2FLD(KPC_DICTL_INT_EN, 1 << (msbOfValidRows + 5)) | EIGEN_VAL2FLD(KPC_DICTL_INT_MODE, 0x1); + } + else + { + KPC->DICTL = EIGEN_VAL2FLD(KPC_DICTL_INT_EN, 1 << (msbOfValidRows + 5)) | EIGEN_VAL2FLD(KPC_DICTL_INT_MODE, 0x2); + } + + KPC->AUTOCG = KPC_AUTOCG_ENABLE_Msk; + + gKpcDataBase.eventCallback = callback; + + gKpcDataBase.enableAutoRepeat = config->autoRepeat.enable; + gKpcDataBase.autoRepeat.delay = config->autoRepeat.delay; + gKpcDataBase.autoRepeat.period = config->autoRepeat.period; + +#ifdef PM_FEATURE_ENABLE + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_KPC_MODULE, KPC_enterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_KPC_MODULE, KPC_exitLowPowerStateRestore, NULL); +#endif + + gKpcDataBase.isInited = 1; + + return ARM_DRIVER_OK; +} + +void KPC_deInit(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + if(gKpcDataBase.isInited == 1) + { + KPC_stopScan(); + + // disable clock + CLOCK_clockDisable(FCLK_KPC); + CLOCK_clockDisable(PCLK_KPC); + + XIC_DisableIRQ(PXIC0_KPC_DIRECT_IRQn); + XIC_DisableIRQ(PXIC0_KPC_KEYPAD_IRQn); + XIC_ClearPendingIRQ(PXIC0_KPC_DIRECT_IRQn); + XIC_ClearPendingIRQ(PXIC0_KPC_KEYPAD_IRQn); + +#ifdef PM_FEATURE_ENABLE + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_KPC_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_KPC_MODULE); +#endif + + gKpcDataBase.isInited = 0; + } + + RestoreIRQMask(mask); +} + +void KPC_startScan(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + if(gKpcDataBase.isInited == 1) + { + KPC->KPENCTL = KPC_KPENCTL_ENABLE_Msk; + } + + RestoreIRQMask(mask); +} + +void KPC_stopScan(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + if(gKpcDataBase.isInited == 1) + { + KPC->DIENCTL = 0; + KPC->CLRCTL = KPC_CLRCTL_INPUT_INT_CLR_Msk; + KPC->DICTL = 0; + } + + RestoreIRQMask(mask); + +} + + diff --git a/PLAT/driver/chip/ec618/ap/src/oneWire.c b/PLAT/driver/chip/ec618/ap/src/oneWire.c new file mode 100644 index 0000000..4df5890 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/oneWire.c @@ -0,0 +1,420 @@ +/**************************************************************************** + * + * Copy right: 2020-, Copyrigths of AirM2M Ltd. + * File name: oneWire.c + * Description: EC618 one wire bus driver source file + * History: Rev1.0 2020-12-17 + * + ****************************************************************************/ +#include "ec618.h" +#include "bsp.h" +#include "oneWire.h" +#include "hal_misc.h" + +extern void delay_us(uint32_t us); + + +#if OW_DEBUG_EN +#define OW_DEBUG(...) printf(__VA_ARGS__) +#else +#define OW_DEBUG(...) +#endif + +#define OW_IRQ_MODE 1 + +static volatile OwStats_e owStats = OW_IDLE; + +#define OW_PAD_ADDR (17) //(19)->gpio4 (17)->gpio2 (48)->gpio28 (22)->gpio7 +#define OW_PAD_FUNC PAD_MUX_ALT4 //PAD_MUX_ALT3 PAD_MUX_ALT4 PAD_MUX_ALT4 PAD_MUX_ALT4 + + +uint8_t *readBuf = NULL; + +#if (OW_IRQ_MODE == 1) +void owIrqHandler(void); +#else + int A, B, C, D, E, F, G, H, I, J; +#endif + +void owSetMode(OwModeSel_e mode) +{ + if (mode == STANDARD) + { +#if (OW_IRQ_MODE == 1) +#if 0 + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_SEND_DIV10, 50); + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_WAIT_DIV10, 50); + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_RDDLY_MIN, 15); + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_RDDLY_MAX_DIV10, 10); + + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_RECO, 2); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_SLOT_DIV10, 7); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_START, 1); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_WRDLY, 14); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_RDDLY, 11); +#endif +#else + OW->ECR |= OW_ECR_RXD_MJR_Msk; + + A = 2; // 6us + B = 12; // 64us + C = 16; // 60us + D = 1; // 10us + E = 5; // 9us + F = 28; // 55us + G = 0; + H = 120;// 480us + I = 35; // 70us + J = 150;// 410us +#endif + } + else + { +#if (OW_IRQ_MODE == 1) + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_SEND_DIV10, 50); + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_WAIT_DIV10, 50); + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_RDDLY_MIN, 15); + OW->RTCR = EIGEN_VAL2FLD(OW_RTCR_RESET_RDDLY_MAX_DIV10, 10); + + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_RECO, 2); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_SLOT_DIV10, 7); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_START, 1); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_WRDLY, 14); + OW->ATCR = EIGEN_VAL2FLD(OW_ATCR_WRRD_RDDLY, 11); +#else + +#endif + } +} + +#if (OW_IRQ_MODE != 1) +void write(uint8_t val) +{ + if (val == 1) + { + OW->IOR |= OW_IOR_IO_SWOEN_Msk; + OW->IOR |= OW_IOR_IO_SWOUT_Msk; + } + else + { + OW->IOR |= OW_IOR_IO_SWOEN_Msk; + OW->IOR &= ~OW_IOR_IO_SWOUT_Msk; + } +} + +uint8_t read() +{ + uint8_t retData, rmjData; + + OW->IOR &= ~OW_IOR_IO_SWOEN_Msk; + rmjData = EIGEN_FLD2VAL(OW_ECR_RXD_MJR, OW->ECR); + + if (rmjData > 0) + { + retData = EIGEN_FLD2VAL(OW_IOR_IO_SWIN_SYNC, OW->IOR); + } + else + { + retData = EIGEN_FLD2VAL(OW_IOR_IO_SWIN, OW->IOR); + } + + return retData; +} +#endif + + + +void owInit() +{ + GPR_clockEnable(PCLK_ONEW); + + // configure onew pins + PadConfig_t padConfig; + PAD_getDefaultConfig(&padConfig); + padConfig.mux = OW_PAD_FUNC; + PAD_setPinConfig(OW_PAD_ADDR, &padConfig); + +#if (OW_IRQ_MODE == 1) + OW->IOR &= ~OW_IOR_IO_SWMODE_Msk; + XIC_SetVector(PXIC0_ONEW_IRQn, owIrqHandler); + XIC_EnableIRQ(PXIC0_ONEW_IRQn); +#else + OW->IOR |= OW_IOR_IO_SWMODE_Msk; +#endif + + OW->ECR |= OW_ECR_ENABLE_Msk; // enable onewire +} + +void owDeInit() +{ +#if (OW_IRQ_MODE == 1) + XIC_DisableIRQ(PXIC0_ONEW_IRQn); +#endif + + GPR_clockDisable(PCLK_ONEW); +} + + +#if (OW_IRQ_MODE == 1) +volatile uint32_t irqNo; +volatile uint16_t count = 0; +void owIrqHandler() +{ + ++count; + irqNo = OW->IIR; + + // Disable ONEW IRQ + XIC_DisableIRQ(PXIC0_ONEW_IRQn); + + // Clear pending ONEW interrupts + XIC_ClearPendingIRQ(PXIC0_ONEW_IRQn); + + if ((OW->IIR & OW_IIR_INT_RESET_PD_Msk) && ((OW->IIR & OW_IIR_INT_RESET_Msk)!=OW_IIR_INT_RESET_Msk)) + { + OW->IER &= ~OW_IER_INTEN_RESET_PD_Msk; + + owStats |= OW_RESET_SUCCESS; + + OW->IIR |= OW_IIR_INT_CLR_Msk; + } + else if ((OW->IIR & OW_IIR_INT_RESET_Msk) && (OW->IIR & OW_IIR_INT_RESET_PD_Msk)) + { + if (OW->IIR & OW_IIR_RESET_PD_RES_Msk) + { + owStats |= OW_RESETPD_SUCCESS; + } + else + { + owStats &= ~OW_RESETPD_SUCCESS; + } + + OW->IIR |= OW_IIR_INT_CLR_Msk; + OW->IER &= ~OW_IER_INTEN_RESET_PD_Msk; + } + else if (OW->IIR & OW_IIR_INT_WRITE_Msk) + { + if (OW->IIR & OW_IIR_INT_WRITE_Msk) + { + owStats |= OW_WRITE_SUCCESS; + } + else + { + owStats &= ~OW_WRITE_SUCCESS; + } + + OW->IIR |= OW_IIR_INT_CLR_Msk; + OW->IER &= ~OW_IER_INTEN_WRITE_Msk; + } + else if (OW->IIR & OW_IIR_INT_READ_Msk) + { + *readBuf = OW->RBR; + + if (OW->IIR & OW_IIR_INT_READ_Msk) + { + owStats |= OW_READ_SUCCESS; + } + else + { + owStats &= ~OW_READ_SUCCESS; + } + + OW->IIR |= OW_IIR_INT_CLR_Msk; + OW->IER &= ~OW_IER_INTEN_READ_Msk; + } + + OW->OCR |= OW_OCR_CMD_FLUSH_Msk; + + XIC_EnableIRQ(PXIC0_ONEW_IRQn); +} +#endif + + +int32_t owReset() +{ +#if (OW_IRQ_MODE == 1) + OW->IER |= OW_IER_INTEN_RESET_PD_Msk; + OW->IER |= OW_IER_INTEN_RESET_Msk; + OW->OCR |= OW_OCR_CMD_RESET_Msk; + while ((owStats & OW_RESET_SUCCESS) != OW_RESET_SUCCESS); + + owStats &= ~OW_RESET_SUCCESS; + +#else + +#endif + return OWDRV_OK; +} +int32_t owResetPd() +{ +#if (OW_IRQ_MODE == 1) + OW->IER |= OW_IER_INTEN_RESET_Msk; + delay_us(20); // wait until former irq finish + OW->OCR |= OW_OCR_CMD_RESET_Msk; + + while ((owStats & OW_RESETPD_SUCCESS) != OW_RESETPD_SUCCESS); + owStats &= ~OW_RESETPD_SUCCESS; + + return OWDRV_OK; +#else + delay_us(50); + //owDelay(G); + write(0); + delay_us(H); + write(1); + delay_us(I); + int ret = read(); + delay_us(J); + if (ret == 1) + { + owStats |= OW_RESETPD_SUCCESS; + return OWDRV_OK; + } + else + { + owStats &= ~OW_RESETPD_SUCCESS; + return OWDRV_RESETPD_ERR; + } +#endif +} + +int32_t owWriteBit(uint8_t data) +{ +#if (OW_IRQ_MODE == 1) + OW->DFR &= ~OW_DFR_MODE_BYTE_Msk; + OW->TBR = data; + OW->IER |= OW_IER_INTEN_WRITE_Msk; + OW->OCR |= OW_OCR_CMD_WRITE_Msk; + + while ((owStats & OW_WRITE_SUCCESS) != OW_WRITE_SUCCESS); + owStats &= ~OW_WRITE_SUCCESS; +#else + if (data == 1) + { + write(0); + delay_us(A); + write(1); + delay_us(B); + } + else + { + write(0); + delay_us(C); + write(1); + delay_us(D); + } +#endif + + return OWDRV_OK; +} + +int32_t owReadBit(uint8_t * dataRead) +{ + if (dataRead != NULL) + { + readBuf = dataRead; + } + +#if (OW_IRQ_MODE == 1) + OW->DFR &= ~OW_DFR_MODE_BYTE_Msk; + OW->IER |= OW_IER_INTEN_READ_Msk; + OW->OCR |= OW_OCR_CMD_READ_Msk; + + while ((owStats & OW_READ_SUCCESS) != OW_READ_SUCCESS); + owStats &= ~OW_READ_SUCCESS; +#else + write(0); + delay_us(1); + write(1); + delay_us(2); + *dataRead = read(); + delay_us(14); +#endif + + return OWDRV_OK; +} + +int32_t owWriteByte(uint8_t data) +{ +#if (OW_IRQ_MODE == 1) + OW->DFR |= OW_DFR_MODE_BYTE_Msk; + OW->TBR = data; + OW->IER |= OW_IER_INTEN_WRITE_Msk; + OW->OCR |= OW_OCR_CMD_WRITE_Msk; + + while ((owStats & OW_WRITE_SUCCESS) != OW_WRITE_SUCCESS); + owStats &= ~OW_WRITE_SUCCESS; +#else + for (int i=0; i<8; i++) + { + owWriteBit(data & 0x01); + data >>= 1; + } +#endif + + return OWDRV_OK; +} + +int32_t owReadByte(uint8_t * dataRead) +{ + if (dataRead != NULL) + { + readBuf = dataRead; + } + +#if (OW_IRQ_MODE == 1) + OW->DFR |= OW_DFR_MODE_BYTE_Msk; + + OW->IER |= OW_IER_INTEN_READ_Msk; + OW->OCR |= OW_OCR_CMD_READ_Msk; + + while ((owStats & OW_READ_SUCCESS) != OW_READ_SUCCESS); + + owStats &= ~OW_READ_SUCCESS; +#else + uint8_t result=0; + uint8_t readBitVal[8]; + memset(readBitVal, 0, 8); + + for (int i=0; i<8; i++) + { + result >>= 1; + owReadBit(readBitVal+i); + + if (readBitVal[i] == 1) + { + result |= 0x80; + } + } + *dataRead = result; +#endif + + return OWDRV_OK; +} + +int32_t owTouchByte(uint8_t data) +{ + int32_t result = 0; + + for (uint8_t i=0; i<8; i++) + { + result >>= 1; + + // if sending a '1' then read a bit, else write a '0' + if (data & 0x01) + { + if (owReadBit(NULL)) + { + result |= 0x80; + } + } + else + { + owWriteBit(0); + } + + data >>= 1; + } + + return result; +} + diff --git a/PLAT/driver/chip/ec618/ap/src/pad.c b/PLAT/driver/chip/ec618/ap/src/pad.c new file mode 100644 index 0000000..c1ca4f3 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/pad.c @@ -0,0 +1,170 @@ + /**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: pad.c + * Description: EC618 pad driver source file + * History: Rev1.0 2018-11-14 + * + ****************************************************************************/ + +#include "pad.h" +#include "clock.h" +#include "slpman.h" + +#ifdef PM_FEATURE_ENABLE + +static uint32_t gPadBackupRegs[PAD_ADDR_MAX_NUM] = {0}; + +/** + \fn void PAD_enterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Backup pad configurations before sleep. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +void PAD_enterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + GPR_clockEnable(PCLK_PAD); + + for(i = 0; i < PAD_ADDR_MAX_NUM; i++) + { + gPadBackupRegs[i] = PAD->PCR[i]; + } + + GPR_clockDisable(PCLK_PAD); + + break; + default: + break; + } + +} + +/** + \fn void PAD_exitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore PAD configurations after exit from sleep. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +void PAD_exitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + GPR_clockEnable(PCLK_PAD); + + for(i = 0; i < PAD_ADDR_MAX_NUM; i++) + { + PAD->PCR[i] = gPadBackupRegs[i]; + } + + GPR_clockDisable(PCLK_PAD); + + break; + + default: + break; + } + +} +#endif + +void PAD_driverInit(void) +{ +#ifdef PM_FEATURE_ENABLE + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_PAD_MODULE, PAD_enterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_PAD_MODULE, PAD_exitLowPowerStateRestore, NULL); +#endif +} + +void PAD_driverDeInit(void) +{ +#ifdef PM_FEATURE_ENABLE + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_PAD_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_PAD_MODULE); +#endif +} + + +void PAD_getDefaultConfig(PadConfig_t *config) +{ + ASSERT(config); + + config->mux = PAD_MUX_ALT0; + config->inputBufferEnable = PAD_INPUT_BUFFER_DISABLE; + config->pullSelect = PAD_PULL_AUTO; + config->pullUpEnable = PAD_PULL_UP_DISABLE; + config->pullDownEnable = PAD_PULL_DOWN_DISABLE; +} + +void PAD_setPinConfig(uint32_t paddr, const PadConfig_t *config) +{ + ASSERT(config); + ASSERT(paddr < PAD_ADDR_MAX_NUM); + + CLOCK_clockEnable(PCLK_PAD); + PAD->PCR[paddr] = *((const uint32_t *)config); + CLOCK_clockDisable(PCLK_PAD); +} + +void PAD_setPinMux(uint32_t paddr, PadMux_e mux) +{ + ASSERT(paddr < PAD_ADDR_MAX_NUM); + + CLOCK_clockEnable(PCLK_PAD); + PAD->PCR[paddr] = (PAD->PCR[paddr] & ~PAD_PCR_MUX_Msk) | EIGEN_VAL2FLD(PAD_PCR_MUX, mux); + CLOCK_clockDisable(PCLK_PAD); + +} + +void PAD_enablePinInputBuffer(uint32_t paddr, bool enable) +{ + ASSERT(paddr < PAD_ADDR_MAX_NUM); + + CLOCK_clockEnable(PCLK_PAD); + + if (enable == true) + { + PAD->PCR[paddr] |= PAD_PCR_INPUT_BUFFER_ENABLE_Msk; + } + else + { + PAD->PCR[paddr] &= ~PAD_PCR_INPUT_BUFFER_ENABLE_Msk; + } + + CLOCK_clockDisable(PCLK_PAD); +} + +void PAD_setPinPullConfig(uint32_t paddr, PadPullConfig_e config) +{ + ASSERT(paddr < PAD_ADDR_MAX_NUM); + + CLOCK_clockEnable(PCLK_PAD); + + switch(config) + { + case PAD_INTERNAL_PULL_UP: + PAD->PCR[paddr] = (PAD->PCR[paddr] & ~PAD_PCR_PULL_DOWN_ENABLE_Msk) | PAD_PCR_PULL_UP_ENABLE_Msk | PAD_PCR_PULL_SELECT_Msk; + break; + case PAD_INTERNAL_PULL_DOWN: + PAD->PCR[paddr] = (PAD->PCR[paddr] & ~PAD_PCR_PULL_UP_ENABLE_Msk) | PAD_PCR_PULL_DOWN_ENABLE_Msk | PAD_PCR_PULL_SELECT_Msk; + break; + case PAD_AUTO_PULL: + PAD->PCR[paddr] = (PAD->PCR[paddr] & ~PAD_PCR_PULL_SELECT_Msk); + break; + default: + break; + } + + CLOCK_clockDisable(PCLK_PAD); + +} + diff --git a/PLAT/driver/chip/ec618/ap/src/timer.c b/PLAT/driver/chip/ec618/ap/src/timer.c new file mode 100644 index 0000000..59b9b78 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/timer.c @@ -0,0 +1,509 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: timer.c + * Description: EC618 timer driver source file + * History: Rev1.0 2018-07-18 + * + ****************************************************************************/ + +#include "timer.h" +#include "clock.h" +#include "slpman.h" +#include DEBUG_LOG_HEADER_FILE + +#define EIGEN_TIMER(n) ((TIMER_TypeDef *) (AP_TIMER0_BASE_ADDR + 0x1000*n)) + +#ifdef PM_FEATURE_ENABLE + +/** \brief Internal used data structure */ +typedef struct +{ + bool isInited; /**< Whether timer has been initialized */ + struct + { + uint32_t TCTLR; /**< Timer Control Register */ + uint32_t TIVR; /**< Timer Init Value Register */ + uint32_t TMR[3]; /**< Timer Match N Register */ + } backupRegisters; /**< Backup registers for low power restore */ +} TimerDatabase_t; + +static bool gIsTimerDriverInited = false; + +static TimerDatabase_t gTimerDataBase[TIMER_INSTANCE_NUM]; + +#endif + +static ClockId_e gTimerClocks[TIMER_INSTANCE_NUM*2] = {PCLK_TIMER0, FCLK_TIMER0, + PCLK_TIMER1, FCLK_TIMER1, + PCLK_TIMER2, FCLK_TIMER2, + PCLK_TIMER3, FCLK_TIMER3, + PCLK_TIMER4, FCLK_TIMER4, + PCLK_TIMER5, FCLK_TIMER5 + }; + +#ifdef PM_FEATURE_ENABLE + +/** + \brief Bitmap of TIMER working status, + when all TIMER instances are not working, we can vote to enter to low power state. + */ +static uint32_t gTimerWorkingStatus; + +/** + \fn static void TIMER_enterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, TIMER hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void TIMER_enterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < TIMER_INSTANCE_NUM; i++) + { + if(gTimerDataBase[i].isInited == true) + { + gTimerDataBase[i].backupRegisters.TCTLR = EIGEN_TIMER(i)->TCTLR; + gTimerDataBase[i].backupRegisters.TIVR = EIGEN_TIMER(i)->TIVR; + gTimerDataBase[i].backupRegisters.TMR[0] = EIGEN_TIMER(i)->TMR[0]; + gTimerDataBase[i].backupRegisters.TMR[1] = EIGEN_TIMER(i)->TMR[1]; + gTimerDataBase[i].backupRegisters.TMR[2] = EIGEN_TIMER(i)->TMR[2]; + } + } + break; + default: + break; + } + +} + +/** + \fn static void TIMER_exitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, TIMER hareware is repowered, we restore user's configurations + by aidding of the stored registers. + + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + + */ +static void TIMER_exitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < TIMER_INSTANCE_NUM; i++) + { + if(gTimerDataBase[i].isInited == true) + { + GPR_clockEnable(gTimerClocks[i*2]); + GPR_clockEnable(gTimerClocks[i*2+1]); + + EIGEN_TIMER(i)->TCTLR = gTimerDataBase[i].backupRegisters.TCTLR; + EIGEN_TIMER(i)->TIVR = gTimerDataBase[i].backupRegisters.TIVR; + EIGEN_TIMER(i)->TMR[0] = gTimerDataBase[i].backupRegisters.TMR[0]; + EIGEN_TIMER(i)->TMR[1] = gTimerDataBase[i].backupRegisters.TMR[1]; + EIGEN_TIMER(i)->TMR[2] = gTimerDataBase[i].backupRegisters.TMR[2]; + } + } + break; + + default: + break; + } +} +#endif + +void TIMER_driverInit(void) +{ + +#ifdef PM_FEATURE_ENABLE + uint32_t i; + + if(gIsTimerDriverInited == false) + { + for(i = 0; i < TIMER_INSTANCE_NUM; i++) + { + gTimerDataBase[i].isInited = false; + } + + gTimerWorkingStatus = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_TIMER_MODULE, TIMER_enterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_TIMER_MODULE, TIMER_exitLowPowerStateRestore, NULL); + + gIsTimerDriverInited = true; + } +#endif + +} + +void TIMER_getDefaultConfig(TimerConfig_t *config) +{ + ASSERT(config); + + config->clockSource = TIMER_INTERNAL_CLOCK; + config->reloadOption = TIMER_RELOAD_ON_MATCH1; + config->initValue = 0; + config->match0 = 0x10000 >> 1U; + config->match1 = 0x10000; + config->match2 = 0xFFFFFFFFU; +} + +void TIMER_init(uint32_t instance, const TimerConfig_t *config) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + ASSERT(config); + + TIMER_driverInit(); + +#ifdef PM_FEATURE_ENABLE + if(gTimerDataBase[instance].isInited == false) + { +#endif + + CLOCK_clockEnable(gTimerClocks[instance*2]); + CLOCK_clockEnable(gTimerClocks[instance*2+1]); + + /* Stop timer counter */ + EIGEN_TIMER(instance)->TCCR = 0; + + EIGEN_TIMER(instance)->TCTLR = EIGEN_VAL2FLD(TIMER_TCTLR_MODE, config->clockSource) | \ + EIGEN_VAL2FLD(TIMER_TCTLR_MCS, config->reloadOption); + EIGEN_TIMER(instance)->TIVR = config->initValue; + EIGEN_TIMER(instance)->TMR[0] = config->match0; + EIGEN_TIMER(instance)->TMR[1] = config->match1; + EIGEN_TIMER(instance)->TMR[2] = config->match2; + +#ifdef PM_FEATURE_ENABLE + gTimerDataBase[instance].isInited = true; + } +#endif +} + +void TIMER_deInit(uint32_t instance) +{ +#ifdef PM_FEATURE_ENABLE + if(gTimerDataBase[instance].isInited == true) + { +#endif + CLOCK_clockDisable(gTimerClocks[instance*2]); + CLOCK_clockDisable(gTimerClocks[instance*2+1]); + +#ifdef PM_FEATURE_ENABLE + gTimerDataBase[instance].isInited = false; + } +#endif +} +void TIMER_setMatch(uint32_t instance, TimerMatchSelect_t matchNum, uint32_t matchValue) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + EIGEN_TIMER(instance)->TMR[matchNum] = matchValue; +} + +void TIMER_setInitValue(uint32_t instance, uint32_t initValue) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + EIGEN_TIMER(instance)->TIVR = initValue; +} + +void TIMER_setReloadOption(uint32_t instance, TimerReloadOption_t option) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + EIGEN_TIMER(instance)->TCTLR = (EIGEN_TIMER(instance)->TCTLR &~ TIMER_TCTLR_MCS_Msk) | EIGEN_VAL2FLD(TIMER_TCTLR_MCS, option); +} + +void TIMER_start(uint32_t instance) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + +#ifdef PM_FEATURE_ENABLE + if(instance != 5) // timer 5 do not vote sleep + { + uint32_t mask = SaveAndSetIRQMask(); + + gTimerWorkingStatus |= (1U << instance); + slpManDrvVoteSleep(SLP_VOTE_TIMER, SLP_ACTIVE_STATE); + + RestoreIRQMask(mask); + } +#endif + EIGEN_TIMER(instance)->TCCR = 1U; +} + +void TIMER_stop(uint32_t instance) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + EIGEN_TIMER(instance)->TCCR = 0; + +#ifdef PM_FEATURE_ENABLE + if(instance != 5) // timer 5 do not vote sleep + { + uint32_t mask = SaveAndSetIRQMask(); + + gTimerWorkingStatus &= ~(1U << instance); + if (gTimerWorkingStatus == 0) + slpManDrvVoteSleep(SLP_VOTE_TIMER, SLP_SLP1_STATE); + + RestoreIRQMask(mask); + } +#endif + +} + +uint32_t TIMER_getCount(uint32_t instance) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + EIGEN_TIMER(instance)->TCLR = TIMER_TCLR_LATCH_Msk; + + while((EIGEN_TIMER(instance)->TCLR & TIMER_TCLR_LATCH_Msk) == TIMER_TCLR_LATCH_Msk); + + return EIGEN_TIMER(instance)->TCR; +} + +int32_t TIMER_setupPwm(uint32_t instance, const TimerPwmConfig_t *config) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + ASSERT(config); + + uint32_t period; + + CLOCK_clockEnable(gTimerClocks[instance*2]); + CLOCK_clockEnable(gTimerClocks[instance*2+1]); + + if(config->srcClock_HZ == 0 || config->pwmFreq_HZ == 0 || config->srcClock_HZ <= config->pwmFreq_HZ) + return ARM_DRIVER_ERROR_PARAMETER; + + period = config->srcClock_HZ / config->pwmFreq_HZ; + + /* Set PWM period */ + EIGEN_TIMER(instance)->TMR[1] = period - 1; + + /* Set duty cycle */ + if(config->dutyCyclePercent == 0) + { + EIGEN_TIMER(instance)->TMR[0] = period; // if TMR[0] > TMR[1], PWM output keeps low + } + else if(config->dutyCyclePercent == 100) + { + EIGEN_TIMER(instance)->TMR[0] = period - 1; // let TMR[0] == TMR[1] + } + else + { + /* + Note the higher pwm frequency is, the lower reslution of dutyCycle we'll get. + Below calculation may overflow for specific dutyCyclePercent and in such case, TMR[0] > TMR[1], PWM output keeps low + */ + EIGEN_TIMER(instance)->TMR[0] = ((uint64_t)period) * (100U - config->dutyCyclePercent) / 100U - 1; + } + EIGEN_TIMER(instance)->TIVR = 0; + + /* Enable PWM out */ + EIGEN_TIMER(instance)->TCTLR = (EIGEN_TIMER(instance)->TCTLR & ~ TIMER_TCTLR_MCS_Msk) | \ + EIGEN_VAL2FLD(TIMER_TCTLR_MCS, 2U) | TIMER_TCTLR_PWMOUT_Msk; + +#ifdef PM_FEATURE_ENABLE + gTimerDataBase[instance].isInited = true; +#endif + + return ARM_DRIVER_OK; + +} + +void TIMER_updatePwmDutyCycle(uint32_t instance, uint32_t dutyCyclePercent) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + if(dutyCyclePercent == 0) + { + EIGEN_TIMER(instance)->TMR[0] = EIGEN_TIMER(instance)->TMR[1] + 1; // if TMR[0] > TMR[1], PWM output keeps low + } + else if(dutyCyclePercent >= 100) + { + EIGEN_TIMER(instance)->TMR[0] = EIGEN_TIMER(instance)->TMR[1]; // let TMR[0] == TMR[1] + } + else + { + EIGEN_TIMER(instance)->TMR[0] = ((uint64_t)EIGEN_TIMER(instance)->TMR[1] + 1) * (100U - dutyCyclePercent) / 100U - 1; + } + +} + +void TIMER_interruptConfig(uint32_t instance, TimerMatchSelect_t match, TimerInterruptConfig_t config) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + uint32_t enableMask, typeMask, registerValue; + + enableMask = 1U << (match + TIMER_TCTLR_IE_0_Pos); + typeMask = 1U << (match + TIMER_TCTLR_IT_0_Pos); + registerValue = EIGEN_TIMER(instance)->TCTLR; + + switch(config) + { + case TIMER_INTERRUPT_DISABLED: + + registerValue &= ~enableMask; + EIGEN_TIMER(instance)->TCTLR = registerValue; + break; + + case TIMER_INTERRUPT_LEVEL: + + registerValue |= enableMask; + registerValue &= ~typeMask; + EIGEN_TIMER(instance)->TCTLR = registerValue; + break; + + case TIMER_INTERRUPT_PULSE: + + registerValue |= enableMask; + registerValue |= typeMask; + EIGEN_TIMER(instance)->TCTLR = registerValue; + break; + + default: + break; + } +} + +TimerInterruptConfig_t TIMER_getInterruptConfig(uint32_t instance, TimerMatchSelect_t match) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + uint32_t enableMask, typeMask, registerValue; + + enableMask = 1U << (match + TIMER_TCTLR_IE_0_Pos); + typeMask = 1U << (match + TIMER_TCTLR_IT_0_Pos); + registerValue = EIGEN_TIMER(instance)->TCTLR; + + if ((enableMask & registerValue) == 0) + return TIMER_INTERRUPT_DISABLED; + else if ((typeMask & registerValue) == 0) + return TIMER_INTERRUPT_LEVEL; + else + return TIMER_INTERRUPT_PULSE; +} + +uint32_t TIMER_getInterruptFlags(uint32_t instance) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + return EIGEN_TIMER(instance)->TSR; +} + +void TIMER_clearInterruptFlags(uint32_t instance, uint32_t mask) +{ + ASSERT(instance < TIMER_INSTANCE_NUM); + + EIGEN_TIMER(instance)->TSR = mask; +} + + +static uint8_t gNetLightInstance = 0xff; +void TIMER_netlightEnable(uint8_t instance) // call by user in bsp_custom.c +{ + gNetLightInstance = instance; +} + +/////// Internal use for Netlight Function ///////////////// +void TIMER_netlightPWM(uint8_t mode) +{ + extern void delay_us(uint32_t us); + uint8_t instance = gNetLightInstance; + static uint8_t curMode; + +#ifdef PM_FEATURE_ENABLE + uint32_t mask; + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, TIMER_netlightPWM_1, P_SIG, "Netlight mode=%u Instance=%d",mode, instance); +#endif + + if(instance == 0xff) + return; + + ASSERT(instance < TIMER_INSTANCE_NUM); + + if(curMode == mode) // do nothing if mode not change + return; + + EIGEN_TIMER(instance)->TCCR = 0; + + if(mode == 0) + { + EIGEN_TIMER(instance)->TMR[0] = 0xFFFFFFFF; + EIGEN_TIMER(instance)->TMR[1] = 0; // TMR[0] > TMR[1], PWM output keeps low + EIGEN_TIMER(instance)->TCCR = 1; + delay_us(10); + EIGEN_TIMER(instance)->TCCR = 0; +#ifdef PM_FEATURE_ENABLE + if(gTimerWorkingStatus & (1U << instance)) + { + CLOCK_clockDisable(gTimerClocks[instance*2]); + CLOCK_clockDisable(gTimerClocks[instance*2+1]); + } + mask = SaveAndSetIRQMask(); + gTimerWorkingStatus &= ~(1U << instance); + if (gTimerWorkingStatus == 0) + slpManDrvVoteSleep(SLP_VOTE_TIMER, SLP_SLP1_STATE); + RestoreIRQMask(mask); +#endif + curMode = 0; + return; + } + +#ifdef PM_FEATURE_ENABLE + if((gTimerWorkingStatus & (1U << instance)) == 0) + { + CLOCK_clockEnable(gTimerClocks[instance*2]); + CLOCK_clockEnable(gTimerClocks[instance*2+1]); + } + mask = SaveAndSetIRQMask(); + gTimerWorkingStatus |= (1U << instance); + slpManDrvVoteSleep(SLP_VOTE_TIMER, SLP_ACTIVE_STATE); + RestoreIRQMask(mask); +#endif + + /* Enable PWM out */ + EIGEN_TIMER(instance)->TCTLR = (EIGEN_TIMER(instance)->TCTLR & ~ TIMER_TCTLR_MCS_Msk) | \ + EIGEN_VAL2FLD(TIMER_TCTLR_MCS, 2U) | TIMER_TCTLR_PWMOUT_Msk; + + if(mode == 1) // fast flash: 64ms high and 800ms low + { + EIGEN_TIMER(instance)->TMR[0] = 0x13D61FF; + + EIGEN_TIMER(instance)->TMR[1] = 0x156C5FE; + + EIGEN_TIMER(instance)->TCCR = 1; + + curMode = mode; + } + else if(mode == 2) // slow flash: 64ms high and 2000ms low + { + EIGEN_TIMER(instance)->TMR[0] = 0x31974FF; + + EIGEN_TIMER(instance)->TMR[1] = 0x332D8FE; + + EIGEN_TIMER(instance)->TCCR = 1; + + curMode = mode; + } + else + { + ASSERT(0); + } + +} + diff --git a/PLAT/driver/chip/ec618/ap/src/tls.c b/PLAT/driver/chip/ec618/ap/src/tls.c new file mode 100644 index 0000000..5fb2c73 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/tls.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: tls.c + * Description: This driver is part of SCT(Security Top) module, only focus on AES and SHA functions which are + * mostly used in TLS(transport layer security) area. + * History: Rev1.0 2021-12-3 + * + ****************************************************************************/ + +#include "tls.h" + +static __attribute__((aligned(4))) sctDescCfg_t sctDescCfg; + +void sctInit() +{ + // open clock + CLOCK_clockEnable(SCT_RMI_HCLK); + + GPR_swReset(RST_SCT_RMI_HCLK); + GPR_swReset(RST_SCT_HCLK); + + memset(&sctDescCfg, 0, sizeof(sctDescCfg_t)); + + // enable sct + *(uint32_t *)SCT_ENABLE_REG = 1; + + // set memory guard + sctMemGuard_t *sctMemGuard = (sctMemGuard_t*)SCT_MEM_GUARD_REG; + sctMemGuard->hAddr0 = MGR_HIGH_ADDR; + sctMemGuard->lAddr0 = MGR_LOW_ADDR; + sctMemGuard->hAddr1 = MGR_HIGH_ADDR1; + sctMemGuard->lAddr1 = MGR_LOW_ADDR1; + sctMemGuard->hAddr2 = MGR_HIGH_ADDR2; + sctMemGuard->lAddr2 = MGR_LOW_ADDR2; + sctMemGuard->hAddr3 = MGR_HIGH_ADDR3; + sctMemGuard->lAddr3 = MGR_LOW_ADDR3; + + // sct common config + sctCfgWord0_t *cfgWord0 = (sctCfgWord0_t*)SCT_COMM_CFG0_REG; + sctCfgWord1_t *cfgWord1 = (sctCfgWord1_t*)SCT_COMM_CFG1_REG; + sctCfgWord0_t word0; + cfgWord0->val = 0; + cfgWord1->descMaxProcTickTime = 0x4fffb; + + word0.ahbAcg = 0; + word0.rmiAcg = 1; + word0.chainStartUnilog = 1; + word0.descDoneUnilog = 1; + word0.chainEndUnilog = 1; + word0.errorIntUnilog = 1; + word0.usbEndianInd = 0; + word0.memHighAddrOffset = 0; + cfgWord0->val = word0.val; +} + +static uint32_t sctCheckBusy() +{ + sctChaState_t *state = (sctChaState_t*)AES_SHA_CH4_STATE_REG; + if (state->chaBeEmpty) + { + return 0; + } + return 1; +} + +static int sctTrigger(sctDescCfg_t* sctDescCfg) +{ + if (sctCheckBusy()) + { + return SCTDRV_BUSY; + } + + sctCfgWord_t* sctCfgWord = (sctCfgWord_t*)AES_SHA_CH4_CFG_REG; + sctCfgWord->chanCfgWord1 = (uint32_t)sctDescCfg; + CLOCK_clockEnable(SCT_HCLK); + sctCfgWord->chanCfgWord5.trigger = 1; + + return SCTDRV_OK; +} + +static int sctPollDone(uint32_t timeOutCycle) +{ + while (timeOutCycle--) + { + delay_us(1); + + if (!sctCheckBusy()) + { + return SCTDRV_OK; + } + } + + return SCTDRV_TIMEOUT; +} + + +int32_t aesUpdate(aesInfo_t* aesInfo) +{ + uint32_t ret = SCTDRV_OK; + + sctDescCfg_t* sctDescCfgPtr = &sctDescCfg; + sctDescCfgPtr->u1.aesField.length = aesInfo->length; + sctDescCfgPtr->u1.aesField.dir = aesInfo->aesCtrl.dir; + sctDescCfgPtr->u1.aesField.aesMode = aesInfo->aesCtrl.aesMode; + sctDescCfgPtr->u1.aesField.paddingMode = aesInfo->aesCtrl.paddingMode; + sctDescCfgPtr->u1.aesField.ckLen = aesInfo->aesCtrl.ckLen; + sctDescCfgPtr->u1.aesField.aesCkSel = aesInfo->aesCtrl.aesCkSel; + sctDescCfgPtr->u1.aesField.subType = 0; // aes + sctDescCfgPtr->u1.aesField.type = 5; // default value is 5 + sctDescCfgPtr->srcAddr = aesInfo->srcAddr; + sctDescCfgPtr->dstAddr = aesInfo->dstAddr; + + if (aesInfo->aesCtrl.aesCkSel == 0) // from memory + { + sctDescCfgPtr->u2.aesCkAddr = aesInfo->aesCkAddr;; + } + + if (aesInfo->aesCtrl.aesMode == 1 || aesInfo->aesCtrl.aesMode == 2) // aes cbc, ctr mode + { + sctDescCfgPtr->u3.aesIvAddr = aesInfo->ivAddr; + } + + sctCfgWord_t* sctCfgWord = (sctCfgWord_t*)AES_SHA_CH4_CFG_REG; + chanCfgWord0_t cfgWord0; + cfgWord0.val = 0; + if (aesInfo->aesCtrl.ckBLEndian == 1) // key is big endian + { + cfgWord0.ckBLEndian = 1; + } + + if (aesInfo->aesCtrl.aesIvBLEndian == 1) // iv is big endian + { + cfgWord0.aesIvBLEndian = 1; + } + + cfgWord0.fifoLen = 1; // only 1 descriptor(aes) + sctCfgWord->chanCfgWord0.val = cfgWord0.val; + + ret = sctTrigger(sctDescCfgPtr); + if (ret != SCTDRV_OK) + { + return SCTDRV_BUSY; + } + + ret = sctPollDone(50000); + return ret; +} + +// if you need to loop call this api, "lastFlag" should be 0 for intermediate steps, and last step it should be 1. +int32_t shaUpdate(shaType_e shaMode, uint32_t srcAddr, uint32_t dstAddr, uint32_t length, uint32_t lastFlag) +{ + uint32_t ret = SCTDRV_OK; + + // sha input should 64bytes aligned, if not, you need to padding it first + if ((length & 0x3f) != 0) + { + return SCTDRV_PAMERR; + } + + sctDescCfg_t* sctDescCfgPtr = &sctDescCfg; + sctDescCfgPtr->srcAddr = srcAddr; // sha input + sctDescCfgPtr->dstAddr = dstAddr; // sha output + sctDescCfgPtr->u1.shaField.length = length; // sha input length, should 64bytes aligned + sctDescCfgPtr->u1.shaField.subType = 1; // 0: aes; 1:sha + sctDescCfgPtr->u1.shaField.shaMode = shaMode; + sctDescCfgPtr->u1.shaField.type = 5; // default value 5 + sctDescCfgPtr->u1.shaField.shaBls = 1; // sha output endian. 0: LE; 1: BE + + if (lastFlag == 0) + { + sctDescCfgPtr->u1.shaField.rcs = 1; // data is continuous + sctDescCfgPtr->u1.shaField.outEn = 0; // not output + } + else + { + sctDescCfgPtr->u1.shaField.rcs = 0; // data has been the last sector + sctDescCfgPtr->u1.shaField.outEn = 1; // open sha output value + } + + sctDescCfgPtr->u3.shaHeadLen.headLen = 0; // no head + + sctCfgWord_t* sctCfgWord = (sctCfgWord_t*)AES_SHA_CH4_CFG_REG; + chanCfgWord0_t cfgWord0; + cfgWord0.val = 0; + cfgWord0.fifoLen = 1; // here only 1 descriptor(sha) + sctCfgWord->chanCfgWord0.val = cfgWord0.val; + + ret = sctTrigger(sctDescCfgPtr); + if (ret != SCTDRV_OK) + { + return SCTDRV_BUSY; + } + + ret = sctPollDone(50000); + return ret; +} + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_custp1.c b/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_custp1.c new file mode 100644 index 0000000..6200cd0 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_custp1.c @@ -0,0 +1,442 @@ +#include "usbd_clscdc.h" +#include "usbd_clscdc_cust_tp.h" + +//#include "func_dbg.h" +#include "string.h" +#include "usbd_macro_def.h" +#include "usbd_func_cconf.h" +#include "usbd_func_cc.h" +#include "usbd_multi_usrcfg_common.h" + + +const usbd_cdc_desc_custp1_st t_usbd_cdc_desc_custp1 = { + .intf_ctrl_desc = { + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + INVALID_INTF_NUM, //VCOM_INTF_NUM_0, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + }, + + .cdc_diep_desc = { + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval */ + }, + + .cdc_doep_desc = { + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + } + +}; + +uint8_t vcom_func_custp1_desc_ass(usb_func_ccinst_st *p_func_ccinst) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + p_ccinst_cdc_setting->desc_assigned = 0; + + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp1_2ep)) + { + return usbd_ret_fail; + } + #endif + p_ccinst_cdc_setting->p_desc_src = (const uint8_t *)(&t_usbd_cdc_desc_custp1); + p_ccinst_cdc_setting->desc_src_size = sizeof(t_usbd_cdc_desc_custp1); + + p_ccinst_cdc_setting->desc_assigned = 1; + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp1_desc_parse(usb_func_ccinst_st *p_func_ccinst) +{ + const uint8_t * p_desc_buf; + uint16_t pos = 0; + uint8_t ret = usbd_ret_no_err; + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usb_endpoint_descriptor_st * p_endp_d; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp1_2ep)) + { + return usbd_ret_fail; + } + #endif + if(p_ccinst_cdc_setting->desc_assigned!=1) + { + return usbd_ret_fail; + } + p_desc_buf = p_ccinst_cdc_setting->p_desc_src; + + p_ccinst_cdc_setting->desc_parsed = 0; + + p_ccinst_cdc_setting->epctrl_valid = 0; + p_ccinst_cdc_setting->epin_valid = 0; + p_ccinst_cdc_setting->epout_valid = 0; + + p_ccinst_cdc_setting->interface_cnt = 0; + + while(pos < p_ccinst_cdc_setting->desc_src_size) + { + if (p_desc_buf[pos] == 0) + { + ret = usbd_ret_fail; + break; + } + if ((pos+ p_desc_buf[pos]) > p_ccinst_cdc_setting->desc_src_size) + { + ret = usbd_ret_fail; + break; + } + + switch (p_desc_buf[pos+1]) + { + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (p_desc_buf[pos] != STANDARD_ENDPOINT_DESC_SIZE) + { + ret = usbd_ret_fail; + break; + } + + p_endp_d = (usb_endpoint_descriptor_st *)(&(p_desc_buf[pos])); + if (p_endp_d->bmAttributes == USBC_CTRL_EP_BULK) + { + //if (p_endp_d->bEndpointAddress &0x80) + + if (p_endp_d == (&t_usbd_cdc_desc_custp1.cdc_diep_desc)) + { + p_ccinst_cdc_setting->epin_valid = 1; + p_ccinst_cdc_setting->p_epin_d = p_endp_d; + } + else if (p_endp_d == (&t_usbd_cdc_desc_custp1.cdc_doep_desc)) + { + p_ccinst_cdc_setting->epout_valid = 1; + p_ccinst_cdc_setting->p_epout_d = p_endp_d; + } + else + { + ret = usbd_ret_fail; + break; + } + } + else if (p_endp_d->bmAttributes == USBC_CTRL_EP_INTR) + { + if (p_endp_d->bEndpointAddress &0x80) + { + p_ccinst_cdc_setting->epctrl_valid = 1; + p_ccinst_cdc_setting->p_epctrl_d = p_endp_d; + } + else + { + ret = usbd_ret_fail; + break; + } + } + else + { + ret = usbd_ret_fail; + break; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + if (p_desc_buf[pos] !=STANDARD_INTERFACE_DESC_SIZE) + { + ret = usbd_ret_fail; + break; + } + p_ccinst_cdc_setting->interface_cnt++; + break; + default: + break; + } + if (ret!=usbd_ret_no_err) + { + break; + } + pos+= p_desc_buf[pos]; + } + + if ((p_ccinst_cdc_setting->epctrl_valid ==1) || + (p_ccinst_cdc_setting->epin_valid ==0) || + (p_ccinst_cdc_setting->epout_valid==0)|| + (p_ccinst_cdc_setting->interface_cnt!=1) ) + { + ret = usbd_ret_fail; + } + if (ret == 0) + { + p_ccinst_cdc_setting->desc_parsed = 1; + } + return ret; +} + +uint8_t vcom_func_custp1_bind(usb_func_ccinst_st *p_func_ccinst, + ccinst_bind_call_data_st *p_bind_call_data) +{ + uint8_t ret = usbd_ret_no_err; + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp1_2ep)) + { + return usbd_ret_fail; + } + #endif + + if ((p_ccinst_cdc_setting->desc_assigned==0) + || (p_ccinst_cdc_setting->desc_parsed==0)) + { + return usbd_ret_fail; + } + + p_ccinst_cdc_setting->ep_datain_num = p_bind_call_data->ep_datain_num; + p_ccinst_cdc_setting->ep_dataout_num = p_bind_call_data->ep_dataout_num; + + p_ccinst_cdc_setting->interface_cnt = p_bind_call_data->interface_cnt; + + p_ccinst_cdc_setting->intf_base_idx = p_bind_call_data->intf_base_idx; + p_ccinst_cdc_setting->intf_1st_idx = p_bind_call_data->intf_1st_idx; + + p_ccinst_cdc_setting->intf_str_id = p_bind_call_data->intf_str_id; + p_ccinst_cdc_setting->binded = 1; + return ret; +} + +uint8_t vcom_func_custp1_get_desc(usb_func_ccinst_st *p_func_ccinst, ccinst_desc_call_data_st*p_desc_call_data) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usbd_cdc_desc_custp1_st *p_usbd_desc_dst; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp1_2ep)) + { + return usbd_ret_fail; + } +#endif + + if (p_desc_call_data->desc_buff_size < p_ccinst_cdc_setting->desc_src_size) + { + return usbd_ret_fail; + } + + if (p_ccinst_cdc_setting->binded == 0) + { + return usbd_ret_fail; + } + + p_usbd_desc_dst = (usbd_cdc_desc_custp1_st *)(p_desc_call_data->p_desc_buff_ptr); + + memcpy(p_usbd_desc_dst, p_ccinst_cdc_setting->p_desc_src, p_ccinst_cdc_setting->desc_src_size); + + p_usbd_desc_dst->cdc_diep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_datain_num); + p_usbd_desc_dst->cdc_doep_desc.bEndpointAddress = p_ccinst_cdc_setting->ep_dataout_num; + p_usbd_desc_dst->intf_ctrl_desc.iInterface = p_ccinst_cdc_setting->intf_str_id; + + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_1st_idx; + + if (p_desc_call_data->b_intf_ctrl_desc_upd) + { + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceProtocol = p_desc_call_data->bInterfaceProtocol; + } + + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp1_get_othspd_desc(usb_func_ccinst_st *p_func_ccinst, ccinst_desc_call_data_st*p_desc_call_data) +{ + + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usbd_cdc_desc_custp1_st *p_usbd_desc_dst; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp1_2ep)) + { + return usbd_ret_fail; + } +#endif + + if (p_desc_call_data->desc_buff_size < p_ccinst_cdc_setting->desc_src_size) + { + return usbd_ret_fail; + } + + if (p_ccinst_cdc_setting->binded == 0) + { + return usbd_ret_fail; + } + + p_usbd_desc_dst = (usbd_cdc_desc_custp1_st*)(p_desc_call_data->p_desc_buff_ptr); + memcpy(p_usbd_desc_dst, p_ccinst_cdc_setting->p_desc_src, p_ccinst_cdc_setting->desc_src_size); + + + p_usbd_desc_dst->cdc_diep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_datain_num); + p_usbd_desc_dst->cdc_doep_desc.bEndpointAddress = p_ccinst_cdc_setting->ep_dataout_num; + p_usbd_desc_dst->intf_ctrl_desc.iInterface = p_ccinst_cdc_setting->intf_str_id; + p_usbd_desc_dst->cdc_diep_desc.wMaxPacketSize_High = 0; + p_usbd_desc_dst->cdc_diep_desc.wMaxPacketSize_Low = 0x40; + p_usbd_desc_dst->cdc_doep_desc.wMaxPacketSize_High = 0; + p_usbd_desc_dst->cdc_doep_desc.wMaxPacketSize_Low = 0x40; + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_1st_idx; + + if (p_desc_call_data->b_intf_ctrl_desc_upd) + { + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceProtocol = p_desc_call_data->bInterfaceProtocol; + } + + return usbd_ret_no_err; +} + + +uint8_t vcom_func_custp1_init(usb_func_ccinst_st *p_func_ccinst, uint8_t cfgidx) +{ + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp1_deinit(usb_func_ccinst_st *p_func_ccinst, uint8_t cfgidx) +{ + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp1_unbind(usb_func_ccinst_st *p_func_ccinst) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp1_2ep)) + { + return usbd_ret_fail; + } +#endif + + if (p_ccinst_cdc_setting->binded==0) + { + return usbd_ret_fail; + } + p_ccinst_cdc_setting->binded = 0; + + return usbd_ret_no_err; +} + +#if (VCOM_CCINST_SUBTP1_2EP_CNT > 0) +const ccinst_setting_base_st t_vcom_custp1_base_setting = +{ + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp1_2ep +}; + +ccinst_cdc_setting_st t_vcom_custp1_setting_arr[VCOM_CCINST_SUBTP1_2EP_CNT] ={ +//[0] + { + .bs_set = t_vcom_custp1_base_setting, + }, + +#if (VCOM_CCINST_SUBTP1_2EP_CNT >=2) +//[1] + + { + .bs_set = t_vcom_custp1_base_setting, + }, +#endif + +#if (VCOM_CCINST_SUBTP1_2EP_CNT >= 3) +//[2] + { + .bs_set = t_vcom_custp1_base_setting, + }, +#endif +}; + +usb_func_ccinst_st t_vcom_func_custp1_arr[VCOM_CCINST_SUBTP1_2EP_CNT] ={ +//[0] + { + .p_cc_setting = &t_vcom_custp1_setting_arr[0], + + .func_desc_ass = vcom_func_custp1_desc_ass, + .func_desc_parse = vcom_func_custp1_desc_parse, + .func_bind = vcom_func_custp1_bind, + .func_get_desc = vcom_func_custp1_get_desc, + .func_get_othspd_desc = vcom_func_custp1_get_othspd_desc, + + .func_init = vcom_func_custp1_init, + .func_deinit = vcom_func_custp1_deinit, + .func_unbind = vcom_func_custp1_unbind, + }, + +#if (VCOM_CCINST_SUBTP1_2EP_CNT >=2) +//[1] + + { + .p_cc_setting = &t_vcom_custp1_setting_arr[1], + .func_desc_ass = vcom_func_custp1_desc_ass, + .func_desc_parse = vcom_func_custp1_desc_parse, + .func_bind = vcom_func_custp1_bind, + .func_get_desc = vcom_func_custp1_get_desc, + .func_get_othspd_desc = vcom_func_custp1_get_othspd_desc, + + .func_init = vcom_func_custp1_init, + .func_deinit = vcom_func_custp1_deinit, + .func_unbind = vcom_func_custp1_unbind, + }, +#endif + +#if (VCOM_CCINST_SUBTP1_2EP_CNT >= 3) +//[2] + { + .p_cc_setting = &t_vcom_custp1_setting_arr[2], + + .func_desc_ass = vcom_func_custp1_desc_ass, + .func_desc_parse = vcom_func_custp1_desc_parse, + .func_bind = vcom_func_custp1_bind, + .func_get_desc = vcom_func_custp1_get_desc, + .func_get_othspd_desc = vcom_func_custp1_get_othspd_desc, + + .func_init = vcom_func_custp1_init, + .func_deinit = vcom_func_custp1_deinit, + .func_unbind = vcom_func_custp1_unbind, + }, +#endif + +}; + +#endif + + + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_custp2.c b/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_custp2.c new file mode 100644 index 0000000..827dada --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_custp2.c @@ -0,0 +1,501 @@ +#include "usbd_clscdc.h" +#include "usbd_clscdc_cust_tp.h" + +//#include "func_dbg.h" +#include "string.h" +#include "usbd_macro_def.h" +#include "usbd_func_cconf.h" +#include "usbd_func_cc.h" +#include "usbd_multi_usrcfg_common.h" +#define CC_CUSTP2_CMDEP_MPS 16 + +const usbd_cdc_desc_custp2_st t_usbd_cdc_desc_custp2 = { + .intf_ctrl_desc = { + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + INVALID_INTF_NUM, //VCOM_INTF_NUM_0, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x03, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + }, + + .cdc_head_desc = { + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + }, + + .cdc_callmgr_desc = { + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + INVALID_INTF_NUM, /* bDataInterface: 1 */ + }, + + .cdc_acm_desc = { + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + }, + + .cdc_union_desc = { + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + INVALID_INTF_NUM,//VCOM_INTF_NUM_0, /* bMasterInterface: Communication class interface */ + INVALID_INTF_NUM,//VCOM_INTF_NUM_1, /* bSlaveInterface0: Data Class Interface */ + }, + + .cdc_cmd_ep_desc = { + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CC_CUSTP2_CMDEP_MPS), /* wMaxPacketSize: */ + HIBYTE(CC_CUSTP2_CMDEP_MPS), +#ifdef USE_USBC_CTRL_HS + 0x10, /* bInterval: */ +#else + 0xFF, /* bInterval: */ +#endif /* USE_USBC_CTRL_HS */ + }, + + + .cdc_diep_desc = { + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval */ + }, + + .cdc_doep_desc = { + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + } + + +}; + +uint8_t vcom_func_custp2_desc_ass(usb_func_ccinst_st *p_func_ccinst) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + p_ccinst_cdc_setting->desc_assigned = 0; + + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp2_3ep)) + { + return usbd_ret_fail; + } + #endif + p_ccinst_cdc_setting->p_desc_src =(const uint8_t *)(&t_usbd_cdc_desc_custp2); + p_ccinst_cdc_setting->desc_src_size = sizeof(t_usbd_cdc_desc_custp2); + p_ccinst_cdc_setting->desc_assigned = 1; + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp2_desc_parse(usb_func_ccinst_st *p_func_ccinst) +{ + const uint8_t * p_desc_buf; + uint16_t pos = 0; + uint8_t ret = usbd_ret_no_err; + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usb_endpoint_descriptor_st * p_endp_d; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp2_3ep)) + { + return usbd_ret_fail; + } + #endif + if(p_ccinst_cdc_setting->desc_assigned!=1) + { + return usbd_ret_fail; + } + p_desc_buf = p_ccinst_cdc_setting->p_desc_src; + + p_ccinst_cdc_setting->desc_parsed = 0; + + p_ccinst_cdc_setting->epctrl_valid = 0; + p_ccinst_cdc_setting->epin_valid = 0; + p_ccinst_cdc_setting->epout_valid = 0; + + p_ccinst_cdc_setting->interface_cnt = 0; + + while(pos < p_ccinst_cdc_setting->desc_src_size) + { + if (p_desc_buf[pos] == 0) + { + ret = usbd_ret_fail; + break; + } + if ((pos+ p_desc_buf[pos]) > p_ccinst_cdc_setting->desc_src_size) + { + ret = usbd_ret_fail; + break; + } + + switch (p_desc_buf[pos+1]) + { + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (p_desc_buf[pos] != STANDARD_ENDPOINT_DESC_SIZE) + { + ret = usbd_ret_fail; + break; + } + + p_endp_d = (usb_endpoint_descriptor_st *)(&(p_desc_buf[pos])); + if (p_endp_d->bmAttributes == USBC_CTRL_EP_BULK) + { + //if (p_endp_d->bEndpointAddress &0x80) + if (p_endp_d == (&t_usbd_cdc_desc_custp2.cdc_diep_desc)) + { + p_ccinst_cdc_setting->epin_valid = 1; + p_ccinst_cdc_setting->p_epin_d = p_endp_d; + } + else if (p_endp_d == (&t_usbd_cdc_desc_custp2.cdc_doep_desc)) + { + p_ccinst_cdc_setting->epout_valid = 1; + p_ccinst_cdc_setting->p_epout_d = p_endp_d; + } + else + { + ret = usbd_ret_fail; + break; + } + } + else if (p_endp_d->bmAttributes == USBC_CTRL_EP_INTR) + { + if (p_endp_d->bEndpointAddress &0x80) + { + p_ccinst_cdc_setting->epctrl_valid = 1; + p_ccinst_cdc_setting->p_epctrl_d = p_endp_d; + } + else + { + ret = usbd_ret_fail; + break; + } + } + else + { + ret = usbd_ret_fail; + break; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + if (p_desc_buf[pos] !=STANDARD_INTERFACE_DESC_SIZE) + { + ret = usbd_ret_fail; + break; + } + p_ccinst_cdc_setting->interface_cnt++; + break; + default: + break; + } + if (ret!=usbd_ret_no_err) + { + break; + } + pos+= p_desc_buf[pos]; + } + + if ((p_ccinst_cdc_setting->epctrl_valid ==0) || + (p_ccinst_cdc_setting->epin_valid ==0) || + (p_ccinst_cdc_setting->epout_valid==0)|| + (p_ccinst_cdc_setting->interface_cnt!=1) ) + { + ret = usbd_ret_fail; + } + if (ret == 0) + { + p_ccinst_cdc_setting->desc_parsed = 1; + } + return ret; +} + +uint8_t vcom_func_custp2_bind(usb_func_ccinst_st *p_func_ccinst, + ccinst_bind_call_data_st *p_bind_call_data) +{ + uint8_t ret = usbd_ret_no_err; + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp2_3ep)) + { + return usbd_ret_fail; + } + #endif + + if ((p_ccinst_cdc_setting->desc_assigned==0) + || (p_ccinst_cdc_setting->desc_parsed==0)) + { + return usbd_ret_fail; + } + + p_ccinst_cdc_setting->ep_ctrl_num = p_bind_call_data->ep_ctrl_num; + p_ccinst_cdc_setting->ep_datain_num = p_bind_call_data->ep_datain_num; + p_ccinst_cdc_setting->ep_dataout_num = p_bind_call_data->ep_dataout_num; + + + p_ccinst_cdc_setting->intf_base_idx = p_bind_call_data->intf_base_idx; + p_ccinst_cdc_setting->intf_1st_idx = p_bind_call_data->intf_1st_idx; + p_ccinst_cdc_setting->intf_2nd_idx = p_bind_call_data->intf_2nd_idx; + p_ccinst_cdc_setting->intf_str_id = p_bind_call_data->intf_str_id; + p_ccinst_cdc_setting->binded = 1; + return ret; +} + +uint8_t vcom_func_custp2_get_desc(usb_func_ccinst_st *p_func_ccinst, ccinst_desc_call_data_st*p_desc_call_data) +{ + + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usbd_cdc_desc_custp2_st *p_usbd_desc_dst; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp2_3ep)) + { + return usbd_ret_fail; + } +#endif + + if (p_desc_call_data->desc_buff_size < p_ccinst_cdc_setting->desc_src_size) + { + return usbd_ret_fail; + } + + if (p_ccinst_cdc_setting->binded == 0) + { + return usbd_ret_fail; + } + + p_usbd_desc_dst = (usbd_cdc_desc_custp2_st *)(p_desc_call_data->p_desc_buff_ptr); + + memcpy(p_usbd_desc_dst, p_ccinst_cdc_setting->p_desc_src, p_ccinst_cdc_setting->desc_src_size); + p_usbd_desc_dst->cdc_cmd_ep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_ctrl_num); + p_usbd_desc_dst->cdc_diep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_datain_num); + p_usbd_desc_dst->cdc_doep_desc.bEndpointAddress = p_ccinst_cdc_setting->ep_dataout_num; + p_usbd_desc_dst->intf_ctrl_desc.iInterface = p_ccinst_cdc_setting->intf_str_id; + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_1st_idx; + + p_usbd_desc_dst->cdc_union_desc.bMasterInterface0 = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bSlaveInterface0 = p_ccinst_cdc_setting->intf_1st_idx; + + if (p_desc_call_data->b_intf_ctrl_desc_upd) + { + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceProtocol = p_desc_call_data->bInterfaceProtocol; + } + + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp2_get_othspd_desc(usb_func_ccinst_st *p_func_ccinst, ccinst_desc_call_data_st*p_desc_call_data) +{ + + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usbd_cdc_desc_custp2_st *p_usbd_desc_dst; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp2_3ep)) + { + return usbd_ret_fail; + } +#endif + + if (p_desc_call_data->desc_buff_size < p_ccinst_cdc_setting->desc_src_size) + { + return usbd_ret_fail; + } + + if (p_ccinst_cdc_setting->binded == 0) + { + return usbd_ret_fail; + } + + p_usbd_desc_dst = (usbd_cdc_desc_custp2_st*)(p_desc_call_data->p_desc_buff_ptr); + memcpy(p_usbd_desc_dst, p_ccinst_cdc_setting->p_desc_src, p_ccinst_cdc_setting->desc_src_size); + + + p_usbd_desc_dst->cdc_cmd_ep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_ctrl_num); + p_usbd_desc_dst->cdc_cmd_ep_desc.bInterval = 0xff; + + p_usbd_desc_dst->cdc_diep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_datain_num); + p_usbd_desc_dst->cdc_doep_desc.bEndpointAddress = p_ccinst_cdc_setting->ep_dataout_num; + p_usbd_desc_dst->intf_ctrl_desc.iInterface = p_ccinst_cdc_setting->intf_str_id; + p_usbd_desc_dst->cdc_diep_desc.wMaxPacketSize_High = 0; + p_usbd_desc_dst->cdc_diep_desc.wMaxPacketSize_Low = 0x40; + p_usbd_desc_dst->cdc_doep_desc.wMaxPacketSize_High = 0; + p_usbd_desc_dst->cdc_doep_desc.wMaxPacketSize_Low = 0x40; + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bMasterInterface0 = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bSlaveInterface0 = p_ccinst_cdc_setting->intf_1st_idx; + + + if (p_desc_call_data->b_intf_ctrl_desc_upd) + { + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceProtocol = p_desc_call_data->bInterfaceProtocol; + } + + return usbd_ret_no_err; +} + + + +uint8_t vcom_func_custp2_init(usb_func_ccinst_st *p_func_ccinst, uint8_t cfgidx) +{ + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp2_deinit(usb_func_ccinst_st *p_func_ccinst, uint8_t cfgidx) +{ + return usbd_ret_no_err; +} + +uint8_t vcom_func_custp2_unbind(usb_func_ccinst_st *p_func_ccinst) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp2_3ep)) + { + return usbd_ret_fail; + } +#endif + + if (p_ccinst_cdc_setting->binded==0) + { + return usbd_ret_fail; + } + p_ccinst_cdc_setting->binded = 0; + + return usbd_ret_no_err; + +} + +#if (VCOM_CCINST_SUBTP2_3EP_CNT > 0) +const ccinst_setting_base_st t_vcom_custp2_base_setting = +{ + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp2_3ep +}; + +ccinst_cdc_setting_st t_vcom_custp2_setting_arr[VCOM_CCINST_SUBTP2_3EP_CNT] ={ +//[0] + { + .bs_set = t_vcom_custp2_base_setting, + }, + +#if (VCOM_CCINST_SUBTP2_3EP_CNT >=2) +//[1] + { + .bs_set = t_vcom_custp2_base_setting, + }, +#endif + +#if (VCOM_CCINST_SUBTP2_3EP_CNT >= 3) +//[2] + { + .bs_set = t_vcom_custp2_base_setting, + }, +#endif +}; + + +usb_func_ccinst_st t_vcom_func_custp2_arr[VCOM_CCINST_SUBTP2_3EP_CNT] ={ +//[0] + { + .p_cc_setting = &t_vcom_custp2_setting_arr[0], + .func_desc_ass = vcom_func_custp2_desc_ass, + .func_desc_parse = vcom_func_custp2_desc_parse, + .func_bind = vcom_func_custp2_bind, + .func_get_desc = vcom_func_custp2_get_desc, + .func_get_othspd_desc = vcom_func_custp2_get_othspd_desc, + + .func_init = vcom_func_custp2_init, + .func_deinit = vcom_func_custp2_deinit, + .func_unbind = vcom_func_custp2_unbind, + }, + +#if (VCOM_CCINST_SUBTP2_3EP_CNT >=2) +//[1] + + { + .p_cc_setting = &t_vcom_custp2_setting_arr[1], + + .func_desc_ass = vcom_func_custp2_desc_ass, + .func_desc_parse = vcom_func_custp2_desc_parse, + .func_bind = vcom_func_custp2_bind, + .func_get_desc = vcom_func_custp2_get_desc, + .func_get_othspd_desc = vcom_func_custp2_get_othspd_desc, + + .func_init = vcom_func_custp2_init, + .func_deinit = vcom_func_custp2_deinit, + .func_unbind = vcom_func_custp2_unbind, + }, +#endif + +#if (VCOM_CCINST_SUBTP2_3EP_CNT >= 3) +//[2] + { + .p_cc_setting = &t_vcom_custp2_setting_arr[2], + .func_desc_ass = vcom_func_custp2_desc_ass, + .func_desc_parse = vcom_func_custp2_desc_parse, + .func_bind = vcom_func_custp2_bind, + .func_get_desc = vcom_func_custp2_get_desc, + .func_get_othspd_desc = vcom_func_custp2_get_othspd_desc, + + .func_init = vcom_func_custp2_init, + .func_deinit = vcom_func_custp2_deinit, + .func_unbind = vcom_func_custp2_unbind, + }, +#endif + +}; + +#endif + + + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_inherent.c b/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_inherent.c new file mode 100644 index 0000000..ebdf39e --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/function_vcom_inherent.c @@ -0,0 +1,603 @@ +#include "usbd_clscdc.h" +#include "usbd_clscdc_cust_tp.h" + +#include "string.h" +#include "usbd_macro_def.h" +#include "usbd_func_cconf.h" +#include "usbd_func_cc.h" +#include "usbd_multi_usrcfg_common.h" +typedef struct tag_usbd_cdc_ccinst_desc_inhrnt usbd_cdc_desc_inhrnt_st; + +#define CC_INHRNT_CMDEP_MPS 16 + + +#define CCINHRNT_SET_LAST_ERR(err_no) usbd_set_mod_last_err(usb_ccinst_inhrnt_mod, err_no) + + +const usbd_cdc_desc_inhrnt_st t_usbd_cdc_desc_inhrnt = { + .intf_asso_desc = { + // IAD COM1 + 0x08, // bLength: Interface Descriptor size + 0x0B, // bDescriptorType: IAD + INVALID_INTF_NUM, //VCOM_INTF_NUM_0, bFirstInterface + 0x02, // bInterfaceCount + 0x02, // bFunctionClass: CDC + 0x02, // bFunctionSubClass + 0x01, // bFunctionProtocol + 0x02, // iFunction + }, + + .intf_ctrl_desc = { + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + INVALID_INTF_NUM, //VCOM_INTF_NUM_0, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + }, + + .cdc_head_desc = { + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + }, + + .cdc_callmgr_desc = { + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + INVALID_INTF_NUM, /* bDataInterface: 1 */ + }, + + .cdc_acm_desc = { + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + }, + + .cdc_union_desc = { + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + INVALID_INTF_NUM,//VCOM_INTF_NUM_0, /* bMasterInterface: Communication class interface */ + INVALID_INTF_NUM,//VCOM_INTF_NUM_1, /* bSlaveInterface0: Data Class Interface */ + }, + + .cdc_cmd_ep_desc = { + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CC_INHRNT_CMDEP_MPS), /* wMaxPacketSize: */ + HIBYTE(CC_INHRNT_CMDEP_MPS), +#ifdef USE_USBC_CTRL_HS + 0x10, /* bInterval: */ +#else + 0xFF, /* bInterval: */ +#endif /* USE_USBC_CTRL_HS */ + }, + + .intf_data_desc = { + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ + INVALID_INTF_NUM, //VCOM_INTF_NUM_1, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + }, + + + .cdc_diep_desc = { + /*Endpoint IN Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00 /* bInterval */ + }, + + .cdc_doep_desc = { + /*Endpoint OUT Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ + INVALID_EP_NUM, //CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_DATA_MAX_PACKET_SIZE), + 0x00, /* bInterval: ignore for Bulk transfer */ + } + + +}; + +uint8_t vcom_func_inhrnt_desc_ass(usb_func_ccinst_st *p_func_ccinst) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + p_ccinst_cdc_setting->desc_assigned = 0; + + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp0_inhrnt)) + { + return usbd_ret_fail; + } + #endif + p_ccinst_cdc_setting->p_desc_src =(const uint8_t *)(&t_usbd_cdc_desc_inhrnt); + p_ccinst_cdc_setting->desc_src_size = sizeof(t_usbd_cdc_desc_inhrnt); + p_ccinst_cdc_setting->desc_assigned = 1; + return usbd_ret_no_err; +} + +uint8_t vcom_func_inhrnt_desc_parse(usb_func_ccinst_st *p_func_ccinst) +{ + const uint8_t * p_desc_buf; + uint16_t pos = 0; + uint8_t ret = usbd_ret_no_err; + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usb_endpoint_descriptor_st * p_endp_d; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp0_inhrnt)) + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_tpinvalid); + return usbd_ret_fail; + } + #endif + if(p_ccinst_cdc_setting->desc_assigned!=1) + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_ass0); + return usbd_ret_fail; + } + p_desc_buf = p_ccinst_cdc_setting->p_desc_src; + + p_ccinst_cdc_setting->desc_parsed = 0; + + p_ccinst_cdc_setting->epctrl_valid = 0; + p_ccinst_cdc_setting->epin_valid = 0; + p_ccinst_cdc_setting->epout_valid = 0; + + p_ccinst_cdc_setting->interface_cnt = 0; + + while(pos < p_ccinst_cdc_setting->desc_src_size) + { + if (p_desc_buf[pos] == 0) + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_len0); + + ret = usbd_ret_fail; + break; + } + if ((pos+ p_desc_buf[pos]) > p_ccinst_cdc_setting->desc_src_size) + { + ret = usbd_ret_fail; + CCINHRNT_SET_LAST_ERR(desc_parse_err_len_ovf); + break; + } + + switch (p_desc_buf[pos+1]) + { + case USB_ENDPOINT_DESCRIPTOR_TYPE: + if (p_desc_buf[pos] != STANDARD_ENDPOINT_DESC_SIZE) + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_epdesclen); + + ret = usbd_ret_fail; + break; + } + + p_endp_d = (usb_endpoint_descriptor_st *)(&(p_desc_buf[pos])); + if (p_endp_d->bmAttributes == USBC_CTRL_EP_BULK) + { + //if (p_endp_d->bEndpointAddress &0x80) + if (p_endp_d == (&t_usbd_cdc_desc_inhrnt.cdc_diep_desc)) + { + p_ccinst_cdc_setting->epin_valid = 1; + p_ccinst_cdc_setting->p_epin_d = p_endp_d; + } + else if (p_endp_d == (&t_usbd_cdc_desc_inhrnt.cdc_doep_desc)) + { + p_ccinst_cdc_setting->epout_valid = 1; + p_ccinst_cdc_setting->p_epout_d = p_endp_d; + } + else + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_epdescptr_1); + + ret = usbd_ret_fail; + break; + } + + } + else if (p_endp_d->bmAttributes == USBC_CTRL_EP_INTR) + { + if (p_endp_d == (&t_usbd_cdc_desc_inhrnt.cdc_cmd_ep_desc)) + + { + p_ccinst_cdc_setting->epctrl_valid = 1; + p_ccinst_cdc_setting->p_epctrl_d = p_endp_d; + + } + else + { + ret = usbd_ret_fail; + CCINHRNT_SET_LAST_ERR(desc_parse_err_epdescptr_2); + + break; + } + } + else + { + ret = usbd_ret_fail; + break; + } + break; + case USB_INTERFACE_DESCRIPTOR_TYPE: + if (p_desc_buf[pos] !=STANDARD_INTERFACE_DESC_SIZE) + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_intfdesclen); + + ret = usbd_ret_fail; + break; + } + p_ccinst_cdc_setting->interface_cnt++; + break; + default: + break; + } + if (ret!=usbd_ret_no_err) + { + break; + } + pos+= p_desc_buf[pos]; + } + + if (ret!=usbd_ret_no_err) + { + return ret; + } + if ((p_ccinst_cdc_setting->epctrl_valid ==0) || + (p_ccinst_cdc_setting->epin_valid ==0) || + (p_ccinst_cdc_setting->epout_valid==0)|| + (p_ccinst_cdc_setting->interface_cnt!=2) ) + { + CCINHRNT_SET_LAST_ERR(desc_parse_err_parserslt); + + ret = usbd_ret_fail; + } + if (ret == 0) + { + p_ccinst_cdc_setting->desc_parsed = 1; + } + return ret; +} + +uint8_t vcom_func_inhrnt_bind(usb_func_ccinst_st *p_func_ccinst, + ccinst_bind_call_data_st *p_bind_call_data) +{ + uint8_t ret = usbd_ret_no_err; + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + #ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp0_inhrnt)) + { + return usbd_ret_fail; + } + #endif + + if ((p_ccinst_cdc_setting->desc_assigned==0) + || (p_ccinst_cdc_setting->desc_parsed==0)) + { + return usbd_ret_fail; + } + + p_ccinst_cdc_setting->ep_ctrl_num = p_bind_call_data->ep_ctrl_num; + p_ccinst_cdc_setting->ep_datain_num = p_bind_call_data->ep_datain_num; + p_ccinst_cdc_setting->ep_dataout_num = p_bind_call_data->ep_dataout_num; + + + p_ccinst_cdc_setting->intf_base_idx = p_bind_call_data->intf_base_idx; + p_ccinst_cdc_setting->intf_1st_idx = p_bind_call_data->intf_1st_idx; + p_ccinst_cdc_setting->intf_2nd_idx = p_bind_call_data->intf_2nd_idx; + p_ccinst_cdc_setting->intf_str_id = p_bind_call_data->intf_str_id; + + p_ccinst_cdc_setting->binded = 1; + return ret; +} + +uint8_t vcom_func_inhrnt_get_desc(usb_func_ccinst_st *p_func_ccinst, ccinst_desc_call_data_st*p_desc_call_data) +{ + + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usbd_cdc_desc_inhrnt_st *p_usbd_desc_dst; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp0_inhrnt)) + { + return usbd_ret_fail; + } +#endif + + if (p_desc_call_data->desc_buff_size < p_ccinst_cdc_setting->desc_src_size) + { + return usbd_ret_fail; + } + + if (p_ccinst_cdc_setting->binded == 0) + { + return usbd_ret_fail; + } + + p_usbd_desc_dst = (usbd_cdc_desc_inhrnt_st *)(p_desc_call_data->p_desc_buff_ptr); + memcpy(p_usbd_desc_dst, p_ccinst_cdc_setting->p_desc_src, p_ccinst_cdc_setting->desc_src_size); + + + p_usbd_desc_dst->cdc_cmd_ep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_ctrl_num); + p_usbd_desc_dst->cdc_diep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_datain_num); + p_usbd_desc_dst->cdc_doep_desc.bEndpointAddress = p_ccinst_cdc_setting->ep_dataout_num; + + + p_usbd_desc_dst->cdc_callmgr_desc.bDataInterface = p_ccinst_cdc_setting->intf_2nd_idx; + + p_usbd_desc_dst->intf_asso_desc.bFirstInterface = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->intf_asso_desc.bInterfaceCount = p_ccinst_cdc_setting->interface_cnt; + + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bMasterInterface0 = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bSlaveInterface0 = p_ccinst_cdc_setting->intf_2nd_idx; + + p_usbd_desc_dst->intf_data_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_2nd_idx; + + p_usbd_desc_dst->intf_ctrl_desc.iInterface = p_ccinst_cdc_setting->intf_str_id; + p_usbd_desc_dst->intf_asso_desc.iFunction = p_ccinst_cdc_setting->intf_str_id; + + if (p_desc_call_data->b_intf_ctrl_desc_upd) + { + p_usbd_desc_dst->intf_asso_desc.bFunctionClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_asso_desc.bFunctionSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_asso_desc.bFunctionProtocol = p_desc_call_data->bInterfaceProtocol; + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceProtocol = p_desc_call_data->bInterfaceProtocol; + } + return usbd_ret_no_err; +} + +uint8_t vcom_func_inhrnt_get_othspd_desc(usb_func_ccinst_st *p_func_ccinst, ccinst_desc_call_data_st*p_desc_call_data) +{ + + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + usbd_cdc_desc_inhrnt_st *p_usbd_desc_dst; + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; + +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp0_inhrnt)) + { + return usbd_ret_fail; + } +#endif + + if (p_desc_call_data->desc_buff_size < p_ccinst_cdc_setting->desc_src_size) + { + return usbd_ret_fail; + } + + if (p_ccinst_cdc_setting->binded == 0) + { + return usbd_ret_fail; + } + + p_usbd_desc_dst = (usbd_cdc_desc_inhrnt_st*)(p_desc_call_data->p_desc_buff_ptr); + memcpy(p_usbd_desc_dst, p_ccinst_cdc_setting->p_desc_src, p_ccinst_cdc_setting->desc_src_size); + + + p_usbd_desc_dst->cdc_cmd_ep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_ctrl_num); + p_usbd_desc_dst->cdc_cmd_ep_desc.bInterval = 0xff; + + p_usbd_desc_dst->cdc_diep_desc.bEndpointAddress = EPIN_MARK_DIR(p_ccinst_cdc_setting->ep_datain_num); + p_usbd_desc_dst->cdc_doep_desc.bEndpointAddress = p_ccinst_cdc_setting->ep_dataout_num; + + p_usbd_desc_dst->cdc_diep_desc.wMaxPacketSize_High = 0; + p_usbd_desc_dst->cdc_diep_desc.wMaxPacketSize_Low = 0x40; + p_usbd_desc_dst->cdc_doep_desc.wMaxPacketSize_High = 0; + p_usbd_desc_dst->cdc_doep_desc.wMaxPacketSize_Low = 0x40; + + p_usbd_desc_dst->cdc_callmgr_desc.bDataInterface = p_ccinst_cdc_setting->intf_2nd_idx; + + p_usbd_desc_dst->intf_asso_desc.bFirstInterface = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->intf_asso_desc.bInterfaceCount = p_ccinst_cdc_setting->interface_cnt; + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bMasterInterface0 = p_ccinst_cdc_setting->intf_1st_idx; + p_usbd_desc_dst->cdc_union_desc.bSlaveInterface0 = p_ccinst_cdc_setting->intf_2nd_idx; + + p_usbd_desc_dst->intf_data_desc.bInterfaceNumber = p_ccinst_cdc_setting->intf_2nd_idx; + + p_usbd_desc_dst->intf_ctrl_desc.iInterface = p_ccinst_cdc_setting->intf_str_id; + p_usbd_desc_dst->intf_asso_desc.iFunction = p_ccinst_cdc_setting->intf_str_id; + + if (p_desc_call_data->b_intf_ctrl_desc_upd) + { + p_usbd_desc_dst->intf_asso_desc.bFunctionClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_asso_desc.bFunctionSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_asso_desc.bFunctionProtocol = p_desc_call_data->bInterfaceProtocol; + + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceClass = p_desc_call_data->bInterfaceClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceSubClass = p_desc_call_data->bInterfaceSubClass; + p_usbd_desc_dst->intf_ctrl_desc.bInterfaceProtocol = p_desc_call_data->bInterfaceProtocol; + } + + return usbd_ret_no_err; +} + + + +uint8_t vcom_func_inhrnt_init(usb_func_ccinst_st *p_func_ccinst, uint8_t cfgidx) +{ + return usbd_ret_no_err; +} + +uint8_t vcom_func_inhrnt_deinit(usb_func_ccinst_st *p_func_ccinst, uint8_t cfgidx) +{ + return usbd_ret_no_err; +} + +uint8_t vcom_func_inhrnt_unbind(usb_func_ccinst_st *p_func_ccinst) +{ + ccinst_cdc_setting_st* p_ccinst_cdc_setting; + + p_ccinst_cdc_setting = p_func_ccinst->p_cc_setting; +#ifdef VCOM_CHK_CCINST_TYPE + if ((p_ccinst_cdc_setting->bs_set.setting_maintp!=ccinst_setting_cdc_vcom_maintp) || + (p_ccinst_cdc_setting->bs_set.setting_subtp != ccinst_setting_vcom_subtp0_inhrnt)) + { + return usbd_ret_fail; + } +#endif + + if (p_ccinst_cdc_setting->binded==0) + { + return usbd_ret_fail; + } + p_ccinst_cdc_setting->binded = 0; + + + return usbd_ret_no_err; +} + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT > 0) +const ccinst_setting_base_st t_vcom_custp0_base_setting = +{ + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, +}; + +ccinst_cdc_setting_st t_vcom_custp0_setting_arr[VCOM_CCINST_SUBTP0_INHERENT_CNT] ={ +//[0] + { + .bs_set = t_vcom_custp0_base_setting, + }, + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT >=2) +//[1] + { + .bs_set = t_vcom_custp0_base_setting, + }, +#endif + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT >= 3) +//[2] + { + .bs_set = t_vcom_custp0_base_setting, + }, +#endif + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT >= 4) +//[2] + { + .bs_set = t_vcom_custp0_base_setting, + }, +#endif + +}; + +usb_func_ccinst_st t_vcom_func_custp0_inhrnt_arr[VCOM_CCINST_SUBTP0_INHERENT_CNT] ={ +//[0] + { + .p_cc_setting = &t_vcom_custp0_setting_arr[0], + .func_desc_ass = vcom_func_inhrnt_desc_ass, + .func_desc_parse = vcom_func_inhrnt_desc_parse, + .func_bind = vcom_func_inhrnt_bind, + .func_get_desc = vcom_func_inhrnt_get_desc, + .func_get_othspd_desc = vcom_func_inhrnt_get_othspd_desc, + + .func_init = vcom_func_inhrnt_init, + .func_deinit = vcom_func_inhrnt_deinit, + .func_unbind = vcom_func_inhrnt_unbind, + }, + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT >=2) +//[1] + + { + .p_cc_setting = &t_vcom_custp0_setting_arr[1], + + .func_desc_ass = vcom_func_inhrnt_desc_ass, + .func_desc_parse = vcom_func_inhrnt_desc_parse, + .func_bind = vcom_func_inhrnt_bind, + .func_get_desc = vcom_func_inhrnt_get_desc, + .func_get_othspd_desc = vcom_func_inhrnt_get_othspd_desc, + + .func_init = vcom_func_inhrnt_init, + .func_deinit = vcom_func_inhrnt_deinit, + .func_unbind = vcom_func_inhrnt_unbind, + }, +#endif + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT >= 3) +//[2] + { + .p_cc_setting = &t_vcom_custp0_setting_arr[2], + .func_desc_ass = vcom_func_inhrnt_desc_ass, + .func_desc_parse = vcom_func_inhrnt_desc_parse, + .func_bind = vcom_func_inhrnt_bind, + .func_get_desc = vcom_func_inhrnt_get_desc, + .func_get_othspd_desc = vcom_func_inhrnt_get_othspd_desc, + + .func_init = vcom_func_inhrnt_init, + .func_deinit = vcom_func_inhrnt_deinit, + .func_unbind = vcom_func_inhrnt_unbind, + }, +#endif + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT >= 4) +//[3] + { + .p_cc_setting = &t_vcom_custp0_setting_arr[3], + .func_desc_ass = vcom_func_inhrnt_desc_ass, + .func_desc_parse = vcom_func_inhrnt_desc_parse, + .func_bind = vcom_func_inhrnt_bind, + .func_get_desc = vcom_func_inhrnt_get_desc, + .func_get_othspd_desc = vcom_func_inhrnt_get_othspd_desc, + + .func_init = vcom_func_inhrnt_init, + .func_deinit = vcom_func_inhrnt_deinit, + .func_unbind = vcom_func_inhrnt_unbind, + }, +#endif + +}; + +#endif + + + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/rndis_protocol.c b/PLAT/driver/chip/ec618/ap/src/usb/open/rndis_protocol.c new file mode 100644 index 0000000..2bf2b13 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/rndis_protocol.c @@ -0,0 +1,262 @@ +#include "bsp.h" +//#include "bsp_custom.h" +#ifndef USB_DRV_SMALL_IMAGE +#include "plat_config.h" +#include DEBUG_LOG_HEADER_FILE +#endif +#include "string.h" + +#include "rndis_protocol.h" +#include "usbmst_external.h" + +#define INFBUF ((uint32_t *)((uint8_t *)&(m->RequestId) + m->InformationBufferOffset)) +#define CFGBUF ((rndis_config_parameter_t *) INFBUF) +#define PARMNAME ((uint8_t *)CFGBUF + CFGBUF->ParameterNameOffset) +#define PARMVALUE ((uint8_t *)CFGBUF + CFGBUF->ParameterValueOffset) +#define PARMVALUELENGTH CFGBUF->ParameterValueLength +#define PARM_NAME_LENGTH 25 /* Maximum parameter name length */ + +#define MAC_OPT NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA | \ + NDIS_MAC_OPTION_RECEIVE_SERIALIZED | \ + NDIS_MAC_OPTION_TRANSFERS_NOT_PEND | \ + NDIS_MAC_OPTION_NO_LOOPBACK + +static const char *rndis_vendor = RNDIS_VENDOR; + + +const uint32_t OIDSupportedList[] = +{ + OID_GEN_SUPPORTED_LIST, + OID_GEN_HARDWARE_STATUS, + OID_GEN_MEDIA_SUPPORTED, + OID_GEN_MEDIA_IN_USE, + OID_GEN_MAXIMUM_FRAME_SIZE, + OID_GEN_LINK_SPEED, + OID_GEN_TRANSMIT_BLOCK_SIZE, + OID_GEN_RECEIVE_BLOCK_SIZE, + OID_GEN_VENDOR_ID, + OID_GEN_VENDOR_DESCRIPTION, + OID_GEN_VENDOR_DRIVER_VERSION, + OID_GEN_CURRENT_PACKET_FILTER, + OID_GEN_MAXIMUM_TOTAL_SIZE, + OID_GEN_PROTOCOL_OPTIONS, + OID_GEN_MAC_OPTIONS, + OID_GEN_MEDIA_CONNECT_STATUS, + OID_GEN_MAXIMUM_SEND_PACKETS, + OID_802_3_PERMANENT_ADDRESS, + OID_802_3_CURRENT_ADDRESS, + OID_802_3_MULTICAST_LIST, + OID_802_3_MAXIMUM_LIST_SIZE, + OID_802_3_MAC_OPTIONS +}; + +#define OID_LIST_LENGTH (sizeof(OIDSupportedList) / sizeof(*OIDSupportedList)) +#define ENC_BUF_SIZE (OID_LIST_LENGTH * 4 + 32) + +static const uint8_t station_hwaddr[6] = { RNDIS_HWADDR }; +static const uint8_t permanent_hwaddr[6] = { RNDIS_HWADDR }; +extern uint32_t connect_status; + +//used for malloc buffer +uint32_t RndisGetEncBufSize(void) +{ + return ENC_BUF_SIZE; +} + +void FuncRndisInitNotify(void) +{ +#if (!defined(USB_DRV_SMALL_IMAGE)) + usbDevNotifyRndisEvent(NOTIFY_MSG_INIT, NULL); +#endif +} + +void FuncRndisHaltNotify(void) +{ +#if (!defined(USB_DRV_SMALL_IMAGE)) + usbDevNotifyRndisEvent(NOTIFY_MSG_HALT, NULL); +#endif +} + +void FuncRndisResetNotify(void) +{ +#if (!defined(USB_DRV_SMALL_IMAGE)) + usbDevNotifyRndisEvent(NOTIFY_MSG_RESET, NULL); +#endif +} + + +void RdsProInitalMsgHdl(rndis_generic_msg_t *msgIn) +{ + rndis_initialize_cmplt_t *m; + m = ((rndis_initialize_cmplt_t *)msgIn); + /* m->MessageID is same as before */ + m->MessageType = REMOTE_NDIS_INITIALIZE_CMPLT; + m->MessageLength = sizeof(rndis_initialize_cmplt_t); + m->MajorVersion = RNDIS_MAJOR_VERSION; + m->MinorVersion = RNDIS_MINOR_VERSION; + m->Status = RNDIS_STATUS_SUCCESS; + m->DeviceFlags = RNDIS_DF_CONNECTIONLESS; + m->Medium = RNDIS_MEDIUM_802_3; + m->MaxPacketsPerTransfer = RNDIS_MAX_PACK_PER_XFER; + m->MaxTransferSize = RNDIS_RX_BUFFER_SIZE; + m->PacketAlignmentFactor = 0; + m->AfListOffset = 0; + m->AfListSize = 0; +} + +void RdsProQueryCmplt(rndis_query_msg_t *m, int status, const void *data, int size) +{ + rndis_query_cmplt_t *c = (rndis_query_cmplt_t *)m; + + c->MessageType = REMOTE_NDIS_QUERY_CMPLT; + c->MessageLength = sizeof(rndis_query_cmplt_t) + size; + c->InformationBufferLength = size; + c->InformationBufferOffset = 16; + c->Status = status; + memcpy(c + 1, data, size); +} + +void RdsProQueryCmplt32(rndis_query_msg_t *m, int status, uint32_t data) +{ + rndis_query_cmplt_t *c = (rndis_query_cmplt_t *)m; + + c->MessageType = REMOTE_NDIS_QUERY_CMPLT; + c->MessageLength = sizeof(rndis_query_cmplt_t) + 4; + c->InformationBufferLength = 4; + c->InformationBufferOffset = 16; + c->Status = status; + *(uint32_t *)(c + 1) = data; +} + +void RdsProQueryHdl(rndis_query_msg_t *m, rndis_ctrl_data_st *p_ctrl_data) +{ + switch (m->Oid) + { + case OID_GEN_SUPPORTED_LIST: RdsProQueryCmplt(m,RNDIS_STATUS_SUCCESS, OIDSupportedList, 4 * OID_LIST_LENGTH); return; + case OID_GEN_VENDOR_DRIVER_VERSION: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0x00001000); return; + case OID_802_3_CURRENT_ADDRESS: RdsProQueryCmplt(m,RNDIS_STATUS_SUCCESS, &station_hwaddr, 6); return; + case OID_802_3_PERMANENT_ADDRESS: RdsProQueryCmplt(m,RNDIS_STATUS_SUCCESS, &permanent_hwaddr, 6); return; + case OID_GEN_MEDIA_SUPPORTED: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, NDIS_MEDIUM_802_3); return; + case OID_GEN_MEDIA_IN_USE: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, NDIS_MEDIUM_802_3); return; + case OID_GEN_PHYSICAL_MEDIUM: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, NDIS_MEDIUM_802_3); return; + case OID_GEN_HARDWARE_STATUS: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + case OID_GEN_LINK_SPEED: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, RNDIS_LINK_SPEED / 100); return; + case OID_GEN_VENDOR_ID: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0x00FFFFFF); return; + case OID_GEN_VENDOR_DESCRIPTION: RdsProQueryCmplt(m,RNDIS_STATUS_SUCCESS, rndis_vendor, strlen(rndis_vendor) + 1); return; + case OID_GEN_CURRENT_PACKET_FILTER: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, p_ctrl_data->oid_packet_filter); return; + case OID_GEN_MAXIMUM_FRAME_SIZE: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, ETH_MAX_PACKET_SIZE - ETH_HEADER_SIZE); return; + case OID_GEN_MAXIMUM_TOTAL_SIZE: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, ETH_MAX_PACKET_SIZE); return; + case OID_GEN_TRANSMIT_BLOCK_SIZE: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, ETH_MAX_PACKET_SIZE); return; + case OID_GEN_RECEIVE_BLOCK_SIZE: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, ETH_MAX_PACKET_SIZE); return; + case OID_GEN_MEDIA_CONNECT_STATUS: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, connect_status); return; + case OID_GEN_RNDIS_CONFIG_PARAMETER: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + case OID_802_3_MAXIMUM_LIST_SIZE: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 1); return; + case OID_802_3_MULTICAST_LIST: RdsProQueryCmplt32(m,RNDIS_STATUS_NOT_SUPPORTED, 0); return; + case OID_802_3_MAC_OPTIONS: RdsProQueryCmplt32(m,RNDIS_STATUS_NOT_SUPPORTED, 0); return; + case OID_GEN_MAC_OPTIONS: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + case OID_802_3_RCV_ERROR_ALIGNMENT: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + case OID_802_3_XMIT_ONE_COLLISION: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + case OID_802_3_XMIT_MORE_COLLISIONS: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + case OID_GEN_XMIT_OK: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, p_ctrl_data->usb_eth_stat.txok); return; + case OID_GEN_RCV_OK: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, p_ctrl_data->usb_eth_stat.rxok); return; + case OID_GEN_RCV_ERROR: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, p_ctrl_data->usb_eth_stat.rxbad); return; + case OID_GEN_XMIT_ERROR: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, p_ctrl_data->usb_eth_stat.txbad); return; + case OID_GEN_RCV_NO_BUFFER: RdsProQueryCmplt32(m,RNDIS_STATUS_SUCCESS, 0); return; + default: RdsProQueryCmplt(m,RNDIS_STATUS_FAILURE, NULL, 0); return; + } +} + + + +void RdsProCfgParaHdl(const char *data, int keyoffset, int valoffset, int keylen, int vallen) +{ + (void)data; + (void)keyoffset; + (void)valoffset; + (void)keylen; + (void)vallen; +} + +void RdsProPktFilter(uint32_t newfilter) +{ + (void)newfilter; +} + +void RdsProSetMsgHdl(rndis_set_msg_t *msgIn, rndis_ctrl_data_st *p_ctrl_data) +{ + rndis_set_cmplt_t *c; + rndis_set_msg_t *m; + rndis_Oid_t oid; + + c = (rndis_set_cmplt_t *)msgIn; + m = (rndis_set_msg_t *)msgIn; + + oid = m->Oid; + c->MessageType = REMOTE_NDIS_SET_CMPLT; + c->MessageLength = sizeof(rndis_set_cmplt_t); + c->Status = RNDIS_STATUS_SUCCESS; + + switch (oid) + { + case OID_GEN_RNDIS_CONFIG_PARAMETER: + { + rndis_config_parameter_t *p; + char *ptr = (char *)m; + ptr += sizeof(rndis_generic_msg_t); + ptr += m->InformationBufferOffset; + p = (rndis_config_parameter_t *)ptr; + RdsProCfgParaHdl(ptr, p->ParameterNameOffset, p->ParameterValueOffset, p->ParameterNameLength, p->ParameterValueLength); + } + break; + + case OID_GEN_CURRENT_PACKET_FILTER: + p_ctrl_data->oid_packet_filter = *INFBUF; + if (p_ctrl_data->oid_packet_filter) + { + RdsProPktFilter(p_ctrl_data->oid_packet_filter); + p_ctrl_data->rndis_state = rndis_data_initialized; + } + else + { + p_ctrl_data->rndis_state = rndis_initialized; + } + break; + + case OID_GEN_CURRENT_LOOKAHEAD: + break; + + case OID_GEN_PROTOCOL_OPTIONS: + break; + + case OID_802_3_MULTICAST_LIST: + break; + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + case OID_PNP_ENABLE_WAKE_UP: + default: + c->Status = RNDIS_STATUS_FAILURE; + break; + } + + return; +} + +void RdsProResetMsgHdl(rndis_reset_cmplt_t *m, rndis_ctrl_data_st *p_ctrl_data) +{ + p_ctrl_data->rndis_state = rndis_uninitialized; + m->MessageType = REMOTE_NDIS_RESET_CMPLT; + m->MessageLength = sizeof(rndis_reset_cmplt_t); + m->Status = RNDIS_STATUS_SUCCESS; + m->AddressingReset = 1; +} + +void RdsProKeepAliveMsgHdl(rndis_keepalive_cmplt_t *m, uint32_t RequestId, rndis_ctrl_data_st *p_ctrl_data) +{ + (void)p_ctrl_data; + m->RequestId = RequestId; + + m->MessageType = REMOTE_NDIS_KEEPALIVE_CMPLT; + m->MessageLength = sizeof(rndis_keepalive_cmplt_t); + m->Status = RNDIS_STATUS_SUCCESS; +} + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/usb_portmon.c b/PLAT/driver/chip/ec618/ap/src/usb/open/usb_portmon.c new file mode 100644 index 0000000..bee4f21 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/usb_portmon.c @@ -0,0 +1,378 @@ +#include "FreeRTOS.h" +#include "cmsis_os2.h" +#include "usb_portmon.h" +#include "apmu_external.h" +#include "plat_config.h" +#include "string.h" +#include "bsp_custom.h" +#include "slpman.h" +#include "usb_ext_inc.h" + +#include DEBUG_LOG_HEADER_FILE +typedef int (*pfn_PadWakeupHook)(uint32_t pad_num); + + +osEventFlagsId_t vBusEvtFlags = NULL; +#define USB_VBUS_EVT_FLAG 1 +//5 for module AirM2M E3 BOARD vbus pad +//#define USB_WKUP_PAD_IDX 5 +//for module AirM2M E1 BOARD vbus pad +uint8_t usb_wkup_pad_idx = 1; +#define VBUS_FILTER_MAX_SAMPLE_CNT 10 + +extern uint8_t usbstack_clear_ctx_stat(void); +extern uint8_t usbstack_ctx_stat_ison(void); +extern uint8_t usbstack_ctx_stat_isoff(void); +extern uint8_t usbstack_get_ctx_stat(void); +extern void usbstack_set_ctx_vbus_mode(uint8_t vbus_mode_en, uint8_t vbus_pad_idx); +extern void usbstack_top_var_clear(void); + +extern int RegPadWakeupIntrHook(pfn_PadWakeupHook pfunc); + + + + +extern void BSP_UsbDeInit(void); +extern void BSP_UsbInit(void); +int usb_portmon_intr_cb(void); +int Pad1WakeupHook(void); +int PadCmnWakeupHook(uint32_t pad_num); + +void usb_portmon_padcfg(void) +{ + APmuWakeupPadSettings_t wakeupPadSetting; + wakeupPadSetting.negEdgeEn = true; + wakeupPadSetting.posEdgeEn = true; + wakeupPadSetting.pullDownEn = false; + wakeupPadSetting.pullUpEn = false; + apmuSetWakeupPadCfg(usb_wkup_pad_idx, true, &wakeupPadSetting); +} + +uint8_t usb_portmon_wkuppad_level(uint32_t idx); + +uint8_t usb_portmon_vbuspad_level(void) +{ + return usb_portmon_wkuppad_level(usb_wkup_pad_idx); +} + + +#define USB_PORTMON_WAIT_INIT_START 10 +#define USB_PORTMON_WAIT_FILTER 10 +#define USB_PORTMON_WAIT_ALWAYS 0xffffffff + +typedef enum { + usb_portmon_state_none= 0, + usb_portmon_state_filter_reset = 1, + usb_portmon_state_filter_sample = 2, + usb_portmon_state_trigger = 3, + usb_portmon_state_stable = 4, +}usb_portmon_state_type; + +uint32_t usb_portmon_stat = usb_portmon_state_none; + +usb_portmon_state_type usb_portmon_getstat(void) +{ + return usb_portmon_stat; +} + +void usb_portmon_setstat(usb_portmon_state_type stat) +{ + usb_portmon_stat = stat; +} + +uint8_t vbus_val_last = 0; + +int usb_portmon_init(void) +{ + uint32_t ret; + usbstack_clear_ctx_stat(); + vBusEvtFlags = osEventFlagsNew(NULL); + if (vBusEvtFlags== NULL) + { + EC_ASSERT((0), 0, 0, 0); + } + + usb_wkup_pad_idx = BSP_UsbGetVBUSWkupPad(); + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_portmon_init_1, P_WARNING, 1,"usb_wkup_pad_idx %d", usb_wkup_pad_idx); + + if (usb_wkup_pad_idx>WAKEUP_PAD_5) + { + EC_ASSERT(0, usb_wkup_pad_idx, WAKEUP_PAD_5, 0); + } + + usbstack_top_var_clear(); + usbstack_set_ctx_vbus_mode(1,usb_wkup_pad_idx); + + NVIC_DisableIRQ(PadWakeup0_IRQn+usb_wkup_pad_idx); + NVIC_ClearPendingIRQ(PadWakeup0_IRQn+usb_wkup_pad_idx); + + ret = RegPadWakeupIntrHook(PadCmnWakeupHook); + EC_ASSERT((ret==0), 0, 0, 0); + + + usb_portmon_stat = usb_portmon_state_filter_reset; + usb_portmon_padcfg(); + NVIC_EnableIRQ(PadWakeup0_IRQn+usb_wkup_pad_idx); + return 0; +} + +int usb_portmon_deinit(void){ + NVIC_DisableIRQ(PadWakeup0_IRQn+usb_wkup_pad_idx); + if (vBusEvtFlags !=NULL){ + osEventFlagsDelete(vBusEvtFlags); + vBusEvtFlags = NULL; + } + usb_portmon_stat = usb_portmon_state_none; + return 0; +} + + +uint8_t usbpm_vote_handle = 0xff; + +void usb_portmon_task(void *arg) +{ + uint32_t vbus_evtflag; + uint32_t vbus_filter_sample_cnt = 0; + uint8_t vbus_val_cur = 0; + slpManApplyPlatVoteHandle("usbpm", &usbpm_vote_handle); + slpManPlatVoteDisableSleep(usbpm_vote_handle, SLP_SLP2_STATE); + + usb_portmon_init(); + + uint32_t usb_portmon_wait = USB_PORTMON_WAIT_ALWAYS; + while(1) + { + switch (usb_portmon_getstat()) + { + case usb_portmon_state_none: + usb_portmon_setstat(usb_portmon_state_filter_reset); + break; + case usb_portmon_state_filter_reset: + + usb_portmon_wait = USB_PORTMON_WAIT_INIT_START; + vbus_evtflag = 0; + vbus_evtflag = osEventFlagsWait (vBusEvtFlags, USB_VBUS_EVT_FLAG, osFlagsWaitAny, usb_portmon_wait); + vbus_val_last = usb_portmon_vbuspad_level(); + + //reset vbus fileter sample cnt + vbus_filter_sample_cnt = 0; + if (vbus_evtflag&USB_VBUS_EVT_FLAG) + { + //filtered type 3, likely + //detect evt in stable state, delay USB_PORTMON_WAIT_FILTER in filter state, detect evt again continuously in USB_PORTMON_WAIT_FILTER + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_portmon_task_1_1, P_WARNING, 2,"filter reset detect evt %x, vbus %d", vbus_evtflag, usb_portmon_vbuspad_level() ); + } + else if (vbus_evtflag == osErrorTimeout) + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_portmon_task_1_2, P_WARNING, 2,"filter reset (to) evt %x, vbus %d", vbus_evtflag, usb_portmon_vbuspad_level() ); + } + usb_portmon_setstat(usb_portmon_state_filter_sample); + break; + case usb_portmon_state_filter_sample: + usb_portmon_wait = USB_PORTMON_WAIT_FILTER; + vbus_evtflag = 0; + vbus_evtflag = osEventFlagsWait (vBusEvtFlags, USB_VBUS_EVT_FLAG, osFlagsWaitAny, usb_portmon_wait); + if (vbus_evtflag&USB_VBUS_EVT_FLAG) + { + //filtered type 3, likely + //detect evt in stable state, delay USB_PORTMON_WAIT_FILTER in filter state, detect evt again continuously in USB_PORTMON_WAIT_FILTER + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_portmon_task_2_1, P_WARNING, 2,"port filtered unstable evt %x, vbus %d", vbus_evtflag, usb_portmon_vbuspad_level() ); + usb_portmon_setstat(usb_portmon_state_filter_reset); + break; + } + + if (vbus_evtflag == osErrorTimeout) + { + vbus_val_cur = usb_portmon_vbuspad_level(); + + if (vbus_val_last!=vbus_val_cur) + { + //unlikely + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_portmon_task_2_2, P_WARNING, 2,"port vbus filter unstable level vbus last %d,vbus cur = %d", vbus_val_last, vbus_val_cur); + usb_portmon_setstat(usb_portmon_state_filter_reset); + + vbus_val_last = vbus_val_cur; + break; + } + + //anyway update vbus_val_last + vbus_val_last = vbus_val_cur; + + //vbus_val_last==vbus_val_cur case + //add vbus fileter sample cnt + vbus_filter_sample_cnt++; + if(vbus_filter_sample_cntusb_portmon_state_none) + { + if (vBusEvtFlags) + { + osEventFlagsSet (vBusEvtFlags, USB_VBUS_EVT_FLAG); + } + } + return 0; +} + +int Pad1WakeupHook(void) +{ + return usb_portmon_intr_cb(); +} + +int Pad5WakeupHook(void) +{ + return usb_portmon_intr_cb(); +} + +int PadCmnWakeupHook(uint32_t pad_num) +{ + if (pad_num==usb_wkup_pad_idx) + { + switch (usb_wkup_pad_idx) + { + case 1: + Pad1WakeupHook(); + break; + case 5: + Pad5WakeupHook(); + break; + default: + break; + } + } + return 0; +} + +#if (RTE_USB_EN == 1) +#define USBPORTON_TASK_STACK_SIZE (1024) +static uint8_t usb_portmon_task_stack[USBPORTON_TASK_STACK_SIZE]; +static StaticTask_t usb_portmon_task_tcb; + +//share task stack_ptr +uint8_t *usb_wkmon_portmon_share_stack_ptr(void) +{ + return &(usb_portmon_task_stack[0]); +} + +uint32_t usb_wkmon_portmon_share_stack_size(void) +{ + return USBPORTON_TASK_STACK_SIZE; +} + + +void usb_portmon_task_init(void) +{ + osThreadAttr_t task_attr; + uint8_t * stack_ptr = usb_wkmon_portmon_share_stack_ptr(); + uint32_t stack_size = usb_wkmon_portmon_share_stack_size(); + + memset(&task_attr,0,sizeof(task_attr)); + memset(stack_ptr, 0xA5,stack_size); + task_attr.name = "usbpm"; + task_attr.stack_mem = stack_ptr; + task_attr.stack_size = stack_size; + task_attr.priority = osPriorityNormal; + task_attr.cb_mem = &usb_portmon_task_tcb;//task control block + task_attr.cb_size = sizeof(StaticTask_t);//size of task control block + + osThreadNew(usb_portmon_task, NULL, &task_attr); +} +#endif + + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/usb_wkmon.c b/PLAT/driver/chip/ec618/ap/src/usb/open/usb_wkmon.c new file mode 100644 index 0000000..d27e0bb --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/usb_wkmon.c @@ -0,0 +1,596 @@ +#include "FreeRTOS.h" +#include "cmsis_os2.h" +#include "usb_wkmon.h" +#include "apmu_external.h" +#include "plat_config.h" +#include "string.h" +#include "bsp_custom.h" +#include "slpman.h" +#include DEBUG_LOG_HEADER_FILE +#include "usb_ext_inc.h" +#include "task.h" +#include "usbd_errinfo.h" +//#include "gpr.h" + +#if (USB_WKMON_TASK_EXIST==1) +typedef enum { + usb_wkmon_state_uninit = 0, + usb_wkmon_state_idle = 1, + usb_wkmon_state_start, + + usb_wkmon_state_detecting, + usb_wkmon_state_actv, + usb_wkmon_state_succ , + usb_wkmon_state_terminate, + +}usb_wkmon_state_type; + +uint32_t usb_wkmon_stat = usb_wkmon_state_uninit; + +void usb_wkmon_setstat(usb_wkmon_state_type stat); + + +osEventFlagsId_t LPUsbWkStatEvtFlags = NULL; +osEventFlagsId_t LPUsbWkDetEvtFlags = NULL; + +#define USB_RETWKUP_STAT_EVT_UPD_FLAG (1UL<0) +#define USB_RETWKUP_STAT_EVT_START_FLAG (1UL<<1) +#define USB_RETWKUP_STAT_EVT_RESET_FLAG (1UL<<2) + +#define USB_RETWKUP_DEV_EVT_UPD_FLAG (1UL<0) +#define USB_RETWKUP_DEV_EVT_TRIG_FLAG (1UL<<1) +#define USB_RETWKUP_DEV_EVT_RESET_FLAG (1UL<<2) + +typedef int (*pfn_LPUsbWkupHook)(void); +extern int RegLPUSBWkupIntrHook(pfn_LPUsbWkupHook pfunc); + + +int usb_wkmon_intr_cb(void); +int USBMonLPWkupIRQHook(void); +//#define TEST_LOW_USB_HCLK +int usb_wkmon_pre_init(void) +{ + uint32_t ret; + + usb_wkmon_stat = usb_wkmon_state_uninit; + +#ifdef TEST_LOW_USB_HCLK + GPR_clockEnable(CLK_HF102M); + GPR_setClockSrc(CLK_CC, CLK_CC_SEL_102M); +#endif + + LPUsbWkStatEvtFlags = osEventFlagsNew(NULL); + if (LPUsbWkStatEvtFlags== NULL) + { + EC_ASSERT((0), 0, 0, 0); + } + + LPUsbWkDetEvtFlags = osEventFlagsNew(NULL); + if (LPUsbWkDetEvtFlags== NULL) + { + EC_ASSERT((0), 0, 0, 0); + } + + if (NVIC_GetEnableIRQ(LpusbWakeup_IRQn)) + { + //illegal LpusbWakeup_IRQn before start + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usblpw_get_retothwk_proc_stat()); + } + + ret = RegLPUSBWkupIntrHook(USBMonLPWkupIRQHook); + EC_ASSERT((ret==0), 0, 0, 0); + usb_wkmon_setstat(usb_wkmon_state_idle); + + return 0; +} + + +int usb_wkmon_cmmon_clear(void){ + usblpw_wkmon_ll_enter_ctx_clear(); + usblpw_wkmon_lpusbwkup_flag_clear(); + +#ifdef TEST_LOW_USB_HCLK + GPR_clockEnable(CLK_HF102M); + + GPR_setClockSrc(CLK_CC, CLK_CC_SEL_102M); +#endif + return 0; +} + +int usb_wkmon_deinit(void){ + if (LPUsbWkStatEvtFlags !=NULL){ + osEventFlagsDelete(LPUsbWkStatEvtFlags); + LPUsbWkStatEvtFlags = NULL; + } + if (LPUsbWkDetEvtFlags !=NULL){ + osEventFlagsDelete(LPUsbWkDetEvtFlags); + LPUsbWkDetEvtFlags = NULL; + } + + + usb_wkmon_setstat(usb_wkmon_state_uninit); + return 0; +} + +int usb_wkmon_hibslp2_stat_evt_start(void) +{ + uint32_t stat_evtflag; + uint32_t det_evtflag; + if (LPUsbWkDetEvtFlags) + { + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG |USB_RETWKUP_DEV_EVT_TRIG_FLAG | USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsClear(LPUsbWkDetEvtFlags, det_evtflag); + + //any uncleared stat abort + det_evtflag = USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsSet (LPUsbWkDetEvtFlags, det_evtflag); + } + + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + + stat_evtflag = USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsSet (LPUsbWkStatEvtFlags, stat_evtflag); + } + return 0; +} + +int usb_wkmon_slp1_stat_evt_start(void) +{ + uint32_t stat_evtflag; + uint32_t det_evtflag; + uint32_t irqflag; + + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_slp1_stat_evt_start_1, P_WARNING, 3,"usb_wkmon_stat %d, det evt 0x%x, stat evt 0x%x", usb_wkmon_stat, LPUsbWkDetEvtFlags, LPUsbWkStatEvtFlags); + irqflag = SaveAndSetIRQMask(); + + switch (usb_wkmon_stat) + { + case usb_wkmon_state_idle: + if (LPUsbWkDetEvtFlags) + { + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG |USB_RETWKUP_DEV_EVT_TRIG_FLAG | USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsClear(LPUsbWkDetEvtFlags, det_evtflag); + + //any uncleared stat abort + det_evtflag = USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsSet (LPUsbWkDetEvtFlags, det_evtflag); + } + + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + + stat_evtflag = USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsSet (LPUsbWkStatEvtFlags, stat_evtflag); + } + break; + + case usb_wkmon_state_start: + //unlikely here, this stat is sleep disabled + case usb_wkmon_state_actv: + //unlikely , this stat is sleep disabled, deal as all reset + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_slp1_stat_evt_start_2, P_WARNING, 0,"usb_wkmon_stat unlikely"); + + case usb_wkmon_state_detecting: + + //abort detecting and reset to none + if (LPUsbWkDetEvtFlags) + { + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG |USB_RETWKUP_DEV_EVT_TRIG_FLAG | USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsClear(LPUsbWkDetEvtFlags,det_evtflag); + + //any uncleared stat abort + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG; + osEventFlagsSet (LPUsbWkDetEvtFlags, det_evtflag); + } + + //start + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + + stat_evtflag = USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsSet (LPUsbWkStatEvtFlags, stat_evtflag); + } + + break; + case usb_wkmon_state_succ: + //start + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG|USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsSet (LPUsbWkStatEvtFlags, stat_evtflag); + } + break; + default: + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usb_wkmon_stat); + break; + } + RestoreIRQMask(irqflag); + + return 0; +} + + +int usb_wkmon_slp1_nothwk_evt_reset(void) +{ + uint32_t stat_evtflag; + uint32_t det_evtflag; + uint32_t irqflag; + + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_slp1_nothwk_evt_reset_1, P_WARNING, 3,"usb_wkmon_stat %d, det evt 0x%x, stat evt 0x%x", usb_wkmon_stat, LPUsbWkDetEvtFlags, LPUsbWkStatEvtFlags); + irqflag = SaveAndSetIRQMask(); + + switch (usb_wkmon_stat) + { + case usb_wkmon_state_uninit: + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_slp1_stat_evt_start_uninit, P_WARNING, 0," "); + break; + case usb_wkmon_state_idle: + if (LPUsbWkDetEvtFlags) + { + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG |USB_RETWKUP_DEV_EVT_TRIG_FLAG | USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsClear(LPUsbWkDetEvtFlags, det_evtflag); + } + + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + } + break; + + case usb_wkmon_state_start: + //unlikely here, this stat is sleep disabled + case usb_wkmon_state_actv: + //unlikely , this stat is sleep disabled, deal as all reset + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_slp1_stat_evt_start_2, P_WARNING, 0,"usb_wkmon_stat unlikely"); + + case usb_wkmon_state_detecting: + + //abort detecting and reset to none + if (LPUsbWkDetEvtFlags) + { + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG |USB_RETWKUP_DEV_EVT_TRIG_FLAG | USB_RETWKUP_DEV_EVT_UPD_FLAG; + osEventFlagsClear(LPUsbWkDetEvtFlags,det_evtflag); + + //any uncleared stat abort + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG; + osEventFlagsSet (LPUsbWkDetEvtFlags, det_evtflag); + } + + //start + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG; + osEventFlagsSet (LPUsbWkStatEvtFlags, stat_evtflag); + } + + break; + case usb_wkmon_state_succ: + //start + if (LPUsbWkStatEvtFlags) + { + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG | USB_RETWKUP_STAT_EVT_START_FLAG|USB_RETWKUP_STAT_EVT_UPD_FLAG; + osEventFlagsClear (LPUsbWkStatEvtFlags, stat_evtflag); + + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG; + osEventFlagsSet (LPUsbWkStatEvtFlags, stat_evtflag); + } + break; + default: + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usb_wkmon_stat); + break; + } + RestoreIRQMask(irqflag); + + return 0; +} + + +usb_wkmon_state_type usb_wkmon_getstat(void) +{ + return usb_wkmon_stat; +} + +void usb_wkmon_setstat(usb_wkmon_state_type stat) +{ + usb_wkmon_stat = stat; +} + +void BSP_UsbWkIRQLog(void); +//uint8_t BSP_UsbRetOthWkLaterRestOnly(void); + + +uint8_t usbwkm_vote_handle = 0xff; + +//5ms +//#define USBWKM_DET_WAIT_TIME 5 +uint8_t usblpw_rd_reg_retwkup_ctxstat(void); + +void usb_wkmon_task(void *arg) +{ + uint32_t stat_evtflag; + uint32_t det_evtflag; + + uint32_t stat_evt_retval; + uint32_t det_evt_retval; + + uint32_t irqflag; + + uint8_t ret; + uint8_t stage; + usb_wkmon_setstat(usb_wkmon_state_idle); + + slpManApplyPlatVoteHandle("usbwk", &usbwkm_vote_handle); + //slpManPlatVoteDisableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + while(1) + { + switch (usb_wkmon_getstat()) + { + case usb_wkmon_state_idle: + stat_evtflag = USB_RETWKUP_STAT_EVT_START_FLAG | USB_RETWKUP_STAT_EVT_UPD_FLAG; + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_none_0, P_INFO, 0,"start"); + stat_evt_retval = osEventFlagsWait (LPUsbWkStatEvtFlags, stat_evtflag, osFlagsWaitAny, portMAX_DELAY); + stage = usblpw_retothwk_get_cur_stg(); + + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_none_1, P_INFO, 2,"stage 0x%x, stat_evt_retval:0x%x", stage, stat_evt_retval); + + if (stat_evt_retval&USB_RETWKUP_STAT_EVT_START_FLAG) + { + if ((usblpw_retothwk_cur_stg_hibslp2_wkmon()==0) &&(usblpw_retothwk_cur_stg_slp1_wkmon()==0)) + { + //only enabled from wkmon is legal + //ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_none_2, P_WARNING, 1,"wkmon stage %d not match", stage); + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usblpw_get_retothwk_proc_stat()); + break; + //continue; + } + + slpManPlatVoteDisableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + usb_wkmon_setstat(usb_wkmon_state_start); + break; + } + else if (stat_evt_retval&0x80000000) + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_none_3, P_WARNING, 1,"stat_evt_retval err 0x%x", stat_evt_retval); + } + else + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_none_4, P_WARNING, 1,"stat_evt_retval no proc 0x%x", stat_evt_retval); + } + break; + case usb_wkmon_state_start: + if (NVIC_GetEnableIRQ(LpusbWakeup_IRQn)) + { + //illegal LpusbWakeup_IRQn before start + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usblpw_get_retothwk_proc_stat()); + break; + } + + irqflag = SaveAndSetIRQMask(); + //enable here after the wkup irq hook, otherwise the irq may not clear in irq hook + usblpw_enable_lpusbwkup_src(); + usblpw_wkmon_lpusbwkup_flag_set(); + usb_wkmon_setstat(usb_wkmon_state_detecting); + slpManPlatVoteEnableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + //because no usb drv is active here, so enable + slpManDrvVoteSleep(SLP_VOTE_LPUSB, SLP_SLP1_STATE); + RestoreIRQMask(irqflag); + break; + + case usb_wkmon_state_detecting: + det_evt_retval = 0; + det_evtflag = USB_RETWKUP_DEV_EVT_RESET_FLAG | USB_RETWKUP_DEV_EVT_TRIG_FLAG | USB_RETWKUP_DEV_EVT_UPD_FLAG; + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_0_0, P_INFO, 0,"usb_wkmon_state_detecting start"); + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_0_1, P_INFO, 1,"ctx stat reg %d", usblpw_rd_reg_retwkup_ctxstat()); + + //may sleep here, current is enable sleep default + det_evt_retval = osEventFlagsWait (LPUsbWkDetEvtFlags, det_evtflag, osFlagsWaitAny, portMAX_DELAY); + + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_1, P_INFO, 1,"det_evt_retval:0x%x", det_evt_retval); + if (det_evt_retval&USB_RETWKUP_DEV_EVT_TRIG_FLAG) + { + //tirg stat, sleep is disabled by irq hook + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_2, P_WARNING, 0,"detect evt succ"); + ret = usblpw_retothwk_wkmon_idle_to_actv_proc(); + if (ret !=0) + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_3_1, P_WARNING, 0,"usblpw_retothwk_wkmon_idle_to_actv_proc fail"); + usb_wkmon_setstat(usb_wkmon_state_terminate); + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usblpw_get_retothwk_proc_stat()); + //assert here + break; + } + if (usblpw_retothwk_cur_proc_stat_gpwr_umatch()) + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_3_2, P_WARNING, 0,"usblpw_retothwk_wkmon_idle_to_actv_proc more detecting"); + + irqflag = SaveAndSetIRQMask(); + //enable here after the wkup irq hook, otherwise the irq may not clear in irq hook + usblpw_enable_lpusbwkup_src(); + usblpw_wkmon_lpusbwkup_flag_set(); + usb_wkmon_setstat(usb_wkmon_state_detecting); + slpManPlatVoteEnableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + //because no usb drv is active here, so enable + slpManDrvVoteSleep(SLP_VOTE_LPUSB, SLP_SLP1_STATE); + RestoreIRQMask(irqflag); + break; + } + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_4, P_WARNING, 0,"usblpw_retothwk_wkmon_idle_to_actv_proc succ"); + + usb_wkmon_setstat(usb_wkmon_state_actv); + } + else if (det_evt_retval&USB_RETWKUP_DEV_EVT_RESET_FLAG) + { + //must be triggered by sleep1 + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_5, P_WARNING, 0,"detecting reset event "); + + //unlikely just wait for next trigger, restart + usb_wkmon_setstat(usb_wkmon_state_idle); + } + else if (det_evt_retval == osErrorTimeout) + { + //slpManPlatVoteEnableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_6, P_WARNING, 0,"detect (to) "); + usb_wkmon_setstat(usb_wkmon_state_detecting); + } + else + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_1_7, P_WARNING, 0,"unknown event "); + + //unlikely just wait for next trigger, restart + slpManPlatVoteEnableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + usb_wkmon_setstat(usb_wkmon_state_start); + } + break; + + case usb_wkmon_state_actv: + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_2_0, P_WARNING, 0,"usblpw_retothwk_wkmon_actv_proc start"); + + ret = usblpw_retothwk_wkmon_actv_proc(); + if (ret != 0) + { + //terminate laterdet or assert + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_2_1, P_WARNING, 0,"usblpw_retothwk_wkmon_actv_proc fail"); + usb_wkmon_setstat(usb_wkmon_state_terminate); + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usblpw_get_retothwk_proc_stat()); + break; + } + + if (usblpw_retothwk_cur_stg_success()==0) + { + usb_wkmon_setstat(usb_wkmon_state_terminate); + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usblpw_get_retothwk_proc_stat()); + } + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_2_2, P_WARNING, 0,"usblpw_retothwk_wkmon_actv_proc succ"); + + usblpw_wkmon_lpusbwkup_flag_clear(); + usb_wkmon_setstat(usb_wkmon_state_succ);// try next loopo + + break; + case usb_wkmon_state_succ: + stat_evtflag = USB_RETWKUP_STAT_EVT_RESET_FLAG; + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_succ_0, P_INFO, 0,"start"); + + slpManPlatVoteEnableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + stat_evt_retval = osEventFlagsWait (LPUsbWkStatEvtFlags, stat_evtflag, osFlagsWaitAny, portMAX_DELAY); + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_succ_1, P_INFO, 1,"stat_evt_retval:0x%x", stat_evt_retval); + if (stat_evt_retval&USB_RETWKUP_STAT_EVT_RESET_FLAG) + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_succ_2, P_WARNING, 0,"stat_evt_retval reset"); + usb_wkmon_setstat(usb_wkmon_state_idle); + break; + } + else if (stat_evt_retval&0x80000000) + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_succ_3, P_WARNING, 0,"stat_evt_retval err "); + } + else + { + ECOMM_TRACE(UNILOG_PLA_DRIVER, usb_wkmon_task_state_succ_4, P_WARNING, 0, "stat_evt_retval default proc as reset"); + usb_wkmon_setstat(usb_wkmon_state_idle); + } + break; + + default: + EC_ASSERT(0, usbd_get_mod_last_err(), usblpw_retothwk_get_cur_stg(), usb_wkmon_getstat()); + break; + } + } +} + +void BSP_LPUsbWkIRQLog(void) +{ + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, BSP_LPUsbWkIRQLog_1, P_VALUE, "othwkup stage %d, proc_stat %d", usblpw_get_retothwk_stage(), usblpw_get_retothwk_proc_stat()); +} + + +int usb_wkmon_intr_cb(void) +{ + if ((usblpw_retothwk_cur_stg_hibslp2_wkmon()) || (usblpw_retothwk_cur_stg_slp1_wkmon())) + { + if (usb_wkmon_getstat()==usb_wkmon_state_detecting) + { + //the legal wkmon stat is usb_wkmon_state_detecting for dev event + osEventFlagsSet (LPUsbWkDetEvtFlags, USB_RETWKUP_DEV_EVT_TRIG_FLAG|USB_RETWKUP_DEV_EVT_UPD_FLAG); + NVIC_DisableIRQ(LpusbWakeup_IRQn); + slpManPlatVoteDisableSleep(usbwkm_vote_handle, SLP_SLP1_STATE); + } + else + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usb_wkmon_intr_cb_1_0, P_VALUE, "usb_wkmon_stat %d not match, no event sent", usb_wkmon_getstat()); + } + + if (usblpw_wkmon_ll_enter_ctx_get()) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usb_wkmon_intr_cb_1_1, P_VALUE, "chk_abort_ll_inirq, wkmon_lpusbwkup_flag %x", usblpw_wkmon_lpusbwkup_flag_get()); + + usblpw_enter_wkmon_chk_abort_ll_inirq(); + } + } + else if (usblpw_retothwk_cur_stg_none()==0) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usb_wkmon_intr_cb_2, P_VALUE, "unlegal stag"); + } + + return 0; +} + +int USBMonLPWkupIRQHook(void) +{ + BSP_LPUsbWkIRQLog(); + return usb_wkmon_intr_cb(); +} + +#define USBWKM_TASK_STACK_SIZE (1024) +//#define USB_WKMON_PRIVATE_STACK +#ifdef USB_WKMON_PRIVATE_STACK +static uint8_t usb_wkmon_task_stack[USBWKM_TASK_STACK_SIZE]; +static StaticTask_t usb_wkmon_task_tcb; + +uint8_t *usb_wkmon_get_stack_ptr(void) +{ + return &(usb_wkmon_task_stack[0]); +} + +uint32_t usb_wkmon_get_stack_size(void) +{ + return USBWKM_TASK_STACK_SIZE; +} +#else +static StaticTask_t usb_wkmon_task_tcb; + +extern uint8_t *usb_wkmon_portmon_share_stack_ptr(void); +extern uint32_t usb_wkmon_portmon_share_stack_size(void); + +#endif +void usb_wkmon_task_init(void) +{ + osThreadAttr_t task_attr; + uint8_t * stack_ptr = usb_wkmon_portmon_share_stack_ptr(); + uint32_t stack_size = usb_wkmon_portmon_share_stack_size(); + memset(&task_attr,0,sizeof(task_attr)); + memset(stack_ptr, 0xA5,stack_size); + task_attr.name = "usbwkm"; + task_attr.stack_mem = stack_ptr; + task_attr.stack_size = stack_size; + task_attr.priority = osPriorityNormal; + task_attr.cb_mem = &usb_wkmon_task_tcb;//task control block + task_attr.cb_size = sizeof(StaticTask_t);//size of task control block + + osThreadNew(usb_wkmon_task, NULL, &task_attr); +} +#endif + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/usbd_multi_usrcfg_custom.c b/PLAT/driver/chip/ec618/ap/src/usb/open/usbd_multi_usrcfg_custom.c new file mode 100644 index 0000000..1a5de80 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/usbd_multi_usrcfg_custom.c @@ -0,0 +1,979 @@ +#include "FreeRTOS.h" +#include "cmsis_os2.h" +#include "plat_config.h" +#include "string.h" +#include "usbd_clscdc.h" +#include "usbd_func_cc.h" +#include "usbd_multi_usrcfg_common.h" + +#ifndef USB_DRV_SMALL_IMAGE +#include "plat_config.h" + +#include DEBUG_LOG_HEADER_FILE +#endif +#include "RTE_Device.h" + +#define USBD_MULTIDEV_LOAD_FAIL 1 + +#define EP_REMAP_CUSTOM_CNT 13 + +#define CUST_DEF_TEST_TYPE1 +//#define CUST_DEF_TEST_TYPE3 + +//#define USBD_EMC_MAC_CONFIG +#ifdef USBD_EMC_MAC_CONFIG + +extern uint8_t *ecm_dev_local_string[1]; +void update_ecm_mac(void) +{ +#ifndef USB_DRV_SMALL_IMAGE + ecm_dev_local_string[0] = (uint8_t*)"2089846a96ab";//update the ecm mac here +#endif +} +#endif + +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT>0) +extern usb_func_ccinst_st t_vcom_func_custp0_inhrnt_arr[VCOM_CCINST_SUBTP0_INHERENT_CNT]; +#endif + +extern usb_func_ccinst_st t_vcom_func_custp1_arr[VCOM_CCINST_SUBTP1_2EP_CNT]; +extern usb_func_ccinst_st t_vcom_func_custp2_arr[VCOM_CCINST_SUBTP2_3EP_CNT]; + +typedef struct { + uint8_t vcom_ccinst_subtp0_inhrnt_cnt; + uint8_t vcom_ccinst_subtp1_2ep_cnt; + uint8_t vcom_ccinst_subtp2_3ep_cnt; + usb_func_ccinst_st *p_vcom_ccinst_subtp0_entry; + usb_func_ccinst_st *p_vcom_ccinst_subtp1_entry; + usb_func_ccinst_st *p_vcom_ccinst_subtp2_entry; + +}usbd_multidev_ccinst_res_st; + +usbd_multidev_ccinst_res_st t_usbd_multidev_ccinst_res = +{ + .vcom_ccinst_subtp0_inhrnt_cnt = VCOM_CCINST_SUBTP0_INHERENT_CNT, + .vcom_ccinst_subtp1_2ep_cnt = VCOM_CCINST_SUBTP1_2EP_CNT, + .vcom_ccinst_subtp2_3ep_cnt = VCOM_CCINST_SUBTP2_3EP_CNT, +#if (VCOM_CCINST_SUBTP0_INHERENT_CNT>0) + .p_vcom_ccinst_subtp0_entry = &(t_vcom_func_custp0_inhrnt_arr[0]), +#endif +#if (VCOM_CCINST_SUBTP1_2EP_CNT >0) + .p_vcom_ccinst_subtp1_entry = &(t_vcom_func_custp1_arr[0]), +#endif +#if (VCOM_CCINST_SUBTP2_3EP_CNT >0) + .p_vcom_ccinst_subtp2_entry = &(t_vcom_func_custp2_arr[0]), +#endif +}; +//#define CUST_DEF_TEST_TYPE2//change at/log order--ok +//#define CUST_DEF_TEST_TYPE3//add a vcom---ok +//#define CUST_DEF_TEST_TYPE4//remove a vcom---ok also need to modify dev create/destory +//#define CUST_DEF_TEST_TYPE5//remove rndis--ok also need to modify dev create/destory +//#define CUST_DEF_TEST_TYPE6//change ep--ok + + +/* +org: if0/1/2/3/4 + iep =2/4/6/8/10 + oep=1/2/3/4/5 + intep=1/2/3/4/5-also in-type + +usr cfg: + usb driver still use org epidx, map 2 usr defined ep in below table + should make sure no same ep num in below table + + e.g-1. if0 use iep=2 oep=1,intep=1, but user define iep=10, oep=5,intep still 1 + epin_remap_custom_tbl[2] =10 + epout_remap_custom_tbl[1]=5 + epin_remap_custom_tbl[10]=2 //not used but change to another val + epout_remap_custom_tbl[5]=1//not used but change to another val + + e.g-2. if0 use iep=2 oep=1,intep=1, if2 use iep=6 oep=3,intep=5. usr want switch if0/2 ep + epin_remap_custom_tbl[2] =6 + epout_remap_custom_tbl[1]=3 + epin_remap_custom_tbl[6]=2 + epout_remap_custom_tbl[3]=1 + + + NOTE: + 1 currently, if enbale rndis, rndis should be at the first interface, + if not,rndis enum will have some issue, mostly win host issue, need further debug + + 2 after add or remove some if, e.g. remmove PPP vcom or add a raw VCOM, user should also modify + ccio dev create logic: not create corresponding dev if removed and create new dev if added. + if still not clear ask EC for help +*/ + + + + +#ifdef CUST_DEF_TEST_TYPE1 + +const uint8_t epin_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + + +const uint8_t epout_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + +#if ((defined LOW_SPEED_SERVICE_ONLY) || (defined LITE_FEATURE_MODE)) + + +#if (VCOM_CCINST_CASE_SEL==VCOM_CCINST_ORG_CASE) + +static multidev_custom_info_st t_multidev_custom_info = { +#ifdef __USER_CODE__ + .elem_cnt = 4, + .elem_arr[0] = + { + (const uint8_t*)"vcom3", + multidev_tp_vcom_com, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[1] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[2] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + + .elem_arr[3] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, +#else + .elem_cnt = 2, + .elem_arr[0] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[1] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, +#endif +}; +#else + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 2, + .elem_arr[0] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp2_3ep, + }, + .elem_arr[1] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp1_2ep, + }, + +}; +#endif + +#else +#if (VCOM_CCINST_CASE_SEL==VCOM_CCINST_ORG_CASE) +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 5, + .elem_arr[0] = + { + (const uint8_t*)"rndis", + multidev_tp_rndis, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[1] = + { + (const uint8_t*)"ecm", + multidev_tp_ecm, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + + .elem_arr[2] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[3] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + + .elem_arr[4] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, +}; +#endif + +#if (VCOM_CCINST_CASE_SEL==VCOM_CCINST_CUST_CASE) + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 5, + .elem_arr[0] = + { + (const uint8_t*)"rndis", + multidev_tp_rndis, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[1] = + { + (const uint8_t*)"ecm", + multidev_tp_ecm, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + + .elem_arr[2] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp2_3ep, + }, + .elem_arr[3] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp1_2ep, + }, + + .elem_arr[4] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp2_3ep, + }, +}; + +#endif + +#endif + +#endif + +#ifdef CUST_DEF_TEST_TYPE2 +const uint8_t epin_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + + +const uint8_t epout_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 5, + .elem_arr[0] = + { + (const uint8_t*)"rndis", + multidev_tp_rndis, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[1] = + { + (const uint8_t*)"ecm", + multidev_tp_ecm, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[2] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[3] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[4] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, +}; +#endif + + +#ifdef CUST_DEF_TEST_TYPE3 +const uint8_t epin_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + + +const uint8_t epout_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 6, + .elem_arr[0] = + { + (const uint8_t*)"rndis", + multidev_tp_rndis, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[1] = + { + (const uint8_t*)"ecm", + multidev_tp_ecm, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[2] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[3] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[4] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[5] = + { + (const uint8_t*)"vcom3", + multidev_tp_vcom_com, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, +}; +#endif + + +#ifdef CUST_DEF_TEST_TYPE4 +const uint8_t epin_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + + +const uint8_t epout_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 4, + .elem_arr[0] = + { + (const uint8_t*)"rndis", + multidev_tp_rndis, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[1] = + { + (const uint8_t*)"ecm", + multidev_tp_ecm, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[2] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[3] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + + .elem_arr[4] = + { + NULL, + multidev_tp_none, + }, +}; +#endif + + + + +#ifdef CUST_DEF_TEST_TYPE5 +const uint8_t epin_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + + +const uint8_t epout_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,2,3,4,5,6,7,8,9,10,11,12 +}; + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 3, + .elem_arr[0] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[1] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[2] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[3] = + { + NULL, + multidev_tp_none, + }, +}; +#endif + + + +#ifdef CUST_DEF_TEST_TYPE6 +const uint8_t epin_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 1,6,3,4,5,2,7,8,9,10,11,12 +}; + + +const uint8_t epout_remap_custom_tbl[EP_REMAP_CUSTOM_CNT] = { + 0, 3,2,1,4,5,6,7,8,9,10,11,12 +}; + + +static multidev_custom_info_st t_multidev_custom_info = { + .elem_cnt = 5, + .elem_arr[0] = + { + (const uint8_t*)"rndis", + multidev_tp_rndis, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[1] = + { + (const uint8_t*)"ecm", + multidev_tp_ecm, + ccinst_setting_mainttp_none, + ccinst_setting_subtp_none, + }, + .elem_arr[2] = + { + (const uint8_t*)"vcom0", + multidev_tp_vcom_at, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[3] = + { + (const uint8_t*)"vcom1", + multidev_tp_vcom_log, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[4] = + { + (const uint8_t*)"vcom2", + multidev_tp_vcom_ppp, + ccinst_setting_cdc_vcom_maintp, + ccinst_setting_vcom_subtp0_inhrnt, + }, + .elem_arr[5] = + { + NULL, + multidev_tp_none, + }, +}; +#endif + +extern uint32_t usbc_dev_int_handler (void); +void USB_IRQ_Handler(void) +{ +#if (RTE_USB_EN == 1) +#if MEASURE_USB_INT_TIME + extern void TMU_APTimeReadOpen(UINT32 *sysTime); + uint32_t startTime, endTime; + TMU_APTimeReadOpen(&startTime); +#endif + usbc_dev_int_handler(); +#if MEASURE_USB_INT_TIME + TMU_APTimeReadOpen(&endTime); + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, USB_IRQ_Handler_0, P_VALUE, "USB IRQ Time=%d", (endTime-startTime)&0x1FFFFFFF); +#endif +#endif +} + + +uint8_t usbcustom_epin_id_map(uint8_t ep_idx) +{ + if (ep_idx > EP_REMAP_CUSTOM_CNT) + { + return 0xff; + } + return epin_remap_custom_tbl[ep_idx]; +} + +uint8_t usbcustom_epout_id_map(uint8_t ep_idx) +{ + if (ep_idx > EP_REMAP_CUSTOM_CNT) + { + return 0xff; + } + return epout_remap_custom_tbl[ep_idx]; +} + +uint8_t usbcustom_multidev_ccinfo_maprst(void) +{ + uint8_t idx; + usb_func_ccinst_st * p_ccinst; + ccinst_cdc_setting_st *p_ccinst_cdc_set; + + for(idx = 0; idx < t_usbd_multidev_ccinst_res.vcom_ccinst_subtp0_inhrnt_cnt; idx++) + { + p_ccinst = t_usbd_multidev_ccinst_res.p_vcom_ccinst_subtp0_entry; + if (p_ccinst==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + + p_ccinst = p_ccinst+idx; + p_ccinst_cdc_set = p_ccinst->p_cc_setting; + if (p_ccinst_cdc_set==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + p_ccinst_cdc_set->map_flag = 0; + } + + for(idx = 0; idx < t_usbd_multidev_ccinst_res.vcom_ccinst_subtp1_2ep_cnt;idx++) + { + p_ccinst = t_usbd_multidev_ccinst_res.p_vcom_ccinst_subtp1_entry; + if (p_ccinst==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + + p_ccinst = p_ccinst+idx; + p_ccinst_cdc_set = p_ccinst->p_cc_setting; + if(p_ccinst_cdc_set==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + p_ccinst_cdc_set->map_flag = 0; + } + + for(idx = 0; idx < t_usbd_multidev_ccinst_res.vcom_ccinst_subtp2_3ep_cnt;idx++) + { + p_ccinst = t_usbd_multidev_ccinst_res.p_vcom_ccinst_subtp2_entry; + if (p_ccinst==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + p_ccinst = p_ccinst+idx; + p_ccinst_cdc_set = p_ccinst->p_cc_setting; + if(p_ccinst_cdc_set==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + + p_ccinst_cdc_set->map_flag = 0; + } + + return 0; +} + +uint8_t usbcustom_multidev_ccinfo_map(usbcust_mdcd_ccinfo_st *p_mdcd_ccinfo) +{ + uint8_t idx; + usb_func_ccinst_st * p_ccinst; + ccinst_cdc_setting_st *p_ccinst_cdc_set; + uint8_t map_valid = 0; + if(p_mdcd_ccinfo->setting_maintp == ccinst_setting_cdc_vcom_maintp) + { + if (p_mdcd_ccinfo->setting_subtp== ccinst_setting_vcom_subtp0_inhrnt) + { + for(idx = 0; idx < t_usbd_multidev_ccinst_res.vcom_ccinst_subtp0_inhrnt_cnt;idx++) + { + p_ccinst = t_usbd_multidev_ccinst_res.p_vcom_ccinst_subtp0_entry; + if (p_ccinst==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + p_ccinst = p_ccinst+idx; + p_ccinst_cdc_set = p_ccinst->p_cc_setting; + if (p_ccinst_cdc_set==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + if (p_ccinst_cdc_set->map_flag ==1) + { + continue; + } + p_ccinst_cdc_set->map_flag = 1; + map_valid = 1; + p_mdcd_ccinfo->p_func_ccinst = p_ccinst; + break; + + } + } + + else if (p_mdcd_ccinfo->setting_subtp== ccinst_setting_vcom_subtp1_2ep) + { + for(idx = 0; idx < t_usbd_multidev_ccinst_res.vcom_ccinst_subtp1_2ep_cnt;idx++) + { + p_ccinst = t_usbd_multidev_ccinst_res.p_vcom_ccinst_subtp1_entry; + if (p_ccinst==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + + p_ccinst = p_ccinst+idx; + p_ccinst_cdc_set = p_ccinst->p_cc_setting; + if (p_ccinst_cdc_set==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + if (p_ccinst_cdc_set->map_flag ==1) + { + continue; + } + p_ccinst_cdc_set->map_flag = 1; + map_valid = 1; + p_mdcd_ccinfo->p_func_ccinst = p_ccinst; + break; + } + } + else if (p_mdcd_ccinfo->setting_subtp== ccinst_setting_vcom_subtp2_3ep) + { + for(idx = 0; idx < t_usbd_multidev_ccinst_res.vcom_ccinst_subtp2_3ep_cnt;idx++) + { + p_ccinst = t_usbd_multidev_ccinst_res.p_vcom_ccinst_subtp2_entry; + if (p_ccinst==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + p_ccinst = p_ccinst+idx; + p_ccinst_cdc_set = p_ccinst->p_cc_setting; + if (p_ccinst_cdc_set==NULL) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + if (p_ccinst_cdc_set->map_flag ==1) + { + continue; + } + p_ccinst_cdc_set->map_flag = 1; + map_valid = 1; + p_mdcd_ccinfo->p_func_ccinst = p_ccinst; + break; + } + } + + } + else + { + //other dev not support ccinst + p_mdcd_ccinfo->p_func_ccinst = NULL; + map_valid = 1; + } + + //load cnt is limited to MULTI_LOAD_CNT_MAX +#ifndef USB_DRV_SMALL_IMAGE + ECOMM_TRACE(UNILOG_PLA_DRIVER, usbcustom_multidev_ccinfo_map_1, P_ERROR, 4, \ + "clstype %d, inst_id %d, maintp %d, subtp %d", \ + p_mdcd_ccinfo->cls_type, \ + p_mdcd_ccinfo->inst_id, \ + p_mdcd_ccinfo->setting_maintp, \ + p_mdcd_ccinfo->setting_subtp); +#endif + + if (map_valid==0) + { +#ifndef USB_DRV_SMALL_IMAGE + ECOMM_TRACE(UNILOG_PLA_DRIVER, usbcustom_multidev_ccinfo_map_2, P_ERROR, 4, \ + "clstype %d, inst_id %d, maintp %d, subtp %d", \ + p_mdcd_ccinfo->cls_type, \ + p_mdcd_ccinfo->inst_id, \ + p_mdcd_ccinfo->setting_maintp, \ + p_mdcd_ccinfo->setting_subtp); + EC_ASSERT(0, p_mdcd_ccinfo->cls_type, p_mdcd_ccinfo->inst_id, \ + (p_mdcd_ccinfo->setting_maintp<<8) |p_mdcd_ccinfo->setting_subtp); +#else + return USBD_MULTIDEV_LOAD_FAIL; + +#endif + } + return 0; +} + + + + +uint8_t usbcustom_multidev_cfg_reset(void) +{ + uint8_t loop_idx; + uint32_t map_flag = 0; + uint32_t cur_flag = 0; + uint8_t ret; + if (epout_remap_custom_tbl[0]!=0) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + for (loop_idx = 1; loop_idx < EP_REMAP_CUSTOM_CNT; loop_idx++) + { + if (epout_remap_custom_tbl[loop_idx] >= EP_REMAP_CUSTOM_CNT) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + cur_flag = (1UL<load_cnt+ p_multidev_load->filter_cnt ) != t_multidev_custom_info.elem_cnt) + { + return USBD_MULTIDEV_LOAD_FAIL; + } + + if (p_multidev_load->load_cnt > MULTI_DEV_LOADCNT_MAX) + { + //load cnt is limited to MULTI_LOAD_CNT_MAX +#ifndef USB_DRV_SMALL_IMAGE + ECOMM_TRACE(UNILOG_PLA_DRIVER, usbcustom_multidev_cfg_end_1, P_ERROR, 1,"p_multidev_load->load_cnt %x", p_multidev_load->load_cnt); +#endif + return USBD_MULTIDEV_LOAD_FAIL; + } + return 0; +} + +uint8_t *usbcustom_multidev_strdesc(usbcust_mdcd_strdesc_st *p_mdcd_strdesc) +{ + uint8_t* p_intf_str_desc = (uint8_t*)"default"; + switch(p_mdcd_strdesc->cls_type) + { + case multidev_tp_rndis: + p_intf_str_desc = (uint8_t*)"rndis"; + break; + case multidev_tp_ecm: + p_intf_str_desc = (uint8_t*)"ecm"; + break; + case multidev_tp_vcom_at: + p_intf_str_desc = (uint8_t*)"at"; + break; + case multidev_tp_vcom_log: + p_intf_str_desc = (uint8_t*)"log"; + break; + case multidev_tp_vcom_ppp: + p_intf_str_desc = (uint8_t*)"ppp"; + break; + case multidev_tp_vcom_com: + p_intf_str_desc = (uint8_t*)"com"; + break; + default: + break; + } + +#ifndef USB_DRV_SMALL_IMAGE + + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usbcustom_multidevstr_desc_1, P_DEBUG, \ + "cls_type %d, inst_id 0x%x, name %s, intf string %s", \ + p_mdcd_strdesc->cls_type, \ + p_mdcd_strdesc->inst_id, \ + p_mdcd_strdesc->p_func_name, \ + p_intf_str_desc); + +#endif + return p_intf_str_desc; +} + +uint8_t usbcustom_multidev_cmndesc(usbcust_mdcd_cmndesc_st *p_mdcd_cmndesc) +{ + + usbcust_cmndesc_data_st *p_cmndesc_data= &(p_mdcd_cmndesc->t_cmndesc_data); + + switch(p_mdcd_cmndesc->cls_type) + { + case multidev_tp_rndis: + p_cmndesc_data->intf_ctrl_desc.bInterfaceClass = 0xE0; + p_cmndesc_data->intf_ctrl_desc.bInterfaceSubClass = 0x01; + p_cmndesc_data->intf_ctrl_desc.bInterfaceProtocol = 0x03; + p_cmndesc_data->b_intf_ctrl_desc_upd = 1; + +#ifndef USB_DRV_SMALL_IMAGE + + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usbcustom_multidev_cmndesc_1, P_DEBUG, \ + "name %s, cls = 0x%x, subcls 0x%x, protocol 0x%x", \ + p_mdcd_cmndesc->p_func_name, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceClass, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceSubClass, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceProtocol); +#endif + break; + case multidev_tp_ecm: + p_cmndesc_data->intf_ctrl_desc.bInterfaceClass = 0x02; + p_cmndesc_data->intf_ctrl_desc.bInterfaceSubClass = 0x06; + p_cmndesc_data->intf_ctrl_desc.bInterfaceProtocol = 0x00; + p_cmndesc_data->b_intf_ctrl_desc_upd = 1; + +#ifndef USB_DRV_SMALL_IMAGE + + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usbcustom_multidev_cmndesc_1, P_DEBUG, \ + "name %s, cls = 0x%x, subcls 0x%x, protocol 0x%x", \ + p_mdcd_cmndesc->p_func_name, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceClass, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceSubClass, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceProtocol); +#endif + break; + case multidev_tp_vcom_at: + case multidev_tp_vcom_log: + case multidev_tp_vcom_ppp: + case multidev_tp_vcom_com: + p_cmndesc_data->intf_ctrl_desc.bInterfaceClass = 0x02; + p_cmndesc_data->intf_ctrl_desc.bInterfaceSubClass = 0x02; + p_cmndesc_data->intf_ctrl_desc.bInterfaceProtocol = 0x01; + p_cmndesc_data->b_intf_ctrl_desc_upd = 1; + +#ifndef USB_DRV_SMALL_IMAGE + + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usbcustom_multidev_cmndesc_1, P_DEBUG, \ + "name %s, cls = 0x%x, subcls 0x%x, protocol 0x%x", \ + p_mdcd_cmndesc->p_func_name, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceClass, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceSubClass, \ + p_cmndesc_data->intf_ctrl_desc.bInterfaceProtocol); +#endif + + break; + default: + break; + } + + return 0; +} + +uint8_t usbcustom_multidev_ctrl_proc(usbcust_md_ctrl_st* p_usbcust_md_ctrl) +{ + // t_ctl_req.cmd Bit 31 : 0 host to dev, 1 dev to host + + #ifndef USB_DRV_SMALL_IMAGE + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, usbcustom_multidev_ctrl_proc_1, P_DEBUG, \ + "cls_type = %d, inst_id %d, name %s, req 0x%x", \ + p_usbcust_md_ctrl->cls_type, \ + p_usbcust_md_ctrl->inst_id, \ + p_usbcust_md_ctrl->p_func_name, \ + p_usbcust_md_ctrl->t_ctl_req.cmd); + #if 0 + ECPLAT_DUMP(UNILOG_PLA_DRIVER, usbcustom_multidev_ctrl_proc_2, P_DEBUG, \ + "clsdev req data:", \ + p_usbcust_md_ctrl->t_ctl_req.len, \ + p_usbcust_md_ctrl->t_ctl_req.buf); + #endif + #endif +#ifdef __USER_CODE__ + extern void usb_ctrl_pre_proc(usbcust_md_ctrl_st *); + usb_ctrl_pre_proc(p_usbcust_md_ctrl); +#endif + p_usbcust_md_ctrl->t_ctl_req.cmd &= (~(0x1UL<<31)); + return 0; +} + + +void usblpw_innophy_enh_drv_strenth(void) +{ + volatile uint32_t* addr = (volatile uint32_t*)0x4d0b0030; + * addr = (* addr &~ (0x7<<0)) | (0x5<<0); + + addr = (volatile uint32_t*)0x4d0b0040; + * addr = (* addr &~ (0x7<<3)) | (0x5<<3); + + addr = (volatile uint32_t*)0x4d0b0064; + * addr = (* addr &~ (0xf<<3)) | (0x0<<3); + + addr = (volatile uint32_t*)0x4d0b0124; + * addr = (* addr &~ (0x7<<2)) | (0x7<<2); +} + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/open/usbd_proc_cb_custom.c b/PLAT/driver/chip/ec618/ap/src/usb/open/usbd_proc_cb_custom.c new file mode 100644 index 0000000..45ec1dd --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/open/usbd_proc_cb_custom.c @@ -0,0 +1,174 @@ +#include +#include "usbd_multi_clstype.h" + + +#define USB_DEV_QUALIFIER_DESC_ARR_SIZE 0x0A + + +#define DEF_LANGID_STR 0x409 +#define DEF_MANUFACT_STR "AirM2M"; +#define DEF_PRODUCT_HS_STR "AirM2M Compo"; +#define DEF_SER_NUM_HS_STR "000000000001" + +#define DEF_CFG_HS_STR "Compo Config" +#define DEF_INTF_HS_STR "Compo Interface" + + +#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 +#define USB_STRING_DESCRIPTOR_TYPE 0x03 +#define USB_SIZ_STRING_LANGID 4 +#define USB_SIZ_DEVICE_DESC 0x12 + +#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) +#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) + + +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIGURATION 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 +#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 +#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 + + +uint32_t udev_last_err = 0; + + + +uint8_t usbd_dev_desc_arr[USB_SIZ_DEVICE_DESC] = +{ + 0x12, /* bLength */ + USB_DEVICE_DESCRIPTOR_TYPE, /* bDescriptorType */ + 0x00, + 0x02, /* bcdUSB = 2.00 */ + 0xEF, /* bDeviceClass: IAD */ + 0x02, /* bDeviceSubClass */ + 0x01, /* bDeviceProtocol */ + + 0x40, /* bMaxPacketSize0 */ + + 0xd1, + 0x19, /* idVendor = 0x19d1 */ + 0x01, + 0x00, /* idProduct = 0x0001 */ + + 0x00, + 0x02, /* bcdDevice = 2.00 */ + 1, /* Index of string descriptor describing manufacturer */ + 2, /* Index of string descriptor describing product */ + 3, /* Index of string descriptor describing the device's serial number */ + 0x01 /* bNumConfigurations */ +}; + + +/* USB Standard Device Descriptor */ +uint8_t usbd_dev_qualifier_desc_arr[USB_DEV_QUALIFIER_DESC_ARR_SIZE] = +{ + USB_DEV_QUALIFIER_DESC_ARR_SIZE, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0xEF, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +}; + +/* USB Standard Device Descriptor */ +uint8_t usbd_dev_langid_desc[USB_SIZ_STRING_LANGID] = +{ + USB_SIZ_STRING_LANGID, + USB_DESC_TYPE_STRING, + LOBYTE(DEF_LANGID_STR), + HIBYTE(DEF_LANGID_STR), +}; + +uint8_t *usbcustom_product_str_desc(void) +{ + return (uint8_t *)DEF_PRODUCT_HS_STR; +} + +uint8_t *usbcustom_manufacture_str_desc(void) +{ + return (uint8_t *)DEF_MANUFACT_STR; +} + +uint8_t *usbcustom_ser_str_desc(void) +{ + return (uint8_t *)DEF_SER_NUM_HS_STR; +} + +uint8_t *usbcustom_cfg_str_desc(void) +{ + return (uint8_t *)DEF_CFG_HS_STR; +} + +uint8_t *usbcustom_intf_str_desc(void) +{ + return (uint8_t *)DEF_INTF_HS_STR; +} + +uint8_t *usbcustom_qulifier_desc(void) +{ + return usbd_dev_qualifier_desc_arr; +} + +uint8_t usbcustom_cfg_remote_wkup_bit(void) +{ + return 1; +} + +uint8_t usbcustom_cfg_self_powered_bit(void) +{ + return 0; +} + +uint8_t usbcustom_cfg_max_power(void) +{ + return 100; +} + +void udev_notify_init(void) +{ +} + +void udev_notify_device_reset (uint8_t speed) +{ +} + +void udev_notify_device_config (void) +{ +} + +void udev_notify_device_suspend(void) +{ +} + +void udev_notify_device_resume(void) +{ +} + +void udev_notify_device_connect (void) +{ +} + +void udev_notify_device_disconnect (void) +{ +} + +void udev_set_last_err(uint32_t err_no) +{ + udev_last_err = err_no; +} + + +uint32_t udev_get_last_err(void) +{ + return udev_last_err; +} + + + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/usb_device/usb_bl_api.c b/PLAT/driver/chip/ec618/ap/src/usb/usb_device/usb_bl_api.c new file mode 100644 index 0000000..a5bb5a3 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/usb_device/usb_bl_api.c @@ -0,0 +1,196 @@ +#include "string.h" +#include "cmsis_os2.h" +#include "hal_misc.h" +#include +#include +#include "usb_bl_api.h" + +int vcomx_isconnect(uint8_t vcom_num); +int vcomx_get_in_waiting(uint8_t vcom_num); +int vcomx_poll_rx(uint8_t vcom_num, uint32_t timeout); + int vcomx_recv(uint8_t vcom_num, uint8_t* buf, uint16_t len); + int vcomx_get_out_avail(uint8_t vcom_num); +int vcomx_poll_tx(uint8_t vcom_num, uint32_t timeout); +int vcomx_send(uint8_t vcom_num, uint8_t* buf, uint16_t len); + + +#ifdef VCOM_DBGEN +void vcom_dbg_putchar(uint8_t ch); + +void vcomdbg_hex(uint32_t hex) +{ + uint16_t val; + for (int32_t idx = 28; idx >=0; idx-=4) + { + val = ((hex>>idx)&0xf) + 0x30; + if(val>=0x3a) + { + val = val + 0x27; + } + vcom_dbg_putchar(val); + } +} + +void vcomdbg_str(uint8_t* str) +{ + while(*str) + { + vcom_dbg_putchar(*str); + str++; + } +} + +void vcomdbg_str_and_hex(uint8_t* str, uint32_t hex) +{ + vcomdbg_str(str); + //vcomdbg_str((uint8_t*)"\r\n"); + vcomdbg_hex(hex); + vcomdbg_str((uint8_t*)"\r\n"); +} +#endif + +void vcom_app_delay(uint32_t ticks) +{ + volatile int us_cnt = 0; + volatile int loop_in_us; + //depend on code speed, add 6 for flash code at 50M, cpu 204m + for (us_cnt = 0; us_cnt < ticks*1000; us_cnt+=6){ + loop_in_us = 0; + while(loop_in_us++< 70); + } +} + +int vcom_app_recv_proc(uint8_t vcom_num, uint8_t* rcvbuf_ptr, uint32_t size, uint8_t timeout) +{ + int rxwait_cnt; + int poll_stat; + uint8_t recvd_size = 0; + int byte_cnt = 0; + uint32_t ticks_tmout = timeout; // 1tick for 1ms + uint32_t ticks_elapsed = 0; + uint32_t ticks_step = 1; + + if (size ==0) + { + return 0; + } + + while(1) + { + if (vcomx_isconnect(vcom_num) <=0) + { + VCDBG_STR_AND_HEX("vcom[%d] not connected%x \r\n", vcom_num); + return ERR_DEV_NO_CONNECT; + } + + //rxwait_cnt = p_serial_vcom->p_ops->get_in_waiting(p_serial_vcom); + rxwait_cnt = vcomx_get_in_waiting(vcom_num); + if (rxwait_cnt <0) + { + VCDBG_STR_AND_HEX("get_in_waiting err %d \r\n", rxwait_cnt); + return rxwait_cnt; + } + if (rxwait_cnt ==0) + { + if (ticks_elapsed >=ticks_tmout) + { + VCDBG_STR_AND_HEX("recv timeout, recved bytes %d \r\n", recvd_size); + return recvd_size; + } + + //poll_stat = p_serial_vcom->p_ops->poll_rx(p_serial_vcom, 0); + poll_stat =vcomx_poll_rx(vcom_num, 0); + if ((poll_stat <0) && (poll_stat!=ERR_DEV_RX_TIMOUT)) + { + VCDBG_STR_AND_HEX("recv poll state break %d \r\n", poll_stat); + return poll_stat; + } + vcom_app_delay(ticks_step); + ticks_elapsed += ticks_step; + continue; + } + + if (rxwait_cnt> size) + { + rxwait_cnt = size; + } + + //byte_cnt = p_serial_vcom->p_ops->recv(p_serial_vcom, rcvbuf_ptr, rxwait_cnt); + byte_cnt = vcomx_recv(vcom_num, rcvbuf_ptr, rxwait_cnt); + if (byte_cnt < 0) + { + VCDBG_STR_AND_HEX("recv state break %d \r\n", byte_cnt); + return byte_cnt; + } + + recvd_size += byte_cnt; + if (recvd_size>=size) + { + return recvd_size; + } + } + return 0; +} + +int vcom_app_send_proc(uint8_t vcom_num, uint8_t* sndbuf_ptr, uint32_t size, uint8_t timeout) +{ + int txavail_cnt; + int poll_stat; + int byte_cnt; + uint8_t sended_size = 0; + uint32_t ticks_tmout = timeout; // 1tick for 1ms + uint32_t ticks_elapsed = 0; + uint32_t ticks_step = 1; + + while(1) + { + if (vcomx_isconnect(vcom_num) <= 0) + { + VCDBG_STR_AND_HEX("vcom[%d] not connected \r\n", vcom_num); + return ERR_DEV_NO_CONNECT; + } + + //txavail_cnt = p_serial_vcom->p_ops->get_out_avail(p_serial_vcom); + txavail_cnt = vcomx_get_out_avail(vcom_num); + if (txavail_cnt == 0) + { + if (ticks_elapsed >=ticks_tmout) + { + VCDBG_STR_AND_HEX("vcom[%d] \r\n", vcom_num); + VCDBG_STR_AND_HEX("send timeout, sended bytes %x \r\n", sended_size); + return sended_size; + } + //poll_stat = p_serial_vcom->p_ops->poll_tx(p_serial_vcom, 0); + poll_stat = vcomx_poll_tx(vcom_num, 0); + if ((poll_stat <0) && (poll_stat!=ERR_DEV_RX_TIMOUT)) + { + VCDBG_STR_AND_HEX("send poll state break %d \r\n", poll_stat); + return poll_stat; + } + + vcom_app_delay(ticks_step); + ticks_elapsed += ticks_step; + continue; + } + + if (size < txavail_cnt) + { + txavail_cnt = size; + } + + //byte_cnt = p_serial_vcom->p_ops->send(p_serial_vcom, sndbuf_ptr, txavail_cnt); + byte_cnt = vcomx_send(vcom_num, sndbuf_ptr, txavail_cnt); + if (byte_cnt <0) + { + VCDBG_STR_AND_HEX("send state break %d \r\n", byte_cnt); + return byte_cnt; + } + + sended_size +=byte_cnt; + if (sended_size>=size) + { + return sended_size; + } + } +} + diff --git a/PLAT/driver/chip/ec618/ap/src/usb/usb_device/usb_bl_test.c b/PLAT/driver/chip/ec618/ap/src/usb/usb_device/usb_bl_test.c new file mode 100644 index 0000000..f828151 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/usb/usb_device/usb_bl_test.c @@ -0,0 +1,378 @@ +#include "ec618.h" +#include "string.h" +#include "cmsis_os2.h" +#include "hal_misc.h" +#include +#include +#include "bl_bsp.h" +#include "usb_bl_api.h" + +int vcomx_isconnect(uint8_t vcom_num); +int vcomx_get_in_waiting(uint8_t vcom_num); +int vcomx_poll_rx(uint8_t vcom_num, uint32_t timeout); + int vcomx_recv(uint8_t vcom_num, uint8_t* buf, uint16_t len); + int vcomx_get_out_avail(uint8_t vcom_num); +int vcomx_poll_tx(uint8_t vcom_num, uint32_t timeout); +int vcomx_send(uint8_t vcom_num, uint8_t* buf, uint16_t len); + +typedef enum +{ + vcom_step_idle = 0, + vcom_step_recv , + vcom_step_send , + vcom_step_busy_sending , + +}vcom_app_step_type; + +#define VCOM_STATE_IDLE 0 +#define VCOM_TEST_BUF_SIZE 0x400 +typedef struct +{ + //uint8_t recv_en; + //uint8_t send_en; + vcom_app_step_type step; + uint32_t received_len; + uint32_t sended_len; + uint8_t vcom_rcvbuff[VCOM_TEST_BUF_SIZE]; + uint8_t vcom_sndbuff[VCOM_TEST_BUF_SIZE]; +}vcom_app_ctx_st; + +#define VCOM_NUM_MAX 3 +vcom_app_ctx_st vcom_app_ctx[VCOM_NUM_MAX]; + +void vcom_app_ctx_init(void) +{ + memset(&vcom_app_ctx, 0, sizeof(vcom_app_ctx)); +} + +int vcom_app_ctx_is_idlestep(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + if(vcom_app_ctx[vcom_num].step == vcom_step_idle) + { + return 1; + } + return 0; +} + +uint8_t vcom_app_ctx_is_recvstep(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return 0; + } + if(vcom_app_ctx[vcom_num].step == vcom_step_recv) + { + return 1; + } + return 0; +} + +uint8_t vcom_app_ctx_is_sendstep(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return 0; + } + if(vcom_app_ctx[vcom_num].step == vcom_step_send) + { + return 1; + } + return 0; +} + +uint8_t vcom_app_ctx_is_busysending(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return 0; + } + if(vcom_app_ctx[vcom_num].step == vcom_step_busy_sending) + { + return 1; + } + return 0; +} + +void vcom_app_ctx_set_step(uint8_t vcom_num, vcom_app_step_type step) +{ + + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return; + } + vcom_app_ctx[vcom_num].step = step; + + return ; +} + +int vcom_app_get_rcvbuff_size(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + return sizeof(vcom_app_ctx[vcom_num].vcom_rcvbuff); +} + +uint8_t* vcom_app_get_rcvbuff_ptr(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return NULL; + } + return &(vcom_app_ctx[vcom_num].vcom_rcvbuff[0]); +} + +int vcom_app_get_sndbuff_size(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + return sizeof(vcom_app_ctx[vcom_num].vcom_sndbuff); +} + +uint8_t* vcom_app_get_sndbuff_ptr(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return NULL; + } + return &(vcom_app_ctx[vcom_num].vcom_sndbuff[0]); +} + +int vcom_app_update_recved_size(uint8_t vcom_num, uint32_t size) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + vcom_app_ctx[vcom_num].received_len = size; + return 0; +} + +int vcom_app_update_sended_size(uint8_t vcom_num, uint32_t size) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + vcom_app_ctx[vcom_num].sended_len = size; + return 0; +} + +int vcom_app_get_recved_size(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + return vcom_app_ctx[vcom_num].received_len; +} + +int vcom_app_get_sended_size(uint8_t vcom_num) +{ + if (vcom_num>=VCOM_NUM_MAX) + { + VCDBG_STR_AND_HEX("vcom_num(%d) error \r\n", vcom_num); + return -1; + } + return vcom_app_ctx[vcom_num].sended_len; +} + +int vcom_app_send_proc(uint8_t vcom_num, uint8_t* sndbuf_ptr, uint32_t size, uint8_t timeout); +int vcom_app_recv_proc(uint8_t vcom_num, uint8_t* rcvbuf_ptr, uint32_t size, uint8_t timeout); +void vcom_app_delay(uint32_t ticks); + +void vcom_loopback_test(void *p) +{ + int ret; + int txavail_cnt; +//#if DEVICE_VCOM_INSTANCE + uint32_t sended_size; + uint8_t * send_buf_ptr; + uint8_t * recv_buf_ptr; + + vcom_app_ctx_init(); + int vcom_num = 0; + VCDBG_STR("uart_loopback_test start \r\n"); + + while(1) + { + vcom_app_delay(10); + vcom_num = vcom_num+1; + vcom_num = vcom_num%VCOM_NUM_MAX; + + while(1) + { + if (vcomx_isconnect(vcom_num) ==0) + { + vcom_app_delay(1000); + break; + } + + if (vcom_app_ctx_is_idlestep(vcom_num)==1) + { + + if (vcomx_isconnect(vcom_num) ==0) + { + vcom_app_delay(20); + break; + } + + vcom_app_ctx_set_step(vcom_num, vcom_step_recv); + VCDBG_STR_AND_HEX("vcom(%d) [recv] \r\n", vcom_num); + } + + if (vcom_app_ctx_is_recvstep(vcom_num)==1) + { + ret= vcom_app_recv_proc(vcom_num, + vcom_app_get_rcvbuff_ptr(vcom_num), + vcom_app_get_rcvbuff_size(vcom_num), 1); + if (ret <=0) + { + vcom_app_delay(1); + break; + } + vcom_app_update_recved_size(vcom_num, ret); + vcom_app_update_sended_size(vcom_num, 0); + vcom_app_ctx_set_step(vcom_num, vcom_step_send); + + VCDBG_STR_AND_HEX("vcom(%d) [recv] ->[send] \r\n", vcom_num); + VCDBG_STR_AND_HEX("ret %d \r\n",ret); + + break; + } + + if (vcom_app_ctx_is_sendstep(vcom_num)==1) + { + if (vcom_app_get_recved_size(vcom_num) <0) + { + VCDBG_STR_AND_HEX("vcom(%d) [send] recved_size <0, ->[idle] \r\n", vcom_num); + vcom_app_ctx_set_step(vcom_num, vcom_step_idle); + vcom_app_update_recved_size(vcom_num, 0); + break; + } + + sended_size = vcom_app_get_sended_size(vcom_num); + recv_buf_ptr= vcom_app_get_rcvbuff_ptr(vcom_num); + send_buf_ptr = vcom_app_get_rcvbuff_ptr(vcom_num); + if (sended_size >=vcom_app_get_recved_size(vcom_num)) + { + VCDBG_STR_AND_HEX("vcom(%d) [send] unneeded->[idle]", vcom_num); + VCDBG_STR_AND_HEX("recved %d\r\n", + vcom_app_get_recved_size(vcom_num)); + VCDBG_STR_AND_HEX("sended %d\r\n", + vcom_app_get_sended_size(vcom_num)); + break; + } + + txavail_cnt = vcom_app_get_sndbuff_size(vcom_num); + if ((txavail_cnt+sended_size) > vcom_app_get_recved_size(vcom_num)) + { + txavail_cnt = vcom_app_get_recved_size(vcom_num) - sended_size; + } + memcpy(send_buf_ptr+sended_size, recv_buf_ptr+sended_size, txavail_cnt); + + ret = vcom_app_send_proc(vcom_num, send_buf_ptr+sended_size, txavail_cnt, 1); + if (ret <0) + { + VCDBG_STR_AND_HEX("vcom(%d) [send] , ->[idle] \r\n", vcom_num); + VCDBG_STR_AND_HEX("fail %08x %d\r\n",ret); + vcom_app_ctx_set_step(vcom_num, vcom_step_idle); + vcom_app_update_recved_size(vcom_num, 0); + break; + } + + sended_size+=ret; + + + vcom_app_update_sended_size(vcom_num, ret); + + if (sended_size >=vcom_app_get_recved_size(vcom_num)) + { + VCDBG_STR_AND_HEX("vcom(%d) [send] ->[idle] finish \r\n", vcom_num); + VCDBG_STR_AND_HEX("recved %d \r\n", vcom_app_get_recved_size(vcom_num)); + VCDBG_STR_AND_HEX("sended %d \r\n", vcom_app_get_sended_size(vcom_num)); + + vcom_app_ctx_set_step(vcom_num, vcom_step_idle); + vcom_app_update_recved_size(vcom_num, 0); + break; + } + + vcom_app_ctx_set_step(vcom_num, vcom_step_busy_sending); + break; + + + } + + if (vcom_app_ctx_is_busysending(vcom_num)==1) + { + vcom_app_delay(1); + vcom_app_ctx_set_step(vcom_num, vcom_step_send); + break; + + } + } + } + + VCDBG_STR("uart_loopback_test end \r\n"); +} + +void vcom_urcprint_test(void) +{ + uint8_t vcom_num = 0; + int cnt = 0; + while(cnt++<2000) + { + vcom_app_delay(10); + vcom_num = vcom_num+1; + vcom_num = vcom_num%VCOM_NUM_MAX; + + SelNormalOrURCPrint(1); + BSP_URCSetCfg(1, 115200, URCVCom0PrintType+vcom_num, vcom_num); + printf("URC PRINT %d\r\n", vcom_num); + + SelNormalOrURCPrint(0); + printf("NO URC PRINT\r\n"); + + } +} +uint32_t BSP_UsbInit(void); +void WDT_stop(void); +void vcom_app_delay(uint32_t ticks); + +void vcom_urc_test_entry(void) +{ + WDT_stop();// stop watchdog for test + extern uint8_t usbstack_clear_ctx_stat(void); + extern void usbstack_set_ctx_vbus_mode(uint8_t vbus_mode_en, uint8_t vbus_pad_idx); + + usbstack_clear_ctx_stat(); + usbstack_set_ctx_vbus_mode(0,0xf); + BSP_UsbInit(); + + extern void vcom_urcprint_test(void); + vcom_urcprint_test(); + + void vcom_loopback_test(void *p); + vcom_loopback_test(NULL); + while(1); +} + diff --git a/PLAT/driver/chip/ec618/ap/src/wdt.c b/PLAT/driver/chip/ec618/ap/src/wdt.c new file mode 100644 index 0000000..d58ed05 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src/wdt.c @@ -0,0 +1,209 @@ +/**************************************************************************** + * + * Copy right: 2017-, Copyrigths of AirM2M Ltd. + * File name: wdt.c + * Description: EC618 wdt driver source file + * History: Rev1.0 2018-07-18 + * + ****************************************************************************/ + +#include "wdt.h" +#include "clock.h" +#include "slpman.h" + +#ifdef PM_FEATURE_ENABLE + +/** \brief Internal used data structure */ +typedef struct _wdt_database +{ + bool isInited; /**< whether wdt has been initialized */ + bool wdtStartStatus; /**< wdt enable status, used for low power restore */ + WdtConfig_t wdtConfig; /**< wdt configuration, used for low power restore */ +} WdtDatabase_t; + +static WdtDatabase_t gWdtDataBase = {0}; + +/** + \fn static void WDT_enterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void WDT_enterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + if(gWdtDataBase.isInited == true) + { + gWdtDataBase.wdtStartStatus = WDT_getStartStatus(); + //disable clock + CLOCK_clockDisable(PCLK_WDG); + CLOCK_clockDisable(FCLK_WDG); + } + + break; + default: + break; + } + +} + +/** + \fn static void WDT_exitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + + */ +static void WDT_exitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + if(gWdtDataBase.isInited == true) + { + //enable clock + CLOCK_clockEnable(PCLK_WDG); + CLOCK_clockEnable(FCLK_WDG); + + WDT_unlock(); + WDT->CTRL = (WDT->CTRL &~ WDT_CTRL_MODE_Msk) | EIGEN_VAL2FLD(WDT_CTRL_MODE, gWdtDataBase.wdtConfig.mode); + WDT_unlock(); + WDT->TOVR = gWdtDataBase.wdtConfig.timeoutValue; + + if(gWdtDataBase.wdtStartStatus) + WDT_start(); + } + + break; + + default: + break; + } +} +#endif + + +void WDT_unlock(void) +{ + WDT->LOCK = 0xABABU; +} + +void WDT_kick(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + WDT_unlock(); + WDT->CCR = WDT_CCR_CNT_CLR_Msk; + + RestoreIRQMask(mask); +} + +void WDT_getDefaultConfig(WdtConfig_t *config) +{ + ASSERT(config); + + config->mode = WDT_INTERRUPT_ONLY_MODE; + config->timeoutValue = 0xFFFFU; +} + +void WDT_init(const WdtConfig_t *config) +{ + ASSERT(config); + +#ifdef PM_FEATURE_ENABLE + + if(gWdtDataBase.isInited == true) + { + return; + } + + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_WDT_MODULE, WDT_enterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_WDT_MODULE, WDT_exitLowPowerStateRestore, NULL); + + gWdtDataBase.isInited = true; + gWdtDataBase.wdtConfig = *config; + +#endif + + //enable clock + CLOCK_clockEnable(PCLK_WDG); + CLOCK_clockEnable(FCLK_WDG); + + + WDT_unlock(); + WDT->CTRL = (WDT->CTRL &~ WDT_CTRL_MODE_Msk) | EIGEN_VAL2FLD(WDT_CTRL_MODE, config->mode); + WDT_unlock(); + WDT->TOVR = config->timeoutValue; +} + +void WDT_deInit(void) +{ +#ifdef PM_FEATURE_ENABLE + + if(gWdtDataBase.isInited == false) + { + return; + } + + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_WDT_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_WDT_MODULE); + + gWdtDataBase.isInited = false; +#endif + + //disable clock + CLOCK_clockDisable(PCLK_WDG); + CLOCK_clockDisable(FCLK_WDG); + +} + +void WDT_start(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + WDT_unlock(); + WDT->CTRL |= WDT_CTRL_ENABLE_Msk; + + RestoreIRQMask(mask); +} + +void WDT_stop(void) +{ + uint32_t mask = SaveAndSetIRQMask(); + + WDT_unlock(); + WDT->CTRL &= ~WDT_CTRL_ENABLE_Msk; + + RestoreIRQMask(mask); + +} + +uint32_t WDT_getInterruptFlags(void) +{ + return WDT->STAT & WDT_STAT_ISTAT_Msk; +} + +void WDTclearInterruptFlags(uint32_t mask) +{ + uint32_t msk = SaveAndSetIRQMask(); + + WDT_unlock(); + WDT->ICR = WDT_ICR_ICLR_Msk; + + RestoreIRQMask(msk); +} + +WdtMode_e WDT_getMode(void) +{ + return (WdtMode_e)EIGEN_FLD2VAL(WDT_CTRL_MODE, WDT->CTRL); +} + +bool WDT_getStartStatus(void) +{ + return (bool)EIGEN_FLD2VAL(WDT_CTRL_ENABLE, WDT->CTRL); +} + diff --git a/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_i2c.c b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_i2c.c new file mode 100644 index 0000000..6691598 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_i2c.c @@ -0,0 +1,1494 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * $Date: 13. July 2018 + * $Revision: V2.0 + * + * Driver: Driver_I2C0, Driver_I2C1 + * Configured: via RTE_Device.h configuration file + * Project: I2C Driver for AirM2M EC618 + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value I2C Interface + * --------------------- ----- ------------- + * Connect to hardware via Driver_I2C# = 0 use I2C0 + * Connect to hardware via Driver_I2C# = 1 use I2C1 + * -------------------------------------------------------------------------- */ +/* History: + * Version 2.0 + * - Initial CMSIS Driver API V2.0 release + */ + +#include "bsp_i2c.h" +#include "slpman.h" + +#define I2C_DEBUG 0 +#if I2C_DEBUG +#define I2CDEBUG(...) printf(__VA_ARGS__) +#else +#define I2CDEBUG(...) +#endif + +#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ + +#if ((!RTE_I2C0) && (!RTE_I2C1)) +#error "I2C not enabled in RTE_Device.h!" +#endif + +#ifdef PM_FEATURE_ENABLE + +/** \brief Internal used data structure */ +typedef struct _i2c_database +{ + bool isInited; /**< Whether i2c has been initialized */ + struct + { + uint32_t MCR; /**< Main Control Register */ + uint32_t SAR; /**< Slave Address Register */ + uint32_t TPR; /**< Timing Parameter Register */ + uint32_t TOR; /**< Timeout Register */ + uint32_t IER; /**< Interrupt Enable Register */ + uint32_t IMR; /**< Interrupt Mask Register */ + } backup_registers; /**< Backup registers for low power restore */ +} i2c_database_t; + +static i2c_database_t g_i2cDataBase[I2C_INSTANCE_NUM] = {0}; + +static I2C_TypeDef* const g_i2cBases[I2C_INSTANCE_NUM] = {I2C0, I2C1}; +#endif + +static ClockId_e g_i2cClocks[I2C_INSTANCE_NUM*2] = {PCLK_I2C0, FCLK_I2C0, PCLK_I2C1, FCLK_I2C1}; + +#ifdef PM_FEATURE_ENABLE +/** + \brief i2c initialization counter, for lower power callback register/de-register + */ +static uint32_t g_i2cInitCounter = 0; + +/** + \brief Bitmap of I2C working status, + when all I2C instances are not working, we can vote to enter to low power state. + */ + +static uint32_t g_i2cWorkingStatus = 0; + +/** + \fn static void I2C_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, I2C hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void I2C_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < I2C_INSTANCE_NUM; i++) + { + if(g_i2cDataBase[i].isInited == true) + { + g_i2cDataBase[i].backup_registers.MCR = g_i2cBases[i]->MCR; + g_i2cDataBase[i].backup_registers.SAR = g_i2cBases[i]->SAR; + g_i2cDataBase[i].backup_registers.TPR = g_i2cBases[i]->TPR; + g_i2cDataBase[i].backup_registers.TOR = g_i2cBases[i]->TOR; + g_i2cDataBase[i].backup_registers.IER = g_i2cBases[i]->IER; + g_i2cDataBase[i].backup_registers.IMR = g_i2cBases[i]->IMR; + } + } + break; + default: + break; + } + +} + +/** + \fn static void I2C_ExitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, I2C hareware is repowered, we restore user's configurations + by aidding of the stored registers. + + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void I2C_ExitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < I2C_INSTANCE_NUM; i++) + { + if(g_i2cDataBase[i].isInited == true) + { + GPR_clockEnable(g_i2cClocks[2*i]); + GPR_clockEnable(g_i2cClocks[2*i+1]); + + g_i2cBases[i]->SAR = g_i2cDataBase[i].backup_registers.SAR; + g_i2cBases[i]->TPR = g_i2cDataBase[i].backup_registers.TPR; + g_i2cBases[i]->TOR = g_i2cDataBase[i].backup_registers.TOR; + g_i2cBases[i]->IER = g_i2cDataBase[i].backup_registers.IER; + g_i2cBases[i]->IMR = g_i2cDataBase[i].backup_registers.IMR; + g_i2cBases[i]->MCR = g_i2cDataBase[i].backup_registers.MCR; + + } + } + break; + + default: + break; + } + +} + +#define LOCK_SLEEP(instance) do \ + { \ + g_i2cWorkingStatus |= (1U << instance); \ + slpManDrvVoteSleep(SLP_VOTE_I2C, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define CHECK_TO_UNLOCK_SLEEP(instance) do \ + { \ + g_i2cWorkingStatus &= ~(1U << instance); \ + if(g_i2cWorkingStatus == 0) \ + slpManDrvVoteSleep(SLP_VOTE_I2C, SLP_SLP1_STATE); \ + } \ + while(0) +#endif + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = +{ + ARM_I2C_API_VERSION, + ARM_I2C_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_I2C_CAPABILITIES DriverCapabilities = +{ + 1 /* supports 10-bit addressing */ +}; + + +#if (RTE_I2C0) + +static I2C_CTRL I2C0_Ctrl = { 0 }; +static PIN I2C0_pin_scl = {RTE_I2C0_SCL_BIT, RTE_I2C0_SCL_FUNC}; +static PIN I2C0_pin_sda = {RTE_I2C0_SDA_BIT, RTE_I2C0_SDA_FUNC}; + +#if (RTE_I2C0_IO_MODE == DMA_MODE) +void I2C0_DmaTxEvent(uint32_t event); +void I2C0_DmaRxEvent(uint32_t event); + +static I2C_DMA I2C0_DMA = { + RTE_I2C0_DMA_TX_CH, + RTE_I2C0_DMA_TX_REQID, + I2C0_DmaTxEvent, + RTE_I2C0_DMA_RX_CH, + RTE_I2C0_DMA_RX_REQID, + I2C0_DmaRxEvent + }; +#endif + +#if (RTE_I2C0_IO_MODE == IRQ_MODE) +void I2C0_IRQHandler(void); + +static I2C_IRQ I2C0_IRQ = { + PXIC_I2c0_IRQn, + I2C0_IRQHandler + }; + +#endif + +static I2C_RESOURCES I2C0_Resources = +{ + I2C0, + { + &I2C0_pin_scl, + &I2C0_pin_sda, + }, +#if (RTE_I2C0_IO_MODE == DMA_MODE) + &I2C0_DMA, +#else + NULL, +#endif + +#if (RTE_I2C0_IO_MODE == IRQ_MODE) + &I2C0_IRQ, +#else + NULL, +#endif + + &I2C0_Ctrl +}; +#endif + +#if (RTE_I2C1) + +static I2C_CTRL I2C1_Ctrl = { 0 }; +static PIN I2C1_pin_scl = {RTE_I2C1_SCL_BIT, RTE_I2C1_SCL_FUNC}; +static PIN I2C1_pin_sda = {RTE_I2C1_SDA_BIT, RTE_I2C1_SDA_FUNC}; + +#if (RTE_I2C1_IO_MODE == DMA_MODE) +void I2C1_DmaTxEvent(uint32_t event); +void I2C1_DmaRxEvent(uint32_t event); + +static I2C_DMA I2C1_DMA = { + DMA_INSTANCE_AP, + RTE_I2C1_DMA_TX_CH, + RTE_I2C1_DMA_TX_REQID, + I2C1_DmaTxEvent, + DMA_INSTANCE_AP, + RTE_I2C1_DMA_RX_CH, + RTE_I2C1_DMA_RX_REQID, + I2C1_DmaRxEvent + }; + +#endif + +#if (RTE_I2C1_IO_MODE == IRQ_MODE) + +void I2C1_IRQHandler(void); + +static I2C_IRQ I2C1_IRQ = { + PXIC_I2c1_IRQn, + I2C1_IRQHandler + }; + +#endif + +static I2C_RESOURCES I2C1_Resources = +{ + I2C1, + { + &I2C1_pin_scl, + &I2C1_pin_sda, + }, +#if (RTE_I2C1_IO_MODE == DMA_MODE) + &I2C1_DMA, +#else + NULL, +#endif + +#if (RTE_I2C1_IO_MODE == IRQ_MODE) + &I2C1_IRQ, +#else + NULL, +#endif + &I2C1_Ctrl +}; +#endif + +// Local Function +/** + \fn ARM_DRIVER_VERSION I2C_GetVersion(void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +ARM_DRIVER_VERSION ARM_I2C_GetVersion(void) +{ + return DriverVersion; +} + + +/** + \fn ARM_I2C_CAPABILITIES I2C_GetCapabilities(void) + \brief Get driver capabilities. + \return \ref ARM_I2C_CAPABILITIES +*/ +ARM_I2C_CAPABILITIES I2C_GetCapabilities() +{ + return DriverCapabilities; +} + +/** + \fn static uint32_t I2C_GetInstanceNumber(I2C_RESOURCES *i2c) + \brief Get instance number + \param[in] i2c Pointer to I2C resources + \returns instance number +*/ +static uint32_t I2C_GetInstanceNumber(I2C_RESOURCES *i2c) +{ + return ((uint32_t)i2c->reg - (uint32_t)I2C0) >> 12; +} + +/** + \fn int32_t I2C_Initialize(ARM_I2C_SignalEvent_t cb_event, + I2C_RESOURCES *i2c) + \brief Initialize I2C Interface. + \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_Initialize(ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c) +{ + int32_t returnCode; +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + PadConfig_t padConfig; + + if(i2c->ctrl->flags & I2C_FLAG_INIT) + { + return ARM_DRIVER_OK; + } + + I2CDEBUG("I2C_Initialize\r\n"); + // Configure I2C Pins + + PAD_getDefaultConfig(&padConfig); + padConfig.mux = i2c->pins.pin_scl->funcNum; + PAD_setPinConfig(i2c->pins.pin_scl->pinNum, &padConfig); + padConfig.mux = i2c->pins.pin_sda->funcNum; + PAD_setPinConfig(i2c->pins.pin_sda->pinNum, &padConfig); + + // Reset Run-Time information structure + memset(i2c->ctrl, 0, sizeof(I2C_CTRL)); + + i2c->ctrl->cb_event = cb_event; + + // Configure DMA if necessary + if(i2c->dma) + { + returnCode = DMA_openChannel(i2c->dma->tx_instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + i2c->dma->tx_ch = returnCode; + + returnCode = DMA_openChannel(i2c->dma->rx_instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + i2c->dma->rx_ch = returnCode; + + + DMA_setChannelRequestSource(i2c->dma->tx_instance, i2c->dma->tx_ch, (DmaRequestSource_e)i2c->dma->tx_req); + DMA_rigisterChannelCallback(i2c->dma->tx_instance, i2c->dma->tx_ch, i2c->dma->tx_callback); + + + DMA_setChannelRequestSource(i2c->dma->rx_instance, i2c->dma->rx_ch, (DmaRequestSource_e)i2c->dma->rx_req); + DMA_rigisterChannelCallback(i2c->dma->rx_instance, i2c->dma->rx_ch, i2c->dma->rx_callback); + } + + i2c->ctrl->flags |= I2C_FLAG_INIT; + +#ifdef PM_FEATURE_ENABLE + + instance = I2C_GetInstanceNumber(i2c); + + g_i2cDataBase[instance].isInited = true; + + g_i2cInitCounter++; + + if(g_i2cInitCounter == 1) + { + g_i2cWorkingStatus = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_I2C_MODULE, I2C_EnterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_I2C_MODULE, I2C_ExitLowPowerStateRestore, NULL); + } +#endif + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t I2C_Uninitialize(I2C_RESOURCES *i2c) + \brief De-initialize I2C Interface. + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_Uninitialize(I2C_RESOURCES *i2c) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + PadConfig_t padConfig; + i2c->ctrl->flags = 0; + i2c->ctrl->cb_event = NULL; + + // Unconfigure SCL and SDA pins + PAD_getDefaultConfig(&padConfig); + padConfig.mux = PAD_MUX_ALT0; + + PAD_setPinConfig(i2c->pins.pin_scl->pinNum, &padConfig); + PAD_setPinConfig(i2c->pins.pin_sda->pinNum, &padConfig); + // Input+pullup + PAD_setPinPullConfig(i2c->pins.pin_scl->pinNum, PAD_INTERNAL_PULL_UP); + PAD_setPinPullConfig(i2c->pins.pin_sda->pinNum, PAD_INTERNAL_PULL_UP); + +#ifdef PM_FEATURE_ENABLE + instance = I2C_GetInstanceNumber(i2c); + g_i2cDataBase[instance].isInited = false; + + g_i2cInitCounter--; + if(g_i2cInitCounter == 0) + { + g_i2cWorkingStatus = 0; + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_I2C_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_I2C_MODULE); + + } +#endif + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t I2C_PowerControl(ARM_POWER_STATE state, + I2C_RESOURCES *i2c) + \brief Control I2C Interface Power. + \param[in] state Power state + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_PowerControl(ARM_POWER_STATE state, I2C_RESOURCES *i2c) +{ + uint32_t instance = I2C_GetInstanceNumber(i2c); + + switch (state) + { + case ARM_POWER_OFF: + // I2C reset controller, including disable all I2C interrupts & clear fifo + if(i2c->irq) + XIC_DisableIRQ(i2c->irq->irq_num); + + // DMA disable + if(i2c->dma) + { + DMA_stopChannel(i2c->dma->tx_instance, i2c->dma->tx_ch, false); + DMA_stopChannel(i2c->dma->rx_instance, i2c->dma->rx_ch, false); + } + // Disable I2C and other control bits + i2c->reg->MCR = 0; + + // Disable I2C power + CLOCK_clockDisable(g_i2cClocks[instance*2]); + CLOCK_clockDisable(g_i2cClocks[instance*2+1]); + + memset((void*)&i2c->ctrl->status, 0, sizeof(ARM_I2C_STATUS)); + + i2c->ctrl->stalled = 0; + i2c->ctrl->snum = 0; + i2c->ctrl->flags &= ~I2C_FLAG_POWER; + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if((i2c->ctrl->flags & I2C_FLAG_INIT) == 0U) + { + return ARM_DRIVER_ERROR; + } + if(i2c->ctrl->flags & I2C_FLAG_POWER) + { + return ARM_DRIVER_OK; + } + + // Enable power to i2c clock + CLOCK_clockEnable(g_i2cClocks[instance*2]); + CLOCK_clockEnable(g_i2cClocks[instance*2+1]); + + // Setup SDA setup/hold time parameter + i2c->reg->TPR = ((0x4 << I2C_TPR_SDA_SETUP_TIME_Pos) | (0x4 << I2C_TPR_SDA_HOLD_TIME_Pos) + | (0x0 << I2C_TPR_SPIKE_FILTER_CNUM_Pos)); + + // Enable I2C irq + if(i2c->irq) + { + XIC_SetVector(i2c->irq->irq_num,i2c->irq->cb_irq); + XIC_EnableIRQ(i2c->irq->irq_num); + } + + i2c->ctrl->flags |= I2C_FLAG_POWER; + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + + +#if 0 +/** + \fn static void I2C_TransferConfig(I2C_RESOURCES *i2c, + uint16_t DevAddress, + uint8_t Size, + uint32_t Request, + uint8_t Mode) + \brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + \param i2c I2C handle. + \param devAddress Specifies the slave address to be programmed. + \param size Specifies the number of bytes to be programmed. + This parameter must be a value between 0 and 255. + \param request New state of the I2C START condition generation. + This parameter can be one of the following values: + \arg \ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + \arg \ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + \arg \ref I2C_GENERATE_START_READ Generate Restart for read request. + \arg \ref I2C_GENERATE_START_WRITE Generate Restart for write request. + \param mode I2C mode + \return void + */ +static void I2C_TransferConfig(I2C_RESOURCES *i2c, uint16_t devAddress, uint8_t size, uint32_t request, uint8_t mode) +{ + uint32_t defaultreg = 0U; + + if((I2C_AUTOMATIC_MODE1 == mode) || (I2C_AUTOMATIC_MODE2 == mode)) + defaultreg |= I2C_MCR_CONTROL_MODE_Msk; + else if(I2C_DEDICATED_MODE == mode) + defaultreg &= ~I2C_MCR_CONTROL_MODE_Msk; + + defaultreg |= ((0x08 << I2C_MCR_TX_FIFO_THRESHOLD_Pos) | (0x08 << I2C_MCR_RX_FIFO_THRESHOLD_Pos) + | I2C_MCR_I2C_EN_Msk); + // Enable DMA + if(i2c->dma) + defaultreg |= (I2C_MCR_TX_DMA_EN_Msk | I2C_MCR_RX_DMA_EN_Msk); + I2CDEBUG("MCR = 0x%x\r\n", defaultreg); + i2c->reg->MCR = defaultreg; + + defaultreg = 0U; + // byte_num_unknown = 0 + if(I2C_AUTOMATIC_MODE1 == mode) + { + // ON Number of bytes (master mode) + defaultreg |= ((size - 1) << I2C_SCR_BYTE_NUM_Pos); + } + else if(I2C_AUTOMATIC_MODE2 == mode) + { + // OFF Number of bytes (master mode) + defaultreg |= I2C_SCR_BYTE_NUM_UNKNOWN_Msk; + } + + defaultreg |= ((devAddress << 1) & (I2C_SCR_TARGET_SLAVE_ADDR_Msk) | (uint32_t)request); + I2CDEBUG("SCR = 0x%x\r\n", defaultreg); + i2c->reg->SCR = defaultreg; + +} +#endif + +typedef enum __I2C_STATE +{ + I2C_STATE_IDLE, // IDLE state + I2C_STATE_MASTER_START, // master START transmitted + I2C_STATE_MASTER_RSTART, // master repeated START transmitted + I2C_STATE_MASTER_SLAW_A, // master SLA+W transmited and ACK received + I2C_STATE_MASTER_SLAW_NA, // master SLA+W transmited but no ACK received + I2C_STATE_MASTER_DT_A, // master data transmited and ACK received + I2C_STATE_MASTER_DT_NA, // master data transmited but no ACK received + I2C_STATE_MASTER_ARB_LOST, // master arbitration lost + I2C_STATE_MASTER_SLAR_A, // master SLA+R transmited and ACK received + I2C_STATE_MASTER_SLAR_NA, // master SLA+R transmited but no ACK received + I2C_STATE_MASTER_DR_A, // master data received and ACK returned + I2C_STATE_MASTER_DR_NA, // master data received but no ACK returned +} I2C_STATE_t; + +void I2C_MasterTransmitStateMachine(I2C_RESOURCES *i2c) +{ + +} + +/** + \fn static int32_t I2C_MasterCheckStatus(I2C_RESOURCES *i2c) + \brief Check status and clear any error if present + \param i2c Pointer to I2C resources + \return ARM_DRIVER_ERROR if any exception occurs, otherwise ARM_DRIVER_OK + */ +static int32_t I2C_MasterCheckStatus(I2C_RESOURCES *i2c) +{ + int32_t ret = ARM_DRIVER_OK; + + volatile uint32_t isr_reg = i2c->reg->ISR; + + if(isr_reg & (I2C_ISR_ARBITRATATION_LOST_Msk | I2C_ISR_BUS_ERROR_Msk | I2C_ISR_RX_NACK_Msk)) + ret = ARM_DRIVER_ERROR; + + // if any exception occurs, clear it + if(ret == ARM_DRIVER_ERROR) + { + if(isr_reg & I2C_ISR_ARBITRATATION_LOST_Msk) + i2c->ctrl->status.arbitration_lost = 1; + + if(isr_reg & I2C_ISR_BUS_ERROR_Msk) + i2c->ctrl->status.bus_error = 1; + + if(isr_reg & I2C_ISR_RX_NACK_Msk) + i2c->ctrl->status.rx_nack = 1; + + i2c->reg->ISR = isr_reg; + i2c->reg->SCR |= (I2C_SCR_FLUSH_TX_FIFO_Msk | I2C_SCR_FLUSH_RX_FIFO_Msk); + } + + return ret; +} + +/** + \fn int32_t I2Cx_MasterTransmit(uint32_t addr, + const uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) + \brief Start transmitting data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[in] data Pointer to buffer with data to transmit to I2C Slave + \param[in] num Number of data bytes to transmit + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + int32_t ret; + uint32_t reg_value; + + //uint8_t send_data; + + DmaTransferConfig_t dmaTxConfig = {(void *)data, (void *)&(i2c->reg->TDR), + DMA_FLOW_CONTROL_TARGET, DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_ONE_BYTE, + DMA_BURST_8_BYTES, num + }; + if(!data || !num || (addr > 0x3ff)) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if(!(i2c->ctrl->flags & I2C_FLAG_SETUP)) + { + return ARM_DRIVER_ERROR; + } + + if(i2c->ctrl->status.busy) + { + return ARM_DRIVER_ERROR_BUSY; + } + +#ifdef PM_FEATURE_ENABLE + instance = I2C_GetInstanceNumber(i2c); +#endif + + // Set control variables + i2c->ctrl->sla_rw = addr; + i2c->ctrl->pending = xfer_pending; + i2c->ctrl->data = (uint8_t *)data; + i2c->ctrl->num = num; + i2c->ctrl->cnt = 0; + + // Update driver status + i2c->ctrl->status.busy = 1; + // 0 :slave / 1 :master + i2c->ctrl->status.mode = 1; + // 0 :tx / 1 :rx + i2c->ctrl->status.direction = 0; + i2c->ctrl->status.arbitration_lost = 0; + i2c->ctrl->status.bus_error = 0; + i2c->ctrl->status.rx_nack = 0; + + if(i2c->reg->STR & I2C_STR_BUSY_Msk) + { + return ARM_DRIVER_ERROR_BUSY; + } + + i2c->ctrl->flags |= I2C_FLAG_MASTER_TX; + // Setup transfer config + // I2C_TransferConfig(i2c, addr & 0x7f, num, I2C_GENERATE_START_WRITE, I2C_AUTOMATIC_MODE1); + + if(i2c->dma) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + + I2CDEBUG("dma configure\n"); + // Configure tx DMA and start it + DMA_transferSetup(i2c->dma->tx_instance, i2c->dma->tx_ch, &dmaTxConfig); + DMA_enableChannelInterrupts(i2c->dma->tx_instance, i2c->dma->tx_ch, DMA_END_INTERRUPT_ENABLE); + + I2CDEBUG("i2c tx dma start\n"); + DMA_startChannel(i2c->dma->tx_instance, i2c->dma->tx_ch); + // Enable interrupts to reflect specific status + i2c->reg->IER = (I2C_IER_TRANSFER_DONE_Msk | + I2C_IER_ARBITRATATION_LOST_Msk | + I2C_IER_DETECT_STOP_Msk | + I2C_IER_BUS_ERROR_Msk | + I2C_IER_RX_NACK_Msk); + + // Clear all flags first(W1C) + i2c->reg->ISR = i2c->reg->ISR; + + // Config and issue command + i2c->reg->MCR = (EIGEN_VAL2FLD(I2C_MCR_TX_FIFO_THRESHOLD, 8) | EIGEN_VAL2FLD(I2C_MCR_RX_FIFO_THRESHOLD, 8) | I2C_MCR_TX_DMA_EN_Msk | I2C_MCR_CONTROL_MODE_Msk | I2C_MCR_I2C_EN_Msk); + + reg_value = (((addr << 1) & (I2C_SCR_TARGET_SLAVE_ADDR_Msk)) | ((num - 1) << I2C_SCR_BYTE_NUM_Pos) | I2C_SCR_START_Msk); + + + i2c->reg->SCR = reg_value; + } + else + { + // Enable interrupts to reflect specific status + i2c->reg->IER = (I2C_IER_TRANSFER_DONE_Msk | + I2C_IER_ARBITRATATION_LOST_Msk | + I2C_IER_DETECT_STOP_Msk | + I2C_IER_BUS_ERROR_Msk | + I2C_IER_RX_NACK_Msk); + + // Clear all flags first(W1C) + i2c->reg->ISR = i2c->reg->ISR; + + // Config and issue command + i2c->reg->MCR = (I2C_MCR_CONTROL_MODE_Msk | I2C_MCR_I2C_EN_Msk); + + reg_value = (((addr << 1) & (I2C_SCR_TARGET_SLAVE_ADDR_Msk)) | ((num - 1) << I2C_SCR_BYTE_NUM_Pos) | I2C_SCR_START_Msk); + + I2CDEBUG("SCR = 0x%x\r\n", reg_value); + + i2c->reg->SCR = reg_value; + + // Send data + while(num > i2c->ctrl->cnt) + { + // Wait for Tx ready + do + { + ret = I2C_MasterCheckStatus(i2c); + + } while(((i2c->reg->FSR & I2C_FSR_TX_FIFO_FREE_NUM_Msk) == 0) && (ret == ARM_DRIVER_OK)); + + if(ret != ARM_DRIVER_OK) + { + i2c->ctrl->status.busy = 0; + return ret; + } + i2c->reg->TDR = i2c->ctrl->data[i2c->ctrl->cnt++]; + } + + // Wait for ACK/NACK + do + { + ret = I2C_MasterCheckStatus(i2c); + + } while((EIGEN_FLD2VAL(I2C_FSR_TX_FIFO_FREE_NUM, i2c->reg->FSR) != 0x10) && (ret == ARM_DRIVER_OK)); + + if(ret != ARM_DRIVER_OK) + { + i2c->ctrl->status.busy = 0; + return ret; + } + + if(xfer_pending == false) + { + i2c->reg->SCR |= I2C_SCR_STOP_Msk; + + // Wait for stop condition has been send out + while((i2c->reg->ISR & I2C_ISR_DETECT_STOP_Msk) == 0); + i2c->reg->ISR = I2C_ISR_DETECT_STOP_Msk; + } + + while(i2c->reg->STR & I2C_STR_BUSY_Msk); + + i2c->reg->IER = 0; + + i2c->ctrl->status.busy = 0; + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t I2Cx_MasterReceive(uint32_t addr, + uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + uint32_t reg_value; + int32_t ret; + + + DmaTransferConfig_t dmaRxConfig = {(void *)&i2c->reg->RDR, (void *)data, + DMA_FLOW_CONTROL_SOURCE, DMA_ADDRESS_INCREMENT_TARGET, + DMA_DATA_WIDTH_ONE_BYTE, + DMA_BURST_8_BYTES, num + }; + if(!data || !num || (addr > 0x3ff)) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if(!(i2c->ctrl->flags & I2C_FLAG_SETUP)) + { + I2CDEBUG("I2C_FLAG_SETUP not done\n"); + return ARM_DRIVER_ERROR; + } + + if(i2c->ctrl->status.busy) + { + return ARM_DRIVER_ERROR_BUSY; + } + +#ifdef PM_FEATURE_ENABLE + instance = I2C_GetInstanceNumber(i2c); +#endif + + I2CDEBUG("I2C_MasterReceive\n"); + + // Set control variables + i2c->ctrl->sla_rw = addr; + i2c->ctrl->pending = xfer_pending; + i2c->ctrl->data = (uint8_t *)data; + i2c->ctrl->num = num; + i2c->ctrl->cnt = 0; + + // Update driver status + i2c->ctrl->status.busy = 1; + // 0 :slave / 1 :master + i2c->ctrl->status.mode = 1; + // 0 :tx / 1 :rx + i2c->ctrl->status.direction = 0; + i2c->ctrl->status.arbitration_lost = 0; + i2c->ctrl->status.bus_error = 0; + i2c->ctrl->status.rx_nack = 0; + + if(i2c->reg->STR & I2C_STR_BUSY_Msk) + { + return ARM_DRIVER_ERROR_BUSY; + } + + i2c->ctrl->flags |= I2C_FLAG_MASTER_RX; + + if(i2c->dma) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + // Configure rx DMA and start it + DMA_transferSetup(i2c->dma->rx_instance, i2c->dma->rx_ch, &dmaRxConfig); + DMA_enableChannelInterrupts(i2c->dma->rx_instance, i2c->dma->rx_ch, DMA_END_INTERRUPT_ENABLE); + + I2CDEBUG("dma configure\n"); + DMA_startChannel(i2c->dma->rx_instance, i2c->dma->rx_ch); + } + else + { + // Enable interrupts to reflect specific status + i2c->reg->IER = (I2C_IER_TRANSFER_DONE_Msk | + I2C_IER_ARBITRATATION_LOST_Msk | + I2C_IER_DETECT_STOP_Msk | + I2C_IER_BUS_ERROR_Msk | + I2C_IER_RX_NACK_Msk); + + + // Clear all flags first(W1C) + i2c->reg->ISR = i2c->reg->ISR; + + // Config and issue command + i2c->reg->MCR = (I2C_MCR_CONTROL_MODE_Msk | I2C_MCR_I2C_EN_Msk); + + reg_value = (((addr << 1) & (I2C_SCR_TARGET_SLAVE_ADDR_Msk)) | ((num - 1) << I2C_SCR_BYTE_NUM_Pos) | I2C_SCR_TARGET_RWN_Msk | I2C_SCR_START_Msk); + + I2CDEBUG("SCR = 0x%x\r\n", reg_value); + + i2c->reg->SCR = reg_value; + + while(num > i2c->ctrl->cnt) + { + // Wait for Rx ready + do + { + ret = I2C_MasterCheckStatus(i2c); + + } while(((i2c->reg->FSR & I2C_FSR_RX_FIFO_DATA_NUM_Msk) == 0) && (ret == ARM_DRIVER_OK)); + + if(ret != ARM_DRIVER_OK) + { + i2c->ctrl->status.busy = 0; + return ret; + } + + i2c->ctrl->data[i2c->ctrl->cnt++] = i2c->reg->RDR; + } + + if(xfer_pending == false) + { + i2c->reg->SCR |= I2C_SCR_STOP_Msk; + + // Wait for stop condition has been send out + while((i2c->reg->ISR & I2C_ISR_DETECT_STOP_Msk) == 0); + i2c->reg->ISR = I2C_ISR_DETECT_STOP_Msk; + } + + while((i2c->reg->ISR & I2C_ISR_TRANSFER_DONE_Msk) == 0); + + i2c->reg->IER = 0; + i2c->ctrl->status.busy = 0; + } + return ARM_DRIVER_OK; +} + +/** + \fn int32_t I2Cx_SlaveTransmit(const uint8_t *data, + uint32_t num, + I2C_RESOURCES *i2c) + \brief Start transmitting data as I2C Slave. + \param[in] data Pointer to buffer with data to transmit to I2C Master + \param[in] num Number of data bytes to transmit + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_SlaveTransmit(const uint8_t *data, uint32_t num, I2C_RESOURCES *i2c) +{ + return ARM_DRIVER_OK; +} + +/** + \fn int32_t I2Cx_MasterReceive(uint32_t addr, + uint8_t *data, + uint32_t num, + bool xfer_pending, + I2C_RESOURCES *i2c) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \param[in] i2c Pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_SlaveReceive(uint8_t *data, uint32_t num, I2C_RESOURCES *i2c) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + if(!data || !num) + { + /* Invalid parameters */ + return ARM_DRIVER_ERROR_PARAMETER; + } + + if(i2c->ctrl->status.busy) + { + /* Transfer operation in progress, Master stalled or Slave transmit stalled */ + return ARM_DRIVER_ERROR_BUSY; + } + +#ifdef PM_FEATURE_ENABLE + instance = I2C_GetInstanceNumber(i2c); +#endif + + /* Set control variables */ + i2c->ctrl->flags |= I2C_FLAG_SLAVE_RX; + i2c->ctrl->sdata = data; + i2c->ctrl->snum = num; + i2c->ctrl->cnt = 0; + + /* Update driver status */ + i2c->ctrl->status.general_call = 0; + i2c->ctrl->status.bus_error = 0; + + // Update driver status + i2c->ctrl->status.busy = 1; + // 0 :slave / 1 :master + i2c->ctrl->status.mode = 0; + // 0 :tx / 1 :rx + i2c->ctrl->status.direction = 1; + + if(i2c->reg->STR & I2C_STR_BUSY_Msk) + { + return ARM_DRIVER_ERROR_BUSY; + } + + if(i2c->dma) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + } + else + { + // Enable interrupts to reflect specific status +#if 0 + i2c->reg->IER = (I2C_IER_TRANSFER_DONE_Msk | + I2C_IER_ARBITRATATION_LOST_Msk | + I2C_IER_DETECT_STOP_Msk | + I2C_IER_BUS_ERROR_Msk | + I2C_IER_RX_NACK_Msk); +#else + i2c->reg->IER = 0x3ffff; +#endif + + // Clear all flags first(W1C) + i2c->reg->ISR = i2c->reg->ISR; + + // Config and issue command + i2c->reg->MCR = EIGEN_VAL2FLD(I2C_MCR_TX_FIFO_THRESHOLD, 8) | EIGEN_VAL2FLD(I2C_MCR_RX_FIFO_THRESHOLD, 8) | \ + I2C_MCR_DISABLE_SCL_STRETCH_Msk | I2C_MCR_AUTOCG_EN_Msk | \ + I2C_MCR_CONTROL_MODE_Msk | I2C_MCR_I2C_EN_Msk | I2C_MCR_DISABLE_MASTER_Msk; + + i2c->reg->SCR = (num - 1) << I2C_SCR_BYTE_NUM_Pos ; //I2C_SCR_BYTE_NUM_UNKNOWN_Msk;//; + + + while((i2c->reg->ISR & I2C_ISR_SLAVE_ADDR_MATCHED_Msk) == 0); + i2c->reg->ISR = I2C_ISR_SLAVE_ADDR_MATCHED_Msk; + + while(num > i2c->ctrl->cnt) + { +#if 1 + if(i2c->reg->ISR & I2C_ISR_RX_ONE_DATA_Msk) + { + i2c->reg->ISR = I2C_ISR_RX_ONE_DATA_Msk; + i2c->reg->SCR = I2C_SCR_ACK_Msk; + i2c->ctrl->sdata[i2c->ctrl->cnt++] = i2c->reg->RDR; + } +#endif + } + + + i2c->reg->IER = 0; + i2c->ctrl->status.busy = 0; + } + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t I2Cx_GetDataCount(I2C_RESOURCES *i2c) + \brief Get transferred data count. + \return number of data bytes transferred; -1 when Slave is not addressed by Master +*/ +int32_t I2C_GetDataCount(I2C_RESOURCES *i2c) +{ + return (i2c->ctrl->cnt); +} + +/** + \fn int32_t I2C_GetClockFreq(I2C_RESOURCES *i2c) + \brief Get i2c clock. + \return value of i2c clock +*/ +int32_t I2C_GetClockFreq(I2C_RESOURCES *i2c) +{ + uint32_t instance = I2C_GetInstanceNumber(i2c); + + return GPR_getClockFreq(g_i2cClocks[instance*2 + 1]); +} + +/** + \fn int32_t I2Cx_Control(uint32_t control, + uint32_t arg, + I2C_RESOURCES *i2c) + \brief Control I2C Interface. + \param[in] control operation + \param[in] arg argument of operation (optional) + \param[in] i2c pointer to I2C resources + \return \ref execution_status +*/ +int32_t I2C_Control(uint32_t control, uint32_t arg, I2C_RESOURCES *i2c) +{ + uint32_t val, clk; + if(!(i2c->ctrl->flags & I2C_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + switch(control) + { + case ARM_I2C_OWN_ADDRESS: + // General call enable + if(arg & ARM_I2C_ADDRESS_GC) + { + i2c->reg->SAR |= I2C_SAR_GENERAL_CALL_EN_Msk; + } + else + { + i2c->reg->SAR &= (~I2C_SAR_GENERAL_CALL_EN_Msk); + } + // Slave address mode 0: 7-bit mode 1: 10-bit mode + if(arg & ARM_I2C_ADDRESS_10BIT) + { + i2c->reg->SAR |= I2C_SAR_SLAVE_ADDR_MODE_Msk; + val = arg & 0x3FF; + } + else + { + i2c->reg->SAR &= (~I2C_SAR_SLAVE_ADDR_MODE_Msk); + val = arg & 0x7F; + } + // Slave address + i2c->reg->SAR |= (val << 1); + // Enable slave address + i2c->reg->SAR |= I2C_SAR_SLAVE_ADDR_EN_Msk; + break; + + case ARM_I2C_BUS_SPEED: + clk = I2C_GetClockFreq(i2c); + switch(arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + // 100kHz + clk /= 100000U; + break; + case ARM_I2C_BUS_SPEED_FAST: + // 400kHz + clk /= 400000U; + break; + case ARM_I2C_BUS_SPEED_FAST_PLUS: + // 1MHz + clk /= 1000000U; + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + i2c->reg->TPR = (((clk / 2) << I2C_TPR_SCLH_Pos) | ((clk / 2 ) << I2C_TPR_SCLL_Pos)) | \ + EIGEN_VAL2FLD(I2C_TPR_SDA_SETUP_TIME, 0) | \ + EIGEN_VAL2FLD(I2C_TPR_SDA_HOLD_TIME, 1) | \ + EIGEN_VAL2FLD(I2C_TPR_SPIKE_FILTER_CNUM, 0); + I2CDEBUG("TPR = 0x%x\r\n", i2c->reg->TPR); + // Speed configured + i2c->ctrl->flags |= I2C_FLAG_SETUP; + break; + + case ARM_I2C_BUS_CLEAR: + break; + + case ARM_I2C_ABORT_TRANSFER: + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +/** + \fn ARM_I2C_STATUS I2Cx_GetStatus(I2C_RESOURCES *i2c) + \brief Get I2C status. + \param[in] i2c pointer to I2C resources + \return I2C status \ref ARM_I2C_STATUS +*/ +ARM_I2C_STATUS I2C_GetStatus(I2C_RESOURCES *i2c) +{ + return (i2c->ctrl->status); +} + + +/** + \fn void I2Cx_IRQHandler(I2C_RESOURCES *i2c) + \brief I2C Event Interrupt handler. + \param[in] i2c Pointer to I2C resources +*/ +void I2C_IRQHandler(I2C_RESOURCES *i2c) +{ + uint32_t tmp_status = 0; + tmp_status = i2c->reg->ISR; + // write 1 clear for those interrupts + i2c->reg->ISR = tmp_status; + + I2CDEBUG("IRQHandler = 0x%x\n", tmp_status); + if(tmp_status & I2C_ISR_TRANSFER_DONE_Msk) + { + I2CDEBUG("I2C_IRQHandler transfer done\r\n"); + + // Clear Tx or Rx flag + i2c->ctrl->flags &= ~(I2C_FLAG_MASTER_TX | I2C_FLAG_MASTER_RX); + i2c->ctrl->status.busy = 0; + if(i2c->ctrl->cb_event) + i2c->ctrl->cb_event(ARM_I2C_EVENT_TRANSFER_DONE); + } + if(tmp_status & I2C_ISR_TX_FIFO_EMPTY_Msk) + { + I2CDEBUG("I2C_IRQHandler tx fifo empty\r\n"); + } + if(tmp_status & I2C_ISR_RX_FIFO_FULL_Msk) + { + I2CDEBUG("I2C_IRQHandler rx fifo full\r\n"); + } + if(tmp_status & I2C_IER_RX_ONE_DATA_Msk) + { + I2CDEBUG("I2C_IRQHandler rx one data\r\n"); + #if 0 + if(i2c->ctrl->num > i2c->ctrl->cnt) + { + temp_data = i2c->reg->RDR; + I2CDEBUG("recv data=%d\n", temp_data); + *(i2c->ctrl->data++) = temp_data; + i2c->ctrl->cnt++; + } + #endif + } + if(tmp_status & I2C_IER_TX_ONE_DATA_Msk) + { + I2CDEBUG("I2C_IRQHandler tx one data\r\n"); + #if 0 + if(i2c->ctrl->num > i2c->ctrl->cnt) + { + if(i2c->ctrl->data) + { + // If data available + temp_data = *(i2c->ctrl->data++); + } + I2CDEBUG("send data=%d\n", temp_data); + i2c->reg->I2CTDR = temp_data; // Activate send + i2c->ctrl->cnt++; + } + #endif + } +} + +/** + \fn void I2C_DmaTxEvent(uint32_t event, I2C_RESOURCES *i2c) + \brief I2C DMA Tx Event handler. + \param[in] event DMA Tx Event + \param[in] i2c Pointer to I2C resources +*/ +void I2C_DmaTxEvent(uint32_t event, I2C_RESOURCES *i2c) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = I2C_GetInstanceNumber(i2c); +#endif + + switch(event) + { + case DMA_EVENT_END: + + I2CDEBUG("I2C_DmaTxEvent\n"); + i2c->ctrl->cnt= i2c->ctrl->num; + i2c->ctrl->status.busy = 0U; + if(i2c->ctrl->cb_event) + { + i2c->ctrl->cb_event(ARM_I2C_EVENT_TRANSFER_DONE); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + + +/** + \fn void I2C_DmaRxEvent(uint32_t event, I2C_RESOURCES *i2c) + \brief I2C DMA Rx Event handler. + \param[in] event DMA Rx Event + \param[in] i2c Pointer to I2C resources +*/ +void I2C_DmaRxEvent(uint32_t event, I2C_RESOURCES *i2c) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = I2C_GetInstanceNumber(i2c); +#endif + + switch(event) + { + case DMA_EVENT_END: + i2c->ctrl->cnt= i2c->ctrl->num; + i2c->ctrl->status.busy = 0U; + if(i2c->ctrl->cb_event) + { + i2c->ctrl->cb_event(ARM_I2C_EVENT_TRANSFER_DONE); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + +#if (RTE_I2C0) +static int32_t I2C0_Initialize(ARM_I2C_SignalEvent_t cb_event) +{ + return I2C_Initialize(cb_event, &I2C0_Resources); +} +static int32_t I2C0_Uninitialize(void) +{ + return I2C_Uninitialize(&I2C0_Resources); +} +static int32_t I2C0_PowerControl(ARM_POWER_STATE state) +{ + return I2C_PowerControl(state, &I2C0_Resources); +} +static int32_t I2C0_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_MasterTransmit(addr, data, num, xfer_pending, &I2C0_Resources); +} +static int32_t I2C0_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_MasterReceive(addr, data, num, xfer_pending, &I2C0_Resources); +} +static int32_t I2C0_SlaveTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_SlaveTransmit(data, num, &I2C0_Resources); +} +static int32_t I2C0_SlaveReceive(uint8_t *data, uint32_t num) +{ + return I2C_SlaveReceive(data, num, &I2C0_Resources); +} +static int32_t I2C0_GetDataCount(void) +{ + return I2C_GetDataCount(&I2C0_Resources); +} +static int32_t I2C0_Control(uint32_t control, uint32_t arg) +{ + return I2C_Control(control, arg, &I2C0_Resources); +} +static ARM_I2C_STATUS I2C0_GetStatus(void) +{ + return I2C_GetStatus(&I2C0_Resources); +} +void I2C0_IRQHandler(void) +{ + I2C_IRQHandler(&I2C0_Resources); +} +void I2C0_DmaTxEvent(uint32_t event) +{ + I2C_DmaTxEvent(event, &I2C0_Resources); +} +void I2C0_DmaRxEvent(uint32_t event) +{ + I2C_DmaRxEvent(event, &I2C0_Resources); +} + +ARM_DRIVER_I2C Driver_I2C0 = +{ + ARM_I2C_GetVersion, + I2C_GetCapabilities, + I2C0_Initialize, + I2C0_Uninitialize, + I2C0_PowerControl, + I2C0_MasterTransmit, + I2C0_MasterReceive, + I2C0_SlaveTransmit, + I2C0_SlaveReceive, + I2C0_GetDataCount, + I2C0_Control, + I2C0_GetStatus +}; + +#endif + +#if (RTE_I2C1) + +static int32_t I2C1_Initialize(ARM_I2C_SignalEvent_t cb_event) +{ + return I2C_Initialize(cb_event, &I2C1_Resources); +} +static int32_t I2C1_Uninitialize(void) +{ + return I2C_Uninitialize(&I2C1_Resources); +} +static int32_t I2C1_PowerControl(ARM_POWER_STATE state) +{ + return I2C_PowerControl(state, &I2C1_Resources); +} +static int32_t I2C1_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_MasterTransmit(addr, data, num, xfer_pending, &I2C1_Resources); +} +static int32_t I2C1_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_MasterReceive(addr, data, num, xfer_pending, &I2C1_Resources); +} +static int32_t I2C1_SlaveTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_SlaveTransmit(data, num, &I2C1_Resources); +} +static int32_t I2C1_SlaveReceive(uint8_t *data, uint32_t num) +{ + return I2C_SlaveReceive(data, num, &I2C1_Resources); +} +static int32_t I2C1_GetDataCount (void) +{ + return I2C_GetDataCount(&I2C1_Resources); +} +static int32_t I2C1_Control(uint32_t control, uint32_t arg) +{ + return I2C_Control(control, arg, &I2C1_Resources); +} +static ARM_I2C_STATUS I2C1_GetStatus(void) +{ + return I2C_GetStatus(&I2C1_Resources); +} +void I2C1_IRQHandler(void) +{ + I2C_IRQHandler(&I2C1_Resources); +} + +void I2C1_DmaTxEvent(uint32_t event) +{ + I2C_DmaTxEvent(event, &I2C1_Resources); +} +void I2C1_DmaRxEvent(uint32_t event) +{ + I2C_DmaRxEvent(event, &I2C1_Resources); +} + +// End I2C Interface + +ARM_DRIVER_I2C Driver_I2C1 = +{ + ARM_I2C_GetVersion, + I2C_GetCapabilities, + I2C1_Initialize, + I2C1_Uninitialize, + I2C1_PowerControl, + I2C1_MasterTransmit, + I2C1_MasterReceive, + I2C1_SlaveTransmit, + I2C1_SlaveReceive, + I2C1_GetDataCount, + I2C1_Control, + I2C1_GetStatus +}; +#endif + diff --git a/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_lpusart.c b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_lpusart.c new file mode 100644 index 0000000..31328d2 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_lpusart.c @@ -0,0 +1,2102 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Driver_Common.h" +#include "bsp_lpusart.h" +#include "slpman.h" + +#ifdef PM_FEATURE_ENABLE + +#include DEBUG_LOG_HEADER_FILE +#define LPUSART_DRIVER_DEBUG 1 + +#endif + +//#pragma push +//#pragma O0 + +#define ARM_LPUSART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ + +#if (!RTE_UART1) +#error "Cooperating UART not enabled in RTE_Device.h!" +#endif + +#define CO_USART_DMA_BURST_SIZE (8) +#define LPUSART_RX_TRIG_LVL (8) + +#ifdef PM_FEATURE_ENABLE +/** \brief Internal used data structure */ +typedef struct _lpusart_database +{ + bool isInited; /**< Whether usart has been initialized */ + struct + { + uint32_t DLL; /**< Divisor Latch Low */ + uint32_t DLH; /**< Divisor Latch High */ + uint32_t IER; /**< Interrupt Enable Register */ + uint32_t FCR; /**< FIFO Control Register */ + uint32_t LCR; /**< Line Control Register */ + uint32_t MCR; /**< Modem Control Register */ + uint32_t MFCR; /**< Main Function Control Register */ + uint32_t EFCR; /**< Extended Function Control Register */ + } co_usart_registers; /**< Backup registers for low power restore */ + struct + { + uint32_t TCR; /**< Timeout Control Register, offset: 0x4 */ + uint32_t FCSR; /**< FIFO Control and Status Register, offset: 0xC */ + uint32_t IER; /**< Interrupt Enable Register, offset: 0x10 */ + } core_registers; + bool autoBaudRateDone; /**< Flag indication whether auto baud dection is done */ +} lpusart_database_t; + +static lpusart_database_t g_lpusartDataBase = {0}; + +#endif + +#ifdef PM_FEATURE_ENABLE +/** + \brief Bitmap of LPUSART working status */ +static uint32_t g_lpusartWorkingStatus = 0; + +/** + \fn static void LPUSART_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, LPUSART hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void LPUSART_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + if(g_lpusartDataBase.isInited == true) + { + g_lpusartDataBase.co_usart_registers.IER = USART_1->IER; + g_lpusartDataBase.co_usart_registers.LCR = USART_1->LCR; + g_lpusartDataBase.co_usart_registers.MCR = USART_1->MCR; + g_lpusartDataBase.co_usart_registers.MFCR = USART_1->MFCR; + g_lpusartDataBase.co_usart_registers.EFCR = USART_1->EFCR; + + g_lpusartDataBase.core_registers.TCR = LPUSART_CORE->TCR; + g_lpusartDataBase.core_registers.FCSR = LPUSART_CORE->FCSR; + g_lpusartDataBase.core_registers.IER = LPUSART_CORE->IER; + } + break; + default: + break; + } + +} + +extern bool apmuGetSleepedFlag(void); + +/** + \fn static void LPUSART_ExitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, LPUSART hareware is repowered, we restore user's configurations + by aidding of the stored registers. + + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + + */ +static void LPUSART_ExitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + // no need to restore if failing to sleep + + if(apmuGetSleepedFlag() == false) + { + break; + } + + if(g_lpusartDataBase.isInited == true) + { + GPR_clockEnable(PCLK_UART1); + GPR_clockEnable(FCLK_UART1); + + USART_1->LCR |= USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + USART_1->DLL = g_lpusartDataBase.co_usart_registers.DLL; + USART_1->DLH = g_lpusartDataBase.co_usart_registers.DLH; + + USART_1->LCR &= ~USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + USART_1->IER = g_lpusartDataBase.co_usart_registers.IER; + USART_1->LCR = g_lpusartDataBase.co_usart_registers.LCR; + USART_1->MCR = g_lpusartDataBase.co_usart_registers.MCR; + USART_1->EFCR = g_lpusartDataBase.co_usart_registers.EFCR; + USART_1->FCR = g_lpusartDataBase.co_usart_registers.FCR; + USART_1->MFCR = g_lpusartDataBase.co_usart_registers.MFCR; + + LPUSART_CORE->DCR = LPUSARTCORE_DCR_RX_REQ_EN_Msk; + LPUSART_CORE->TCR = (LPUSARTCORE_TCR_TOCNT_SWTRG_Msk | g_lpusartDataBase.core_registers.TCR); + LPUSART_CORE->IER = g_lpusartDataBase.core_registers.IER; + } + + break; + + default: + break; + } + +} + +#define LOCK_SLEEP(tx, rx) do \ + { \ + g_lpusartWorkingStatus |= (rx); \ + g_lpusartWorkingStatus |= (tx << 1); \ + slpManDrvVoteSleep(SLP_VOTE_LPUSART, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define CHECK_TO_UNLOCK_SLEEP(tx, rx) do \ + { \ + g_lpusartWorkingStatus &= ~(rx); \ + g_lpusartWorkingStatus &= ~(tx << 1); \ + if(g_lpusartWorkingStatus == 0) \ + { \ + NVIC_ClearPendingIRQ(LpuartWakeup_IRQn); \ + slpManDrvVoteSleep(SLP_VOTE_LPUSART, SLP_SLP1_STATE); \ + } \ + } \ + while(0) +#endif + +#define LPUSART_AON_REGISTER_WRITE(register, value) do \ + { \ + (register) = (value); \ + while((register) != (value)); \ + } \ + while(0) +#define LPUSART_AON_CR1_ENABLE (LPUSARTAON_CR1_ENABLE_Msk | LPUSARTAON_CR1_ACG_EN_Msk) + +// declearation for DMA API +extern void DMA_stopChannelNoWait(DmaInstance_e instance, uint32_t channel); +extern uint32_t DMA_setDescriptorTransferLen(uint32_t dcmd, uint32_t len); +extern void DMA_loadChannelDescriptorAndRun(DmaInstance_e instance, uint32_t channel, void* descriptorAddress); +extern uint32_t DMA_getChannelCurrentTargetAddress(DmaInstance_e instance, uint32_t channel, bool sync); +extern void DMA_buildDescriptor(DmaDescriptor_t* descriptor, const DmaTransferConfig_t* config, const DmaExtraConfig_t* extraConfig); + +// Driver Version +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_LPUSART_DRV_VERSION +}; + +// Driver Capabilities +static const ARM_USART_CAPABILITIES DriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0 /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +void LPUSART1_IRQHandler(void); +void CO_USART1_IRQHandler(void); + +#if (RTE_UART1) + +static LPUSART_INFO LPUSART1_Info = { 0 }; +static const PIN LPUSART1_pin_tx = {RTE_UART1_TX_BIT, RTE_UART1_TX_FUNC}; +static const PIN LPUSART1_pin_rx = {RTE_UART1_RX_BIT, RTE_UART1_RX_FUNC}; +#if (RTE_UART1_CTS_PIN_EN == 1) +static const PIN LPUSART1_pin_cts = {RTE_UART1_CTS_BIT, RTE_UART1_CTS_FUNC}; +#endif +#if (RTE_UART1_RTS_PIN_EN == 1) +static const PIN LPUSART1_pin_rts = {RTE_UART1_RTS_BIT, RTE_UART1_RTS_FUNC}; +#endif + +#if (RTE_UART1_TX_IO_MODE == DMA_MODE) + +void LPUSART1_DmaTxEvent(uint32_t event); +static LPUSART_TX_DMA LPUSART1_DMA_Tx = { + DMA_INSTANCE_MP, + -1, + RTE_UART1_DMA_TX_REQID, + LPUSART1_DmaTxEvent + }; +#endif + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) + +void CO_USART1_DmaRxEvent(uint32_t event); +static DmaDescriptor_t __ALIGNED(16) CO_USART1_DMA_Rx_Descriptor[2]; + +static LPUSART_RX_DMA CO_USART1_DMA_Rx = { + DMA_INSTANCE_MP, + -1, + RTE_UART1_DMA_RX_REQID, + CO_USART1_DMA_Rx_Descriptor, + CO_USART1_DmaRxEvent + }; + +static DmaDescriptor_t __ALIGNED(16) LPUSART1_DMA_Rx_Descriptor; + +static LPUSART_RX_DMA LPUSART1_DMA_Rx = { + DMA_INSTANCE_MP, + -1, + DMA_REQUEST_LPUSART_RX, + &LPUSART1_DMA_Rx_Descriptor, + NULL + }; + +#endif + +#if (RTE_UART1_TX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == DMA_MODE) +static LPUSART_IRQ CO_USART1_IRQ = { + PXIC0_UART1_IRQn, + CO_USART1_IRQHandler + }; + +static LPUSART_IRQ LPUSART1_IRQ = { + PXIC0_LPUC_IRQn, + LPUSART1_IRQHandler + }; +#endif + +static const LPUSART_RESOURCES LPUSART1_Resources = { + USART_1, + LPUSART_AON, + LPUSART_CORE, + { + &LPUSART1_pin_tx, + &LPUSART1_pin_rx, +#if (RTE_UART1_CTS_PIN_EN == 1) + &LPUSART1_pin_cts, +#else + NULL, +#endif +#if (RTE_UART1_RTS_PIN_EN == 1) + &LPUSART1_pin_rts, +#else + NULL, +#endif + }, + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) + &LPUSART1_DMA_Rx, +#else + NULL, +#endif + +#if (RTE_UART1_TX_IO_MODE == DMA_MODE) + &LPUSART1_DMA_Tx, +#else + NULL, +#endif + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) + &CO_USART1_DMA_Rx, +#else + NULL, +#endif + +#if (RTE_UART1_TX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == DMA_MODE) + &LPUSART1_IRQ, + &CO_USART1_IRQ, +#else + NULL, + NULL, +#endif + &LPUSART1_Info +}; +#endif + + +static DmaTransferConfig_t dmaTxConfig = {NULL, NULL, + DMA_FLOW_CONTROL_TARGET, DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_ONE_BYTE, DMA_BURST_16_BYTES, 0 + }; + +ARM_DRIVER_VERSION LPUSART_GetVersion(void) +{ + return DriverVersion; +} + +ARM_USART_CAPABILITIES LPUSART_GetCapabilities(void) +{ + return DriverCapabilities; +} + +/* + * when uart input clock is 26000000, the supported baudrate is: + * 4800,9600,14400,19200, + * 28800,38400,56000,57600, + * 115200,230400,460800,921600, + * 1000000,1500000,2000000,3000000 + */ +int32_t LPUSART_SetBaudrate(uint32_t baudrate, LPUSART_RESOURCES *lpusart) +{ + uint8_t frac = 0; + uint32_t uart_clock = 0; + uint32_t div; + int32_t i; + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + const static uint16_t g_lpusartSupportedBaudRate[5] = {600, 1200, 2400, 4800, 9600}; + + // timeout threshold is 24 bits, sample clock is 26M, threshold/26M = 24/baudrate + const static uint32_t g_lpusartTimeoutValue[5] = {1040000, 520000, 260000, 130000, 65000}; + + const static uint16_t g_lpusartDLRValue[5] = {1748, 874, 437, 218, 109}; + + for(i = 0; i <= 4; i++) + { + if(baudrate == g_lpusartSupportedBaudRate[i]) + { + if((lpusart->core_regs->FCSR & (LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk | LPUSARTCORE_FCSR_AON_RX_BUSY_Msk | LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk)) == (LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk | LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk)) + { + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR0, LPUSARTAON_CR0_CLK_ENABLE_Msk); + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->DLR, g_lpusartDLRValue[i]); + } + lpusart->core_regs->TCR |= LPUSARTCORE_TCR_TOCNT_SWCLR_Msk; + lpusart->core_regs->TCR = g_lpusartTimeoutValue[i]; + lpusart->core_regs->TCR |= LPUSARTCORE_TCR_TOCNT_SWTRG_Msk; + break; + } + } + + if(i > 5) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + } + + if(baudrate == 0) + { + lpusart->co_usart_regs->ADCR = 0x3; + } + else + { + uart_clock = GPR_getClockFreq(FCLK_UART1); + + /* + * formula to calculate baudrate, baudrate = clock_in / (prescalar * divisor_value), + * where prescalar = MFCR_PRESCALE_FACTOR(4,8,16), divisor_value = DLH:DLL.EFCR_FRAC + */ + for(i = 0; i <= 2; i++) + { + div = (1 << i) * uart_clock / baudrate; + frac = div & 0xf; + div >>= 4; + // Integer part of divisor value shall not be zero, otherwise, the result is invalid + if (div != 0) + break; + } + + if(i > 2) + return ARM_DRIVER_ERROR_PARAMETER; + + // Disable uart first + lpusart->co_usart_regs->MFCR &= ~USART_MFCR_UART_EN_Msk; + + // Enable latch bit to change divisor + lpusart->co_usart_regs->LCR |= USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + lpusart->co_usart_regs->MFCR = ((lpusart->co_usart_regs->MFCR & ~USART_MFCR_PRESCALE_FACTOR_Msk) | EIGEN_VAL2FLD(USART_MFCR_PRESCALE_FACTOR, i)); + lpusart->co_usart_regs->DLL = (div >> 0) & 0xff; + lpusart->co_usart_regs->DLH = (div >> 8) & 0xff; + lpusart->co_usart_regs->EFCR = ((lpusart->co_usart_regs->EFCR & ~USART_EFCR_FRAC_DIVISOR_Msk) | (frac << USART_EFCR_FRAC_DIVISOR_Pos)); + // Reset latch bit + lpusart->co_usart_regs->LCR &= (~USART_LCR_ACCESS_DIVISOR_LATCH_Msk); + +#ifdef PM_FEATURE_ENABLE + // backup setting + g_lpusartDataBase.co_usart_registers.DLL = (div >> 0) & 0xff; + g_lpusartDataBase.co_usart_registers.DLH = (div >> 8) & 0xff; +#endif + + } + + lpusart->info->baudrate = baudrate; + + return ARM_DRIVER_OK; +} + +uint32_t LPUSART_GetBaudRate(LPUSART_RESOURCES *lpusart) +{ + return lpusart->info->baudrate; +} + +/* + * Check whether rx is ongoing, return true if rx is ongoing at this moment, otherwise false + */ +bool LPUSART_IsRxActive(void) +{ +#ifdef PM_FEATURE_ENABLE + if(LPUSART1_Info.flags & LPUSART_FLAG_POWER_LOW) + { + return !((LPUSART_CORE->FCSR & (LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk | LPUSARTCORE_FCSR_AON_RX_BUSY_Msk | LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk)) == (LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk | LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk)); + } + else + { + return 0; + } +#else + return 0; +#endif +} + +void LPUSART_ClearStopFlag(void) +{ +#ifdef PM_FEATURE_ENABLE + if(LPUSART1_Info.flags & LPUSART_FLAG_POWER_LOW) + { + LPUSART_AON->SCR = LPUSARTAON_SCR_STOP_SW_CLR_Msk; + while(LPUSART_CORE->FCSR & LPUSARTCORE_FCSR_AON_STOP_FLAG_Msk); + LPUSART_AON->SCR = 0; + } +#endif +} + +void LPUSART_SetStopFlag(void) +{ +#ifdef PM_FEATURE_ENABLE + if(LPUSART1_Info.flags & LPUSART_FLAG_POWER_LOW) + { + LPUSART_AON->SCR = LPUSARTAON_SCR_STOP_SW_SET_Msk; + while((LPUSART_CORE->FCSR & LPUSARTCORE_FCSR_AON_STOP_FLAG_Msk) == 0); + LPUSART_AON->SCR = 0; + } +#endif +} + +static void LPUSART_DMARxConfig(LPUSART_RESOURCES *lpusart, bool isLpuart) +{ + DmaTransferConfig_t dmaConfig; + DmaExtraConfig_t extraConfig; + + dmaConfig.addressIncrement = DMA_ADDRESS_INCREMENT_TARGET; + dmaConfig.dataWidth = DMA_DATA_WIDTH_ONE_BYTE; + dmaConfig.flowControl = DMA_FLOW_CONTROL_SOURCE; + dmaConfig.targetAddress = NULL; + + if(isLpuart == true) + { + dmaConfig.burstSize = DMA_BURST_64_BYTES; + dmaConfig.sourceAddress = (void*)&(lpusart->core_regs->RBR); + dmaConfig.targetAddress = NULL; + dmaConfig.totalLength = LPUSART_RX_TRIG_LVL - 1; + extraConfig.stopDecriptorFetch = true; + extraConfig.enableStartInterrupt = false; + extraConfig.enableEndInterrupt = false; + extraConfig.nextDesriptorAddress = lpusart->dma_rx->descriptor; + + DMA_buildDescriptor(lpusart->dma_rx->descriptor, &dmaConfig, &extraConfig); + + DMA_resetChannel(lpusart->dma_rx->instance, lpusart->dma_rx->channel); + + } + else + { + dmaConfig.burstSize = DMA_BURST_8_BYTES; + dmaConfig.sourceAddress = (void*)&(lpusart->co_usart_regs->RBR); + dmaConfig.totalLength = CO_USART_DMA_BURST_SIZE; + + extraConfig.stopDecriptorFetch = false; + extraConfig.enableStartInterrupt = false; + extraConfig.enableEndInterrupt = true; + extraConfig.nextDesriptorAddress = &lpusart->co_usart_dma_rx->descriptor[1]; + + DMA_buildDescriptor(&lpusart->co_usart_dma_rx->descriptor[0], &dmaConfig, &extraConfig); + + extraConfig.stopDecriptorFetch = true; + extraConfig.nextDesriptorAddress = &lpusart->co_usart_dma_rx->descriptor[0]; + + DMA_buildDescriptor(&lpusart->co_usart_dma_rx->descriptor[1], &dmaConfig, &extraConfig); + + DMA_resetChannel(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel); + + } +} + +PLAT_PA_RAMCODE static void CO_USART_DmaUpdateRxConfig(LPUSART_RESOURCES *lpusart, uint32_t targetAddress, uint32_t num) +{ + uint32_t firstDescriptorLen = MIN(num, CO_USART_DMA_BURST_SIZE); + + lpusart->co_usart_dma_rx->descriptor[0].TAR = targetAddress; + lpusart->co_usart_dma_rx->descriptor[0].CMDR = DMA_setDescriptorTransferLen(lpusart->co_usart_dma_rx->descriptor[1].CMDR, firstDescriptorLen); + + lpusart->co_usart_dma_rx->descriptor[1].TAR = lpusart->co_usart_dma_rx->descriptor[0].TAR + firstDescriptorLen; + lpusart->co_usart_dma_rx->descriptor[1].CMDR = DMA_setDescriptorTransferLen(lpusart->co_usart_dma_rx->descriptor[1].CMDR, num - firstDescriptorLen); +} + + +int32_t LPUSART_Initialize(ARM_USART_SignalEvent_t cb_event, LPUSART_RESOURCES *lpusart) +{ + int32_t returnCode; + + if (lpusart->info->flags & LPUSART_FLAG_INITIALIZED) + return ARM_DRIVER_OK; + + // Pin initialize + PadConfig_t config; + PAD_getDefaultConfig(&config); + + config.mux = lpusart->pins.pin_tx->funcNum; + PAD_setPinConfig(lpusart->pins.pin_tx->pinNum, &config); + + config.pullSelect = PAD_PULL_INTERNAL; + config.pullUpEnable = PAD_PULL_UP_ENABLE; + config.pullDownEnable = PAD_PULL_DOWN_DISABLE; + config.mux = lpusart->pins.pin_rx->funcNum; + PAD_setPinConfig(lpusart->pins.pin_rx->pinNum, &config); + + if(lpusart->pins.pin_cts) + { + config.mux = lpusart->pins.pin_cts->funcNum; + PAD_setPinConfig(lpusart->pins.pin_cts->pinNum, &config); + } + + if(lpusart->pins.pin_rts) + { + config.mux = lpusart->pins.pin_rts->funcNum; + PAD_setPinConfig(lpusart->pins.pin_rts->pinNum, &config); + } + +#ifdef PM_FEATURE_ENABLE + g_lpusartDataBase.isInited = true; +#endif + + // Initialize LPUSART run-time resources + lpusart->info->cb_event = cb_event; + memset(&(lpusart->info->rx_status), 0, sizeof(LPUSART_STATUS)); + + lpusart->info->xfer.send_active = 0; + lpusart->info->xfer.tx_def_val = 0; + + if(lpusart->co_usart_dma_tx) + { + returnCode = DMA_openChannel(lpusart->co_usart_dma_tx->instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + lpusart->co_usart_dma_tx->channel = returnCode; + + DMA_setChannelRequestSource(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel, (DmaRequestSource_e)lpusart->co_usart_dma_tx->request); + DMA_rigisterChannelCallback(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel, lpusart->co_usart_dma_tx->callback); + } + + if(lpusart->co_usart_dma_rx) + { + returnCode = DMA_openChannel(lpusart->co_usart_dma_rx->instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + lpusart->co_usart_dma_rx->channel = returnCode; + + DMA_setChannelRequestSource(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, (DmaRequestSource_e)lpusart->co_usart_dma_rx->request); + LPUSART_DMARxConfig(lpusart, false); + DMA_rigisterChannelCallback(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, lpusart->co_usart_dma_rx->callback); + } + + if(lpusart->dma_rx) + { + returnCode = DMA_openChannel(lpusart->dma_rx->instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + lpusart->dma_rx->channel = returnCode; + + DMA_setChannelRequestSource(lpusart->dma_rx->instance, lpusart->dma_rx->channel, (DmaRequestSource_e)lpusart->dma_rx->request); + LPUSART_DMARxConfig(lpusart, true); + } + + lpusart->info->flags = LPUSART_FLAG_INITIALIZED; // LPUSART is initialized + +#ifdef PM_FEATURE_ENABLE + g_lpusartWorkingStatus = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_LPUSART_MODULE, LPUSART_EnterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_LPUSART_MODULE, LPUSART_ExitLowPowerStateRestore, NULL); +#endif + return ARM_DRIVER_OK; +} + +int32_t LPUSART_Uninitialize(LPUSART_RESOURCES *lpusart) +{ + lpusart->info->flags = 0; + lpusart->info->cb_event = NULL; + + if(lpusart->co_usart_dma_tx) + { + DMA_closeChannel(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel); + } + + if(lpusart->co_usart_dma_rx) + { + DMA_closeChannel(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel); + } + + if(lpusart->dma_rx) + { + DMA_closeChannel(lpusart->dma_rx->instance, lpusart->dma_rx->channel); + } + +#ifdef PM_FEATURE_ENABLE + + g_lpusartDataBase.isInited = false; + g_lpusartWorkingStatus = 0; + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_LPUSART_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_LPUSART_MODULE); +#endif + + return ARM_DRIVER_OK; +} + +int32_t LPUSART_PowerControl(ARM_POWER_STATE state,LPUSART_RESOURCES *lpusart) +{ + uint32_t val = 0; + + switch (state) + { + case ARM_POWER_OFF: + + // Reset LPUSART + GPR_swReset(RST_PCLK_UART1); + GPR_swReset(RST_FCLK_UART1); + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + GPR_swReset(RST_LPUA); + + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR1, 0); + + } + + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR0, 0); + + // DMA disable + if(lpusart->co_usart_dma_tx) + DMA_stopChannel(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel, false); + + if(lpusart->co_usart_dma_rx) + DMA_stopChannel(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, false); + + if(lpusart->dma_rx) + DMA_stopChannel(lpusart->dma_rx->instance, lpusart->dma_rx->channel, false); + + // Disable clock + GPR_clockDisable(PCLK_LPUC); + GPR_clockDisable(PCLK_UART1); + GPR_clockDisable(FCLK_UART1); + + // Clear driver variables + memset(&(lpusart->info->rx_status), 0, sizeof(LPUSART_STATUS)); + lpusart->info->frame_code = 0; + lpusart->info->xfer.send_active = 0; + + // Disable LPUSART IRQ + if(lpusart->irq) + { + XIC_ClearPendingIRQ(lpusart->irq->irq_num); + XIC_DisableIRQ(lpusart->irq->irq_num); + } + + if(lpusart->co_usart_irq) + { + XIC_ClearPendingIRQ(lpusart->co_usart_irq->irq_num); + XIC_DisableIRQ(lpusart->co_usart_irq->irq_num); + } + + lpusart->info->flags &= ~(LPUSART_FLAG_POWER_MSK | LPUSART_FLAG_CONFIGURED); + + break; + + case ARM_POWER_LOW: + if((lpusart->info->flags & LPUSART_FLAG_INITIALIZED) == 0) + { + return ARM_DRIVER_ERROR; + } + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + return ARM_DRIVER_OK; + } + + // Enable lpusart clock + GPR_clockEnable(PCLK_LPUC); + GPR_clockEnable(PCLK_UART1); + GPR_clockEnable(FCLK_UART1); + + // Disable interrupts + lpusart->co_usart_regs->IER = 0; + lpusart->core_regs->IER = 0; + + // Clear driver variables + memset(&(lpusart->info->rx_status), 0, sizeof(LPUSART_STATUS)); + lpusart->info->frame_code = 0; + lpusart->info->xfer.send_active = 0; + + // Configure FIFO Control register + val = USART_FCR_FIFO_EN_Msk | USART_FCR_RESET_TX_FIFO_Msk; + + lpusart->co_usart_regs->FCR = val; + +#ifdef PM_FEATURE_ENABLE + g_lpusartDataBase.co_usart_registers.FCR = val; +#endif + + val = EIGEN_VAL2FLD(LPUSARTCORE_FCSR_RXFIFO_THRLD, LPUSART_RX_TRIG_LVL); + //val |= LPUSARTCORE_FCSR_FLUSH_RXFIFO_Msk; + lpusart->core_regs->FCSR = val; + + if(lpusart->co_usart_dma_tx) + { + lpusart->co_usart_regs->MFCR |= USART_MFCR_DMA_EN_Msk; + } + + if(lpusart->dma_rx) + { + lpusart->core_regs->DCR = LPUSARTCORE_DCR_RX_REQ_EN_Msk; + } + + if(lpusart->irq) + { + XIC_SetVector(lpusart->irq->irq_num, lpusart->irq->cb_irq); + XIC_EnableIRQ(lpusart->irq->irq_num); + XIC_SuppressOvfIRQ(lpusart->irq->irq_num); + } + if(lpusart->co_usart_irq) + { + XIC_SetVector(lpusart->co_usart_irq->irq_num, lpusart->co_usart_irq->cb_irq); + XIC_EnableIRQ(lpusart->co_usart_irq->irq_num); + XIC_SuppressOvfIRQ(lpusart->co_usart_irq->irq_num); + } + + lpusart->info->flags |= LPUSART_FLAG_POWER_LOW; // LPUSART is powered on + + break; + + case ARM_POWER_FULL: + if((lpusart->info->flags & LPUSART_FLAG_INITIALIZED) == 0) + { + return ARM_DRIVER_ERROR; + } + if(lpusart->info->flags & LPUSART_FLAG_POWER_FULL) + { + return ARM_DRIVER_OK; + } + + // Enable cooperating usart clock + GPR_clockEnable(PCLK_AON); + GPR_clockEnable(PCLK_UART1); + GPR_clockEnable(FCLK_UART1); + + GPR_swReset(RST_PCLK_UART1); + GPR_swReset(RST_FCLK_UART1); + + // Clear driver variables + memset(&(lpusart->info->rx_status), 0, sizeof(LPUSART_STATUS)); + lpusart->info->frame_code = 0; + lpusart->info->xfer.send_active = 0; + + // Configure FIFO Control register + val = USART_FCR_FIFO_EN_Msk | USART_FCR_RESET_RX_FIFO_Msk | USART_FCR_RESET_TX_FIFO_Msk; + + // rxfifo trigger level set as 16 bytes + val |= (2U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + + lpusart->co_usart_regs->FCR = val; + +#ifdef PM_FEATURE_ENABLE + g_lpusartDataBase.co_usart_registers.FCR = val; +#endif + + if(lpusart->co_usart_dma_tx || lpusart->co_usart_dma_rx) + { + lpusart->co_usart_regs->MFCR |= USART_MFCR_DMA_EN_Msk; + } + + if(lpusart->co_usart_irq) + { + XIC_SetVector(lpusart->co_usart_irq->irq_num, lpusart->co_usart_irq->cb_irq); + XIC_EnableIRQ(lpusart->co_usart_irq->irq_num); + XIC_SuppressOvfIRQ(lpusart->co_usart_irq->irq_num); + } + lpusart->info->flags |= LPUSART_FLAG_POWER_FULL; // LPUSART is powered on + + // Enable wakeup feature only + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR0, LPUSARTAON_CR0_RX_ENABLE_Msk); + + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +int32_t LPUSART_Send(const void *data, uint32_t num, LPUSART_RESOURCES *lpusart) +{ + uint32_t mask; + if ((data == NULL) || (num == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + if ((lpusart->info->flags & LPUSART_FLAG_CONFIGURED) == 0) + return ARM_DRIVER_ERROR; + +#ifdef PM_FEATURE_ENABLE + if((lpusart->co_usart_regs->ADCR & USART_ADCR_AUTO_BAUD_INT_EN_Msk) && (g_lpusartDataBase.autoBaudRateDone == false)) + { + return ARM_DRIVER_OK; + } +#endif + + mask = SaveAndSetIRQMask(); + if (lpusart->info->xfer.send_active != 0) + { + RestoreIRQMask(mask); + return ARM_DRIVER_ERROR_BUSY; + } + + lpusart->info->xfer.send_active = 1U; + RestoreIRQMask(mask); + + // Save transmit buffer info + lpusart->info->xfer.tx_buf = (uint8_t *)data; + lpusart->info->xfer.tx_num = num; + lpusart->info->xfer.tx_cnt = 0; + // DMA mode + if(lpusart->co_usart_dma_tx) + { +#if 0 + // wait until tx is empty + while((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0); +#else + // relax the constraint + while(EIGEN_FLD2VAL(USART_FCNR_TX_FIFO_NUM, lpusart->co_usart_regs->FCNR) > 16); +#endif + +#ifdef PM_FEATURE_ENABLE + mask = SaveAndSetIRQMask(); + + LOCK_SLEEP(1, 0); + + RestoreIRQMask(mask); +#endif + + if(num == 1) + { + mask = SaveAndSetIRQMask(); + + lpusart->co_usart_regs->IER |= USART_IER_TX_DATA_REQ_Msk; + + lpusart->co_usart_regs->THR = lpusart->info->xfer.tx_buf[0]; + + RestoreIRQMask(mask); + } + else + { + dmaTxConfig.sourceAddress = (void*)data; + dmaTxConfig.targetAddress = (void*)&(lpusart->co_usart_regs->THR); + dmaTxConfig.totalLength = num - 1; + + // Configure tx DMA and start it + DMA_transferSetup(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel, &dmaTxConfig); + DMA_enableChannelInterrupts(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel); + } + + } + else + { + while (lpusart->info->xfer.tx_cnt < lpusart->info->xfer.tx_num) + { + // wait until tx is empty + while((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + lpusart->co_usart_regs->THR = lpusart->info->xfer.tx_buf[lpusart->info->xfer.tx_cnt++]; + } + while((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + mask = SaveAndSetIRQMask(); + lpusart->info->xfer.send_active = 0; + RestoreIRQMask(mask); + } + + return ARM_DRIVER_OK; +} + +int32_t LPUSART_SendPolling(const void *data, uint32_t num, LPUSART_RESOURCES *lpusart) +{ + uint32_t mask; + if ((data == NULL) || (num == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + if ((lpusart->info->flags & LPUSART_FLAG_CONFIGURED) == 0) + return ARM_DRIVER_ERROR; + +#ifdef PM_FEATURE_ENABLE + if((lpusart->co_usart_regs->ADCR & USART_ADCR_AUTO_BAUD_INT_EN_Msk) && (g_lpusartDataBase.autoBaudRateDone == false)) + { + return ARM_DRIVER_OK; + } +#endif + + mask = SaveAndSetIRQMask(); + if (lpusart->info->xfer.send_active != 0) + { + RestoreIRQMask(mask); + return ARM_DRIVER_ERROR_BUSY; + } + + lpusart->info->xfer.send_active = 1U; + RestoreIRQMask(mask); + + // Save transmit buffer info + lpusart->info->xfer.tx_buf = (uint8_t *)data; + lpusart->info->xfer.tx_num = num; + lpusart->info->xfer.tx_cnt = 0; + + while (lpusart->info->xfer.tx_cnt < lpusart->info->xfer.tx_num) + { + // wait until tx is empty + while((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + lpusart->co_usart_regs->THR = lpusart->info->xfer.tx_buf[lpusart->info->xfer.tx_cnt++]; + } + while((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + mask = SaveAndSetIRQMask(); + lpusart->info->xfer.send_active = 0; + RestoreIRQMask(mask); + + return ARM_DRIVER_OK; +} + +PLAT_PA_RAMCODE int32_t LPUSART_Receive(void *data, uint32_t num, LPUSART_RESOURCES *lpusart) +{ + uint32_t mask, bytes_in_fifo, i; + + volatile uint32_t left_to_recv = num; + + if ((data == NULL) || num == 0) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((lpusart->info->flags & LPUSART_FLAG_CONFIGURED) == 0) + { + return ARM_DRIVER_ERROR; + } + + // check if receiver is busy + if (lpusart->info->rx_status.rx_busy == 1U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + lpusart->info->rx_status.rx_busy = 1U; + + // save num of data to be received + lpusart->info->xfer.rx_num = num; + lpusart->info->xfer.rx_buf = (uint8_t *)data; + lpusart->info->xfer.rx_cnt = 0; + + if(lpusart->dma_rx || lpusart->co_usart_dma_rx) + { + lpusart->info->rx_status.rx_dma_triggered = 0; + + if(lpusart->co_usart_dma_rx) + { + CO_USART_DmaUpdateRxConfig(lpusart, (uint32_t)data, num); + } + } + + if(lpusart->info->flags & LPUSART_FLAG_POWER_FULL) + { + lpusart->co_usart_regs->IER |= USART_IER_RX_LINE_STATUS_Msk; + + lpusart->info->rx_status.rx_busy = 1U; + + // Lucky :), we have bytes waiting, try our best to receive all of them, however, let normal recv process handle the case if new data keeps arriving + while((bytes_in_fifo = EIGEN_FLD2VAL(USART_FCNR_RX_FIFO_NUM, lpusart->co_usart_regs->FCNR)) > 0) + { + + if(lpusart->co_usart_regs->LSR & USART_LSR_RX_BUSY_Msk) + { + break; + } + + left_to_recv = num - lpusart->info->xfer.rx_cnt; + + i = MIN(bytes_in_fifo, left_to_recv); + + while(i--) + { + lpusart->info->xfer.rx_buf[lpusart->info->xfer.rx_cnt++] = lpusart->co_usart_regs->RBR; + } + + left_to_recv = num - lpusart->info->xfer.rx_cnt; + + // prepare in advance for dma recv + if(lpusart->co_usart_dma_rx) + { + CO_USART_DmaUpdateRxConfig(lpusart, (uint32_t)&lpusart->info->xfer.rx_buf[lpusart->info->xfer.rx_cnt], left_to_recv); + } + + if(left_to_recv == 0) + { + // Full + lpusart->info->rx_status.rx_busy = 0; + + lpusart->co_usart_regs->IER &= ~USART_IER_RX_LINE_STATUS_Msk; + + if(lpusart->info->cb_event != NULL) + { + lpusart->info->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + + return ARM_DRIVER_OK; + + } + + // check again whether there's ongoing data stream + if(lpusart->co_usart_regs->LSR & USART_LSR_RX_BUSY_Msk) + { + break; + } + + } + + // need to add protection to check rxfifo in irqHandler for 'fake' timeout, that's caused by + // we have try to receive bytes from rxfifo as many as possible so when timeout occurs, there maybe no bytes left in rxfifo + if(lpusart->co_usart_dma_rx) + { + lpusart->co_usart_regs->IER |= USART_IER_RX_TIMEOUT_Msk; + + DMA_loadChannelDescriptorAndRun(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, &lpusart->co_usart_dma_rx->descriptor[0]); + + if(lpusart->info->xfer.rx_cnt != 0) + { + if(lpusart->co_usart_regs->LSR & USART_LSR_RX_BUSY_Msk) + { + // do nothing if there's still data coming since we can let isr report later + } + else + { + // report to upper layer that we've received some data + lpusart->info->rx_status.rx_busy = 0; + + // rx_busy is not reliable flag since it'll change to 0 on stop bit + // so it's possible here to break the continuous rx data steam into two parts + if(lpusart->info->cb_event != NULL) + { + lpusart->info->cb_event(ARM_USART_EVENT_RX_TIMEOUT); + } + } + + } + + } + else if(lpusart->co_usart_irq) + { + lpusart->co_usart_regs->IER |= USART_IER_RX_TIMEOUT_Msk | \ + USART_IER_RX_DATA_REQ_Msk; + + if(lpusart->info->xfer.rx_cnt != 0) + { + if(lpusart->co_usart_regs->LSR & USART_LSR_RX_BUSY_Msk) + { + // do nothing if there's still data coming since we can let isr report later + } + else + { + // report to upper layer that we've received some data + lpusart->info->rx_status.rx_busy = 0; + + // rx_busy is not reliable flag since it'll change to 0 on stop bit + // so it's possible here to break the continuous rx data steam into two parts + if(lpusart->info->cb_event != NULL) + { + lpusart->info->cb_event(ARM_USART_EVENT_RX_TIMEOUT); + } + } + + } + } + else + { + while(lpusart->info->xfer.rx_cnt < lpusart->info->xfer.rx_num) + { + //wait unitl receive data is ready + while((lpusart->co_usart_regs->LSR & USART_LSR_RX_DATA_READY_Msk) == 0); + //read data + lpusart->info->xfer.rx_buf[lpusart->info->xfer.rx_cnt++] = lpusart->co_usart_regs->RBR; + } + lpusart->info->rx_status.rx_busy = 0; + } + } + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + if(lpusart->irq) + { +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_recv_0, P_DEBUG, "lpuart recv enter, iir: 0x%x, fcsr: 0x%x, tcr: 0x%x, tsr: 0x%x", lpusart->core_regs->IIR, lpusart->core_regs->FCSR, lpusart->core_regs->TCR, lpusart->core_regs->TSR); +#endif + mask = SaveAndSetIRQMask(); + + // refresh timeout counter when wakeup from low power state + lpusart->core_regs->IIR |= LPUSARTCORE_IIR_CLR_Msk; + lpusart->core_regs->TCR |= LPUSARTCORE_TCR_TOCNT_SWTRG_Msk; + lpusart->core_regs->IER = LPUSARTCORE_IER_AON_RX_OVERRUN_Msk | \ + LPUSARTCORE_IER_AON_RX_PARITY_Msk | \ + LPUSARTCORE_IER_AON_RX_FRMERR_Msk | \ + LPUSARTCORE_IER_RX_DATA_AVAIL_Msk | \ + LPUSARTCORE_IER_RX_TIMEOUT_Msk | \ + LPUSARTCORE_IER_RX_OVERRUN_Msk; + + RestoreIRQMask(mask); + +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_recv_1, P_DEBUG, "lpuart recv exit, iir: 0x%x, fcsr: 0x%x, tcr: 0x%x, tsr: 0x%x", lpusart->core_regs->IIR, lpusart->core_regs->FCSR, lpusart->core_regs->TCR, lpusart->core_regs->TSR); +#endif + } + else + { + while(lpusart->info->xfer.rx_cnt < lpusart->info->xfer.rx_num) + { + //wait unitl receive data is ready + while(lpusart->core_regs->FCSR & LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk); + //read data + lpusart->info->xfer.rx_buf[lpusart->info->xfer.rx_cnt++] = lpusart->core_regs->RBR; + } + lpusart->info->rx_status.rx_busy = 0; + } + } + + return ARM_DRIVER_OK; +} + +int32_t LPUSART_Transfer(const void *data_out, void *data_in, uint32_t num,LPUSART_RESOURCES *lpusart) +{ + //maybe used by command transfer + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +int32_t LPUSART_GetTxCount(LPUSART_RESOURCES *lpusart) +{ + uint32_t cnt; + if (!(lpusart->info->flags & LPUSART_FLAG_CONFIGURED)) + return 0; + if(lpusart->co_usart_dma_tx) + cnt = DMA_getChannelCount(lpusart->co_usart_dma_tx->instance, lpusart->co_usart_dma_tx->channel); + else + cnt = lpusart->info->xfer.tx_cnt; + return cnt; +} + +PLAT_PA_RAMCODE int32_t LPUSART_GetRxCount(LPUSART_RESOURCES *lpusart) +{ + if (!(lpusart->info->flags & LPUSART_FLAG_CONFIGURED)) + return 0; + return lpusart->info->xfer.rx_cnt; +} + +int32_t LPUSART_Control(uint32_t control, uint32_t arg, LPUSART_RESOURCES *lpusart) +{ + uint32_t val, mfcr, mask; + uint8_t aon_lcr = 0; + uint8_t lcr = lpusart->co_usart_regs->LCR; + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + aon_lcr = lpusart->aon_regs->LCR; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + // Control TX + case ARM_USART_CONTROL_TX: + return ARM_DRIVER_OK; + // Control RX + case ARM_USART_CONTROL_RX: + // Not recommend to use this feature + if ((lpusart->info->flags & LPUSART_FLAG_CONFIGURED) == 0U) + { + return ARM_DRIVER_ERROR; + } + + // What we can do now is just to suppress irqs since we have no solo control bit to disable RX for UART + + mask = SaveAndSetIRQMask(); + + if(lpusart->info->flags & LPUSART_FLAG_POWER_FULL) + { + if(arg == 0) + { + if(lpusart->co_usart_dma_rx) + { + lpusart->co_usart_regs->IER &= ~(USART_IER_RX_TIMEOUT_Msk | \ + USART_IER_RX_LINE_STATUS_Msk); + + lpusart->info->rx_status.rx_dma_triggered = 0; + + DMA_stopChannelNoWait(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel); + } + else if(lpusart->co_usart_irq) + { + lpusart->co_usart_regs->IER &= ~(USART_IER_RX_TIMEOUT_Msk | \ + USART_IER_RX_DATA_REQ_Msk | \ + USART_IER_RX_LINE_STATUS_Msk); + } + + lpusart->co_usart_regs->ICR = USART_ICR_RX_DATA_REQ_Msk | \ + USART_ICR_RX_TIMEOUT_Msk | \ + USART_ICR_RX_LINE_STATUS_Msk; + + } + else + { + // Not support now, call receive instead + } + + } + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + if(arg == 1) + { + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR1, LPUSART_AON_CR1_ENABLE); + } + else + { + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR1, 0); + } + } + + + lpusart->info->rx_status.rx_busy = 0; + + RestoreIRQMask(mask); + + return ARM_DRIVER_OK; + + + // Control break + case ARM_USART_CONTROL_BREAK: + return ARM_DRIVER_ERROR_UNSUPPORTED; + // Abort Send + case ARM_USART_ABORT_SEND: + return ARM_DRIVER_ERROR_UNSUPPORTED; + // Abort receive + case ARM_USART_ABORT_RECEIVE: + return ARM_DRIVER_ERROR_UNSUPPORTED; + // Abort transfer + case ARM_USART_ABORT_TRANSFER: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_USART_MODE_ASYNCHRONOUS: + break; + // Flush TX fifo + case ARM_USART_CONTROL_FLUSH_TX: + + if(lpusart->co_usart_regs->MFCR & USART_MFCR_AUTO_FLOW_CTS_EN_Msk) + { + while(((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0) && ((lpusart->co_usart_regs->MSR & USART_MSR_CTS_Msk) == USART_MSR_CTS_Msk)); + } + else + { + while((lpusart->co_usart_regs->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + } + return ARM_DRIVER_OK; + + case ARM_USART_CONTROL_PURGE_COMM: + if(lpusart->info->flags & LPUSART_FLAG_POWER_FULL) + { + mfcr = lpusart->co_usart_regs->MFCR; + lpusart->co_usart_regs->MFCR = 0; + // reconfigure FIFO Control register + val = USART_FCR_FIFO_EN_Msk | USART_FCR_RESET_RX_FIFO_Msk | USART_FCR_RESET_TX_FIFO_Msk; + + // rxfifo trigger level set as 16 bytes + val |= (2U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + + lpusart->co_usart_regs->FCR = val; + lpusart->co_usart_regs->MFCR = mfcr; + } + else if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + val = EIGEN_VAL2FLD(LPUSARTCORE_FCSR_RXFIFO_THRLD, LPUSART_RX_TRIG_LVL); + val |= LPUSARTCORE_FCSR_FLUSH_RXFIFO_Msk; + lpusart->core_regs->FCSR = val; + GPR_swReset(RST_LPUA); + lpusart->core_regs->IIR = LPUSARTCORE_IIR_CLR_Msk; + } + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_DATA_BITS_Msk) + { + case ARM_USART_DATA_BITS_5: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + aon_lcr &= ~LPUSARTAON_LCR_CHAR_LEN_Msk; + break; + case ARM_USART_DATA_BITS_6: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + lcr |= 1U; + aon_lcr &= ~LPUSARTAON_LCR_CHAR_LEN_Msk; + aon_lcr |= 1U; + break; + case ARM_USART_DATA_BITS_7: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + lcr |= 2U; + aon_lcr &= ~LPUSARTAON_LCR_CHAR_LEN_Msk; + aon_lcr |= 2U; + break; + case ARM_USART_DATA_BITS_8: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + lcr |= 3U; + aon_lcr &= ~LPUSARTAON_LCR_CHAR_LEN_Msk; + aon_lcr |= 3U; + break; + default: + return ARM_USART_ERROR_DATA_BITS; + } + + // LPUSART Parity + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + lcr &= ~USART_LCR_PARITY_EN_Msk; + aon_lcr &= ~LPUSARTAON_LCR_PARITY_EN_Msk; + break; + case ARM_USART_PARITY_EVEN: + lcr |= (USART_LCR_PARITY_EN_Msk | USART_LCR_EVEN_PARITY_Msk); + aon_lcr |= (LPUSARTAON_LCR_PARITY_EN_Msk | LPUSARTAON_LCR_EVEN_PARITY_Msk); + break; + case ARM_USART_PARITY_ODD: + lcr |= USART_LCR_PARITY_EN_Msk; + lcr &= ~USART_LCR_EVEN_PARITY_Msk; + aon_lcr |= LPUSARTAON_LCR_PARITY_EN_Msk; + aon_lcr &= ~LPUSARTAON_LCR_EVEN_PARITY_Msk; + break; + default: + return (ARM_USART_ERROR_PARITY); + } + + // LPUSART Stop bits + switch (control & ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + lcr &=~ USART_LCR_STOP_BIT_NUM_Msk; + break; + case ARM_USART_STOP_BITS_1_5: + if ((control & ARM_USART_DATA_BITS_Msk) == ARM_USART_DATA_BITS_5) + { + lcr |= USART_LCR_STOP_BIT_NUM_Msk; + break; + } + else + return ARM_USART_ERROR_STOP_BITS; + case ARM_USART_STOP_BITS_2: + lcr |= USART_LCR_STOP_BIT_NUM_Msk; + break; + default: + return ARM_USART_ERROR_STOP_BITS; + } + + // LPUSART Flow Control + switch (control & ARM_USART_FLOW_CONTROL_Msk) + { + case ARM_USART_FLOW_CONTROL_NONE: + lpusart->co_usart_regs->MFCR &= ~(USART_MFCR_AUTO_FLOW_RTS_EN_Msk | USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + case ARM_USART_FLOW_CONTROL_RTS: + lpusart->co_usart_regs->MCR |= USART_MCR_RTS_Msk; //activate rts, put rts pin to low level + lpusart->co_usart_regs->MFCR &= ~(USART_MFCR_AUTO_FLOW_RTS_EN_Msk | USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + case ARM_USART_FLOW_CONTROL_CTS: + lpusart->co_usart_regs->MFCR |= (USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + case ARM_USART_FLOW_CONTROL_RTS_CTS: + lpusart->co_usart_regs->MCR |= USART_MCR_RTS_Msk; //activate rts, put rts pin to low level + lpusart->co_usart_regs->MFCR |= (USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + } + // LPUSART Baudrate + if(ARM_DRIVER_OK != LPUSART_SetBaudrate(arg, lpusart)) + { + return ARM_USART_ERROR_BAUDRATE; + } + + // Configuration is OK - frame code is valid + lpusart->info->frame_code = control; + + lpusart->co_usart_regs->LCR = lcr; + + if(lpusart->info->flags & LPUSART_FLAG_POWER_LOW) + { + + if((lpusart->core_regs->FCSR & (LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk | LPUSARTCORE_FCSR_AON_RX_BUSY_Msk | LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk)) == (LPUSARTCORE_FCSR_RXFIFO_EMPTY_Msk | LPUSARTCORE_FCSR_AON_RXFIFO_EMPTY_Msk)) + { + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR0, LPUSARTAON_CR0_RX_ENABLE_Msk | LPUSARTAON_CR0_CLK_ENABLE_Msk); + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->LCR, aon_lcr); + //LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR1, LPUSARTAON_CR1_ENABLE_Msk | LPUSARTAON_CR1_ACG_EN_Msk | LPUSARTAON_CR1_AUTO_ADJ_Msk); + LPUSART_AON_REGISTER_WRITE(lpusart->aon_regs->CR1, LPUSART_AON_CR1_ENABLE); + } + LPUSART_ClearStopFlag(); + } + + // lpusart enable + lpusart->co_usart_regs->MFCR |= USART_MFCR_UART_EN_Msk; + + lpusart->info->flags |= LPUSART_FLAG_CONFIGURED; + return ARM_DRIVER_OK; +} + +ARM_USART_STATUS LPUSART_GetStatus(LPUSART_RESOURCES *lpusart) +{ + ARM_USART_STATUS status; + + status.tx_busy = lpusart->info->xfer.send_active; + status.rx_busy = lpusart->info->rx_status.rx_busy; + status.tx_underflow = 0; + status.rx_overflow = lpusart->info->rx_status.rx_overflow; + status.rx_break = lpusart->info->rx_status.rx_break; + status.rx_framing_error = lpusart->info->rx_status.rx_framing_error; + status.rx_parity_error = lpusart->info->rx_status.rx_parity_error; + status.is_send_block = (lpusart->co_usart_dma_tx == NULL); + return status; +} + +int32_t LPUSART_SetModemControl(ARM_USART_MODEM_CONTROL control, LPUSART_RESOURCES *lpusart) +{ + if((lpusart->info->flags & LPUSART_FLAG_CONFIGURED) == 0U) + { + // USART is not configured + return ARM_DRIVER_ERROR; + } + + if(lpusart->info->frame_code & ARM_USART_FLOW_CONTROL_RTS) + { + if(control == ARM_USART_RTS_CLEAR) //Deactivate RTS, put rts pin to high level + { + lpusart->co_usart_regs->MCR &= ~USART_MCR_RTS_Msk; + } + + if(control == ARM_USART_RTS_SET) //Activate RTS, put rts pin to low level + { + lpusart->co_usart_regs->MCR |= USART_MCR_RTS_Msk; + } + + } + + if(control == ARM_USART_DTR_CLEAR) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + if(control == ARM_USART_DTR_SET) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; + +} + +ARM_USART_MODEM_STATUS LPUSART_GetModemStatus(LPUSART_RESOURCES *lpusart) +{ + ARM_USART_MODEM_STATUS status = {0}; + + if(lpusart->info->flags & LPUSART_FLAG_CONFIGURED) + { + status.cts = EIGEN_FLD2VAL(USART_MSR_CTS, lpusart->co_usart_regs->MSR); + } + + return status; +} + +void LPUSART_WakeupIntHandler(void) +{ + slpManExtIntPreProcess(LpuartWakeup_IRQn); + + //extern void AonRegAPClrWIC(void); + // WIC clear + //AonRegAPClrWIC(); + *(uint32_t*) 0x4d020140 = 1; + NVIC_DisableIRQ(LpuartWakeup_IRQn); + +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_wakeup_irq_1, P_SIG, "LPUART->IIR:0x%x, LPUART->FCSR:0x%x", LPUSART_CORE->IIR, LPUSART_CORE->FCSR); +#endif +} + +PLAT_PA_RAMCODE void LPUSART_IRQHandler(LPUSART_RESOURCES *lpusart) +{ + uint32_t i, dma_rx_channel; + uint32_t event = 0; + uint32_t iir_reg; + uint32_t current_cnt, total_cnt, left_to_recv, bytes_in_fifo; + +#define LPUSARTAON_INT_MASK (LPUSARTCORE_IIR_AON_RX_OVERRUN_Msk | LPUSARTCORE_IIR_AON_RX_PARITY_Msk | LPUSARTCORE_IIR_AON_RX_FRMERR_Msk) +#define LPUSARTCORE_INT_MASK (LPUSARTCORE_IIR_RX_DATA_AVAIL_Msk | LPUSARTCORE_IIR_RX_TIMEOUT_Msk | LPUSARTCORE_IIR_RX_OVERRUN_Msk) + + LPUSART_INFO *info = lpusart->info; + + // Check interrupt source +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_irq_0, P_DEBUG, "Enter lpuart irq, iir: 0x%x, fcsr: 0x%x, tcr: 0x%x, tsr: 0x%x, rx_cnt:%d, ", lpusart->core_regs->IIR, lpusart->core_regs->FCSR, lpusart->core_regs->TCR, lpusart->core_regs->TSR, info->xfer.rx_cnt); +#endif + + iir_reg = lpusart->core_regs->IIR; + + if(iir_reg & LPUSARTAON_INT_MASK) + { + if(iir_reg & LPUSARTCORE_IIR_AON_RX_OVERRUN_Msk) + { + info->rx_status.rx_overflow = 1U; + info->rx_status.aon_rx_overflow = 1U; + event |= ARM_USART_EVENT_RX_OVERFLOW; + } + + if(iir_reg & LPUSARTCORE_IIR_RX_OVERRUN_Msk) + { + info->rx_status.rx_overflow = 1U; + event |= ARM_USART_EVENT_RX_OVERFLOW; + } + + // Parity error + if (iir_reg & LPUSARTCORE_IIR_AON_RX_PARITY_Msk) + { + info->rx_status.rx_parity_error= 1U; + event |= ARM_USART_EVENT_RX_PARITY_ERROR; + } + + // Framing error + if (iir_reg & LPUSARTCORE_IIR_AON_RX_FRMERR_Msk) + { + info->rx_status.rx_framing_error= 1U; + event |= ARM_USART_EVENT_RX_FRAMING_ERROR; + } + + info->rx_status.rx_busy = 0; +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(0, 1); +#endif + } + else if(iir_reg & LPUSARTCORE_INT_MASK) + { + // clear interrupt flags + lpusart->core_regs->IIR = LPUSARTCORE_IIR_CLR_Msk; + + if(iir_reg & LPUSARTCORE_IIR_RX_OVERRUN_Msk) + { + info->rx_status.rx_overflow = 1U; + event |= ARM_USART_EVENT_RX_OVERFLOW; + } + else + { + if(iir_reg & LPUSARTCORE_IIR_RX_DATA_AVAIL_Msk) + { + // need to retrigger timeout counter if both interrupts have reached or timeout is approaching + if((lpusart->core_regs->TSR & LPUSARTCORE_TSR_TOCNT_Msk) > ((lpusart->core_regs->TCR & LPUSARTCORE_TCR_TIMEOUT_THRLD_Msk) - 20000)) + { + lpusart->core_regs->TCR |= LPUSARTCORE_TCR_TOCNT_SWTRG_Msk; // timeout interrupt is not cleared by this operation + lpusart->core_regs->IIR = LPUSARTCORE_IIR_CLR_Msk; + } + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(0, 1); +#endif + info->rx_status.rx_busy = 1U; + + current_cnt = info->xfer.rx_cnt; + total_cnt = info->xfer.rx_num; + + left_to_recv = total_cnt - current_cnt; + + bytes_in_fifo = EIGEN_FLD2VAL(LPUSARTCORE_FCSR_RXFIFO_NUM, lpusart->core_regs->FCSR); + + // leave at least one byte in fifo to trigger timeout interrupt + i = bytes_in_fifo - 1; + + if(i == 0) + i = 1; + + i = MIN(i, left_to_recv); + + // DMA mode + if(lpusart->dma_rx) + { + // Let CPU transfer last chunk and all data when trigger level is set to be 1 + if ((left_to_recv <= (bytes_in_fifo - 1)) || (LPUSART_RX_TRIG_LVL == 1)) + { +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_irq_3, P_DEBUG, "CPU will transfer: %d", i); +#endif + while(i--) + { + info->xfer.rx_buf[current_cnt++] = lpusart->core_regs->RBR; + } + + } + else + { + dma_rx_channel = lpusart->dma_rx->channel; +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_irq_2, P_DEBUG, "DMA will transfer: %d", i); +#endif + lpusart->dma_rx->descriptor->TAR = (uint32_t)(info->xfer.rx_buf + current_cnt); + lpusart->dma_rx->descriptor->CMDR = DMA_setDescriptorTransferLen(lpusart->dma_rx->descriptor->CMDR, i); + + // load descriptor and start DMA transfer + DMA_loadChannelDescriptorAndRun(lpusart->dma_rx->instance, dma_rx_channel, lpusart->dma_rx->descriptor); + + current_cnt += i; + info->rx_status.rx_dma_triggered = 1; + } + + } + // IRQ mode + else + { + while(i--) + { + info->xfer.rx_buf[current_cnt++] = lpusart->core_regs->RBR; + } + // clear interrupt flags + lpusart->core_regs->IIR = LPUSARTCORE_IIR_CLR_Msk; + + } + + info->xfer.rx_cnt = current_cnt; + + if(current_cnt == total_cnt) + { + // Clear RX busy flag and set receive transfer complete event + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + + //Disable interrupt + lpusart->core_regs->IER = 0; + + info->rx_status.rx_busy = 0; + } + + } + else if(iir_reg & LPUSARTCORE_IIR_RX_TIMEOUT_Msk) + { + bytes_in_fifo = EIGEN_FLD2VAL(LPUSARTCORE_FCSR_RXFIFO_NUM, lpusart->core_regs->FCSR); + + if((bytes_in_fifo > 0) && (lpusart->core_regs->TSR & LPUSARTCORE_TSR_TOCNT_REACH_Msk)) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(0, 1); +#endif + info->rx_status.rx_busy = 1U; + + info->rx_status.rx_dma_triggered = 0; + + current_cnt = info->xfer.rx_cnt; + + total_cnt = info->xfer.rx_num; + + left_to_recv = total_cnt - current_cnt; + + i = MIN(bytes_in_fifo, left_to_recv); + +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, lpuart_irq_4, P_DEBUG, "Time out, CPU will transfer: %d", i); +#endif + + while(i--) + { + info->xfer.rx_buf[current_cnt++] = lpusart->core_regs->RBR; + } + + info->xfer.rx_cnt = current_cnt; + + // Check if required amount of data is received + if (current_cnt == total_cnt) + { + // Clear RX busy flag and set receive transfer complete event + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + + //Disable interrupt + lpusart->core_regs->IER = 0; + + } + else + { + event |= ARM_USART_EVENT_RX_TIMEOUT; + } + + info->rx_status.rx_busy = 0; + } + + } + } + } + + if ((info->cb_event != NULL) && (event != 0)) + { + info->cb_event (event); + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(0, 1); +#endif + + } +} + + +PLAT_PA_RAMCODE void CO_USART_IRQHandler(LPUSART_RESOURCES *lpusart) +{ + uint32_t i; + uint32_t event = 0; + uint32_t lsr_reg, isr_reg; + uint32_t current_cnt, total_cnt, left_to_recv, bytes_in_fifo; + + LPUSART_INFO *info = lpusart->info; + + // Check interrupt source + isr_reg = lpusart->co_usart_regs->ISR; + lpusart->co_usart_regs->ICR = isr_reg; + lpusart->co_usart_regs->ICR = 0; + +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CO_USART_IRQHandler_0, P_DEBUG, "Enter co_uart irq, isr: 0x%x, fcnr: 0x%x, rx_cnt:%d", isr_reg, lpusart->co_usart_regs->FCNR, info->xfer.rx_cnt); +#endif + + + if((isr_reg & USART_ISR_RX_LINE_STATUS_Msk) == USART_ISR_RX_LINE_STATUS_Msk) + { + lsr_reg = lpusart->co_usart_regs->LSR; + + if (lsr_reg & USART_LSR_RX_OVERRUN_ERROR_Msk) + { + info->rx_status.rx_overflow = 1U; + event |= ARM_USART_EVENT_RX_OVERFLOW; + } + + // Parity error + if (lsr_reg & USART_LSR_RX_PARITY_ERROR_Msk) + { + info->rx_status.rx_parity_error= 1U; + event |= ARM_USART_EVENT_RX_PARITY_ERROR; + } + // Break detected + if (lsr_reg & USART_LSR_RX_BREAK_Msk) + { + info->rx_status.rx_break= 1U; + event |= ARM_USART_EVENT_RX_BREAK; + } + // Framing error + if (lsr_reg & USART_LSR_RX_FRAME_ERROR_Msk) + { + info->rx_status.rx_framing_error= 1U; + event |= ARM_USART_EVENT_RX_FRAMING_ERROR; + } + + info->rx_status.rx_busy = 0; +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(0, 1); +#endif + + } + else if((isr_reg & USART_ISR_RX_TIMEOUT_Msk) == USART_ISR_RX_TIMEOUT_Msk) + { + { + // refer to receive API for this check + if(lpusart->co_usart_regs->FCNR >> USART_FCNR_RX_FIFO_NUM_Pos) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(0, 1); +#endif + info->rx_status.rx_busy = 1U; + + current_cnt = info->xfer.rx_cnt; + + if(lpusart->co_usart_dma_rx) + { + if(info->rx_status.rx_dma_triggered) + { + // Sync with undergoing DMA transfer, wait until DMA burst transfer(8 bytes) done and update current_cnt + do + { + current_cnt = DMA_getChannelCurrentTargetAddress(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, true) - (uint32_t)info->xfer.rx_buf; +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CO_USART_IRQHandler_1, P_DEBUG, "dma transfer done, cnt:%d", current_cnt); +#endif + } while(((current_cnt - info->xfer.rx_cnt) & (CO_USART_DMA_BURST_SIZE - 1)) != 0); + + info->rx_status.rx_dma_triggered = 0; + + } + /* + No matter DMA transfer is started or not(left recv buffer space is not enough), + now we can stop DMA saftely for next transfer and handle tailing bytes in FIFO + */ + DMA_stopChannelNoWait(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel); + } + + total_cnt = info->xfer.rx_num; + + bytes_in_fifo = lpusart->co_usart_regs->FCNR >> USART_FCNR_RX_FIFO_NUM_Pos; + + left_to_recv = total_cnt - current_cnt; + + i = MIN(bytes_in_fifo, left_to_recv); + + // if still have space to recv + if(left_to_recv > 0) + { + while(i--) + { + info->xfer.rx_buf[current_cnt++] = lpusart->co_usart_regs->RBR; + } + } + + info->xfer.rx_cnt = current_cnt; + + // Check if required amount of data is received + if (current_cnt == total_cnt) + { + // Clear RX busy flag and set receive transfer complete event + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + + //Disable RDA interrupt + lpusart->co_usart_regs->IER &= ~(USART_IER_RX_DATA_REQ_Msk | USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + + } + else + { + event |= ARM_USART_EVENT_RX_TIMEOUT; + + if(lpusart->co_usart_dma_rx) + { + // Prepare for next recv + left_to_recv = total_cnt - info->xfer.rx_cnt; + + CO_USART_DmaUpdateRxConfig(lpusart, (uint32_t)info->xfer.rx_buf + info->xfer.rx_cnt, left_to_recv); + + // load descriptor and start DMA transfer + DMA_loadChannelDescriptorAndRun(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, &lpusart->co_usart_dma_rx->descriptor[0]); + + } + + } + + info->rx_status.rx_busy = 0; + } + } + } + else if((isr_reg & USART_ISR_RX_DATA_REQ_Msk) == USART_ISR_RX_DATA_REQ_Msk) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(0, 1); +#endif + info->rx_status.rx_busy = 1U; + + current_cnt = info->xfer.rx_cnt; + total_cnt = info->xfer.rx_num; + + left_to_recv = total_cnt - current_cnt; + + bytes_in_fifo = lpusart->co_usart_regs->FCNR >> USART_FCNR_RX_FIFO_NUM_Pos; + + // leave at least one byte in fifo to trigger timeout interrupt + i = bytes_in_fifo - 1; + + if(i == 0) + i = 1; + + i = MIN(i, left_to_recv); + + while(i--) + { + info->xfer.rx_buf[current_cnt++] = lpusart->co_usart_regs->RBR; + } + + info->xfer.rx_cnt = current_cnt; + + if(current_cnt == total_cnt) + { + // Clear RX busy flag and set receive transfer complete event + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + + //Disable RDA interrupt + lpusart->co_usart_regs->IER &= ~(USART_IER_RX_DATA_REQ_Msk | USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + + info->rx_status.rx_busy = 0; + } + } + + if(((isr_reg & USART_ISR_TX_DATA_REQ_Msk) == USART_ISR_TX_DATA_REQ_Msk) || \ + ((lpusart->co_usart_regs->IER & USART_IER_TX_DATA_REQ_Msk) && ((lpusart->co_usart_regs->FCNR & USART_FCNR_TX_FIFO_NUM_Msk) == 0))) + { + info->xfer.tx_cnt = info->xfer.tx_num; + info->xfer.send_active = 0U; + event |= ARM_USART_EVENT_SEND_COMPLETE; + lpusart->co_usart_regs->IER &= ~USART_IER_TX_DATA_REQ_Msk; + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(1, 0); +#endif + } + + if ((info->cb_event != NULL) && (event != 0)) + { + info->cb_event (event); + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(0, 1); +#endif + + } +} + +/** + \fn void LPUSART_DmaTxEvent(uint32_t event, LPUSART_RESOURCES *usart) + \brief LPUSART DMA Tx Event handler. + \param[in] event DMA Tx Event + \param[in] usart Pointer to LPUSART resources +*/ +void LPUSART_DmaTxEvent(uint32_t event, LPUSART_RESOURCES *lpusart) +{ + switch (event) + { + case DMA_EVENT_END: + // TXFIFO may still have data not sent out + lpusart->co_usart_regs->IER |= USART_IER_TX_DATA_REQ_Msk; + lpusart->co_usart_regs->THR = lpusart->info->xfer.tx_buf[lpusart->info->xfer.tx_num-1]; + + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + +void CO_USART_DmaRxEvent(uint32_t event, LPUSART_RESOURCES *lpusart) +{ + + uint32_t dmaCurrentTargetAddress = DMA_getChannelCurrentTargetAddress(lpusart->co_usart_dma_rx->instance, lpusart->co_usart_dma_rx->channel, false); + + switch (event) + { + case DMA_EVENT_END: + +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CO_USART_DmaRxEvent_0, P_DEBUG, "uart dma rx event, fcnr:%x, cnt:%d", lpusart->co_usart_regs->FCNR, dmaCurrentTargetAddress - (uint32_t)lpusart->info->xfer.rx_buf); +#endif + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(0, 1); +#endif + lpusart->info->rx_status.rx_busy = 1U; + lpusart->info->rx_status.rx_dma_triggered = 1; + + if(dmaCurrentTargetAddress == ( (uint32_t)lpusart->info->xfer.rx_buf + lpusart->info->xfer.rx_num)) + { +#if LPUSART_DRIVER_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, CO_USART_DmaRxEvent_1, P_DEBUG, "uart dma rx complete"); +#endif + lpusart->info->xfer.rx_cnt = lpusart->info->xfer.rx_num; + + //Disable all recv interrupt + lpusart->co_usart_regs->IER &= ~(USART_IER_RX_DATA_REQ_Msk | USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + lpusart->info->rx_status.rx_busy = 0; + lpusart->info->rx_status.rx_dma_triggered = 0; + + if(lpusart->info->cb_event) + { + lpusart->info->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(0, 1); +#endif + } + + break; + case DMA_EVENT_ERROR: + default: + break; + } +} +#if (RTE_UART1) +static int32_t LPUSART1_Initialize (ARM_USART_SignalEvent_t cb_event) { return LPUSART_Initialize(cb_event, &LPUSART1_Resources); } +static int32_t LPUSART1_Uninitialize (void) { return LPUSART_Uninitialize(&LPUSART1_Resources); } +static int32_t LPUSART1_PowerControl (ARM_POWER_STATE state) { return LPUSART_PowerControl(state, &LPUSART1_Resources); } +static int32_t LPUSART1_Send (const void *data, uint32_t num) { return LPUSART_Send(data, num, &LPUSART1_Resources); } +static int32_t LPUSART1_Receive (void *data, uint32_t num) { return LPUSART_Receive(data, num, &LPUSART1_Resources); } +static int32_t LPUSART1_Transfer (const void *data_out, void *data_in, uint32_t num) { return LPUSART_Transfer(data_out, data_in, num, &LPUSART1_Resources); } +static int32_t LPUSART1_SendPolling (const void *data, uint32_t num) { return LPUSART_SendPolling (data, num, &LPUSART1_Resources); } +static uint32_t LPUSART1_GetTxCount (void) { return LPUSART_GetTxCount(&LPUSART1_Resources); } +PLAT_PA_RAMCODE static uint32_t LPUSART1_GetRxCount (void) { return LPUSART_GetRxCount(&LPUSART1_Resources); } +static uint32_t LPUSART1_GetBaudRate (void) { return LPUSART_GetBaudRate(&LPUSART1_Resources); } +static int32_t LPUSART1_Control (uint32_t control, uint32_t arg) { return LPUSART_Control(control, arg, &LPUSART1_Resources); } +static ARM_USART_STATUS LPUSART1_GetStatus (void) { return LPUSART_GetStatus(&LPUSART1_Resources); } +static int32_t LPUSART1_SetModemControl (ARM_USART_MODEM_CONTROL control) { return LPUSART_SetModemControl(control, &LPUSART1_Resources); } +static ARM_USART_MODEM_STATUS LPUSART1_GetModemStatus (void) { return LPUSART_GetModemStatus(&LPUSART1_Resources); } +PLAT_PA_RAMCODE void LPUSART1_IRQHandler (void) { LPUSART_IRQHandler(&LPUSART1_Resources); } +PLAT_PA_RAMCODE void CO_USART1_IRQHandler (void) { CO_USART_IRQHandler(&LPUSART1_Resources); } +#if (RTE_UART1_TX_IO_MODE == DMA_MODE) +void LPUSART1_DmaTxEvent(uint32_t event) { LPUSART_DmaTxEvent(event, &LPUSART1_Resources);} +#endif +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) +void CO_USART1_DmaRxEvent(uint32_t event) { CO_USART_DmaRxEvent(event, &LPUSART1_Resources);}; +#endif + +ARM_DRIVER_USART Driver_LPUSART1 = { + LPUSART_GetVersion, + LPUSART_GetCapabilities, + LPUSART1_Initialize, + LPUSART1_Uninitialize, + LPUSART1_PowerControl, + LPUSART1_Send, + LPUSART1_Receive, + LPUSART1_Transfer, + LPUSART1_GetTxCount, + LPUSART1_GetRxCount, + LPUSART1_Control, + LPUSART1_GetStatus, + LPUSART1_SetModemControl, + LPUSART1_GetModemStatus, + LPUSART1_GetBaudRate, + LPUSART1_SendPolling +}; + +#endif + +//#pragma pop + diff --git a/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_lpusart_stub.c b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_lpusart_stub.c new file mode 100644 index 0000000..4c03d0b --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_lpusart_stub.c @@ -0,0 +1,15 @@ +#include +bool LPUSART_IsRxActive(void) +{ + return 0; +} + +void LPUSART_ClearStopFlag(void) +{ + +} + +void LPUSART_SetStopFlag(void) +{ + +} \ No newline at end of file diff --git a/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_spi.c b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_spi.c new file mode 100644 index 0000000..ef15381 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_spi.c @@ -0,0 +1,1694 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 12. July 2018 + * $Revision: V2.0 + * + * Driver: Driver_SPI0, Driver_SPI1, Driver_SPI2 + * Configured: via RTE_Device.h configuration file + * Project: SPI (SSP used for SPI) Driver for AirM2M EC618 + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value SPI Interface + * --------------------- ----- ------------- + * Connect to hardware via Driver_SPI# = 0 use SPI0 (SSP0) + * Connect to hardware via Driver_SPI# = 1 use SPI1 (SSP1) + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.0 + * - Initial CMSIS Driver API V2.0 release + */ + +#include "bsp_spi.h" +#include "slpman.h" + +#ifndef DISTANCE +#define DISTANCE(a,b) ((a>b)?(a-b):(b-a)) +#endif + +#define SPI_RX_FIFO_TRIG_LVL (8) + +#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) // driver version + +#if ((!RTE_SPI0) && (!RTE_SPI1)) +#error "spi not enabled in RTE_Device.h!" +#endif + +#ifdef PM_FEATURE_ENABLE + +/** \brief Internal used data structure */ +typedef struct _spi_database +{ + bool isInited; /**< Whether spi has been initialized */ + struct + { + uint32_t CR0; /**< Control Register 0 */ + uint32_t CR1; /**< Control Register 1 */ + uint32_t CPSR; /**< Clock Prescale Register */ + uint32_t IMSC; /**< Interrupt Mask Set or Clear Register */ + uint32_t DMACR; /**< DMA Control Register */ + } backup_registers; /**< Backup registers for low power restore */ +} spi_database_t; + +static spi_database_t g_spiDataBase[SPI_INSTANCE_NUM] = {0}; + +static SPI_TypeDef* const g_spiBases[SPI_INSTANCE_NUM] = {SPI0, SPI1}; +#endif + +static const ClockId_e g_spiClocks[SPI_INSTANCE_NUM*2] = {PCLK_SPI0, FCLK_SPI0, PCLK_SPI1, FCLK_SPI1}; + +static const ClockResetVector_t g_spiResetVectors[] = {SPI0_RESET_VECTOR, SPI1_RESET_VECTOR}; + + +#ifdef PM_FEATURE_ENABLE +/** + \brief spi initialization counter, for lower power callback register/de-register + */ +static uint32_t g_spiInitCounter = 0; + +/** + \brief Bitmap of SPI working status, each instance is assigned 2 bits representing tx and rx status, + when all SPI instances are not working, we can vote to enter to low power state. + */ + +static uint32_t g_spiWorkingStatus = 0; + + +/** + \fn static void SPI_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, SPI hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void SPI_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < SPI_INSTANCE_NUM; i++) + { + if(g_spiDataBase[i].isInited == true) + { + g_spiDataBase[i].backup_registers.CR0 = g_spiBases[i]->CR0; + g_spiDataBase[i].backup_registers.CR1 = g_spiBases[i]->CR1; + g_spiDataBase[i].backup_registers.CPSR = g_spiBases[i]->CPSR; + g_spiDataBase[i].backup_registers.IMSC = g_spiBases[i]->IMSC; + g_spiDataBase[i].backup_registers.DMACR = g_spiBases[i]->DMACR; + } + } + break; + default: + break; + } + +} + +/** + \fn static void SPI_ExitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, SPI hareware is repowered, we restore user's configurations + by aidding of the stored registers. + + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + + */ +static void SPI_ExitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < SPI_INSTANCE_NUM; i++) + { + if(g_spiDataBase[i].isInited == true) + { + GPR_clockEnable(g_spiClocks[2*i]); + GPR_clockEnable(g_spiClocks[2*i+1]); + + g_spiBases[i]->CR0 = g_spiDataBase[i].backup_registers.CR0; + g_spiBases[i]->CPSR = g_spiDataBase[i].backup_registers.CPSR; + g_spiBases[i]->IMSC = g_spiDataBase[i].backup_registers.IMSC; + g_spiBases[i]->DMACR = g_spiDataBase[i].backup_registers.DMACR; + g_spiBases[i]->CR1 = g_spiDataBase[i].backup_registers.CR1; + } + } + break; + + default: + break; + } + +} + +#define LOCK_SLEEP(instance) do \ + { \ + g_spiWorkingStatus |= (1U << instance); \ + slpManDrvVoteSleep(SLP_VOTE_SPI, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define CHECK_TO_UNLOCK_SLEEP(instance) do \ + { \ + g_spiWorkingStatus &= ~(1U << instance); \ + if(g_spiWorkingStatus == 0) \ + slpManDrvVoteSleep(SLP_VOTE_SPI, SLP_SLP1_STATE); \ + } \ + while(0) + +#endif + +// Driver Version +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_SPI_API_VERSION, + ARM_SPI_DRV_VERSION +}; + +// Driver Capabilities +static const ARM_SPI_CAPABILITIES DriverCapabilities = { + 0, // Simplex Mode (Master and Slave) + 1, // TI Synchronous Serial Interface + 1, // Microwire Interface + 0 // Signal Mode Fault event +}; + +void SPI0_IRQHandler(void); +void SPI1_IRQHandler(void); + +#if (RTE_SPI0) + +static SPI_INFO SPI0_Info = {0}; +static PIN SPI0_pin_sclk = {RTE_SPI0_SCLK_BIT, RTE_SPI0_SCLK_FUNC}; +static PIN SPI0_pin_ssn = {RTE_SPI0_SSN_BIT, RTE_SPI0_SSN_FUNC}; +static PIN SPI0_pin_mosi = {RTE_SPI0_MOSI_BIT, RTE_SPI0_MOSI_FUNC}; +static PIN SPI0_pin_miso = {RTE_SPI0_MISO_BIT, RTE_SPI0_MISO_FUNC}; + + +#if (RTE_SPI0_IO_MODE == DMA_MODE) +void SPI0_DmaTxEvent(uint32_t event); +void SPI0_DmaRxEvent(uint32_t event); + +static SPI_DMA SPI0_DMA = { + DMA_INSTANCE_MP, + -1, + RTE_SPI0_DMA_TX_REQID, + SPI0_DmaTxEvent, + DMA_INSTANCE_MP, + -1, + RTE_SPI0_DMA_RX_REQID, + SPI0_DmaRxEvent, + }; +#endif + +#if (RTE_SPI0_IO_MODE == IRQ_MODE) || (RTE_SPI0_IO_MODE == DMA_MODE) + +static SPI_IRQ SPI0_IRQ = { + PXIC0_SSP0_IRQn, + SPI0_IRQHandler + }; +#endif + +static SPI_RESOURCES SPI0_Resources = { + SPI0, + { + &SPI0_pin_sclk, + &SPI0_pin_ssn, + &SPI0_pin_mosi, + &SPI0_pin_miso, + }, +#if (RTE_SPI0_IO_MODE == DMA_MODE) + &SPI0_DMA, +#else + NULL, +#endif + +#if (RTE_SPI0_IO_MODE == IRQ_MODE) || (RTE_SPI0_IO_MODE == DMA_MODE) + &SPI0_IRQ, +#else + NULL, +#endif + &SPI0_Info +}; +#endif + +#if (RTE_SPI1) + +static SPI_INFO SPI1_Info = {0}; +static const PIN SPI1_pin_sclk = {RTE_SPI1_SCLK_BIT, RTE_SPI1_SCLK_FUNC}; +static const PIN SPI1_pin_ssn = {RTE_SPI1_SSN_BIT, RTE_SPI1_SSN_FUNC}; +static const PIN SPI1_pin_mosi = {RTE_SPI1_MOSI_BIT, RTE_SPI1_MOSI_FUNC}; +static const PIN SPI1_pin_miso = {RTE_SPI1_MISO_BIT, RTE_SPI1_MISO_FUNC}; + +#if (RTE_SPI1_IO_MODE == DMA_MODE) +void SPI1_DmaTxEvent(uint32_t event); +void SPI1_DmaRxEvent(uint32_t event); + +static SPI_DMA SPI1_DMA = { + DMA_INSTANCE_MP, + -1, + RTE_SPI1_DMA_TX_REQID, + SPI1_DmaTxEvent, + DMA_INSTANCE_MP, + -1, + RTE_SPI1_DMA_RX_REQID, + SPI1_DmaRxEvent, + }; +#endif + +#if (RTE_SPI1_IO_MODE == IRQ_MODE) || (RTE_SPI1_IO_MODE == DMA_MODE) + +static SPI_IRQ SPI1_IRQ = { + PXIC0_SSP1_IRQn, + SPI1_IRQHandler + }; +#endif + +static SPI_RESOURCES SPI1_Resources = { + SPI1, + { + &SPI1_pin_sclk, + &SPI1_pin_ssn, + &SPI1_pin_mosi, + &SPI1_pin_miso, + }, +#if (RTE_SPI1_IO_MODE == DMA_MODE) + &SPI1_DMA, +#else + NULL, +#endif + +#if (RTE_SPI1_IO_MODE == IRQ_MODE) || (RTE_SPI1_IO_MODE == DMA_MODE) + &SPI1_IRQ, +#else + NULL, +#endif + &SPI1_Info +}; + +#endif + +static DmaTransferConfig_t g_dmaTxConfig = { NULL, NULL, + DMA_FLOW_CONTROL_TARGET, DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_ONE_BYTE, + DMA_BURST_8_BYTES, 0 + }; + +static DmaTransferConfig_t g_dmaRxConfig = { NULL, NULL, + DMA_FLOW_CONTROL_SOURCE, DMA_ADDRESS_INCREMENT_TARGET, + DMA_DATA_WIDTH_ONE_BYTE, + DMA_BURST_4_BYTES, 0 + }; + +// Local Function + +/** + \fn static uint32_t SPI_GetInstanceNumber(SPI_RESOURCES *spi) + \brief Get instance number + \param[in] spi Pointer to SPI resources + \returns instance number +*/ +static uint32_t SPI_GetInstanceNumber(SPI_RESOURCES *spi) +{ + return ((uint32_t)spi->reg - (uint32_t)SPI0) >> 12U; +} + +/** + \fn ARM_DRIVER_VERSION SPI_GetVersion(void) + \brief Get SSP driver version. + \return \ref ARM_DRV_VERSION +*/ +ARM_DRIVER_VERSION SPI_GetVersion(void) +{ + return DriverVersion; +} + +/** + \fn ARM_SPI_CAPABILITIES SPI_GetCapabilities(void) + \brief Get driver capabilities. + \return \ref ARM_SPI_CAPABILITIES +*/ +ARM_SPI_CAPABILITIES SPI_GetCapabilities(void) +{ + return DriverCapabilities; +} + +/** + \fn static int32_t SPI_SetBusSpeed(uint32_t bps, SPI_RESOURCES *spi) + \brief Set bus speed + \param[in] bps bus speed to set + \param[in] spi Pointer to SPI resources + \return \ref execution_status +*/ +static int32_t SPI_SetBusSpeed(uint32_t bps, SPI_RESOURCES *spi) +{ + uint32_t instance, spi_clock = 0; + + uint32_t cpsr, scr, best_cpsr = 2U, best_scr = 1U; + uint32_t div = 0, best_div = 2U; + + if(bps == 0) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + instance = SPI_GetInstanceNumber(spi); + + spi_clock = GPR_getClockFreq(g_spiClocks[instance*2+1]); + + // bps = clock_in / div where div = cpsr * scr + + // round to nearest even number + div = spi_clock / bps; + div += (div & 1U); + + if (div == 0) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + /* divider range [2,512] = 2*[1,256] (cpsr = 2) + * this range convers most cases, for 51.2M input clock, + * the minimum generated bps can reach 51.2M/512 = 100K + */ + else if (div <= 512U) + { + best_cpsr = 2U; + best_scr = div >> 1U; + } + // divider range [512, 254*256] + else + { + // for each cpsr, we can search scr from 1 to 256, however we can narrow down the range for symmetry nature + for (cpsr = 4U; cpsr <= 254U; cpsr += 2U) + { + uint32_t scr_mid; + // search upper triangular matrix + uint32_t scr_left = cpsr >> 1U; + uint32_t scr_right = 256U; + + // scr locates outside of current range [cpsr >> 1, 256] + if (div >= (cpsr << 8U)) + { + scr = 256U; + } + // scr locates in [cpsr >> 1, 256], then binary search + else + { + while (scr_left <= scr_right) + { + scr_mid = (scr_right + scr_left) >> 1U; + if (div > cpsr * scr_mid) + scr_left = scr_mid + 1U; + else + scr_right = scr_mid - 1U; + } + if (cpsr * scr_left - div < div - cpsr * scr_right) + { + scr = scr_left; + } + else + { + scr = scr_right; + } + + } + // update best_div value + if (DISTANCE(div, best_div) >= DISTANCE(div, cpsr * scr)) + { + best_scr = scr; + best_cpsr = cpsr; + best_div = best_cpsr * best_scr; + if (best_div == div) + break; + } + } + } + + spi->reg->CPSR = best_cpsr & SPI_CPSR_CPSDVSR_Msk; + spi->reg->CR0 = ((spi->reg->CR0 & ~SPI_CR0_SCR_Msk) | EIGEN_VAL2FLD(SPI_CR0_SCR, best_scr - 1)); + + spi->info->bus_speed = spi_clock / (best_cpsr * best_scr); + + return ARM_DRIVER_OK; + +} + +/** + \fn int32_t SPI_Initialize(ARM_SPI_SignalEvent_t cb_event, SPI_RESOURCES *spi) + \brief Initialize SPI Interface. + \param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent + \param[in] spi Pointer to SPI resources + \return \ref execution_status +*/ +int32_t SPI_Initialize(ARM_SPI_SignalEvent_t cb_event, SPI_RESOURCES *spi) +{ + int32_t returnCode; + +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + PadConfig_t config; + + if (spi->info->flags & SPI_FLAG_INITIALIZED) + return ARM_DRIVER_OK; + +#ifdef PM_FEATURE_ENABLE + instance = SPI_GetInstanceNumber(spi); + g_spiDataBase[instance].isInited = true; +#endif + + // Initialize SPI PINS + PAD_getDefaultConfig(&config); + config.mux = spi->pins.pin_sclk->funcNum; + PAD_setPinConfig(spi->pins.pin_sclk->pinNum, &config); + config.mux = spi->pins.pin_ssn->funcNum; + PAD_setPinConfig(spi->pins.pin_ssn->pinNum, &config); + config.mux = spi->pins.pin_mosi->funcNum; + PAD_setPinConfig(spi->pins.pin_mosi->pinNum, &config); + config.mux = spi->pins.pin_miso->funcNum; + PAD_setPinConfig(spi->pins.pin_miso->pinNum, &config); + + // Initialize SPI run-time resources + spi->info->cb_event = cb_event; + + spi->info->status.busy = 0; + spi->info->status.data_lost = 0; + spi->info->status.mode_fault = 0; + + // Clear transfer information + memset(&(spi->info->xfer), 0, sizeof(SPI_TRANSFER_INFO)); + + spi->info->mode = 0; + + // Configure DMA if necessary + if (spi->dma) + { + returnCode = DMA_openChannel(spi->dma->tx_instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + spi->dma->tx_ch = returnCode; + + DMA_setChannelRequestSource(spi->dma->tx_instance, spi->dma->tx_ch, (DmaRequestSource_e)spi->dma->tx_req); + DMA_rigisterChannelCallback(spi->dma->tx_instance, spi->dma->tx_ch, spi->dma->tx_callback); + + returnCode = DMA_openChannel(spi->dma->rx_instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + spi->dma->rx_ch = returnCode; + + DMA_setChannelRequestSource(spi->dma->rx_instance, spi->dma->rx_ch, (DmaRequestSource_e)spi->dma->rx_req); + DMA_rigisterChannelCallback(spi->dma->rx_instance, spi->dma->rx_ch, spi->dma->rx_callback); + } + + spi->info->flags = SPI_FLAG_INITIALIZED; // SPI is initialized + +#ifdef PM_FEATURE_ENABLE + g_spiInitCounter++; + + if(g_spiInitCounter == 1U) + { + g_spiWorkingStatus = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_SPI_MODULE, SPI_EnterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_SPI_MODULE, SPI_ExitLowPowerStateRestore, NULL); + } +#endif + + return ARM_DRIVER_OK; + +} + + +/** + \fn int32_t SPI_Uninitialize(SPI_RESOURCES *ssp) + \brief De-initialize SPI Interface. + \param[in] spi Pointer to SPI resources + \return \ref execution_status +*/ +int32_t SPI_Uninitialize(SPI_RESOURCES *spi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; + + instance = SPI_GetInstanceNumber(spi); + + g_spiDataBase[instance].isInited = false; + + g_spiInitCounter--; + + if(g_spiInitCounter == 0) + { + g_spiWorkingStatus = 0; + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_SPI_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_SPI_MODULE); + } +#endif + + spi->info->flags = 0; // SPI is uninitialized + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t SPI_PowerControl(ARM_POWER_STATE state, SPI_RESOURCES *spi) + \brief Control SPI Interface Power. + \param[in] state Power state + \param[in] spi Pointer to SPI resources + \return \ref execution_status +*/ +int32_t SPI_PowerControl(ARM_POWER_STATE state, SPI_RESOURCES *spi) +{ + uint32_t instance = SPI_GetInstanceNumber(spi); + + switch (state) + { + case ARM_POWER_OFF: + + if(spi->irq) + { + // Disable SPI IRQ + XIC_DisableIRQ(spi->irq->irq_num); + + // Clear pending SPI interrupts + XIC_ClearPendingIRQ(spi->irq->irq_num); + } + + // DMA disable + if(spi->dma) + { + DMA_stopChannel(spi->dma->tx_instance, spi->dma->tx_ch, true); + DMA_stopChannel(spi->dma->rx_instance, spi->dma->rx_ch, true); + } + + // Reset register values + spi->reg->IMSC = 0; + spi->reg->DMACR = 0; + spi->reg->CR0 = 0; + spi->reg->CR1 = 0; + spi->reg->CPSR = 0; + spi->reg->ICR = (SPI_ICR_RTIC_Msk | SPI_ICR_RORIC_Msk); + + // Disable SPI clock + CLOCK_clockDisable(g_spiClocks[instance*2]); + CLOCK_clockDisable(g_spiClocks[instance*2+1]); + + // Clear SPI run-time resources + spi->info->status.busy = 0; + spi->info->status.data_lost = 0; + spi->info->status.mode_fault = 0; + + // Clear transfer information + memset(&(spi->info->xfer), 0, sizeof(SPI_TRANSFER_INFO)); + + spi->info->mode = 0; + + spi->info->flags &= ~SPI_FLAG_POWERED; + break; + + case ARM_POWER_FULL: + if ((spi->info->flags & SPI_FLAG_INITIALIZED) == 0) + return ARM_DRIVER_ERROR; + + if (spi->info->flags & SPI_FLAG_POWERED) + return ARM_DRIVER_OK; + + // Enable spi clock + CLOCK_clockEnable(g_spiClocks[instance*2]); + CLOCK_clockEnable(g_spiClocks[instance*2+1]); + + GPR_swResetModule(&g_spiResetVectors[instance]); + + // Clear interrupts + spi->reg->IMSC = 0; + spi->reg->ICR = (SPI_ICR_RTIC_Msk | SPI_ICR_RORIC_Msk); + + // Reset SPI run-time resources + spi->info->status.busy = 0; + spi->info->status.data_lost = 0; + spi->info->status.mode_fault = 0; + + // Set power flag + spi->info->flags |= SPI_FLAG_POWERED; + + // Clear RX FIFO + while((spi->reg->SR & SPI_SR_RNE_Msk) != 0) + { + spi->reg->DR; + } + + // Enable spi interrupt + if(spi->irq) + { + XIC_SetVector(spi->irq->irq_num, spi->irq->cb_irq); + XIC_EnableIRQ(spi->irq->irq_num); + XIC_SuppressOvfIRQ(spi->irq->irq_num); + } + + break; + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +/** + \fn int32_t SPI_Send(const void *data, uint32_t num, SPI_RESOURCES *spi) + \brief Start sending data to SPI transmitter. + \param[in] data Pointer to buffer with data to send to SPI transmitter + \param[in] num Number of data items to send + \param[in] ssp Pointer to SPI resources + \return \ref execution_status +*/ +int32_t SPI_Send(const void *data, uint32_t num, SPI_RESOURCES *spi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + uint8_t data_width; + + if ((data == NULL) || (num == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + + if (!(spi->info->flags & SPI_FLAG_CONFIGURED)) + return ARM_DRIVER_ERROR; + + if (spi->info->status.busy) + return ARM_DRIVER_ERROR_BUSY; + +#ifdef PM_FEATURE_ENABLE + instance = SPI_GetInstanceNumber(spi); +#endif + + // set busy flag + spi->info->status.busy = 1U; + spi->info->status.data_lost = 0; + spi->info->status.mode_fault = 0; + + spi->info->xfer.rx_buf = NULL; + spi->info->xfer.tx_buf = (uint8_t *)data; + spi->info->xfer.tx_cnt = 0; + spi->info->xfer.rx_cnt = 0; + spi->info->xfer.num = num; + + // whether occupys 2 bytes + data_width = spi->info->data_width; + + // dma mode + if(spi->dma) + { + // transfer number shall exceeds rx trigger level + if(num < SPI_RX_FIFO_TRIG_LVL) + return ARM_DRIVER_ERROR_UNSUPPORTED; + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + + // Configure tx DMA and start it + g_dmaTxConfig.dataWidth = (DmaDataWidth_e)data_width; + g_dmaTxConfig.addressIncrement = DMA_ADDRESS_INCREMENT_SOURCE; + g_dmaTxConfig.sourceAddress = (void *)data; + g_dmaTxConfig.targetAddress = (void *)&(spi->reg->DR); + g_dmaTxConfig.totalLength = num * data_width; + + DMA_transferSetup(spi->dma->tx_instance, spi->dma->tx_ch, &g_dmaTxConfig); + DMA_enableChannelInterrupts(spi->dma->tx_instance, spi->dma->tx_ch, DMA_END_INTERRUPT_ENABLE); + + DMA_startChannel(spi->dma->tx_instance, spi->dma->tx_ch); + + // retrieve data from RX FIFO to get rid of overflow + + + g_dmaRxConfig.dataWidth = (DmaDataWidth_e)data_width; + g_dmaRxConfig.addressIncrement = DMA_ADDRESS_INCREMENT_NONE; + g_dmaRxConfig.sourceAddress = (void *)&(spi->reg->DR); + g_dmaRxConfig.targetAddress = (void *)&spi->info->xfer.dump_val; + g_dmaRxConfig.totalLength = num * data_width; + + DMA_transferSetup(spi->dma->rx_instance, spi->dma->rx_ch, &g_dmaRxConfig); + DMA_enableChannelInterrupts(spi->dma->rx_instance, spi->dma->rx_ch, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(spi->dma->rx_instance, spi->dma->rx_ch); + + // Enable DMA + spi->reg->DMACR |= (SPI_DMACR_TXDMAE_Msk | SPI_DMACR_RXDMAE_Msk); + + } + // irq mode + else if(spi->irq) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + spi->reg->IMSC = SPI_IMSC_TXIM_Msk; + } + // polling mode + else + { + while(spi->info->xfer.num > spi->info->xfer.tx_cnt) + { + if(spi->reg->SR & SPI_SR_TNF_Msk) + { + if(data_width == 2U) + spi->reg->DR = *((uint16_t *)(spi->info->xfer.tx_buf + (spi->info->xfer.tx_cnt << 1U))); + else + spi->reg->DR = spi->info->xfer.tx_buf[spi->info->xfer.tx_cnt]; + spi->info->xfer.tx_cnt++; + + // retrieve data from RX FIFO to get rid of overflow + (void)spi->reg->DR; + } + + } + + do + { + // wait transfer done and retrieve data from RX FIFO to get rid of overflow + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + (void)spi->reg->DR; + } + + }while(spi->reg->SR & SPI_SR_BSY_Msk); + + spi->info->status.busy = 0; + } + + return ARM_DRIVER_OK; +} + + +/** + \fn int32_t SPI_Receive(void *data, uint32_t num, SPI_RESOURCES *spi) + \brief Start receiving data from SPI receiver. + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to receive + \param[in] ssp Pointer to SPI resources + \return \ref execution_status +*/ +int32_t SPI_Receive(void *data, uint32_t num, SPI_RESOURCES *spi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + uint8_t data_width; + + if ((data == NULL) || (num == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + + if (!(spi->info->flags & SPI_FLAG_CONFIGURED)) + return ARM_DRIVER_ERROR; + + if (spi->info->status.busy) + return ARM_DRIVER_ERROR_BUSY; + +#ifdef PM_FEATURE_ENABLE + instance = SPI_GetInstanceNumber(spi); +#endif + + // set busy flag + spi->info->status.busy = 1U; + spi->info->status.data_lost = 0; + spi->info->status.mode_fault = 0; + + spi->info->xfer.rx_buf = (uint8_t *)data; + spi->info->xfer.tx_buf = NULL; + spi->info->xfer.tx_cnt = 0; + spi->info->xfer.rx_cnt = 0; + spi->info->xfer.num = num; + + // whether occupys 2 bytes + data_width = spi->info->data_width; + + // dma mode + if(spi->dma) + { + // transfer number shall exceeds rx trigger level + if(num < SPI_RX_FIFO_TRIG_LVL) + return ARM_DRIVER_ERROR_UNSUPPORTED; + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + + // Configure rx DMA and start it + g_dmaRxConfig.dataWidth = (DmaDataWidth_e)data_width; + g_dmaRxConfig.addressIncrement = DMA_ADDRESS_INCREMENT_TARGET; + g_dmaRxConfig.sourceAddress = (void *)&(spi->reg->DR); + g_dmaRxConfig.targetAddress = (void *)data; + g_dmaRxConfig.totalLength = num * data_width; + + DMA_transferSetup(spi->dma->rx_instance, spi->dma->rx_ch, &g_dmaRxConfig); + DMA_enableChannelInterrupts(spi->dma->rx_instance, spi->dma->rx_ch, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(spi->dma->rx_instance, spi->dma->rx_ch); + + spi->reg->IMSC |= SPI_IMSC_RTIM_Msk | SPI_IMSC_RORIM_Msk; + + // Enable DMA + spi->reg->DMACR |= SPI_DMACR_RXDMAE_Msk; + } + // ird mode + else if(spi->irq) + { + spi->reg->IMSC = SPI_IMSC_RXIM_Msk | SPI_IMSC_RTIM_Msk | SPI_IMSC_RORIM_Msk; + } + // polling mode + else + { + while(spi->info->xfer.num > spi->info->xfer.rx_cnt) + { + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + if(data_width == 2U) + *((uint16_t *)(spi->info->xfer.rx_buf + (spi->info->xfer.rx_cnt << 1U))) = spi->reg->DR; + else + spi->info->xfer.rx_buf[spi->info->xfer.rx_cnt] = (uint8_t)(spi->reg->DR); + + spi->info->xfer.rx_cnt++; + } + } + + spi->info->status.busy = 0; + + } + return ARM_DRIVER_OK; + +} + + +/** + \fn int32_t SPI_Transfer(const void *data_out, + void *data_in, + uint32_t num, + SPI_RESOURCES *spi) + \brief Start sending/receiving data to/from SPI transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to transfer + \param[in] ssp Pointer to SPI resources + \return \ref execution_status +*/ +int32_t SPI_Transfer(const void *data_out, void *data_in, uint32_t num, SPI_RESOURCES *spi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + uint8_t data_width; + + if ((data_out == NULL) || (data_in == NULL) || (num == 0)) + return ARM_DRIVER_ERROR_PARAMETER; + + if (!(spi->info->flags & SPI_FLAG_CONFIGURED)) + return ARM_DRIVER_ERROR; + + if (spi->info->status.busy) + return ARM_DRIVER_ERROR_BUSY; + +#ifdef PM_FEATURE_ENABLE + instance = SPI_GetInstanceNumber(spi); +#endif + + // set busy flag + spi->info->status.busy = 1U; + spi->info->status.data_lost = 0; + spi->info->status.mode_fault = 0; + + spi->info->xfer.rx_buf = (uint8_t *)data_in; + spi->info->xfer.tx_buf = (uint8_t *)data_out; + spi->info->xfer.tx_cnt = 0; + spi->info->xfer.rx_cnt = 0; + spi->info->xfer.num = num; + + // whether occupys 2 bytes + data_width = spi->info->data_width; + + // Wait last operation end + while(spi->reg->SR & SPI_SR_BSY_Msk); + + if(spi->dma) + { + // transfer number shall exceeds rx trigger level + if(num < SPI_RX_FIFO_TRIG_LVL) + return ARM_DRIVER_ERROR_UNSUPPORTED; + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + + // Configure tx DMA and start it + g_dmaTxConfig.dataWidth = (DmaDataWidth_e)data_width; + g_dmaTxConfig.addressIncrement = DMA_ADDRESS_INCREMENT_SOURCE; + g_dmaTxConfig.sourceAddress = (void *)data_out; + g_dmaTxConfig.targetAddress = (void *)&(spi->reg->DR); + g_dmaTxConfig.totalLength = num * data_width; + + DMA_transferSetup(spi->dma->tx_instance, spi->dma->tx_ch, &g_dmaTxConfig); + DMA_enableChannelInterrupts(spi->dma->tx_instance, spi->dma->tx_ch, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(spi->dma->tx_instance, spi->dma->tx_ch); + + // Configure rx DMA and start it + g_dmaRxConfig.dataWidth = (DmaDataWidth_e)data_width; + g_dmaRxConfig.addressIncrement = DMA_ADDRESS_INCREMENT_TARGET; + g_dmaRxConfig.sourceAddress = (void *)&(spi->reg->DR); + g_dmaRxConfig.targetAddress = (void *)data_in; + g_dmaRxConfig.totalLength = num * data_width; + + DMA_transferSetup(spi->dma->rx_instance, spi->dma->rx_ch, &g_dmaRxConfig); + DMA_enableChannelInterrupts(spi->dma->rx_instance, spi->dma->rx_ch, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(spi->dma->rx_instance, spi->dma->rx_ch); + + spi->reg->IMSC |= SPI_IMSC_RTIM_Msk | SPI_IMSC_RORIM_Msk; + + // Enable DMA + spi->reg->DMACR |= (SPI_DMACR_TXDMAE_Msk | SPI_DMACR_RXDMAE_Msk); + + + } + else if(spi->irq) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance); +#endif + spi->reg->IMSC = SPI_IMSC_TXIM_Msk | SPI_IMSC_RXIM_Msk | SPI_IMSC_RTIM_Msk | SPI_IMSC_RORIM_Msk; + } + else + { + while(spi->info->xfer.num > spi->info->xfer.tx_cnt) + { + if(spi->reg->SR & SPI_SR_TNF_Msk) + { + if(data_width == 2U) + { + spi->reg->DR = *((uint16_t *)(spi->info->xfer.tx_buf + (spi->info->xfer.tx_cnt << 1U))); + // RNE flag shall be checked for speed difference of cpu and peripheral working frequency + // data is writen to TX FIFO doesn't mean it has been transmitted + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + *((uint16_t *)(spi->info->xfer.rx_buf + (spi->info->xfer.rx_cnt << 1U))) = spi->reg->DR; + spi->info->xfer.rx_cnt++; + } + } + else + { + spi->reg->DR = spi->info->xfer.tx_buf[spi->info->xfer.tx_cnt]; + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + spi->info->xfer.rx_buf[spi->info->xfer.rx_cnt] = (uint8_t)(spi->reg->DR); + spi->info->xfer.rx_cnt++; + } + } + spi->info->xfer.tx_cnt++; + } + } + + while(spi->info->xfer.rx_cnt < spi->info->xfer.tx_cnt) + { + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + if(data_width == 2U) + *((uint16_t *)(spi->info->xfer.rx_buf + (spi->info->xfer.rx_cnt << 1U))) = spi->reg->DR; + else + spi->info->xfer.rx_buf[spi->info->xfer.rx_cnt] = (uint8_t)(spi->reg->DR); + + spi->info->xfer.rx_cnt++; + } + } + + spi->info->status.busy = 0; + + } + return ARM_DRIVER_OK; + +} + + +/** + \fn uint32_t SPI_GetDataCount(SPI_RESOURCES *spi) + \brief Get transferred data count. + \param[in] spi Pointer to SPI resources + \return number of data items transferred +*/ +uint32_t SPI_GetDataCount(SPI_RESOURCES *spi) +{ + uint32_t cnt; + if (!(spi->info->flags & SPI_FLAG_CONFIGURED)) + return 0; + if (spi->dma) + cnt = DMA_getChannelCount(spi->dma->rx_instance, spi->dma->rx_ch); + else + cnt = spi->info->xfer.rx_cnt; + return cnt; +} + + +/** + \fn int32_t SPI_Control(uint32_t control, uint32_t arg, SPI_RESOURCES *spi) + \brief Control SPI Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \param[in] spi Pointer to SPI resources + \return common \ref execution_status and driver specific \ref spi_execution_status +*/ +int32_t SPI_Control(uint32_t control, uint32_t arg, SPI_RESOURCES *spi) +{ + int32_t ret; + uint32_t dataBits; + PadConfig_t padConfig; + GpioPinConfig_t gpioConfig; + + if(!(spi->info->flags & SPI_FLAG_POWERED)) + return ARM_DRIVER_ERROR; + + if((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_ABORT_TRANSFER) + { + // abort SPI transfer + // Disable SPI and SPI interrupts + spi->reg->CR1 &= ~SPI_CR1_SSE_Msk; + spi->reg->IMSC = 0; + + if(spi->info->status.busy) + { + // If DMA mode, disable DMA channel + if(spi->dma) + { + DMA_stopChannel(spi->dma->tx_instance, spi->dma->tx_ch, true); + DMA_stopChannel(spi->dma->rx_instance, spi->dma->rx_ch, true); + } + } + + // clear SPI run-time resources + spi->info->status.busy = 0; + memset(&(spi->info->xfer), 0, sizeof(SPI_TRANSFER_INFO)); + spi->reg->CR1 |= SPI_CR1_SSE_Msk; + + return ARM_DRIVER_OK; + } + + if(spi->info->status.busy) + { + return ARM_DRIVER_ERROR_BUSY; + } + + switch(control & ARM_SPI_CONTROL_Msk) + { + // SPI Inactive + case ARM_SPI_MODE_INACTIVE: + + // Disable SPI + spi->reg->CR1 &= ~SPI_CR1_SSE_Msk; + // Disable interrupts + spi->reg->IMSC = 0; + spi->info->mode = ((spi->info->mode & ~ARM_SPI_CONTROL_Msk) | ARM_SPI_MODE_INACTIVE); + spi->info->flags &= ~SPI_FLAG_CONFIGURED; + + return ARM_DRIVER_OK; + + // SPI Slave (Output on MISO, Input on MOSI) + case ARM_SPI_MODE_SLAVE: + + // Disable SPI first + spi->reg->CR1 &= ~SPI_CR1_SSE_Msk; + + // Set slave mode and Enable SPI + spi->reg->CR1 |= (SPI_CR1_MS_Msk | SPI_CR1_SSE_Msk); + + spi->info->mode = ((spi->info->mode & ~ARM_SPI_CONTROL_Msk) | ARM_SPI_MODE_SLAVE); + spi->info->flags |= SPI_FLAG_CONFIGURED; + + break; + + // SPI Master (Output/Input on MOSI); arg = Bus Speed in bps + case ARM_SPI_MODE_MASTER_SIMPLEX: + + // SPI Slave (Output/Input on MISO) + case ARM_SPI_MODE_SLAVE_SIMPLEX: + return ARM_SPI_ERROR_MODE; + + // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps + case ARM_SPI_MODE_MASTER: + + // Set Bus Speed in bps; arg = value + case ARM_SPI_SET_BUS_SPEED: + + if((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_MODE_MASTER) + { + // Disable SPI first + spi->reg->CR1 &= ~SPI_CR1_SSE_Msk; + + // Disable interrupts + spi->reg->IMSC = 0; + + // Set master mode and Enable SPI + spi->reg->CR1 = ((spi->reg->CR1 & ~SPI_CR1_MS_Msk) | SPI_CR1_SSE_Msk); + + spi->info->mode = ((spi->info->mode & ~ARM_SPI_CONTROL_Msk) | ARM_SPI_MODE_MASTER); + spi->info->flags |= SPI_FLAG_CONFIGURED; + + } + + ret = SPI_SetBusSpeed(arg, spi); + + if(ret != ARM_DRIVER_OK) + return ARM_DRIVER_ERROR; + + if((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_SET_BUS_SPEED) + { + return ARM_DRIVER_OK; + } + break; + + // Get Bus Speed in bps + case ARM_SPI_GET_BUS_SPEED: + return spi->info->bus_speed; + + // Set default Transmit value; arg = value + case ARM_SPI_SET_DEFAULT_TX_VALUE: + spi->info->xfer.def_val = (uint16_t)(arg & 0xffff); + return ARM_DRIVER_OK; + + // Control Slave Select; arg = 0:inactive, 1:active + case ARM_SPI_CONTROL_SS: + if(SPI0 == spi->reg) + { + GPIO_pinWrite(RTE_SPI0_SSN_GPIO_INSTANCE, 1 << RTE_SPI0_SSN_GPIO_INDEX, arg << RTE_SPI0_SSN_GPIO_INDEX); + } + else if(SPI1 == spi->reg) + { + GPIO_pinWrite(RTE_SPI1_SSN_GPIO_INSTANCE, 1 << RTE_SPI1_SSN_GPIO_INDEX, arg << RTE_SPI1_SSN_GPIO_INDEX); + } + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + } + + // SPI slave select mode for master + if((spi->info->mode & ARM_SPI_CONTROL_Msk) == ARM_SPI_MODE_MASTER) + { + switch(control & ARM_SPI_SS_MASTER_MODE_Msk) + { + // SPI Slave Select when Master: Not used(default) + case ARM_SPI_SS_MASTER_UNUSED: + spi->info->mode = (spi->info->mode & ~ARM_SPI_SS_MASTER_MODE_Msk) | ARM_SPI_SS_MASTER_UNUSED; + break; + + case ARM_SPI_SS_MASTER_SW: + + PAD_getDefaultConfig(&padConfig); + padConfig.mux = PAD_MUX_ALT0; + PAD_setPinConfig(spi->pins.pin_ssn->pinNum, &padConfig); + + gpioConfig.pinDirection = GPIO_DIRECTION_OUTPUT; + gpioConfig.misc.initOutput = 1U; + + if(SPI0 == spi->reg) + { + GPIO_pinConfig(RTE_SPI0_SSN_GPIO_INSTANCE, RTE_SPI0_SSN_GPIO_INDEX, &gpioConfig); + } + else if(SPI1 == spi->reg) + { + GPIO_pinConfig(RTE_SPI1_SSN_GPIO_INSTANCE, RTE_SPI1_SSN_GPIO_INDEX, &gpioConfig); + } + + spi->info->mode = (spi->info->mode & ~ARM_SPI_SS_MASTER_MODE_Msk) | ARM_SPI_SS_MASTER_SW; + + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: + + PAD_getDefaultConfig(&padConfig); + padConfig.mux = spi->pins.pin_ssn->funcNum; + PAD_setPinConfig(spi->pins.pin_ssn->pinNum, &padConfig); + + spi->info->mode = (spi->info->mode & ~ARM_SPI_SS_MASTER_MODE_Msk) | ARM_SPI_SS_MASTER_HW_OUTPUT; + + break; + case ARM_SPI_SS_MASTER_HW_INPUT: + return ARM_SPI_ERROR_SS_MODE; + default: + break; + } + } + + // SPI slave select mode for slave + if((spi->info->mode & ARM_SPI_CONTROL_Msk) == ARM_SPI_MODE_SLAVE) + { + switch(control & ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + spi->info->mode &= ~ARM_SPI_SS_SLAVE_MODE_Msk; + spi->info->mode |= ARM_SPI_SS_SLAVE_HW; + break; + case ARM_SPI_SS_SLAVE_SW: + return ARM_SPI_ERROR_SS_MODE; + default: + break; + } + } + + // set SPI frame format + switch(control & ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + spi->reg->CR0 &= ~(SPI_CR0_FRF_Msk | SPI_CR0_SPO_Msk | SPI_CR0_SPH_Msk); + break; + case ARM_SPI_CPOL0_CPHA1: + spi->reg->CR0 = (spi->reg->CR0 & ~(SPI_CR0_FRF_Msk | SPI_CR0_SPO_Msk)) | SPI_CR0_SPH_Msk; + break; + case ARM_SPI_CPOL1_CPHA0: + spi->reg->CR0 = (spi->reg->CR0 & ~(SPI_CR0_FRF_Msk | SPI_CR0_SPH_Msk)) | SPI_CR0_SPO_Msk; + break; + case ARM_SPI_CPOL1_CPHA1: + spi->reg->CR0 = (spi->reg->CR0 & ~SPI_CR0_FRF_Msk) | SPI_CR0_SPO_Msk | SPI_CR0_SPH_Msk; + break; + case ARM_SPI_TI_SSI: + spi->reg->CR0 = (spi->reg->CR0 & ~SPI_CR0_FRF_Msk) | (1U << SPI_CR0_FRF_Pos); + break; + case ARM_SPI_MICROWIRE: + spi->reg->CR0 = (spi->reg->CR0 & ~SPI_CR0_FRF_Msk) | (2U << SPI_CR0_FRF_Pos); + default: + return ARM_SPI_ERROR_FRAME_FORMAT; + } + // set number of data bits + dataBits = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos); + + if((dataBits >= 4U) && (dataBits <= 16U)) + { + spi->reg->CR0 = (spi->reg->CR0 & ~SPI_CR0_DSS_Msk) | (dataBits - 1U); + spi->info->data_width = (dataBits > 8U) ? 2U : 1U; + } + else + return ARM_SPI_ERROR_DATA_BITS; + + // set SPI bit order + if((control & ARM_SPI_BIT_ORDER_Msk) == ARM_SPI_LSB_MSB) + return ARM_SPI_ERROR_BIT_ORDER; + return ARM_DRIVER_OK; +} + + +/** + \fn ARM_SPI_STATUS SPI_GetStatus(SPI_RESOURCES *spi) + \brief Get SPI status. + \param[in] spi Pointer to SPI resources + \return SPI status \ref ARM_SPI_STATUS +*/ +ARM_SPI_STATUS SPI_GetStatus(SPI_RESOURCES *spi) +{ + ARM_SPI_STATUS status; + status.busy = spi->info->status.busy; + status.data_lost = spi->info->status.data_lost; + status.mode_fault = spi->info->status.mode_fault; + return (status); +} + + +/** + \fn void SPI_IRQHandler(SPI_RESOURCES *spi) + \brief SPI Interrupt handler. + \param[in] spi Pointer to SPI resources +*/ +void SPI_IRQHandler(SPI_RESOURCES *spi) +{ + uint32_t mis, data_width; + +#ifdef PM_FEATURE_ENABLE + uint32_t instance = SPI_GetInstanceNumber(spi); + LOCK_SLEEP(instance); +#endif + + // whether occupys 2 bytes + data_width = spi->info->data_width; + + mis = spi->reg->MIS; + spi->reg->ICR = mis & (SPI_ICR_RTIC_Msk | SPI_ICR_RORIC_Msk); + + // full duplex + if(spi->info->xfer.tx_buf && spi->info->xfer.rx_buf) + { + while((spi->reg->SR & SPI_SR_TNF_Msk) && (spi->info->xfer.num > spi->info->xfer.tx_cnt)) + { + if(data_width == 2U) + { + spi->reg->DR = *((uint16_t *)(spi->info->xfer.tx_buf + (spi->info->xfer.tx_cnt << 1U))); + // RNE flag shall be checked for speed difference of cpu and peripheral working frequency + // data is writen to TX FIFO doesn't mean it has been transmitted + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + *((uint16_t *)(spi->info->xfer.rx_buf + (spi->info->xfer.rx_cnt << 1U))) = spi->reg->DR; + spi->info->xfer.rx_cnt++; + } + } + else + { + spi->reg->DR = spi->info->xfer.tx_buf[spi->info->xfer.tx_cnt]; + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + spi->info->xfer.rx_buf[spi->info->xfer.rx_cnt] = (uint8_t)(spi->reg->DR); + spi->info->xfer.rx_cnt++; + } + } + spi->info->xfer.tx_cnt++; + } + + // Disable TX interupt to get rid of xic overflow + if(spi->info->xfer.num == spi->info->xfer.tx_cnt) + { + spi->reg->IMSC &= ~SPI_IMSC_TXIM_Msk; + } + + if((spi->dma) && (mis & SPI_MIS_RTMIS_Msk)) + { + spi->info->xfer.rx_cnt = DMA_getChannelCount(spi->dma->rx_instance, spi->dma->rx_ch); + DMA_stopChannel(spi->dma->rx_instance, spi->dma->rx_ch, true); + } + + while((spi->reg->SR & SPI_SR_RNE_Msk) && (spi->info->xfer.rx_cnt < spi->info->xfer.tx_cnt)) + { + if(data_width == 2U) + *((uint16_t *)(spi->info->xfer.rx_buf + (spi->info->xfer.rx_cnt << 1U))) = spi->reg->DR; + else + spi->info->xfer.rx_buf[spi->info->xfer.rx_cnt] = (uint8_t)(spi->reg->DR); + + spi->info->xfer.rx_cnt++; + } + + } + // send only + else if(spi->info->xfer.tx_buf) + { + while((spi->reg->SR & SPI_SR_TNF_Msk) && (spi->info->xfer.num > spi->info->xfer.tx_cnt)) + { + if(data_width == 2U) + spi->reg->DR = *((uint16_t *)(spi->info->xfer.tx_buf + (spi->info->xfer.tx_cnt << 1U))); + else + spi->reg->DR = spi->info->xfer.tx_buf[spi->info->xfer.tx_cnt]; + spi->info->xfer.tx_cnt++; + + // retrieve data from RX FIFO to get rid of overflow + if(spi->reg->SR & SPI_SR_RNE_Msk) + { + (void)spi->reg->DR; + spi->info->xfer.rx_cnt++; + } + } + + if((spi->dma) && (mis & SPI_MIS_RTMIS_Msk)) + { + spi->info->xfer.rx_cnt = DMA_getChannelCount(spi->dma->rx_instance, spi->dma->rx_ch); + DMA_stopChannel(spi->dma->rx_instance, spi->dma->rx_ch, true); + } + + // retrieve data from RX FIFO to get rid of overflow + while(spi->reg->SR & SPI_SR_RNE_Msk) + { + (void)spi->reg->DR; + spi->info->xfer.rx_cnt++; + } + } + // receive only + else if(spi->info->xfer.rx_buf) + { + if((spi->dma) && (mis & SPI_MIS_RTMIS_Msk)) + { + spi->info->xfer.rx_cnt = DMA_getChannelCount(spi->dma->rx_instance, spi->dma->rx_ch); + DMA_stopChannel(spi->dma->rx_instance, spi->dma->rx_ch, true); + } + while((spi->info->xfer.num > spi->info->xfer.rx_cnt) && (spi->reg->SR & SPI_SR_RNE_Msk)) + { + if(data_width == 2U) + *((uint16_t *)(spi->info->xfer.rx_buf + (spi->info->xfer.rx_cnt << 1U))) = spi->reg->DR; + else + spi->info->xfer.rx_buf[spi->info->xfer.rx_cnt] = (uint8_t)(spi->reg->DR); + + spi->info->xfer.rx_cnt++; + } + } + + + //---------------------------------- complete criteria ------------------------------------------- + // dma mode irq mode + // tx rx_cnt = num && tx_cnt = num(first reach) rx_cnt = num && tx_cnt = num + // rx rx_cnt = num && tx_cnt = 0 rx_cnt = num && tx_cnt = 0 + // tx&rx rx_cnt = num && tx_cnt = num(first reach) rx_cnt = num && tx_cnt = num + //------------------------------------------------------------------------------------------------ + + if(spi->info->xfer.rx_cnt == spi->info->xfer.num) + { + // disable interrupts no matter what kind of trasaction is + spi->reg->IMSC &= ~(SPI_IMSC_TXIM_Msk | SPI_IMSC_RXIM_Msk | SPI_IMSC_RTIM_Msk | SPI_IMSC_RORIM_Msk); + spi->info->status.busy = 0; + if(spi->info->cb_event) + { + spi->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + } + + if(mis & SPI_MIS_RORMIS_Msk) + { + // Handle errors + // Overrun flag is set + spi->info->status.data_lost = 1U; + if(spi->info->cb_event) + spi->info->cb_event(ARM_SPI_EVENT_DATA_LOST); + + } + +} + +/** + \fn void SPI_DmaTxEvent(uint32_t event, SPI_RESOURCES *spi) + \brief SPI DMA Tx Event handler. + \param[in] event DMA Tx Event + \param[in] spi Pointer to SPI resources +*/ +void SPI_DmaTxEvent(uint32_t event, SPI_RESOURCES *spi) +{ + + switch (event) + { + case DMA_EVENT_END: + // Disable DMA + spi->reg->DMACR &= ~SPI_DMACR_TXDMAE_Msk; + spi->info->xfer.tx_cnt = spi->info->xfer.num; + // update below flags in rx callback +#if 0 + spi->info->status.busy = 0; + if (spi->info->cb_event) + { + spi->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE); + } +#endif + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + + +/** + \fn void SPI_DmaRxEvent(uint32_t event, SPI_RESOURCES *spi) + \brief SPI DMA Rx Event handler. + \param[in] event DMA Rx Event + \param[in] spi Pointer to SPI resources +*/ +void SPI_DmaRxEvent(uint32_t event, SPI_RESOURCES *spi) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = SPI_GetInstanceNumber(spi); +#endif + + switch(event) + { + case DMA_EVENT_END: + + spi->info->xfer.rx_cnt = spi->info->xfer.num; + + DMA_stopChannel(spi->dma->rx_instance, spi->dma->rx_ch, true); + spi->reg->DMACR &= ~SPI_DMACR_RXDMAE_Msk; + spi->info->status.busy = 0; + + if(spi->info->cb_event) + { + spi->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE); + } +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance); +#endif + + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + + +#if (RTE_SPI0) + +static int32_t SPI0_Initialize(ARM_SPI_SignalEvent_t pSignalEvent) +{ + return SPI_Initialize(pSignalEvent, &SPI0_Resources); +} +static int32_t SPI0_Uninitialize(void) +{ + return SPI_Uninitialize(&SPI0_Resources); +} +static int32_t SPI0_PowerControl(ARM_POWER_STATE state) +{ + return SPI_PowerControl(state, &SPI0_Resources); +} +static int32_t SPI0_Send(const void *data, uint32_t num) +{ + return SPI_Send(data, num, &SPI0_Resources); +} +static int32_t SPI0_Receive(void *data, uint32_t num) +{ + return SPI_Receive(data, num, &SPI0_Resources); +} +static int32_t SPI0_Transfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_Transfer(data_out, data_in, num, &SPI0_Resources); +} +static uint32_t SPI0_GetDataCount(void) +{ + return SPI_GetDataCount(&SPI0_Resources); +} +static int32_t SPI0_Control(uint32_t control, uint32_t arg) +{ + return SPI_Control(control, arg, &SPI0_Resources); +} +static ARM_SPI_STATUS SPI0_GetStatus(void) +{ + return SPI_GetStatus(&SPI0_Resources); +} +void SPI0_IRQHandler(void) +{ + SPI_IRQHandler(&SPI0_Resources); +} +void SPI0_DmaTxEvent(uint32_t event) +{ + SPI_DmaTxEvent(event, &SPI0_Resources); +} +void SPI0_DmaRxEvent(uint32_t event) +{ + SPI_DmaRxEvent(event, &SPI0_Resources); +} + +// SPI0 Driver Control Block +ARM_DRIVER_SPI Driver_SPI0 = { + SPI_GetVersion, + SPI_GetCapabilities, + SPI0_Initialize, + SPI0_Uninitialize, + SPI0_PowerControl, + SPI0_Send, + SPI0_Receive, + SPI0_Transfer, + SPI0_GetDataCount, + SPI0_Control, + SPI0_GetStatus +}; + +#endif + +#if (RTE_SPI1) + +static int32_t SPI1_Initialize(ARM_SPI_SignalEvent_t pSignalEvent) +{ + return SPI_Initialize(pSignalEvent, &SPI1_Resources); +} +static int32_t SPI1_Uninitialize(void) +{ + return SPI_Uninitialize(&SPI1_Resources); +} +static int32_t SPI1_PowerControl(ARM_POWER_STATE state) +{ + return SPI_PowerControl(state, &SPI1_Resources); +} +static int32_t SPI1_Send(const void *data, uint32_t num) +{ + return SPI_Send(data, num, &SPI1_Resources); +} +static int32_t SPI1_Receive(void *data, uint32_t num) +{ + return SPI_Receive(data, num, &SPI1_Resources); +} +static int32_t SPI1_Transfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_Transfer(data_out, data_in, num, &SPI1_Resources); +} +static uint32_t SPI1_GetDataCount(void) +{ + return SPI_GetDataCount(&SPI1_Resources); +} +static int32_t SPI1_Control(uint32_t control, uint32_t arg) +{ + return SPI_Control(control, arg, &SPI1_Resources); +} +static ARM_SPI_STATUS SPI1_GetStatus(void) +{ + return SPI_GetStatus(&SPI1_Resources); +} +void SPI1_IRQHandler(void) +{ + SPI_IRQHandler(&SPI1_Resources); +} +void SPI1_DmaTxEvent(uint32_t event) +{ + SPI_DmaTxEvent(event, &SPI1_Resources); +} +void SPI1_DmaRxEvent(uint32_t event) +{ + SPI_DmaRxEvent(event, &SPI1_Resources); +} + +// SPI1 Driver Control Block +ARM_DRIVER_SPI Driver_SPI1 = { + SPI_GetVersion, + SPI_GetCapabilities, + SPI1_Initialize, + SPI1_Uninitialize, + SPI1_PowerControl, + SPI1_Send, + SPI1_Receive, + SPI1_Transfer, + SPI1_GetDataCount, + SPI1_Control, + SPI1_GetStatus +}; + +#endif diff --git a/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_usart.c b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_usart.c new file mode 100644 index 0000000..1cd0378 --- /dev/null +++ b/PLAT/driver/chip/ec618/ap/src_cmsis/bsp_usart.c @@ -0,0 +1,2047 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Driver_Common.h" +#include "bsp_usart.h" +#include "slpman.h" + +#ifdef PM_FEATURE_ENABLE +#define USART_DEBUG 1 +#if USART_DEBUG +#include DEBUG_LOG_HEADER_FILE +#endif +#endif + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */ + +#if ((!RTE_UART0) && (!RTE_UART1)) && (!RTE_UART2) +#error "UART not enabled in RTE_Device.h!" +#endif + +enum _USART_RX_FIFO_TRIG_LVL +{ + RX_FIFO_TRIG_LVL_1BYTE = 1U, + RX_FIFO_TRIG_LVL_8BYTE = 8U, + RX_FIFO_TRIG_LVL_16BYTE = 16U, + RX_FIFO_TRIG_LVL_30BYTE = 30U +}; + +enum _USART_TX_FIFO_TRIG_LVL +{ + TX_FIFO_TRIG_LVL_0BYTE, + TX_FIFO_TRIG_LVL_2BYTE, + TX_FIFO_TRIG_LVL_8BYTE, + TX_FIFO_TRIG_LVL_16BYTE +}; + +#define UART_DMA_BURST_SIZE 8 + +// Trigger level definitions +#ifndef USART0_RX_TRIG_LVL + +#if (RTE_UART0_RX_IO_MODE == DMA_MODE) +#define USART0_RX_TRIG_LVL RX_FIFO_TRIG_LVL_16BYTE +#else +#define USART0_RX_TRIG_LVL RX_FIFO_TRIG_LVL_30BYTE +#endif + +#endif + +#ifndef USART1_RX_TRIG_LVL + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) +#define USART1_RX_TRIG_LVL RX_FIFO_TRIG_LVL_16BYTE +#else +#define USART1_RX_TRIG_LVL RX_FIFO_TRIG_LVL_30BYTE +#endif + +#endif + +#ifndef USART2_RX_TRIG_LVL + +#if (RTE_UART2_RX_IO_MODE == DMA_MODE) +#define USART2_RX_TRIG_LVL RX_FIFO_TRIG_LVL_16BYTE +#else +#define USART2_RX_TRIG_LVL RX_FIFO_TRIG_LVL_30BYTE +#endif + +#endif + +#define USART0_TX_TRIG_LVL TX_FIFO_TRIG_LVL_0BYTE +#define USART1_TX_TRIG_LVL TX_FIFO_TRIG_LVL_0BYTE +#define USART2_TX_TRIG_LVL TX_FIFO_TRIG_LVL_0BYTE + +#ifdef PM_FEATURE_ENABLE +/** \brief Internal used data structure */ +typedef struct _usart_database +{ + bool isInited; /**< Whether usart has been initialized */ + struct + { + uint32_t DLL; /**< Divisor Latch Low */ + uint32_t DLH; /**< Divisor Latch High */ + uint32_t IER; /**< Interrupt Enable Register */ + uint32_t FCR; /**< FIFO Control Register */ + uint32_t LCR; /**< Line Control Register */ + uint32_t MCR; /**< Modem Control Register */ + uint32_t MFCR; /**< Main Function Control Register */ + uint32_t EFCR; /**< Extended Function Control Register */ + uint32_t ADCR; /**< Auto-baud Detect Control Register*/ + } backup_registers; /**< Backup registers for low power restore */ + bool autoBaudRateDone; /**< Flag indication whether auto baud dection is done */ +} usart_database_t; + +static usart_database_t g_usartDataBase[USART_INSTANCE_NUM] = {0}; + +static USART_TypeDef* const g_usartBases[USART_INSTANCE_NUM] = {USART_0, USART_1, USART_2}; +#endif + +static const ClockId_e g_uartClocks[USART_INSTANCE_NUM*2] = {PCLK_UART0, FCLK_UART0, + PCLK_UART1, FCLK_UART1, + PCLK_UART2, FCLK_UART2 + }; + +static const ClockResetVector_t g_usartResetVectors[] = {UART0_RESET_VECTOR, UART1_RESET_VECTOR, UART2_RESET_VECTOR}; + +#ifdef PM_FEATURE_ENABLE +/** + \brief usart initialization counter, for lower power callback register/de-register + */ +static uint32_t g_usartInitCounter = 0; + +/** + \brief Bitmap of USART working status, + when all USART instances are not working, we can vote to enter to low power state. + */ +static uint32_t g_usartWorkingStatus = 0; + + +/** + \fn static void USART_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) + \brief Perform necessary preparations before sleep. + After recovering from SLPMAN_SLEEP1_STATE, USART hareware is repowered, we backup + some registers here first so that we can restore user's configurations after exit. + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + */ +static void USART_EnterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + uint32_t i; + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + for(i = 0; i < USART_INSTANCE_NUM; i++) + { + if(g_usartDataBase[i].isInited == true) + { + g_usartDataBase[i].backup_registers.IER = g_usartBases[i]->IER; + g_usartDataBase[i].backup_registers.LCR = g_usartBases[i]->LCR; + g_usartDataBase[i].backup_registers.MCR = g_usartBases[i]->MCR; + g_usartDataBase[i].backup_registers.MFCR = g_usartBases[i]->MFCR; + g_usartDataBase[i].backup_registers.EFCR = g_usartBases[i]->EFCR; + g_usartDataBase[i].backup_registers.ADCR = g_usartBases[i]->ADCR; + } + } + break; + default: + break; + } + +} + +/** + \fn static void USART_ExitLowPowerStateRestore(void* pdata, slpManLpState state) + \brief Restore after exit from sleep. + After recovering from SLPMAN_SLEEP1_STATE, USART hareware is repowered, we restore user's configurations + by aidding of the stored registers. + + \param[in] pdata pointer to user data, not used now + \param[in] state low power state + + */ +static void USART_ExitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + uint32_t i; + extern bool apmuGetSleepedFlag(void); + + switch (state) + { + case SLPMAN_SLEEP1_STATE: + + // no need to restore if failing to sleep + if(apmuGetSleepedFlag() == false) + { + break; + } + + for(i = 0; i < USART_INSTANCE_NUM; i++) + { + if(g_usartDataBase[i].isInited == true) + { + GPR_clockEnable(g_uartClocks[2*i]); + GPR_clockEnable(g_uartClocks[2*i+1]); + + g_usartBases[i]->LCR |= USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + g_usartBases[i]->DLL = g_usartDataBase[i].backup_registers.DLL; + g_usartBases[i]->DLH = g_usartDataBase[i].backup_registers.DLH; + + g_usartBases[i]->LCR &= ~USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + g_usartBases[i]->IER = g_usartDataBase[i].backup_registers.IER; + g_usartBases[i]->LCR = g_usartDataBase[i].backup_registers.LCR; + g_usartBases[i]->MCR = g_usartDataBase[i].backup_registers.MCR; + g_usartBases[i]->EFCR = g_usartDataBase[i].backup_registers.EFCR; + g_usartBases[i]->FCR = g_usartDataBase[i].backup_registers.FCR; + g_usartBases[i]->MFCR = g_usartDataBase[i].backup_registers.MFCR; + } + } + break; + + default: + break; + } + +} + +#define LOCK_SLEEP(instance, tx, rx) do \ + { \ + g_usartWorkingStatus |= (rx << (2 * instance)); \ + g_usartWorkingStatus |= (tx << (2 * instance + 1)); \ + slpManDrvVoteSleep(SLP_VOTE_USART, SLP_ACTIVE_STATE); \ + } \ + while(0) + +#define CHECK_TO_UNLOCK_SLEEP(instance, tx, rx) do \ + { \ + g_usartWorkingStatus &= ~(rx << (2 * instance)); \ + g_usartWorkingStatus &= ~(tx << (2 * instance + 1)); \ + if(g_usartWorkingStatus == 0) \ + slpManDrvVoteSleep(SLP_VOTE_USART, SLP_SLP1_STATE); \ + } \ + while(0) +#endif + +// declearation for DMA API +extern void DMA_stopChannelNoWait(DmaInstance_e instance, uint32_t channel); +extern uint32_t DMA_setDescriptorTransferLen(uint32_t dcmd, uint32_t len); +extern void DMA_loadChannelDescriptorAndRun(DmaInstance_e instance, uint32_t channel, void* descriptorAddress); +extern uint32_t DMA_getChannelCurrentTargetAddress(DmaInstance_e instance, uint32_t channel, bool sync); +extern void DMA_buildDescriptor(DmaDescriptor_t* descriptor, const DmaTransferConfig_t* config, const DmaExtraConfig_t* extraConfig); + +// Driver Version +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +// Driver Capabilities +static const ARM_USART_CAPABILITIES DriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0 /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +void USART0_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); + +#if (RTE_UART0) + +static USART_INFO USART0_Info = { 0U }; +static const PIN USART0_pin_tx = {RTE_UART0_TX_BIT, RTE_UART0_TX_FUNC}; +static const PIN USART0_pin_rx = {RTE_UART0_RX_BIT, RTE_UART0_RX_FUNC}; +#if (RTE_UART0_CTS_PIN_EN == 1) +static const PIN USART0_pin_cts = {RTE_UART0_CTS_BIT, RTE_UART0_CTS_FUNC}; +#endif +#if (RTE_UART0_RTS_PIN_EN == 1) +static const PIN USART0_pin_rts = {RTE_UART0_RTS_BIT, RTE_UART0_RTS_FUNC}; +#endif + +#if (RTE_UART0_TX_IO_MODE == DMA_MODE) + +void USART0_DmaTxEvent(uint32_t event); +static USART_TX_DMA USART0_DMA_Tx = { + DMA_INSTANCE_MP, + -1, + RTE_UART0_DMA_TX_REQID, + USART0_DmaTxEvent + }; +#endif + +#if (RTE_UART0_RX_IO_MODE == DMA_MODE) + +void USART0_DmaRxEvent(uint32_t event); + +static DmaDescriptor_t __ALIGNED(16) USART0_DMA_Rx_Descriptor[2]; + +static USART_RX_DMA USART0_DMA_Rx = { + DMA_INSTANCE_MP, + -1, + RTE_UART0_DMA_RX_REQID, + USART0_DMA_Rx_Descriptor, + USART0_DmaRxEvent + }; + +#endif + +#if (RTE_UART0_TX_IO_MODE == IRQ_MODE) || (RTE_UART0_RX_IO_MODE == IRQ_MODE) || (RTE_UART0_RX_IO_MODE == DMA_MODE) +static USART_IRQ USART0_IRQ = { + PXIC0_UART0_IRQn, + USART0_IRQHandler + }; +#endif + + +static const USART_RESOURCES USART0_Resources = { + USART_0, + { + &USART0_pin_tx, + &USART0_pin_rx, +#if (RTE_UART0_CTS_PIN_EN == 1) + &USART0_pin_cts, +#else + NULL, +#endif +#if (RTE_UART0_RTS_PIN_EN == 1) + &USART0_pin_rts, +#else + NULL, +#endif + }, + +#if (RTE_UART0_TX_IO_MODE == DMA_MODE) + &USART0_DMA_Tx, +#else + NULL, +#endif + +#if (RTE_UART0_RX_IO_MODE == DMA_MODE) + &USART0_DMA_Rx, +#else + NULL, +#endif +#if (RTE_UART0_TX_IO_MODE == IRQ_MODE) || (RTE_UART0_RX_IO_MODE == IRQ_MODE) || (RTE_UART0_RX_IO_MODE == DMA_MODE) + &USART0_IRQ, +#else + NULL, +#endif + USART0_TX_TRIG_LVL, + USART0_RX_TRIG_LVL, + &USART0_Info, +#if (RTE_UART0_TX_IO_MODE == UNILOG_MODE) + 1, +#else + 0 +#endif +}; + +#endif + +#if (RTE_UART1) + +static USART_INFO USART1_Info = { 0 }; +static const PIN USART1_pin_tx = {RTE_UART1_TX_BIT, RTE_UART1_TX_FUNC}; +static const PIN USART1_pin_rx = {RTE_UART1_RX_BIT, RTE_UART1_RX_FUNC}; +#if (RTE_UART1_CTS_PIN_EN == 1) +static const PIN USART1_pin_cts = {RTE_UART1_CTS_BIT, RTE_UART1_CTS_FUNC}; +#endif +#if (RTE_UART1_RTS_PIN_EN == 1) +static const PIN USART1_pin_rts = {RTE_UART1_RTS_BIT, RTE_UART1_RTS_FUNC}; +#endif + +#if (RTE_UART1_TX_IO_MODE == DMA_MODE) + +void USART1_DmaTxEvent(uint32_t event); +static USART_TX_DMA USART1_DMA_Tx = { + DMA_INSTANCE_MP, + -1, + RTE_UART1_DMA_TX_REQID, + USART1_DmaTxEvent + }; +#endif + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) + +void USART1_DmaRxEvent(uint32_t event); + +static DmaDescriptor_t __ALIGNED(16) USART1_DMA_Rx_Descriptor[2]; + +static USART_RX_DMA USART1_DMA_Rx = { + DMA_INSTANCE_MP, + -1, + RTE_UART1_DMA_RX_REQID, + USART1_DMA_Rx_Descriptor, + USART1_DmaRxEvent + }; + +#endif + +#if (RTE_UART1_TX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == DMA_MODE) +static USART_IRQ USART1_IRQ = { + PXIC0_UART1_IRQn, + USART1_IRQHandler + }; +#endif + +static const USART_RESOURCES USART1_Resources = { + USART_1, + { + &USART1_pin_tx, + &USART1_pin_rx, +#if (RTE_UART1_CTS_PIN_EN == 1) + &USART1_pin_cts, +#else + NULL, +#endif +#if (RTE_UART1_RTS_PIN_EN == 1) + &USART1_pin_rts, +#else + NULL, +#endif + }, + +#if (RTE_UART1_TX_IO_MODE == DMA_MODE) + &USART1_DMA_Tx, +#else + NULL, +#endif + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) + &USART1_DMA_Rx, +#else + NULL, +#endif +#if (RTE_UART1_TX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == IRQ_MODE) || (RTE_UART1_RX_IO_MODE == DMA_MODE) + &USART1_IRQ, +#else + NULL, +#endif + USART1_TX_TRIG_LVL, + USART1_RX_TRIG_LVL, + &USART1_Info, +#if (RTE_UART1_TX_IO_MODE == UNILOG_MODE) + 1, +#else + 0 +#endif +}; +#endif + +#if (RTE_UART2) + +static USART_INFO USART2_Info = { 0 }; +static const PIN USART2_pin_tx = {RTE_UART2_TX_BIT, RTE_UART2_TX_FUNC}; +static const PIN USART2_pin_rx = {RTE_UART2_RX_BIT, RTE_UART2_RX_FUNC}; +#if (RTE_UART2_CTS_PIN_EN == 1) +static const PIN USART2_pin_cts = {RTE_UART2_CTS_BIT, RTE_UART2_CTS_FUNC}; +#endif +#if (RTE_UART2_RTS_PIN_EN == 1) +static const PIN USART2_pin_rts = {RTE_UART2_RTS_BIT, RTE_UART2_RTS_FUNC}; +#endif + +#if (RTE_UART2_TX_IO_MODE == DMA_MODE) + +void USART2_DmaTxEvent(uint32_t event); +static USART_TX_DMA USART2_DMA_Tx = { + DMA_INSTANCE_MP, + -1, + RTE_UART2_DMA_TX_REQID, + USART2_DmaTxEvent + }; +#endif + +#if (RTE_UART2_RX_IO_MODE == DMA_MODE) + +void USART2_DmaRxEvent(uint32_t event); + +static DmaDescriptor_t __ALIGNED(16) USART2_DMA_Rx_Descriptor[2]; + +static USART_RX_DMA USART2_DMA_Rx = { + DMA_INSTANCE_MP, + -1, + RTE_UART2_DMA_RX_REQID, + USART2_DMA_Rx_Descriptor, + USART2_DmaRxEvent + }; + +#endif + +#if (RTE_UART2_TX_IO_MODE == IRQ_MODE) || (RTE_UART2_RX_IO_MODE == IRQ_MODE) || (RTE_UART2_RX_IO_MODE == DMA_MODE) +static USART_IRQ USART2_IRQ = { + PXIC0_UART2_IRQn, + USART2_IRQHandler + }; +#endif + +static const USART_RESOURCES USART2_Resources = { + USART_2, + { + &USART2_pin_tx, + &USART2_pin_rx, +#if (RTE_UART2_CTS_PIN_EN == 1) + &USART2_pin_cts, +#else + NULL, +#endif +#if (RTE_UART2_RTS_PIN_EN == 1) + &USART2_pin_rts, +#else + NULL, +#endif + }, + +#if (RTE_UART2_TX_IO_MODE == DMA_MODE) + &USART2_DMA_Tx, +#else + NULL, +#endif + +#if (RTE_UART2_RX_IO_MODE == DMA_MODE) + &USART2_DMA_Rx, +#else + NULL, +#endif +#if (RTE_UART2_TX_IO_MODE == IRQ_MODE) || (RTE_UART2_RX_IO_MODE == IRQ_MODE) || (RTE_UART2_RX_IO_MODE == DMA_MODE) + &USART2_IRQ, +#else + NULL, +#endif + USART2_TX_TRIG_LVL, + USART2_RX_TRIG_LVL, + &USART2_Info, +#if (RTE_UART2_TX_IO_MODE == UNILOG_MODE) + 1, +#else + 0 +#endif +}; +#endif + + +static DmaTransferConfig_t dmaTxConfig = {NULL, NULL, + DMA_FLOW_CONTROL_TARGET, DMA_ADDRESS_INCREMENT_SOURCE, + DMA_DATA_WIDTH_ONE_BYTE, DMA_BURST_16_BYTES, 0 + }; + +ARM_DRIVER_VERSION ARM_USART_GetVersion(void) +{ + return DriverVersion; +} + +ARM_USART_CAPABILITIES USART_GetCapabilities(const USART_RESOURCES *usart) +{ + return DriverCapabilities; +} + +PLAT_PA_RAMCODE static uint32_t USART_GetInstanceNumber(USART_RESOURCES *usart) +{ + return ((uint32_t)usart->reg - (uint32_t)USART_0) >> 12; +} + +/* + * when uart input clock is 26000000, the supported baudrate is: + * 300,600,1200,2400, + * 4800,9600,14400,19200, + * 28800,38400,56000,57600, + * 115200,230400,460800,921600, + * 1000000,1500000,2000000,3000000 + * + */ +int32_t USART_SetBaudrate (uint32_t baudrate, USART_RESOURCES *usart) +{ + uint8_t frac = 0; + uint32_t uart_clock = 0; + uint32_t div, instance; + int32_t i; + + instance = USART_GetInstanceNumber(usart); + + uart_clock = GPR_getClockFreq(g_uartClocks[instance*2+1]); + + if(baudrate == 0) + { + usart->reg->ADCR = 0x3; + } + else + { + /* + * formula to calculate baudrate, baudrate = clock_in / (prescalar * divisor_value), + * where prescalar = MFCR_PRESCALE_FACTOR(4,8,16), divisor_value = DLH:DLL.EFCR_FRAC + */ + for(i = 0; i <= 2; i++) + { + div = (1 << i) * uart_clock / baudrate; + frac = div & 0xf; + div >>= 4; + // Integer part of divisor value shall not be zero, otherwise, the result is invalid + if (div != 0) + break; + } + + if (i > 2) + return ARM_DRIVER_ERROR_PARAMETER; + + // Disable uart first + usart->reg->MFCR &= ~USART_MFCR_UART_EN_Msk; + + // Enable latch bit to change divisor + usart->reg->LCR |= USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + usart->reg->MFCR = ((usart->reg->MFCR & ~USART_MFCR_PRESCALE_FACTOR_Msk) | EIGEN_VAL2FLD(USART_MFCR_PRESCALE_FACTOR, i)); + usart->reg->DLL = (div >> 0) & 0xff; + usart->reg->DLH = (div >> 8) & 0xff; + usart->reg->EFCR = ((usart->reg->EFCR & ~USART_EFCR_FRAC_DIVISOR_Msk) | (frac << USART_EFCR_FRAC_DIVISOR_Pos)); + // Reset latch bit + usart->reg->LCR &= (~USART_LCR_ACCESS_DIVISOR_LATCH_Msk); + +#ifdef PM_FEATURE_ENABLE + // backup setting + g_usartDataBase[instance].backup_registers.DLL = (div >> 0) & 0xff; + g_usartDataBase[instance].backup_registers.DLH = (div >> 8) & 0xff; +#endif + } + + usart->info->baudrate = baudrate; + + return ARM_DRIVER_OK; +} + +uint32_t USART_GetBaudRate(USART_RESOURCES *usart) +{ + return usart->info->baudrate; +} + + +static void USART_DmaRxConfig(USART_RESOURCES *usart) +{ + + DmaTransferConfig_t dmaConfig; + DmaExtraConfig_t extraConfig; + + dmaConfig.addressIncrement = DMA_ADDRESS_INCREMENT_TARGET; + dmaConfig.burstSize = DMA_BURST_8_BYTES; + dmaConfig.dataWidth = DMA_DATA_WIDTH_ONE_BYTE; + dmaConfig.flowControl = DMA_FLOW_CONTROL_SOURCE; + dmaConfig.sourceAddress = (void*)&(usart->reg->RBR); + dmaConfig.targetAddress = NULL; + dmaConfig.totalLength = UART_DMA_BURST_SIZE; + + extraConfig.stopDecriptorFetch = false; + extraConfig.enableStartInterrupt = false; + extraConfig.enableEndInterrupt = true; + extraConfig.nextDesriptorAddress = &usart->dma_rx->descriptor[1]; + + DMA_buildDescriptor(&usart->dma_rx->descriptor[0], &dmaConfig, &extraConfig); + + extraConfig.stopDecriptorFetch = true; + extraConfig.nextDesriptorAddress = &usart->dma_rx->descriptor[0]; + DMA_buildDescriptor(&usart->dma_rx->descriptor[1], &dmaConfig, &extraConfig); + DMA_resetChannel(usart->dma_rx->instance, usart->dma_rx->channel); + +} + +PLAT_PA_RAMCODE static void USART_DmaUpdateRxConfig(USART_RESOURCES *usart, uint32_t targetAddress, uint32_t num) +{ + uint32_t firstDescriptorLen = MIN(num, UART_DMA_BURST_SIZE); + + usart->dma_rx->descriptor[0].TAR = targetAddress; + usart->dma_rx->descriptor[0].CMDR = DMA_setDescriptorTransferLen(usart->dma_rx->descriptor[1].CMDR, firstDescriptorLen); + + usart->dma_rx->descriptor[1].TAR = usart->dma_rx->descriptor[0].TAR + firstDescriptorLen; + usart->dma_rx->descriptor[1].CMDR = DMA_setDescriptorTransferLen(usart->dma_rx->descriptor[1].CMDR, num - firstDescriptorLen); +} + +int32_t USART_Initialize(ARM_USART_SignalEvent_t cb_event, USART_RESOURCES *usart) +{ + int32_t returnCode; +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + if (usart->info->flags & USART_FLAG_INITIALIZED) + return ARM_DRIVER_OK; + + // Pin initialize + PadConfig_t config; + PAD_getDefaultConfig(&config); + + config.mux = usart->pins.pin_tx->funcNum; + PAD_setPinConfig(usart->pins.pin_tx->pinNum, &config); + + config.pullSelect = PAD_PULL_INTERNAL; + config.pullUpEnable = PAD_PULL_UP_ENABLE; + config.pullDownEnable = PAD_PULL_DOWN_DISABLE; + config.mux = usart->pins.pin_rx->funcNum; + + PAD_setPinConfig(usart->pins.pin_rx->pinNum, &config); + + if(usart->pins.pin_cts) + { + config.mux = usart->pins.pin_cts->funcNum; + PAD_setPinConfig(usart->pins.pin_cts->pinNum, &config); + } + + if(usart->pins.pin_rts) + { + config.mux = usart->pins.pin_rts->funcNum; + PAD_setPinConfig(usart->pins.pin_rts->pinNum, &config); + } + +#ifdef PM_FEATURE_ENABLE + instance = USART_GetInstanceNumber(usart); + g_usartDataBase[instance].isInited = true; +#endif + + // Initialize USART run-time resources + usart->info->cb_event = cb_event; + memset(&(usart->info->rx_status), 0, sizeof(USART_STATUS)); + + usart->info->xfer.send_active = 0U; + usart->info->xfer.tx_def_val = 0U; + + if (usart->dma_tx) + { + returnCode = DMA_openChannel(usart->dma_tx->instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + usart->dma_tx->channel = returnCode; + + DMA_setChannelRequestSource(usart->dma_tx->instance, usart->dma_tx->channel, (DmaRequestSource_e)usart->dma_tx->request); + DMA_rigisterChannelCallback(usart->dma_tx->instance, usart->dma_tx->channel, usart->dma_tx->callback); + } + if (usart->dma_rx) + { + returnCode = DMA_openChannel(usart->dma_rx->instance); + + if (returnCode == ARM_DMA_ERROR_CHANNEL_ALLOC) + return ARM_DRIVER_ERROR; + else + usart->dma_rx->channel = returnCode; + + DMA_setChannelRequestSource(usart->dma_rx->instance, usart->dma_rx->channel, (DmaRequestSource_e)usart->dma_rx->request); + USART_DmaRxConfig(usart); + DMA_rigisterChannelCallback(usart->dma_rx->instance, usart->dma_rx->channel, usart->dma_rx->callback); + } + + usart->info->flags = USART_FLAG_INITIALIZED; // USART is initialized + +#ifdef PM_FEATURE_ENABLE + g_usartInitCounter++; + + if(g_usartInitCounter == 1) + { + g_usartWorkingStatus = 0; + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_USART_MODULE, USART_EnterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_USART_MODULE, USART_ExitLowPowerStateRestore, NULL); + } +#endif + return ARM_DRIVER_OK; +} + +int32_t USART_Uninitialize(USART_RESOURCES *usart) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; + instance = USART_GetInstanceNumber(usart); +#endif + + usart->info->flags = 0U; + usart->info->cb_event = NULL; + + if(usart->dma_tx) + { + DMA_closeChannel(usart->dma_tx->instance, usart->dma_tx->channel); + } + + if(usart->dma_rx) + { + DMA_closeChannel(usart->dma_rx->instance, usart->dma_rx->channel); + } + +#ifdef PM_FEATURE_ENABLE + + g_usartDataBase[instance].isInited = false; + + g_usartInitCounter--; + + if(g_usartInitCounter == 0) + { + g_usartWorkingStatus = 0; + slpManUnregisterPredefinedBackupCb(SLP_CALLBACK_USART_MODULE); + slpManUnregisterPredefinedRestoreCb(SLP_CALLBACK_USART_MODULE); + } +#endif + + return ARM_DRIVER_OK; +} + +int32_t USART_PowerControl(ARM_POWER_STATE state,USART_RESOURCES *usart) +{ + uint32_t instance; + uint32_t val = 0; + + instance = USART_GetInstanceNumber(usart); + + switch (state) + { + case ARM_POWER_OFF: + + // Reset USART registers + GPR_swResetModule(&g_usartResetVectors[instance]); + + // DMA disable + if(usart->dma_tx) + DMA_stopChannel(usart->dma_tx->instance, usart->dma_tx->channel, false); + if(usart->dma_rx) + DMA_stopChannel(usart->dma_rx->instance, usart->dma_rx->channel, false); + + + // Disable power to usart clock + CLOCK_clockDisable(g_uartClocks[instance*2]); + CLOCK_clockDisable(g_uartClocks[instance*2+1]); + + // Clear driver variables + memset(&(usart->info->rx_status), 0, sizeof(USART_STATUS)); + usart->info->frame_code = 0U; + usart->info->xfer.send_active = 0U; + + // Disable USART IRQ + if(usart->usart_irq) + { + XIC_ClearPendingIRQ(usart->usart_irq->irq_num); + XIC_DisableIRQ(usart->usart_irq->irq_num); + } + + usart->info->flags &= ~(USART_FLAG_POWERED | USART_FLAG_CONFIGURED); + + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if ((usart->info->flags & USART_FLAG_INITIALIZED) == 0U) + { + return ARM_DRIVER_ERROR; + } + if (usart->info->flags & USART_FLAG_POWERED) + { + return ARM_DRIVER_OK; + } + + // Enable power to usart clock + CLOCK_clockEnable(g_uartClocks[instance*2]); + CLOCK_clockEnable(g_uartClocks[instance*2+1]); + + // Disable interrupts + usart->reg->IER = 0U; + // Clear driver variables + memset(&(usart->info->rx_status), 0, sizeof(USART_STATUS)); + usart->info->frame_code = 0U; + usart->info->xfer.send_active = 0U; + + // Configure FIFO Control register + val = USART_FCR_FIFO_EN_Msk | USART_FCR_RESET_RX_FIFO_Msk | USART_FCR_RESET_TX_FIFO_Msk; + + switch(usart->rx_fifo_trig_lvl) + { + case RX_FIFO_TRIG_LVL_8BYTE: + val |= (1U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + break; + + case RX_FIFO_TRIG_LVL_16BYTE: + val |= (2U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + break; + + case RX_FIFO_TRIG_LVL_30BYTE: + val |= (3U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + break; + default: + break; + } + + switch(usart->tx_fifo_trig_lvl) + { + case TX_FIFO_TRIG_LVL_2BYTE: + val |= (1U << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos); + break; + + case TX_FIFO_TRIG_LVL_8BYTE: + val |= (2U << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos); + break; + + case TX_FIFO_TRIG_LVL_16BYTE: + val |= (3U << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos); + break; + default: + break; + } + + usart->reg->FCR = val; + +#ifdef PM_FEATURE_ENABLE + g_usartDataBase[instance].backup_registers.FCR = val; +#endif + + if(usart->dma_tx || usart->dma_rx || usart->is_unilog_mode == 1) + { + usart->reg->MFCR |= USART_MFCR_DMA_EN_Msk; + } + + if(usart->usart_irq) + { + XIC_SetVector(usart->usart_irq->irq_num, usart->usart_irq->cb_irq); + XIC_EnableIRQ(usart->usart_irq->irq_num); + XIC_SuppressOvfIRQ(usart->usart_irq->irq_num); + } + usart->info->flags |= USART_FLAG_POWERED; // USART is powered on + + break; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +int32_t USART_Send(const void *data, uint32_t num, USART_RESOURCES *usart) +{ + uint32_t mask; +#ifdef PM_FEATURE_ENABLE + uint32_t instance = USART_GetInstanceNumber(usart); +#endif + + if ((data == NULL) || (num == 0U)) + return ARM_DRIVER_ERROR_PARAMETER; + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) + return ARM_DRIVER_ERROR; + +#ifdef PM_FEATURE_ENABLE + if(usart->reg->MCR == 0x10) + { + return ARM_DRIVER_OK; + } + + if((usart->reg->ADCR & USART_ADCR_AUTO_BAUD_INT_EN_Msk) && (g_usartDataBase[instance].autoBaudRateDone == false)) + { + if(usart->info->cb_event && usart->dma_tx) + { + usart->info->cb_event(ARM_USART_EVENT_SEND_COMPLETE); + } + + return ARM_DRIVER_OK; + } +#endif + + mask = SaveAndSetIRQMask(); + if (usart->info->xfer.send_active != 0) + { + RestoreIRQMask(mask); + return ARM_DRIVER_ERROR_BUSY; + } + + usart->info->xfer.send_active = 1U; + RestoreIRQMask(mask); + + + // Save transmit buffer info + usart->info->xfer.tx_buf = (uint8_t *)data; + usart->info->xfer.tx_num = num; + usart->info->xfer.tx_cnt = 0U; + // DMA mode + if(usart->dma_tx) + { +#if 0 + // wait until tx is empty + while((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0); +#else + // relax the constraint + while(EIGEN_FLD2VAL(USART_FCNR_TX_FIFO_NUM, usart->reg->FCNR) > 16); +#endif + +#ifdef PM_FEATURE_ENABLE + mask = SaveAndSetIRQMask(); + + LOCK_SLEEP(instance, 1, 0); + + RestoreIRQMask(mask); +#endif + + if(num == 1) + { + mask = SaveAndSetIRQMask(); + + usart->reg->IER |= USART_IER_TX_DATA_REQ_Msk; + + usart->reg->THR = usart->info->xfer.tx_buf[0]; + + RestoreIRQMask(mask); + } + else + { + dmaTxConfig.sourceAddress = (void*)data; + dmaTxConfig.targetAddress = (void*)&(usart->reg->THR); + dmaTxConfig.totalLength = num-1; + + // Configure tx DMA and start it + DMA_transferSetup(usart->dma_tx->instance, usart->dma_tx->channel, &dmaTxConfig); + DMA_enableChannelInterrupts(usart->dma_tx->instance, usart->dma_tx->channel, DMA_END_INTERRUPT_ENABLE); + DMA_startChannel(usart->dma_tx->instance, usart->dma_tx->channel); + } + + } + else + { + while (usart->info->xfer.tx_cnt < usart->info->xfer.tx_num) + { + // wait until tx is empty + while((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_cnt++]; + } + while((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + mask = SaveAndSetIRQMask(); + usart->info->xfer.send_active = 0U; + RestoreIRQMask(mask); + } + + return ARM_DRIVER_OK; +} + + +int32_t USART_SendPolling(const void *data, uint32_t num, USART_RESOURCES *usart) +{ + uint32_t mask; +#ifdef PM_FEATURE_ENABLE + uint32_t instance = USART_GetInstanceNumber(usart); +#endif + + if ((data == NULL) || (num == 0U)) + return ARM_DRIVER_ERROR_PARAMETER; + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) + return ARM_DRIVER_ERROR; + +#ifdef PM_FEATURE_ENABLE + if(usart->reg->MCR == 0x10) + { + return ARM_DRIVER_OK; + } + + if((usart->reg->ADCR & USART_ADCR_AUTO_BAUD_INT_EN_Msk) && (g_usartDataBase[instance].autoBaudRateDone == false)) + { + return ARM_DRIVER_OK; + } +#endif + + mask = SaveAndSetIRQMask(); + if (usart->info->xfer.send_active != 0) + { + RestoreIRQMask(mask); + return ARM_DRIVER_ERROR_BUSY; + } + + usart->info->xfer.send_active = 1U; + RestoreIRQMask(mask); + + // Save transmit buffer info + usart->info->xfer.tx_buf = (uint8_t *)data; + usart->info->xfer.tx_num = num; + usart->info->xfer.tx_cnt = 0U; + + while (usart->info->xfer.tx_cnt < usart->info->xfer.tx_num) + { + // wait until tx is empty + while((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_cnt++]; + } + while((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + + mask = SaveAndSetIRQMask(); + usart->info->xfer.send_active = 0U; + RestoreIRQMask(mask); + + return ARM_DRIVER_OK; +} + +PLAT_PA_RAMCODE int32_t USART_Receive(void *data, uint32_t num, USART_RESOURCES *usart) +{ + uint32_t bytes_in_fifo, i; + + volatile uint32_t left_to_recv = num; + + if ((data == NULL) || num == 0U) + { + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) + { + return ARM_DRIVER_ERROR; + } + + // check if receiver is busy + if (usart->info->rx_status.rx_busy == 1U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + // save num of data to be received + usart->info->xfer.rx_num = num; + usart->info->xfer.rx_buf = (uint8_t *)data; + usart->info->xfer.rx_cnt = 0U; + + usart->reg->IER |= USART_IER_RX_LINE_STATUS_Msk; + + // prepare in advance for dma recv + if(usart->dma_rx) + { + usart->info->rx_status.rx_dma_triggered = 0; + + USART_DmaUpdateRxConfig(usart, (uint32_t)data, num); + } + + usart->info->rx_status.rx_busy = 1U; + + // Lucky :), we have bytes waiting, try our best to receive all of them, however, let normal recv process handle the case if new data keeps arriving + while((bytes_in_fifo = EIGEN_FLD2VAL(USART_FCNR_RX_FIFO_NUM, usart->reg->FCNR)) > 0) + { + + if(usart->reg->LSR & USART_LSR_RX_BUSY_Msk) + { + break; + } + + left_to_recv = num - usart->info->xfer.rx_cnt; + + i = MIN(bytes_in_fifo, left_to_recv); + + while(i--) + { + usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt++] = usart->reg->RBR; + } + + left_to_recv = num - usart->info->xfer.rx_cnt; + + // prepare in advance for dma recv + if(usart->dma_rx) + { + USART_DmaUpdateRxConfig(usart, (uint32_t)&usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt], left_to_recv); + } + + if(left_to_recv == 0) + { + // Full + usart->info->rx_status.rx_busy = 0; + + usart->reg->IER &= ~USART_IER_RX_LINE_STATUS_Msk; + + if(usart->info->cb_event != NULL) + { + usart->info->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + + return ARM_DRIVER_OK; + + } + + // check again whether there's ongoing data stream + if(usart->reg->LSR & USART_LSR_RX_BUSY_Msk) + { + break; + } + + } + + // need to add protection to check rxfifo in irqHandler for 'fake' timeout, that's caused by + // we have try to receive bytes from rxfifo as many as possible so when timeout occurs, there maybe no bytes left in rxfifo + if(usart->dma_rx) + { + usart->reg->IER |= USART_IER_RX_TIMEOUT_Msk; + + DMA_loadChannelDescriptorAndRun(usart->dma_rx->instance, usart->dma_rx->channel, &usart->dma_rx->descriptor[0]); + + if(usart->info->xfer.rx_cnt != 0) + { + if(usart->reg->LSR & USART_LSR_RX_BUSY_Msk) + { + // do nothing if there's still data coming since we can let isr report later + } + else + { + // report to upper layer that we've received some data + usart->info->rx_status.rx_busy = 0; + + // rx_busy is not reliable flag since it'll change to 0 on stop bit + // so it's possible here to break the continuous rx data steam into two parts + if(usart->info->cb_event != NULL) + { + usart->info->cb_event(ARM_USART_EVENT_RX_TIMEOUT); + } + } + + } + } + else if(usart->usart_irq) + { + usart->reg->IER |= USART_IER_RX_TIMEOUT_Msk | \ + USART_IER_RX_DATA_REQ_Msk ; + + if(usart->info->xfer.rx_cnt != 0) + { + if(usart->reg->LSR & USART_LSR_RX_BUSY_Msk) + { + // do nothing if there's still data coming since we can let isr report later + } + else + { + // report to upper layer that we've received some data + usart->info->rx_status.rx_busy = 0; + + // rx_busy is not reliable flag since it'll change to 0 on stop bit + // so it's possible here to break the continuous rx data steam into two parts + if(usart->info->cb_event != NULL) + { + usart->info->cb_event(ARM_USART_EVENT_RX_TIMEOUT); + } + } + + } + } + else + { + while(usart->info->xfer.rx_cnt < usart->info->xfer.rx_num) + { + //wait unitl receive data is ready + while((usart->reg->LSR & USART_LSR_RX_DATA_READY_Msk) == 0); + //read data + usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt++] = usart->reg->RBR; + } + usart->info->rx_status.rx_busy = 0U; + } + return ARM_DRIVER_OK; +} + +int32_t USART_Transfer(const void *data_out, void *data_in, uint32_t num,USART_RESOURCES *usart) +{ + //maybe used by command transfer + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +int32_t USART_GetTxCount(USART_RESOURCES *usart) +{ + uint32_t cnt; + if (!(usart->info->flags & USART_FLAG_CONFIGURED)) + return 0U; + if(usart->dma_tx) + cnt = DMA_getChannelCount(usart->dma_tx->instance, usart->dma_tx->channel); + else + cnt = usart->info->xfer.tx_cnt; + return cnt; +} + +PLAT_PA_RAMCODE int32_t USART_GetRxCount(USART_RESOURCES *usart) +{ + if (!(usart->info->flags & USART_FLAG_CONFIGURED)) + return 0U; + return usart->info->xfer.rx_cnt; +} + +int32_t USART_Control(uint32_t control, uint32_t arg, USART_RESOURCES *usart) +{ + uint32_t val, mfcr, mask; + uint8_t lcr = usart->reg->LCR; + + switch (control & ARM_USART_CONTROL_Msk) + { + // Control TX + case ARM_USART_CONTROL_TX: + return ARM_DRIVER_OK; + // Control RX + case ARM_USART_CONTROL_RX: + // Not recommend to use this feature + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) + { + return ARM_DRIVER_ERROR; + } + + // Only support disable RX + if(!arg) + { + // What we can do now is just to suppress irqs since we have no solo control bit to disable RX + + mask = SaveAndSetIRQMask(); + + if(usart->dma_rx) + { + + usart->reg->IER &= ~(USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + usart->info->rx_status.rx_dma_triggered = 0; + DMA_stopChannelNoWait(usart->dma_rx->instance, usart->dma_rx->channel); + } + else if(usart->usart_irq) + { + usart->reg->IER &= ~(USART_IER_RX_TIMEOUT_Msk | \ + USART_IER_RX_DATA_REQ_Msk | \ + USART_IER_RX_LINE_STATUS_Msk); + } + + usart->reg->ICR = USART_ICR_RX_DATA_REQ_Msk | \ + USART_ICR_RX_TIMEOUT_Msk | \ + USART_ICR_RX_LINE_STATUS_Msk; + + usart->info->rx_status.rx_busy = 0; + + RestoreIRQMask(mask); + return ARM_DRIVER_OK; + } + else + { + // Not support, call receive instead + return ARM_DRIVER_OK; + } + // Control break + case ARM_USART_CONTROL_BREAK: + return ARM_DRIVER_ERROR_UNSUPPORTED; + // Abort Send + case ARM_USART_ABORT_SEND: + return ARM_DRIVER_ERROR_UNSUPPORTED; + // Abort receive + case ARM_USART_ABORT_RECEIVE: + return ARM_DRIVER_ERROR_UNSUPPORTED; + // Abort transfer + case ARM_USART_ABORT_TRANSFER: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_USART_MODE_ASYNCHRONOUS: + break; + // Flush TX fifo + case ARM_USART_CONTROL_FLUSH_TX: + + if(usart->reg->MFCR & USART_MFCR_AUTO_FLOW_CTS_EN_Msk) + { + while(((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0) && ((usart->reg->MSR & USART_MSR_CTS_Msk) == USART_MSR_CTS_Msk)); + } + else + { + while((usart->reg->LSR & USART_LSR_TX_EMPTY_Msk) == 0); + } + return ARM_DRIVER_OK; + + case ARM_USART_CONTROL_PURGE_COMM: + + mfcr = usart->reg->MFCR; + usart->reg->MFCR = 0; + + // reconfigure FIFO Control register + val = USART_FCR_FIFO_EN_Msk | USART_FCR_RESET_RX_FIFO_Msk | USART_FCR_RESET_TX_FIFO_Msk; + + switch(usart->rx_fifo_trig_lvl) + { + case RX_FIFO_TRIG_LVL_8BYTE: + val |= (1U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + break; + + case RX_FIFO_TRIG_LVL_16BYTE: + val |= (2U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + break; + + case RX_FIFO_TRIG_LVL_30BYTE: + val |= (3U << USART_FCR_RX_FIFO_AVAIL_TRIG_LEVEL_Pos); + break; + default: + break; + } + + switch(usart->tx_fifo_trig_lvl) + { + case TX_FIFO_TRIG_LVL_2BYTE: + val |= (1U << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos); + break; + + case TX_FIFO_TRIG_LVL_8BYTE: + val |= (2U << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos); + break; + + case TX_FIFO_TRIG_LVL_16BYTE: + val |= (3U << USART_FCR_TX_FIFO_EMPTY_TRIG_LEVEL_Pos); + break; + default: + break; + } + + usart->reg->FCR = val; + usart->reg->MFCR = mfcr; + + return ARM_DRIVER_OK; + + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_DATA_BITS_Msk) + { + case ARM_USART_DATA_BITS_5: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + break; + case ARM_USART_DATA_BITS_6: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + lcr |= 1U; + break; + case ARM_USART_DATA_BITS_7: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + lcr |= 2U; + break; + case ARM_USART_DATA_BITS_8: + lcr &= ~USART_LCR_CHAR_LEN_Msk; + lcr |= 3U; + break; + default: + return ARM_USART_ERROR_DATA_BITS; + } + + // USART Parity + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + lcr &= ~USART_LCR_PARITY_EN_Msk; + break; + case ARM_USART_PARITY_EVEN: + lcr |= (USART_LCR_PARITY_EN_Msk | USART_LCR_EVEN_PARITY_Msk); + break; + case ARM_USART_PARITY_ODD: + lcr |= USART_LCR_PARITY_EN_Msk; + lcr &= ~USART_LCR_EVEN_PARITY_Msk; + break; + default: + return (ARM_USART_ERROR_PARITY); + } + + // USART Stop bits + switch (control & ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + lcr &=~ USART_LCR_STOP_BIT_NUM_Msk; + break; + case ARM_USART_STOP_BITS_1_5: + if ((control & ARM_USART_DATA_BITS_Msk) == ARM_USART_DATA_BITS_5) + { + lcr |= USART_LCR_STOP_BIT_NUM_Msk; + break; + } + else + return ARM_USART_ERROR_STOP_BITS; + case ARM_USART_STOP_BITS_2: + lcr |= USART_LCR_STOP_BIT_NUM_Msk; + break; + default: + return ARM_USART_ERROR_STOP_BITS; + } + + // USART Flow Control + switch (control & ARM_USART_FLOW_CONTROL_Msk) + { + case ARM_USART_FLOW_CONTROL_NONE: + usart->reg->MFCR &= ~(USART_MFCR_AUTO_FLOW_RTS_EN_Msk | USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + case ARM_USART_FLOW_CONTROL_RTS: + usart->reg->MCR |= USART_MCR_RTS_Msk; //activate rts, put rts pin to low level + usart->reg->MFCR &= ~(USART_MFCR_AUTO_FLOW_RTS_EN_Msk | USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + case ARM_USART_FLOW_CONTROL_CTS: + usart->reg->MFCR |= (USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + case ARM_USART_FLOW_CONTROL_RTS_CTS: + usart->reg->MCR |= USART_MCR_RTS_Msk; //activate rts, put rts pin to low level + usart->reg->MFCR |= (USART_MFCR_AUTO_FLOW_CTS_EN_Msk); + break; + } + // USART Baudrate + if(ARM_DRIVER_OK != USART_SetBaudrate (arg, usart)) + return ARM_USART_ERROR_BAUDRATE; + + // Configuration is OK - frame code is valid + usart->info->frame_code = control; + + usart->reg->LCR = lcr; + // usart enable + usart->reg->MFCR |= USART_MFCR_UART_EN_Msk; + + usart->info->flags |= USART_FLAG_CONFIGURED; + return ARM_DRIVER_OK; +} + +ARM_USART_STATUS USART_GetStatus(USART_RESOURCES *usart) +{ + ARM_USART_STATUS status; + + status.tx_busy = usart->info->xfer.send_active; + status.rx_busy = usart->info->rx_status.rx_busy; + status.tx_underflow = 0U; + status.rx_overflow = usart->info->rx_status.rx_overflow; + status.rx_break = usart->info->rx_status.rx_break; + status.rx_framing_error = usart->info->rx_status.rx_framing_error; + status.rx_parity_error = usart->info->rx_status.rx_parity_error; + status.is_send_block = (usart->dma_tx == NULL); + return status; +} + + +/* +if not enable FC via AT+IFC, RTS default is high level +if peer enbale CTS, it could send data +if enable FC via AT+IFC, set RTS to low level when init, allow peer to send + +*/ +int32_t USART_SetModemControl(ARM_USART_MODEM_CONTROL control,USART_RESOURCES *usart) +{ + if((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) + { + // USART is not configured + return ARM_DRIVER_ERROR; + } + + if(usart->info->frame_code & ARM_USART_FLOW_CONTROL_RTS) + { + if(control == ARM_USART_RTS_CLEAR) //Deactivate RTS, put rts pin to high level + { + usart->reg->MCR &= ~USART_MCR_RTS_Msk; + } + + if(control == ARM_USART_RTS_SET) //Activate RTS, put rts pin to low level + { + usart->reg->MCR |= USART_MCR_RTS_Msk; + } + + } + + if(control == ARM_USART_DTR_CLEAR) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + if(control == ARM_USART_DTR_SET) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; + +} + +ARM_USART_MODEM_STATUS USART_GetModemStatus(USART_RESOURCES *usart) +{ + ARM_USART_MODEM_STATUS status = {0}; + + if(usart->info->flags & USART_FLAG_CONFIGURED) + { + status.cts = EIGEN_FLD2VAL(USART_MSR_CTS, usart->reg->MSR); + } + + return status; +} + +PLAT_PA_RAMCODE void USART_IRQHandler (USART_RESOURCES *usart) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance; +#endif + + uint32_t i; + uint32_t event = 0; + uint32_t lsr_reg, isr_reg; + uint32_t current_cnt, total_cnt, left_to_recv, bytes_in_fifo; + + USART_INFO *info = usart->info; + +#ifdef PM_FEATURE_ENABLE + instance = USART_GetInstanceNumber(usart); +#endif + // Check interrupt source + isr_reg = usart->reg->ISR; + usart->reg->ICR = isr_reg; + usart->reg->ICR = 0; + +#ifdef PM_FEATURE_ENABLE +#if USART_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, USART_IRQHandler_0, P_DEBUG, "isr:0x%x, fcnr_reg:0x%x, rx_cnt:%d",isr_reg, usart->reg->FCNR, info->xfer.rx_cnt); +#endif + +#endif + + if((isr_reg & USART_ISR_RX_LINE_STATUS_Msk) == USART_ISR_RX_LINE_STATUS_Msk) + { + lsr_reg = usart->reg->LSR; + + if (lsr_reg & USART_LSR_RX_OVERRUN_ERROR_Msk) + { + info->rx_status.rx_overflow = 1U; + event |= ARM_USART_EVENT_RX_OVERFLOW; + } + + // Parity error + if (lsr_reg & USART_LSR_RX_PARITY_ERROR_Msk) + { + info->rx_status.rx_parity_error= 1U; + event |= ARM_USART_EVENT_RX_PARITY_ERROR; + } + // Break detected + if (lsr_reg & USART_LSR_RX_BREAK_Msk) + { + info->rx_status.rx_break= 1U; + event |= ARM_USART_EVENT_RX_BREAK; + } + // Framing error + if (lsr_reg & USART_LSR_RX_FRAME_ERROR_Msk) + { + info->rx_status.rx_framing_error= 1U; + event |= ARM_USART_EVENT_RX_FRAMING_ERROR; + } + + info->rx_status.rx_busy = 0; +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance, 0, 1); +#endif + + } + else if((isr_reg & USART_ISR_RX_TIMEOUT_Msk) == USART_ISR_RX_TIMEOUT_Msk) + { +#ifdef PM_FEATURE_ENABLE + + if(usart->reg->ADCR & USART_ADCR_AUTO_BAUD_INT_EN_Msk) + { + uint32_t adrr_reg = usart->reg->ADRR; + usart->reg->MFCR &= ~USART_MFCR_UART_EN_Msk; + usart->reg->LCR |= USART_LCR_ACCESS_DIVISOR_LATCH_Msk; + usart->reg->MFCR = ((usart->reg->MFCR & ~USART_MFCR_PRESCALE_FACTOR_Msk) | EIGEN_VAL2FLD(USART_MFCR_PRESCALE_FACTOR, 0)); + usart->reg->DLL = ((adrr_reg & USART_ADRR_AUTO_BAUD_INTE_Msk) >> 4) & 0xff; + usart->reg->DLH = ((adrr_reg & USART_ADRR_AUTO_BAUD_INTE_Msk) >> 12) & 0xff; + usart->reg->EFCR = ((usart->reg->EFCR & ~USART_EFCR_FRAC_DIVISOR_Msk) | ((adrr_reg >> USART_ADRR_AUTO_BAUD_FRAC_Pos) << USART_EFCR_FRAC_DIVISOR_Pos)); + usart->reg->LCR &= (~USART_LCR_ACCESS_DIVISOR_LATCH_Msk); + usart->reg->ADCR = 0; + usart->reg->MFCR |= USART_MFCR_UART_EN_Msk; + + usart->reg->FCR = g_usartDataBase[instance].backup_registers.FCR; + + g_usartDataBase[instance].autoBaudRateDone = true; + // backup setting + g_usartDataBase[instance].backup_registers.DLL = ((adrr_reg & USART_ADRR_AUTO_BAUD_INTE_Msk) >> 4) & 0xff; + g_usartDataBase[instance].backup_registers.DLH = ((adrr_reg & USART_ADRR_AUTO_BAUD_INTE_Msk) >> 12) & 0xff; + + event = ARM_USART_EVENT_AUTO_BAUDRATE_DONE; + + if(adrr_reg != 0) + { + usart->info->baudrate = GPR_getClockFreq(g_uartClocks[instance*2+1]) / (adrr_reg & USART_ADRR_AUTO_BAUD_INTE_Msk); + } + else + { + usart->info->baudrate = 0; + } + } + else +#endif + { + // refer to receive API for this check + if(usart->reg->FCNR >> USART_FCNR_RX_FIFO_NUM_Pos) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance, 0, 1); +#endif + info->rx_status.rx_busy = 1U; + + current_cnt = info->xfer.rx_cnt; + + if(usart->dma_rx) + { + if(usart->info->rx_status.rx_dma_triggered) + { + // Sync with undergoing DMA transfer, wait until DMA burst transfer(8 bytes) done and update current_cnt + do + { + current_cnt = DMA_getChannelCurrentTargetAddress(usart->dma_rx->instance, usart->dma_rx->channel, true) - (uint32_t)info->xfer.rx_buf; +#if USART_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, USART_IRQHandler_1, P_INFO, "dma transfer done, cnt:%d", current_cnt); +#endif + } while(((current_cnt - info->xfer.rx_cnt) & (UART_DMA_BURST_SIZE - 1)) != 0); + + usart->info->rx_status.rx_dma_triggered = 0; + + } + /* + No matter DMA transfer is started or not(left recv buffer space is not enough), + now we can stop DMA saftely for next transfer and handle tailing bytes in FIFO + */ + DMA_stopChannelNoWait(usart->dma_rx->instance, usart->dma_rx->channel); + } + + total_cnt = info->xfer.rx_num; + + bytes_in_fifo = usart->reg->FCNR >> USART_FCNR_RX_FIFO_NUM_Pos; + + left_to_recv = total_cnt - current_cnt; + + i = MIN(bytes_in_fifo, left_to_recv); + + // if still have space to recv + if(left_to_recv > 0) + { + while(i--) + { + info->xfer.rx_buf[current_cnt++] = usart->reg->RBR; + } + } + + info->xfer.rx_cnt = current_cnt; + + // Check if required amount of data is received + if (current_cnt == total_cnt) + { + // Clear RX busy flag and set receive transfer complete event + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + + //Disable RDA interrupt + usart->reg->IER &= ~(USART_IER_RX_DATA_REQ_Msk | USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + } + else + { + event |= ARM_USART_EVENT_RX_TIMEOUT; + + if(usart->dma_rx) + { + // Prepare for next recv + left_to_recv = total_cnt - info->xfer.rx_cnt; + + USART_DmaUpdateRxConfig(usart, (uint32_t)info->xfer.rx_buf + info->xfer.rx_cnt, left_to_recv); + + // load descriptor and start DMA transfer + DMA_loadChannelDescriptorAndRun(usart->dma_rx->instance, usart->dma_rx->channel, &usart->dma_rx->descriptor[0]); + + } + + } + + info->rx_status.rx_busy = 0U; + + } + + + } + + } + else if((isr_reg & USART_ISR_RX_DATA_REQ_Msk) == USART_ISR_RX_DATA_REQ_Msk) + { +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance, 0, 1); +#endif + info->rx_status.rx_busy = 1U; + + current_cnt = info->xfer.rx_cnt; + total_cnt = info->xfer.rx_num; + + left_to_recv = total_cnt - current_cnt; + + bytes_in_fifo = usart->reg->FCNR >> USART_FCNR_RX_FIFO_NUM_Pos; + + // leave at least one byte in fifo to trigger timeout interrupt + i = bytes_in_fifo - 1; + + if(i == 0) + i = 1; + + i = MIN(i, left_to_recv); + + while(i--) + { + info->xfer.rx_buf[current_cnt++] = usart->reg->RBR; + } + + info->xfer.rx_cnt = current_cnt; + + if(current_cnt == total_cnt) + { + // Clear RX busy flag and set receive transfer complete event + event |= ARM_USART_EVENT_RECEIVE_COMPLETE; + + //Disable RDA interrupt + usart->reg->IER &= ~(USART_IER_RX_DATA_REQ_Msk | USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + + info->rx_status.rx_busy = 0U; + } + } + + if(((isr_reg & USART_ISR_TX_DATA_REQ_Msk) == USART_ISR_TX_DATA_REQ_Msk) || \ + ((usart->reg->IER & USART_IER_TX_DATA_REQ_Msk) && ((usart->reg->FCNR & USART_FCNR_TX_FIFO_NUM_Msk) == 0))) + { + info->xfer.tx_cnt = info->xfer.tx_num; + info->xfer.send_active = 0U; + event |= ARM_USART_EVENT_SEND_COMPLETE; + usart->reg->IER &= ~USART_IER_TX_DATA_REQ_Msk; + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance, 1, 0); +#endif + } + + + if ((info->cb_event != NULL) && (event != 0U)) + { + info->cb_event (event); + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance, 0, 1); +#endif + + } +} + +/** + \fn void USART_DmaTxEvent(uint32_t event, USART_RESOURCES *usart) + \brief USART DMA Tx Event handler. + \param[in] event DMA Tx Event + \param[in] usart Pointer to USART resources +*/ +void USART_DmaTxEvent(uint32_t event, USART_RESOURCES *usart) +{ + switch (event) + { + case DMA_EVENT_END: + // TXFIFO may still have data not sent out + usart->reg->IER |= USART_IER_TX_DATA_REQ_Msk; + usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_num-1]; + + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + +void USART_DmaRxEvent(uint32_t event, USART_RESOURCES *usart) +{ +#ifdef PM_FEATURE_ENABLE + uint32_t instance = USART_GetInstanceNumber(usart); +#endif + + uint32_t dmaCurrentTargetAddress = DMA_getChannelCurrentTargetAddress(usart->dma_rx->instance, usart->dma_rx->channel, false); + + switch (event) + { + case DMA_EVENT_END: + +#if USART_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, USART_DmaRxEvent_0, P_INFO, "uart dma rx event, fcnr:%x, cnt:%d", usart->reg->FCNR, dmaCurrentTargetAddress - (uint32_t)usart->info->xfer.rx_buf); +#endif + +#ifdef PM_FEATURE_ENABLE + LOCK_SLEEP(instance, 0, 1); +#endif + usart->info->rx_status.rx_busy = 1U; + usart->info->rx_status.rx_dma_triggered = 1; + + if(dmaCurrentTargetAddress == ( (uint32_t)usart->info->xfer.rx_buf + usart->info->xfer.rx_num)) + { +#if USART_DEBUG + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, USART_DmaRxEvent_1, P_INFO,"uart dma rx complete"); +#endif + usart->info->xfer.rx_cnt = usart->info->xfer.rx_num; + + //Disable all recv interrupt + usart->reg->IER &= ~(USART_IER_RX_DATA_REQ_Msk | USART_IER_RX_TIMEOUT_Msk | USART_IER_RX_LINE_STATUS_Msk); + usart->info->rx_status.rx_busy = 0; + usart->info->rx_status.rx_dma_triggered = 0; + + if(usart->info->cb_event) + { + usart->info->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + +#ifdef PM_FEATURE_ENABLE + CHECK_TO_UNLOCK_SLEEP(instance, 0, 1); +#endif + } + + break; + case DMA_EVENT_ERROR: + default: + break; + } +} + + +#if (RTE_UART0) +// End USART Interface +static ARM_USART_CAPABILITIES USART0_GetCapabilities (void) { return USART_GetCapabilities (&USART0_Resources); } +static int32_t USART0_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART0_Resources); } +static int32_t USART0_Uninitialize (void) { return USART_Uninitialize (&USART0_Resources); } +static int32_t USART0_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART0_Resources); } +static int32_t USART0_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART0_Resources); } +static int32_t USART0_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART0_Resources); } +static int32_t USART0_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART0_Resources); } +static int32_t USART0_SendPolling (const void *data, uint32_t num) { return USART_SendPolling (data, num, &USART0_Resources); } +static uint32_t USART0_GetTxCount (void) { return USART_GetTxCount (&USART0_Resources); } +PLAT_PA_RAMCODE static uint32_t USART0_GetRxCount (void) { return USART_GetRxCount (&USART0_Resources); } +static uint32_t USART0_GetBaudRate (void) { return USART_GetBaudRate (&USART0_Resources); } +static int32_t USART0_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART0_Resources); } +static ARM_USART_STATUS USART0_GetStatus (void) { return USART_GetStatus (&USART0_Resources); } +static int32_t USART0_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART0_Resources); } +static ARM_USART_MODEM_STATUS USART0_GetModemStatus (void) { return USART_GetModemStatus (&USART0_Resources); } +PLAT_PA_RAMCODE void USART0_IRQHandler (void) { USART_IRQHandler (&USART0_Resources); } + +#if (RTE_UART0_TX_IO_MODE == DMA_MODE) + void USART0_DmaTxEvent(uint32_t event) { USART_DmaTxEvent(event, &USART0_Resources);} +#endif + +#if (RTE_UART0_RX_IO_MODE == DMA_MODE) + void USART0_DmaRxEvent(uint32_t event) { USART_DmaRxEvent(event, &USART0_Resources);} +#endif + +ARM_DRIVER_USART Driver_USART0 = { + ARM_USART_GetVersion, + USART0_GetCapabilities, + USART0_Initialize, + USART0_Uninitialize, + USART0_PowerControl, + USART0_Send, + USART0_Receive, + USART0_Transfer, + USART0_GetTxCount, + USART0_GetRxCount, + USART0_Control, + USART0_GetStatus, + USART0_SetModemControl, + USART0_GetModemStatus, + USART0_GetBaudRate, + USART0_SendPolling +}; + +#endif + +#if (RTE_UART1) +static ARM_USART_CAPABILITIES USART1_GetCapabilities (void) { return USART_GetCapabilities (&USART1_Resources); } +static int32_t USART1_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART1_Resources); } +static int32_t USART1_Uninitialize (void) { return USART_Uninitialize (&USART1_Resources); } +static int32_t USART1_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART1_Resources); } +static int32_t USART1_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART1_Resources); } +static int32_t USART1_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART1_Resources); } +static int32_t USART1_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART1_Resources); } +static int32_t USART1_SendPolling (const void *data, uint32_t num) { return USART_SendPolling (data, num, &USART1_Resources); } +static uint32_t USART1_GetTxCount (void) { return USART_GetTxCount (&USART1_Resources); } +PLAT_PA_RAMCODE static uint32_t USART1_GetRxCount (void) { return USART_GetRxCount (&USART1_Resources); } +static uint32_t USART1_GetBaudRate (void) { return USART_GetBaudRate (&USART1_Resources); } +static int32_t USART1_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART1_Resources); } +static ARM_USART_STATUS USART1_GetStatus (void) { return USART_GetStatus (&USART1_Resources); } +static int32_t USART1_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART1_Resources); } +static ARM_USART_MODEM_STATUS USART1_GetModemStatus (void) { return USART_GetModemStatus (&USART1_Resources); } +PLAT_PA_RAMCODE void USART1_IRQHandler (void) { USART_IRQHandler (&USART1_Resources); } + +#if (RTE_UART1_TX_IO_MODE == DMA_MODE) + void USART1_DmaTxEvent(uint32_t event) { USART_DmaTxEvent(event, &USART1_Resources);} +#endif + +#if (RTE_UART1_RX_IO_MODE == DMA_MODE) + void USART1_DmaRxEvent(uint32_t event) { USART_DmaRxEvent(event, &USART1_Resources);} +#endif + + +ARM_DRIVER_USART Driver_USART1 = { + ARM_USART_GetVersion, + USART1_GetCapabilities, + USART1_Initialize, + USART1_Uninitialize, + USART1_PowerControl, + USART1_Send, + USART1_Receive, + USART1_Transfer, + USART1_GetTxCount, + USART1_GetRxCount, + USART1_Control, + USART1_GetStatus, + USART1_SetModemControl, + USART1_GetModemStatus, + USART1_GetBaudRate, + USART1_SendPolling +}; + +#endif + +#if (RTE_UART2) +static ARM_USART_CAPABILITIES USART2_GetCapabilities (void) { return USART_GetCapabilities (&USART2_Resources); } +static int32_t USART2_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART2_Resources); } +static int32_t USART2_Uninitialize (void) { return USART_Uninitialize (&USART2_Resources); } +static int32_t USART2_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART2_Resources); } +static int32_t USART2_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART2_Resources); } +static int32_t USART2_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART2_Resources); } +static int32_t USART2_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART2_Resources); } +static int32_t USART2_SendPolling (const void *data, uint32_t num) { return USART_SendPolling (data, num, &USART2_Resources); } +static uint32_t USART2_GetTxCount (void) { return USART_GetTxCount (&USART2_Resources); } +PLAT_PA_RAMCODE static uint32_t USART2_GetRxCount (void) { return USART_GetRxCount (&USART2_Resources); } +static uint32_t USART2_GetBaudRate (void) { return USART_GetBaudRate (&USART2_Resources); } +static int32_t USART2_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART2_Resources); } +static ARM_USART_STATUS USART2_GetStatus (void) { return USART_GetStatus (&USART2_Resources); } +static int32_t USART2_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART2_Resources); } +static ARM_USART_MODEM_STATUS USART2_GetModemStatus (void) { return USART_GetModemStatus (&USART2_Resources); } +PLAT_PA_RAMCODE void USART2_IRQHandler (void) { USART_IRQHandler (&USART2_Resources); } + +#if (RTE_UART2_TX_IO_MODE == DMA_MODE) + void USART2_DmaTxEvent(uint32_t event) { USART_DmaTxEvent(event, &USART2_Resources);} +#endif + +#if (RTE_UART2_RX_IO_MODE == DMA_MODE) + void USART2_DmaRxEvent(uint32_t event) { USART_DmaRxEvent(event, &USART2_Resources);} +#endif + + +ARM_DRIVER_USART Driver_USART2 = { + ARM_USART_GetVersion, + USART2_GetCapabilities, + USART2_Initialize, + USART2_Uninitialize, + USART2_PowerControl, + USART2_Send, + USART2_Receive, + USART2_Transfer, + USART2_GetTxCount, + USART2_GetRxCount, + USART2_Control, + USART2_GetStatus, + USART2_SetModemControl, + USART2_GetModemStatus, + USART2_GetBaudRate, + USART2_SendPolling +}; + +#endif + + diff --git a/PLAT/driver/chip/ec618/common/gcc/memcpy-armv7m.S b/PLAT/driver/chip/ec618/common/gcc/memcpy-armv7m.S new file mode 100644 index 0000000..c8bff36 --- /dev/null +++ b/PLAT/driver/chip/ec618/common/gcc/memcpy-armv7m.S @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2013 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* This memcpy routine is optimised for Cortex-M3/M4 cores with/without + unaligned access. + + If compiled with GCC, this file should be enclosed within following + pre-processing check: + if defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + + Prototype: void *memcpy (void *dst, const void *src, size_t count); + + The job will be done in 5 steps. + Step 1: Align src/dest pointers, copy mis-aligned if fail to align both + Step 2: Repeatedly copy big block size of __OPT_BIG_BLOCK_SIZE + Step 3: Repeatedly copy big block size of __OPT_MID_BLOCK_SIZE + Step 4: Copy word by word + Step 5: Copy byte-to-byte + + Tunable options: + __OPT_BIG_BLOCK_SIZE: Size of big block in words. Default to 64. + __OPT_MID_BLOCK_SIZE: Size of big block in words. Default to 16. + */ +#ifndef __OPT_BIG_BLOCK_SIZE +#define __OPT_BIG_BLOCK_SIZE (4 * 16) +#endif + +#ifndef __OPT_MID_BLOCK_SIZE +#define __OPT_MID_BLOCK_SIZE (4 * 4) +#endif + +#if __OPT_BIG_BLOCK_SIZE == 16 +#define BEGIN_UNROLL_BIG_BLOCK \ + .irp offset, 0,4,8,12 +#elif __OPT_BIG_BLOCK_SIZE == 32 +#define BEGIN_UNROLL_BIG_BLOCK \ + .irp offset, 0,4,8,12,16,20,24,28 +#elif __OPT_BIG_BLOCK_SIZE == 64 +#define BEGIN_UNROLL_BIG_BLOCK \ + .irp offset, 0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60 +#else +#error "Illegal __OPT_BIG_BLOCK_SIZE" +#endif + +#if __OPT_MID_BLOCK_SIZE == 8 +#define BEGIN_UNROLL_MID_BLOCK \ + .irp offset, 0,4 +#elif __OPT_MID_BLOCK_SIZE == 16 +#define BEGIN_UNROLL_MID_BLOCK \ + .irp offset, 0,4,8,12 +#else +#error "Illegal __OPT_MID_BLOCK_SIZE" +#endif + +#define END_UNROLL .endr + + .syntax unified + .text + .align 2 + .global memcpy + .thumb + .thumb_func + .type memcpy, %function +memcpy: + @ r0: dst + @ r1: src + @ r2: len +#ifdef __ARM_FEATURE_UNALIGNED + /* In case of UNALIGNED access supported, ip is not used in + function body. */ + mov ip, r0 +#else + push {r0} +#endif + orr r3, r1, r0 + ands r3, r3, #3 + bne .Lmisaligned_copy + +.Lbig_block: + subs r2, __OPT_BIG_BLOCK_SIZE + blo .Lmid_block + + /* Kernel loop for big block copy */ + .align 2 +.Lbig_block_loop: + BEGIN_UNROLL_BIG_BLOCK +#ifdef __ARM_ARCH_7EM__ + ldr r3, [r1], #4 + str r3, [r0], #4 + END_UNROLL +#else /* __ARM_ARCH_7M__ */ + ldr r3, [r1, \offset] + str r3, [r0, \offset] + END_UNROLL + adds r0, __OPT_BIG_BLOCK_SIZE + adds r1, __OPT_BIG_BLOCK_SIZE +#endif + subs r2, __OPT_BIG_BLOCK_SIZE + bhs .Lbig_block_loop + +.Lmid_block: + adds r2, __OPT_BIG_BLOCK_SIZE - __OPT_MID_BLOCK_SIZE + blo .Lcopy_word_by_word + + /* Kernel loop for mid-block copy */ + .align 2 +.Lmid_block_loop: + BEGIN_UNROLL_MID_BLOCK +#ifdef __ARM_ARCH_7EM__ + ldr r3, [r1], #4 + str r3, [r0], #4 + END_UNROLL +#else /* __ARM_ARCH_7M__ */ + ldr r3, [r1, \offset] + str r3, [r0, \offset] + END_UNROLL + adds r0, __OPT_MID_BLOCK_SIZE + adds r1, __OPT_MID_BLOCK_SIZE +#endif + subs r2, __OPT_MID_BLOCK_SIZE + bhs .Lmid_block_loop + +.Lcopy_word_by_word: + adds r2, __OPT_MID_BLOCK_SIZE - 4 + blo .Lcopy_less_than_4 + + /* Kernel loop for small block copy */ + .align 2 +.Lcopy_word_by_word_loop: + ldr r3, [r1], #4 + str r3, [r0], #4 + subs r2, #4 + bhs .Lcopy_word_by_word_loop + +.Lcopy_less_than_4: + adds r2, #4 + beq .Ldone + + lsls r2, r2, #31 + itt ne + ldrbne r3, [r1], #1 + strbne r3, [r0], #1 + + bcc .Ldone +#ifdef __ARM_FEATURE_UNALIGNED + ldrh r3, [r1] + strh r3, [r0] +#else + ldrb r3, [r1] + strb r3, [r0] + ldrb r3, [r1, #1] + strb r3, [r0, #1] +#endif /* __ARM_FEATURE_UNALIGNED */ + +.Ldone: +#ifdef __ARM_FEATURE_UNALIGNED + mov r0, ip +#else + pop {r0} +#endif + bx lr + + .align 2 +.Lmisaligned_copy: +#ifdef __ARM_FEATURE_UNALIGNED + /* Define label DST_ALIGNED to BIG_BLOCK. It will go to aligned copy + once destination is adjusted to aligned. */ +#define Ldst_aligned Lbig_block + + /* Copy word by word using LDR when alignment can be done in hardware, + i.e., SCTLR.A is set, supporting unaligned access in LDR and STR. */ + + cmp r2, #8 + blo .Lbyte_copy + + /* if src is aligned, just go to the big block loop. */ + lsls r3, r1, #30 + beq .Ldst_aligned +#else + /* if len < 12, misalignment adjustment has more overhead than + just byte-to-byte copy. Also, len must >=8 to guarantee code + afterward work correctly. */ + cmp r2, #12 + blo .Lbyte_copy +#endif /* __ARM_FEATURE_UNALIGNED */ + + /* Align dst only, not trying to align src. That is the because + handling of aligned src and misaligned dst need more overhead than + otherwise. By doing this the worst case is when initial src is aligned, + additional up to 4 byte additional copy will executed, which is + acceptable. */ + + ands r3, r0, #3 + beq .Ldst_aligned + + rsb r3, #4 + subs r2, r3 + + lsls r3, r3, #31 + itt ne + ldrbne r3, [r1], #1 + strbne r3, [r0], #1 + + bcc .Ldst_aligned + +#ifdef __ARM_FEATURE_UNALIGNED + ldrh r3, [r1], #2 + strh r3, [r0], #2 + b .Ldst_aligned +#else + ldrb r3, [r1], #1 + strb r3, [r0], #1 + ldrb r3, [r1], #1 + strb r3, [r0], #1 + /* Now that dst is aligned */ +.Ldst_aligned: + /* if r1 is aligned now, it means r0/r1 has the same misalignment, + and they are both aligned now. Go aligned copy. */ + ands r3, r1, #3 + beq .Lbig_block + + /* dst is aligned, but src isn't. Misaligned copy. */ + + push {r4, r5} + subs r2, #4 + + /* Backward r1 by misaligned bytes, to make r1 aligned. + Since we need to restore r1 to unaligned address after the loop, + we need keep the offset bytes to ip and sub it from r1 afterward. */ + subs r1, r3 + rsb ip, r3, #4 + + /* Pre-load on word */ + ldr r4, [r1], #4 + + cmp r3, #2 + beq .Lmisaligned_copy_2_2 + cmp r3, #3 + beq .Lmisaligned_copy_3_1 + + .macro mis_src_copy shift +1: +#ifdef __ARM_BIG_ENDIAN + lsls r4, r4, \shift +#else + lsrs r4, r4, \shift +#endif + ldr r3, [r1], #4 +#ifdef __ARM_BIG_ENDIAN + lsrs r5, r3, 32-\shift +#else + lsls r5, r3, 32-\shift +#endif + orr r4, r4, r5 + str r4, [r0], #4 + mov r4, r3 + subs r2, #4 + bhs 1b + .endm + +.Lmisaligned_copy_1_3: + mis_src_copy shift=8 + b .Lsrc_misaligned_tail + +.Lmisaligned_copy_3_1: + mis_src_copy shift=24 + b .Lsrc_misaligned_tail + +.Lmisaligned_copy_2_2: + /* For 2_2 misalignment, ldr is still faster than 2 x ldrh. */ + mis_src_copy shift=16 + +.Lsrc_misaligned_tail: + adds r2, #4 + subs r1, ip + pop {r4, r5} + +#endif /* __ARM_FEATURE_UNALIGNED */ + +.Lbyte_copy: + subs r2, #4 + blo .Lcopy_less_than_4 + +.Lbyte_copy_loop: + subs r2, #1 + ldrb r3, [r1], #1 + strb r3, [r0], #1 + bhs .Lbyte_copy_loop + + ldrb r3, [r1] + strb r3, [r0] + ldrb r3, [r1, #1] + strb r3, [r0, #1] + ldrb r3, [r1, #2] + strb r3, [r0, #2] + +#ifdef __ARM_FEATURE_UNALIGNED + mov r0, ip +#else + pop {r0} +#endif + bx lr + + .size memcpy, .-memcpy diff --git a/PLAT/driver/hal/common/inc/ec_string.h b/PLAT/driver/hal/common/inc/ec_string.h new file mode 100644 index 0000000..d49e290 --- /dev/null +++ b/PLAT/driver/hal/common/inc/ec_string.h @@ -0,0 +1,35 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef EC_STRING_H +#define EC_STRING_H + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +#if defined(__cplusplus) +extern "C" { +#endif + +int32_t strlen_fast(const char *str); +char* ec_strnstr(const char *s, const char *find, size_t slen); + +#ifdef __cplusplus +} +#endif + +#endif // EC_STRING_H + diff --git a/PLAT/driver/hal/common/inc/ecuiccapi.h b/PLAT/driver/hal/common/inc/ecuiccapi.h new file mode 100644 index 0000000..ddb2b5b --- /dev/null +++ b/PLAT/driver/hal/common/inc/ecuiccapi.h @@ -0,0 +1,70 @@ +#ifndef __EC_UICC_API_H__ +#define __EC_UICC_API_H__ +/****************************************************************************** +Copyright: - 2017, All rights reserved by AirM2M Ltd. +File name: - ecuiccapi.h +Description: - the header file for UICC open API. +Function List: - +History: - 09/20/2022, Originated by xlhu +******************************************************************************/ + +/********************************************************************************* +* Includes +*********************************************************************************/ +#include "commontypedef.h" + +/********************************************************************************* +* Macros +*********************************************************************************/ + +/********************************************************************************* +* Type Definition +*********************************************************************************/ + + +/****************************************************************************** + ***************************************************************************** + * Functions + ***************************************************************************** +******************************************************************************/ + +/****************************************************************************** + * SoftSimReset + * Description: This API called by modem/uiccdrv task to reset softsim and get ATR parameter from softsim, + * as same as code/warm reset with physical SIM card. + * param[out] UINT16 *atrLen, the pointer to the length of ATR, this memory don't need to be free. + * param[out] UINT8 *atrData, the pointer to the ATR data, this memory don't need to be free. + * atrData buffer size is 33, fill atrData shall not exceed 33 bytes. + * Comment: This API will be called only if softsim feature is enabled by AT CMD. + * Shall send signal/msg to softsim task and block to wait response . + * Softsim internal process running in this func is not allowed. +******************************************************************************/ +void SoftSimReset(UINT16 *atrLen, UINT8 *atrData); + +/****************************************************************************** + * SoftSimApduReq + * Description: This API will be called by modem/uiccdrv task to send APDU(TPDU) request and get response from softsim, + * support case 1/2/3/4 command/response process. + * param[in] UINT16 txDataLen, the length of tx data + * param[in] UINT8 *txData, the pointer to the tx data, this memory don't need to be free. + * param[out] UINT16 *rxDataLen, the pointer to the length of rx data, this memory don't need to be free. + * param[out] UINT8 *rxData, the pointer to the rx data, this memory don't need to be free. + * rxData buffer size is 258, fill rxData shall not exceed 258 bytes. + * Comment: This API will be called only if softsim feature is enabled by AT CMD. + * Shall send signal/msg to softsim task and block to wait response. + * Softsim internal process running in this func is not allowed. +******************************************************************************/ +void SoftSimApduReq(UINT16 txDataLen, UINT8 *txData, UINT16 *rxDataLen, UINT8 *rxData); + +/****************************************************************************** + * SoftSimInit + * Description: This api called by modem/uiccdrv task to start softsim task if softsim feature is enabled. + * input: void + * output: void + * Comment: +******************************************************************************/ +void SoftSimInit(void); + +#endif + + diff --git a/PLAT/driver/hal/common/inc/exception_dump.h b/PLAT/driver/hal/common/inc/exception_dump.h new file mode 100644 index 0000000..ff35498 --- /dev/null +++ b/PLAT/driver/hal/common/inc/exception_dump.h @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file exception_dump.h + * @brief CMSIS OS Tick header file + * @version V1.0.0 + * @date 05. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _EXCEPTION_DUMP_H +#define _EXCEPTION_DUMP_H +#include "cmsis_compiler.h" +#include "commontypedef.h" +#include "mem_map.h" + +#define MAX_DELAYHHH 0//0xffffff +#define MAX_DELAY 0//0xff + +#define DUMP_UART_INSTANCE 0 +#define DUMP_SYNC_RSP_LEN 8 +//#define DUMP_SYNC_RSP_LEN 2 + +#define DUMP_RECV_FIFO_LEN 16 +#define CMD_FIX_LEN 8 +#define CMD_FCS_LEN 4 + +#define PROTOCOL_RSP_FIX_LEN 8 +#define PREAMBLE_CNT 1 +#define PREAMBLE_STRING_LEN 10 +#define PREAMBLE_WITH_NULL 1 +#define MAX_CMD_DATALEN 32 //maximum data size for cmd +#define MAX_READ_DATALEN (48*1024) //maximum data size for cmd + +#define MAX_RETRY_COUNT 32 +#define DATA_DUMP_WAIT_SYNC_MAX_RETRY_COUNT 10 +#define DATA_DUMP_GET_CMD_MAX_RETRY_COUNT 100 +#define DUMP_CID 0xdc +#define N_DUMP_CID 0x23 + +#define READ_ONECE_DATA_LEN 256 + +#define ACK 0 +#define NACK 1 + +#define GetDataCmd 0x20 +#define GetInfoCmd 0x21 +#define FinishCmd 0x25 + +#define WaitPeriod_1s 1000000 + +#define DUMP_RETRY_CMD_COUNT 1 +#define DUMP_RETRY_CMD_RESEND 2 + +#define DUMP_RETRY_ADDR 0x00C000 +#define DUMP_RETRY_COUNT_MAX 2 + +#define DUMP_END_FLAG_INIT 0xEC00 +#define DUMP_END_FLAG_SUCC 0xEC88 + + +typedef struct { + uint32_t ReadDataAddr; + uint32_t ReadLen; +}ReadDataReqCell; + +typedef struct { + uint8_t Command; + uint8_t Sequence; + uint8_t CID; + uint8_t NCID; + uint16_t Status; + uint16_t Length;//Length for Data filed + //uint8_t Data[MAX_CMD_DATALEN]; + uint32_t FCS; +}DumpRspWrap, *PtrDumpRspWrap; + +typedef struct { + uint8_t Command; + uint8_t Sequence; + uint8_t CID; + uint8_t NCID; + uint32_t Length;//Length for Data filed + uint8_t Data[MAX_CMD_DATALEN]; + uint32_t FCS; +}DumpReqWrap, *PtrDumpReqWrap; + +uint32_t EcDumpTopFlow(void); + +#ifdef FEATURE_UART_HELP_DUMP_ENABLE +#define EC_UART_HELP_DUMP_BUFF_LEN 128 +uint32_t EcDumpHandshakeProcUart(uint32_t SyncPeriod); +uint32_t EcDumpDataFlowUart(void); +#endif +#endif /* _EXCEPTION_DUMP_H */ diff --git a/PLAT/driver/hal/common/inc/exception_process.h b/PLAT/driver/hal/common/inc/exception_process.h new file mode 100644 index 0000000..0304be4 --- /dev/null +++ b/PLAT/driver/hal/common/inc/exception_process.h @@ -0,0 +1,502 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename:exception_process.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#ifndef _EXCEPTION_PROCESS_H +#define _EXCEPTION_PROCESS_H +#include "cmsis_compiler.h" +#include "commontypedef.h" +#include "mem_map.h" + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +#define EC_FUNC_CALL_ADDR_DEPTH 4 +#define EC_ASSERT_FUNC_CALL_ADDR_DEPTH 4 +#define EC_EXCEP_STACK_DEPTH 32 +#define EC_EXCEP_SECTOR_SIZE 4096 +#define EC_EXCEP_MAGIC_NUMBER (0x00ec00ec) + +#define EC_EXCEP_FLASH_SECTOR_BASE EC_EXCEPTION_FLASH_BASE +#define EC_EXCEP_TASK_NAME_LEN 12 + +#define EC_SP_PSP_FLAG 0x4 + +#define EC_REG_SYS_CTRL_STATE (*(volatile unsigned int *) (0xE000ED24u)) +#define EC_REG_MFSR (*(volatile unsigned int *) (0xE000ED28u)) +#define EC_REG_MMAR (*(volatile unsigned int *) (0xE000ED34u)) +#define EC_REG_BFSR (*(volatile unsigned int *) (0xE000ED29u)) +#define EC_REG_BFAR (*(volatile unsigned int *) (0xE000ED38u)) +#define EC_REG_UFSR (*(volatile unsigned int *) (0xE000ED2Au)) +#define EC_REG_HFSR (*(volatile unsigned int *) (0xE000ED2Cu)) +#define EC_REG_DFSR (*(volatile unsigned int *) (0xE000ED30u)) +#define EC_REG_AFSR (*(volatile unsigned int *) (0xE000ED3Cu)) + +// magic number for fs assert indication "FS_Assert_sF", 12bytes/3 words 0x46535F41 0x73736572 0x745F7346 +#define EC_FS_ASSERT_MAGIC_NUMBER0 (0x46535F41) +#define EC_FS_ASSERT_MAGIC_NUMBER1 (0x73736572) +#define EC_FS_ASSERT_MAGIC_NUMBER2 (0x745F7346) + +#define EC_FS_ASSERT_REFORMAT_THRESHOLD (10) + +#define AT_PORT_UART_INSTANCE (1) +#define RESET_REASON_MAGIC (0xACD20E00) +#define RESET_REASON_MASK (0xFFFFFF00) +#define ACTIVE_RESET_MAGIC (0x5) +#define ACTIVE_RESET_MASK (0xF) +#define FUNC_CALL_TRACE + +#define EC_EXCEP_COMPRESS_SIZE 4096 +#define EC_EXCEP_COMPRESS_HEAD_OFFSET 4 + +#define EC_AP_64K_RAM_START_ADDR 0x000 +#define EC_AP_64K_RAM_END_ADDR 0x10000 +#define EC_AP_64K_RAM_LEN (EC_AP_64K_RAM_END_ADDR - EC_AP_64K_RAM_START_ADDR) + +#define EC_AP_125M_RAM_START_ADDR 0x400000 +#define EC_AP_125M_RAM_END_ADDR 0x4B0000 +#define EC_AP_125M_RAM_CODE_START_ADDR 0x400000 +#define EC_AP_125M_RAM_CODE_END_ADDR 0x8000 +#define EC_AP_125M_RAM_CODE_LEN (EC_AP_125M_RAM_CODE_END_ADDR - EC_AP_125M_RAM_CODE_START_ADDR) +#define EC_AP_125M_RAM_RW_START_ADDR 0x400000 +#define EC_AP_125M_RAM_RW_END_ADDR 0x4B0000 +#define EC_AP_125M_RAM_RW_LEN (EC_AP_125M_RAM_RW_END_ADDR - EC_AP_125M_RAM_RW_START_ADDR) + +#define EC_CP_64K_RAM_START_ADDR 0x200000 +#define EC_CP_64K_RAM_END_ADDR 0x210000 +#define EC_CP_64K_RAM_LEN (EC_CP_64K_RAM_END_ADDR - EC_CP_64K_RAM_START_ADDR) +#define EC_CP_125M_RAM_START_ADDR 0x4B0000 +#define EC_CP_125M_RAM_END_ADDR 0x4B0000 +#define EC_CP_125M_RAM_CODE_START_ADDR 0x4B0000 +#define EC_CP_125M_RAM_CODE_END_ADDR 0x4B0000 +#define EC_CP_125M_RAM_CODE_LEN (EC_CP_125M_RAM_CODE_END_ADDR - EC_CP_125M_RAM_CODE_START_ADDR) +#define EC_CP_125M_RAM_RW_START_ADDR 0x4B0000 +#define EC_CP_125M_RAM_RW_END_ADDR 0x4B0000 +#define EC_CP_125M_RAM_RW_LEN (EC_CP_125M_RAM_RW_END_ADDR - EC_CP_125M_RAM_RW_START_ADDR) + +#define EC_EXCEPTION_FLASH_BASE FLASH_EXCEP_DUMP_ADDR +#define EC_EXCEPTION_FLASH_BLOCK_NUMBS FLASH_EXCEP_DUMP_SECTOR_NUM // (420KB/105 sectors) +#define EC_EXCEPTION_FLASH_MAX_LEN (EC_EXCEPTION_FLASH_BLOCK_NUMBS*EC_EXCEP_COMPRESS_SIZE) // (424KB) + +#define EC_EXCEPTION_AP_RAM_BASE (0x00000) +#define EC_EXCEPTION_AP_RAM_END (0x10000) +#define EC_EXCEPTION_AP_RAM_LEN (EC_EXCEPTION_AP_RAM_END - EC_EXCEPTION_AP_RAM_BASE) + +#define EC_EXCEPTION_CP_RAM_BASE (0x200000) +#define EC_EXCEPTION_CP_RAM_END (0x210000) +#define EC_EXCEPTION_CP_RAM_LEN (EC_EXCEPTION_CP_RAM_END - EC_EXCEPTION_CP_RAM_BASE) + +#define EC_EXCEPTION_APCP_RAM_BASE (0x400000) +#define EC_EXCEPTION_APCP_RAM_END (0x540000) +#define EC_EXCEPTION_APCP_RAM_LEN (EC_EXCEPTION_APCP_RAM_END - EC_EXCEPTION_APCP_RAM_BASE) + +#define EC_EXCEPTION_CP_SHARED_RAM_LEN (0x14000) + +#define EC_SHAREDINFO_RAM_END_ADDR (0x53F000) + +#define EC_ASSERT_PC_ADDR (EC_SHAREDINFO_RAM_END_ADDR-0x20) // 0x53EFE0 +#define EC_ASSERT_LR_ADDR (EC_SHAREDINFO_RAM_END_ADDR-0x18) // 0x53EFE8 +#define EC_EXCEPTION_MAGIC_AP_ADDR (EC_SHAREDINFO_RAM_END_ADDR-0x10) // 0x53EFF0 +#define EC_EXCEPTION_MAGIC_CP_ADDR (EC_SHAREDINFO_RAM_END_ADDR-0x0C) // 0x53EFF4 +#define EC_EXCEPTION_STORE_RAM_ADDR (EC_SHAREDINFO_RAM_END_ADDR-0x8) // 0x53EFF8 + +#define EC_COMPRESS_FLAG_AP_64K "ec_comp_ap_64k" +#define EC_COMPRESS_FLAG_AP_125M "ec_comp_ap_125m" +#define EC_COMPRESS_FLAG_CP_64K "ec_comp_cp_64k" +#define EC_COMPRESS_FLAG_CP_125M "ec_comp_cp_125m" + +#define EC_COMPRESS_ADDR_AP_64K "ec_comp_addr_ap:" +#define EC_COMPRESS_ADDR_CP_64K "ec_comp_addr_cp:" +#define EC_COMPRESS_ADDR_125M "ec_comp_addr_all:" +#define EC_COMPRESS_ADDR_AP_125M "ec_comp_addr_share_ap:" +#define EC_COMPRESS_ADDR_CP_125M "ec_comp_addr_share_cp:" + +#define EC_AP_HARDFAULT_TASK_FLAG 0xAF012013 +#define EC_AP_ASSERT_TASK_FLAG 0xAA012013 +#define EC_AP_HARDFAULT_INT_FLAG 0xAF010129 +#define EC_AP_ASSERT_INT_FLAG 0xAA010129 +#define EC_AP_HARDFAULT_SMALLIMAGE_FLAG 0xAF019527 +#define EC_AP_ASSERT_SMALLIMAGE_FLAG 0xAA019527 + +#define EC_CP_HARDFAULT_TASK_FLAG 0xCF012013 +#define EC_CP_ASSERT_TASK_FLAG 0xCA012013 +#define EC_CP_HARDFAULT_INT_FLAG 0xCF010129 +#define EC_CP_ASSERT_INT_FLAG 0xCA010129 +#define EC_CP_HARDFAULT_SMALLIMAGE_FLAG 0xCF019527 +#define EC_CP_ASSERT_SMALLIMAGE_FLAG 0xCA019527 + +#define EC_EXCEP_TYPE_AP_TASK_HARDFAULT EC_AP_HARDFAULT_TASK_FLAG +#define EC_EXCEP_TYPE_AP_TASK_ASSERT EC_AP_ASSERT_TASK_FLAG +#define EC_EXCEP_TYPE_CP_TASK_HARDFAULT EC_CP_HARDFAULT_TASK_FLAG +#define EC_EXCEP_TYPE_CP_TASK_ASSERT EC_CP_ASSERT_TASK_FLAG +#define EC_EXCEP_TYPE_AP_INT_HARDFAULT EC_AP_HARDFAULT_INT_FLAG +#define EC_EXCEP_TYPE_AP_INT_ASSERT EC_AP_ASSERT_INT_FLAG +#define EC_EXCEP_TYPE_CP_INT_HARDFAULT EC_CP_HARDFAULT_INT_FLAG +#define EC_EXCEP_TYPE_CP_INT_ASSERT EC_CP_ASSERT_INT_FLAG +#define EC_EXCEP_TYPE_AP_SMALLIMAGE_HARDFAULT EC_AP_HARDFAULT_SMALLIMAGE_FLAG +#define EC_EXCEP_TYPE_AP_SMALLIMAGE_ASSERT EC_AP_ASSERT_SMALLIMAGE_FLAG +#define EC_EXCEP_TYPE_CP_SMALLIMAGE_HARDFAULT EC_CP_HARDFAULT_SMALLIMAGE_FLAG +#define EC_EXCEP_TYPE_CP_SMALLIMAGE_ASSERT EC_CP_ASSERT_SMALLIMAGE_FLAG + +#define EC_EXCEPTION_START_FLAG 0xEC112013 +#define EC_EXCEPTION_END_FLAG 0xEC990129 + +#define EC_EXCEP_ASSERT_BUFF_LEN 120 + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +typedef struct ec_exception_comp_tag +{ + uint32_t needCompressAddr; + uint32_t needCompressTotalLen; + uint32_t needCompressOnceLen; + uint32_t compressedBufAddr; + uint32_t compressedBufLen; + uint32_t writeFlashAddr; + uint32_t compressType; +}ec_comp_input; + +typedef struct ec_exception_data_tag +{ + UINT32 startAddr; + UINT32 compressedLen; +}ec_exception_data; + +typedef struct ec_exception_addr_tag +{ + uint32_t ap_ram_start_addr; + uint32_t ap_ram_end_addr; + uint32_t cp_ram_start_addr; + uint32_t cp_ram_end_addr; + uint32_t apcp_ram_start_addr; + uint32_t apcp_ram_end_addr; + + uint32_t ec_stack_start_addr; + uint32_t ec_stack_end_addr; + uint32_t ec_code_start_addr; + uint32_t ec_code_end_addr; +}ec_exception_addr; + +typedef struct _ec_m3_exception_regs +{ + struct + { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + union + { + uint32_t value; + struct + { + uint32_t IPSR : 8; + uint32_t EPSR : 8; + uint32_t APSR : 8; + }bits; + }psr; + uint32_t exc_return; + uint32_t msp; + uint32_t psp; + uint32_t CONTROL; + uint32_t BASEPRI; + uint32_t PRIMASK; + uint32_t FAULTMASK; + }stack_frame; + + union + { + uint32_t value; + struct + { + uint32_t MEM_FAULT_ACT : 1; + uint32_t BUS_FAULT_ACT : 1; + uint32_t UNUSED_BITS1 : 1; + uint32_t USAGE_FAULT_ACT : 1; + uint32_t UNUSED_BITS2 : 3; + uint32_t SVCALLACT : 1; + uint32_t MONITORACT : 1; + uint32_t UNUSED_BITS3 : 1; + uint32_t PENDSVACT : 1; + uint32_t SYSTICKACT : 1; + uint32_t USAGEFAULTPENDED : 1; + uint32_t MEMFAULTPENDED : 1; + uint32_t BUSFAULTPENDED : 1; + uint32_t SVCALLPENDED : 1; + uint32_t MEMFAULT_EN : 1; + uint32_t BUSFAULT_EN : 1; + uint32_t USAGEFAULT_EN : 1; + }bits; + }sys_ctrl_stat; + + union + { + uint8_t value; + struct + { + uint8_t IACCVIOL : 1; + uint8_t DACCVIOL : 1; + uint8_t UNUSED_BIT : 1; + uint8_t MUNSTKERR : 1; + uint8_t MSTKERR : 1; + uint8_t MLSPERR : 1; + uint8_t UNUSED_BIT2 : 1; + uint8_t MMARVALID : 1; + }bits; + }mfsr; + + union + { + uint8_t value; + struct + { + uint8_t IBUSERR : 1; + uint8_t PRECISEER : 1; + uint8_t IMPREISEER : 1; + uint8_t UNSTKERR : 1; + uint8_t STKERR : 1; + uint8_t LSPERR : 1; + uint8_t UNUSED_BIT : 1; + uint8_t BFARVALID : 1; + }bits; + }bfsr; + + union + { + unsigned short value; + struct + { + unsigned short UNDEFINSTR : 1; + unsigned short INVSTATE : 1; + unsigned short INVPC : 1; + unsigned short NOCP : 1; + unsigned short UNUSED_BITS : 4; + unsigned short UNALIGNED : 1; + unsigned short DIVBYZERO : 1; + }bits; + }ufsr; + + union + { + uint32_t value; + struct + { + uint32_t UNUSED_BIT1 : 1; + uint32_t VECTBL : 1; + uint32_t UNUSED_BIT2 : 28; + uint32_t FORCED : 1; + uint32_t DEBUGEVT : 1; + }bits; + }hfsr; + + union + { + uint32_t value; + struct + { + uint32_t HALTED : 1; + uint32_t BKPT : 1; + uint32_t DWTTRAP : 1; + uint32_t VCATCH : 1; + uint32_t EXTERNAL : 1; + }bits; + }dfsr; + + uint32_t mmfar; + uint32_t bfar; + uint32_t afar; +}ec_m3_exception_regs; + +typedef struct _ec_exception_store +{ + uint32_t ec_start_flag; + uint32_t ec_exception_flag; + uint32_t ec_exception_count; + ec_m3_exception_regs excep_regs; + ec_exception_addr excep_addr; + uint32_t func_call_stack[EC_FUNC_CALL_ADDR_DEPTH]; + uint32_t curr_time; + uint32_t excep_step; + uint8_t curr_task_name[EC_EXCEP_TASK_NAME_LEN]; + uint8_t ec_assert_buff[EC_EXCEP_ASSERT_BUFF_LEN]; + uint32_t ec_end_flag; +}ec_exception_store; + +enum +{ + excep_r0 = 0, + excep_r1 = 1, + excep_r2 = 2, + excep_r3 = 3, + excep_r12 = 4, + excep_lr = 5, + excep_pc = 6, + excep_psr = 7, +}; + +typedef enum EXCEPTION_CONFIG_OPTION +{ + EXCEP_OPTION_DUMP_FLASH_EPAT_LOOP, /*0 -- dump full exception info to flash and EPAT tool then trapped in endless loop(while(1))*/ + EXCEP_OPTION_PRINT_RESET, /*print necessary exception info, and then reset*/ + EXCEP_OPTION_DUMP_FLASH_RESET, /*dump full exception info to flash, and then reset*/ + EXCEP_OPTION_DUMP_FLASH_EPAT_RESET, /*dump full exception info to flash and EPAT tool, and then reset*/ + EXCEP_OPTION_SILENT_RESET, /*reset directly*/ + EXCEP_OPTION_DUMP_FLASH_EPAT_LOOP_AND_UART_HELP_DUMP = 10, /*10 -- enable uart help dump and dump full exception info to flash and EPAT tool then trapped in endless loop(while(1))*/ + EXCEP_OPTION_DUMP_FLASH_EPAT_RESET_AND_UART_HELP_DUMP = 13, /*13 -- enable uart help dump and dump full exception info to flash and EPAT tool, and then reset*/ + + EXCEP_OPTION_MAX + +}ExcepConfigOp; + +enum +{ + reg_r0 = 0, + reg_r1, + reg_r2, + reg_r3, + reg_r4, + reg_r5, + reg_r6, + reg_r7, + reg_r8, + reg_r9, + reg_r10, + reg_r11, + reg_r12, + reg_sp, + reg_lr, + reg_pc, +}; + +typedef enum +{ + EC_RAM_COMP_NORMAL = 0, + EC_AP_64K_RAM_COMP = 1, + EC_AP_125M_RAM_COMP, + EC_CP_64K_RAM_COMP, + EC_CP_125M_RAM_COMP, +}ecRamCompType; + +typedef enum +{ + EC_CORE_TYPE_AP = 1, + EC_CORE_TYPE_CP = 2, +}ecCoreType; + +typedef enum +{ + EC_CHIP_TYPE_EC616 = 0x616, + EC_CHIP_TYPE_EC618 = 0x618, +}ecChipType; + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +#if defined ( __CC_ARM ) +extern unsigned int __current_pc(void); // arm_cc used to get pc, it cannot get pc directly +extern unsigned int __current_sp(void); // arm_cc used to get sp + +#elif defined(__GNUC__) +void *__current_pc(void); +#endif + +void ecRecordNodeInit(void); + +void excepCheckFaultType(ec_m3_exception_regs *excep_regs); +void excepShowStackFrame(ec_m3_exception_regs *excep_regs); + +extern void excepEcAssert(const char *func, uint32_t line, uint32_t v1, uint32_t v2, uint32_t v3); +void excepGetTaskInfo(void); +void excepCleanInExcephandler(void); +BOOL excepIsInExcephandler(void); +BOOL excepIsFsAssert(void); +BOOL excepDumpCheckPoint(uint8_t id); + + + +#if defined ( __CC_ARM ) +//extern __inline void ec_assert_regs(void); +extern __INLINE __asm void ec_assert_regs(void); +extern void excepPrintAssertInfo(const char *func, uint32_t line, const char *file, uint32_t v1, uint32_t v2, uint32_t v3); + #ifdef EC_ASSERT_FLAG + #define EC_ASSERT(x,v1,v2,v3) \ + do { \ + { \ + if((x) == 0) \ + { \ + ec_assert_regs(); \ + *((unsigned int *)EC_ASSERT_PC_ADDR) = __current_pc(); \ + *((unsigned int *)EC_ASSERT_LR_ADDR) = __GET_RETURN_ADDRESS(); \ + excepEcAssert(__FUNCTION__, __LINE__, (uint32_t)(v1),(uint32_t)(v2),(uint32_t)(v3)); \ + while(1); \ + }\ + } \ + } while(0) + #else + #define EC_ASSERT(x,v1,v2,v3) \ + do { \ + { \ + if((x) == 0) \ + { \ + printf("Assert, func:%s, file: %s, line: %d, val: 0x%x,0x%x,0x%x \r\n", __FUNCTION__, __FILE__, __LINE__, (uint32_t)(v1),(uint32_t)(v2),(uint32_t)(v3)); \ + __disable_irq();\ + while(1);\ + }\ + } \ + } while(0) + #endif + +#elif defined(__GNUC__) +extern void ec_assert_regs(void); +#define EC_ASSERT(x,v1,v2,v3) \ + do { \ + { \ + if((x) == 0) \ + { \ + ec_assert_regs(); \ + excepEcAssert(__FUNCTION__, __LINE__, (uint32_t)(v1),(uint32_t)(v2),(uint32_t)(v3)); \ + while(1); \ + }\ + } \ + } while(0) +#endif + +#ifdef FEATURE_DUMP_CHECK +#define EXCEP_CHECK_POINT(ID) excepDumpCheckPoint(ID) +#endif + +#endif /* _EXCEPTION_H */ diff --git a/PLAT/driver/hal/common/inc/sct_aes_sha_api.h b/PLAT/driver/hal/common/inc/sct_aes_sha_api.h new file mode 100644 index 0000000..89c9df8 --- /dev/null +++ b/PLAT/driver/hal/common/inc/sct_aes_sha_api.h @@ -0,0 +1,243 @@ +#ifndef __SCT_AES_SHA_API_H__ +#define __SCT_AES_SHA_API_H__ + +/****************************************************************************** + ****************************************************************************** + Copy right: 2017-, Copyrigths of AirM2M Ltd. + File name: sct_aes_sha_api.h + Description: SCT AES/SHA API, external, and provide to app + History: 2020/12/02 Originated by Jason + ****************************************************************************** +******************************************************************************/ +#include "osasys.h" + + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ + + + + +/****************************************************************************** + ***************************************************************************** + * STRUCT + ***************************************************************************** +******************************************************************************/ + +typedef enum +{ + SCT_AES_SHA_RET_OK = 0, + SCT_AES_SHA_ERROR = -1, + SCT_AES_SHA_BUSY = -2 +}SctAesShaRetEnum; + +typedef INT32 SctAesShaRet; + + +/* + * AES mode, same enum as: DescAESMode +*/ +typedef enum +{ + SCT_AES_ECB = 0, + SCT_AES_CBC = 1, + SCT_AES_CTR = 2 +}SctAESMode; + +/* + * AES PAD MODE, same enum as: DescAESPadMode +*/ +typedef enum +{ + /* + 0 - No Padding, should: dataLen%16 == 0 + 1 - PKCS7, paddingLen = 16 ¨C dataLen%16, paddingValue = k + 2 ¨C PaddingOneZeros (ISO/IEC 7816-4), paddingLen = 16 ¨C dataLen%16, paddingValue = 0x80,0x00,¡­..0x00 + 3 - PaddingZerosLen (ANSI X.923), paddingLen = 16 ¨C dataLen%16, paddingValue = 0x00,0x00,¡­..k + 4 - PaddingZeros, paddingLen = 16 ¨C dataLen%16, paddingValue = 0x00,0x00,¡­..0x00 + */ + SCT_AES_NO_PAD = 0, + SCT_AES_PKCS7_PAD = 1, + SCT_AES_ONE_ZEROS_PAD = 2, + SCT_AES_ZERO_LEN_PAD = 3, + SCT_AES_ZERO_PAD = 4 +}SctAESPadMode; + + +/* + * AES Key source, same enum as: DescAESKeySelect +*/ +typedef enum +{ + SCT_AES_CK_FROM_ADDR = 0, + SCT_AES_CK_FROM_EFUSE = 1 +}SctAESKeySelect; + +/* + * AES CK len, same enum as: DescAESCKLen +*/ +typedef enum +{ + /* If key is from flash, only support length: 128/192 */ + SCT_AES_CK_LEN_128 = 0, + SCT_AES_CK_LEN_192 = 1, + SCT_AES_CK_LEN_256 = 2 +}SctAESCKLen; + +/* + * AES DIR + * AESDIR is useless (default set to 0) for CTR (2) AES mode +*/ +typedef enum +{ + SCT_AES_ENC_DIR = 0, /* Encryption */ + SCT_AES_DEC_DIR = 1 /* Decryption */ +}SctAESDir; + +/* + * endian +*/ +typedef enum +{ + SCT_LITTLE_ENDIAN = 0, + SCT_BIG_ENDIAN = 1 +}SctEndianType; + +/* + * SHA MODE, same enum as: DescSHAMode +*/ +typedef enum +{ + SCT_SHA_1 = 0, /* SHA output: 20 bytes */ + SCT_SHA_224 = 1, /* SHA output: 28 bytes */ + SCT_SHA_256 = 2 /* SHA output: 32 bytes */ +}SctSHAMode; + + + +/* + * SCT AES cipher request +*/ +typedef struct +{ + UINT32 inputByteLen : 16; /* AES input data length */ + + UINT32 aesMode : 2; /* SctAESMode: ECB/CBC/CTR */ + UINT32 aesPadMode : 3; /* SctAESPadMode, For CTR mode, useless, set to 0 */ + UINT32 ckSelect : 1; /* SctAESKeySelect, CK select from: "ckAddr", or from eFUSE */ + UINT32 ckLen : 2; /* SctAESCKLen: 128/192/256, if CK select from eFUSE, only support: 128/192 */ + + UINT32 dir : 1; /* SctAESDir, Encryption/Decryption. For CTR mode, useless, set to 0 */ + UINT32 ckBLEndian : 1; /* SctEndianType, if not certain/known, suggest big endian: DESC_BIG_ENDIAN */ + UINT32 ivBLEndian : 1; /* SctEndianType, if not certain/known, suggest big endian: DESC_BIG_ENDIAN */ + UINT32 : 5; + + UINT8 *pInput; /* Input */ + UINT8 *pOutput; /* Output */ + + UINT8 *pCkAddr; /* Ignore it, if key select from eFUSE. and must 4 bytes aligned */ + UINT8 *pIvAddr; /* initial vector, + * Note: + * a) for CBC(AESMode = 1) mode, initial vector address + * b) for CTR(AESMode = 2) mode, initial counter address, + * c) Must 4 bytes aligned, and total 16 bytes + */ +}SctAesReq; //20 bytes + + +/****************************************************************************** + ***************************************************************************** + * Functions + ***************************************************************************** +******************************************************************************/ + +/***************************************************************************** + * Two types of SHA API + * 1> SHA segment API, which SHA input datas could be divided serveral segments + * + * 2> SHA whole API, all SHA datas input once. +*****************************************************************************/ + +/******* + * 1> SHA segment API +*******/ +/* + * SHA start +*/ +/****************************************************************************** + * SctShaSegStart + * Description: SHA segment API, which SHA input datas could be divided serveral segments, + * SHA start and lock the SCT HW, before SHA done (called by SctShaSegEnd()), + * SHA HW can't used by other modules + * input: SctSHAMode shaMode //SHA mode + * const UINT8 *shaHdr //SHA header, which also need to calc SHA before input data, if none, input PNULL + * UINT16 shaHdrByteLen //SHA header byte length + * output: SctShaRet + * Note: "pShaHdr" should be freed in caller, after "SctShaSegEnd()" called +******************************************************************************/ +SctAesShaRet SctShaSegStart(SctSHAMode shaMode, const UINT8 *pShaHdr, UINT16 shaHdrByteLen); + +/****************************************************************************** + * SctShaAppendSeg + * Description: SHA segment API, calc SHA + * input: SctSHAMode shaMode //SHA mode + * const UINT8 *pInput //SHA input source data + * UINT16 inputLen //SHA input source data length + * output: SctShaRet +******************************************************************************/ +SctAesShaRet SctShaAppendSeg(SctSHAMode shaMode, const UINT8 *pInput, UINT16 inputLen); + +/****************************************************************************** + * SctShaSegEnd + * Description: SHA segment API, end SHA calc + * input: SctSHAMode shaMode //SHA mode + * SctEndianType outBLType //output, big/little endian, if not known, suggest BIG endian + * UINT8 shaOutput[32] //output, SHA value + * output: SctShaRet +******************************************************************************/ +SctAesShaRet SctShaSegEnd(SctSHAMode shaMode, SctEndianType outBLType, UINT8 shaOutput[32]); + + +/******** + * 2. SHA whole API, all SHA datas input once. +********/ +/****************************************************************************** + * SctShaCalc + * Description: SHA whole API, all SHA datas input once + * input: SctSHAMode shaMode //SHA mode + * const UINT8 *pInput //pInput data + * UINT16 inputLen //input data length in byte + * const UINT8 *pShaHdr //SHA header, which also need to calc SHA before input data, if none, input PNULL + * UINT16 shaHdrByteLen //SHA header length in byte + * SctEndianType outBLType //big/little endian, if not known, suggest BIG endian + * UINT8 shaOutput[32] //output, SHA value + * output: SctShaRet +******************************************************************************/ +SctAesShaRet SctShaCalc(SctSHAMode shaMode, + UINT8 *pInput, + UINT16 inByteLen, + UINT8 *pShaHdr, + UINT16 shaHdrByteLen, + SctEndianType outBLType, + UINT8 shaOutput[32]); + + +/***************************************************************************** + * AES API +*****************************************************************************/ +/****************************************************************************** + * SctAesCalc + * Description: AES encrypt/decrypt calculation + * input: SctAesReq *pAesReq + * output: SctShaRet +******************************************************************************/ +SctAesShaRet SctAesCalc(SctAesReq *pAesReq); + + + + +#endif + diff --git a/PLAT/driver/hal/common/inc/sct_ppp_crc_api.h b/PLAT/driver/hal/common/inc/sct_ppp_crc_api.h new file mode 100644 index 0000000..05a109c --- /dev/null +++ b/PLAT/driver/hal/common/inc/sct_ppp_crc_api.h @@ -0,0 +1,141 @@ +#ifndef __SCT_PPP_CRC_API_H__ +#define __SCT_PPP_CRC_API_H__ + +/****************************************************************************** + ****************************************************************************** + Copy right: 2017-, Copyrigths of AirM2M Ltd. + File name: sct_ppp_crc_api.h + Description: SCT PPP EEA and CRC API, which provide to app + History: 2022/02/08 Originated by Jason + ****************************************************************************** +******************************************************************************/ +#include "osasys.h" + + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ +/* + * UINT32 * 8 = 256 bits +*/ +#define SCT_PPP_ACCM_TABLE_WORD_SIZE 8 + + +typedef enum +{ + SCT_PPP_RET_OK = 0, + SCT_PPP_ERROR = -1, + SCT_PPP_BUSY = -2, + SCT_PPP_INVALID_INPUT = -3 +}SctPppRetEnum; + +typedef INT32 SctPppRet; + + +/****************************************************************************** + ***************************************************************************** + * STRUCT + ***************************************************************************** +******************************************************************************/ + + + + +/****************************************************************************** + ***************************************************************************** + * Functions + ***************************************************************************** +******************************************************************************/ + +/* + * PPP escape ACCM table config +*/ +void SctPppEscapeAccmConfig(UINT32 pppAccmTbl[SCT_PPP_ACCM_TABLE_WORD_SIZE]); + +/* + * PPP de-escape ACCM table config +*/ +void SctPppDeEscapeAccmConfig(UINT32 pppAccmTbl[SCT_PPP_ACCM_TABLE_WORD_SIZE]); + +/****************************************************************************** + * SctPppEscapeCalcSize + * Description: calc PPP escape PKG size/length in bytes + * input: const DlPduBlock *pHead //input, a list, one PDU one PPP raw packet + * UINT32 *pOutList //output, should be a UINT32 array, escape pkg size for each PDU, and must 4 bytes aligned + * UINT32 listSize //input, "pOutList" array size + * DlPduBlock **pRetNext //output, if PDU number in input: "pHead" > "listSize", then not all PDU could calc escaped size, then output here + * output: INT32 //succ return 0, or return < 0 + * Comment: + * 1> PPP raw pkg (DlPduBlock) input format: + * +-------+---------------------+ + * |PPP hdr| data | + * +-------+---------------------+ + * 2> \PPP escape pkg format: \ + * +--+-------------------------------+-----+--+ + * |7E| escaped PPP pkg | CRC |7E| + * +--+-------------------------------+-----+--+ + * |<-------------- output size -------------->| + * 3> if "pOutList[n]" set to 0, means last PKG + * 4> !!!!!! "pOutList" must be __ALIGNED(4) !!!!!! +******************************************************************************/ +SctPppRet SctPppEscapeCalcSize(DlPduBlock *pHead, UINT32 *pOutList, UINT32 listSize, DlPduBlock **pRetNext); + +/****************************************************************************** + * SctPppEscape + * Description: PPP escape: add "7E" and CRC + * input: const DlPduBlock *pHead //input, a list, one PDU one PPP raw packet + * DlPduBlock *pEscapeHead //ouput, output buffer should allocated in caller + * output: INT32 //succ return 0, or return < 0 + * Comment: + * 1> PPP raw pkg (DlPduBlock) input format: + * +-------+---------------------+ + * |PPP hdr| data | + * +-------+---------------------+ + * 2> \output PPP escape pkg format: \ + * +--+-------------------------------+-----+--+ + * |7E| escaped PPP pkg | CRC |7E| + * +--+-------------------------------+-----+--+ + * |<------ pEscapeHead->length -------------->| + * ^pEscapeHead->pPdu + * Note: + * a) Caller should call: SctPppEscapeCalcSize() to calc the escaped pkg size; + * b) then alloc the buffer (maybe from DLFC) according to the escaped pkg size; + * c) finally call this API: SctPppEscape() to do PPP escape, and the escaped pkg size + * will be checked again in this API, to avoid a bug cause overflow +******************************************************************************/ +SctPppRet SctPppEscape(const DlPduBlock *pHead, DlPduBlock *pEscapeHead); + + +/****************************************************************************** + * SctPppDeEscape + * Description: PPP deescape + * input: const UlPduBlock *pHead //input, a list, PPP pkg start and end with "7E" + * UlPduBlock *pDeEscapeHead //ouput, output buffer should allocated in caller + * output: INT32 //succ return 0, or return < 0 + * Comment: + * 1> PPP pkg (UlPduBlock) input format: //note, PKG should start and end with "7E" (will check in this API) + * +--+-------------------------------+-----+--+ + * |7E| escaped PPP pkg | CRC |7E| + * +--+-------------------------------+-----+--+ + * 2> |output PPP deescape pkg format: / + * +-------+----------------------+-----+ + * |PPP hdr| data | CRC | + * +-------+----------------------+-----+ + * |<------ pDeEscapeHead->length ----->| + * ^pDeEscapeHead->ptr + * 3> If CRC checked failed, "pDeEscapeHead->pppCrcNok" set to 1 + * Note: + * a) The caller should be pre-alloc the buffer in "pDeEscapeHead", use to fill + * de-escaped pkg. And the pre-alloc buffer size should be estimated big enough, suggest + * equal the input escaped pkg size. + * b) After de-escaped in this API, de-escaped pkg size will be checked and set to + * the actually value. + * c) In some case, the caller can't input the header "7E", so we don't check it as mandatory +******************************************************************************/ +SctPppRet SctPppDeEscape(const UlPduBlock *pHead, UlPduBlock *pDeEscapeHead); + + +#endif + diff --git a/PLAT/driver/hal/common/inc/sys_record.h b/PLAT/driver/hal/common/inc/sys_record.h new file mode 100644 index 0000000..a593466 --- /dev/null +++ b/PLAT/driver/hal/common/inc/sys_record.h @@ -0,0 +1,67 @@ +#ifndef _SYS_RECORD_H +#define _SYS_RECORD_H + + + +#define EC_TRACE_SCHEDULE_RECORD 1 + +#define EC_TRACE_SCHEDULE_PRINT 1 + + +#define RECORD_LIST_LEN 30 +#define RECORD_LIST_NAME_LEN 4 + +typedef enum ecRecordType_enum +{ + EC_RECORD_TYPE_RESV = 0, + EC_RECORD_TYPE_USB = 1, + EC_RECORD_TYPE_XIC = 2, + EC_RECORD_TYPE_TASK = 3, + + EC_RECORD_TYPE_MAX, +}ecRecordType; + +typedef enum ecRecordPrintType_enum +{ + EC_RECORD_PRINT_RESV = 0, + EC_RECORD_PRINT_IN = 1, + EC_RECORD_PRINT_OUT = 2, + + EC_RECORD_PRINT_MAX, +}ecRecordPrintType; + +typedef union +{ + UINT32 ecNVICAndResv; // NVIC(0-14)---U16 resv(0xFFFF)---U16 + UINT32 ecXicModuleAndIdx; // xic module(0-2)---U16 idx(0-31)---U16 + CHAR ecRecordName[RECORD_LIST_NAME_LEN]; // +}ecInterInfo; + +typedef struct _recordNodeList +{ + ecInterInfo ecInterInfos; + UINT32 ecInTime; +}ecRecordNodeList; + +typedef struct _recordNodeParam +{ + UINT32 ecRecordType; + UINT32 ecLogInOrOut; + UINT32 ecNVIC; + UINT32 ecResv; + UINT32 ecInTime; + UINT32 ecXicModule; + UINT32 ecInterruptIdx; + UINT32 ecInterruptType; +}vRecordParam; + + +void ecTraceUsbIntOut(void); +void ecTraceUsbIntIn(void); +void ecTraceXicIntOut(INT32 module, INT32 idx); +void ecTraceXicIntIn(INT32 module, INT32 idx); + +void vTracePrintSchedule(vRecordParam recordParam); +void vTraceScheduleRecord(vRecordParam recordParam); + +#endif diff --git a/PLAT/driver/hal/common/src/ec_string.c b/PLAT/driver/hal/common/src/ec_string.c new file mode 100644 index 0000000..e8323e8 --- /dev/null +++ b/PLAT/driver/hal/common/src/ec_string.c @@ -0,0 +1,81 @@ +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +#define UNALIGNED(x) ((uint32_t)x & 0x3) +#define DETECTNULL(x) (((x) - 0x01010101) & ~(x) & 0x80808080) + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ + +/* + * Reference: https://github.com/eblot/newlib/blob/master/newlib/libc/string/strlen.c + */ +int32_t strlen_fast(const char *str) +{ + const char *start = str; + + uint32_t* aligned_addr; + + while(UNALIGNED(str)) + { + if(!*str) + { + return str - start; + } + str++; + } + + aligned_addr = (uint32_t*)str; + + while(!DETECTNULL(*aligned_addr)) + { + aligned_addr++; + } + + str = (char *)aligned_addr; + + while(*str) + { + str++; + } + + return str - start; +} + +/* + * Reference: http://src.gnu-darwin.org/src/lib/libc/string/strnstr.c.html + */ +char* ec_strnstr(const char *s, const char *find, size_t slen) +{ + char c, sc; + size_t len; + + if((c = *find++) != '\0') + { + len = strlen(find); + + do + { + do + { + if((sc = *s++) == '\0' || slen-- < 1) + return NULL; + } while(sc != c); + + if(len > slen) + return NULL; + + } while(strncmp(s, find, len) != 0); + + s--; + } + + return (char*)s; +} diff --git a/PLAT/driver/hal/common/src/ecuiccapi.c b/PLAT/driver/hal/common/src/ecuiccapi.c new file mode 100644 index 0000000..0dea396 --- /dev/null +++ b/PLAT/driver/hal/common/src/ecuiccapi.c @@ -0,0 +1,200 @@ +/****************************************************************************** +Copyright: - 2017, All rights reserved by AirM2M Ltd. +File name: - ecuiccapi.c +Description: - UICC open API. +Function List: - +History: - 09/20/2022, Originated by xlhu +******************************************************************************/ + + +/****************************************************************************** + * Include Files +*******************************************************************************/ +#include "cmsis_os2.h" +#include "FreeRTOS.h" +#include "task.h" +#include "os_common.h" +#include DEBUG_LOG_HEADER_FILE +#include "debug_trace.h" +#include "ecuiccapi.h" + +/********************************************************************************* + * Macros +*********************************************************************************/ + +/****************************************************************************** + * Extern global variables +*******************************************************************************/ + +/****************************************************************************** + * Extern functions +*******************************************************************************/ + +/****************************************************************************** + * Global variables +*******************************************************************************/ +/* + * bSoftSIMTaskCreate + * Whether the SoftSIM task created. +*/ +BOOL bSoftSIMTaskCreate = FALSE; +/****************************************************************************** + * Types +*******************************************************************************/ + +/****************************************************************************** + * Local variables +*******************************************************************************/ + + +/****************************************************************************** + * Function Prototypes +*******************************************************************************/ + +/****************************************************************************** + * Function definition +*******************************************************************************/ +#define __DEFINE_SOFTSIM_ADAPT_FUNCTION__ //just for easy to find this position in SS +/****************************************************************************** + * SoftSIM interface adapted note + * 1> The SoftSIM feature is disable as default, and enabled by AT+ECSIMCFG="softsim",1 + * 2> SoftSIM task shall be created in SoftSimInit func or appinit depended by softsim vender. + * 3> SoftSIM vender shall adapt functions SoftSimReset/SoftSimApduReq. +*******************************************************************************/ + +/****************************************************************************** + * SoftSimReset + * Description: This API called by modem/uiccdrv task to reset softsim and get ATR parameter from softsim, + * as same as code/warm reset with physical SIM card. + * param[in] null + * param[out] UINT16 *atrLen, the pointer to the length of ATR, this memory don't need to be free. + * param[out] UINT8 *atrData, the pointer to the ATR data, this memory don't need to be free. + * atrData buffer size is 33, fill atrData shall not exceed 33 bytes. + * Comment: This API will be called only if softsim feature is enabled by AT CMD. + * Shall send signal/msg to softsim task and block to wait response . + * Softsim internal process running in this func is not allowed. +******************************************************************************/ +void SoftSimReset(UINT16 *atrLen, UINT8 *atrData) +{ + osSemaphoreId_t sem = osSemaphoreNew(1U, 0, PNULL); + osStatus_t osState = osOK; + + /* + * softsim vender shall implement 3 steps as below + */ + + /* + * 1> create signal/msg + */ + + /* + * 2> send signal/msg to softsim task with sem/atrLen/atrData + */ + + /* + * 3> process signal/msg on softsim task, then retrun paramters and release sem on softsim task + */ + + + /* + * wait for sem 2sec + */ + if ((osState = osSemaphoreAcquire(sem, 2000)) != osOK) + { + OsaDebugBegin(FALSE, osState, 0, 0); + OsaDebugEnd(); + } + + /* + * Semaphore delete + */ + osSemaphoreDelete(sem); + +} + +/****************************************************************************** + * SoftSimApduReq + * Description: This API will be called by modem/uiccdrv task to send APDU(TPDU) request and get response from softsim, + * support case 1/2/3/4 command/response process. + * param[in] UINT16 txDataLen, the length of tx data + * param[in] UINT8 *txData, the pointer to the tx data, this memory don't need to be free. + * param[out] UINT16 *rxDataLen, the pointer to the length of rx data, this memory don't need to be free. + * param[out] UINT8 *rxData, the pointer to the rx data, this memory don't need to be free. + * rxData buffer size is 258, fill rxData shall not exceed 258 bytes. + * Comment: This API will be called only if softsim feature is enabled by AT CMD. + * Shall send signal/msg to softsim task and block to wait response. + * Softsim internal process running in this func is not allowed. +******************************************************************************/ +void SoftSimApduReq(UINT16 txDataLen, UINT8 *txData, UINT16 *rxDataLen, UINT8 *rxData) +{ + osSemaphoreId_t sem = osSemaphoreNew(1U, 0, PNULL); + osStatus_t osState = osOK; + + /* + * softsim vender shall implement 3 steps as below + */ + + /* + * 1> create signal/msg + */ + + /* + * 2> send signal/msg to softsim task with sem/txDataLen/txData/rxDataLen/rxData + */ + + /* + * 3> process signal/msg on softsim task, then retrun paramters and release sem on softsim task + */ + + + /* + * wait for sem 2sec + */ + if ((osState = osSemaphoreAcquire(sem, 2000)) != osOK) + { + OsaDebugBegin(FALSE, osState, 0, 0); + OsaDebugEnd(); + } + + /* + * Semaphore delete + */ + osSemaphoreDelete(sem); + +} + + + +/****************************************************************************** + * SoftSimInit + * Description: This api called by modem/uiccdrv task to start softsim task if softsim feature is enabled. + * input: void + * output: void + * Comment: +******************************************************************************/ +void SoftSimInit(void) +{ + if (bSoftSIMTaskCreate == TRUE) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, SoftSimInit_0, P_INFO, "Softsim task has already been created"); + return; + } + /* + * start softsim task + */ + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, SoftSimInit_1, P_INFO, "Start softsim task"); + /* + * softsim vender implement softsim task created + */ + + + + //delay 100ms for softsim task init + osDelay(100); + + //set flag after task created + bSoftSIMTaskCreate = TRUE; + +} + + diff --git a/PLAT/driver/hal/common/src/exception_dump.c b/PLAT/driver/hal/common/src/exception_dump.c new file mode 100644 index 0000000..18004fd --- /dev/null +++ b/PLAT/driver/hal/common/src/exception_dump.c @@ -0,0 +1,781 @@ +#include "stdio.h" +#include "string.h" + +#include "uart.h" +#if FEATURE_CCIO_ENABLE +#include "usb_device.h" +#endif +#include DEBUG_LOG_HEADER_FILE +#include "mem_map.h" +#include "exception_process.h" +#include "hal_dumpMedia.h" +#include "exception_dump.h" +#include "plat_config.h" + +#ifdef FEATURE_UART_HELP_DUMP_ENABLE +int *excepStepDump = (int *)0x404008; +uint32_t excepCfgOption = 0xff; +#define EcDumpGetUartDumpModeId(ownerId, moduleId, subId) (ownerId##__##moduleId##__##subId) +#endif +extern int *excepStep; +int excepDumpEndFlag = DUMP_END_FLAG_INIT; + +uint32_t dumpRetryReadCount = MAX_RETRY_COUNT; +uint32_t dumpHandshakeRetryCnt = MAX_RETRY_COUNT; +uint32_t dumpWaitSyncRetryCnt = DATA_DUMP_WAIT_SYNC_MAX_RETRY_COUNT; +uint32_t dumpGetCmdRetryCnt = DATA_DUMP_GET_CMD_MAX_RETRY_COUNT; + +const uint8_t dump_handshake_code[]= "enter assert dump mode"; +const uint8_t dump_response_code[]= "ok"; +const uint8_t PreambleDumpString[PREAMBLE_STRING_LEN] = {0x44, 0x55, 0x4d, 0x50, 0x44, 0x55, 0x4d, 0x50, 0xd, 0xa}; + +const uint16_t wCRCTableAbs[] = +{ + 0x0000, 0xCC01, 0xD801, 0x1400, 0xF001, 0x3C00, 0x2800, 0xE401, 0xA001, 0x6C00, 0x7800, 0xB401, 0x5000, 0x9C01, 0x8801, 0x4400, +}; + +uint32_t tDataInfoCell [][2]= +{ + {EC_EXCEPTION_AP_RAM_BASE, EC_EXCEPTION_AP_RAM_LEN}, + {EC_EXCEPTION_CP_RAM_BASE, EC_EXCEPTION_CP_RAM_LEN}, + {EC_EXCEPTION_APCP_RAM_BASE, EC_EXCEPTION_APCP_RAM_LEN}, +}; + +extern void delay_us(uint32_t us); +extern void usbc_trace_disable(void); + +int excepDelay(uint32_t maxDelay) +{ + int i=0; + int j=0; + + for(i=0; iData[0])); + ptrReadDataReqCellTemp = (ReadDataReqCell*)(&(dumpReqWrapTemp->Data[0])); + + if(ptrReadDataReqCell->ReadDataAddr == ptrReadDataReqCellTemp->ReadDataAddr) + { + dumpRetryReadCount++; + } + else + { + dumpRetryReadCount = 0; + memcpy(dumpReqWrapTemp, dumpReqWrap, sizeof(DumpReqWrap)); + } + break; + + case DUMP_RETRY_CMD_RESEND: + *excepStep = (*excepStep | 0x20000000); + if(dumpRetryReadCount >= DUMP_RETRY_COUNT_MAX) + { + ptrReadDataReqCell = (ReadDataReqCell*)(&dumpReqWrap->Data); + memset((void *)DUMP_RETRY_ADDR, 0, ptrReadDataReqCell->ReadLen); + memcpy((void *)DUMP_RETRY_ADDR, (void *)ptrReadDataReqCell->ReadDataAddr, ptrReadDataReqCell->ReadLen); + ptrReadDataReqCell->ReadDataAddr = DUMP_RETRY_ADDR; + } + break; + } + + return 0; +} + +static uint16_t EcDumpCRC16(uint16_t wCRC, uint8_t *pchMsg, uint16_t wDataLen) +{ + //uint16_t wCRC = 0xFFFF; + uint16_t i; + uint8_t chChar; + for (i = 0; i < wDataLen; i++) + { + chChar = *pchMsg++; + wCRC = wCRCTableAbs[(chChar^wCRC)&15]^(wCRC>>4); + wCRC = wCRCTableAbs[((chChar >>4)^ wCRC)&15]^(wCRC>>4); + } + return wCRC; +} + +uint32_t VerifyPreamble(uint8_t *Preamble) +{ + uint32_t idx; + uint32_t CheckCnt = 0; + for (idx = 0; idx < sizeof(PreambleDumpString); idx++) + { + if (PreambleDumpString[idx] == Preamble[idx]) { + CheckCnt++; + } + } + if (CheckCnt>1) + { + return TRUE; + } + return FALSE; +} + +uint32_t EcDumpWaitSync(void) +{ + uint8_t idx = 0; + uint8_t RecChar[DUMP_RECV_FIFO_LEN]; + uint8_t RetValue = 0; + uint8_t epNum = 0xff; + uint32_t instance; + uint32_t instanceTemp; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + instance = DUMP_UART_INSTANCE; + instanceTemp = instance; + eehDumpMediaFlush(UART_0_FOR_UNILOG);//flush RX FIFO is better to avoid left hdsk data, only for UART + } + else + { + instance = (uint32_t)usbDevGetLogIfIdx(); + epNum = usbDevGetEpNumFromIf(usbDevGetLogIfIdx()); + instanceTemp = (epNum&0xf); + extern void usbc_ctrl_full_flush_txfifo (uint32_t num ); + usbc_ctrl_full_flush_txfifo((epNum>>4)&0xf); + } + + delay_us(400000);//wait and let EPAT change its baudrate + + for (idx = 0; idx < PREAMBLE_CNT; idx++) + { + RetValue = eehDumpMediaSend(instance, (uint8_t *)&PreambleDumpString[0], PREAMBLE_STRING_LEN, 1000); + if (RetValue != PREAMBLE_STRING_LEN) + { + *excepStep = (*excepStep | 0x8); + + return 1; + } + } + + //Host send Preamble twice + RetValue = eehDumpMediaRecv(instanceTemp, &RecChar[0], PREAMBLE_CNT*PREAMBLE_STRING_LEN-2 + PREAMBLE_WITH_NULL, WaitPeriod_1s); + + if(RetValue > 0) + { + eehDumpMediaSend(instance, &RecChar[0], RetValue, 1000); + } + + if (RetValue != (PREAMBLE_CNT*PREAMBLE_STRING_LEN+PREAMBLE_WITH_NULL-2)) + { + *excepStep = (*excepStep | 0x10); + + return 1; + } + + if (VerifyPreamble(&RecChar[0]) ||VerifyPreamble(&RecChar[4])) + { + *excepStep = (*excepStep | 0x20); + return 0; + } + *excepStep = (*excepStep | 0x40); + + return 1; +} + +uint32_t EcDumpWaitCmd(PtrDumpReqWrap ptrDumpReqWrap) +{ + uint32_t RetValue = 0; + uint8_t epNum; + uint32_t instance; + uint32_t instanceTemp; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + instance = DUMP_UART_INSTANCE; + instanceTemp = instance; + } + else + { + instance = (uint32_t)usbDevGetLogIfIdx(); + epNum = usbDevGetEpNumFromIf(usbDevGetLogIfIdx()); + instanceTemp = (epNum&0xf); + } + + RetValue = eehDumpMediaRecv(instanceTemp, (uint8_t *)ptrDumpReqWrap, CMD_FIX_LEN, WaitPeriod_1s); + if (RetValue != CMD_FIX_LEN) + { + *excepStep = (*excepStep | 0x100); + return 1; + } + + if (ptrDumpReqWrap->Length > MAX_CMD_DATALEN) + { + ptrDumpReqWrap->Length = MAX_CMD_DATALEN; + } + #if 1 + RetValue = eehDumpMediaRecv(instanceTemp, (uint8_t *)(&ptrDumpReqWrap->Data[0]), ptrDumpReqWrap->Length, WaitPeriod_1s); + if (RetValue != ptrDumpReqWrap->Length) + { + *excepStep = (*excepStep | 0x200); + return 1; + } + + RetValue = eehDumpMediaRecv(instanceTemp, (uint8_t *)(&ptrDumpReqWrap->FCS), CMD_FCS_LEN, WaitPeriod_1s); + if (RetValue != CMD_FCS_LEN) + { + *excepStep = (*excepStep | 0x400); + return 1; + } + #endif + + *excepStep = (*excepStep | 0x800); + return 0; +} + +uint32_t EcDumpCheckCmd(PtrDumpReqWrap ptrDumpReqWrap) +{ + uint32_t sum = 0; + uint8_t * pStartAddr; + + if ((ptrDumpReqWrap->CID != DUMP_CID) ||(ptrDumpReqWrap->NCID != N_DUMP_CID)) + { + *excepStep = (*excepStep | 0x1000); + return 1; + } + pStartAddr = (uint8_t*) (&ptrDumpReqWrap->Command); + + sum = EcDumpCRC16(0xFFFF, pStartAddr, CMD_FIX_LEN + ptrDumpReqWrap->Length); + if (sum != ptrDumpReqWrap->FCS) + { + //return 0;//test now , no check sum + *excepStep = (*excepStep | 0x2000); + return 1; + } + + *excepStep = (*excepStep | 0x4000); + return 0; +} + +uint32_t EcDumpHandleGetData(PtrDumpReqWrap ptrDumpReqWrap) +{ + uint32_t RetValue = 0; + DumpRspWrap tDumpRspWrap; + ReadDataReqCell * ptrReadDataReqCell; + uint32_t Sum = 0xFFFF; + uint32_t Idx; + uint32_t *DataBuff; + uint32_t instance; + uint32_t sendDataLenLeft; + uint32_t sendDataLen; + uint32_t sendDataLastFlag = 0; + uint8_t dataAndCrcBuf[READ_ONECE_DATA_LEN+CMD_FCS_LEN] = {0}; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + instance = DUMP_UART_INSTANCE; + EcDumpCheckIfNeedRetry(DUMP_RETRY_CMD_RESEND, ptrDumpReqWrap, NULL); + } + else + { + instance = (uint32_t)usbDevGetLogIfIdx(); + EcDumpCheckIfNeedRetry(DUMP_RETRY_CMD_RESEND, ptrDumpReqWrap, NULL); + } + + ptrReadDataReqCell = (ReadDataReqCell*)(&ptrDumpReqWrap->Data[0]); + tDumpRspWrap.Command = ptrDumpReqWrap->Command; + tDumpRspWrap.Sequence = ptrDumpReqWrap->Sequence; + tDumpRspWrap.CID = ptrDumpReqWrap->CID; + tDumpRspWrap.NCID = ptrDumpReqWrap->NCID; + if ((ptrReadDataReqCell->ReadLen > MAX_READ_DATALEN) || ((ptrReadDataReqCell->ReadDataAddr%4)!=0)) + { + tDumpRspWrap.Length = 0; + tDumpRspWrap.Status = NACK; + Sum = EcDumpCRC16(0xFFFF, &tDumpRspWrap.Command, PROTOCOL_RSP_FIX_LEN+tDumpRspWrap.Length); + tDumpRspWrap.FCS = Sum; + RetValue = eehDumpMediaSend(instance, &tDumpRspWrap.Command, PROTOCOL_RSP_FIX_LEN+tDumpRspWrap.Length + CMD_FCS_LEN, 1000); + *excepStep = (*excepStep | 0x10000); + return RetValue; + } + + tDumpRspWrap.Status = ACK; + tDumpRspWrap.Length = ptrReadDataReqCell->ReadLen; + + RetValue = eehDumpMediaSend(instance, &tDumpRspWrap.Command, PROTOCOL_RSP_FIX_LEN, 1000); + if (RetValue != PROTOCOL_RSP_FIX_LEN) + { + *excepStep = (*excepStep | 0x20000); + return 1; + } + Sum = EcDumpCRC16(Sum, &tDumpRspWrap.Command,PROTOCOL_RSP_FIX_LEN); + + for (Idx = 0; Idx < ptrReadDataReqCell->ReadLen;) + { + (DataBuff) = (uint32_t *)(ptrReadDataReqCell->ReadDataAddr + Idx); + + sendDataLenLeft = ptrReadDataReqCell->ReadLen - Idx; + if(sendDataLenLeft < READ_ONECE_DATA_LEN) + { + sendDataLen = sendDataLenLeft; + } + else + { + sendDataLen = READ_ONECE_DATA_LEN; + } + + Sum = EcDumpCRC16(Sum, (uint8_t*)(DataBuff), sendDataLen); + + Idx = Idx + sendDataLen; + } + tDumpRspWrap.FCS = Sum; + + for (Idx = 0; Idx < ptrReadDataReqCell->ReadLen;) + { + (DataBuff) = (uint32_t *)(ptrReadDataReqCell->ReadDataAddr + Idx); + + sendDataLenLeft = ptrReadDataReqCell->ReadLen - Idx; + if(sendDataLenLeft < READ_ONECE_DATA_LEN) + { + sendDataLen = sendDataLenLeft; + sendDataLastFlag = 1; + } + else + { + sendDataLen = READ_ONECE_DATA_LEN; + if((READ_ONECE_DATA_LEN+Idx)==ptrReadDataReqCell->ReadLen) + { + sendDataLastFlag = 1; + } + } + if(sendDataLastFlag != 1) + { + RetValue = eehDumpMediaSend(instance, (uint8_t*)(DataBuff), sendDataLen, 5000); + } + else + { + memcpy(dataAndCrcBuf, (uint8_t*)(DataBuff), READ_ONECE_DATA_LEN); + memcpy(&dataAndCrcBuf[READ_ONECE_DATA_LEN], (uint8_t *)(&tDumpRspWrap.FCS), CMD_FCS_LEN); + + RetValue = eehDumpMediaSend(instance, (uint8_t*)(dataAndCrcBuf), (READ_ONECE_DATA_LEN+CMD_FCS_LEN), 5000); + } + //excepDelay(1000); + + if (RetValue != READ_ONECE_DATA_LEN) + { + *excepStep = (*excepStep | 0x40000); + return 1; + } + + Idx = Idx + sendDataLen; + } + + *excepStep = (*excepStep | 0x100000); + return RetValue; +} + +uint32_t EcDumpHandleGetInfo(PtrDumpReqWrap ptrDumpReqWrap) +{ + uint32_t RetValue = 0; + DumpRspWrap tDumpRspWrap; + uint32_t Sum = 0xFFFF; + uint32_t instance; + char infoCmdBuf[96] = {0}; + uint32_t infoCellLen = sizeof(tDataInfoCell); + + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + instance = DUMP_UART_INSTANCE; + } + else + { + instance = (uint32_t)usbDevGetLogIfIdx(); + } + + tDumpRspWrap.Command = ptrDumpReqWrap->Command; + tDumpRspWrap.Sequence = ptrDumpReqWrap->Sequence; + tDumpRspWrap.CID = ptrDumpReqWrap->CID; + tDumpRspWrap.NCID = ptrDumpReqWrap->NCID; + + tDumpRspWrap.Status = ACK; + tDumpRspWrap.Length = sizeof(tDataInfoCell); + + memcpy(infoCmdBuf, &tDumpRspWrap.Command, PROTOCOL_RSP_FIX_LEN); + + Sum = EcDumpCRC16(Sum, &tDumpRspWrap.Command,PROTOCOL_RSP_FIX_LEN); + memcpy(&infoCmdBuf[PROTOCOL_RSP_FIX_LEN], (uint8_t *)&tDataInfoCell, sizeof(tDataInfoCell)); + + Sum = EcDumpCRC16(Sum, (uint8_t *)&tDataInfoCell, sizeof(tDataInfoCell)); + tDumpRspWrap.FCS = Sum; + memcpy(&infoCmdBuf[PROTOCOL_RSP_FIX_LEN+infoCellLen], (uint8_t *)(&tDumpRspWrap.FCS), CMD_FCS_LEN); + RetValue = eehDumpMediaSend(instance, (uint8_t *)infoCmdBuf, PROTOCOL_RSP_FIX_LEN+infoCellLen+CMD_FCS_LEN, 1000); + if (RetValue != CMD_FCS_LEN) + { + *excepStep = (*excepStep | 0x1000000); + return 1; + } + + *excepStep = (*excepStep | 0x2000000); + return 0; +} + +uint32_t EcDumpDataFlow(void) +{ + uint32_t retryCount = dumpWaitSyncRetryCnt; + uint32_t RetValue = 1; + DumpReqWrap tDumpReqWrap; + DumpReqWrap tDumpReqWrapTmep; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + //UART_init(DUMP_UART_INSTANCE, 921600, false); + eehDumpMediaInit(); + } + + while(retryCount) + { + RetValue = EcDumpWaitSync(); + if(RetValue == 0) + { + break; + } + else + { + retryCount--; + } + } + if(retryCount == 0)//sync failed + { + return 1; + } + + retryCount = dumpGetCmdRetryCnt; + + while(retryCount) + { + memset(&tDumpReqWrap, 0, sizeof(tDumpReqWrap)); + *excepStep = (*excepStep | 0x80); + RetValue = EcDumpWaitCmd(&tDumpReqWrap); + if (RetValue != 0) + { + retryCount--; + continue; + } + + if(tDumpReqWrap.Command != 0x00) + { + EcDumpCheckIfNeedRetry(DUMP_RETRY_CMD_COUNT, &tDumpReqWrap, &tDumpReqWrapTmep); + } + + *excepStep = (*excepStep | 0x10); + RetValue = EcDumpCheckCmd(&tDumpReqWrap); + if (RetValue != 0) + { + continue; + } + + retryCount = dumpGetCmdRetryCnt; + + switch(tDumpReqWrap.Command) + { + case GetDataCmd: + *excepStep = (*excepStep | 0x8000); + EcDumpHandleGetData(&tDumpReqWrap); + break; + + case GetInfoCmd: + *excepStep = (*excepStep | 0x200000); + EcDumpHandleGetInfo(&tDumpReqWrap); + break; + + case FinishCmd: + excepDumpEndFlag = DUMP_END_FLAG_SUCC; + return 0; + + default: + break; + + } + } + return RetValue; +} + +uint32_t EcDumpHandshakeProc(uint32_t SyncPeriod) +{ + uint8_t recv_buffer[DUMP_SYNC_RSP_LEN]; + uint32_t SyncCnt = 0; + uint32_t RetValue = 0; + uint32_t idx; + uint8_t epNum; + uint32_t instance; + uint32_t retryCnt = 0; + uint32_t instanceTemp; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + instance = DUMP_UART_INSTANCE; + retryCnt = dumpHandshakeRetryCnt; + instanceTemp = instance; + } + else + { + retryCnt = dumpHandshakeRetryCnt; + instance = (uint32_t)usbDevGetLogIfIdx(); + epNum = usbDevGetEpNumFromIf(usbDevGetLogIfIdx()); + instanceTemp = (epNum&0xf); + } + + //eehDumpMediaPurgeRx(instance); only valid for UART and no need to reset RX FIFO again + + memset(recv_buffer, 0, sizeof(recv_buffer)); + + while(SyncCnt++ < retryCnt) + { + uniLogFlushOut(); + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + ECPLAT_PRINTF(UNILOG_PLA_INTERNAL_CMD, ecDumpHandshakeProc, P_ERROR, "enter dump handshake mode"); + + uniLogFlushOut(); + } + else + { + ECPLAT_PRINTF(UNILOG_PLA_INTERNAL_CMD, ecDumpUsbHandshakeProc, P_ERROR, "enter USB dump handshake mode"); + uniLogFlushOut(); + } + RetValue = eehDumpMediaRecv(instanceTemp, recv_buffer, DUMP_SYNC_RSP_LEN, WaitPeriod_1s/2); + + if (RetValue >= 2) + { + if(RetValue < (DUMP_SYNC_RSP_LEN - 2)) + { + delay_us(WaitPeriod_1s/2); + } + else + { + for (idx = 0; idx < DUMP_SYNC_RSP_LEN - 2; idx++) + { + if ((recv_buffer[idx] == dump_response_code[0]) && (recv_buffer[idx+1] == dump_response_code[1])) + { + *excepStep = (*excepStep | 0x2); + return 0; + } + } + } + } + else + { + delay_us(WaitPeriod_1s/2); + } + } + + *excepStep = (*excepStep | 0x4); + return 1; +} + +uint32_t EcDumpTopFlow(void) +{ + uint32_t RetValue = 1; + uint32_t instance = 0; + + *excepStep = 0x0; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + instance = DUMP_UART_INSTANCE; + } + else + { + usbc_trace_disable(); + eehDumpMediaInit(); + instance = (uint32_t)usbDevGetLogIfIdx(); + } + + *excepStep = (*excepStep | 0x1); + eehDumpMediaFlush(instance); + RetValue = EcDumpHandshakeProc(WaitPeriod_1s>>1); + + if (RetValue == 0) + { + RetValue = EcDumpDataFlow(); + *excepStep = (*excepStep | 0x4000000); + } + *excepStep = (*excepStep | 0x8000000); + + #ifdef FEATURE_UART_HELP_DUMP_ENABLE + excepCfgOption = BSP_GetPlatConfigItemValue(PLAT_CONFIG_ITEM_FAULT_ACTION); + + if ((RetValue == 1)&&((excepCfgOption == EXCEP_OPTION_DUMP_FLASH_EPAT_LOOP_AND_UART_HELP_DUMP)||(excepCfgOption == EXCEP_OPTION_DUMP_FLASH_EPAT_RESET_AND_UART_HELP_DUMP))) + { + RetValue = EcDumpHandshakeProcUart(WaitPeriod_1s>>1); + + if (RetValue == 0) + { + RetValue = EcDumpDataFlowUart(); + *excepStepDump = (*excepStepDump | 0x4000000); + } + *excepStepDump = (*excepStepDump | 0x8000000); + } + #endif + return RetValue; +} + +#ifdef FEATURE_UART_HELP_DUMP_ENABLE +uint32_t EcDumpHandshakeProcUart(uint32_t SyncPeriod) +{ + uint8_t recv_buffer[DUMP_SYNC_RSP_LEN]; + uint32_t SyncCnt = 0; + uint32_t RetValue = 0; + uint32_t idx; + uint32_t retryCnt = 0; + uint32_t instanceTemp; + uint32_t uartDumpModeId = 0; + uint32_t atPortBaudRate = 0xff; + uint8_t uartDumpModeBuff[EC_UART_HELP_DUMP_BUFF_LEN] = {0}; + int i; + + *excepStepDump = 0; + + uniLogSetPherType(UART_0_FOR_UNILOG); + + atPortBaudRate = BSP_GetPlatConfigItemValue(PLAT_CONFIG_ITEM_LOG_BAUDRATE); + UART_init(DUMP_UART_INSTANCE, atPortBaudRate & 0x7FFFFFFFUL, false); + retryCnt = 32; + instanceTemp = DUMP_UART_INSTANCE; + + memset(recv_buffer, 0, sizeof(recv_buffer)); + for(i=0; i> 28)&0xff)|0x20; + uartDumpModeBuff[33] = (uartDumpModeId >> 20)&0xff; + uartDumpModeBuff[34] = (uartDumpModeId >> 12)&0xff; + uartDumpModeBuff[35] = (uartDumpModeId >> 4)&0xf0; + uartDumpModeBuff[36] = 0xf; + + while(SyncCnt++ < retryCnt) + { + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + //ECPLAT_PRINTF(UNILOG_EXCEP_PRINT, ecDumpHandshakeProc, P_ERROR, "enter dump handshake mode"); + UART_send(DUMP_UART_INSTANCE, (const uint8_t *)uartDumpModeBuff, EC_UART_HELP_DUMP_BUFF_LEN, 10000); + } + + RetValue = eehDumpMediaRecv(instanceTemp, recv_buffer, DUMP_SYNC_RSP_LEN, WaitPeriod_1s); + + if (RetValue >= 2) + { + for (idx = 0; idx < DUMP_SYNC_RSP_LEN - 2; idx++) + { + if ((recv_buffer[idx] == dump_response_code[0]) && (recv_buffer[idx+1] == dump_response_code[1])) + { + *excepStepDump = (*excepStepDump | 0x2); + return 0; + } + } + } + } + + *excepStepDump = (*excepStepDump | 0x4); + return 1; +} + +uint32_t EcDumpDataFlowUart(void) +{ + uint32_t retryCount = dumpWaitSyncRetryCnt; + uint32_t RetValue = 1; + DumpReqWrap tDumpReqWrap; + DumpReqWrap tDumpReqWrapTmep; + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + //UART_init(DUMP_UART_INSTANCE, 921600, false); + eehDumpMediaInit(); + } + + while(retryCount) + { + RetValue = EcDumpWaitSync(); + if(RetValue == 0) + { + break; + } + else + { + retryCount--; + } + } + if(retryCount == 0)//sync failed + { + return 1; + } + + retryCount = dumpGetCmdRetryCnt; + + while(retryCount) + { + memset(&tDumpReqWrap, 0, sizeof(tDumpReqWrap)); + *excepStepDump = (*excepStepDump | 0x80); + RetValue = EcDumpWaitCmd(&tDumpReqWrap); + if (RetValue != 0) + { + retryCount--; + continue; + } + + if(tDumpReqWrap.Command != 0x00) + { + EcDumpCheckIfNeedRetry(DUMP_RETRY_CMD_COUNT, &tDumpReqWrap, &tDumpReqWrapTmep); + } + + *excepStepDump = (*excepStepDump | 0x10); + RetValue = EcDumpCheckCmd(&tDumpReqWrap); + if (RetValue != 0) + { + continue; + } + + retryCount = dumpGetCmdRetryCnt; + + switch(tDumpReqWrap.Command) + { + case GetDataCmd: + *excepStepDump = (*excepStepDump | 0x8000); + EcDumpHandleGetData(&tDumpReqWrap); + break; + + case GetInfoCmd: + *excepStepDump = (*excepStepDump | 0x200000); + EcDumpHandleGetInfo(&tDumpReqWrap); + break; + + case FinishCmd: + excepDumpEndFlag = DUMP_END_FLAG_SUCC; + return 0; + + default: + break; + } + } + return RetValue; +} +#endif diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_adc.h b/PLAT/driver/hal/ec618/ap/inc/hal_adc.h new file mode 100644 index 0000000..7332584 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_adc.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: hal_adc.h + * Description: EC618 adc hal driver header file + * History: Rev1.0 2019-12-12 + * Rev1.1 2020-02-29 Add api to get internal thermal temperature + * + ****************************************************************************/ + +#ifndef _HAL_ADC_H +#define _HAL_ADC_H + +/** + \addtogroup hal_adc_interface_gr + \{ + */ + +/** + \brief Calibarte ADC raw sample code + \param[in] input ADC conversion raw register value + \return calibrated voltage in unit of uV + */ +uint32_t HAL_ADC_CalibrateRawCode(uint32_t input); + +/** + \brief Convert ADC thermal channel raw sample to temperature in unit of mili degree centigrade + \param[in] input ADC thermal channel register value + \return temperature in unit of mili centidegree + */ +int32_t HAL_ADC_ConvertThermalRawCodeToTemperatureHighAccuracy(uint32_t input); + +/** + \brief Convert ADC thermal channel raw sample to temperature in unit of degree centigrade + \param[in] input ADC thermal channel register value + \return temperature in unit of centidegree + */ +int32_t HAL_ADC_ConvertThermalRawCodeToTemperature(uint32_t input); + +/** + \brief Get Vbat voltage in unit of mV in given time + \param[in] timeout_ms timeout value in unit of ms + \return error code or calibrated Vbat voltage + - -2 : timeout + - -1 : other errors + - > 0 : calibrated Vbat voltage in unit of mV + \note This API shall only be used in task context since semphore is used for synchronization + */ +int32_t HAL_ADC_SampleVbatVoltage(uint32_t timeout_ms); + +/** + \brief Get ADC thermal temperature in unit of degree centigrade in given time + \param[in] timeout_ms timeout value in unit of ms + \param[in,out] temperatruePtr pointer to temperature + \return error code + - -2 : timeout + - -1 : other errors + \note This API shall only be used in task context since semphore is used for synchronization + */ +int32_t HAL_ADC_GetThermalTemperature(uint32_t timeout_ms, int32_t* temperatruePtr); + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ADC_H */ diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_adcproxy.h b/PLAT/driver/hal/ec618/ap/inc/hal_adcproxy.h new file mode 100644 index 0000000..165f354 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_adcproxy.h @@ -0,0 +1,87 @@ + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_adcproxy.h +* +* Description: ap collect adc for cp use +* +* History: 2021.06.20 initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ + +#ifndef HAL_ADC_PROXY_H +#define HAL_ADC_PROXY_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +/* to use default efuse data, set to 1 if no data in efuse */ +#define USE_DEFAULT_EFUSE_VALUE 1 + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ +#define ADC_PROXY_VBAT 0 +#define ADC_PROXY_INTTEMP 1 +#define ADC_PROXY_EXTTEMP 2 + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** +* @brief cpADCProxyStartChannel +* @details start adc collection for cp use +* @note +*/ +void cpADCProxyStartChannel(uint8_t ADCSampleBm); + +/** +* @brief cpADCInit +* @details always call this api, use + use aio1 for vref, should call far before aio2 start sample, aio1 output need long stable time, + so call this api as early as possible +* @note +*/ +void cpADCInit(void); + +/** +* @brief cpADCDeInit +* @details power off vref output + +* @note +*/ +void cpADCDeInit(void); + +/** +* @brief adcProxyConvertRawCodeToTemperature +* @details calculate internal thermal from adc raw data. output accuracy is 0.001 degree +* @note +*/ +int32_t adcProxyConvertRawCodeToTemperature(uint32_t input); + + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_alarm.h b/PLAT/driver/hal/ec618/ap/inc/hal_alarm.h new file mode 100644 index 0000000..8f99043 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_alarm.h @@ -0,0 +1,171 @@ + + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_alarm.h +* +* Description: header of hal_alarm.c, battery low and high temperature interrupt handler +* +* History: 2021.05.12 initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ +#ifndef CHIP_HALALARM_H +#define CHIP_HALALARM_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ +typedef enum +{ + ALARM_TYPE_VOLT = 0, + ALARM_TYPE_THERM, +}alarmMsgType_e; + +typedef enum +{ + ALARM_INFO_DOWNWARD = 0, + ALARM_INFO_UPWARD, +}alarmMsgInfo_e; + +typedef struct +{ + uint8_t value; +}alarmInfo; + +typedef enum _EPAT_alarmVoltThd +{ + VOLT_THRESHOLD_2150 = 0, + VOLT_THRESHOLD_2200, + VOLT_THRESHOLD_2250, + VOLT_THRESHOLD_2300, + VOLT_THRESHOLD_2350, + VOLT_THRESHOLD_2400, + VOLT_THRESHOLD_2450, + VOLT_THRESHOLD_2500, + VOLT_THRESHOLD_2550, + VOLT_THRESHOLD_2600, + VOLT_THRESHOLD_2650 = 10, + VOLT_THRESHOLD_2700, + VOLT_THRESHOLD_2750, + VOLT_THRESHOLD_2800, + VOLT_THRESHOLD_2850, + VOLT_THRESHOLD_2900, + VOLT_THRESHOLD_2950 = 16, + VOLT_THRESHOLD_3000, + VOLT_THRESHOLD_3050, + VOLT_THRESHOLD_3100, + VOLT_THRESHOLD_3150 = 20, + VOLT_THRESHOLD_3200, + VOLT_THRESHOLD_3250, + VOLT_THRESHOLD_3300 = 23, +}alarmVoltThd; + +typedef enum _EPAT_alarmThmThd +{ + THM_THRESHOLD_LEVEL0 = 0, + THM_THRESHOLD_LEVEL1 = 1, + THM_THRESHOLD_LEVEL2 = 2, + THM_THRESHOLD_LEVEL3 = 3, +}alarmThmThd; + +typedef enum _EPAT_alarmHysteresisRange +{ + THM_HYSTERESIS_10 = 0, + THM_HYSTERESIS_20 = 1, + THM_HYSTERESIS_30 = 2, + THM_HYSTERESIS_40 = 3, +}alarmHysteresisRange; + + +typedef struct +{ + uint8_t voltEnable : 1; + uint8_t thermEnable : 1; + uint8_t rsvd : 6; + alarmVoltThd voltThd; /* voltage alarm threshold */ + alarmThmThd thermThd; /* thermal alarm threshold */ + alarmHysteresisRange hysterThd; /* thermal alarm hysteresis config */ +}alarmParamCfg_t; + + +typedef void(* vbatLowCallback_t)(bool isVoltAboveThd); +typedef void(* thmHighCallback_t)(bool isTempAboveThd); + + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** +* @brief alarmVBatInit +* @details vbat alarm init, callback will excute when vbat is too low + the hysteresis is fixed to 200mV +* +* @param voltThd100: vbat too low threshold + e.g. set threshold to 2.20V then voltThd100 = 220 +* @return null +*/ +void alarmVBatInit(uint16_t voltThd100); +/** +* @brief alarmVBatDeinit +* @details vbat alarm deinit, no vbat alarm will come anymore +* +* @return null +*/ +void alarmVBatDeinit(void); +/** +* @brief alarmThmHighInit +* @details thermometer alarm init, callback will excute when temperature is too high +* +* @param thmThd: set the threshold + @param range: set the hysteresis range +* @return null +*/ +void alarmThmHighInit(alarmThmThd thmThd, alarmHysteresisRange range); +/** +* @brief alarmThmHighDeinit +* @details thermometer alarm deinit, no thermometer alarm will come anymore +* +* @return null +*/ +void alarmThmHighDeinit(void); +/** +* @brief alarmFuncInit +* @details init to detect low voltage and high temperature +* +* @return null +*/ +void alarmFuncInit(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_charge.h b/PLAT/driver/hal/ec618/ap/inc/hal_charge.h new file mode 100644 index 0000000..a76d068 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_charge.h @@ -0,0 +1,95 @@ + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_charge.c +* +* Description: api for charge status detect +* +* History: initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ + +#ifndef HAL_CHARGE_H +#define HAR_CHARGE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include +#include "charge.h" + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ + + + + + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ +/** +* @brief chargeIntHandler +* @details charge interrupt handler +* +* @return null +*/ +void chargeIntHandler(void); +/** +* @brief chargeDetectInit +* @details Charge detect initialize +* +* @param cb: callback function for charge status update +* @param monitorEn: enable monitor to detect status_charging and status_full + @param sample_dly: sample delay. + +* @return null +*/ +void chargeDetectInit(chargeStatusCb cb, bool monitorEn, uint32_t sample_dly); +/** +* @brief chargeDetectDeinit +* @details Charge detect deinitialize +* +* @return null +*/ +void chargeDetectDeinit(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_dumpMedia.h b/PLAT/driver/hal/ec618/ap/inc/hal_dumpMedia.h new file mode 100644 index 0000000..da4b023 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_dumpMedia.h @@ -0,0 +1,129 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename:hal_dumpMedia.h +* +* Description: used to provid adapt API for ram dump +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef HAL_DUMPMEDIA_H +#define HAL_DUMPMEDIA_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + + + + + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** + \fn eehDumpMediaInit( void ) + \brief used to init dump media for eeh dump, map to UART or USB + \note only called in eeh dump procedure +*/ +void eehDumpMediaInit( void ); + + + +/** + \fn eehDumpMediaFlush(uint32_t instance) + \brief used to flush FIFO, only valid for UART now + \param[in] instance UART instance + \note only called in eeh dump procedure +*/ +void eehDumpMediaFlush(uint32_t instance); + +/** + \fn eehDumpMediaPurgeRx(uint32_t instance) + \brief used to flush FIFO, only valid for UART now + \param[in] instance UART instance + \note only called in eeh dump procedure +*/ +void eehDumpMediaPurgeRx(uint32_t instance); + +/** + \fn eehDumpMediaRecv(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief used to recv data from host via polling, uldp is still involved + \param[in] instance ep number or uart instance for recv + \param[in] data data pointer to store recv data + \param[in] num recv data length + \param[in] timeout_us timeout value when nothing recv + \note only called in eeh dump procedure + */ +uint32_t eehDumpMediaRecv(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us); + + + +/** + \fn eehDumpMediaSend(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief used to recv data from host via polling, uldp is still involved + \param[in] instance ep number or uart instance for recv + \param[in] data data pointer to send + \param[in] num send data length + \param[in] timeout_us timeout value when nothing recv + \note only called in eeh dump procedure + */ +uint32_t eehDumpMediaSend(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us); + + + +/** + \fn eehDumpMediaPollingEp0(uint32_t loopCnt, uint32_t loopInr) + \brief polling EP0 ctrl info and handle it, e.g. VCOM open + \param[in] loopCnt how many loop times + \param[in] loopInr internalval for each loop + \note only called in eeh dump procedure + */ +void eehDumpMediaPollingEp0(uint32_t loopCnt, uint32_t loopInr); + + + +/** + \fn eehDumpMediaPollingRndisHalt(uint32_t loopCnt, uint32_t loopInr) + \brief request rndis halt to host, need polling send sucesss or timeout + \param[in] loopCnt how many loop times + \param[in] loopInr internalval for each loop + \note only called in eeh dump procedure + */ +int32_t eehDumpMediaPollingRndisHalt(uint32_t loopCnt, uint32_t loopInr); + + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_i2s.h b/PLAT/driver/hal/ec618/ap/inc/hal_i2s.h new file mode 100644 index 0000000..f6657cb --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_i2s.h @@ -0,0 +1,287 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: hal_i2s.h + * Description: EC618 i2s hal driver header file + * History: Rev1.0 2021-9-18 + * + ****************************************************************************/ + +#ifndef _HAL_I2S_H +#define _HAL_I2S_H + +#include "i2s.h" +#include "codecDrv.h" + +/** + \addtogroup i2s_interface_gr + \{ + */ + +// 1. Static control part +typedef enum +{ + CODEC_ES8388 = 0, ///< ES8388 codec + CODEC_NAU88C22 = 1, ///< NAU88C22 codec + CODEC_ES7148 = 2, ///< ES7148 + CODEC_ES7149 = 3, ///< ES7149 + CODEC_ES8311 = 4, ///< ES8311 + CODEC_TM8211 = 5, ///< TM8211 +}i2sCodecType_e; + +typedef enum +{ + MSB_MODE = 0, ///< Left aligned mode + LSB_MODE = 1, ///< Right aligned mode + I2S_MODE = 2, ///< I2S mode + PCM_MODE = 3, ///< PCM mode +}i2sMode_e; + +typedef enum +{ + CODEC_MASTER_MODE = 0, ///< Codec plays as master + CODEC_SLAVE_MODE = 1, ///< Codec plays as slave +}i2sRole_e; + +typedef enum +{ + SAMPLERATE_8K = 1, ///< Sample rate 8k + SAMPLERATE_16K = 2, ///< Sample rate 16k + SAMPLERATE_32K = 3, ///< Sample rate 32k + SAMPLERATE_22_05K = 4, ///< Sample rate 22.05k + SAMPLERATE_44_1K = 5, ///< Sample rate 44.1k + SAMPLERATE_48K = 6, ///< Sample rate 48k + SAMPLERATE_96K = 7, ///< Sample rate 96k +}i2sSampleRate_e; + +typedef enum +{ + FRAME_SIZE_16_16 = 0, ///< WordSize 16bit, SlotSize 16bit + FRAME_SIZE_16_32 = 1, ///< WordSize 16bit, SlotSize 32bit + FRAME_SIZE_24_32 = 2, ///< WordSize 24bit, SlotSize 32bit + FRAME_SIZE_32_32 = 3, ///< WordSize 32bit, SlotSize 32bit +}i2sFrameSize_e; + +typedef enum +{ + PLAY = 0, ///< Audio play + RECORD = 1, ///< Audio record +}i2sPlayRecord_e; + +typedef enum +{ + I2S_CLK_DISABLE = 0, ///< Disable I2S clock + I2S_CLK_ENABLE = 1, ///< Enable I2S clock +}i2sPowerCtrl_e; + +typedef enum +{ + MONO = 0, + DUAL_CHANNEL = 1, +}i2sChannelSel_e; + +typedef struct +{ + i2sCodecType_e codecType; ///< Codec choose + i2sMode_e mode; ///< Audio mode choose + i2sRole_e role; ///< Role choose + i2sSampleRate_e sampleRate; ///< Sample rate choose + i2sFrameSize_e frameSize; ///< Frame size choose + i2sPlayRecord_e playRecord; ///< Play or record choose + i2sChannelSel_e channelSel; ///< Mono or dual channel select + uint32_t totalNum; ///< Audio source total num +}i2sParamCtrl_t; + +// 2. Dynamic control part +typedef enum +{ + STOP_I2S = 0, ///< Stop play or record + START_SEND = 1, ///< Start Play + START_RECV = 2, ///< Start record + START_SEND_RECV = 3, ///< Start Play or record +}i2sStartStop_e; + +typedef enum +{ + VOLUMN_INCREASE = 0, ///< Volumn increase + VOLUMN_DECREASE = 1, ///< Volumn decrease +}i2sVolumnCtrl_e; + +typedef enum +{ + // @ 1.8V level + VOL_1_65V = 0, + VOL_1_70V, + VOL_1_75V, + VOL_1_80V, + VOL_1_85V, + VOL_1_90V, + VOL_1_95V, + VOL_2_00V, + + // @ 2.8V level + VOL_2_65V = 8, + VOL_2_70V, + VOL_2_75V, + VOL_2_80V, + VOL_2_85V, + VOL_2_90V, + VOL_2_95V, + VOL_3_00V, + + // @ 3.3V level + VOL_3_05V = 16, + VOL_3_10V, + VOL_3_15V, + VOL_3_20V, + VOL_3_25V, + VOL_3_30V, + VOL_3_35V, + VOL_3_40V, + +}i2sIOVolSel_t; + + +typedef void (*i2sCbFunc_fn) (uint32_t event, uint32_t arg); ///< I2S init callback event. + + + + + +/////////////////////////////////////////////////////////////// +// When play, everytime play 1k size of audio src, then in i2sTxCb function, calculate how many data remained for +// sending. Data on the tail of transfering can be abandon, it won't influence the user to listen. +//////////////////////////////////////////////////////////////// +#define I2S_DMA_TX_DESCRIPTOR_CHAIN_NUM 1 ///< DMA TX descriptor chain number +#define AUDIO_TX_TRANSFER_SIZE 1024 ///< Maximum TX DMA transfer size each descriptor + +/////////////////////////////////////////////////////////////// +// This macro controls record. Every receive buffer is 8k, total has 35 picecs of this buffer that using DMA to receive. +// If you want to change the time of record, modify these two macros. +// How to set these parameters? +// For example: +// Your buffer size is 284954byte, use it to divide 8000, get 35.61925. Define this macro to 35. +//////////////////////////////////////////////////////////////// +#define I2S_DMA_RX_DESCRIPTOR_CHAIN_NUM 35 ///< DMA RX descriptor chain number +#define AUDIO_RX_TRANSFER_SIZE 8000 ///< Maximum RX DMA transfer size each descriptor + +/** + \brief Init I2S interface, include pinMux, and enable clock. + \param[out] powerCtrl Enable or disable I2S clock. + \param[out] txCb Indicate that i2s tx operation has been done. + \param[out] rxCb Indicate that i2s rx operation has been done. + + \return +*/ +void HAL_I2sInit(i2sPowerCtrl_e powerCtrl, i2sCbFunc_fn txCb, i2sCbFunc_fn rxCb); + + +/** + \brief Configure i2s. + \param[in] paramCtrl Every i2s control parameters + \return + \details + + 1. Parameter "paramCtrl" involves all the parameters that need to set in i2s development. + (1). i2sCodecType_e codecType + Choose the codec that you use. + + (2). i2sMode_e mode + We support 4 I2S interface modes, choose the one you need. + Note! Since I2S mode will have phase difference with other 3 modes, so please note that if you connect a speaker + in the LOUT1 or LOUT2, I2S mode will change to another speaker outer pin than other 3 modes. + + (3). i2sRole_e role + Codec acts as master or slave, so our controller will act as slave or master accordingly. + + (4). i2sSampleRate_e sampleRate + Choose the Sample rate you need. + + (5). i2sFrameSize_e frameSize + WordSize shouldn't bigger than slotSize. WordSize is the real size you use, and slotSize is the length that one + frame occupys. + + (6). i2sPlayRecord_e playRecord + Choose play audio or record audio. + + (7). i2sChannelSel_e channelSel + Choose mono or dual channel. + + (8). uint32_t totalNum + When playing, the total size of audio source. +*/ +void HAL_I2sConfig(i2sParamCtrl_t paramCtrl); + +/** + \brief Use i2s interface to play or record audio. + \param[in] playRecord Play or record. + \param[in,out] memAddr Audio source buffer when playing or recording + \param[in] trunkSize The size of everytime send or receive data. + \return +*/ +void HAL_I2sTransfer(i2sPlayRecord_e playRecord, uint8_t* memAddr, uint32_t trunkSize); + +/** + \brief Start play/record audio or stop play/record audio. + \param[in] startStop Start or stop play/record audio. + \return +*/ +void HAL_I2sStartSop(i2sStartStop_e startStop); + +/** + \brief Set total num of sending data to i2s. + \param[in] totalNum Total num of data. + \return +*/ +void HAL_I2SSetTotalNum(uint32_t totalNum); + +/** + \brief Get total num of data. + \return Total num of data. +*/ +uint32_t HAL_I2SGetTotalNum(void); + +/** + \brief Set play or record. + \param[in] playRecord Set i2s to play or record. + \return +*/ +void HAL_I2SSetPlayRecord(i2sPlayRecord_e playRecord); + +/** + \brief If codec don't have the ablity to adjust volumn, using this api to achieve it. + \param[in] srcBuf Audio source address of playing. + \param[in] srcTotalNum Total num of audio source for playing. + \param[in] volScale Increase or decrease the volumn. + \details + 1. Mute, write 00 for volScale. + 1. Decrease volumn to 50% of original, write 05 for volScale. + 2. Increase volumn to 5 times of original, write 50 for volScale. + 3. Increase volumn to 10 times of original, write 100 for volScale. + 4. "volScale" can change from 00(mute), 01(10%), 02(20%)......30(300%), 40(400%), 100(1000%)...... + \return +*/ +void HAL_I2sSrcAdjustVolumn(int16_t* srcBuf, uint32_t srcTotalNum, uint16_t volScale); + +void HAL_normalIOVoltSet(i2sIOVolSel_t sel); +void HAL_aonIOVoltSet(i2sIOVolSel_t sel); + + + +#if 0 +/** + \brief Control the volumn by codec when play audio. + \param[out] volumnCtrl Increase or decrease the volumn. + \param[out] step The gap each time when adjust the volumn. + \return +*/ +void HAL_I2sVolumnCtrl(i2sVolumnCtrl_e volumnCtrl, uint8_t step); +#endif + +/** \} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_I2S_H */ diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_misc.h b/PLAT/driver/hal/ec618/ap/inc/hal_misc.h new file mode 100644 index 0000000..7c39a6a --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_misc.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: hal_misc.h + * Description: EC618 hal for misc header file + * History: Rev1.0 2019-12-12 + * + ****************************************************************************/ + +#ifndef _HAL_MISC_H +#define _HAL_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + \brief HAL_Get_ChipID enum + */ +typedef enum _chip_id_sel +{ + CHIP_ID_ONLYID = 0, /**< only read chip ID */ + CHIP_ID_REVID, /**< only read revison ID */ + CHIP_ID_FULLID /**< read both chip ID & revison ID */ +} chip_id_sel; + + +/** + \brief Get chip id + \param[in] sel HAL_Get_ChipID enum + \return chip id value + */ +uint32_t HAL_Get_ChipID(chip_id_sel sel); + +/** + \fn delay_us(uint32_t us) + \brief delay time in microseconds. + \param[in] us number of us + \note Given the maximum cpu frequency is 204.8MHz and the limit in calculation, + * the maximum time can be delayed is 0xFFFFFFFF / 2048 = 2097151 us = 2097 m + */ +void delay_us(uint32_t us); + +/** + \fn apmuBootDbgGPIOSet(bool level) + \brief set gpio level in boot flow, for boot time dbg + \param[in] level + \note should set register directly, do not use api + */ +void apmuBootDbgGPIOSet(bool level); + +/** + \fn bool apmuGetLongSlpCfg(void) + \brief config the maximum sleep length. + 1. We suggest return false to sleep no more than 36hour + 2. But when usb is disabled and you do not care about time accuracy, + return true to set maximum sleep time to 1165 hour + \note false: sleep no more than 36.4 hour, true: can sleep 1165 hour + */ +bool apmuGetLongSlpCfg(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_MISC_H */ diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_phy.h b/PLAT/driver/hal/ec618/ap/inc/hal_phy.h new file mode 100644 index 0000000..4804696 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_phy.h @@ -0,0 +1,83 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef HAL_PHY_H +#define HAL_PHY_H + +#include "commontypedef.h" + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ + + + + +/** + \fn void Phy2ApPlatSignalProc(UINT16 sigId) + \brief handle phy to plat ipc signal + \param[in] sigId + \returns void +*/ +void Phy2ApPlatSignalProc(UINT16 sigId, void *msgBdyPtr); + +/** + \fn void halPhyGetDebugModule(CHAR *strName, UINT8 *phyModule) + \brief STRING -> PHY debug module ID + \returns BOOL +*/ +BOOL halPhyGetDebugModule(CHAR *strName, UINT8 *phyModule); + +/** + \fn INT32 halPhySetDebugCfgInfo(UINT16 atHandle, UINT32 phyModId, INT32 *pCfgParams, UINT8 paramNum) + \brief Set PHY debug config + \returns INT32 // 0 - succ, < 0 fail +*/ +INT32 halPhySetDebugCfgInfo(UINT16 atHandle, UINT32 phyModId, INT32 *pCfgParams, UINT8 paramNum); + +/** + \fn void halPhyGetDebugAtStringInfo(CHAR *pAtRspBuf, UINT16 bufLen) + \brief print the PHY debug info + \returns void +*/ +void halPhyGetDebugAtStringInfo(CHAR *pAtRspBuf, UINT16 bufLen); + +#endif /* _HAL_PHY_H */ + diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_pwrkey.h b/PLAT/driver/hal/ec618/ap/inc/hal_pwrkey.h new file mode 100644 index 0000000..f98fa40 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_pwrkey.h @@ -0,0 +1,82 @@ + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_pwrkey.h +* +* Description: header of hal_pwrkey.c, power on/off and software debounce +* +* History: 2021.05.06 initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ + +#ifndef HAL_PWRKEY_H +#define HAL_PWRKEY_H + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ + +#include "pwrkey.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS DECLEARATION * + *----------------------------------------------------------------------------*/ +/** +* @brief pwrKeyIntHandler +* @details call in PwrKey_WakeupIntHandler +* +* @return null +*/ +void pwrKeyIntHandler(void); +/** +* @brief pwrKeyInit +* @details init and enable powerkey +* +* @param workMode + @param pullUpEn + @param dlyCfg + @param Callback + +* @return null +*/ +void pwrKeyInit(pwrKeyWorkMode workMode, bool pullUpEn, pwrKeyDly_t dlyCfg, pwrKeyCallback_t Callback); +/** +* @brief pwrKeyDeinit +* @details deinit and disable powerkey +* +* @param pullUpEn +* @return null +*/ +void pwrKeyDeinit(bool pullUpEn); + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_rfCali.h b/PLAT/driver/hal/ec618/ap/inc/hal_rfCali.h new file mode 100644 index 0000000..96fd100 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_rfCali.h @@ -0,0 +1,316 @@ + + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_rfCali.h +* +* Description: header of hal_rfCali.c +* +* History: 2021.07.28 initiated by Jinxin Huang +* +* Notes: +* +******************************************************************************/ +#ifndef HAL_RF_CALI_H +#define HAL_RF_CALI_H + +#include +//#include "at_util.h" + +#include DEBUG_LOG_HEADER_FILE +#include "debug_trace.h" +#include "shareinfo.h" + +#if defined(__CC_ARM) +#pragma anon_unions +#endif + +/********************************************************************************* +* Defines +*********************************************************************************/ +#define RF_NST_A2C_BUFF_ADDR ShareInfoAPSetPhyCaliMem() // 0xC800 : 50K +#define RF_NST_C2A_BUFF_ADDR (RF_NST_A2C_BUFF_ADDR+0xC800) +#define RF_NST_TEMP_BUFF_ADDR1 (RF_NST_C2A_BUFF_ADDR+0x3C00)//(RF_NST_C2A_BUFF_ADDR+0xC800) // 50K -> 30K +#define RF_NST_TEMP_BUFF_ADDR2 (RF_NST_TEMP_BUFF_ADDR1+0x7800)//(RF_NST_TEMP_BUFF_ADDR1+0xC800) // 50K -> 15K +#define RF_NST_TABLE_BUFF_ADDR (RF_NST_TEMP_BUFF_ADDR2+0x3C00)//(RF_NST_TEMP_BUFF_ADDR2+0xC800) //100K + + +#define RF_CALNST_CRC16_LENGTH_HEX (2) +#define RF_CALNST_CRC16_LENGTH_CHAR (RF_CALNST_CRC16_LENGTH_HEX * 2) +#define RF_CALNST_RSP_HEADER_LENGTH_HEX (4) +#define RF_CALNST_RSP_HEADER_LENGTH_CHAR (RF_CALNST_RSP_HEADER_LENGTH_HEX * 2) +#define RF_CALNST_CRC_ENABLE_IND_BITMASK (0x2) // indicate crc check enable or not 0-disable, 1-enable +#define RF_CALNST_PC_CRC_IND_BITMASK (0x4) // indicate crc check value by pc +#define RF_CALNST_NEXT_DATA_BLOCK_BITMASK (0xF8) // indicate ue next send data block counter +#define RF_CALNST_DATA_END_IND_BITMASK (0x1) // indicate data end, 0-end, 1- not end +#define SIZE_OF_COMMANDID (2) +#define RF_CAL_RSP_HEADER_BYTES (10) // (2+4+4) MT00000000 +#define NO_ERR_DATA_FINISH_NOT (2) +#define NO_ERR_DATA_FINISH (1) +#define NO_ERR (0) +#define ERR_WR_FLASH (-14) +#define ERR_AFC_FAILURE_RC32K_CALI_ERR (-15) +#define ERR_AFC_FAILURE_RC32K_CALI_ERR_TIMEOUT (-16) +#define ERR_WR_FLASH_AT_TYPE (-17) + + +// define RF factory calibration Response message Buffer Maximum Length. Unit: bytes(Hex) +#define RF_FC_RESPONSE_OTHER_LEN (16) // 2(MT)+4(status+errInd)+4(length)+4(crc)+2(\r\n) +#define RF_FC_RESPONSE_ONE_MSG_MAX_HEX_LEN ((8000 - RF_FC_RESPONSE_OTHER_LEN)/2) // 4-finishstatus+errInd, 2-crc +#define RF_FC_RESPONSE_ONE_MSG_MAX_CHAR_LEN (8000) +#define C2A_BUFFER_DATA_LENGTH_IND_SIZE (12) // 4bytes-cmdid,4bytes-retvalue, 4bytes-datalength + +/* AT+ECRFTEST */ +#define ATC_ECRFTEST_0_STR_DEFAULT NULL +#define ATC_ECRFTEST_0_STR_MAX_LEN 8000 /* */ + +/* AT+ECRFNST */ +#define ATC_ECRFNST_0_STR_DEFAULT NULL +#define ATC_ECRFNST_0_STR_MAX_LEN 8000 /* */ + +/* Command Handle in AP*/ + +#define RF_CAL_SELFCAL (0x03) +#define RF_CAL_WRITE_TABLE (0x0f) +#define RF_CAL_READ_TABLE (0x10) +#define RF_CAL_AFC_GET_DATA (0x0e) + +/* AT^PHYDEBUG */ + +/* RF CaliTable struct*/ +#define FCALI_COMN_TABLE_SIZE 96 +#define FCALI_AFC_TABLE_SIZE 5 +#define FCALI_AGC_ONEFREQ_TABLE_SIZE 12 +#define FCALI_FREQ_MAX_NUM 10 +#define RX_IP2_FREQ_MAX_NUM 32 +#define FCALI_APC_FREQCMPST_POINTS_MAX_NUM 20 +#define FCALI_BAND_BTMP_MAX_NUM 20 // Ec618,EC718P +#define FCALI_BAND_BTMP_MAX_NUM_718 11 // EC718 +#define FCALI_POWER_SWP_MAX_NUM 8 +#define FCALI_APC_CENTRA_CMDS_MAX_NUM 100 +#define RX_IP2_TABLE_SIZE (RX_IP2_FREQ_MAX_NUM+1) + +#define FCALI_AGC_ONEBAND_TABLE_SIZE (FCALI_AGC_ONEFREQ_TABLE_SIZE+1)*FCALI_FREQ_MAX_NUM +#define FCALI_APC_ONEBAND_TABLE_SIZE ((FCALI_FREQ_MAX_NUM/2)+(FCALI_FREQ_MAX_NUM*(3+FCALI_APC_FREQCMPST_POINTS_MAX_NUM))+(FCALI_POWER_SWP_MAX_NUM*2)+(FCALI_APC_CENTRA_CMDS_MAX_NUM*2)) +#define NV_HEADER_SIZE 32 +#define SELFCALI_TABLE_MAX_DATA_SIZE (8*1024 - NV_HEADER_SIZE) +#define FCALI_TABLE_MAX_DATA_SIZE (60*1024 - NV_HEADER_SIZE) + +//#define FPGA_DEBUG_ADI + +#define RF_NST_CP_GOTO_WHILE 0x80 +#define RF_NST_CP_DO_NOTHING 0x81 + + +#define FCALI_AFC_TABLE_SIZE 5 + +#ifdef FPGA_DEBUG_ADI +#define RF_RC32K_CALI_THRESHOLD 94 // error = 3125*3% ~= 94 +#define RF_RC32K_CALI_RADIO 3125 // 102.4MHz / 32768 = 3125 +#else +#define RF_RC32K_CALI_THRESHOLD 250 // error = 12500*2% = 250 +#define RF_RC32K_CALI_RADIO 12500 // 409.6MHz / 32768 = 12500 +#endif +#define ABS(a) ((a)>0 ? (a) : -(a)) + +/* AT+ECRFTEST */ +#define ATC_ECRFTEST_0_STR_DEFAULT NULL +#define ATC_ECRFTEST_0_STR_MAX_LEN 8000 /* */ + +/* AT+ECRFNST */ +#define ATC_ECRFNST_0_STR_DEFAULT NULL +#define ATC_ECRFNST_0_STR_MAX_LEN 8000 /* */ + +#define RF_CALNST_PREHANDLE_CRC_ERROR (-2) // preHandle error +#define RF_CALNST_TRANSDATABLOCK_INDEX_ERROR (-3) + + +/********************************************************************************* +* Enums +*********************************************************************************/ +enum +{ + DATA_END = 0, + DATA_NOEND = 1, +}; + +enum +{ + PC_CRC_CHECK_OK = 0, + PC_CRC_CHECK_ERROR = 1, +}; + +enum +{ + CRC_CHECK_DISABLE = 0, + CRC_CHECK_ENABLE = 1, +}; + +enum +{ + RF_FCCALI_TABLE_Start = 0, + RF_FCCALI_TABLE_COMMINFO = 1, + RF_FCCALI_TABLE_AFC = 2, + RF_FCCALI_TABLE_AGC_1 = 3, + RF_FCCALI_TABLE_AGC_2 = 4, + RF_FCCALI_TABLE_RXIP2_1 = 5, + RF_FCCALI_TABLE_RXIP2_2 = 6, + RF_FCCALI_TABLE_APC = 7, + RF_FCCALI_TABLE_END = 8, + RF_FCCALI_TABLE_SELFCAL = 9, +}; + +// EC+ECRFTEST command Index +enum +{ + RF_UNIT_TEST = 0x0, + RF_TX_POWER_FIXED = 0x1, + RF_APT_DAC_FIXED = 0x2, + RF_TX_CMD_FIXED = 0x3, + RF_THERMAL_VAL_GET = 0x4, + RF_TMPRT_COMP_ONOFF = 0x5, + RF_SIGNALING_DEBUG_ENA = 0x6, + RF_VOLTG_COMP_ONOFF = 0x7, + RF_TX_PABIAS_MIPI_REGS_FIXED = 0x8, + RF_FEM_GPIO_SET = 0x9, + RF_RC32K_LATCH_URC = 0x30, + RF_RC32K_GAP_GET = 0x31, + RF_RC32K_PTEST = 0x50, + RF_LDORET_SET = 0x60, + RF_DCDCVPA_ENA_DEBUG = 0x70, +}; + +//extern UINT16 dataPos = C2A_BUFFER_DATA_LENGTH_IND_SIZE; // first 4 bytes is total data length +//extern UINT16 lstDataSize = 0; +//extern UINT16 lstDataAddrOfst = 0; +//extern UINT8 transCount = 0; + +enum +{ + ADC_CVT_IDLE = 0x0, + ADC_CVT_BUSY +}; + + + +enum +{ + RF_DEBUG_CMD_OUT_FLAG_NONE = 0x0, + RF_DEBUG_CMD_OUT_FLAG_REGS, + RF_DEBUG_CMD_OUT_FLAG_SARADC, + RF_DEBUG_CMD_OUT_FLAG_DUPLEXLOSS, +}; + + +/********************************************************************************* +* struct +*********************************************************************************/ + +typedef union +{ + struct + { + UINT16 finishInd :1; // data finish indication, 0-finished, 1-unfinshed + UINT16 crcEnaFlag :1; // crc check enable 0-disable, 1-enable + UINT16 pcCrcErrInd :1; // pc crc check indication, 0-no error, 1-error + UINT16 dbCounter :5; // data blocker counter + UINT16 cmdId :8; // commandId + }; + + UINT16 u16; +}CmdInfo; + + +typedef union +{ + UINT32 u32[FCALI_COMN_TABLE_SIZE]; +}RfFcComInfos; // 384 bytes + +typedef union +{ + UINT32 u32[FCALI_AFC_TABLE_SIZE]; +}RfAfcTable; // 20 bytes + +typedef union +{ + UINT32 u32[FCALI_AGC_ONEBAND_TABLE_SIZE]; + +}RfAgcOneBandTable; // 520Bytes + +typedef union +{ + UINT32 u32[RX_IP2_TABLE_SIZE]; +}RfRxIp2Table; // 132Bytes + +typedef union +{ + UINT32 u32[FCALI_APC_ONEBAND_TABLE_SIZE]; +}RfApcOneBandTable; // 2*10+92*10+64+800 = 1804 bytes + +typedef struct // for ec618, ec718p +{ + RfFcComInfos comInfo; + RfAfcTable afc; + RfAgcOneBandTable agcTb1[FCALI_BAND_BTMP_MAX_NUM]; + RfAgcOneBandTable agcTb2[FCALI_BAND_BTMP_MAX_NUM]; + RfRxIp2Table rxIp2Tb1; + RfRxIp2Table rxIp2Tb2; + RfApcOneBandTable apc[FCALI_BAND_BTMP_MAX_NUM]; +}RfFcaliTable; + +typedef struct // for ec718 +{ + RfFcComInfos comInfo; + RfAfcTable afc; + RfAgcOneBandTable agcTb1[FCALI_BAND_BTMP_MAX_NUM_718]; + RfRxIp2Table rxIp2Tb1; + RfRxIp2Table rxIp2Tb2; + RfApcOneBandTable apc[FCALI_BAND_BTMP_MAX_NUM_718]; +}RfFcaliTable718; + +typedef struct +{ + __IO UINT16 cvtStatus; + __IO UINT16 cvtCode; +}RfCaliAdcStatus; + +//define Afc info sections +typedef union RfAfcTableAp_Tag +{ + struct + { + UINT32 freq100KHz; // unit:100KHz + INT32 dcxoDeltaFreq; + UINT32 dcxoCbank; + INT16 dcxoT0; // fwl=4, 1/16 degree. + UINT16 dcxoT0Code; + UINT32 rc32KCap; + }; + + UINT32 u32[FCALI_AFC_TABLE_SIZE]; +}RfAfcTableAp; // 20 bytes + +void atRfNstRspInd(INT32 chanId, UINT8 *dataOutReq, UINT32 outLen, BOOL phyRspEna); +INT32 ResumeTrans(UINT16 dataBlockCounter,UINT8* dataOut, UINT16* lenOut); +void atRfCaliGetThermal(RfAfcTableAp *pAfcTb); +INT32 atRf32KCapCali(UINT32 *cTuneRst); +BOOL atRf32KEnaGet(void); +INT32 RfAtNstCmdPreHandle(UINT16 atHandle, UINT8* data, UINT16 length, UINT8* dataOut, UINT16* lenOut); +UINT16 crc16_ccitt(void *dataptr, int len); +void RfHexToChar(UINT8* inHex); +void RfHexToString(UINT8* outStr, UINT8* rawData, UINT16 rawDataLen); +INT32 RfFcWriteTable(UINT16 *pDataIn, UINT16 srcHdr); +void RfAtTestCmd(UINT16 atHandle, UINT8* dataIn, UINT16 length); +void RfRc32KTestTmExp(void* arg); +void atRfNstRspDebug(INT32 chanId); +BOOL RfOpenApiDcdcVpaCfg (UINT8 ena, UINT8 voltage); +void RfCmiReqNoAt(UINT16 primId, UINT16 primSize, void *primBody); +//void RfOpenApiDcdcVpaRsp ( void ); + +#endif + diff --git a/PLAT/driver/hal/ec618/ap/inc/hal_uartDump.h b/PLAT/driver/hal/ec618/ap/inc/hal_uartDump.h new file mode 100644 index 0000000..236df6b --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/inc/hal_uartDump.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * + * Copy right: 2022-, Copyrigths of AirM2M Ltd. + * File name: hal_uartDump.h + * Description: header file for dumping info through UART when exception occurs + * History: Rev1.0 2022-1-17 + * + ****************************************************************************/ + +#ifndef _HAL_UART_DUMP_H +#define _HAL_UART_DUMP_H + +/** + \brief Initialize uart dump port + \details + This API will use the setting(pinmux, baudrate) if UART has already been initialized, + otherwise custom settting should be supplied properly to make uart dump work + */ +void HAL_UartDumpPortInit(void); + +/** + \brief Check validation of uart dump port + \return true if current dump port is valid, otherwise false + \note Internal use for exception code + */ +bool HAL_UartDumpPortCheck(void); + +/** + \brief Send data to uart dump port in polling way + \param[in] data Pointer to buffer with data to be sent to + \param[in] num Number of data items to send + \param[in] timeout_us timeout value in unit of us + \return num of data items sent in the internal of timeout + \note Internal use for exception code + */ +uint32_t HAL_UartDumpPortSend(const uint8_t *data, uint32_t num, uint32_t timeout_us); + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_UART_DUMP_H */ diff --git a/PLAT/driver/hal/ec618/ap/src/hal_adc.c b/PLAT/driver/hal/ec618/ap/src/hal_adc.c new file mode 100644 index 0000000..296e591 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_adc.c @@ -0,0 +1,251 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: hal_adc.c + * Description: EC618 adc hal driver source file + * History: Rev1.0 2019-12-12 + * Rev1.1 2020-02-29 Add api to get internal thermal temperature + * + ****************************************************************************/ + +#include "adc.h" +#include "hal_trim.h" +#include "cmsis_os2.h" + +typedef struct _adc_conversion_result +{ + volatile uint32_t rawCode; + osSemaphoreId_t sem; +} adc_conversion_result_t; + +static adc_conversion_result_t g_adcVbatResult = {0}; +static adc_conversion_result_t g_adcThermalResult = {0}; + +/** + \fn void ADC_VbatCallback(uint32_t result) + \brief Vbat channel callback + \return +*/ +static void ADC_VbatCallback(uint32_t result) +{ + g_adcVbatResult.rawCode = result; + + if(g_adcVbatResult.sem) + { + osSemaphoreRelease(g_adcVbatResult.sem); + } +} + +/** + \fn void ADC_ThermalCallback(uint32_t result) + \brief Thermal channel callback + \return +*/ +static void ADC_ThermalCallback(uint32_t result) +{ + g_adcThermalResult.rawCode = result; + + if(g_adcThermalResult.sem) + { + osSemaphoreRelease(g_adcThermalResult.sem); + } +} + +/** + \breif Calibarte ADC raw sample code + \param[in] input ADC conversion raw register value + \return calibrated voltage in unit of mV + \details + + The calibration data stored in EFUSE is two sample values of 500mV and 900mV when Vref is set to 1200mV. + The calibration process can be deduced below with 3 equations: + + Given: + Gain * Code500 + Offset = 500 (a) + Gain * Code900 + Offset = 900 (b) + To calculate: + Gain * Input + Offset (c) where Input is actual conversion data from ADC + + We can get Gain and Offset from equation (a) and (b): + + Gain = 400 / (Code900 - Code500) + Offset = 500 - 400 / (Code900 -Code500) * Code500 + + Put them into equation (c), Result is: + + Result = 400 * (Input - Code500) / (Code900 - Code500) + 500 + + Round the result in the way: round(a/b) = (a + b/2) / b + + Final result = (400 * (Input - Code500) + (Code900 - Code500) / 2) / (Code900 - Code500) + 500 + + In case of EFUSE value is invalid, we have to set Gain value to be 1200 / 4096 and Offset value to be 0. + + So Result = Input * 1200 / 4096, after round + Final result = ((Input * 1200) + 2048) / 4096 + + */ +uint32_t HAL_ADC_CalibrateRawCode(uint32_t input) +{ + int32_t temp = 0; + int32_t diff = 0; + + AdcEfuseCalCode_t * efuseCalcodePtr = trimAdcGetCalCode(); + + // Resulotion is 12-bits + input &= 0xFFFU; + + // EFUSE value is invalid + if((efuseCalcodePtr->code500 == 0) || (efuseCalcodePtr->code900 == 0)) + { + return ((input * 1200000) + 2048) / 4096; + } + else + { + temp = input - efuseCalcodePtr->code500; + diff = efuseCalcodePtr->code900 - efuseCalcodePtr->code500; + temp = (400000 * temp + (diff >> 1)) / diff + 500000; + + return (temp < 0) ? 0 : temp; + } + +} + +/** + \breif Convert ADC thermal channel raw sample to temperature in unit of centidegree + \param[in] input ADC thermal channel register value + \return temperature in unit of centidegree + \details + + The empirical equation between temperature and ADC thermal ram sample is: + + T = k * Input + T0 (a) + + where k is slope and its value is approximately -0.16, T0 is bias and its value ranges from 400 to 500, + Input is actual conversion data from ADC + + The actural k is deduced from EFUSE values with equation: + + k = -(1000 / 1.731 / 0.95) * (0.4 / (Code900 - Code500)) (b) + + where Code900 and Code500 are ADC calibration data stored in EFUSE, refer to previous comment in \ref HAL_ADC_CalibrateRawCode + + T0 = Toffset - k * Tcode (c) + + where Toffset and Tcode are Thermal calibartion data also stored in EFUSE and Toffset is a number with accuracy of 2 decimal digits + + To get rid of float number calculation and balance accuracy loss, we here amplify the equation (a) by 4000, + + that's T = (4000 * k * Input + 4000 * T0) / 4000 (d) + + Combine equation (c), we get + + T = (4000 * k * (Input - Tcode) + 4000 * Toffset) / 4000 (e) + + Put equation (b) into (e) and note that Toffset has accuracy of 2 decimal digits, perform some simplifying we get + + T = (-972970 / (Code900 - Code500) * (Input - Tcode) + Toffset * 1000) / 4000 (f) + + Also, round the result in the way: round(a/b) = (a + b/2) / b if a > 0 and round(a/b) = (a - b/2) / b if a < 0 + + The final result is: + + T = (-972970 / (Code900 - Code500) * (Input - Tcode) + Toffset * 1000 + 2000) / 4000 (g) + + */ +int32_t HAL_ADC_ConvertThermalRawCodeToTemperatureHighAccuracy(uint32_t input) +{ + static int32_t gain = 0; + + int32_t temp; + + AdcEfuseCalCode_t * efuseCalcodePtr = trimAdcGetCalCode(); + AdcEfuseT0Code_t * efuseT0CodePtr = trimAdcGetT0Code(); + + // Resulotion is 12-bits + input &= 0xFFFU; + + if(gain == 0) + { + gain = -972970 / (int32_t)(efuseCalcodePtr->code900 - efuseCalcodePtr->code500); + } + + temp = gain * (int32_t)(input - efuseT0CodePtr->codet0) + (int32_t)(efuseT0CodePtr->t0 * 1000); + + return (temp > 0) ? (temp + 2000) / 4 : (temp - 2000) / 4; + +} + + +int32_t HAL_ADC_ConvertThermalRawCodeToTemperature(uint32_t input) +{ + return HAL_ADC_ConvertThermalRawCodeToTemperatureHighAccuracy(input) / 1000; +} + +int32_t HAL_ADC_SampleVbatVoltage(uint32_t timeout_ms) +{ + AdcConfig_t adcConfig; + int ret = -1; + + g_adcVbatResult.sem = osSemaphoreNew(1U, 0, NULL); + + // semphore created succussful + if(g_adcVbatResult.sem != NULL) + { + ADC_getDefaultConfig(&adcConfig); + adcConfig.channelConfig.vbatResDiv = ADC_VBAT_RESDIV_RATIO_3OVER16; + ADC_channelInit(ADC_CHANNEL_VBAT, ADC_USER_APP, &adcConfig, ADC_VbatCallback); + + ADC_startConversion(ADC_CHANNEL_VBAT, ADC_USER_APP); + + ret = osSemaphoreAcquire(g_adcVbatResult.sem, timeout_ms); + + ADC_channelDeInit(ADC_CHANNEL_VBAT, ADC_USER_APP); + + if(ret == osOK) + { + ret = HAL_ADC_CalibrateRawCode(g_adcVbatResult.rawCode); + // amplify the result by the reciprocal of div ratio + ret = ret * 16 / 3; + ret = (ret + 500) / 1000; // uV -> mV + } + + osSemaphoreDelete(g_adcVbatResult.sem); + } + + return ret; + +} + +int32_t HAL_ADC_GetThermalTemperature(uint32_t timeout_ms, int32_t* temperatruePtr) +{ + int ret = -1; + + if(temperatruePtr == NULL) + return -1; + + g_adcThermalResult.sem = osSemaphoreNew(1U, 0, NULL); + + // semphore created succussful + if(g_adcThermalResult.sem != NULL) + { + ADC_channelInit(ADC_CHANNEL_THERMAL, ADC_USER_APP, NULL, ADC_ThermalCallback); + + ADC_startConversion(ADC_CHANNEL_THERMAL, ADC_USER_APP); + + ret = osSemaphoreAcquire(g_adcThermalResult.sem, timeout_ms); + + ADC_channelDeInit(ADC_CHANNEL_THERMAL, ADC_USER_APP); + + if(ret == osOK) + { + *temperatruePtr = HAL_ADC_ConvertThermalRawCodeToTemperature(g_adcThermalResult.rawCode); + } + + osSemaphoreDelete(g_adcThermalResult.sem); + } + + return ret; + +} + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_alarm.c b/PLAT/driver/hal/ec618/ap/src/hal_alarm.c new file mode 100644 index 0000000..7d9ea00 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_alarm.c @@ -0,0 +1,350 @@ + + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_alarm.c +* +* Description: api for battery low and high temperature interrupt process +* +* History: initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include "hal_alarm.h" +#include DEBUG_LOG_HEADER_FILE +#include "alarm.h" +#include "FreeRTOS.h" +#include "cmsis_os2.h" +#include "queue.h" +#include "ic.h" +#include "ec618.h" +#include "slpman.h" +#include "cms_comm.h" +#ifdef FEATURE_AT_ENABLE +#include "atec_alarm_cnf_ind.h" +#endif + +extern void delay_us(uint32_t us); + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +#define ALARM_TASK_STATK_SIZE 512 +#define ALARM_EVENT_QUEUE_SIZE 2 + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ +typedef struct { + alarmMsgType_e msgType; + alarmMsgInfo_e msgInfo; +} alarmQueueMsg_t; + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ +static QueueHandle_t alarmQueueHandle; +static bool alarmTaskExist = false; +static vbatLowCallback_t gAlarmVoltCb = NULL; +static vbatLowCallback_t gAlarmThermCb = NULL; +static alarmParamCfg_t gAlmParamDataBase; + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ +static void ALM_enterLowPowerStatePrepare(void* pdata, slpManLpState state) +{ + switch (state) + { + case SLPMAN_SLEEP1_STATE: + break; + default: + break; + } +} + +static void ALM_exitLowPowerStateRestore(void* pdata, slpManLpState state) +{ + switch (state) + { + case SLPMAN_SLEEP1_STATE: + if(gAlmParamDataBase.voltEnable == true) + { + alarmVBatInit(gAlmParamDataBase.voltThd); + } + if(gAlmParamDataBase.thermEnable == true) + { + alarmThmHighInit(gAlmParamDataBase.thermThd,gAlmParamDataBase.hysterThd); + } + if((gAlmParamDataBase.voltEnable == true) || (gAlmParamDataBase.thermEnable == true)) + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, ALM_exitLowPowerStateRestore_1, P_VALUE, "Alarm Func Init: %d,%e - %d,%e,%e", gAlmParamDataBase.voltEnable, gAlmParamDataBase.voltThd, gAlmParamDataBase.thermEnable, gAlmParamDataBase.thermThd, gAlmParamDataBase.hysterThd); + break; + default: + break; + } + +} + +static void thmHigh_interruptHandler(void) +{ + alarmQueueMsg_t msg; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint8_t thm_hi = alarmThmGetIntIndicate(); + + if(thm_hi) + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, thmHigh_interruptHandler_0, P_WARNING, "Thm Interrupt Enter: Temperature too high"); + else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, thmHigh_interruptHandler_1, P_VALUE, "Thm Interrupt Enter: Temperature below threshold"); + + if(apmuGetImageType() == 1) + { + msg.msgType = ALARM_TYPE_THERM; + if(thm_hi == 1) + msg.msgInfo = ALARM_INFO_UPWARD; + else + msg.msgInfo = ALARM_INFO_DOWNWARD; + + if (alarmQueueHandle) + { + if (pdTRUE != xQueueSendFromISR(alarmQueueHandle, &msg, &xHigherPriorityTaskWoken)) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, thmHigh_interruptHandler_2, P_VALUE, "Alarm message send in isr error"); + } + } + else + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, thmHigh_interruptHandler_3, P_VALUE, "Alarm message queue not ready in isr"); + } + + if(xHigherPriorityTaskWoken) + { + portYIELD_FROM_ISR(pdTRUE); + } + } + else + { + if(gAlarmThermCb!=NULL) + gAlarmThermCb(thm_hi); + } + +} + + +static void vbatLow_interruptHandler(void) +{ + alarmQueueMsg_t msg; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint8_t vbat_info = alarmVBatGetIntIndicate(); + + if(vbat_info == 0) + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, vbatLow_interruptHandler_0, P_WARNING, "Vbat Interrupt Enter: Bat volatage too low"); + else + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, vbatLow_interruptHandler_1, P_VALUE, "Vbat Interrupt Enter: Bat volatage above threshold"); + + if(apmuGetImageType() == 1) + { + msg.msgType = ALARM_TYPE_VOLT; + if(vbat_info == 1) + msg.msgInfo = ALARM_INFO_UPWARD; + else + msg.msgInfo = ALARM_INFO_DOWNWARD; + + if (alarmQueueHandle) + { + if (pdTRUE != xQueueSendFromISR(alarmQueueHandle, &msg, &xHigherPriorityTaskWoken)) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, vbatLow_interruptHandler_2, P_VALUE, "Alarm message send in isr error"); + } + } + else + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, vbatLow_interruptHandler_3, P_VALUE, "Alarm message queue not ready in isr"); + } + + if(xHigherPriorityTaskWoken) + { + portYIELD_FROM_ISR(pdTRUE); + } + } + else + { + if(gAlarmVoltCb!=NULL) + gAlarmVoltCb(vbat_info); + } + +} + +static void alarmIndUrcBcast(alarmMsgType_e msgType, alarmInfo *info) +{ +#ifdef FEATURE_AT_ENABLE + MWNvmCfgAlarmParam param; + + mwNvmCfgGetAlarmParam(¶m); + if(!param.voltUrcEnable) return; + + uint32_t primId = (msgType == ALARM_TYPE_VOLT) ? APPL_ALARM_VOLT_IND : APPL_ALARM_THERM_IND; + applSendCmsInd(BROADCAST_IND_HANDLER, APPL_ALARM, primId, sizeof(alarmInfo), (void *)info); +#endif +} + +static void alarmTask(void *arg) +{ + alarmQueueMsg_t msg; + alarmInfo info; + + while(1) + { + if (xQueueReceive(alarmQueueHandle, &msg, portMAX_DELAY)) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, alarmTask_1, P_VALUE, "alarmTask: type=%d, info=%d", msg.msgType, msg.msgInfo); + + info.value = msg.msgInfo; + switch(msg.msgType) + { + case ALARM_TYPE_VOLT: + { + alarmIndUrcBcast(ALARM_TYPE_VOLT, &info); + + if(gAlarmVoltCb!=NULL) + gAlarmVoltCb(msg.msgInfo); + break; + } + case ALARM_TYPE_THERM: + { + alarmIndUrcBcast(ALARM_TYPE_THERM, &info); + + if(gAlarmThermCb!=NULL) + gAlarmThermCb(msg.msgInfo); + break; + } + + default: + break; + } + } + } +} + +static void alarmThreadInit(void) +{ + if(alarmTaskExist == false) + { + alarmTaskExist = true; + + alarmQueueHandle = xQueueCreate(ALARM_EVENT_QUEUE_SIZE, sizeof(alarmQueueMsg_t)); + if(alarmQueueHandle == NULL) + { + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, alarmThreadInit_1, P_VALUE, "Alarm task queue init error"); + } + + osThreadAttr_t task_attr; + memset(&task_attr,0,sizeof(task_attr)); + task_attr.name = "almTask"; + task_attr.stack_size = ALARM_TASK_STATK_SIZE; + task_attr.priority = osPriorityNormal1; + osThreadNew(alarmTask, NULL, &task_attr); + } +} + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ +void alarmVBatInit(uint16_t voltThd) +{ + if(apmuGetImageType() == 1) + alarmThreadInit(); + + alarmVBatHwInit(voltThd); + delay_us(10); + XIC_ClearPendingIRQ(PXIC0_PM_VBAT_LOW_IRQn); + XIC_SetVector(PXIC0_PM_VBAT_LOW_IRQn, vbatLow_interruptHandler); + XIC_EnableIRQ(PXIC0_PM_VBAT_LOW_IRQn); +} + + +void alarmVBatDeinit(void) +{ + XIC_DisableIRQ(PXIC0_PM_VBAT_LOW_IRQn); + alarmVBatHwDeinit(); + delay_us(10); + XIC_ClearPendingIRQ(PXIC0_PM_VBAT_LOW_IRQn); +} + +void alarmThmHighInit(alarmThmThd thmThd, alarmHysteresisRange range) +{ + if(apmuGetImageType() == 1) + alarmThreadInit(); + + alarmThmHwInit(thmThd, range); + delay_us(10); + XIC_ClearPendingIRQ(PXIC1_THM_HI_IRQn); + XIC_SetVector(PXIC1_THM_HI_IRQn, thmHigh_interruptHandler); + XIC_EnableIRQ(PXIC1_THM_HI_IRQn); + +} + +void alarmThmHighDeinit(void) +{ + XIC_DisableIRQ(PXIC1_THM_HI_IRQn); + alarmThmHwDeinit(); + delay_us(10); + XIC_ClearPendingIRQ(PXIC1_THM_HI_IRQn); + +} + + +void alarmFuncInit(void) // this function also call in paging +{ + alarmParamCfg_t cfg; + cfg.voltEnable = true; + cfg.voltThd = VOLT_THRESHOLD_2200; + cfg.thermEnable = true; + cfg.thermThd = THM_THRESHOLD_LEVEL3; + cfg.hysterThd = THM_HYSTERESIS_40; + + ECPLAT_PRINTF(UNILOG_PLA_DRIVER, alarmFuncInit_1, P_VALUE, "Alarm Func Init: %d,%e - %d,%e,%e", cfg.voltEnable, cfg.voltThd, cfg.thermEnable, cfg.thermThd, cfg.hysterThd); + + if(cfg.voltEnable) + alarmVBatInit(cfg.voltThd); + + if(cfg.thermEnable) + alarmThmHighInit(cfg.thermThd,cfg.hysterThd); + + gAlarmThermCb = NULL; + gAlarmVoltCb = NULL; + + if(apmuGetImageType() == 1) + { + #ifdef PM_FEATURE_ENABLE + slpManRegisterPredefinedBackupCb(SLP_CALLBACK_ALM_MODULE, ALM_enterLowPowerStatePrepare, NULL); + slpManRegisterPredefinedRestoreCb(SLP_CALLBACK_ALM_MODULE, ALM_exitLowPowerStateRestore, NULL); + memcpy(&gAlmParamDataBase, &cfg, sizeof(alarmParamCfg_t)); + #endif + } + +} + + + + + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_charge.c b/PLAT/driver/hal/ec618/ap/src/hal_charge.c new file mode 100644 index 0000000..d6227aa --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_charge.c @@ -0,0 +1,117 @@ + + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: hal_charge.c +* +* Description: api for charge status detect +* +* History: initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include "hal_charge.h" +#include"ec618.h" +#include "FreeRTOS.h" +#include DEBUG_LOG_HEADER_FILE +#include "cmsis_os2.h" + + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ +osTimerId_t chargeMonTimer; +static uint8_t chargeMonTimerId = 0; +chargeStatusCb chargeStatusCbFunc; + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ +static void chargeMonTimerExp(void *argument) +{ + chargeStatus_e chargeStatus = chargeGetCurStatus(); + if(chargeStatusCbFunc != NULL) + chargeStatusCbFunc(chargeStatus); +} +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ +void chargeIntHandler(void) +{ + chargeStatus_e chargeStatus = chargeGetCurStatus(); + ECPLAT_PRINTF(UNILOG_PMU, chargeIntHandler_1, P_VALUE, "Charger Int Enter, Status Update = %d", chargeStatus); + if(chargeStatusCbFunc != NULL) + chargeStatusCbFunc(chargeStatus); +} + + +void chargeDetectInit(chargeStatusCb cb, bool monitorEn, uint32_t sample_dly) +{ + chargeHwInit(); + + chargeStatusCbFunc = cb; + + chargeStatus_e chargeStatus = chargeGetCurStatus(); + + ECPLAT_PRINTF(UNILOG_PMU, chargeDetectInit_1, P_VALUE, "Charger Detect Init, Status Update = %d", chargeStatus); + + if(chargeStatusCbFunc != NULL) + chargeStatusCbFunc(chargeStatus); + + if(monitorEn) + { + if(chargeMonTimer == NULL) + { + chargeMonTimer = osTimerNew((osTimerFunc_t)chargeMonTimerExp, osTimerPeriodic, (void *)(uint32_t)chargeMonTimerId, NULL); + } + osTimerStart(chargeMonTimer, sample_dly); + } + NVIC_EnableIRQ(ChrgpadWakeup_IRQn); + +} + + +void chargeDetectDeinit(void) +{ + chargeHwDeinit(); + NVIC_DisableIRQ(ChrgpadWakeup_IRQn); + + chargeStatusCbFunc = NULL; + + if(chargeMonTimer != NULL) + { + if(osTimerIsRunning(chargeMonTimer)) + { + osTimerStop(chargeMonTimer); + } + osTimerDelete(chargeMonTimer); + chargeMonTimer = NULL; + } +} + + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_dumpMedia.c b/PLAT/driver/hal/ec618/ap/src/hal_dumpMedia.c new file mode 100644 index 0000000..9cd4643 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_dumpMedia.c @@ -0,0 +1,443 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename:hal_dumpMedia.c +* +* Description: used to provid adapt API for ram dump +* +* History: initiated by bchang +* +* Notes: +* +******************************************************************************/ + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include "RTE_Device.h" +#include "Driver_Common.h" +#include "usbmst_top.h" +#include "uldp.h" +#if FEATURE_CCIO_ENABLE +#include "usb_device.h" +#endif +//#include "usbc_ctrl.h" +#include "uart.h" + + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + + + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ + + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ +extern int32_t uldpUsbClrCmpltFlg(usbmst_top_st *ptop,uint8_t epNum); +extern void delay_us(uint32_t us); +extern uint32_t usbc_dev_int_handler (void); +extern int32_t uldpUsbGetCmpltFlg(usbmst_top_st *ptop); +extern int32_t ulog_vcom_chkdtr( void ); + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ + + +#if (RTE_USB_EN == 1) + +/** + \fn usbPollingRecv(uint32_t epNum, uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief used to recv data from host via polling, uldp is still involved + \param[in] epNum ep number for recv + \param[in] data data pointer to store recv data + \param[in] num recv data length + \param[in] timeout_us timeout value when nothing recv + \note only called in eeh dump procedure + */ +static uint32_t usbPollingRecv(uint32_t epNum, uint8_t *data, uint32_t num, uint32_t timeout_us) +{ + uint32_t rbIdx=0,avaSize=0; + uint32_t rbAddr,rbLen; + + if(num == 0) + return num; + + //wait until cmplt flag set for epNum or timeout + while((!(uldpUsbGetCmpltFlg(NULL)&(1<>4)&0xf)); + + //usbc_ctrl_flush_txfifo(&t_usbc_core_top, epNum); + //usbc_ctrl_flush_rxfifo(&t_usbc_core_top); + + usbUldpEehInit((epNum&0xf));//low 4 bit is outep num + #endif + + } + +} + + +/** + \fn eehDumpMediaFlush(uint32_t instance) + \brief used to flush FIFO, only valid for UART now + \param[in] instance UART instance + \note only called in eeh dump procedure +*/ +void eehDumpMediaFlush(uint32_t instance) +{ + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + UART_flush(instance);//flush both TX/RX FIFO + } + else//USB + { + // TBD: no need to flush, flushed when init + + } + +} + +/** + \fn eehDumpMediaPurgeRx(uint32_t instance) + \brief used to flush FIFO, only valid for UART now + \param[in] instance UART instance + \note only called in eeh dump procedure +*/ +void eehDumpMediaPurgeRx(uint32_t instance) +{ + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + UART_purgeRx(instance);//flush both RX FIFO + } + else//USB + { + // TBD: no need to flush, flushed when init + + } + +} + +/** + \fn eehDumpMediaRecv(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief used to recv data from host via polling, uldp is still involved + \param[in] instance ep number or uart instance for recv + \param[in] data data pointer to store recv data + \param[in] num recv data length + \param[in] timeout_us timeout value when nothing recv + \note only called in eeh dump procedure + */ +uint32_t eehDumpMediaRecv(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) +{ + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + return UART_receive(instance, data, num, timeout_us); + } + else//USB + { + #if (RTE_USB_EN == 1) + return usbPollingRecv(instance, data, num, timeout_us); + #else + return 0; + #endif + } + +} + + +/** + \fn eehDumpMediaSend(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) + \brief used to recv data from host via polling, uldp is still involved + \param[in] instance ep number or uart instance for recv + \param[in] data data pointer to send + \param[in] num send data length + \param[in] timeout_us timeout value when nothing recv + \note only called in eeh dump procedure + */ +uint32_t eehDumpMediaSend(uint32_t instance, uint8_t *data, uint32_t num, uint32_t timeout_us) +{ + + if(uniLogGetPherType() == UART_0_FOR_UNILOG) + { + return UART_send(instance, data, num, timeout_us); + } + else//USB + { + #if (RTE_USB_EN == 1) + #if 0 + //check ep0 recv data from uldp + if((uldpUsbGetCmpltFlg(NULL)&0x1) == 0x1) + { + uldpUsbEp0RecvHandle(); + } + #endif + // to be added: call USB polling send API + extern int ulog_vcom_polling_write(uint32_t instance, uint8_t *data, uint16_t num, uint32_t timeout_us); + return ulog_vcom_polling_write(instance, data, (uint16_t)num, timeout_us); + #else + return 0; + #endif + } + +} + + + + +/** + \fn eehDumpMediaPollingEp0(uint32_t loopCnt, uint32_t loopInr) + \brief polling EP0 ctrl info and handle it, e.g. VCOM open + \param[in] loopCnt how many loop times + \param[in] loopInr internalval for each loop + \note only called in eeh dump procedure + host will first send request(set/get line coding etc) on every interface(not by EPAT) + then EPAT will open VCOM + serial_vcom1_chkdtr will check setcontrolline state is active + after active, host will not stop and will send more request, + that's why we will loop more times after active + + !!but if host send addtional request after this API, will not response.!! + */ +void eehDumpMediaPollingEp0(uint32_t loopCnt, uint32_t loopInr) +{ + #if (RTE_USB_EN == 1) + uint32_t loop = 200; + while(loopCnt--) + { + //check ep0 recv data from uldp + if((uldpUsbGetCmpltFlg(NULL)&0x1) == 0x1) + { + uldpUsbEp0RecvHandle(); + } + + //delay_us(loopInr); + + //loop if any pending usb int + usbc_dev_int_handler( ); + + delay_us(loopInr); + + + if((loopCnt%500 == 0)&&(uniLogGetPherType() == USB_FOR_UNILOG))//add log per 500ms to avoid host suspend + { + ECPLAT_PRINTF(UNILOG_CCIO, eehDumpMediaPollingEp0_1, P_INFO, "eehDumpMediaPollingEp0:avoid host suspend %d",loopCnt); + uniLogForceOut(true); + } + + if(ulog_vcom_chkdtr()==1) + { + + while(loop--) + { + //check ep0 recv data from uldp + if((uldpUsbGetCmpltFlg(NULL)&0x1) == 0x1) + { + uldpUsbEp0RecvHandle(); + } + //delay_us(loopInr); + //loop if any pending usb int + usbc_dev_int_handler( ); + + delay_us(loopInr); + } + + + break; + + } + } + #endif +} + + + +/** + \fn eehDumpMediaPollingRndisHalt(uint32_t loopCnt, uint32_t loopInr) + \brief request rndis halt to host, need polling send sucesss or timeout + \param[in] loopCnt how many loop times + \param[in] loopInr internalval for each loop + \note only called in eeh dump procedure + */ +int32_t eehDumpMediaPollingRndisHalt(uint32_t loopCnt, uint32_t loopInr) +{ + #if (RTE_USB_EN == 1) + int32_t ret = -1; + uint16_t cntBefore = 0, cntAfter = 0; + + extern uint16_t get_rndis_func_notifyok_cnt( void ); + extern int rndis0_sig_set_halt(void); + + //step1: loop request send ok + while(loopCnt--) + { + ret=rndis0_sig_set_halt(); + if(ret == 0) + break; + delay_us(loopInr); + + + if((loopCnt%500 == 0)&&(uniLogGetPherType() == USB_FOR_UNILOG))//add log per 500ms to avoid host suspend + { + ECPLAT_PRINTF(UNILOG_CCIO, eehDumpMediaPollingRndisHalt_0, P_INFO, "eehDumpMediaPollingRndisHalt0:avoid host suspend %d",loopCnt); + uniLogForceOut(true); + } + } + + if(ret < 0) + return ret ; + + cntBefore=get_rndis_func_notifyok_cnt(); + + + while(loopCnt--) + { + //loop if any pending usb int + usbc_dev_int_handler( ); + + delay_us(loopInr); + + if((loopCnt%500 == 0)&&(uniLogGetPherType() == USB_FOR_UNILOG))//add log per 500ms to avoid host suspend + { + ECPLAT_PRINTF(UNILOG_CCIO, eehDumpMediaPollingRndisHalt_1, P_INFO, "eehDumpMediaPollingRndisHalt1:avoid host suspend %d",loopCnt); + uniLogForceOut(true); + } + + cntAfter = get_rndis_func_notifyok_cnt(); + + if(cntAfter > cntBefore) + return 0; + } + + return -1; + + #else + return 0; + #endif + +} + + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_i2s.c b/PLAT/driver/hal/ec618/ap/src/hal_i2s.c new file mode 100644 index 0000000..28d05fc --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_i2s.c @@ -0,0 +1,384 @@ +/**************************************************************************** + * + * Copy right: 2019-, Copyrigths of AirM2M Ltd. + * File name: hal_i2s.c + * Description: EC618 i2s hal driver source file + * History: Rev1.0 2021-9-18 + * + ****************************************************************************/ + +#include "hal_i2s.h" + +void es8388MasterInit(void); +void es8388SlaveInit(void); +void nau88c22SlaveInit(void); +void nau88c22MasterInit(void); +void es8311MasterInit(void); +void es8311SlaveInit(void); + +extern i2sDrvInterface_t i2sDrvInterface0; +extern i2sDrvInterface_t i2sDrvInterface1; + +static i2sDrvInterface_t *i2sDrv = &CREATE_SYMBOL(i2sDrvInterface, 0); // Choose i2s0 + +extern i2sDataFmt_t i2sDataFmt; +extern i2sSlotCtrl_t i2sSlotCtrl; +extern i2sBclkFsCtrl_t i2sBclkFsCtrl; +extern i2sCtrl_t i2sCtrl; +extern i2sDmaCtrl_t i2sDmaCtrl; + + +static codecType_e codecType; // Record codec type +static i2sMode_e i2sMode; + +void HAL_normalIOVoltSet(i2sIOVolSel_t sel) +{ + if(sel <= VOL_2_00V) + { + *(uint32_t*)0x4d020018 = (0 | (1<<2) | (0<<1)); // HW_AonRegStaticDig->ldoio_33_18_sel + *(uint32_t*)0x4d040308 = (sel-0*8); // HW_PmuApRegs->ldo_io_cfg + } + else if(sel <= VOL_3_00V) + { + *(uint32_t*)0x4d020018 = 1; + *(uint32_t*)0x4d040308 = (sel-1*8); + } + else if(sel <= VOL_3_40V) + { + *(uint32_t*)0x4d020018 = (0 | (1<<2) | (1<<1)); + *(uint32_t*)0x4d040308 = (sel-2*8); + } +} + +void HAL_aonIOVoltSet(i2sIOVolSel_t sel) +{ + uint8_t tmp = 0; + + if(sel <= VOL_2_00V) + { + tmp = sel << 2; + } + else if(sel <= VOL_3_00V) + { + tmp = ((sel-8) << 2) | 0x2; + } + else if(sel <= VOL_3_40V) + { + tmp = ((sel-16) << 2) | 0x1; + } + + *(uint32_t*)0x4d020054 = tmp; //HW_AonRegStaticAna->ldo_aonio_cfg + + *(uint32_t*)0x4d020150 = 0x7; // Enable AON gpio as wakeup pin + *(uint32_t*)0x4d020170 = 0x1; // Enable AON IO +} + + +// Register +void HAL_I2sInit(i2sPowerCtrl_e powerCtrl, i2sCbFunc_fn txCb, i2sCbFunc_fn rxCb) +{ + i2sDrv->init(txCb, rxCb); + + switch (powerCtrl) + { + case I2S_CLK_DISABLE: + i2sDrv->powerCtrl(I2S_POWER_OFF); + break; + + case I2S_CLK_ENABLE: + i2sDrv->powerCtrl(I2S_POWER_FULL); + break; + } +} + +void HAL_I2SSetTotalNum(uint32_t totalNum) +{ + i2sDrv->ctrl(I2S_CTRL_SET_TOTAL_NUM , totalNum); +} + +uint32_t HAL_I2SGetTotalNum() +{ + return i2sDrv->getTotalCnt(); +} + +void HAL_I2SSetPlayRecord(i2sPlayRecord_e playRecord) +{ + if (playRecord == PLAY) + { + i2sCtrl.i2sMode = 0x1; // Set I2S controller to send + i2sDmaCtrl.txDmaReqEn = 1; + } + else if (playRecord == RECORD) + { + i2sCtrl.i2sMode = 0x2; // Set I2S controller to receive + i2sDmaCtrl.rxDmaReqEn = 1; // Enable I2S controller RX DMA + } + + i2sDrv->ctrl(I2S_CTRL_I2SCTL , 0); + i2sDrv->ctrl(I2S_CTRL_DMA_CTRL , 0); + +} + +void HAL_I2sConfig(i2sParamCtrl_t paramCtrl) +{ + // 1. Setting parameters per the I2S working mode + i2sMode = paramCtrl.mode; + switch (i2sMode) + { + case MSB_MODE: + i2sDataFmt.dataDly = 0; + i2sBclkFsCtrl.bclkPolarity = 1; + i2sBclkFsCtrl.fsPolarity = 1; + + break; + + case LSB_MODE: + i2sDataFmt.dataDly = 1; + i2sBclkFsCtrl.bclkPolarity = 1; + i2sBclkFsCtrl.fsPolarity = 1; + + break; + + case I2S_MODE: + i2sDataFmt.dataDly = 1; + if (paramCtrl.codecType == CODEC_ES8311) + { + i2sBclkFsCtrl.bclkPolarity = 1; + } + else + { + i2sBclkFsCtrl.bclkPolarity = 0; + } + i2sBclkFsCtrl.fsPolarity = 1; + + break; + + case PCM_MODE: + // Configure codec to PCM mode + i2sBclkFsCtrl.bclkPolarity = 1; + break; + + default: + break; + } + + + // 2. Init codec and I2S controller + switch (paramCtrl.codecType) + { + case CODEC_ES8388: + { + codecType = ES8388; + if (paramCtrl.role == CODEC_MASTER_MODE) // Codec act as master + { + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_SLAVE , paramCtrl.sampleRate); // I2S Set sample rate in slave role + es8388MasterInit(); + } + else // Codec act as slave + { + i2sDataFmt.slaveModeEn = 0; // Master mode + i2sDrv->ctrl(I2S_CTRL_DATA_FORMAT , 0); + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_MASTER , paramCtrl.sampleRate); // I2S Set sample rate in master role + es8388SlaveInit(); + } + + break; + } + + case CODEC_NAU88C22: + { + codecType = NAU88C22; + if (paramCtrl.role == CODEC_MASTER_MODE) // Codec act as master + { + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_SLAVE , paramCtrl.sampleRate); // I2S Set sample rate in slave role + nau88c22MasterInit(); + } + else // Codec act as slave + { + i2sDataFmt.slaveModeEn = 0; // Master mode + i2sDrv->ctrl(I2S_CTRL_DATA_FORMAT , 0); + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_MASTER , paramCtrl.sampleRate); // I2S Set sample rate in slave role + nau88c22SlaveInit(); + } + + break; + } + + case CODEC_ES7148: + case CODEC_ES7149: + case CODEC_TM8211: + { + // now we only can act as master mode + i2sDataFmt.slaveModeEn = 0; // Master mode + i2sDrv->ctrl(I2S_CTRL_DATA_FORMAT , 0); + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_MASTER , paramCtrl.sampleRate); // I2S Set sample rate in master role + + // need to set gpio to 3.3v + HAL_normalIOVoltSet(VOL_3_30V); + break; + } + + case CODEC_ES8311: + { + codecType = ES8311; + if (paramCtrl.role == CODEC_MASTER_MODE) // Codec act as master + { + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_SLAVE , paramCtrl.sampleRate); // I2S Set sample rate in slave role + es8311MasterInit(); + } + else // Codec act as slave + { + i2sDataFmt.slaveModeEn = 0; // Master mode + i2sDrv->ctrl(I2S_CTRL_DATA_FORMAT , 0); + i2sDrv->ctrl(I2S_CTRL_SAMPLE_RATE_MASTER , paramCtrl.sampleRate); // I2S Set sample rate in master role + es8311SlaveInit(); + } + break; + } + + default: + break; + } + + // 3. Set frame size + switch (paramCtrl.frameSize) + { + case FRAME_SIZE_16_16: + i2sDataFmt.slotSize = 0xf; + i2sBclkFsCtrl.fsWidth = 0xf; + i2sDataFmt.wordSize = 0xf; + + break; + + case FRAME_SIZE_16_32: + // I2S controller part + i2sDataFmt.slotSize = 0x1f; + i2sDataFmt.wordSize = 0xf; + i2sBclkFsCtrl.fsWidth = 0x1f; + + break; + + case FRAME_SIZE_24_32: + // I2S controller part + i2sDataFmt.slotSize = 0x1f; + i2sDataFmt.wordSize = 0x17; + i2sBclkFsCtrl.fsWidth = 0x1f; + + break; + + case FRAME_SIZE_32_32: + // I2S controller part + i2sDataFmt.slotSize = 0x1f; + i2sDataFmt.wordSize = 0x1f; + i2sBclkFsCtrl.fsWidth = 0x1f; + + break; + + default: + break; + } + + // 4. Select mono or dual-channel + switch(paramCtrl.channelSel) + { + case MONO: + { + i2sSlotCtrl.slotEn = 1; + i2sSlotCtrl.slotNum = 1; + } + break; + + case DUAL_CHANNEL: + { + i2sSlotCtrl.slotEn = 3; + i2sSlotCtrl.slotNum = 1; + } + break; + + default: + break; + } + + // Init part of I2S controller + i2sDrv->ctrl(I2S_CTRL_DATA_FORMAT , 0); + i2sDrv->ctrl(I2S_CTRL_BCLK_FS_CTRL , 0); + i2sDrv->ctrl(I2S_CTRL_SLOT_CTRL , 0); + + // 5. Set play or record + HAL_I2SSetPlayRecord(paramCtrl.playRecord); +} + +void HAL_I2sTransfer(i2sPlayRecord_e playRecord, uint8_t* memAddr, uint32_t trunkSize) +{ + // 5. After other parameters are ready, start the I2S controller + if (playRecord == PLAY) // Play audio + { + i2sDrv->send(memAddr, trunkSize); + } + else // Record audio + { + i2sDrv->recv(memAddr, trunkSize); + } +} + +void HAL_I2sSrcAdjustVolumn(int16_t* srcBuf, uint32_t srcTotalNum, uint16_t volScale) +{ + int integer = volScale / 10; + int decimal = volScale % 10; + int scale = 0; + int32_t tmp = 0; + uint32_t totalNum = srcTotalNum; + uint32_t step = 0; + + while (totalNum) + { + if (volScale < 10) + { + tmp = ((*(srcBuf + step)) * (256 * integer + 26 * decimal)) >> 8; + } + else + { + scale = (256 * integer + 26 * decimal) >> 8; + tmp = (*(srcBuf + step)) * scale; + } + + if (tmp > 32767) + { + tmp = 32767; + } + else if (tmp < -32768) + { + tmp = -32768; + } + + *(srcBuf + step) = (int16_t)tmp; + step += 1; + totalNum -= 2; + } +} + + +// Control I2S to start or stop +void HAL_I2sStartSop(i2sStartStop_e startStop) +{ + i2sDrv->ctrl(I2S_CTRL_START_STOP , startStop); +} + + + + +#if 0 +// Control volumn of codec when play the audio +void HAL_I2sVolumnCtrl(i2sVolumnCtrl_e volumnCtrl, uint8_t step) +{ + if (volumnCtrl == VOLUMN_INCREASE) + { + codecCtrlVolume(codecType, TRUE, step); // Increase volumn + } + else + { + codecCtrlVolume(codecType, FALSE, step); // Decrease volumn + } +} +#endif + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_misc.c b/PLAT/driver/hal/ec618/ap/src/hal_misc.c new file mode 100644 index 0000000..57b9594 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_misc.c @@ -0,0 +1,187 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: initiated by xxxx +* +* Notes: +* +******************************************************************************/ + +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#include +#include "cmsis_os2.h" +#include "hal_misc.h" +#include "sctdef.h" +#include "ec618.h" +#include "clock.h" +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ + + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + + + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ +extern uint32_t SystemCoreClock; + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ + +extern uint32_t GPR_getChipFullID(void); +extern uint32_t GPR_getChipRevID(void); +extern uint32_t GPR_getChipID(void); + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ + +/* + * cpu cycles delay, every loop spends 2 cpu cycles, so the actual delay is 2*cycles + * Parameter: cycles + */ + +#if defined(__CC_ARM) +PLAT_PA_RAMCODE __asm static void delay_cycles(uint32_t cycles) +{ +loop + SUBS r0, r0, #1 + BNE loop + BX lr +} +#elif defined (__GNUC__) +PLAT_PA_RAMCODE static void delay_cycles(uint32_t cycles) +{ +asm volatile( + "mov r0, %0\n\t" + "loop:\n\t" + "SUBS r0, r0, #1\n\t" + "BNE loop\n\t" + : : "r" (cycles) +); +} +#endif + + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ + +/** + \fn HAL_Get_ChipID(chip_id_sel sel) + \brief Get chip id. + \param[in] HAL_Get_ChipID enum + \note + 31-----8 is chip id + 7------0 is revision id + sel=CHIP_ID_ONLYID, return chip id + sel=CHIP_ID_REVID, return revision id + sel=CHIP_ID_FULL, return both revision and chip id + */ +uint32_t HAL_Get_ChipID(chip_id_sel sel) +{ + uint32_t chipID=0; + + + switch(sel) + { + case CHIP_ID_ONLYID: + + chipID=GPR_getChipID(); + break; + + case CHIP_ID_REVID: + chipID=GPR_getChipRevID(); + break; + + case CHIP_ID_FULLID: + + chipID=GPR_getChipFullID(); + break; + + default: + break; + } + + return chipID; + +} + + + + +/** + \fn delay_us(uint32_t us) + \brief delay time in microseconds. + \param[in] number of us + \note Given the maximum cpu frequency is 204.8MHz and the limit in calculation, + * the maximum time can be delayed is 0xFFFFFFFF / 2048 = 2097151 us = 2097 m + */ +PLAT_PA_RAMCODE void delay_us(uint32_t us) +{ + uint32_t ticks; + + // cpu frequency ranges from 26MHz to 204.8MHz + // first divide 0.1M to get rid of multiply overflow + // considering 3 cpu cycles are taken to execute one loop operation(sub and branch) in delay_cycles function(includ one pre read assembly), + // and 0.1M in first step, so we shall divide another 30 before passing the result to delay_cycles function + // if the delay us is short, it may not be accurate + ticks = SystemCoreClock / 100000U; + ticks = ticks * us / 30U; + + delay_cycles(ticks); +} + +/** + \fn apmuBootDbgGPIOSet(bool level) + \brief set gpio level in boot flow, for boot time dbg + \param[in] gpio level + \note should set register directly, do not use api + */ +void apmuBootDbgGPIOSet(bool level) +{ +#if 0 + volatile uint32_t *apb_mp_pclken = (volatile uint32_t *)0x4d000030; + (*apb_mp_pclken) |= ((1<<6) | (1<<7)); // pclk pad and gpio + GPIO_TypeDef *base = (GPIO_TypeDef *)0x4D070000; //gpio instance 0 + base->OUTENSET = (1<<7); + base->DATAOUT = (level<<7); +#endif +} + + +/** + \fn bool apmuGetLongSlpCfg(void) + \brief config the maximum sleep length. + 1. We suggest return false to sleep no more than 36hour + 2. But when usb is disabled and you do not care about time accuracy, + return true to set maximum sleep time to 1165 hour + \note false: sleep no more than 36.4 hour, true: can sleep 1165 hour + */ +bool apmuGetLongSlpCfg(void) +{ + return false; +} + +ClockId_e CLOCK_checkClkID(void) +{ + return INVALID_CLK; +} + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_pwrkey.c b/PLAT/driver/hal/ec618/ap/src/hal_pwrkey.c new file mode 100644 index 0000000..1ff89eb --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_pwrkey.c @@ -0,0 +1,326 @@ + +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: pwrkey.c +* +* Description: power on/off and software debounce +* +* History: initiated by Zhao Weiqi +* +* Notes: +* +******************************************************************************/ +/*----------------------------------------------------------------------------* + * INCLUDES * + *----------------------------------------------------------------------------*/ +#ifndef FEATURE_BOOTLOADER_PROJECT_ENABLE + +#include +#include "hal_pwrkey.h" +#include "ec618.h" +#include "FreeRTOS.h" +#include "cmsis_os2.h" +#include "queue.h" +#include "exception_process.h" +#include "reset.h" +#include "apmu_external.h" +#include "slpman.h" + +#include DEBUG_LOG_HEADER_FILE + + +/*----------------------------------------------------------------------------* + * MACROS * + *----------------------------------------------------------------------------*/ +#define PWRKEY_TASK_STATK_SIZE 512 +#define PWRKEY_EVENT_QUEUE_SIZE 2 +#define PWRKEY_KEY_MESSAGE 0x1 + +#define PWRKEY_LOCK_SLEEP() slpManDrvVoteSleep(SLP_VOTE_PWRKEY, SLP_ACTIVE_STATE) +#define PWRKEY_UNLOCK_SLEEP() slpManDrvVoteSleep(SLP_VOTE_PWRKEY, SLP_SLP1_STATE) + +/*----------------------------------------------------------------------------* + * DATA TYPE DEFINITION * + *----------------------------------------------------------------------------*/ + +typedef struct { + uint32_t messageId; +} pwrKeyQueueMsg_t; + +typedef void(* pwrKeyIsrCb)(void); + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTION DECLEARATION * + *----------------------------------------------------------------------------*/ +static void pwrKeyLongPressTimerExp(void *argument); + + + +/*----------------------------------------------------------------------------* + * GLOBAL VARIABLES * + *----------------------------------------------------------------------------*/ +pwrKeyInfo_t gPwrKeyInfo; +static uint8_t pwrKeyLongPressTimerId = 0; +static uint8_t pwrKeyRepeatTimerId = 0; +static QueueHandle_t pwrKeyEventQueueHandle; +osTimerId_t pwrKeyLongPressTimer; +osTimerId_t pwrKeyRepeatTimer; +pwrKeyIsrCb pwrKeyIsrCallback = NULL; + + + +/*----------------------------------------------------------------------------* + * PRIVATE FUNCTIONS * + *----------------------------------------------------------------------------*/ +void pwrKeySendKeyStatus(void) +{ + uint32_t msgId = PWRKEY_KEY_MESSAGE; + if (pwrKeyEventQueueHandle) + { + if (pdTRUE != xQueueSend(pwrKeyEventQueueHandle, &msgId, 1000)) + { + ECPLAT_PRINTF(UNILOG_PMU, pwrKeySendKeyStatus_1, P_VALUE, "Power Key message send error"); + } + } + else + { + ECPLAT_PRINTF(UNILOG_PMU, pwrKeySendKeyStatus_2, P_VALUE, "Power Key queue not ready"); + } +} + + +void pwrKeySendKeyStatusInIsr(void) +{ + BaseType_t xHigherPriorityTaskWoken; + + xHigherPriorityTaskWoken = pdFALSE; + + uint32_t msgId = PWRKEY_KEY_MESSAGE; + + if (pwrKeyEventQueueHandle) + { + if (pdTRUE != xQueueSendFromISR(pwrKeyEventQueueHandle, &msgId, &xHigherPriorityTaskWoken)) + { + ECPLAT_PRINTF(UNILOG_PMU, pwrKeySendKeyStatusInIsr_1, P_VALUE, "Power Key message send in isr error"); + } + } + else + { + ECPLAT_PRINTF(UNILOG_PMU, pwrKeySendKeyStatusInIsr_2, P_VALUE, "Power Key queue not ready in isr"); + } + + if(xHigherPriorityTaskWoken) + { + portYIELD_FROM_ISR(pdTRUE); + } +} + +static void pwrKeyQueueInit(void) +{ + pwrKeyEventQueueHandle = xQueueCreate(PWRKEY_EVENT_QUEUE_SIZE, sizeof(pwrKeyQueueMsg_t)); + + if(pwrKeyEventQueueHandle == NULL) + { + ECPLAT_PRINTF(UNILOG_PMU, pwrKeyTask_1, P_VALUE, "Power Key task queue init error"); + } +} + +static void pwrKeyTask(void *arg) +{ + uint32_t msgId = 0; + pwrKeyPressStatus keyStatus = PWRKEY_RELEASE; + + while(1) + { + if (xQueueReceive(pwrKeyEventQueueHandle, &msgId, portMAX_DELAY)) + { + switch(msgId) + { + case PWRKEY_KEY_MESSAGE: + keyStatus = pwrKeyPopKey(&gPwrKeyInfo); + if(gPwrKeyInfo.pwrKeyCallback != NULL) + { + gPwrKeyInfo.pwrKeyCallback(keyStatus); + } + if(keyStatus == PWRKEY_PRESS) + { + if(pwrKeyLongPressTimer == NULL) + pwrKeyLongPressTimer = osTimerNew((osTimerFunc_t)pwrKeyLongPressTimerExp, osTimerOnce, (void *)(uint32_t)pwrKeyLongPressTimerId, NULL); + osTimerStart(pwrKeyLongPressTimer, gPwrKeyInfo.delayCfg.longPressTimeout); + } + break; + default: + break; + } + } + } +} + + +static void pwrKeyTaskInit(void) +{ + osThreadAttr_t task_attr; + memset(&task_attr,0,sizeof(task_attr)); + task_attr.name = "pwrKeyTask"; + task_attr.stack_size = PWRKEY_TASK_STATK_SIZE; + task_attr.priority = osPriorityNormal1; + osThreadNew(pwrKeyTask, NULL, &task_attr); +} + +static void pwrKeyLongPressTimerExp(void *argument) +{ + if(gPwrKeyInfo.curStatus == PWRKEY_PRESS) + { + gPwrKeyInfo.curStatus = PWRKEY_LONGPRESS; + + pwrKeyPushKey(&gPwrKeyInfo, PWRKEY_LONGPRESS); + + pwrKeySendKeyStatus(); + + if(pwrKeyRepeatTimer == NULL) + { + pwrKeyRepeatTimer = osTimerNew((osTimerFunc_t)pwrKeyLongPressTimerExp, osTimerOnce, (void *)(uint32_t)pwrKeyRepeatTimerId, NULL); + } + osTimerStart(pwrKeyRepeatTimer, gPwrKeyInfo.delayCfg.repeatTimeout); + } + else if(gPwrKeyInfo.curStatus == PWRKEY_LONGPRESS) + { + pwrKeyPushKey(&gPwrKeyInfo, PWRKEY_REPEAT); + + pwrKeySendKeyStatus(); + + EC_ASSERT(pwrKeyRepeatTimer != NULL, 0, 0, 0); + + osTimerStart(pwrKeyRepeatTimer, gPwrKeyInfo.delayCfg.repeatTimeout); + } + +} + + + +static void pwrkeyIntProcess(void) +{ + bool pinlevel = pwrKeyGetPinLevel(); + + PWRKEY_LOCK_SLEEP(); + if((gPwrKeyInfo.workMode == PWRKEY_WAKEUP_LOWACTIVE_MODE) || + (gPwrKeyInfo.workMode == PWRKEY_PWRON_MODE)) + { + if(pinlevel == true) + { + // release + gPwrKeyInfo.curStatus = PWRKEY_RELEASE; + pwrKeyPushKey(&gPwrKeyInfo, PWRKEY_RELEASE); + PWRKEY_UNLOCK_SLEEP(); + pwrKeySendKeyStatusInIsr(); + } + else + { + gPwrKeyInfo.curStatus = PWRKEY_PRESS; + pwrKeyPushKey(&gPwrKeyInfo, PWRKEY_PRESS); + pwrKeySendKeyStatusInIsr(); + } + } + else if(gPwrKeyInfo.workMode == PWRKEY_WAKEUP_HIGHACTIVE_MODE) + { + if(pinlevel == true) + { + gPwrKeyInfo.curStatus = PWRKEY_PRESS; + pwrKeyPushKey(&gPwrKeyInfo, PWRKEY_PRESS); + pwrKeySendKeyStatusInIsr(); + } + else + { + gPwrKeyInfo.curStatus = PWRKEY_RELEASE; + pwrKeyPushKey(&gPwrKeyInfo, PWRKEY_RELEASE); + PWRKEY_UNLOCK_SLEEP(); + pwrKeySendKeyStatusInIsr(); + } + } + +} + +/*----------------------------------------------------------------------------* + * GLOBAL FUNCTIONS * + *----------------------------------------------------------------------------*/ +/* example for pwrKeyCallback : +void powerKeyStatusUpdate(pwrKeyPressStatus status) +{ + ECPLAT_PRINTF(UNILOG_PMU, powerKeyStatusUpdate_1, P_VALUE, "PowerKey Status update to = %d", status); + if(status == PWRKEY_LONGPRESS) + { + pwrKeyStartPowerOff(); + } +} +*/ + + +void pwrKeyIntHandler(void) +{ + if(pwrKeyIsrCallback != NULL) + pwrKeyIsrCallback(); +} + + + +void pwrKeyInit(pwrKeyWorkMode workMode, bool pullUpEn, pwrKeyDly_t dlyCfg, pwrKeyCallback_t Callback) +{ + bool pinlevel = pwrKeyGetPinLevel(); + + memset(&gPwrKeyInfo, 0, sizeof(gPwrKeyInfo)); + gPwrKeyInfo.delayCfg = dlyCfg; + gPwrKeyInfo.workMode = workMode; + gPwrKeyInfo.curStatus = PWRKEY_RELEASE; + gPwrKeyInfo.pwrKeyCallback = Callback; + + pwrKeyHwInit(pullUpEn); + + if(workMode == PWRKEY_PWRON_MODE) + { + if(pinlevel == false) + { + gPwrKeyInfo.curStatus = PWRKEY_PRESS; + } + } + else if(workMode == PWRKEY_WAKEUP_LOWACTIVE_MODE) + { + if(pinlevel == false) + { + gPwrKeyInfo.curStatus = PWRKEY_PRESS; + } + } + else if(workMode == PWRKEY_WAKEUP_HIGHACTIVE_MODE) + { + if(pinlevel == true) + { + gPwrKeyInfo.curStatus = PWRKEY_PRESS; + } + } + + pwrKeyIsrCallback = pwrkeyIntProcess; + + pwrKeyQueueInit(); + + pwrKeyTaskInit(); + + NVIC_EnableIRQ(PwrkeyWakeup_IRQn); +} + + +void pwrKeyDeinit(bool pullUpEn) +{ + memset(&gPwrKeyInfo, 0, sizeof(gPwrKeyInfo)); + pwrKeyHwDeinit(pullUpEn); + NVIC_DisableIRQ(PwrkeyWakeup_IRQn); + + pwrKeyIsrCallback = NULL; +} + +#endif + diff --git a/PLAT/driver/hal/ec618/ap/src/hal_uartDump.c b/PLAT/driver/hal/ec618/ap/src/hal_uartDump.c new file mode 100644 index 0000000..1649172 --- /dev/null +++ b/PLAT/driver/hal/ec618/ap/src/hal_uartDump.c @@ -0,0 +1,192 @@ +/**************************************************************************** + * + * Copy right: 2022-, Copyrigths of AirM2M Ltd. + * File name: hal_uartDump.c + * Description: source file for dumping info through UART when exception occurs + * Damn it, too many dependencies are pulled into this module + * History: Rev1.0 2022-1-17 + * + ****************************************************************************/ + +#include "uart.h" +#include "bsp_usart.h" +#include "bsp_lpusart.h" +#include "plat_config.h" +#include "apmu_external.h" + +// Doesn't matter this variable is initialized or not since it'll be set in HAL_UartDumpPortInit +static uint8_t gCurrentUartDumpPort = 0xFF; + +void HAL_UartDumpPortInit(void) +{ + uint32_t uartDumpPort = BSP_GetPlatConfigItemValue(PLAT_CONFIG_ITEM_UART_DUMP_PORT); + uint32_t uartBaudRate = 0; + +#if RTE_UART0 == 1 + extern ARM_DRIVER_USART Driver_USART0; +#endif + +#if RTE_UART1 == 1 + extern ARM_DRIVER_USART Driver_USART1; + extern ARM_DRIVER_USART Driver_LPUSART1; +#endif + +#if RTE_UART2 == 1 + extern ARM_DRIVER_USART Driver_USART2; +#endif + + switch(uartDumpPort) + { + case 0: + +#if RTE_UART0 == 1 + uartBaudRate = Driver_USART0.GetBaudRate(); +#endif + + // Means uart has already been initialized + if((apmuGetImageType() == 1) && (uartBaudRate != 0)) + { + UART_init(0, uartBaudRate, false); + gCurrentUartDumpPort = uartDumpPort; + } + else + { + // Add custom setting(pinmux & baudrate) here !!!!!! +#if 0 + PadConfig_t config; + PAD_getDefaultConfig(&config); + + config.mux = RTE_UART0_TX_FUNC; + + config.pullSelect = PAD_PULL_INTERNAL; + config.pullUpEnable = PAD_PULL_UP_ENABLE; + config.pullDownEnable = PAD_PULL_DOWN_DISABLE; + + PAD_setPinConfig(RTE_UART0_TX_BIT, &config); + + UART_init(0, 115200, false); + + gCurrentUartDumpPort = uartDumpPort; +#endif + } + + break; + + case 1: + +#if RTE_UART1 == 1 + if(apmuGetImageType() == 1) + { + uartBaudRate = Driver_USART1.GetBaudRate(); + + if(uartBaudRate == 0) + { + uartBaudRate = Driver_LPUSART1.GetBaudRate(); + } + } +#endif + // Means uart has already been initialized + if((apmuGetImageType() == 1) && (uartBaudRate != 0)) + { + UART_init(1, uartBaudRate, false); + + gCurrentUartDumpPort = uartDumpPort; + } + else + { + // Add custom setting(pinmux & baudrate) here !!!!!! +#if 0 + PadConfig_t config; + PAD_getDefaultConfig(&config); + + config.mux = RTE_UART1_TX_FUNC; + + config.pullSelect = PAD_PULL_INTERNAL; + config.pullUpEnable = PAD_PULL_UP_ENABLE; + config.pullDownEnable = PAD_PULL_DOWN_DISABLE; + + PAD_setPinConfig(RTE_UART1_TX_BIT, &config); + + UART_init(1, 115200, false); + + gCurrentUartDumpPort = uartDumpPort; +#endif + } + + break; + + case 2: + +#if RTE_UART2 == 1 + uartBaudRate = Driver_USART2.GetBaudRate(); +#endif + // Means uart has already been initialized + if((apmuGetImageType() == 1) && (uartBaudRate != 0)) + { + UART_init(2, uartBaudRate, false); + + gCurrentUartDumpPort = uartDumpPort; + } + else + { + // Add custom setting(pinmux & baudrate) here !!!!!! +#if 0 + PadConfig_t config; + PAD_getDefaultConfig(&config); + + config.mux = RTE_UART2_TX_FUNC; + + config.pullSelect = PAD_PULL_INTERNAL; + config.pullUpEnable = PAD_PULL_UP_ENABLE; + config.pullDownEnable = PAD_PULL_DOWN_DISABLE; + + PAD_setPinConfig(RTE_UART2_TX_BIT, &config); + + UART_init(2, 115200, false); + + gCurrentUartDumpPort = uartDumpPort; + +#endif + } + + break; + + // means uart dump function is disabled + default: + + gCurrentUartDumpPort = 0xFF; + + return; + } +} + + +/** + \brief Check validation of uart dump port + \return true if current dump port is valid, otherwise false + */ +bool HAL_UartDumpPortCheck(void) +{ + return (gCurrentUartDumpPort < USART_INSTANCE_NUM) ? true : false; +} + +/** + \brief Send data to uart dump port in polling way + \param[in] data Pointer to buffer with data to be sent to + \param[in] num Number of data items to send + \param[in] timeout_us timeout value in unit of us + \return num of data items sent in the internal of timeout + */ +uint32_t HAL_UartDumpPortSend(const uint8_t *data, uint32_t num, uint32_t timeout_us) +{ + if(gCurrentUartDumpPort < USART_INSTANCE_NUM) + { + return UART_send(gCurrentUartDumpPort, data, num, timeout_us); + } + else + { + return 0; + } +} + + diff --git a/PLAT/libs/libcore_airm2m.a b/PLAT/libs/libcore_airm2m.a new file mode 100644 index 0000000..c7e38b7 Binary files /dev/null and b/PLAT/libs/libcore_airm2m.a differ diff --git a/PLAT/libs/libfreertos.a b/PLAT/libs/libfreertos.a new file mode 100644 index 0000000..ccbaaac Binary files /dev/null and b/PLAT/libs/libfreertos.a differ diff --git a/PLAT/libs/liblfs.a b/PLAT/libs/liblfs.a new file mode 100644 index 0000000..9419cb9 Binary files /dev/null and b/PLAT/libs/liblfs.a differ diff --git a/PLAT/libs/liblwip.a b/PLAT/libs/liblwip.a new file mode 100644 index 0000000..dc97205 Binary files /dev/null and b/PLAT/libs/liblwip.a differ diff --git a/PLAT/libs/libmiddleware_ec.a b/PLAT/libs/libmiddleware_ec.a new file mode 100644 index 0000000..8127a8d Binary files /dev/null and b/PLAT/libs/libmiddleware_ec.a differ diff --git a/PLAT/libs/libpsnv.a b/PLAT/libs/libpsnv.a new file mode 100644 index 0000000..106e4a5 Binary files /dev/null and b/PLAT/libs/libpsnv.a differ diff --git a/PLAT/libs/libstartup.a b/PLAT/libs/libstartup.a new file mode 100644 index 0000000..c082a6a Binary files /dev/null and b/PLAT/libs/libstartup.a differ diff --git a/PLAT/libs/libtcpipmgr.a b/PLAT/libs/libtcpipmgr.a new file mode 100644 index 0000000..adcadc6 Binary files /dev/null and b/PLAT/libs/libtcpipmgr.a differ diff --git a/PLAT/libs/libyrcompress.a b/PLAT/libs/libyrcompress.a new file mode 100644 index 0000000..2f7be11 Binary files /dev/null and b/PLAT/libs/libyrcompress.a differ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_adc.h b/PLAT/middleware/developed/at/atcust/inc/atec_adc.h new file mode 100644 index 0000000..e276223 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_adc.h @@ -0,0 +1,30 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_adc.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_ADC_H__ +#define __ATEC_ADC_H__ + +#include "at_util.h" + +#define EC_ADC_STR_LEN_MAX 32 +#define EC_ADC_STR_BUF_SIZE (EC_ADC_STR_LEN_MAX + 1) +#define EC_ADC_STR_DEFAULT NULL + +CmsRetId ecADC(const AtCmdInputContext *pAtCmdReq); +#endif + +/* END OF FILE */ + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_ctwing.h b/PLAT/middleware/developed/at/atcust/inc/atec_ctwing.h new file mode 100644 index 0000000..09144fb --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_ctwing.h @@ -0,0 +1,64 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_ctwing.h +* +* Description: Process ctwing access test related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_CTWING_H__ +#define __ATEC_CTWING_H__ + +#include "at_util.h" + + + +#define CTW_PARAM_0_SOFT_STR_LEN 32 +#define CTW_PARAM_0_SOFT_STR_DEF NULL +#define CTW_PARAM_1_MODULE_STR_LEN 32 +#define CTW_PARAM_1_MODULE_STR_DEF NULL +#define CTW_PARAM_2_CHIPTYPE_STR_LEN 32 +#define CTW_PARAM_2_CHIPTYPE_STR_DEF NULL + +#define CTW_PARAM_0_CLIENTID_STR_LEN 64 +#define CTW_PARAM_0_CLIENTID_STR_DEF NULL +#define CTW_PARAM_1_USERNAME_STR_LEN 64 +#define CTW_PARAM_1_USERNAME_STR_DEF NULL +#define CTW_PARAM_2_PWD_STR_LEN 72 +#define CTW_PARAM_2_PWD_STR_DEF NULL + +#define CTW_PARAM_0_TOPIC_STR_LEN 128 +#define CTW_PARAM_0_TOPIC_STR_DEF NULL +#define CTW_PARAM_1_PAYLOAD_STR_LEN 1024 +#define CTW_PARAM_1_PAYLOAD_STR_DEF NULL + + +CmsRetId ctwPARAM(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwHTTPCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwHTTPREGPARAM(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwHTTPREG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwHTTPDEREG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwHTTPSEND(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwTCPCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwTCPREGPARAM(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwTCPREG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwTCPDEREG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwTCPSEND(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwMQTTCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwMQTTREGPARAM(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwMQTTREG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwMQTTDEREG(const AtCmdInputContext *pAtCmdReq); +CmsRetId ctwMQTTSEND(const AtCmdInputContext *pAtCmdReq); + + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_cust_cmd_table.h b/PLAT/middleware/developed/at/atcust/inc/atec_cust_cmd_table.h new file mode 100644 index 0000000..b451626 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_cust_cmd_table.h @@ -0,0 +1,43 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_cust_cmd_table.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_CUSTOMER_CMD_TABLE_H +#define _ATEC_CUSTOMER_CMD_TABLE_H + +#include "at_util.h" + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ + + + +/****************************************************************************** + ***************************************************************************** + * ENUM + ***************************************************************************** +******************************************************************************/ + +AtCmdPreDefInfoC* atcGetATCustCommandsSeqPointer(void); + +uint32_t atcGetATCustCommandsSeqNumb(void); + + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_cust_dev.h b/PLAT/middleware/developed/at/atcust/inc/atec_cust_dev.h new file mode 100644 index 0000000..bc68855 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_cust_dev.h @@ -0,0 +1,58 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_CUST_DEV_H_ +#define _ATEC_CUST_DEV_H_ + +#include +#include "at_def.h" +#include DEBUG_LOG_HEADER_FILE +#include "debug_trace.h" + + +#define CC_CGSN_VALUE_MIN 0 +#define CC_CGSN_VALUE_MAX 3 +#define CC_CGSN_VALUE_DEF 1 + +/* ATI */ +#define CC_ATI_0_VAL_MIN 0 +#define CC_ATI_0_VAL_MAX 255 +#define CC_ATI_0_VAL_DEFAULT 0 + +/* AT&W/AT&W0 */ +#define CC_AND_W_0_VAL_MIN 0 +#define CC_AND_W_0_VAL_MAX 0 +#define CC_AND_W_0_VAL_DEFAULT 0 + +/* AT&F/AT&F0 */ +#define CC_AND_F_0_VAL_MIN 0 +#define CC_AND_F_0_VAL_MAX 0 +#define CC_AND_F_0_VAL_DEFAULT 0 + + +CmsRetId ccCGMI(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccCGMM(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccGMM(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccCGMR(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccCGSN(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccATI(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccATANDW(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccATANDF(const AtCmdInputContext *pAtCmdReq); +CmsRetId ccATANDV(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_dm.h b/PLAT/middleware/developed/at/atcust/inc/atec_dm.h new file mode 100644 index 0000000..d727a84 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_dm.h @@ -0,0 +1,62 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_dm.h +* +* Description: Device manager +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_DM_H__ +#define __ATEC_DM_H__ + +#include "at_util.h" + +#define AUTOREGCFG_STR_LEN 128 +#define DMCONFIG_CET_RESP_STR_LEN 64 +/* AT+AUTOREGCFG */ +#define AUTOREGCFG_0_STR_LEN 32 +#define AUTOREGCFG_0_STR_DEF NULL +#define AUTOREGCFG_1_STR_LEN 66 +#define AUTOREGCFG_1_STR_DEF NULL +#define AUTOREGCFG_2_MIN 0 +#define AUTOREGCFG_2_MAX 0x7fffffff +#define AUTOREGCFG_2_DEF 0 +#define AUTOREGCFG_2_LIFETIME_MIN 1 +#define AUTOREGCFG_2_LIFETIME_MAX 0xffff +#define AUTOREGCFG_2_LIFETIME_DEF 0 +#define AUTOREGCFG_2_TEST_MIN 0 +#define AUTOREGCFG_2_TEST_MAX 1 +#define AUTOREGCFG_2_TEST_DEF 0 +#define AUTOREGCFG_2_APPKEY_STR_LEN 11 +#define AUTOREGCFG_2_APPKEY_STR_DEF NULL +#define AUTOREGCFG_2_SECRET_STR_LEN 33 +#define AUTOREGCFG_2_SECRET_STR_DEF NULL + +/* AT+DMCONFIG */ +#define DMCONFIG_0_MIN 0 +#define DMCONFIG_0_MAX 1 +#define DMCONFIG_0_DEF 0 +#define DMCONFIG_1_MIN 0 +#define DMCONFIG_1_MAX 0xFFFF//large than 24x60 minutes +#define DMCONFIG_1_DEF 0 +#define DMCONFIG_2_STR_LEN 12 +#define DMCONFIG_2_STR_DEF NULL +#define DMCONFIG_3_STR_LEN 33 +#define DMCONFIG_3_STR_DEF NULL +#define DMCONFIG_4_MIN 0 +#define DMCONFIG_4_MAX 1 +#define DMCONFIG_4_DEF 0 + +CmsRetId dmAUTOREGCFG(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_example.h b/PLAT/middleware/developed/at/atcust/inc/atec_example.h new file mode 100644 index 0000000..9e12b5a --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_example.h @@ -0,0 +1,65 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_example.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_EXAMPLE_H__ +#define __ATEC_EXAMPLE_H__ + +#include "at_util.h" + + +#define EC_TESTDEMO_VALUE_MIN 0 +#define EC_TESTDEMO_VALUE_MAX 1 +#define EC_TESTDEMO_VALUE_DEF 0 + +#define EC_TESTA_VALUE_MIN 0 +#define EC_TESTA_VALUE_MAX 8 +#define EC_TESTA_VALUE_DEF 0 + +#define EC_TESTA_STR_LEN_MAX 32 +#define EC_TESTA_STR_BUF_SIZE (EC_TESTA_STR_LEN_MAX + 1) +#define EC_TESTA_STR_DEFAULT NULL + +#define EC_TESTB_VALUE_MIN 0 +#define EC_TESTB_VALUE_MAX 8 +#define EC_TESTB_VALUE_DEF 0 + +#define EC_TESTB_STR_LEN_MAX 32 +#define EC_TESTB_STR_BUF_SIZE (EC_TESTB_STR_LEN_MAX + 1) +#define EC_TESTB_STR_DEFAULT NULL + +#define EC_TESTC_VALUE_MIN 0 +#define EC_TESTC_VALUE_MAX 8 +#define EC_TESTC_VALUE_DEF 0 + +#define EC_TESTC_STR_LEN_MAX 32 +#define EC_TESTC_STR_BUF_SIZE (EC_TESTC_STR_LEN_MAX + 1) +#define EC_TESTC_STR_DEFAULT NULL + + +CmsRetId ecTESTDEMO(const AtCmdInputContext *pAtCmdReq); +CmsRetId ecTESTA(const AtCmdInputContext *pAtCmdReq); +CmsRetId ecTESTB(const AtCmdInputContext *pAtCmdReq); +CmsRetId ecTESTC(const AtCmdInputContext *pAtCmdReq); + +CmsRetId ecTESTBcnf(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId ecTESTCcnf(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); + +CmsRetId ecTESTCind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); + +#endif + +/* END OF FILE */ + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_file.h b/PLAT/middleware/developed/at/atcust/inc/atec_file.h new file mode 100644 index 0000000..a010632 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_file.h @@ -0,0 +1,152 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_adc.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_FILE_H__ +#define __ATEC_FILE_H__ + +#include "at_util.h" + +#define EC_FILE_NAME_OFFSET 12 +#define EC_FILE_NAME_HEAD_OFFSET 5 +#define EC_FILE_NAME_HEAD "EcFs_00_f_" /*00 is handle, f is flag*/ + +#define EC_FINFO_PRINT_BUF_LEN (128) + +#define EC_FOPEN_0_NAME_STR_LEN 63 +#define EC_FOPEN_0_NAME_STR_DEF NULL +#define EC_FOPEN_1_MODE_MIN 0 +#define EC_FOPEN_1_MODE_MAX 2 +#define EC_FOPEN_1_MODE_DEF 0 + +#define EC_FREAD_0_HANDLE_LEN_MIN 1 +#define EC_FREAD_0_HANDLE_LEN_MAX 33 +#define EC_FREAD_0_HANDLE_LEN_DEF 0 +#define EC_FREAD_1_LEN_MIN 0 +#define EC_FREAD_1_LEN_MAX 6000 +#define EC_FREAD_1_LEN_DEF 0 + +#define EC_FWRITE_0_HANDLE_LEN_MIN 1 +#define EC_FWRITE_0_HANDLE_LEN_MAX 33 +#define EC_FWRITE_0_HANDLE_LEN_DEF 0 +#define EC_FWRITE_1_LEN_MIN 0 +#define EC_FWRITE_1_LEN_MAX (10*1024) +#define EC_FWRITE_1_LEN_DEF (1000) +#define EC_FWRITE_2_TIMEOUT_MIN 0 +#define EC_FWRITE_2_TIMEOUT_MAX 100 +#define EC_FWRITE_2_TIMEOUT_DEF 5 + +#define EC_FSEEK_0_HANDLE_LEN_MIN 1 +#define EC_FSEEK_0_HANDLE_LEN_MAX 33 +#define EC_FSEEK_0_HANDLE_LEN_DEF 0 +#define EC_FSEEK_1_LEN_MIN 0 +#define EC_FSEEK_1_LEN_MAX 0x7fffffff +#define EC_FSEEK_1_LEN_DEF 0 +#define EC_FSEEK_2_POSITION_MIN 0 +#define EC_FSEEK_2_POSITION_MAX 2 +#define EC_FSEEK_2_POSITION_DEF 0 + +#define EC_FPOSITION_0_HANDLE_LEN_MIN 1 +#define EC_FPOSITION_0_HANDLE_LEN_MAX 33 +#define EC_FPOSITION_0_HANDLE_LEN_DEF 0 + +#define EC_FTUCAT_0_HANDLE_LEN_MIN 1 +#define EC_FTUCAT_0_HANDLE_LEN_MAX 33 +#define EC_FTUCAT_0_HANDLE_LEN_DEF 0 + +#define EC_FCLOSE_0_HANDLE_LEN_MIN 1 +#define EC_FCLOSE_0_HANDLE_LEN_MAX 33 +#define EC_FCLOSE_0_HANDLE_LEN_DEF 0 + +#define EC_FERASE_0_HANDLE_LEN_MIN 1 +#define EC_FERASE_0_HANDLE_LEN_MAX 33 +#define EC_FERASE_0_HANDLE_LEN_DEF 0 +#define EC_FERASE_0_NAME_STR_LEN 81 +#define EC_FERASE_0_NAME_STR_DEF NULL + +#define EC_FDELETE_0_HANDLE_LEN_MIN 1 +#define EC_FDELETE_0_HANDLE_LEN_MAX 33 +#define EC_FDELETE_0_HANDLE_LEN_DEF 0 +#define EC_FDELETE_0_NAME_STR_LEN 81 +#define EC_FDELETE_0_NAME_STR_DEF NULL + +#define EC_FRENAME_0_NAME_STR_LEN 81 +#define EC_FRENAME_0_NAME_STR_DEF NULL +#define EC_FRENAME_1_NAME_STR_LEN 81 +#define EC_FRENAME_1_NAME_STR_DEF NULL + +#define EC_FDEL_0_NAME_STR_LEN 81 +#define EC_FDEL_0_NAME_STR_DEF NULL + +#define EC_FLDS_0_NAME_STR_LEN 81 +#define EC_FDEL_0_NAME_STR_DEF NULL + +#define EC_FLST_0_NAME_STR_LEN 81 +#define EC_FLST_0_NAME_STR_DEF NULL + +#define EC_FUPL_0_NAME_STR_LEN 81 +#define EC_FUPL_0_NAME_STR_DEF NULL +#define EC_FUPL_1_SIZE_MIN 0 +#define EC_FUPL_1_SIZE_MAX 0xffff +#define EC_FUPL_1_SIZE_DEF 0 +#define EC_FUPL_2_TIMEOUT_MIN 0 +#define EC_FUPL_2_TIMEOUT_MAX 2 +#define EC_FUPL_2_TIMEOUT_DEF 0 +#define EC_FUPL_3_ACK_MIN 0 +#define EC_FUPL_3_ACK_MAX 0xffff +#define EC_FUPL_3_ACK_DEF 0 + +#define EC_FDWL_0_NAME_STR_LEN 81 +#define EC_FDWL_0_NAME_STR_DEF NULL + +typedef struct +{ + uint32_t reqhandle; + uint32_t cmdType; + char *fileName; + char *filePattern; + char *fileHandle; + uint32_t mode; + uint32_t length; + uint32_t timeout; + uint32_t offset; + uint32_t position; + +}fileWriteTempInfo; + +CmsRetId fileOPEN(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileREAD(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileWRITE(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileWriteInputData(UINT8 chanId, UINT8 *pData, INT16 dataLength); +CmsRetId fileWriteCancel(void); +CmsRetId fileSEEK(const AtCmdInputContext *pAtCmdReq); +CmsRetId filePOSITION(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileTUCAT(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileCLOSE(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileRENAME(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileERASE(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileDELETE(const AtCmdInputContext *pAtCmdReq); + +CmsRetId fileMOV(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileMsLDS(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileMsLST(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileMsDEL(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileMsUPL(const AtCmdInputContext *pAtCmdReq); +CmsRetId fileMsDWL(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_fwupd.h b/PLAT/middleware/developed/at/atcust/inc/atec_fwupd.h new file mode 100644 index 0000000..eebff50 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_fwupd.h @@ -0,0 +1,28 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_fwupd.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_FWUPD_H__ +#define __ATEC_FWUPD_H__ + +#include "at_util.h" + + +CmsRetId ecNFWUPD(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_http.h b/PLAT/middleware/developed/at/atcust/inc/atec_http.h new file mode 100644 index 0000000..cec7e5d --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_http.h @@ -0,0 +1,112 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_http.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_HTTP_H +#define _ATEC_HTTP_H + +#include "at_util.h" + +#define HTTP_MAX_RSP_LEN 256 +/* AT+HTTPCFG */ +#define HTTPCFG_CONTEXTID_MIN 1 +#define HTTPCFG_CONTEXTID_MAX 15 +#define HTTPCFG_CONTEXTID_DEF 1 +#define HTTPCFG_REQUESTHEAD_MIN 0 +#define HTTPCFG_REQUESTHEAD_MAX 1 +#define HTTPCFG_REQUESTHEAD_DEF 0 +#define HTTPCFG_RESPONSEHEAD_MIN 0 +#define HTTPCFG_RESPONSEHEAD_MAX 1 +#define HTTPCFG_RESPONSEHEAD_DEF 0 +#define HTTPCFG_SSLCTXID_MIN 0 +#define HTTPCFG_SSLCTXID_MAX 5 +#define HTTPCFG_SSLCTXID_DEF 1 +#define HTTPCFG_CONTENTTYPE_MIN 0 +#define HTTPCFG_CONTENTTYPE_MAX 3 +#define HTTPCFG_CONTENTTYPE_DEF 0 +#define HTTPCFG_AUTOOUT_MIN 0 +#define HTTPCFG_AUTOOUT_MAX 1 +#define HTTPCFG_AUTOOUT_DEF 0 +#define HTTPCFG_CLOSEIND_MIN 0 +#define HTTPCFG_CLOSEIND_MAX 1 +#define HTTPCFG_CLOSEIND_DEF 0 +/* AT+HTTPURL */ +#define HTTPURL_LEN_MIN 1 +#define HTTPURL_LEN_MAX 2048 +#define HTTPURL_TIMEOUT_MIN 1 +#define HTTPURL_TIMEOUT_MAX 65535 +#define HTTPURL_TIMEOUT_DEF 60 +/* AT+HTTPGET */ +#define HTTPGET_RSPTIME_MIN 1 +#define HTTPGET_RSPTIME_MAX 65535 +#define HTTPGET_RSPTIME_DEF 60 +#define HTTPGET_DATALEN_MIN 1 +#define HTTPGET_DATALEN_MAX 2048 +#define HTTPGET_INPUT_MIN 1 +#define HTTPGET_INPUT_MAX 65535 +#define HTTPGET_INPUT_DEF 60 +/* AT+HTTPGETEX */ +#define HTTPGETEX_RSPTIME_MIN 1 +#define HTTPGETEX_RSPTIME_MAX 65535 +#define HTTPGETEX_RSPTIME_DEF 60 +#define HTTPGETEX_STARTPOS_MIN 0 +#define HTTPGETEX_STARTPOS_MAX 0x7FFFFFFF +#define HTTPGETEX_STARTPOS_DEF 0 +#define HTTPGETEX_READLEN_MIN 1 +#define HTTPGETEX_READLEN_MAX 0x7FFFFFFF +#define HTTPGETEX_READLEN_DEF -1 +/* AT+HTTPPOST */ +#define HTTPPOST_DATALEN_MIN 1 +#define HTTPPOST_DATALEN_MAX 4096 +#define HTTPPOST_INPUTTIME_MIN 1 +#define HTTPPOST_INPUTTIME_MAX 65534 +#define HTTPPOST_INPUTTIME_DEF 60 +#define HTTPPOST_RSPTIME_MIN 1 +#define HTTPPOST_RSPTIME_MAX 65535 +#define HTTPPOST_RSPTIME_DEF 60 + +/* AT+HTTPREAD */ +#define HTTPREAD_WAIT_MIN 1 +#define HTTPREAD_WAIT_MAX 65535 +#define HTTPREAD_WAIT_DEF 60 + +/* AT+HTTFOTADL */ +#define HTTPFOTADL_URC_MIN 0 +#define HTTPFOTADL_URC_MAX 100 +#define HTTPFOTADL_URC_DEF 100 + +#define HTTPFILENAME_MAX_LEN 63 +enum HTTP_CHANNEL_STATUS +{ + HTTP_URL_INPUT, + HTTP_REQCONTENT_INPUT +}; + +void httpTimerExpired(void); +CmsRetId httpInputData(uint8_t chanId, uint8_t *pData, uint16_t dataLength); + +CmsRetId httpCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpURL(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpGET(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpGETEX(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpPOST(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpPOSTFILE(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpSTOP(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpREAD(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpFOTADL(const AtCmdInputContext *pAtCmdReq); +CmsRetId httpREADFILE(const AtCmdInputContext *pAtCmdReq); + +#endif + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_mqtt.h b/PLAT/middleware/developed/at/atcust/inc/atec_mqtt.h new file mode 100644 index 0000000..28f622b --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_mqtt.h @@ -0,0 +1,253 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_mqtt.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_MQTT_H +#define _ATEC_MQTT_H + +#include "at_util.h" + +#define MQTT_ID_MIN 0 +#define MQTT_ID_MAX 3 +#define MQTT_ID_DEF 0xff +#define MQTT_TCP_ID_MIN 0 +#define MQTT_TCP_ID_MAX 0 +#define MQTT_TCP_ID_DEF 0 + +/* AT+ECMTCFG */ +#define MQTTCFG_CFG_MAX_LEN 17 +#define MQTTCFG_CFG_STR_DEF NULL +#define MQTTCFG_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTCFG_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTCFG_TCP_ID_DEF MQTT_TCP_ID_DEF + +#define MQTTCFG_2_ECHO_MIN 0 +#define MQTTCFG_2_ECHO_MAX 1 +#define MQTTCFG_2_ECHO_DEF 0 + +#define MQTTCFG_2_TXFORMAT_MIN 0 +#define MQTTCFG_2_TXFORMAT_MAX 1 +#define MQTTCFG_2_TXFORMAT_DEF 0 +#define MQTTCFG_3_RXFORMAT_MIN 0 +#define MQTTCFG_3_RXFORMAT_MAX 1 +#define MQTTCFG_3_RXFORMAT_DEF 0 + +#define MQTTCFG_2_KEEPALIVE_MIN 0 +#define MQTTCFG_2_KEEPALIVE_MAX 3600 +#define MQTTCFG_2_KEEPALIVE_DEF 120 + +#define MQTTCFG_2_SESSION_MIN 0 +#define MQTTCFG_2_SESSION_MAX 1 +#define MQTTCFG_2_SESSION_DEF 0 + +#define MQTTCFG_2_PKT_MIN 1 +#define MQTTCFG_2_PKT_MAX 60 +#define MQTTCFG_2_PKT_DEF 10 +#define MQTTCFG_3_RETRY_MIN 1 +#define MQTTCFG_3_RETRY_MAX 10 +#define MQTTCFG_3_RETRY_DEF 3 +#define MQTTCFG_4_NOTICE_MIN 0 +#define MQTTCFG_4_NOTICE_MAX 1 +#define MQTTCFG_4_NOTICE_DEF 0 + +#define MQTTCFG_2_WILLFLAG_MIN 0 +#define MQTTCFG_2_WILLFLAG_MAX 1 +#define MQTTCFG_2_WILLFLAG_DEF 0 +#define MQTTCFG_3_WILLQOS_MIN 0 +#define MQTTCFG_3_WILLQOS_MAX 2 +#define MQTTCFG_3_WILLQOS_DEF 0 +#define MQTTCFG_4_WILLQRETAIN_MIN 0 +#define MQTTCFG_4_WILLQRETAIN_MAX 1 +#define MQTTCFG_4_WILLQRETAIN_DEF 0 +#define MQTTCFG_5_WILLTOPIC_MAX_LEN 256 +#define MQTTCFG_5_WILLTOPIC_STR_DEF NULL +#define MQTTCFG_6_WILLMSG_MAX_LEN 256 +#define MQTTCFG_6_WILLMSG_STR_DEF NULL + +#define MQTTCFG_2_VERSION_MIN 3 +#define MQTTCFG_2_VERSION_MAX 4 +#define MQTTCFG_2_VERSION_DEF 4 + +#define MQTTCFG_2_PRODKEY_MAX_LEN 33 +#define MQTTCFG_2_PRODKEY_STR_DEF NULL +#define MQTTCFG_3_DEVICENAME_MAX_LEN 33 +#define MQTTCFG_3_DEVICENAME_STR_DEF NULL +#define MQTTCFG_4_DEVICESECRET_MAX_LEN 65 +#define MQTTCFG_4_DEVICESECRET_STR_DEF NULL +#define MQTTCFG_5_PRODNAME_MAX_LEN 65 +#define MQTTCFG_5_PRODNAME_STR_DEF NULL +#define MQTTCFG_6_PRODSECRET_MAX_LEN 65 +#define MQTTCFG_6_PRODSECRET_STR_DEF NULL +#define MQTTCFG_7_AUTHTYPE_MAX_LEN 33 +#define MQTTCFG_7_AUTHTYPE_STR_DEF NULL +#define MQTTCFG_8_SIGNMETHOD_MAX_LEN 33 +#define MQTTCFG_8_SIGNMETHOD_STR_DEF NULL +#define MQTTCFG_9_AUTHMODE_MAX_LEN 33 +#define MQTTCFG_9_AUTHMODE_STR_DEF NULL +#define MQTTCFG_10_SECUREMODE_MAX_LEN 9 +#define MQTTCFG_10_SECUREMODE_STR_DEF NULL +#define MQTTCFG_11_INSTANCEID_MAX_LEN 33 +#define MQTTCFG_11_INSTANCEID_STR_DEF NULL +#define MQTTCFG_12_DYNREGUSED_MIN 0 +#define MQTTCFG_12_DYNREGUSED_MAX 8 +#define MQTTCFG_12_DYNREGUSED_DEF 0 + +#define MQTTCFG_1_SSL_MAX_LEN 9 +#define MQTTCFG_1_SSL_STR_DEF NULL + +#define MQTTCFG_2_PSK_MAX_LEN 129 +#define MQTTCFG_2_PSK_STR_DEF NULL +#define MQTTCFG_3_PSKID_MAX_LEN 256 +#define MQTTCFG_3_PSKID_STR_DEF NULL + +#define MQTTCFG_2_ECC_MAX_LEN 4001 +#define MQTTCFG_2_ECC_STR_DEF NULL + +#define MQTTCFG_2_CA_MAX_LEN 4001 +#define MQTTCFG_2_CA_STR_DEF NULL + +#define MQTTCFG_3_NAME_MAX_LEN 65 +#define MQTTCFG_3_NAME_STR_DEF NULL + +#define MQTTCFG_2_CLOUD_MIN 0 +#define MQTTCFG_2_CLOUD_MAX 255 +#define MQTTCFG_2_CLOUD_DEF 0 +#define MQTTCFG_3_PAYLOADTYPE_MIN 0 +#define MQTTCFG_3_PAYLOADTYPE_MAX 255 +#define MQTTCFG_3_PAYLOADTYPE_DEF 1 + +/* AT+ECMTOPEN */ +#define MQTTOPEN_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTOPEN_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTOPEN_TCP_ID_DEF MQTT_TCP_ID_DEF +#define MQTTOPEN_1_HOST_MAX_LEN 128 +#define MQTTOPEN_1_HOST_STR_DEF NULL +#define MQTTOPEN_2_PORT_MIN 1 +#define MQTTOPEN_2_PORT_MAX 65535 +#define MQTTOPEN_2_PORT_DEF 1883 + +/* AT+ECMTCLOSE */ +#define MQTTCLOSE_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTCLOSE_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTCLOSE_TCP_ID_DEF MQTT_TCP_ID_DEF + +/* AT+ECMTCONN*/ +#define MQTTCONN_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTCONN_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTCONN_TCP_ID_DEF MQTT_TCP_ID_DEF +#define MQTTCONN_1_CLIENTID_MAX_LEN 49//256 +#define MQTTCONN_1_CLIENTID_STR_DEF NULL +#define MQTTCONN_2_USERNAME_MAX_LEN 49//256 +#define MQTTCONN_2_USERNAME_STR_DEF NULL +#define MQTTCONN_3_PWD_MAX_LEN 129//256 +#define MQTTCONN_3_PWD_STR_DEF NULL + +/* AT+ECMTDISC */ +#define MQTTDISC_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTDISC_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTDISC_TCP_ID_DEF MQTT_TCP_ID_DEF + +/* AT+ECMTSUB */ +#define MQTTSUB_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTSUB_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTSUB_TCP_ID_DEF MQTT_TCP_ID_DEF +#define MQTTSUB_1_MSGID_MIN 1 +#define MQTTSUB_1_MSGID_MAX 65535 +#define MQTTSUB_1_MSGID_DEF 10 +#define MQTTSUB_2_TOPIC_MAX_LEN 256 +#define MQTTSUB_2_TOPIC_STR_DEF NULL +#define MQTTSUB_3_QOS_MIN 0 +#define MQTTSUB_3_QOS_MAX 2 +#define MQTTSUB_3_QOS_DEF 0 + +/* AT+ECMTUNSUB */ +#define MQTTUNSUB_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTUNSUB_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTUNSUB_TCP_ID_DEF MQTT_TCP_ID_DEF +#define MQTTUNSUB_1_MSGID_MIN 1 +#define MQTTUNSUB_1_MSGID_MAX 65535 +#define MQTTUNSUB_1_MSGID_DEF 10 +#define MQTTUNSUB_2_TOPIC_MAX_LEN 256 +#define MQTTUNSUB_2_TOPIC_STR_DEF NULL + +/* AT+ECMTPUB */ +#define MQTTPUB_TCP_ID_MIN MQTT_TCP_ID_MIN +#define MQTTPUB_TCP_ID_MAX MQTT_TCP_ID_MAX +#define MQTTPUB_TCP_ID_DEF MQTT_TCP_ID_DEF +#define MQTTPUB_1_MSGID_MIN 0 +#define MQTTPUB_1_MSGID_MAX 65535 +#define MQTTPUB_1_MSGID_DEF 10 +#define MQTTPUB_2_QOS_MIN 0 +#define MQTTPUB_2_QOS_MAX 2 +#define MQTTPUB_2_QOS_DEF 1 +#define MQTTPUB_3_RETRAINED_MIN 0 +#define MQTTPUB_3_RETRAINED_MAX 40 +#define MQTTPUB_3_RETRAINED_DEF 0 +#define MQTTPUB_4_TOPIC_MAX_LEN 256 +#define MQTTPUB_4_TOPIC_STR_DEF NULL +#define MQTTPUB_5_MSG_MAX_LEN 1027 +#define MQTTPUB_5_MSG_STR_DEF NULL +#define MQTTPUB_6_CLOUD_MIN 0 +#define MQTTPUB_6_CLOUD_MAX 128 +#define MQTTPUB_6_CLOUD_DEF 0xff +#define MQTTPUB_7_RETRAINED_MIN 0 +#define MQTTPUB_7_RETRAINED_MAX 1 +#define MQTTPUB_7_RETRAINED_DEF 0xff +#define MQTTPUB_6_RAI_MIN 0 +#define MQTTPUB_6_RAI_MAX 128 +#define MQTTPUB_6_RAI_DEF 0 + +#define MQTT_DATA_FORMAT_TXT 0 +#define MQTT_DATA_FORMAT_HEX 1 +#define MQTT_TLS_CA_SUB_SEQ_LEN 64 + +typedef struct +{ + UINT32 reqHandle; + int tcpId; + int msgId; + int qos; + int retained; + int rai; + char *mqttTopic; + +}mqtt_pub_data; + +CmsRetId mqttCFG(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttOPEN(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttCLOSE(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttCONN(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttDISC(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttSUB(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttUNS(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttPUB(const AtCmdInputContext *AtCmdReqParaPtr); +CmsRetId mqttPUBInputData(UINT8 chanId, UINT8 *pData, INT16 dataLength); +CmsRetId mqttPUBCancel(void); + +CmsRetId mqttOPENind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttCLOSEind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttCONNind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttDISCind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttSUBind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttUNSind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttPUBind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); + +CmsRetId mqttSTATind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId mqttRECVind(UINT16 primId, UINT16 reqHandle, UINT16 rc, void *paras); + + +#endif + + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_plat_dev.h b/PLAT/middleware/developed/at/atcust/inc/atec_plat_dev.h new file mode 100644 index 0000000..588e973 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_plat_dev.h @@ -0,0 +1,279 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_plat_dev.h +* +* Description: Device debug related AT CMD +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_DEBUG_H__ +#define __ATEC_DEBUG_H__ + +#include "at_util.h" + +#define EC_CMD_BUF_LEN 640 +#define EC_PRINT_BUF_LEN 72 +#define EC_DUMP_DATA_LEN 32 +#define EC_DUMP_DATA_BLOCK 8192 +#define ATC_ECRFTEST_STR_MAX_LEN 5000 + + +/* AT+ECUNITTEST */ +#define ATC_ECUNITTEST_0_VAL_MIN 0 +#define ATC_ECUNITTEST_0_VAL_MAX 16 +#define ATC_ECUNITTEST_0_VAL_DEFAULT 0 /* full functionality */ + + + +/*AT+ECRST*/ +#define ATC_ECRST_MAX_DELAY_MS 2000 + +/* AT+ECSYSTEST */ +#define ATC_SYSTEST_0_VAL_MIN 0 +#define ATC_SYSTEST_0_VAL_MAX 512 +#define ATC_SYSTEST_0_VAL_DEFAULT 0 /* full functionality */ +#define ATC_SYSTEST_0_STR_DEFAULT NULL +#define ATC_SYSTEST_0_STR_MAX_LEN 256 /* */ + +/* AT+ECPMUCFG */ +#define ATC_ECPMUCFG_0_VAL_MIN 0 +#define ATC_ECPMUCFG_0_VAL_MAX 1 +#define ATC_ECPMUCFG_0_VAL_DEFAULT 0 /* full functionality */ +#define ATC_ECPMUCFG_1_VAL_MIN 0 +#define ATC_ECPMUCFG_1_VAL_MAX 5 +#define ATC_ECPMUCFG_1_VAL_DEFAULT 0 /* full functionality */ + +/* AT+ECPCFG */ +#define ATC_ECPCFG_MAX_PARM_STR_LEN 32 +#define ATC_ECPCFG_MAX_PARM_STR_DEFAULT NULL + +#define ATC_ECPCFG_VAL_MIN 0 +#define ATC_ECPCFG_VAL_MAX 0xffff +#define ATC_ECPCFG_VAL_DEFAULT 0 /* full functionality */ + +#define ATC_ECPCFG_WDT_VAL_MIN 0 +#define ATC_ECPCFG_WDT_VAL_MAX 1 +#define ATC_ECPCFG_WDT_VAL_DEFAULT 0 /* full functionality */ + +#define ATC_ECPCFG_UART_DUMP_PORT_VAL_MIN 0 +#define ATC_ECPCFG_UART_DUMP_PORT_VAL_MAX 255 +#define ATC_ECPCFG_UART_DUMP_PORT_VAL_DEFAULT 1 /* full functionality */ + +#define ATC_ECPCFG_UNI_CTRL_VAL_MIN 0 +#define ATC_ECPCFG_UNI_CTRL_VAL_MAX 2 +#define ATC_ECPCFG_UNI_CTRL_VAL_DEFAULT 2 /* full functionality */ + +#define ATC_ECPCFG_UNI_LEVEL_VAL_MIN 0 +#define ATC_ECPCFG_UNI_LEVEL_VAL_MAX 5 +#define ATC_ECPCFG_UNI_LEVEL_VAL_DEFAULT 0 /* full functionality */ + +#define ATC_ECPCFG_LOG_BAUDRATE_VAL_MIN 921600 +#define ATC_ECPCFG_LOG_BAUDRATE_VAL_MAX 6000001 +#define ATC_ECPCFG_LOG_BAUDRATE_VAL_DEFAULT 6000000 /* full functionality */ + +#define ATC_ECPCFG_SLEEP_VAL_MIN 0 +#define ATC_ECPCFG_SLEEP_VAL_MAX 0xffff +#define ATC_ECPCFG_SLEEP_VAL_DEFAULT 0 /* full functionality */ + +#define ATC_ECPCFG_FAULT_VAL_MIN EXCEP_OPTION_DUMP_FLASH_EPAT_LOOP +#define ATC_ECPCFG_FAULT_VAL_MAX (EXCEP_OPTION_MAX) +#define ATC_ECPCFG_FAULT_VAL_DEFAULT EXCEP_OPTION_DUMP_FLASH_EPAT_LOOP /* full functionality */ + +#define ATC_ECPCFG_LOG_PORT_SEL_MIN 0 +#define ATC_ECPCFG_LOG_PORT_SEL_MAX 2 +#define ATC_ECPCFG_LOG_PORT_SEL_DEFAULT 0 + + +#define ATC_ECPCFG_USB_CTRL_VAL_MIN 0 +#define ATC_ECPCFG_USB_CTRL_VAL_MAX 2 +#define ATC_ECPCFG_USB_CTRL_VAL_DEFAULT 0 + +#define ATC_ECPCFG_USB_SW_TRACEFLAG_VAL_MIN 0 +#define ATC_ECPCFG_USB_SW_TRACEFLAG_VAL_MAX 0x0fffffff +#define ATC_ECPCFG_USB_SW_TRACEFLAG_VAL_DEFAULT 0 + + +#define ATC_ECPCFG_USB_SLPMASK_VAL_MIN 0 +#define ATC_ECPCFG_USB_SLPMASK_VAL_MAX 1 +#define ATC_ECPCFG_USB_SLPMASK_VAL_DEFAULT 0 + +#define ATC_ECPCFG_USB_SLPTHD_VAL_MIN 0 +#define ATC_ECPCFG_USB_SLPTHD_VAL_MAX 0xFFFF +#define ATC_ECPCFG_USB_SLPTHD_VAL_DEFAULT 0 + +#define ATC_ECPCFG_PWRKEY_MODE_VAL_MIN 0 +#define ATC_ECPCFG_PWRKEY_MODE_VAL_MAX 2 +#define ATC_ECPCFG_PWRKEY_MODE_VAL_DEFAULT 0 + +#define ATC_ECPCFG_USBNET_VAL_MIN 0 +#define ATC_ECPCFG_USBNET_VAL_MAX 1 +#define ATC_ECPCFG_USBNET_VAL_DEFAULT 0 + +#define ATC_ECPCFG_FOTA_URC_PORT_TYPE_USB PLAT_CFG_FOTA_URC_PORT_USB +#define ATC_ECPCFG_FOTA_URC_PORT_TYPE_UART PLAT_CFG_FOTA_URC_PORT_UART + +#define ATC_ECPCFG_FOTA_URC_USB_PORT_IDX_MIN PLAT_CFG_FOTA_URC_USB_PORT_IDX_MIN +#define ATC_ECPCFG_FOTA_URC_USB_PORT_IDX_MAX PLAT_CFG_FOTA_URC_USB_PORT_IDX_MAX + +#define ATC_ECPCFG_FOTA_URC_UART_PORT_IDX_MIN PLAT_CFG_FOTA_URC_UART_PORT_IDX_MIN +#define ATC_ECPCFG_FOTA_URC_UART_PORT_IDX_MAX PLAT_CFG_FOTA_URC_UART_PORT_IDX_MAX + +#define ATC_ECPCFG_FOTA_URC_PORT_SEL_MIN ((ATC_ECPCFG_FOTA_URC_PORT_TYPE_USB << 4) | ATC_ECPCFG_FOTA_URC_USB_PORT_IDX_MIN) +#define ATC_ECPCFG_FOTA_URC_PORT_SEL_MAX ((ATC_ECPCFG_FOTA_URC_PORT_TYPE_UART << 4) | ATC_ECPCFG_FOTA_URC_UART_PORT_IDX_MAX) +#define ATC_ECPCFG_FOTA_URC_PORT_SEL_DEFAULT ((ATC_ECPCFG_FOTA_URC_PORT_TYPE_USB << 4) | 0) + +/* AT+ECUSBSYS */ +#define ATC_ECUSBSYS_MAX_PARM_STR_LEN 32 +#define ATC_ECUSBSYS_MAX_PARM_STR_DEFAULT NULL + +#define ATC_ECUSBSYS_VAL_MIN 0 +#define ATC_ECUSBSYS_VAL_MAX 0xffff +#define ATC_ECUSBSYS_VAL_DEFAULT 0 /* full functionality */ + +#define ATC_ECUSBSYS_VBUS_MODE_EN_VAL_MIN 0 +#define ATC_ECUSBSYS_VBUS_MODE_EN_VAL_MAX 1 +#define ATC_ECUSBSYS_VBUS_MODE_EN_VAL_DEFAULT 0 + +#define ATC_ECUSBSYS_VBUS_WKUP_PAD_VAL_MIN 0 +#define ATC_ECUSBSYS_VBUS_WKUP_PAD_VAL_MAX 5 +#define ATC_ECUSBSYS_VBUS_WKUP_PAD_VAL_DEFAULT 1 + + +#define ATC_TASKINFO_LEN 64 + +/* AT+IPR */ +#define ATC_IPR_MAX_PARM_STR_LEN 32 +#define ATC_IPR_MAX_PARM_STR_DEFAULT NULL + +/* AT+ECLEDMODE */ +#define ATC_ECLED_MODE_VAL_MIN 0 +#define ATC_ECLED_MODE_VAL_MAX 1 +#define ATC_ECLED_MODE_VAL_DEFAULT 0 + +/* AT+ECFLASHMONITORINFO */ +#define ATC_ECFLASHMONITORINFO_VAL_MIN 0 +#define ATC_ECFLASHMONITORINFO_VAL_MAX 3 +#define ATC_ECFLASHMONITORINFO_VAL_DEFAULT 1 + +/* AT+ECPURC */ +#define ATC_ECPURC_0_MAX_PARM_STR_LEN 16 +#define ATC_ECPURC_0_MAX_PARM_STR_DEFAULT NULL +#define ATC_ECPURC_1_VAL_MIN 0 +#define ATC_ECPURC_1_VAL_MAX 1 +#define ATC_ECPURC_1_VAL_DEFAULT 0 + +/* AT+ECPALARM */ +#define ATC_ECPALARM_0_MAX_PARM_STR_LEN 8 +#define ATC_ECPALARM_0_MAX_PARM_STR_DEFAULT NULL +#define ATC_ECPALARM_1_VAL_MIN 0 +#define ATC_ECPALARM_1_VAL_MAX 1 +#define ATC_ECPALARM_1_VAL_DEFAULT 0 +#define ATC_ECPALARM_VOLT_VAL_MIN 0 +#define ATC_ECPALARM_VOLT_VAL_MAX 25 +#define ATC_ECPALARM_VOLT_VAL_DEFAULT 0 +#define ATC_ECPALARM_THERM_VAL_MIN 0 +#define ATC_ECPALARM_THERM_VAL_MAX 3 +#define ATC_ECPALARM_THERM_VAL_DEFAULT 3 +#define ATC_ECPALARM_HYSTER_VAL_MIN 0 +#define ATC_ECPALARM_HYSTER_VAL_MAX 3 +#define ATC_ECPALARM_HYSTER_VAL_DEFAULT 3 + +/* AT+ICF */ +#define ATC_ICF_FORMAT_VAL_MIN 1 +#define ATC_ICF_FORMAT_VAL_MAX 6 +#define ATC_ICF_FORMAT_VAL_DEFAULT 3 + +#define ATC_ICF_PARITY_VAL_MIN 0 +#define ATC_ICF_PARITY_VAL_MAX 1 +#define ATC_ICF_PARITY_VAL_DEFAULT 0 + +/* AT+IFC */ +#define ATC_IFC_RTS_VAL_MIN 0 +#define ATC_IFC_RTS_VAL_MAX 2 +#define ATC_IFC_RTS_VAL_DEFAULT 0 + +#define ATC_IFC_CTS_VAL_MIN 0 +#define ATC_IFC_CTS_VAL_MAX 2 +#define ATC_IFC_CTS_VAL_DEFAULT 0 + +/* AT+ECSCLK */ +#define ATC_EC_SCLK_VAL_MIN 0 +#define ATC_EC_SCLK_VAL_MAX 1 +#define ATC_EC_SCLK_VAL_DEFAULT 0 + +/* AT+ECMEM32 */ +#define ATC_ECMEM32_OPMODE_VAL_READ 0 +#define ATC_ECMEM32_OPMODE_VAL_WRITE 1 +#define ATC_ECMEM32_OPMODE_VAL_DEFAULT 0 + +#define ATC_ECMEM32_ADDR_VAL_MIN 0x80000000 +#define ATC_ECMEM32_ADDR_VAL_MAX 0x7fffffff +#define ATC_ECMEM32_ADDR_VAL_DEFAULT 0 + + +#define ATC_ECMEM32_VAL_MIN 0x80000000 +#define ATC_ECMEM32_VAL_MAX 0x7fffffff +#define ATC_ECMEM32_VAL_DEFAULT 0 + + +/* AT+ECPOWD */ +#define ATC_ECPOWD_VAL_MIN 0 +#define ATC_ECPOWD_VAL_MAX 1 +#define ATC_ECPOWD_VAL_DEFAULT 1 + +/* AT+ECBTOFFSETDBG */ +#define ATC_ECBTOFFSETDBG_VAL_MIN 0x80000000 +#define ATC_ECBTOFFSETDBG_VAL_MAX 0x7fffffff +#define ATC_ECBTOFFSETDBG_VAL_DEFAULT 0 + +#define PRINTF_BUF_LEN 512 +#define ECFSINFO_PRINT_BUF_LEN (256) + +/* AT+RLCHK */ +#define ATC_RLCHK_MAX_PARM_STR_LEN 32 +#define ATC_RLCHK_MAX_PARM_STR_DEFAULT NULL + +//CmsRetId pdevHELP(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevRST(const AtCmdInputContext *pAtCmdReq); +//CmsRetId pdevPOWERON(const AtCmdInputContext *pAtCmdReq); +//CmsRetId pdevPOWEROFF(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECTASKINFO(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECTASKHISTINFO(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSHOWMEM(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECHEAPINFO(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECDLFCMEM(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECFSINFO(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECFSFORMAT(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECFMONITORINFO(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevSYSTEST(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSYSTEST(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECLOGDBVER(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECPCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECUSBSYS(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECPMUCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECVOTECHK(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevIPR(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevNetLight(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevPMUSTATUS(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECPURC(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECPALARM(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevICF(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevIFC(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECMEM32(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSCLK(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECDUMPCHK(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECPOWD(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevBTOFFSETDBG(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevRLCHK(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_plat_test.h b/PLAT/middleware/developed/at/atcust/inc/atec_plat_test.h new file mode 100644 index 0000000..6990b1d --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_plat_test.h @@ -0,0 +1,155 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_plat_test.h +* +* Description: plat verification related AT CMD +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_PLAT_TEST_H__ +#define __ATEC_PLAT_TEST_H__ + +#include "at_util.h" + +#define PRINTF_BUF_LEN 512 +#define ATC_MALLOC_MAGIN_32 32 +#define ATC_MALLOC_MAGIN_64 64 + +/* AT+ECPERTEST */ +#define ATC_ECPERTEST_MODULE_MAX_PARM_STR_LEN 16 +#define ATC_ECPERTEST_MODULE_MAX_PARM_STR_DEFAULT NULL + + +#define ATC_ECPERTEST_CASENUM_VAL_MIN 0 +#define ATC_ECPERTEST_CASENUM_VAL_MAX 256 +#define ATC_ECPERTEST_CASENUM_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_INSNUM_VAL_MIN 0 +#define ATC_ECPERTEST_INSNUM_VAL_MAX 256 +#define ATC_ECPERTEST_INSNUM_VAL_DEFAULT 0 + + +#define ATC_ECPERTEST_LOOPCNT_VAL_MIN 0 +#define ATC_ECPERTEST_LOOPCNT_VAL_MAX 0x7fffffff +#define ATC_ECPERTEST_LOOPCNT_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_WAKEUPNUM_VAL_MIN 0 +#define ATC_ECPERTEST_WAKEUPNUM_VAL_MAX 5 +#define ATC_ECPERTEST_WAKEUPNUM_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_WAKEUPEN_VAL_MIN 0 +#define ATC_ECPERTEST_WAKEUPEN_VAL_MAX 1 +#define ATC_ECPERTEST_WAKEUPEN_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_WAKEUPEDGE_VAL_MIN 0 +#define ATC_ECPERTEST_WAKEUPEDGE_VAL_MAX 1 +#define ATC_ECPERTEST_WAKEUPEDGE_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_SLEEPMODE_VAL_MIN 0 +#define ATC_ECPERTEST_SLEEPMODE_VAL_MAX 9 +#define ATC_ECPERTEST_SLEEPMODE_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_AONIOPWRCTRL_VAL_MIN 0 +#define ATC_ECPERTEST_AONIOPWRCTRL_VAL_MAX 1 +#define ATC_ECPERTEST_AONIOPWRCTRL_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_AONIONUM_VAL_MIN 0 +#define ATC_ECPERTEST_AONIONUM_VAL_MAX 8 +#define ATC_ECPERTEST_AONIONUM_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_AONIOLEVEL_VAL_MIN 0 +#define ATC_ECPERTEST_AONIOLEVEL_VAL_MAX 1 +#define ATC_ECPERTEST_AONIOLEVEL_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_AONIOLATCH_VAL_MIN 0 +#define ATC_ECPERTEST_AONIOLATCH_VAL_MAX 1 +#define ATC_ECPERTEST_AONIOLATCH_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_AONIOLDOCASENUM_VAL_MIN 0 +#define ATC_ECPERTEST_AONIOLDOCASENUM_VAL_MAX 2 +#define ATC_ECPERTEST_AONIOLDOCASENUM_VAL_DEFAULT 0 + +#define ATC_ECPERTEST_MCUMODECASENUM_VAL_MIN 0 +#define ATC_ECPERTEST_MCUMODECASENUM_VAL_MAX 1 +#define ATC_ECPERTEST_MCUMODECASENUM_VAL_DEFAULT 0 + + +/* AT+ECI2COPEN */ +#define ATC_I2C_INSTANCE_VAL_MIN 0 +#define ATC_I2C_INSTANCE_VAL_MAX 1 +#define ATC_I2C_INSTANCE_VAL_DEFAULT 0 + +#define ATC_I2C_SPEED_VAL_MIN 100 +#define ATC_I2C_SPEED_VAL_MAX 1000 +#define ATC_I2C_SPEED_VAL_DEFAULT 100 + +#define ATC_I2C_SLAVEADDRESS_VAL_MIN 0x1 +#define ATC_I2C_SLAVEADDRESS_VAL_MAX 0x3ff +#define ATC_I2C_SLAVEADDRESS_VAL_DEFAULT 0x55 + +#define ATC_I2C_DATALEN_VAL_MIN 1 +#define ATC_I2C_DATALEN_VAL_MAX 511 +#define ATC_I2C_DATALEN_VAL_DEFAULT 1 + +/* AT+ECSPIOPEN */ +#define ATC_SPI_INSTANCE_VAL_MIN 0 +#define ATC_SPI_INSTANCE_VAL_MAX 1 +#define ATC_SPI_INSTANCE_VAL_DEFAULT 0 + +#define ATC_SPI_SPEED_VAL_MIN 1 +#define ATC_SPI_SPEED_VAL_MAX 10000000 // 10M +#define ATC_SPI_SPEED_VAL_DEFAULT 100000 + +#define ATC_SPI_CPOL_VAL_MIN 0 +#define ATC_SPI_CPOL_VAL_MAX 1 +#define ATC_SPI_CPOL_VAL_DEFAULT 0 + +#define ATC_SPI_CPHA_VAL_MIN 0 +#define ATC_SPI_CPHA_VAL_MAX 1 +#define ATC_SPI_CPHA_VAL_DEFAULT 0 + +#define ATC_SPI_DATALEN_VAL_MIN 1 +#define ATC_SPI_DATALEN_VAL_MAX 1024 +#define ATC_SPI_DATALEN_VAL_DEFAULT 1 + +#define ATC_ECONEWREAD_ADDR_STR_LEN 10 +#define ATC_ECONEWREAD_ADDR_STR_DEFAULT NULL + +#define ATC_ECREGWRITE_ADDR_STR_LEN 10 +#define ATC_ECREGWRITE_ADDR_STR_DEFAULT NULL + +#define ATC_ECREGWRITE_VAL_STR_LEN 10 +#define ATC_ECREGWRITE_VAL_STR_DEFAULT NULL + +CmsRetId pdevECPERTEST(const AtCmdInputContext *pAtCmdReq); + +CmsRetId pdevECI2COPEN(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECI2CREAD(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECI2CWRITE(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECI2CCLOSE(const AtCmdInputContext *pAtCmdReq); + +CmsRetId pdevECONEWOPEN(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECONEWREAD(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECONEWWRITE(const AtCmdInputContext *pAtCmdReq); + +CmsRetId pdevECSPIOPEN(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSPIREAD(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSPIWRITE(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSPITRANSFER(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSPICLOSE(const AtCmdInputContext *pAtCmdReq); + +CmsRetId pdevECREGREAD(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECREGWRITE(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdevECSWMODE(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_product.h b/PLAT/middleware/developed/at/atcust/inc/atec_product.h new file mode 100644 index 0000000..9d8d2d4 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_product.h @@ -0,0 +1,88 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_product.h +* +* Description: production related command +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_PRODUCT_H__ +#define __ATEC_PRODUCT_H__ + +#include "at_util.h" + + +/* AT+ECSLEEP */ +#define ECSLEEP_HANDLE_CREATED 0x1 +#define ECSLEEP_HANDLE_NOT_CREATED 0x0 + +#define ECSLEEP_HIB2 0x0 +#define ECSLEEP_HIB1 0x1 +#define ECSLEEP_SLP2 0x2 +#define ECSLEEP_SLP1 0x3 +#define ECSLEEP_OFF 0x4 + +#define CC_ECSLEEP_VALUE_MIN 0 +#define CC_ECSLEEP_VALUE_MAX 4 +#define CC_ECSLEEP_VALUE_DEF 0 + +/* AT+ECSAVEFAC */ +#define SAVEFAC_0_STR_LEN 16 +#define SAVEFAC_0_STR_BUF_LEN (SAVEFAC_0_STR_LEN +1) +#define SAVEFAC_0_STR_DEF NULL + +/* AT+ECIPR */ +#define ATC_ECIPR_MAX_PARM_STR_LEN 32 +#define ATC_ECIPR_MAX_PARM_STR_DEFAULT NULL + +/* AT+ECNPICFG */ +#define ATC_ECNPICFG_MAX_PARM_STR_LEN 32 +#define ATC_ECNPICFG_MAX_PARM_STR_DEFAULT NULL + +#define ATC_ECNPICFG_RFCALI_VAL_MIN 0 +#define ATC_ECNPICFG_RFCALI_VAL_MAX 1 +#define ATC_ECNPICFG_RFCALI_VAL_DEFAULT 0 /* full functionality */ + +#define ATC_ECNPICFG_RFNST_VAL_MIN 0 +#define ATC_ECNPICFG_RFNST_VAL_MAX 1 +#define ATC_ECNPICFG_RFNST_VAL_DEFAULT 0 /* full functionality */ + +/* AT+ECPRODMODE */ +#define ATC_ECPRODMODE_MAX_PARM_STR_LEN 32 + +/* AT+ECATE */ +#define ATC_ECATE_0_VAL_MIN 0 +#define ATC_ECATE_0_VAL_MAX 1 +#define ATC_ECATE_0_VAL_DEFAULT 0 + +/* AT+ECVERSION */ +#define ATC_ECVERSION_0_VAL_MIN 0 +#define ATC_ECVERSION_0_VAL_MAX 0xffffffff +#define ATC_ECVERSION_0_VAL_DEFAULT 0 + +/* AT+ECGMDATA */ +#define ATC_ECGMDATA_MAX_PARM_STR_LEN 2048 +#define ATC_ECGMDATA_MAX_PARM_STR_DEFAULT NULL + +CmsRetId pdECRFTEST(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECSLEEP(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECSAVEFAC(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECIPR(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdNPICFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECRFSTAT(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECPRODMODE(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECATE(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECGMDATA(const AtCmdInputContext *pAtCmdReq); +CmsRetId pdECVERSION(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_ssl.h b/PLAT/middleware/developed/at/atcust/inc/atec_ssl.h new file mode 100644 index 0000000..a6e21c8 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_ssl.h @@ -0,0 +1,87 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_http.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_SSL_H +#define _ATEC_SSL_H + +#include "at_util.h" +#include "at_ssl_task.h" + +#define SSL_MAX_RSP_LEN 512 +/* AT+SSLCFG */ +#define SSLCFG_CONTEXTID_MIN 0 +#define SSLCFG_CONTEXTID_MAX 5 +#define SSLCFG_CONTEXTID_DEF 0 +#define SSLCFG_VERSION_MIN 0 +#define SSLCFG_VERSION_MAX 4 +#define SSLCFG_VERSION_DEF 4 +#define SSLCFG_CIPHSUIT_MAX_SIZE 7 +#define SSLCFG_CIPHSUIT_DEF 0xFFFF +#define SSLCFG_DTLS_MIN 0 +#define SSLCFG_DTLS_MAX 1 +#define SSLCFG_DTLS_DEF 0 +#define SSLCFG_SECLEVEL_MIN 0 +#define SSLCFG_SECLEVEL_MAX 2 +#define SSLCFG_SECLEVEL_DEF 0 +#define SSLCFG_NEGOTIME_MIN 10 +#define SSLCFG_NEGOTIME_MAX 300 +#define SSLCFG_NEGOTIME_DEF 300 +#define SSLCFG_DTLSVER_MIN 0 +#define SSLCFG_DTLSVER_MAX 1 +#define SSLCFG_DTLSVER_DEF 0 +#define SSLCFG_CACHE_MIN 0 +#define SSLCFG_CACHE_MAX 1 +#define SSLCFG_CACHE_DEF 1 +#define SSLCFG_SNI_MIN 0 +#define SSLCFG_SNI_MAX 1 +#define SSLCFG_SNI_DEF 0 +#define SSLCFG_IGNORE_MIN 0 +#define SSLCFG_IGNORE_MAX 1 +#define SSLCFG_IGNORE_DEF 1 + +/* AT+SSLOPEN */ +#define SSLOPEN_PDPCXTID_MIN 1 +#define SSLOPEN_PDPCXTID_MAX 15 +#define SSLOPEN_PDPCXTID_DEF 0 +#define SSLOPEN_SSLCXTID_MIN 0 +#define SSLOPEN_SSLCXTID_MAX 5 +#define SSLOPEN_SSLCXTID_DEF 0 +#define SSLOPEN_CLIENTID_MIN 0 +#define SSLOPEN_CLIENTID_MAX MAX_SSL_CLIENT_INSTANCE-1 +#define SSLOPEN_CLIENTID_DEF 0 +#define SSLOPEN_URL_MAX_LEN SSL_URL_MAX_LEN +#define SSLOPEN_PORT_MIN 0 +#define SSLOPEN_PORT_MAX 0xFFFF +#define SSLOPEN_PORT_DEF 0 +#define SSLOPEN_ACCESS_MIN 0 +#define SSLOPEN_ACCESS_MAX 1 +#define SSLOPEN_ACCESS_DEF 0 +/* AT+SSLSEND */ +#define SSLOPEN_SENDLEN_MIN 1 +#define SSLOPEN_SENDLEN_MAX 1460 +#define SSLOPEN_SENDLEN_DEF 1 + +CmsRetId sslInputSendData(uint8_t chanId, uint8_t *pData, uint16_t dataLength); +void sslSendCancel(void); + +CmsRetId sslCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId sslOPEN(const AtCmdInputContext *pAtCmdReq); +CmsRetId sslSEND(const AtCmdInputContext *pAtCmdReq); +CmsRetId sslCLOSE(const AtCmdInputContext *pAtCmdReq); +CmsRetId sslSTATE(const AtCmdInputContext *pAtCmdReq); + +#endif + diff --git a/PLAT/middleware/developed/at/atcust/inc/atec_tcpip.h b/PLAT/middleware/developed/at/atcust/inc/atec_tcpip.h new file mode 100644 index 0000000..529acf3 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/atec_tcpip.h @@ -0,0 +1,514 @@ +/****************************************************************************** + * (C) Copyright 2018 AirM2M International Ltd. + * All Rights Reserved +******************************************************************************* + * Filename: atec_tcpip.h + * + * Description: + * + * History: + * + * Notes: + * +******************************************************************************/ +#ifndef _ATEC_TCPIP_H +#define _ATEC_TCPIP_H + +#include "at_util.h" + + + +/* AT+SKTCREATE */ +#define SKTCREATE_0_MIN 1 +#define SKTCREATE_0_MAX 2 +#define SKTCREATE_0_DEF 1 +#define SKTCREATE_1_MIN 1 +#define SKTCREATE_1_MAX 3 +#define SKTCREATE_1_DEF 1 +#define SKTCREATE_2_MIN 0 +#define SKTCREATE_2_MAX 0xff +#define SKTCREATE_2_DEF 0 + +/* AT+SKTSEND */ +#define SKTSEND_0_MIN AT_SOC_FD_MIN +#define SKTSEND_0_MAX AT_SOC_FD_MAX +#define SKTSEND_0_DEF AT_SOC_FD_DEF +#define SKTSEND_1_MIN 1 +#define SKTSEND_1_MAX SUPPORT_MAX_SOCKET_RAW_DATA_LENGTH +#define SKTSEND_1_DEF 1 +#define SKTSEND_2_STR_MAX_LEN 6 +#define SKTSEND_2_STR_DEF NULL +#define SKTSEND_3_MIN 0 +#define SKTSEND_3_MAX 2 +#define SKTSEND_3_DEF 0 +#define SKTSEND_4_MIN 0 +#define SKTSEND_4_MAX 1 +#define SKTSEND_4_DEF 0 + +#define SKTSENDT_0_MIN AT_SOC_FD_MIN +#define SKTSENDT_0_MAX AT_SOC_FD_MAX +#define SKTSENDT_0_DEF AT_SOC_FD_DEF +#define SKTSENDT_1_MIN 1 +#define SKTSENDT_1_MAX SUPPORT_MAX_SOCKET_RAW_DATA_LENGTH +#define SKTSENDT_1_DEF -1 +#define SKTSENDT_2_MIN 0 +#define SKTSENDT_2_MAX 2 +#define SKTSENDT_2_DEF 0 +#define SKTSENDT_3_MIN 0 +#define SKTSENDT_3_MAX 1 +#define SKTSENDT_3_DEF 0 + +/* AT+SKTCONNECT */ +#define SKTCONNECT_0_SEQ_MIN AT_SOC_FD_MIN +#define SKTCONNECT_0_SEQ_MAX AT_SOC_FD_MAX//max socket fd +#define SKTCONNECT_0_SEQ_DEF AT_SOC_FD_DEF +#define SKTCONNECT_1_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define SKTCONNECT_1_ADDR_STR_DEF NULL +#define SKTCONNECT_2_PORT_MIN AT_SOC_PORT_MIN +#define SKTCONNECT_2_PORT_MAX AT_SOC_PORT_MAX +#define SKTCONNECT_2_PORT_DEF 0 + +/* AT+SKTBIND */ +#define SKTBIND_0_SEQ_MIN AT_SOC_FD_MIN +#define SKTBIND_0_SEQ_MAX AT_SOC_FD_MAX//max socket fd +#define SKTBIND_0_SEQ_DEF AT_SOC_FD_DEF +#define SKTBIND_1_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define SKTBIND_1_ADDR_STR_DEF NULL +#define SKTBIND_2_PORT_MIN 0 +#define SKTBIND_2_PORT_MAX AT_SOC_PORT_MAX +#define SKTBIND_2_PORT_DEF 0 + +/* AT+SKTSTATUS */ +#define SKTSTATUS_0_SEQ_MIN AT_SOC_FD_MIN +#define SKTSTATUS_0_SEQ_MAX AT_SOC_FD_MAX//max socket fd +#define SKTSTATUS_0_SEQ_DEF 0 + +/* AT+SKTDELETE */ +#define SKTDELETE_0_SEQ_MIN AT_SOC_FD_MIN +#define SKTDELETE_0_SEQ_MAX AT_SOC_FD_MAX//max socket fd +#define SKTDELETE_0_SEQ_DEF AT_SOC_FD_DEF + +#define MAX_URL_IPADDR_LEN 255 + + +/*AT+ECSNTP*/ +#define SNTP_0_STR_MAX_LEN MAX_URL_IPADDR_LEN +#define SNTP_0_STR_DEF NULL +#define SNTP_DEC_1_MIN 0 +#define SNTP_DEC_1_MAX AT_SOC_PORT_MAX +#define SNTP_DEC_1_DEF 0 +#define SNTP_DEC_2_MIN 0 +#define SNTP_DEC_2_MAX 1 +#define SNTP_DEC_2_DEF 0 + +/* AT+ECPING */ +#define PING_DEC_0_MIN 0 +#define PING_DEC_0_MAX 0 +#define PING_DEC_0_DEF 0 +#define PING_0_STR_MAX_LEN MAX_URL_IPADDR_LEN +#define PING_0_STR_DEF NULL +#define PING_1_COUNT_MIN 1 +#define PING_1_COUNT_MAX 255 +#define PING_1_COUNT_DEF 4 +#define PING_2_PAYLOAD_MIN 1 +#define PING_2_PAYLOAD_MAX 1500 +#define PING_2_PAYLOAD_DEF 32 +#define PING_3_TIMEOUT_MIN 1 +#define PING_3_TIMEOUT_MAX 10*60*1000 +#define PING_3_TIMEOUT_DEF 20000 +#define PING_4_RAI_FLAG_MIN 0 +#define PING_4_RAI_FLAG_MAX 1 +#define PING_4_RAI_FLAG_DEF 0 + + +/* AT+CMDNS */ +#define CMDNS_0_STR_MAX_LEN MAX_URL_IPADDR_LEN +#define CMDNS_0_STR_DEF NULL + +/* AT+ECIPERF */ +#define ECIPERF_0_ACT_MIN 0 +#define ECIPERF_0_ACT_MAX 5 +#define ECIPERF_0_ACT_DEF 0 + +#define ECIPERF_1_PROTO_MIN 0 //UDP +#define ECIPERF_1_PROTO_MAX 1 //TCP +#define ECIPERF_1_PROTO_DEF 0 //UDP + +#define ECIPERF_2_PORT_MIN AT_SOC_PORT_MIN +#define ECIPERF_2_PORT_MAX AT_SOC_PORT_MAX +#define ECIPERF_2_PORT_DEF 5001 + +#define ECIPERF_3_STR_MAX_LEN 64 +#define ECIPERF_3_STR_DEF NULL + +#define ECIPERF_4_TPT_MIN 1 +#define ECIPERF_4_TPT_MAX 12000000 //12M bps +#define ECIPERF_4_TPT_DEF 20000 //20kbps + +#define ECIPERF_5_PAYLOAD_MIN 36 +#define ECIPERF_5_PAYLOAD_MAX 1472 +#define ECIPERF_5_PAYLOAD_DEF 940 + +#define ECIPERF_6_PKG_NUM_MIN 1 +#define ECIPERF_6_PKG_NUM_MAX 65000 +#define ECIPERF_6_PKG_NUM_DEF 0 + +#define ECIPERF_7_DURATION_MIN 1 +#define ECIPERF_7_DURATION_MAX 65000 +#define ECIPERF_7_DURATION_DEF 65000 + +#define ECIPERF_8_RPT_INTERVAL_MIN 1 +#define ECIPERF_8_RPT_INTERVAL_MAX 65000 +#define ECIPERF_8_RPT_INTERVAL_DEF 10 + +/* AT+ECDNSCFG */ +#define ECDNSCFG_DNS_NUM 4 + +#define ECDNSCFG_DNS_STR_MAX_LEN 64 +#define ECDNSCFG_DNS_STR_DEF PNULL +#define ATEC_ECDNSCFG_GET_CNF_STR_LEN 256 +#define ATEC_ECDNSCFG_GET_CNF_TMP_STR_LEN 50 + +/* AT+ECNETCFG */ +#define ECNETCFG_0_MAX_PARM_STR_LEN 32 +#define ECNETCFG_0_MAX_PARM_STR_DEFAULT NULL +#define ECNETCFG_1_PPP_AUTH_SELECT_MIN 0 +#define ECNETCFG_1_PPP_AUTH_SELECT_MAX 1 +#define ECNETCFG_1_PPP_AUTH_SELECT_DEF 0 +#define ECNETCFG_1_NAT_MIN 0 +#define ECNETCFG_1_NAT_MAX 1 +#define ECNETCFG_1_NAT_DEF 0 +#define ECNETCFG_2_HOST_ADDR_STR_MAX_LEN 64 +#define ECNETCFG_2_HOST_ADDR_STR_DEFAULT NULL + +/* AT+ECNETDEVCTL */ +#define ECNETDEVCTL_0_OP_MIN 0 +#define ECNETDEVCTL_0_OP_MAX 3 +#define ECNETDEVCTL_0_OP_DEF 0 +#define ECNETDEVCTL_1_CID_MIN 1 +#define ECNETDEVCTL_1_CID_MAX 15 +#define ECNETDEVCTL_1_CID_DEF 1 +#define ECNETDEVCTL_2_URCEN_MIN 0 +#define ECNETDEVCTL_2_URCEN_MAX 1 +#define ECNETDEVCTL_2_URCEN_DEF 0 + + +/* AT+ECSOCR*/ +#define ECSOCR_0_TYPE_STR_MAX_LEN 6 +#define ECSOCR_0_TYPE_STR_DEF NULL +#define ECSOCR_1_PROTOCOL_MIN 6 +#define ECSOCR_1_PROTOCOL_MAX 17 +#define ECSOCR_1_PROTOCOL_DEF 17 +#define ECSOCR_2_LISTEN_PORT_MIN 0 +#define ECSOCR_2_LISTEN_PORT_MAX AT_SOC_PORT_MAX +#define ECSOCR_2_LISTEN_PORT_DEF 0 +#define ECSOCR_3_RECEIVE_CONTROL_MIN 0 +#define ECSOCR_3_RECEIVE_CONTROL_MAX 1 +#define ECSOCR_3_RECEIVE_CONTROL_DEF 1 +#define ECSOCR_4_AF_TYPE_STR_MAX_LEN 8 +#define ECSOCR_4_AF_TYPE_STR_DEF NULL +#define ECSOCR_5_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSOCR_5_IP_ADDR_STR_DEF NULL + +/*AT+ECSOST*/ +#define ECSOST_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOST_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOST_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOST_1_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSOST_1_IP_ADDR_STR_DEF NULL +#define ECSOST_2_REMOTE_PORT_MIN AT_SOC_PORT_MIN +#define ECSOST_2_REMOTE_PORT_MAX AT_SOC_PORT_MAX +#define ECSOST_2_REMOTE_PORT_DEF 0 +#define ECSOST_3_LENGTH_MIN AT_SOC_UL_LENGTH_MIN +#define ECSOST_3_LENGTH_MAX AT_SOC_UL_LENGTH_MAX +#define ECSOST_3_LENGTH_DEF 0 +#define ECSOST_4_DATA_MAX_LEN AT_SOC_UL_LENGTH_MAX +#define ECSOST_4_DATA_DEF NULL +#define ECSOST_5_SEQUENCE_MIN AT_SOC_UL_DATA_SEQUENCE_MIN +#define ECSOST_5_SEQUENCE_MAX AT_SOC_UL_DATA_SEQUENCE_MAX +#define ECSOST_5_SEQUENCE_DEF 0 +#define ECSOST_6_SEGMENT_ID_MIN AT_SOC_UL_SEGMENT_ID_MIN +#define ECSOST_6_SEGMENT_ID_MAX AT_SOC_UL_SEGMENT_ID_MAX +#define ECSOST_6_SEGMENT_ID_DEF 0 +#define ECSOST_7_SEGMENT_NUM_MIN AT_SOC_UL_SEGMENT_NUM_MIN +#define ECSOST_7_SEGMENT_NUM_MAX AT_SOC_UL_SEGMENT_NUM_MAX +#define ECSOST_7_SEGMENT_NUM_DEF 0 + +#define ECSOSTT_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOSTT_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOSTT_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOSTT_1_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSOSTT_1_IP_ADDR_STR_DEF NULL +#define ECSOSTT_2_REMOTE_PORT_MIN AT_SOC_PORT_MIN +#define ECSOSTT_2_REMOTE_PORT_MAX AT_SOC_PORT_MAX +#define ECSOSTT_2_REMOTE_PORT_DEF 0 +#define ECSOSTT_3_LENGTH_MIN AT_SOC_UL_LENGTH_MIN +#define ECSOSTT_3_LENGTH_MAX AT_SOC_UL_LENGTH_MAX +#define ECSOSTT_3_LENGTH_DEF -1 +#define ECSOSTT_4_SEQUENCE_MIN AT_SOC_UL_DATA_SEQUENCE_MIN +#define ECSOSTT_4_SEQUENCE_MAX AT_SOC_UL_DATA_SEQUENCE_MAX +#define ECSOSTT_4_SEQUENCE_DEF 0 +/*AT+ECSOSTF*/ +#define ECSOSTF_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOSTF_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOSTF_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOSTF_1_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSOSTF_1_IP_ADDR_STR_DEF NULL +#define ECSOSTF_2_REMOTE_PORT_MIN AT_SOC_PORT_MIN +#define ECSOSTF_2_REMOTE_PORT_MAX AT_SOC_PORT_MAX +#define ECSOSTF_2_REMOTE_PORT_DEF 0 +#define ECSOSTF_3_FLAG_STR_MAX_LEN 5 +#define ECSOSTF_3_FLAG_STR_DEF NULL +#define ECSOSTF_4_LENGTH_MIN AT_SOC_UL_LENGTH_MIN +#define ECSOSTF_4_LENGTH_MAX AT_SOC_UL_LENGTH_MAX +#define ECSOSTF_4_LENGTH_DEF 0 +#define ECSOSTF_5_DATA_MAX_LEN AT_SOC_UL_LENGTH_MAX +#define ECSOSTF_5_DATA_DEF NULL +#define ECSOSTF_6_SEQUENCE_MIN AT_SOC_UL_DATA_SEQUENCE_MIN +#define ECSOSTF_6_SEQUENCE_MAX AT_SOC_UL_DATA_SEQUENCE_MAX +#define ECSOSTF_6_SEQUENCE_DEF 0 +#define ECSOSTF_7_SEGMENT_ID_MIN AT_SOC_UL_SEGMENT_ID_MIN +#define ECSOSTF_7_SEGMENT_ID_MAX AT_SOC_UL_SEGMENT_ID_MAX +#define ECSOSTF_7_SEGMENT_ID_DEF 0 +#define ECSOSTF_8_SEGMENT_NUM_MIN AT_SOC_UL_SEGMENT_NUM_MIN +#define ECSOSTF_8_SEGMENT_NUM_MAX AT_SOC_UL_SEGMENT_NUM_MAX +#define ECSOSTF_8_SEGMENT_NUM_DEF 0 +#define ECSOSTFT_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOSTFT_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOSTFT_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOSTFT_1_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSOSTFT_1_IP_ADDR_STR_DEF NULL +#define ECSOSTFT_2_REMOTE_PORT_MIN AT_SOC_PORT_MIN +#define ECSOSTFT_2_REMOTE_PORT_MAX AT_SOC_PORT_MAX +#define ECSOSTFT_2_REMOTE_PORT_DEF 0 +#define ECSOSTFT_3_FLAG_STR_MAX_LEN 5 +#define ECSOSTFT_3_FLAG_STR_DEF NULL +#define ECSOSTFT_4_LENGTH_MIN AT_SOC_UL_LENGTH_MIN +#define ECSOSTFT_4_LENGTH_MAX AT_SOC_UL_LENGTH_MAX +#define ECSOSTFT_4_LENGTH_DEF -1 +#define ECSOSTFT_5_SEQUENCE_MIN AT_SOC_UL_DATA_SEQUENCE_MIN +#define ECSOSTFT_5_SEQUENCE_MAX AT_SOC_UL_DATA_SEQUENCE_MAX +#define ECSOSTFT_5_SEQUENCE_DEF 0 + +/*AT+ECQSOS*/ +#define ECQSOS_0_SOCKET1_ID_MIN AT_SOC_FD_MIN +#define ECQSOS_0_SOCKET1_ID_MAX AT_SOC_FD_MAX +#define ECQSOS_0_SOCKET1_ID_DEF AT_SOC_FD_DEF +#define ECQSOS_1_SOCKET2_ID_MIN AT_SOC_FD_MIN +#define ECQSOS_1_SOCKET2_ID_MAX AT_SOC_FD_MAX +#define ECQSOS_1_SOCKET2_ID_DEF AT_SOC_FD_DEF +#define ECQSOS_2_SOCKET3_ID_MIN AT_SOC_FD_MIN +#define ECQSOS_2_SOCKET3_ID_MAX AT_SOC_FD_MAX +#define ECQSOS_2_SOCKET3_ID_DEF AT_SOC_FD_DEF +#define ECQSOS_3_SOCKET4_ID_MIN AT_SOC_FD_MIN +#define ECQSOS_3_SOCKET4_ID_MAX AT_SOC_FD_MAX +#define ECQSOS_3_SOCKET4_ID_DEF AT_SOC_FD_DEF +#define ECQSOS_4_SOCKET5_ID_MIN AT_SOC_FD_MIN +#define ECQSOS_4_SOCKET5_ID_MAX AT_SOC_FD_MAX +#define ECQSOS_4_SOCKET5_ID_DEF AT_SOC_FD_DEF + +/*AT+ECSORF*/ +#define ECSORF_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSORF_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSORF_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSORF_1_LENGTH_ID_MIN AT_SOC_DL_LENGTH_MIN +#define ECSORF_1_LENGTH_ID_MAX AT_SOC_DL_LENGTH_MAX +#define ECSORF_1_LENGTH_ID_DEF 0 + +/*AT+ECSOCO*/ +#define ECSOCO_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOCO_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOCO_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOCO_1_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSOCO_1_IP_ADDR_STR_DEF NULL +#define ECSOCO_2_REMOTE_PORT_MIN AT_SOC_PORT_MIN +#define ECSOCO_2_REMOTE_PORT_MAX AT_SOC_PORT_MAX +#define ECSOCO_2_REMOTE_PORT_DEF 0 + +/*AT+ECSOSD*/ +#define ECSOSD_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOSD_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOSD_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOSD_1_LENGTH_MIN AT_SOC_UL_LENGTH_MIN +#define ECSOSD_1_LENGTH_MAX AT_SOC_UL_LENGTH_MAX +#define ECSOSD_1_LENGTH_DEF 0 +#define ECSOSD_2_DATA_MAX_LEN AT_SOC_UL_LENGTH_MAX +#define ECSOSD_2_DATA_DEF NULL +#define ECSOSD_3_FLAG_STR_MAX_LEN 5 +#define ECSOSD_3_FLAG_STR_DEF NULL +#define ECSOSD_3_FLAG_DEF 0 +#define ECSOSD_4_SEQUENCE_MIN AT_SOC_UL_DATA_SEQUENCE_MIN +#define ECSOSD_4_SEQUENCE_MAX AT_SOC_UL_DATA_SEQUENCE_MAX +#define ECSOSD_4_SEQUENCE_DEF 0 + +#define ECSOSDT_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOSDT_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOSDT_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSOSDT_1_LENGTH_MIN AT_SOC_UL_LENGTH_MIN +#define ECSOSDT_1_LENGTH_MAX AT_SOC_UL_LENGTH_MAX +#define ECSOSDT_1_LENGTH_DEF -1 +#define ECSOSDT_2_FLAG_STR_MAX_LEN 5 +#define ECSOSDT_2_FLAG_STR_DEF NULL +#define ECSOSDT_2_FLAG_DEF 0 +#define ECSOSDT_3_SEQUENCE_MIN AT_SOC_UL_DATA_SEQUENCE_MIN +#define ECSOSDT_3_SEQUENCE_MAX AT_SOC_UL_DATA_SEQUENCE_MAX +#define ECSOSDT_3_SEQUENCE_DEF 0 +/*AT+ECSOCL*/ +#define ECSOCL_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOCL_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOCL_0_SOCKET_ID_DEF AT_SOC_FD_DEF + +/*AT+ECSONMI*/ +#define ECSONMI_0_MODE_MIN AT_SOC_NOTIFY_MODE_MIN +#define ECSONMI_0_MODE_MAX AT_SOC_NOTIFY_MODE_MAX +#define ECSONMI_0_MODE_DEF AT_SOC_NOTIFY_MODE_IGNORE +#define ECSONMI_1_DL_BUFFER_MAX AT_SOC_PUBLIC_DL_BUFFER_MAX +#define ECSONMI_1_DL_BUFFER_MIN AT_SOC_PUBLIC_DL_BUFFER_MIN +#define ECSONMI_1_DL_BUFFER_DEF AT_SOC_PUBLIC_DL_BUFFER_IGNORE +#define ECSONMI_2_DL_PKG_NUM_MAX AT_SOC_PUBLIC_DL_PKG_NUM_MAX +#define ECSONMI_2_DL_PKG_NUM_MIN AT_SOC_PUBLIC_DL_PKG_NUM_MIN +#define ECSONMI_2_DL_PKG_NUM_DEF AT_SOC_PUBLIC_DL_PKG_NUM_IGNORE + +/*AT+ECSONMIE*/ +#define ECSONMIE_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSONMIE_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSONMIE_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSONMIE_1_MODE_MIN AT_SOC_NOTIFY_MODE_MIN +#define ECSONMIE_1_MODE_MAX AT_SOC_NOTIFY_MODE_PRIVATE_DISABLE +#define ECSONMIE_1_MODE_DEF AT_SOC_NOTIFY_MODE_IGNORE +#define ECSONMIE_2_DL_BUFFER_MAX AT_SOC_PRIVATE_DL_BUFFER_MAX +#define ECSONMIE_2_DL_BUFFER_MIN AT_SOC_PRIVATE_DL_BUFFER_MIN +#define ECSONMIE_2_DL_BUFFER_DEF AT_SOC_PRIVATE_DL_BUFFER_IGNORE +#define ECSONMIE_3_DL_PKG_NUM_MAX AT_SOC_PRIVATE_DL_PKG_NUM_MAX +#define ECSONMIE_3_DL_PKG_NUM_MIN AT_SOC_PRIVATE_DL_PKG_NUM_MIN +#define ECSONMIE_3_DL_PKG_NUM_DEF AT_SOC_PRIVATE_DL_PKG_NUM_IGNORE + +#define ECSOSTATUS_0_SOCKET_ID_MIN AT_SOC_FD_MIN +#define ECSOSTATUS_0_SOCKET_ID_MAX AT_SOC_FD_MAX +#define ECSOSTATUS_0_SOCKET_ID_DEF AT_SOC_FD_DEF +#define ECSRVSOCRTCP_0_LISTEN_PORT_MIN 10000 // tcpip port manager limited +#define ECSRVSOCRTCP_0_LISTEN_PORT_MAX 10015 +#define ECSRVSOCRTCP_0_LISTEN_PORT_DEF 10000 +#define ECSRVSOCRTCP_1_AF_TYPE_STR_MAX_LEN 8 +#define ECSRVSOCRTCP_1_AF_TYPE_STR_DEF NULL +#define ECSRVSOCRTCP_2_IP_ADDR_STR_MAX_LEN AT_SOC_IP_ADDR_STRING_LENGTH_MAX +#define ECSRVSOCRTCP_2_IP_ADDR_STR_DEF NULL +#define ECSRVSOCLLISTEN_0_SERVER_FD_MIN AT_SOC_FD_MIN +#define ECSRVSOCLLISTEN_0_SERVER_FD_MAX AT_SOC_FD_MAX +#define ECSRVSOCLLISTEN_0_SERVER_FD_DEF AT_SOC_FD_DEF +#define ECSRVSOCLCLIENT_0_SERVER_FD_MIN AT_SOC_FD_MIN +#define ECSRVSOCLCLIENT_0_SERVER_FD_MAX AT_SOC_FD_MAX +#define ECSRVSOCLCLIENT_0_SERVER_FD_DEF AT_SOC_FD_DEF +#define ECSRVSOCLCLIENT_1_CLIENT_FD_MIN AT_SOC_FD_MIN +#define ECSRVSOCLCLIENT_1_CLIENT_FD_MAX AT_SOC_FD_MAX +#define ECSRVSOCLCLIENT_1_CLIENT_FD_DEF AT_SOC_FD_ALL +#define ECCRVSOTCPSENDCLT_0_MIN AT_SOC_FD_MIN +#define ECCRVSOTCPSENDCLT_0_MAX AT_SOC_FD_MAX +#define ECCRVSOTCPSENDCLT_0_DEF AT_SOC_FD_DEF +#define ECCRVSOTCPSENDCLT_1_MIN 1 +#define ECCRVSOTCPSENDCLT_1_MAX SUPPORT_MAX_SOCKET_RAW_DATA_LENGTH +#define ECCRVSOTCPSENDCLT_1_DEF 1 +#define ECCRVSOTCPSENDCLT_2_STR_MAX_LEN 6 +#define ECCRVSOTCPSENDCLT_2_STR_DEF NULL +#define ECCRVSOTCPSENDCLT_3_MIN 0 +#define ECCRVSOTCPSENDCLT_3_MAX 2 +#define ECCRVSOTCPSENDCLT_3_DEF 0 +#define ECCRVSOTCPSENDCLT_4_MIN 0 +#define ECCRVSOTCPSENDCLT_4_MAX 1 +#define ECCRVSOTCPSENDCLT_4_DEF 0 +#define ECSRVSOTCPLISTENSTATUS_0_SERVER_FD_MIN AT_SOC_FD_MIN +#define ECSRVSOTCPLISTENSTATUS_0_SERVER_FD_MAX AT_SOC_FD_MAX +#define ECSRVSOTCPLISTENSTATUS_0_SERVER_FD_DEF AT_SOC_FD_DEF +#define ECCRVSOTCPSENDCLTT_0_MIN AT_SOC_FD_MIN +#define ECCRVSOTCPSENDCLTT_0_MAX AT_SOC_FD_MAX +#define ECCRVSOTCPSENDCLTT_0_DEF AT_SOC_FD_DEF +#define ECCRVSOTCPSENDCLTT_1_MIN 1 +#define ECCRVSOTCPSENDCLTT_1_MAX SUPPORT_MAX_SOCKET_RAW_DATA_LENGTH +#define ECCRVSOTCPSENDCLTT_1_DEF -1 +#define ECCRVSOTCPSENDCLTT_2_MIN 0 +#define ECCRVSOTCPSENDCLTT_2_MAX 2 +#define ECCRVSOTCPSENDCLTT_2_DEF 0 +#define ECCRVSOTCPSENDCLTT_3_MIN 0 +#define ECCRVSOTCPSENDCLTT_3_MAX 1 +#define ECCRVSOTCPSENDCLTT_3_DEF 0 + +#define ECSOCR_NAME "+ECSOCR" +#define ECSOST_NAME "+ECSOST" +#define ECSOSTT_NAME "+ECSOSTT" +#define ECSOSTF_NAME "+ECSOSTF" +#define ECSOSTFT_NAME "+ECSOSTFT" +#define ECQSOS_NAME "+ECQSOS" +#define ECSORF_NAME "+ECSORF" +#define ECSOCO_NAME "+ECSOCO" +#define ECSOSD_NAME "+ECSOSD" +#define ECSOSDT_NAME "+ECSOSDT" +#define ECSOCL_NAME "+ECSOCL" +#define ECSONMI_NAME "+ECSONMI" +#define ECSONMIE_NAME "+ECSONMIE" +#define ECSOSTATUS_NAME "+ECSOSTATUS" +#define ECSOCLI_NAME "+ECSOCLI" +#define ECSOSTR_NAME "+ECSOSTR" +#define ECQSOSR_NAME "+ECQSOSR" + +//#else +#if 0 +#define ECSOCR_NAME "+NSOCR" +#define ECSOST_NAME "+NSOST" +#define ECSOSTT_NAME "+NSOSTT" +#define ECSOSTF_NAME "+NSOSTF" +#define ECSOSTFT_NAME "+NSOSTFT" +#define ECQSOS_NAME "+NQSOS" +#define ECSORF_NAME "+NSORF" +#define ECSOCO_NAME "+NSOCO" +#define ECSOSD_NAME "+NSOSD" +#define ECSOSDT_NAME "+NSOSDT" +#define ECSOCL_NAME "+NSOCL" +#define ECSONMI_NAME "+NSONMI" +#define ECSONMIE_NAME "+NSONMIE" +#define ECSOSTATUS_NAME "+NSOSTATUS" +#define ECSOCLI_NAME "+NSOCLI" +#define ECSOSTR_NAME "+NSOSTR" +#define ECQSOSR_NAME "+NQSOSR" +#endif +CmsRetId nmSNTP(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmPING(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECDNS(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECIPERF(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTCREATE(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTSEND(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTSENDT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTSTATUS(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTCONNECT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTBIND(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSKTDELETE(const AtCmdInputContext *pAtCmdReq); + +CmsRetId nmECSOCR(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOST(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOSTT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOSTF(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOSTFT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECQSOS(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSORF(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOCO(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOSD(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOSDT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSOCL(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSONMI(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSONMIE(const AtCmdInputContext *pAtCmdReq); + +CmsRetId nmECSOSTATUS(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECDNSCFG(const AtCmdInputContext *pAtCmdReq); + +CmsRetId nmECSRVSOCRTCP(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSRVSOCLLISTEN(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSRVSOCLCLIENT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSRVSOTCPSENDCLT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSRVSOTCPLISTENSTATUS(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECSRVSOTCPSENDCLTT(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmSocketInputData(UINT8 chanId, UINT8 *pInput, UINT16 length); +void nmSocketFreeSendInfo(void); +CmsRetId nmECNETCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId nmECNETDEVCTL(const AtCmdInputContext *pAtCmdReq); + +#endif + diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_adc_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_adc_cnf_ind.h new file mode 100644 index 0000000..7956155 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_adc_cnf_ind.h @@ -0,0 +1,27 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_ADC_CNF_IND_H__ +#define __ATEC_ADC_CNF_IND_H__ + +#include "at_util.h" + +CmsRetId ecAdcCnf(UINT16 reqHandle, UINT16 rc, void *paras); +void atApplAdcProcCmsCnf(CmsApplCnf *pCmsCnf); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_alarm_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_alarm_cnf_ind.h new file mode 100644 index 0000000..088f714 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_alarm_cnf_ind.h @@ -0,0 +1,37 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_dm.h +* +* Description: Device manager +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_ALARM_H__ +#define __ATEC_ALARM_H__ + +#include "at_util.h" + + +typedef enum applAlarmPrimId_Enum +{ + APPL_ALARM_PRIM_ID_BASE = 0, + + APPL_ALARM_VOLT_IND, + APPL_ALARM_THERM_IND, + APPL_ALARM_PRIM_ID_END = 0xFF +}applAlarmPrimId; + + +void atApplAlarmProcCmsInd(CmsApplInd *pCmsInd); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_ctwing_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_ctwing_cnf_ind.h new file mode 100644 index 0000000..bcb80d1 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_ctwing_cnf_ind.h @@ -0,0 +1,26 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_ctwing_cnf_ind.h +* +* Description: Process ctwing related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_CTWING_CNF_IND_H_ +#define _ATEC_CTWING_CNF_IND_H_ + +#include "at_util.h" + +void atApplCtwProcCmsCnf(CmsApplCnf *pCmsCnf); +void atApplCtwProcCmsInd(CmsApplInd *pCmsInd); + +#endif + diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_dm_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_dm_cnf_ind.h new file mode 100644 index 0000000..6226640 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_dm_cnf_ind.h @@ -0,0 +1,30 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_DM_CNF_IND_H__ +#define __ATEC_DM_CNF_IND_H__ + +#include "at_util.h" + +CmsRetId dmCtccRecvInd(UINT16 reqhandle, void *paras); +CmsRetId dmCuccRecvInd(UINT16 reqhandle, void *paras); +CmsRetId dmCmccRecvInd(UINT16 reqhandle, void *paras); + +void atApplDmProcCmsInd(CmsApplInd *pCmsInd); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_example_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_example_cnf_ind.h new file mode 100644 index 0000000..5c181af --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_example_cnf_ind.h @@ -0,0 +1,34 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_EXAMPLE_CNF_IND_H__ +#define __ATEC_EXAMPLE_CNF_IND_H__ + +#include "at_util.h" + + +CmsRetId ecTestbCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId ecTestcCnf(UINT16 reqHandle, UINT16 rc, void *paras); + +CmsRetId ecTestcInd(UINT16 indHandle, void *paras); + +void atApplExampleProcCmsCnf(CmsApplCnf *pCmsCnf); +void atApplExampleProcCmsInd(CmsApplInd *pCmsInd); + + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_file_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_file_cnf_ind.h new file mode 100644 index 0000000..6747077 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_file_cnf_ind.h @@ -0,0 +1,42 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_FILE_CNF_IND_H__ +#define __ATEC_FILE_CNF_IND_H__ + +#include "at_util.h" + +CmsRetId fileOpenCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileReadCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileWriteCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileSeekCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId filePositionCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileTucatCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileCloseCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileRenameCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileEraseCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileDeleteCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileMsLdsCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileMsLstCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileMsDelCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileMsUplCnf(UINT16 reqHandle, UINT16 rc, void *paras); +CmsRetId fileMsDwlCnf(UINT16 reqHandle, UINT16 rc, void *paras); + +void atApplFileProcCmsCnf(CmsApplCnf *pCmsCnf); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_fwupd_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_fwupd_cnf_ind.h new file mode 100644 index 0000000..699c125 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_fwupd_cnf_ind.h @@ -0,0 +1,26 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename:atec_fwupd_cnf_ind.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_FWUPD_CNF_IND_H__ +#define __ATEC_FWUPD_CNF_IND_H__ + +#include "at_util.h" + +void atApplFwupdProcCmsCnf(CmsApplCnf *pCmsCnf); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_http_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_http_cnf_ind.h new file mode 100644 index 0000000..bf85c5d --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_http_cnf_ind.h @@ -0,0 +1,30 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_http_cnf_ind.h +* +* Description: Process http(s) client related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_HTTP_CNF_IND_H_ +#define _ATEC_HTTP_CNF_IND_H_ + +#include "at_util.h" + +//CmsRetId httpSendCnf(uint16_t reqHandle, uint16_t rc, void *paras); +//CmsRetId httpReadCnf(uint16_t reqHandle, uint16_t rc, void *paras); +//CmsRetId httpCloseCnf(uint16_t reqHandle, uint16_t rc, void *paras); + +void atApplHttpProcCmsCnf(CmsApplCnf *pCmsCnf); +void atApplHttpProcCmsInd(CmsApplInd *pCmsInd); + +#endif + diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_mqtt_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_mqtt_cnf_ind.h new file mode 100644 index 0000000..99f1e00 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_mqtt_cnf_ind.h @@ -0,0 +1,37 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_mqtt_cnf_ind.h +* +* Description: Process MQTT related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_MQTT_CNF_IND_H +#define _ATEC_MQTT_CNF_IND_H + +#include "at_util.h" +#include "atec_mqtt.h" + +CmsRetId mqttOpenInd(UINT16 indHandle, void *paras); +CmsRetId mqttCloseInd(UINT16 indHandle, void *paras); +CmsRetId mqttConnInd(UINT16 indHandle, void *paras); +CmsRetId mqttDiscInd(UINT16 indHandle, void *paras); +CmsRetId mqttSubInd(UINT16 indHandle, void *paras); +CmsRetId mqttUnSubInd(UINT16 indHandle, void *paras); +CmsRetId mqttPubInd(UINT16 indHandle, void *paras); + +CmsRetId mqttStatInd(UINT16 indHandle, void *paras); +CmsRetId mqttRecvInd(UINT16 indHandle, void *paras); + +void atApplMqttProcCmsCnf(CmsApplCnf *pCmsCnf); +void atApplMqttProcCmsInd(CmsApplInd *pCmsInd); +#endif + diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_ssl_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_ssl_cnf_ind.h new file mode 100644 index 0000000..ec8db2b --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_ssl_cnf_ind.h @@ -0,0 +1,31 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_ssl_cnf_ind.h +* +* Description: Process ssl client related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_SSL_CNF_IND_H_ +#define _ATEC_SSL_CNF_IND_H_ + +#include "at_util.h" + +CmsRetId sslOpenCnf(uint16_t reqHandle, uint16_t rc, void *paras); +CmsRetId httpReadCnf(uint16_t reqHandle, uint16_t rc, void *paras); +CmsRetId httpCloseCnf(uint16_t reqHandle, uint16_t rc, void *paras); + +void atApplSslProcCmsCnf(CmsApplCnf *pCmsCnf); +void atApplSslProcCmsInd(CmsApplInd *pCmsInd); + +#endif + + diff --git a/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_tcpip_cnf_ind.h b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_tcpip_cnf_ind.h new file mode 100644 index 0000000..0724d92 --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/inc/cnfind/atec_tcpip_cnf_ind.h @@ -0,0 +1,36 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_tcpip_cnf_ind.h +* +* Description: Process TCP/IP service related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_TCPIP_CNF_IND_API_H +#define _ATEC_TCPIP_CNF_IND_API_H + +#include "at_util.h" + +void atTcpIpProcNmApplCnf(CmsApplCnf *pApplCnf); +void atTcpIpProcNmApplInd(CmsApplInd *pApplInd); + +void atTcpIpProcSktApplCnf(CmsApplCnf *pApplCnf); +void atTcpIpProcSktApplInd(CmsApplInd *pApplInd); + +void atTcpIpProcSocApplCnf(CmsApplCnf *pApplCnf); +void atTcpIpProcSocApplInd(CmsApplInd *pApplInd); + +void atTcpIpProcSrvSocApplCnf(CmsApplCnf *pApplCnf); +void atTcpIpProcSrvSocApplInd(CmsApplInd *pApplInd); + + +#endif + diff --git a/PLAT/middleware/developed/at/atcust/src/readme.txt b/PLAT/middleware/developed/at/atcust/src/readme.txt new file mode 100644 index 0000000..acc841c --- /dev/null +++ b/PLAT/middleware/developed/at/atcust/src/readme.txt @@ -0,0 +1,5 @@ +at_cust_dev.c includes AT commands which may modifed by customer e.g. CGMR(set customer own version info) + +at_product.c includes AT commands for prodcution + +at_plat_dev.c in1udes AT commands defined by AirM2M for debug and misc purpose \ No newline at end of file diff --git a/PLAT/middleware/developed/at/atdecoder/inc/atc_decoder.h b/PLAT/middleware/developed/at/atdecoder/inc/atc_decoder.h new file mode 100644 index 0000000..bf4c69c --- /dev/null +++ b/PLAT/middleware/developed/at/atdecoder/inc/atc_decoder.h @@ -0,0 +1,1030 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATC_DECODER_H__ +#define __ATC_DECODER_H__ + +#include "osasys.h" +#include "at_api.h" + + +/****************************************************************************** + * +-----+ +-----+ + * | DTE | --> AT CMD --> | DCE | + * +-----+ +-----+ + * + * +-----+ +-----+ +-----+ + * | TE | --> AT CMD --> | TA |-->MT ctrl-->| MT | + * +-----+ +-----+ +-----+ + * TE: Terminal Equipment + * TA: Terminal Adaptor + * MT: Mobile Termination + * + * V.250 + * 1. Two types of commands: "action commands" and "parameter commands". + * A) "action commands" maybe: "executed" or "tested"; + * example: AT+CMD1 //"executed" + * AT+CMD1= //"executed" + * AT+CMD1=? //"tested" + * AT+CMD1? (ERROR) + * B) "parameter commands" maybe: "set", "read", or "tested"; + * example: AT+CMD2= //"set" + * AT+CMD2? //"read" + * AT+CMD2=? //"tested" + * + *============================================================================= + * 1. shall consist of either a "numeric" constant or a "string" constant. + * A) "numeric constants" are expressed in "numValue", "hexadecimal", or "binary" + * a) "numValue": "0" - "9" + * b) "hexadecimal": "0"-"9", "A"-"F", "a"-"f", should not contain: "0x" + * c) "binary": "0"-"1" + * B) "string" + * a) String constants shall consist of displayable displayable, in the range from + * 0x20 (Space or blank) to 0x7F (delete), inclusive, except for the characters: + * """ and "\" + * a) String constants shall be bounded at the beginning and end by the + * ouble-quote character: " + * b) Any character value may be included in the string by representing it + * as a backslash ("\") character followed by two hexadecimal digits; + * example: "\" => "\5C" + * => "\0D" + * """ => "\22" + * + *============================================================================== + * 1. A command line is made up of three elements: the prefix, the body, and the termination character. + * 2. The command line prefix consists of the characters "AT" (IA5 4/1, 5/4) or "at" (IA5 6/1, 7/4), or, + * to repeat the execution of the previous command line, the characters "A/" (IA5 4/1, 2/15) or "a/" + * (IA5 6/1, 2/15). + * 3. The body is made up of individual commands, Space characters (IA5 2/0) are ignored and may be used + * freely for formatting purposes, unless they are embedded in numeric or string constants (see 5.4.2.1 or 5.4.2.2). + * The termination character may not appear in the body. + * 4. The termination character may be selected by a user option (parameter S3), + * the default being CR (IA5 0/13). +******************************************************************************/ + + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ + + +/* + * ignore: +*/ +#define AT_IGNORE_SPACE_CHAR(pChr, pEnd) \ +do { \ + while (((*(pChr)) == ' ') && ((UINT32)(pChr) < (UINT32)(pEnd))) \ + (pChr)++; \ +}while(FALSE) + +/* + * ignore: +*/ +#define AT_IGNORE_SPACE_S3_S4_CHAR(pChr, S3, S4, pEnd) \ +do { \ + while (((*(pChr)) == ' ' || (*(pChr)) == (S3) || (*(pChr)) == (S4)) && ((UINT32)(pChr) < (UINT32)(pEnd))) \ + (pChr)++; \ +}while(FALSE) + + + +/* + * AT channel real number, this ID:0 is reserved for internal, so the real number should: CMS_CHAN_NUM -1 +*/ +#define ATC_CHAN_REAL_ENTITY_NUM (CMS_CHAN_NUM-1) + + + +/* + * Time out value for a AT CMD, + * When time out, just return ERROR +*/ +#define AT_DEFAULT_TIMEOUT_SEC ((UINT16)5) //5*sys tick + +#define AT_CMD_PARAM_MAX_NUM 32 //max parameters number +#define AT_CMD_MAX_NAME_LEN 32 + + +#define AT_CMD_MAX_PENDING_STR_LEN 8192 //MAX pending 8KB AT CMD +#define AT_CMD_MAX_PENDING_NODE_NUM 64 //MAX pending AT CMD input string node + + +/* + * S-parameter and special AT charcters +*/ +#define AT_S3_CMD_LINE_TERM_CHAR_DEFAULT '\r' +#define AT_S4_RESP_FORMAT_CHAR_DEFAULT '\n' +#define AT_S5_CMD_LINE_EDIT_CHAR_DEFAULT 0x08 +#define AT_SEPA_PARM_COMMA_CHAR ',' /*separator between compound values*/ +#define AT_SEPA_CMD_SEMICOLON_CHAR ';' +#define AT_EXT_CMD_PLUS_CHAR '+' +#define AT_EXT_CMD_STAR_CHAR '*' +#define AT_EXT_CMD_CARET_CHAR '^' +#define AT_SMALLEST_VALID_CHAR 0x20 + +#define AT_BE_VALID_CHAR(chr) \ + ((chr) >= 0x20 || (chr) == '\r' || (chr) == '\n') + + +/* + * +*/ +#define AT_BE_EXT_CMD_CHAR(cr) \ + ((cr) == AT_EXT_CMD_PLUS_CHAR || (cr) == AT_EXT_CMD_STAR_CHAR || (cr) == AT_EXT_CMD_CARET_CHAR) + + +/* + * set by ATS3/ATS4/ATS5 +*/ +#define AT_S3_CMD_LINE_TERM_CHAR_IDX (0) /* S3, Command line termination character, default: \r */ +#define AT_S4_RESP_FORMAT_CHAR_IDX (1) /* S4, Response formatting character, default: \n */ +#define AT_S5_CMD_LINE_EDIT_CHAR_IDX (2) /* S5, Command line editing character, default: Backspace , useless now */ + +#define AT_S_PARM_NUM (4) + +#if 0 +/* + * DEFAULT AT CHANNEL maybe not need to do "channel register" procedure, + * just set the default config/callback here +*/ +#define AT_DEFAULT_CHAN_NAME "UARTAT" +#endif + +/* + * AT RIL API CHANNEL not need to do "channel register" procedure, +*/ +#define AT_RIL_API_CHAN_NAME "RILAPI" + +/* + * For some solution (PMU enabled), UART maybe down, use this handshake string, to let MCU/PC know + * the chip is wake uped. + * MCU/PC -> UE: "HDSK" + * UE -> MCU/PC: "KSHD\r\n" +*/ +#define AT_HANDSHAKE_REQ_STR "HDSK" +#define AT_HANDSHAKE_RESP_STR "KSDH\r\n" +#define AT_HANDSHAKE_REQ_STR_LEN 6 //strlen("HDSK\r\n") +#define AT_HANDSHAKE_RESP_STR_LEN 6 //strlen("KSDH\r\n") + + +/****************************************************************************** + ***************************************************************************** + * COMMON ENUM + ***************************************************************************** +******************************************************************************/ + +/****************************************************************************** + * 1. Two types of commands: "action commands" and "parameter commands". + * A) "action commands" maybe: "executed" or "tested"; + * example: AT+CMD1 //"executed" + * AT+CMD1= //"set" + * AT+CMD1=? //"tested" + * AT+CMD1? (ERROR) + * B) "parameter commands" maybe: "set", "read", or "tested"; + * example: AT+CMD2 //"executed", ==> whether this is right? - TBD + * AT+CMD2= //"set" + * AT+CMD2? //"read" + * AT+CMD2=? //"tested" + *============================================================ + * Case: AT+CMD1 => type: AT_EXEC_REQ, and AtCmdInputContext->paramRealNum = 0 + * Case: AT+CMD2= => type: AT_SET_REQ, and AtCmdInputContext->paramRealNum = 0 + * Basic AT: + * 1. ATE0 => AT_SET_REQ + * ^ + * 2. AT => AT_EXEC_REQ + * ^ + * 3. ATI => AT_EXEC_REQ + * ^ + * 4. ATS3? => AT_READ_REQ + * ^ + * 5. ATS3=13 => AT_SET_REQ + * ^ + * 6. AT&F0 => AT_SET_REQ + * ^ + * 7. AT&F=? => AT_TEST_REQ + * ^ + * 8. AT&F? => AT_READ_REQ + * ^ + * 9. AT&F=0 => AT_BASIC_EXT_SET_REQ, some customer need to support such type of input + * ^ and act as: AT&F0. In fact, this is not a standard input. So here, we + * involve a new type: AT_BASIC_EXT_SET_REQ (Basic AT extended set request). +******************************************************************************/ +typedef enum AtCmdReqType_enum +{ + AT_INVALID_REQ_TYPE = 0, + AT_EXEC_REQ = 1, //AT+CMD1, ATI/AT&F, no parameter + AT_SET_REQ = 2, //AT+CMD2=, AT&F0/ATE0/ATS3=13 + AT_READ_REQ = 3, //AT+CMD2? + AT_TEST_REQ = 4, //AT+CMD2=? + AT_BASIC_EXT_SET_REQ= 5, //AT&F= + + AT_MAX_REQ = 15, +}AtCmdReqType; + +/****************************************************************************** + * 1. shall consist of either a "numeric" constant or a "string" constant. + * A) "numeric constants" are expressed in "numValue", "hexadecimal", or "binary" + * a) "numValue": "0" - "9" + * b) "hexadecimal": "0"-"9", "A"-"F", "a"-"f", should not contain: "0x" + * c) "binary": "0"-"1" + * B) "string" + * a) String constants shall consist of displayable displayable, in the range from + * 0x20 (Space or blank) to 0x7F (delete), inclusive, except for the characters: + * """ and "\" + * a) String constants shall be bounded at the beginning and end by the + * ouble-quote character: " + * b) Any character value may be included in the string by representing it + * as a backslash ("\") character followed by two hexadecimal digits; + * example: "\" => "\5C" + * => "\0D" + * """ => "\22" +******************************************************************************/ +typedef enum AtValueType_enum +{ + AT_DEC_VAL, /* INT32, value range: [-2147483648, 2147483647] */ + AT_HEX_VAL, /* INT32, only support range: [0, 0x7FFFFFFF] */ + AT_BIN_VAL, /* INT32, only support range: [0, 0x7FFFFFFF] */ + AT_STR_VAL, + + /* + * input parameters, could be "numeric" or "string" + * 1> AT decoder try to decode according to the input value, and set the valueType to: AT_DEC_VAL or AT_STR_VAL + * 2> If this parameter not input/present, then the parameter valueType is still: AT_MIX_VAL, let caller to descide it. + * Example: + * AT+CMD1=[,] //param2 is "AT_MIX_VAL" type + * a) AT+CMD1=1,2 + * AtParamValueCP[1].type = AT_DEC_VAL + * b) AT+CMD1=1,"abc" + * AtParamValueCP[1].type = AT_STR_VAL + * c) AT+CMD1=1 + * AtParamValueCP[1].type = AT_MIX_VAL + * AtParamValueCP[1].bDefault = TRUE + */ + AT_MIX_VAL, + AT_JSON_VAL, /*input parameter is JSON string format */ + + /* + * AT CMD last parameter, maybe a MIX value, contain special characters: ','';','\r\n', + * AT decoder don't care it, just pass the whole string to the AT processor + */ + AT_LAST_MIX_STR_VAL, + AT_MAX_VAL +}AtValueType; + +/****************************************************************************** + * 1. If is not recognized, one or more mandatory values are omitted, + * or one or more values are of the wrong type or outside the permitted range, + * the DCE issues the ERROR result code and terminates processing of the command line + * SO: + * a) mandatory, or optional; +******************************************************************************/ +typedef enum AtPresentType_enum +{ + AT_MUST_VAL, //mandatory + AT_OPT_VAL //optional +}AtPresentType; + +/****************************************************************************** + * 1. Basic Syntax commands + * a) Basic Syntax command format: + * [] + * where is either a single character, or the "&" character (IA5 2/6) + * followed by a single character + * Example: ATE0/ATE1 AT&F0 + * b) S-parameters: + * S? + * S= [] + * Example: ATS3? + * + * 2. Extended Syntax commands, two types: "action commands" and "parameter commands" + * a) action commands: + * + //execute + * +[=] //set + * +[=] //set + * +=? //test + * b) parameter commands + * + //execute + * +=[] //set + * +=[] //set + * +? //read + * +=? //test +******************************************************************************/ +typedef enum AtCmdSyntaxType_enum +{ + AT_BASIC_CMD, + AT_EXT_PARAM_CMD, + AT_EXT_ACT_CMD +}AtCmdSyntaxType; + +/* + * AT decoder return code +*/ +typedef enum AtcDecRetCode_enum +{ + ATC_DEC_OK, //AT command decode & proc OK, + ATC_DEC_NO_AT, //No AT command in line; + ATC_DEC_SYNTAX_ERR, //AT command format is not right + ATC_DEC_PROC_ERR //AT command procFunc error +}AtcDecRetCode; + +/* + * AT channel state +*/ +typedef enum AtcState_enum +{ + /* + * V250 3.1 + * Data signals from the DTE on circuit 103 are treated as command lines and processed by the DCE, + * and DCE responses are sent to the DTE on circuit 104. The DCE enters this state upon power-up. + */ + ATC_COMMAND_STATE, //default: command state + + /* + * V250 3.1 + * 1> Signals from the DTE on circuit 103 as command lines and sends responses to the DTE on circuit 104. + * Note: Data recv from MCU is treated as AT command. + * 2> Depending on the implementation, data received from the remote station during Online Command State may be + * either discarded or retained in the DCE until Online Data State is once again entered (by a command: ATO from the DTE). + * 3> Online Command State may be entered from Online Data state by a mechanism defined in 6.2.9 (DTR on-to-off transition if AT&D1) or + * by other manufacturer-defined means("+++"). + * Note, example: + * a) when in PPP online data state, if "+++" recv from MCU, then enter this state: ATC_ONLINE_COMMAND_STATE, + * and, PPP DL pkg recv from network, will be discard for easy. + */ + ATC_ONLINE_COMMAND_STATE, + + /* + * V250 3.1 + * Following states are all: online data state + * 1> In Online Data State, the DCE is communicating with a remote station. Data signals from the DTE on circuit 103 are treated as data and + * transmitted to the remote station, and data received from the remote station are delivered to the DTE on circuit 104. + * + */ + ATC_ONLINE_DATA_STATE, //online data state + + /* + * For SMS: + * The "Text" and "PDU" modes are transitory states and after each operation, + * control is automatically returned to the V.25ter "command" state or "on-line command" state. + * 1> "AT+CMGS=" (PDU mode) or "+CMGC=,[,[,[,[,]]]]" + * 2> ATEC SMS submodule. change the "atcState" to : ATC_SMS_CMGS_DATA_STATE; + * 3> ATC decoder, discard pending input sting, and forard following input to ATEC SMS mode; + * 4> ATEC SMS parse the input, and when meet: ctrl-z/ESC, then change the "atcState" to : ATC_COMMAND_STATE, and send/cancel this SMS + */ + ATC_SMS_CMGS_CMGC_DATA_STATE, + + /* + * For SMS: + * AT+CMGC, - TBD + */ + //ATC_SMS_CMGC_DATA_STATE, + + /* + * For SMS: + * AT+CMGW + * 1> "+CMGW=[,]" (PDU mode) or "+CMGW[=[,[,]]]" + * 2> ATEC SMS submodule. change the "atcState" to : ATC_SMS_CMGW_DATA_STATE; + * 3> ATC decoder, discard pending input sting, and forard following input to ATEC SMS mode; + * 4> ATEC SMS parse the input, and when meet: ctrl-z/ESC, then change the "atcState" to : ATC_COMMAND_STATE, and send/cancel this SMS + */ + ATC_SMS_CMGW_DATA_STATE, + + ATC_SMS_CNMA_DATA_STATE, + + ATC_MQTT_PUB_DATA_STATE, + + ATC_COAP_SEND_DATA_STATE, + + ATC_HTTP_INPUT_STATE, + + ATC_FILE_WRITE_DATA_STATE, + + ATC_SSL_SEND_INPUT_STATE, + + ATC_SOCKET_SEND_DATA_STATE, + + ATC_REF_SOCKET_SEND_DATA_STATE, + + ATC_REF_SOCKET_PASSTHROUGH_STATE, + + ATC_PPP_ONLINE_DATA_STATE, + + ATC_SSL_PASSTHROUGH_STATE, + + ATC_STATE_MAX = 0xFF +}AtcState; + + +/* + * AT channel config parameter +*/ +typedef enum AtcChanCfgItem_enum +{ + ATC_CFG_S3_PARAM, + ATC_CFG_S4_PARAM, + ATC_CFG_S5_PARAM, + ATC_CFG_ECHO_PARAM, + ATC_CFG_SUPPRESS_PARAM, + ATC_CFG_VERBOSE_PARAM, + + ATC_CFG_PARAM_NUM +}AtcChanCfgItem; + +/* + * URC RI (Ring indication) event state +*/ +typedef enum +{ + AT_URC_RI_NONE, + AT_URC_RI_TIGGER, /* RI tiggered, and wait for done */ + AT_RI_DONE_URC_DELAY, /* RI done, and URC need delay */ + AT_URC_RI_DONE /* RI done, and delay timeout, could Tx URC */ +}AtUrcRiState; + + +/* +*/ +typedef enum +{ + AT_DATA_STATE_DATA_INPUT, /* "pArg" => AtDataStateDataInput */ + AT_DATA_STATE_DTR_EVT, /* DTR (Data Terminal Ready) on-to-off transition event, when recv in online data state + * 1> if AT&D1 cfg, channel enters: ATC_ONLINE_COMMAND_STATE, and could back to data state + * via AT: ATO + * 2> if AT&D2 cfg, online data should be disconnnected, and enters: ATC_COMMAND_STATE + */ + AT_ONLINE_CMD_ATO_EVT, /* when ATC_ONLINE_COMMAND_STATE, recv ATO event, return to online data state. + * "pArg" => AtOnlineCmdATOInput + */ +}AtDataAndOnlineCmdSEvt; + +/* + * API func, which called when AT channel enter: DATA_STATE and ATC_ONLINE_COMMAND_STATE. + * Note + * 1> for event: AT_DATA_STATE_DATA_INPUT + * a) if this callback not return CMS_RET_SUCC, the AT channel state will change back to: ATC_COMMAND_STATE, in the caller + * 2> for event: AT_ONLINE_CMD_ATO_EVT, + * a) AT response should be replied (atcReply()) in this callback, and return CMS_RET_SUCC + * b) If not return CMS_RET_SUCC, the caller will call: atcReply() +*/ +typedef CmsRetId (*AtDataAndOnlineCmdStateFuncP)(UINT8 chanId, UINT8 curChanState, AtDataAndOnlineCmdSEvt eventId, void *pArg); + + +/****************************************************************************** + ***************************************************************************** + * STRUCTURE + ***************************************************************************** +******************************************************************************/ + +/* + * AT input parameter value +*/ +typedef struct AtParamValue_Tag +{ + UINT8 type; //AtValueType, parameter value type + BOOL bDefault; //if not set, just need to use the default value + BOOL inputQuote; //whether input string contain quote (""), for "AT_STR_VAL" type + UINT8 rsvd; + + + //AtDataValueType value; + union + { + /* + * AT_DEC_VAL, value range: [-2147483648, 2147483647] + * AT_HEX_VAL, only support range: [0, 0x7FFFFFFF] + * AT_BIN_VAL, only support range: [0, 0x7FFFFFFF] + */ + INT32 numValue; + + /* + * AT_STR_VAL, + * 1> don't need to free it, as point to the input AT command string, + * will free the whole AT CMD string, when all AT processed. + * 2> if input: "", then: bDefault = FALSE, pStr = PNULL; + * 3> if input: "abcdef", then + * ^pStr and "inputQuote" = TRUE + * 4> if input: abcdef, then: + * ^pStr and "inputQuote" = FALSE + */ + CHAR *pStr; + } value; +}AtParamValue; //8 bytes + +typedef const AtParamValue *AtParamValueCP; + +/* + * input context +*/ +typedef struct AtCmdInputContext_Tag +{ + UINT16 operaType : 4; //AtCmdReqType, AT REQ type + UINT16 chanId : 4; //channel ID, 0 - 15 + UINT16 tid : 5; //asyn guard timer index, 0 - 31; + UINT16 rsvd : 3; + + /* + * MAX parameters number of this AT CMD, set when this AT predefined in: AT_CMD_PRE_DEFINE() + */ + UINT8 paramMaxNum; + + /* + * Input paramters number at this time. + * Example: + * 1> AT defination: AT+CMD1=[,[,[,]]] + * 2> AT input: AT+CMD1="test",,9 + * Here: paramMaxNum = 4; + * paramRealNum = 3; + * pParamList[0].type = AT_STR_VAL; + * pParamList[0].bDefault = FALSE; + * pParamList[0].value.pStr = "test"; //"test" allocated in a heap memory + * pParamList[1].type = ... ; //type value pre-defined + * pParamList[1].bDefault = TRUE; + * pParamList[2].type = AT_DEC_VAL; + * pParamList[2].bDefault = FALSE; + * pParamList[2].value.numValue = 9 + */ + UINT8 paramRealNum; + + + /* + * Input parameters value list; + * 1> An array pointer, allocated in stack memory, don't need to free + * 2> Size = sizeof(AtParamValue)*AT_CMD_PARAM_MAX_NUM + */ + AtParamValue *pParamList; + +}AtCmdInputContext; //8 bytes + + +/****************************************************************************** + * V 250 + * AT parameter value attributes + * AT+=[] + * AT+=[] + * ========================================================================== + * 1. If is not recognized, one or more mandatory values are omitted, + * or one or more values are of the wrong type or outside the permitted range, + * the DCE issues the ERROR result code and terminates processing of the command line + * SO: + * a) mandatory, or optional; + * b) type: numeric, or string; + * c) Range: numeric: [min, max] + * string: [minlength, maxLength] + * + * 2. Parameters may be defined as "read-only" or "read-write". "Read-only" parameters + * are used to provide status or identifying information to the DTE, but are not + * settable by the DTE //seems useless -TBD + * +******************************************************************************/ +typedef struct AtValueAttr_Tag +{ + AtValueType type; + AtPresentType presentType; + + /* + * Range, -TBD + */ + /* + * ACCESS ATTR: RO/RW - useless? + */ +}AtValueAttr; + +/* + * MARCO to per-define the AT parameter value attributes +*/ +#define AT_PARAM_ATTR_DEF(valuetype, presentType) {valuetype, presentType} + + +typedef CmsRetId (*AtCallbackFunctionP)(const AtCmdInputContext *pAtInputCtx); + + +typedef struct AtCmdPreDefInfo_Tag +{ + const CHAR *pName; //AT name, MAX length: AT_CMD_MAX_NAME_LEN = 32 + + UINT16 timeOutS; //time out value in seconds + UINT8 cmdType; //AtCmdSyntaxType, basic/extended action command/extended parameter command + UINT8 paramMaxNum; //max parameters number + + const AtValueAttr *pParamList; + + const AtCallbackFunctionP atProcFunc; +}AtCmdPreDefInfo; //16 bytes + +typedef const AtCmdPreDefInfo AtCmdPreDefInfoC; + + +/****************************************************************************** + ****************************************************************************** + * AT CHANNEL ENTITY + ****************************************************************************** +******************************************************************************/ + +/* + * AT channel configuration +*/ +typedef struct AtChanConfig_Tag +{ + CHAR S[AT_S_PARM_NUM]; //4 bytes + + UINT8 echoFlag; /*set by ATE0/ATE1*/ + UINT8 respFormat; /*set by ATV0/ATV1*/ + UINT8 suppressValue; /*set by ATQ0/ATQ1*/ + UINT8 rsvd; +}AtChanConfig; //8 bytes + +/* + * Input AT string info +*/ +typedef struct AtCmdInputNode_Tag +{ + struct AtCmdInputNode_Tag *pNextNode; + + /* + * example: + * 1st node: + * "AT+CEREG=5\r\nAT+\0" + * 2dn node: + * "CEREG?\r\n\0" + * + * After decoded first AT: AT+CEREG=5, then + * "AT+CEREG=5\r\nAT+\0" + * ^ ^ + * pStart pNextDec + */ + + CHAR *pStart; /*start of input string, !!!! MEMORY Allocated in heap by: OsaAllcateMemory() !!!!*/ + CHAR *pEnd; /*end of input string*/ + CHAR *pNextDec; /*Next decode header, AT decode line by line*/ +}AtCmdInputNode; //16 bytes + +/* + * AT command send via SDK API +*/ +typedef struct AtApiInputNode_Tag +{ + struct AtApiInputNode_Tag *pNextNode; + + /* + * Must be a whole/valid AT CMD, end with: \r\n + * "AT+CEREG?\r\n" + * ^ + * |pEnd + */ + CHAR *pStart; /*start of input string, !!!! MEMORY Allocated in heap by: OsaAllcateMemory() !!!!*/ + CHAR *pEnd; /*end of input string*/ + + AtRespFunctionP respFunc; + void *pArg; + UINT32 timeOutMs; + osSemaphoreId_t sem; //the caller API, maybe wait for this "semaphore" +}AtApiInputNode; //28 bytes + + +typedef struct AtInputInfo_Tag +{ + /* + * If "bApiMode" == TRUE, pHdr & pTailer point to "AtApiInputNode"; + * Else, (AT from UART), pHdr & pTailer point to "AtCmdInputNode"; + */ + union + { + struct + { + AtCmdInputNode *pHdr; + AtCmdInputNode *pTailer; + }cmdInput; + + struct + { + AtApiInputNode *pHdr; + AtApiInputNode *pTailer; + }apiInput; + }input; + + UINT8 pendingNodeNum; + INT8 rsvd; + UINT16 pendingLen; +}AtInputInfo; //12 bytes + +/* + * AT command line info +*/ +typedef struct AtCmdLineInfo_Tag +{ + /* + * ATC decoder decode/parse the AT command line by line, and maybe several AT CMDs in one line, + * example: AT+CFUN=1;+COPS?\r\0 + * Note: + * 1> "pLine" point to the head of the line; + * 2> "pNextHdr" point to the next CMD header; + */ + CHAR *pLine; /* !!! MEMORY Allocated in heap by: OsaAllcateMemory() !!!! */ + CHAR *pEnd; /* ending: */ + CHAR *pNextHdr; //point to start char of next AT CMD + + /* + * Note: + * 1> if "pNextHdr" == PNULL, just means all AT are processed, and "startLine" == FALSE & "startAt" == FALSE; + * 2> if "startLine" == TRUE, means prefix characeters: "AT" is needed; + * 3> if "startLine" == TRUE, then: "startAt" == TRUE and "pNextHdr" != PNULL; + * 4> if "startLine" == FALSE, and "startAt" == TRUE, then "pNextHdr" != PNULL, just means next AT CMD in one/same line + * example: AT+CFUN=1;+CEREG? + * ^ + * |pNextHdr, here "startLine" = FALSE, "startAt" = TRUE + * 5> if several AT line in current line, example: + * AT+CFUN=1\r\nAT+CEREG?\r\n + * ^ ^ + * |pLine |pNextHdr, here "startLine" = TRUE, "startAt" = TRUE + */ + BOOL startLine; /* if "pNextHdr" point to start of one line, if so, prefix: "AT" needed */ + BOOL startAt; /* if "pNextHdr" point to start of one AT command */ + UINT16 rsvd0; + + /* + * For AT API mode, current AT command guard time maybe set via API, if so store here + * If this value is zero, find the time value in AT command table. + */ + UINT32 timeOutMs; +}AtCmdLineInfo; //20 bytes + +/* + * AT channel miscellaneous info/control +*/ +typedef struct AtChanMiscellaneous_Tag +{ + UINT32 endSetbaud : 1; /* Whether need to set serial baudrate, after AT proc done, if return OK */ + UINT32 endReset : 1; /* whether need to reset UE, after AT proc done */ + UINT32 endPowerOff : 1; /* whether need to power off UE, after AT proc done */ + UINT32 rsvd : 20; + UINT32 baudSaveFlag: 1; /* when when endSetbaud == TRUE */ + UINT32 poweroffMode : 8; /* when endPowerOff == TRUE, pass to power off action */ + + UINT32 baudrate; /* when endSetbaud == TRUE */ + UINT32 baudFrameFormat; /* when endSetbaud == TRUE */ + UINT32 resetDelayMs; /* when endRest == TRUE */ +}AtChanMiscellaneous; + + + +typedef struct AtChanUrcInfo_Tag +{ + UINT8 riState; /* AtUrcRiState, URC RI state */ + UINT8 urcNum; /* How many URC in pending list: pUrcHead/pUrcTail */ + + /* + * As RI (Ring Indication) for SMS is different, here we record to indicate which URC is SMS + * Example: + * a) Bit0: pUrcHead, 0 - not SMS, 1 - SMS URC. + */ + UINT16 smsUrcBitmap; + + /* + * URC pending list, max number: 16 + */ + DlPduBlock *pUrcHead; + DlPduBlock *pUrcTail; + + osTimerId_t urcDelayTimer; /* URC delay timer, URC maybe delayed after RI indication done */ +}AtChanUrcInfo; //16 bytes + +/* + * AT_DATA_STATE_DATA_INPUT, pArgv +*/ +typedef struct AtDataStateDataInput_Tag +{ + UINT16 dataLen; + UINT16 rsvd0; + + UINT8 *pData; //data allocated in heap, and freed after the API: AtDataAndOnlineCmdStateFuncP() called +}AtDataStateDataInput; + +/* + * AT_ONLINE_CMD_ATO_EVT, pArgv +*/ +typedef struct AtOnlineCmdATOHInput_Tag +{ + UINT16 atHandle; + UINT16 atVal; /* ATO input value */ +}AtOnlineCmdATOInput; + + +typedef struct AtChanEntity_tag +{ + UINT8 chanId; //channel ID + BOOL bInited; //whether this channel inited + UINT8 chanState; //AtcState + BOOL bApiMode; //whether this AT channel is used for SDK API mode + + UINT32 nextTid : 5; //next asyn timer ID, start from 0, range: [0 - 31] + UINT32 curTid : 5; //current TID, in fact: nextTid = curTid + 1, TID of "asynTimer" + UINT32 bWaitDataModeHSCnf : 1; // whether the CCIO task confirms that data mode handshake succ. + UINT32 rsvd1 : 21; + + CHAR chanName[AT_CHAN_NAME_SIZE]; + + AtChanConfig cfg; //8 bytes + AtInputInfo atInputInfo; //12 bytes + AtCmdLineInfo atLineInfo; //20 bytes + + AtChanUrcInfo urcInfo; //16 bytes + + struct + { + AtRespFunctionP respFunc; + void *pArg; + osSemaphoreId_t apiSem; //the caller API, maybe wait for this "semaphore", only used for API mode + + /* + * if response separate several string, need to buffer here, and when final result arrived, sent it totally + * Used for API mode. !!! memory used in heap !!! + */ + CHAR *pBufResp; + UINT16 respBufLen; + UINT16 respBufOffset; + + AtUrcFunctionP urcFunc; + + /* + * AT resp and URC interface, the resp/urc string is carried in "DlPduBlock", and "DlPduBlock" should be freed in caller + */ + AtRespPduFunctionP respPduFunc; + AtUrcPduFunctionP urcPduFunc; + + AtDataAndOnlineCmdStateFuncP dataAndOnlineCmdFunc; /* when AT state enters: ATC_ONLINE_COMMAND_STATE/DATA_STATE, how to proc the input data/event */ + }callBack; //36 bytes + + + UINT16 preDefCmdNum; + UINT16 preDefCustCmdNum; + AtCmdPreDefInfoC *pPreDefCmdList; + AtCmdPreDefInfoC *pPreDefCustCmdList; + + UINT16 preDefRefCmdNum; + UINT16 rsvd2; + AtCmdPreDefInfoC *pPreDefRefCmdList; + + /* + * AT channel is an asynchronous interface, AT command should be processed in serial, + * so one guard timer is enough; + */ + osTimerId_t asynTimer; + + /* + * AT channel miscellaneous info/control + */ + AtChanMiscellaneous *pMiscell; +}AtChanEntity; // 136 bytes + +typedef struct AtChanEntity_tag *AtChanEntityP; + + +/****************************************************************************** + ***************************************************************************** + * EXTERNAL FUNCTION + ***************************************************************************** +******************************************************************************/ + +/* +*/ +AtChanEntityP atcGetEntityById(UINT32 chanId); + +/* + * whether previous AT line all decoded +*/ +BOOL atcBePreAtLineDone(AtChanEntity *pAtChanEty); + +/* + * any pending AT need to decode +*/ +BOOL atcAnyPendingAt(AtChanEntity *pAtChanEty); + +/* + * send: SIG_AT_CMD_CONTINUE_REQ signal +*/ +void atcSendAtCmdContinueReqSig(AtChanEntityP pAtChanEty); + +/* + * abort current AT line, ubsequent commands in the same line all need aborted +*/ +void atcAbortAtCmdLine(AtChanEntity *pAtChanEty); + +/* + * decode init +*/ +void atcDecInit(void); + +/* + * register the AT channel +*/ +CmsRetId atcRegisterAtChannelCallback(UINT16 inputSize, void *pInput, UINT16 outputSize, void *pOutput); + +/* + * de-register the AT channel by chanID +*/ +CmsRetId atcDeRegisterAtChannelCallback(UINT16 inputSize, void *pInput, UINT16 outputSize, void *pOutput); + +/* +*/ +void atcAsynTimerExpiry(UINT16 timeId); + +/* +*/ +void atcStopAsynTimer(AtChanEntityP pAtChanEty, UINT8 tid); + +/* + * restart AT asynchronoous response guard timer +*/ +void atcRestartGuardTimer(UINT8 chanId, UINT8 tid, UINT32 timeValueMs); + +/* +*/ +void atcProcAtCmdStrReqSig(AtCmdStrReq *pAtReq); + +/* +*/ +void atcProcAtCmdContinueReqSig(AtCmdContinueReq *pContReq); + +void atcProcAtCmdDataModeHSCnfSig(AtCmdDataModeHSCnf *pAtCmdDataCnf); + +/* +*/ +CmsRetId atcSetConfigValue(UINT8 chanId, AtcChanCfgItem item, UINT32 value); + +/* +*/ +CmsRetId atcChangeChannelState(UINT8 chanId, AtcState newState); + +/* +*/ +void atcRilAtCmdApiCallback(void *pArg); + +/* +*/ +CmsRetId atcRilRegisterUrcSynCallback(UINT16 inputSize, void *pInput, UINT16 outputSize, void *pOutput); + +/* +*/ +CmsRetId atcRilDeRegisterUrcSynCallback(UINT16 inputSize, void *pInput, UINT16 outputSize, void *pOutput); + + +UINT8 atcQueryChannelState(UINT8 chanId); + +/* +*/ +CmsRetId atcEndResetSystem(UINT8 chanId, UINT32 delayMs); + +/* +*/ +CmsRetId atcEndPowerOff(UINT8 chanId, UINT8 poweroffMode); + +/* +*/ +CmsRetId atcEndSetBaudrate(UINT8 chanId, UINT32 baudrate, UINT32 frameFormat, BOOL saveFlag); + +/* +*/ +CmsRetId atcDiscardAllPendingAt(UINT8 chanId); + + +/** + \brief AT channel state enter online data state, data recv from AT channel pass to dataStateFunc directly + \Note: API only can be called in CMS task +*/ +CmsRetId atcEnterOnlineDataState(UINT8 chanId, AtcState dataState, AtDataAndOnlineCmdStateFuncP dataStateFunc); + +/** + \brief AT channel state enter: ATC_ONLINE_COMMAND_STATE, data recv from AT channel act as AT command, and could + \ backup to online data state, when recv ATH + \Note: API only can be called in CMS task +*/ +CmsRetId atcEnterOnlineCommandState(UINT8 chanId, AtDataAndOnlineCmdStateFuncP onlineCmdStateFunc); + +/** + \brief AT channel state enter: ATC_COMMAND_STATE + \Note: API only can be called in CMS task +*/ +CmsRetId atcEnterCommandState(UINT8 chanId); + +/** + \brief DTR event: on-to-off transition +*/ +void atcDtrEventCallback(UINT16 paramSize, void *pParam); + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_adc_task.h b/PLAT/middleware/developed/at/atentity/inc/at_adc_task.h new file mode 100644 index 0000000..79bcd49 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_adc_task.h @@ -0,0 +1,41 @@ +#ifndef _AT_ADC_TASK_ +#define _AT_ADC_TASK_ +#include "FreeRTOS.h" +#include "queue.h" + +#define AT_ADC_TASK_STACK_SIZE (512) +#define AT_ADC_MSG_TIMEOUT (1000) +#define AT_ADC_GET_RESULT_TIMOUT (2000) +#define AT_ADC_MSG_MAX_NUM (2) + +#define AT_ADC_REQ_BITMAP_TEMP (0x1) +#define AT_ADC_REQ_BITMAP_VBAT (0x2) + +typedef enum applAdcPrimId_Enum +{ + APPL_ADC_PRIM_ID_BASE = 0, + + APPL_ADC_REQ, + APPL_ADC_CNF, + + APPL_ADC_PRIM_ID_END = 0xFF +}applAdcPrimId; + + +typedef struct +{ + uint32_t reqhandle; + uint32_t request; +}adcReqMsg; + +typedef struct +{ + uint32_t ack; + uint32_t data[2]; +}adcCnfMsg; + + +int32_t adcSendMsg(uint32_t atHandle, QueueHandle_t msgHandle, uint32_t req); +int32_t atAdcTaskInit(void); + +#endif diff --git a/PLAT/middleware/developed/at/atentity/inc/at_api.h b/PLAT/middleware/developed/at/atentity/inc/at_api.h new file mode 100644 index 0000000..17205a5 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_api.h @@ -0,0 +1,254 @@ +/****************************************************************************** + * (C) Copyright 2018 AirM2M International Ltd. + * All Rights Reserved +******************************************************************************* + * Filename: at_api.h + * + * Description: AT CMD entity/task (in CMS task) api + * + * History: + * + * Notes: All other tasks if need to use AT CMD functions, should ONLY include this header file + * +******************************************************************************/ +#ifndef __AT_API_H__ +#define __AT_API_H__ + +#include "cms_api.h" +#include "at_def.h" + +/****************************************************************************** + ***************************************************************************** + * EXTERNAL COMMON MARCO + ***************************************************************************** +******************************************************************************/ +#define AT_CHAN_NAME_SIZE 8 +#define AT_UART_PRINT_MAX 256 + + +#define UARTAT_CHAN_NAME "UARTAT" +#define UARTAT_CHAN_NAME_LEN 6 + +#define USBAT_CHAN_NAME "USBAT" +#define USBAT_CHAN_NAME_LEN 5 + +#define USBPPP_CHAN_NAME "USBPP" +#define USBPPP_CHAN_NAME_LEN 5 + +/* + * DEFAULT AT CHANNEL NAME, if registered, assign the fixed chanID: AT_CHAN_DEFAULT + * USB AT is set to default channel +*/ +#define AT_DEFAULT_CHAN_NAME USBAT_CHAN_NAME +#define AT_DEFAULT_CHAN_NAME_LEN USBAT_CHAN_NAME_LEN + + +/* + * AT CMD MAC string size +*/ +#define AT_CMD_STR_MAX_LEN 3072 + +/* + * Return the succ sent length. + * 1> if all sent to CCIO Tx task, return: strLen + * 2> if failed, return < 0 +*/ +typedef INT32 (*AtRespFunctionP)(UINT8 chanId, const CHAR *pStr, UINT32 strLen, void *pArg); +typedef INT32 (*AtUrcFunctionP)(UINT8 chanId, const CHAR *pStr, UINT32 strLen); + +/* + * AT resp and URC interface, the resp/urc string is carried in "DlPduBlock", and "DlPduBlock" should be freed in caller. + * Return the succ sent length. + * 1> if all sent to CCIO Tx task, return: DlPduBlock->length + * 2> if failed, return < 0 +*/ +typedef INT32 (*AtRespPduFunctionP)(UINT8 chanId, DlPduBlock *pPdu, void *pArg); +typedef INT32 (*AtUrcPduFunctionP)(UINT8 chanId, DlPduBlock *pPdu); + + +/****************************************************************************** + ***************************************************************************** + * EXTERNAL COMMON STRUCT + ***************************************************************************** +******************************************************************************/ + +/* + * SigId: SIG_AT_CMD_STR_REQ +*/ +typedef struct AtCmdStrReq_Tag +{ + UINT8 atChanId; //AT channel ID + UINT8 rsvd0; + + #if 0 //if AT STRING need to pass a copy in the signal, not suggest + UINT16 atStrLen; + UINT8 atStr[]; + #else + UINT16 atStrLen; + CHAR *pAtStr; //memory allocated in heap by OsaAllocateMemory() + #endif +}AtCmdStrReq; + + +/* + * SigId: SIG_AT_CMD_DATA_MODE_HS_CNF */ +typedef struct AtCmdDataModeHSCnf_Tag +{ + UINT8 atChanId; //AT channel ID + UINT8 rsvd[3]; +}AtCmdDataModeHSCnf; + + +/* +*/ +typedef struct AtChanRegInfo_tag +{ + CHAR chanName[AT_CHAN_NAME_SIZE]; + + AtRespFunctionP atRespFunc; + void *pRespArg; //passed in atRespFunc(chanId, str, pRespArg), or atRespPduFunc(chanId, pdu, pRespArg); + + AtUrcFunctionP atUrcFunc; + + /* + * AT RESP/URC PDU mode, the resp/urc string is carried in "DlPduBlock", and "DlPduBlock" should be freed in caller + * 1> "atRespFunc" & "atUrcFunc" is must, and "atRespPduFunc"/"atUrcPduFunc" is optional + * 2> "atRespPduFunc"/"atUrcPduFunc" is more efficient, expecially for longer RESP/URC string + * 3> "DlPduBlock" should be freed in caller via API: OsaFreeDlPduBlockList() + */ + AtRespPduFunctionP atRespPduFunc; + AtUrcPduFunctionP atUrcPduFunc; +}AtChanRegInfo; //28 bytes + + +/* + * SIGID: SIG_AT_CMD_CONTINUE_REQ +*/ +typedef struct AtCmdContinueReq_tag +{ + UINT8 atChanId; //AT channel ID + UINT8 rsvd0; + UINT16 rsvd1; +}AtCmdContinueReq; + + +/* +*/ +typedef struct AtRilAtCmdReqData_Tag +{ + CHAR *pCmdLine; /* memory alloacted in heap by: OsaAllocateMemory() */ + + UINT16 cmdLen; + UINT16 rsvd; + + AtRespFunctionP respCallback; + void *respData; +}AtRilAtCmdReqData; //16 bytes + +/****************************************************************************** + ***************************************************************************** + * EXTERNAL API + ***************************************************************************** +******************************************************************************/ + +/* + * register a AT channel; + * 1> if succ, return the "channId" (>=0); + * 2> else, return "CmsRetId" (< 0) +*/ +INT32 atRegisterAtChannel(AtChanRegInfo *pAtRegInfo); + +/* + * deregister AT channel by AT channel ID +*/ +void atDeRegisterAtChannel(UINT8 atChanId); + +/* + * send the AT command to AT CMD task: CMS_TASK_ID +*/ +void atSendAtcmdStrSig(UINT8 atChanId, const UINT8 *pCmdStr, UINT32 len); + +/* + * send the DATA MODE Handshake cnf to AT CMD task: CMS_TASK_ID +*/ +void atSendAtcmdDataModeHSCnfSig(UINT8 atChanId); + +/* + * at UART print callback +*/ +void atUartPrintCallback(UINT16 paramSize, void *pParam); + +/* + * print LOG to AT UART port +*/ +#define atUartPrint(fmt, ...) \ +do { \ + CHAR *PSTRUARTPRINT = (CHAR *)OsaAllocMemory(AT_UART_PRINT_MAX); \ + if (PSTRUARTPRINT == PNULL) \ + { \ + OsaDebugBegin(FALSE, AT_UART_PRINT_MAX, 0, 0); \ + OsaDebugEnd(); \ + } \ + else \ + { \ + snprintf(PSTRUARTPRINT, AT_UART_PRINT_MAX, fmt, ##__VA_ARGS__); \ + \ + cmsNonBlockApiCall(atUartPrintCallback, sizeof(void *), &PSTRUARTPRINT); \ + } \ +}while(FALSE) + + +/* + * AT RIL API +*/ +CmsRetId atRilAtCmdReq(const CHAR *pAtCmdLine, UINT32 cmdLen, AtRespFunctionP respCallback, void *respData, UINT32 timeOutMs); + +/* + * register AT RIL URC callback +*/ +CmsRetId atRilRegisterUrcCallback(AtUrcFunctionP urcCallback); + +/* + * unregister AT RIL URC callback +*/ +CmsRetId atRilDeRegisterUrcCallback(void); + +/* + * get dtr (Data Terminal Ready) config: AT&D value + * Comment: called by CCIO +*/ +UINT8 atGetDtrCfg(UINT8 atChanId); + +/* + * get dcd (Data Carrier Detect) config: AT&C value + * Comment: called by CCIO +*/ +UINT8 atGetDcdCfg(UINT8 atChanId); + +/* + * get DCD (Data Carrier Detect) state: TRUE - DCD on (low level), FALSE - DCD off (High level) + * Comment: called by CCIO +*/ +BOOL atGetDcdState(UINT8 atChanId); + +/* + * whether there is an RI type is enablee : TRUE - At least one of the RI Type is not "off", FALSE - All RI Type is "off". + * Comment: called by CCIO +*/ +BOOL atIsRITypeEnable(UINT8 atChanId); + +/* + * Indicate the RING IND operation is done + * Comment: called by CCIO +*/ +void atRingIndDone(UINT8 atChanId); + +/* + * notify AT the DTR (Data Terminal Ready) event: on-to-off transition + * Comment: called by CCIO +*/ +void atDtrEventInd(UINT8 atChanId); + + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_ctwing_task.h b/PLAT/middleware/developed/at/atentity/inc/at_ctwing_task.h new file mode 100644 index 0000000..bdbdcdc --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_ctwing_task.h @@ -0,0 +1,92 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: at_http_task.h +* +* Description: Process http(s) client related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _AT_CTWING_TASK_H_ +#define _AT_CTWING_TASK_H_ + +#include "at_util.h" +#include "ctw_tcp.h" + +/* + * APPL SGID: APPL_CTW, related PRIM ID +*/ +enum applCtwPrimId_Enum +{ + APPL_CTW_PRIM_ID_BASE = 0, + + APPL_CTW_HTTP_REG_CNF, + APPL_CTW_HTTP_SEND_CNF, + APPL_CTW_TCP_REG_CNF, + APPL_CTW_TCP_SEND_CNF, + APPL_CTW_TCP_DEREG_CNF, + APPL_CTW_TCP_DL_IND, + APPL_CTW_MQTT_REG_CNF, + APPL_CTW_MQTT_SEND_CNF, + APPL_CTW_MQTT_DL_IND, + APPL_CTW_MQTT_FOTA_IND, + APPL_CTW_PRIM_ID_END = 0xFF +}; + +enum CTW_CMD_TYPE +{ + CTW_HTTP_REG_COMMAND, + CTW_HTTP_SEND_COMMAND, + CTW_TCP_REG_COMMAND, + CTW_TCP_SEND_COMMAND, + CTW_MQTT_REG_COMMAND, + CTW_MQTT_SEND_COMMAND, + CTW_MQTT_DEREG_COMMAND, + +}; + +typedef struct +{ + uint16_t athandle; + uint8_t cmd_type; + uint8_t Qos; + char* topic; + char* data; + uint16_t datalen; + uint16_t ackMode; + uint16_t msgId; + uint32_t port; + uint32_t fotaFlag; +} ctwCmdMsg_t; + +typedef struct +{ + uint8_t ret; +} ctwCnfCmdMsg_t; + +typedef struct +{ + void *str; +} ctwIndMsg_t; + +CmsRetId ctwHttpRegReq(uint16_t athandle); +CmsRetId ctwHttpSendReq(uint16_t athandle, char* topic, char* data); +CmsRetId ctwTcpRegReq(uint16_t athandle); +CmsRetId ctwTcpSendReq(uint16_t athandle, char* data, uint16_t len); +uint8_t ctwTcpRegStatus(void); +void ctwTcpSetRegStatus(uint8_t status); +bool ctwTcpGetRecvTaskOut(void); +CmsRetId ctwMqttRegReq(uint16_t athandle); +CmsRetId ctwMqttSendReq(uint16_t athandle, uint8_t Qos, char* topic, char* data, uint16_t len); +CmsRetId ctwMqttDeregReq(uint16_t athandle); +CmsRetId ctwMqttFotaReq(uint16_t athandle, char* uri, uint32_t port); + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_def.h b/PLAT/middleware/developed/at/atentity/inc/at_def.h new file mode 100644 index 0000000..f326366 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_def.h @@ -0,0 +1,160 @@ +/****************************************************************************** + * (C) Copyright 2018 AirM2M International Ltd. + * All Rights Reserved +******************************************************************************* + * Filename: at_def.h + * + * Description: AT common defination + * + * History: + * + * Notes: + * +******************************************************************************/ +#ifndef __AT_DEF_H__ +#define __AT_DEF_H__ + +#include "cms_def.h" + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ + +/****************************************************************************** + * SRC HANDLER + * 15 12 11 8 7 5 4 0 + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * | R | channel ID | SUB AT ID | TID | + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * Note: + * 1> Channel ID: + * Channel ID 0, is reserved for internal. + * Channel ID 1, used for AT CMD from UART (default). + * 2> SUB AT ID + * If several AT CMD correlated with same CMI REQ ID, this "AT ID" is used to distinguish + * which AT CMD when CMI CNF comes; so MAX 8 AT CMD could use one same CMI REQ ID + * 3> TID: AT Asynchronous Timer index + * Used to index AT CMD guard timer +******************************************************************************/ +#define AT_SET_SRC_HANDLER(TID, atId, chanId) CMS_SET_SRC_HANDLER(TID, atId, chanId) +#define AT_GET_HANDLER_TID(srcHandler) CMS_GET_HANDLER_TID(srcHandler) +#define AT_GET_HANDLER_SUB_ATID(srcHandler) CMS_GET_HANDLER_SUB_ATID(srcHandler) +#define AT_GET_HANDLER_CHAN_ID(srcHandler) CMS_GET_HANDLER_CHAN_ID(srcHandler) +#define AT_GET_UINT16_HANDLER(srcHandler) CMS_GET_UINT16_HANDLER(srcHandler) +#define AT_MAX_ASYN_GUARD_TIMER_TID 31 + + +/* + * 1> CMS task OSA timer ID defination: + * + * 16 bits timerID + * 15 12 0 + * +-------+---------------------+ + * | modId | timerId in modId | + * +-------+---------------------+ + * MSB 4 bits: use to distinguish which sub-module in CMS task, so MAX 16 sub-modes + * + * 2> AT timer sub-module ID: CMS_TIMER_AT_SUB_MOD_ID + * + * 3> AT sub timer ID defination: + * 15 12 8 7 4 0 + * +-------+------+-----+-------+ + * | 0 | CID | R(0)| TID | + * +-------+------+-----+-------+ + * CID: AT channel ID, 4 bits + * R: reserved, 3 bits + * TID: AT Asynchronous Timer index, 5 bits + * + * 4> AT URC delay timer: + * 15 12 8 7 5 4 0 + * +-------+------+-----+-------+ + * | 0 | CID | 001 | 00000 | + * +-------+------+-----+-------+ +*/ +#define AT_SET_ASYN_TIMER_ID(chanId, tid) (UINT16)((((CMS_TIMER_AT_SUB_MOD_ID)<<12)&0xF000) | (((chanId)<<8)&0x0F00) | ((tid)&0x1F)) +#define AT_GET_ASYN_TIMER_CHAN_ID(timerId) (((timerId)>>8)&0x0F) +#define AT_GET_ASYN_TIMER_TID(timerId) ((timerId)&0x1F) + +#define AT_SET_URC_DELAY_TIMER_ID(chanId) (UINT16)((((CMS_TIMER_AT_SUB_MOD_ID)<<12)&0xF000) | (((chanId)<<8)&0x0F00) | 0x20) +#define AT_IS_URC_DELAY_TIMER(timerId) (((timerId)&0xF0FF) == 0x0020) +#define AT_GET_URC_DELAY_TIMER_CHAN_ID(timerId) (((timerId)>>8)&0x0F) + + + +/****************************************************************************** + * CMI REQ/CNF/IND ID: + * 15 11 0 + * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ + * | SG ID | PRIM ID | + * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ + * + * CMI: CIOT Modem Interface +******************************************************************************/ +#define AT_GET_CMI_SG_ID(reqId) CMS_GET_CMI_SG_ID(reqId) +#define AT_GET_CMI_PRIM_ID(reqId) CMS_GET_CMI_PRIM_ID(reqId) +#define AT_SET_CMI_REQ_CNF_ID(sgId, primId) CMS_SET_CMI_REQ_CNF_ID(sgId, primId) + + +/* +*/ +#define ATEC_IND_RESP_1024_STR_LEN 1024 //must using heap for this size +#define ATEC_IND_RESP_512_STR_LEN 512 //must using heap for this size +#define ATEC_IND_RESP_256_STR_LEN 256 +#define ATEC_IND_RESP_128_STR_LEN 128 +#define ATEC_IND_RESP_64_STR_LEN 64 +#define ATEC_IND_RESP_48_STR_LEN 48 +#define ATEC_IND_RESP_32_STR_LEN 32 + +#define AT_DEC_NUM_STR_MAX_LEN 11 //0xFFFFFFFF="4294967295", len("4294967295") = 10 + 1 +#define AT_HEX_NUM_STR_MAX_LEN 9 //FFFFFFFF, 8 + 1 +#define AT_BIN_NUM_STR_MAX_LEN 33 //len("11111111")*4 + 1 + +/* + * CTRL-Z/ESC ASCI value +*/ +#define AT_ASCI_CTRL_Z 0x1A +#define AT_ASCI_ESC 0x1B + +/* + * AT CMD buffer size +*/ +#define AT_CMD_BUF_MAX_LEN (1024 * 3) + + +/* + * Number of array +*/ +#define AT_NUM_OF_ARRAY(array) (sizeof(array)/sizeof((array)[0])) + +/* + * typedef struct AtCmdPreDefInfo_Tag + * { + * const CHAR *pName; //AT name + * + * UINT16 timeOutS; //time out value in seconds + * UINT8 cmdType; //AtCmdSyntaxType, basic/extended action command/extended parameter command + * UINT8 paramMaxNum; //max parameters number + * + * const AtValueAttr *pParamList; + * + * const AtCallbackFunctionP atProcFunc; + * }AtCmdPreDefInfo; //16 bytes +*/ +#define AT_CMD_PRE_DEFINE(name, atProcFunc, paramAttrList, cmdType, timeOutS) \ + {name, (timeOutS), cmdType, (paramAttrList == PNULL ? 0 : (sizeof(paramAttrList)/sizeof(AtValueAttr))), paramAttrList, atProcFunc} + + + +#if 0 +/* number of seconds between 1900 and 1970 (MSB=1)*/ +#define TIME_SEC_1900_1970 (2208988800UL) +/* number of seconds between 1970 and Feb 7, 2036 (6:28:16 UTC) (MSB=0) */ +#define TIME_SEC_1970_2036 (2085978496UL) +#endif + + + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_entity.h b/PLAT/middleware/developed/at/atentity/inc/at_entity.h new file mode 100644 index 0000000..fa05d9d --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_entity.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * (C) Copyright 2018 AirM2M International Ltd. + * All Rights Reserved +******************************************************************************* + * Filename: at_entity.h + * + * Description: Entracne of AT CMD + * + * History: + * + * Notes: + * +******************************************************************************/ + +#ifndef __AT_ENTITY_H__ +#define __AT_ENTITY_H__ +#include "osasys.h" +#include "atc_decoder.h" + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ + + +/****************************************************************************** + ***************************************************************************** + * ENUM + ***************************************************************************** +******************************************************************************/ + +/* + * AT APP to process the "SIG_CMS_APPL_CNF" signal +*/ +typedef void (*AtProcApplCnfFunc)(CmsApplCnf *pApplCnf); + +typedef struct AtApplCnfFuncTable_Tag +{ + UINT32 appId; + AtProcApplCnfFunc applCnfFunc; +}AtApplCnfFuncTable; + +/* + * AT APP to process the "SIG_CMS_APPL_IND" signal +*/ +typedef void (*AtProcApplIndFunc)(CmsApplInd *pApplInd); + +typedef struct AtApplIndFuncTable_Tag +{ + UINT32 appId; + AtProcApplIndFunc applIndFunc; +}AtApplIndFuncTable; + + +/****************************************************************************** + ***************************************************************************** + * API + ***************************************************************************** +******************************************************************************/ + +/* + * process signal +*/ +void atProcSignal(const SignalBuf *pSig); + +/* + * AT module init +*/ +void atInit(void); + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_example_task.h b/PLAT/middleware/developed/at/atentity/inc/at_example_task.h new file mode 100644 index 0000000..363d8c9 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_example_task.h @@ -0,0 +1,102 @@ +#ifndef _EXAMPLE_TASK_ +#define _EXAMPLE_TASK_ +#include "FreeRTOS.h" +#include "queue.h" + +#define EG_AT_DEMO_TASK_STACK_SIZE 512 +#define EG_MSG_TIMEOUT 1000 +#define EG_MSG_MAX_NUMB 10 + +typedef enum AT_EC_RET_TAG +{ + EC_RET_SUCC = 0, + EC_RET_FAIL = 1, + EC_RET_END, +}AT_EC_RET_TYPE; + +typedef enum AT_EC_REQ_TYPE_TAG +{ + // customer cmd param type + AT_EC_REQ_TESTA = 1, + AT_EC_REQ_TESTB, + AT_EC_REQ_TESTC, + +}AT_EG_REQ_TYPE; + +typedef enum AT_EC_CNF_TYPE_TAG +{ + // customer cmd param type + AT_EC_CNF_TESTA = 1, + AT_EC_CNF_TESTB, + AT_EC_CNF_TESTC, + +}AT_EC_CNF_TYPE; + +typedef enum AT_EC_IND_TYPE_TAG +{ + // customer cmd param type + AT_EC_IND_TESTA = 1, + AT_EC_IND_TESTB, + AT_EC_IND_TESTC, + +}AT_EC_IND_TYPE; + +typedef enum applExamplePrimId_Enum +{ + APPL_EXAMPLE_PRIM_ID_BASE = 0, + + APPL_EXAMPLE_ECTESTB_REQ, + APPL_EXAMPLE_ECTESTB_CNF, + APPL_EXAMPLE_ECTESTB_IND, + + APPL_EXAMPLE_ECTESTC_REQ, + APPL_EXAMPLE_ECTESTC_CNF, + APPL_EXAMPLE_ECTESTC_IND, + + APPL_EXAMPLE_PRIM_ID_END = 0xFF +}applExamplePrimId; + + +typedef struct +{ + char data_type; + unsigned int data_value; + char * data_ptr; + int data_len; +}EC_SEND_DATA_STRUCT; + +typedef struct +{ + int cmd_type; + unsigned int reqhandle; + EC_SEND_DATA_STRUCT send_data; +}EC_SEND_Q_MSG; + +typedef struct +{ + int cmd_type; + unsigned int data; +}EC_CNF_MSG; + +typedef struct +{ + int cmd_type; + unsigned int data; +}EC_IND_MSG; + +int ecFuncTestA(int input); +int ecFuncTestB(int input); +int ecFuncTestC(int input); + + +int ecTestaApi(UINT32 atHandle, QueueHandle_t msgHandle, INT32 cmdType, UINT32 data, CHAR *dataPtr); +int ecTestbApi(UINT32 atHandle, QueueHandle_t msgHandle, INT32 cmdType, UINT32 data, CHAR *dataPtr); +int ecTestcApi(UINT32 atHandle, QueueHandle_t msgHandle, INT32 cmdType, UINT32 data, CHAR *dataPtr); +INT32 ecHandleEGErrCode(UINT32 atHandle, UINT16 errCode); +void ecExecuteRetAck(UINT16 atHandle, UINT16 ackType, AT_EC_RET_TYPE retCode, UINT8 sgId, UINT16 primId, UINT16 primSize, void *primBody); +void ecSendMsg(UINT32 atHandle, QueueHandle_t msgHandle, INT32 cmdType, UINT32 data, CHAR *dataPtr); +void ecFreeMsg(const EC_SEND_Q_MSG *ccMsg); + +int custAtDemoTaskInit(void); + +#endif diff --git a/PLAT/middleware/developed/at/atentity/inc/at_file_task.h b/PLAT/middleware/developed/at/atentity/inc/at_file_task.h new file mode 100644 index 0000000..7c61e15 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_file_task.h @@ -0,0 +1,151 @@ +#ifndef _AT_FILE_TASK_ +#define _AT_FILE_TASK_ +#include "FreeRTOS.h" +#include "queue.h" + +#define FILE_SEMPHR_MAX_NUMB 4 +#define FILE_TASK_STACK_SIZE 1600 +#define FILE_INFO_MAX_NUMB 16 +#define FILE_MSG_TIMEOUT 2000 +#define FILE_TASK_CREATE 1 +#define FILE_TASK_DELETE 2 +#define FILE_READ_MAX_COUNT 4 + +#define FILE_READ_DEFAULT_LEN 0xffff + +enum FILE_RET +{ + FILE_OK = 200, + FILE_ERR, + FILE_CTRL_Z_OK, + + FILE_MAX_ERR, +}; + +enum FILE_MODE +{ + FILE_MODE_0 = 0, + FILE_MODE_1, + FILE_MODE_2, +}; + +enum FILE_STATUS +{ + FILE_STATUS_RESERVE, + FILE_STATUS_OPEN, + FILE_STATUS_READ, + FILE_STATUS_WRITE, + FILE_STATUS_SEEK, + FILE_STATUS_POSITION, + FILE_STATUS_TUCAT, + FILE_STATUS_CLOSE, + FILE_STATUS_RENAME, + FILE_STATUS_DELETE, + FILE_STATUS_ERASE, + FILE_STATUS_DELETE_ALL, + + FILE_STATUS_MSLDS, /*memory space LDS*/ + FILE_STATUS_MSLST, /*memory space LST*/ + FILE_STATUS_MSDEL, /*memory space DEL*/ + FILE_STATUS_MSUPL, /*memory space UPL*/ + FILE_STATUS_MSDWL, /*memory space DWL*/ + FILE_STATUS_MOV, + +}; + +enum FILE_MSG_CMD +{ + FILE_MSG_RESERVE, + FILE_MSG_OPEN, + FILE_MSG_READ, + FILE_MSG_WRITE, + FILE_MSG_SEEK, + FILE_MSG_POSITION, + FILE_MSG_TUCAT, + FILE_MSG_CLOSE, + FILE_MSG_RENAME, + FILE_MSG_DELETE, + FILE_MSG_ERASE, + FILE_MSG_DELETE_ALL, + + FILE_MSG_MSLDS, /*memory space LDS*/ + FILE_MSG_MSLST, /*memory space LST*/ + FILE_MSG_MSDEL, /*memory space DEL*/ + FILE_MSG_MSUPL, /*memory space UPL*/ + FILE_MSG_MSDWL, /*memory space DWL*/ + FILE_MSG_MOV, + +}; + +typedef struct +{ + char *fileName; + char *fileSysHandle; + int32_t flags; + uint32_t fileHandler; + uint32_t fileMode; + uint32_t fileLen; + uint32_t fileStatus; +}fileInfo; + +typedef struct +{ + uint32_t reqhandle; + uint32_t cmdType; + int32_t flags; + char *fileName; + char *filePattern; + char *fileSysHandle; + char *fileBuff; + char *fileNameNew; + uint32_t fileHandler; + uint32_t mode; + uint32_t length; + uint32_t totalLength; + uint32_t timeout; + uint32_t offset; + uint32_t position; + uint32_t fileStatus; + +}fileInfoPara; + + +typedef struct +{ + uint32_t reqhandle; + uint32_t cmdType; + char *fileName; + char *filePattern; + char *fileNameNew; + fileInfo *fileInfoPtr; + uint32_t fileHandle; + uint32_t mode; + uint32_t length; + uint32_t totalLength; + uint32_t timeout; + uint32_t offset; + uint32_t position; + char *reqBuff; +}fileReqMsg; + +typedef struct +{ + uint32_t reqhandle; + char *fileName; + char *filePattern; + uint32_t fileHandle; + uint32_t result; + uint32_t ack; + char *retBuff; + INT32 retLen; + INT32 retTotalLen; + +}fileCnfMsg; + + +fileInfo *fileFindExistFileByName(fileInfoPara fileInfo); +fileInfo *fileFindExistFileByHandler(fileInfoPara fileInfo); +int fileClientInterface(fileInfoPara fileReq); +fileInfo *fileGetExistFile(uint32_t index); + +#endif diff --git a/PLAT/middleware/developed/at/atentity/inc/at_fwupd_task.h b/PLAT/middleware/developed/at/atentity/inc/at_fwupd_task.h new file mode 100644 index 0000000..ee36ff9 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_fwupd_task.h @@ -0,0 +1,113 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: at_fwupd_task.h +* +* Description:FW upgrade over serial port via AT command +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __AT_FWUPD_TASK_H__ +#define __AT_FWUPD_TASK_H__ + +#include "at_util.h" + +#define FWUPD_MQUE_MSG_MAXNUM 2 +#define FWUPD_MQUE_SEND_TIMEOUT 500 +#define FWUPD_TASK_STACK_SIZE 2048 + +#define FWUPD_RESP_BUF_MAXLEN 128 + +#define FWUPD_FW_VER_MAXLEN 32 +#define FWUPD_FW_NAME_MAXLEN 32 +#define FWUPD_FW_PSN_MINNUM 0 +#define FWUPD_FW_PSN_MAXNUM 65535 +#define FWUPD_DATA_BYTES_MAXNUM 256 +#define FWUPD_DATA_HEXSTR_MAXLEN FWUPD_HEXSTR_LEN(FWUPD_DATA_BYTES_MAXNUM) + +#define FWUPD_HEXBYTE_NUM(strlen) ((strlen) >> 1) +#define FWUPD_HEXSTR_LEN(nbytes) ((nbytes) << 1) +#define FWUPD_HEXCHAR_TO_INTEGER(hex) ((hex >= '0' && hex <= '9') ? (hex - '0') : \ + ((hex >= 'A' && hex <= 'F') ? (hex - 'A' + 10) : \ + ((hex >= 'a' && hex <= 'f') ? (hex - 'a' + 10) : 0))) + +#define FWUPD_REQMSG_INIT(msg) \ + do{\ + msg.atHandle = 0;\ + msg.cmdCode = FWUPD_CMD_CODE_MAXNUM;\ + msg.pkgSn = FWUPD_FW_PSN_MINNUM;\ + msg.strLen = 0;\ + msg.crc8 = 0;\ + memset(&msg.hexStr, '\0', (FWUPD_DATA_HEXSTR_MAXLEN + 1));\ + }while(0) + +#define FWUPD_CNFMSG_INIT(msg) \ + do{\ + msg.errCode = FWUPD_EC_UNDEF_ERROR;\ + msg.strLen = 0;\ + memset(&msg.respStr, '\0', FWUPD_RESP_BUF_MAXLEN);\ + }while(0) + +typedef enum +{ + FWUPD_CMD_CODE_BEGIN = 0, + FWUPD_CMD_CLEAR_FLASH = FWUPD_CMD_CODE_BEGIN, + FWUPD_CMD_DOWNLOAD_FW, + FWUPD_CMD_VERIFY_FW, + FWUPD_CMD_QUERY_FWNAME, + FWUPD_CMD_QUERY_FWVER, + FWUPD_CMD_UPGRADE_FW, + FWUPD_CMD_DOWNLOAD_OVER, + FWUPD_CMD_DFU_STATUS, + FWUPD_CMD_CODE_END = FWUPD_CMD_DFU_STATUS, + + FWUPD_CMD_CODE_MAXNUM +}FwupdCmdCode_e; + +typedef enum +{ + APPL_FWUPD_PRIM_ID_BASE = 0, + + APPL_FWUPD_REQ, + APPL_FWUPD_CNF, + + APPL_FWUPD_PRIM_ID_END = 0xFF +}ApplFwupdPrimId; + + +typedef struct +{ + uint32_t atHandle; + uint16_t cmdCode; + uint16_t pkgSn; + uint16_t strLen; + uint8_t hexStr[FWUPD_DATA_HEXSTR_MAXLEN + 1]; + uint8_t crc8; +}FwupdReqMsg_t; + +typedef struct +{ + uint8_t errCode; + uint8_t rsvd; + uint16_t strLen; + uint8_t respStr[FWUPD_RESP_BUF_MAXLEN]; +}FwupdCnfMsg_t; + + + +int32_t FWUPD_initTask(void); +int32_t FWUPD_deinitTask(void); +int32_t FWUPD_sendMsg(FwupdReqMsg_t *msg); + + +#endif + +/* END OF FILE */ + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_http_task.h b/PLAT/middleware/developed/at/atentity/inc/at_http_task.h new file mode 100644 index 0000000..5f15371 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_http_task.h @@ -0,0 +1,165 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: at_http_task.h +* +* Description: Process http(s) client related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _AT_HTTP_TASK_H_ +#define _AT_HTTP_TASK_H_ + +#include "at_util.h" +#include "httpclient.h" + +#define HTTP_RSP_HEAD_BUFFER_SIZE 800 +#define HTTP_RSP_CONTENT_BUFFER_SIZE 1501 +/* + * APPL SGID: APPL_HTTP, related PRIM ID +*/ +enum applHttpPrimId_Enum +{ + APPL_HTTP_PRIM_ID_BASE = 0, + + APPL_HTTP_SEND_CNF, + APPL_HTTP_READ_CNF, + APPL_HTTP_STOP_CNF, + APPL_HTTP_FOTADL_CNF, + APPL_HTTP_URC_IND, + APPL_HTTP_READ_IND, + + APPL_HTTP_PRIM_ID_END = 0xFF +}; + +typedef enum { + HTTPSTAT_CLOSE = 0, + HTTPSTAT_CONNECT, + HTTPSTAT_REQHANDL, +}HTTPAtStatus_e; + +enum HTTP_CMD_TYPE +{ + HTTP_SEND_COMMAND, + HTTP_STOP_COMMAND, + HTTP_CLOSE_TCP_COMMAND, +}; + +typedef enum AT_HTTP_ERROR +{ + HTTPAT_OK = 0, //success + HTTPAT_PARAM_ERROR = 1, //parameter error + HTTPAT_INPUT_TIMEOUT = 2, //input timeout + HTTPAT_NO_URL = 3, //not set url + HTTPAT_OPERATION_NOT_SUPPORT = 4, //operation not support + HTTPAT_NO_REQ = 5, //no request + HTTPAT_REQ_PROCESSING = 6, //request processing + HTTPAT_FILENAME_TOO_LONG = 7, //filename too long + HTTPAT_NO_SUCH_FILE = 8, //no file or read nothing + HTTPAT_MEMORY_NOT_ENOUGH = 9, //memory not enough + HTTPAT_CONFIG_SSL_ERROR = 10, //ssl config error + HTTPAT_URL_PARSE_ERROR = 11, //url parse error + HTTPAT_DNS_FAILED = 12, //dns resolution failed + HTTPAT_PRTCL_ERROR = 13, //decode http data failed + HTTPAT_SOCKET_ERROR = 14, //create socket failed + HTTPAT_BIND_FAILED = 15, //bind socket failed + HTTPAT_CONNECT_TIMEOUT = 16, //connect timeout + HTTPAT_CONNECT_ERROR = 17, //connect error + HTTPAT_CONNECT_CLOSE = 18, //connect close by remote host + HTTPAT_TLS_ERROR = 19, //meet tls error + HTTPAT_REQ_TIMEOUT = 20, //http request timeout + HTTPAT_INTERNAL = 21, //internal error + HTTPAT_URL_ERROR = 22, //url error + HTTPAT_NOT_SUPPORT_TLS = 23, //tls is not supported + HTTPAT_RECV_COMP = 100, //receive complete +}AtHttpError_e; + +typedef enum +{ + HTTPFOTA_BEGIN = 0, //FOTA begin http download + HTTPFOTA_DL_PROC = 1, //FOTA download progress + HTTPFOTA_ERR = 2, //FOTA http error + HTTPFOTA_DOWNLOADEND = 3, //FOTA http download end + HTTPFOTA_PACKAGE_MISMATCH = 4 //FOTA http package mismatch +}HTTPFotaUrc_e; + +typedef enum +{ + HTTP_EN_SLEEP, + HTTP_DIS_SLEEP +}HTTPSleep_e; + +typedef struct{ + uint8_t contextID; + uint8_t requestHead; + uint8_t responseHead; + uint8_t sslctxID; + uint8_t contentType; + uint8_t bRestore; + //uint8_t autoOutrsp; + //uint8_t closedInd; +}httpAtCfgParam_t; + +typedef struct { + HTTPAtStatus_e status; + bool hasRequest; + uint8_t method; + char* url; + HttpClientContext* clientContext; + HttpClientData* clientData; + uint32_t reqhandle; + bool isRange; + uint32_t startPos; + int32_t endPos; + bool isFota; + uint8_t dlUrcRag; + bool cache2flash; + bool postfile; + char* postfilename; + bool readfile; + char* respfilename; + void* fp; +} httpAtContext_t; + +typedef struct +{ + uint8_t cmd_type; +} httpCmdMsg_t; + +typedef struct +{ + uint8_t ret; +} httpCnfCmdMsg_t; + +typedef struct +{ + void *pHttpInd; +} httpIndMsg_t; + +void httpSleepVote(HTTPSleep_e sleep); + +bool httpClrCustNewContext(uint16_t datalen); +void httpClearAtContext(httpAtContext_t* atContext); + +bool httpCreateClientContext(httpAtContext_t* atContext); + +CmsRetId httpStopReq(void); +CmsRetId httpSendReq(void); +CmsRetId httpReadReq(void); + +void httpSaveUrltoNvm(void); +void httpSaveConfigtoNvm(void); +AtHttpError_e httpCheckRestore(void); + +void httpEngineInit(void); + + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_mqtt_task.h b/PLAT/middleware/developed/at/atentity/inc/at_mqtt_task.h new file mode 100644 index 0000000..8a2a34f --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_mqtt_task.h @@ -0,0 +1,376 @@ +/* + * atec_mqtt_task.h + * + * Created on: + * Author: + */ +#ifndef _MQTT_TASK_H +#define _MQTT_TASK_H + +#include "MQTTClient.h" +#ifdef FEATURE_MQTT_TLS_ENABLE +#include "mqtttls.h" +#endif + +#define MQTT_SEND_Q_LENGTH 7 + +#define MQTT_SEND_TIMEOUT 2000 +#define MQTT_RECV_TIMEOUT 5000 +#define MQTT_TASK_CREATE 1 +#define MQTT_TASK_DELETE 2 + +#define MQTT_SEMPHR_NOT_CREATE 1 +#define MQTT_SEMPHR_HAVE_CREATE 2 + +#define MQTT_SEMPHR_MAX_NUMB 6 + +#define MQTT_RECV_LOOP_TIMEOUT 2000 + +#define EC_TOPIC_LENGTH 128 +#define EC_BUFF_LENGTH 128 + +#define MQTT_CONTEXT_NUMB_MAX 1 +#define MQTT_ID_DEFAULT 0xff +#define MQTT_CLOUD_DEFAULT 0xff +#define MQTT_TCP_ID_DEFAULT 0xff + +#define MQTT_CMD_TIMEOUT_DEFAULT 10000 +#define MQTT_CMD_TIMEOUT_TX_DEFAULT 2 +#define MQTT_CMD_TIMEOUT_RX_DEFAULT 20 + +#define MQTT_KEEPALIVE_DEFAULT 120 + +#define MQTT_TX_BUF_DEFAULT (4+128+1024) /*header+topic+payload*/ +#define MQTT_RX_BUF_DEFAULT (4+128+1024) /*header+topic+payload*/ + +#define MQTT_PORT_DEFAULT 1883 + +#define MQTT_MSG_TIMEOUT 1000 + +#define MQTT_ERR_ABRT (-13) +#define MQTT_ERR_RST (-14) +#define MQTT_ERR_CLSD (-15) +#define MQTT_ERR_BADE (9) + +#define MQTT_TAG_LEN 8 +#define KEEPALIVE_RETRY_MAX 3 +#define MQTT_RECONN_MAX 3 + +#define ALI_DYNAMIC_REGISTER_IS_NOT_USED 0 +#define ALI_DYNAMIC_REGISTER_IS_USED 1 + +enum MQTT_PUB_TYPE +{ + MQTT_PUB_CTRLZ = 0, + MQTT_PUB_AT = 1, +}; + +enum MQTT_INT_RET +{ + MQTTSUCCESS = 0, + MQTTKEEPALIVE = 1 +}; + +enum MQTT_RET +{ + MQTT_OK = 200, + MQTT_ERR, + MQTT_NETWORK_ERR, + MQTT_CONTEXT_ERR, + MQTT_PARAM_ERR, + MQTT_SOCKET_ERR, + MQTT_SOCKET_TIME_ERR, + MQTT_MQTT_CONN_ERR, + MQTT_TASK_ERR, + MQTT_RECONNECT, + MQTT_CLIENT_ERR, + MQTT_ALI_ENCRYP_ERR, + MQTT_BUSY_ERR, + MQTT_CONTINUE, + + MQTT_MAX_ERR, +}; + +enum MQTT_CONTEXT +{ + MQTT_CONTEXT_NOT_USED, + MQTT_CONTEXT_USED, + MQTT_CONTEXT_IS_CREATING, + MQTT_CONTEXT_OPENED, + MQTT_CONTEXT_CONFIGED, + +}; + +enum MQTT_CONNECT +{ + MQTT_CONN_DEFAULT, + + MQTT_CONN_NOT_OPEN, + MQTT_CONN_IS_OPENING, + MQTT_CONN_OPENED, + MQTT_CONN_OPEN_FAIL, + + MQTT_CONN_IS_CONNECTING, + MQTT_CONN_CONNECTED, + MQTT_CONN_CONNECT_FAIL, + + MQTT_CONN_IS_CLOSING, + MQTT_CONN_CLOSED, + MQTT_CONN_CLOSED_FAIL, + + MQTT_CONN_IS_DISCONNECTING, + MQTT_CONN_DISCONNECTED, + MQTT_CONN_DISCONNECTED_FAIL, + + MQTT_CONN_RECONNECTING, + MQTT_CONN_RECONNECTING_FAIL, + +}; + +enum MQTT_MSG_CMD +{ + MSG_RESERVE, + MQTT_MSG_OPEN, + MQTT_MSG_CONNECT, + MQTT_MSG_CLOSE, + MQTT_MSG_DISCONNECT, + MQTT_MSG_CREATE_CLINET, + MQTT_MSG_KEEPALIVE, + MQTT_MSG_RECONNECT, + MQTT_MSG_DELETE_CLINET, + MQTT_MSG_PUBLISH, + MQTT_MSG_PUBLISH_REC, + MQTT_MSG_PUBLISH_REL, + MQTT_MSG_PUBLISH_ACK, + MQTT_MSG_PUBLISH_COMP, + MQTT_MSG_SUB, + MQTT_MSG_UNSUB, + MQTT_MSG_CONNECT_DOWN, + MQTT_MSG_ALI_DYN_CONNECT, + +}; + +enum MQTT_CMD +{ + ONENET_CMD, + ALI_CMD, +}; +enum MQTT_DATA_TYPE +{ + MQTT_DATA_JSON = 0, + MQTT_DATA_STR = 1, + MQTT_DATA_HEX = 2, + + ONENET_DATA_TYPE1 = 1, + ONENET_DATA_TYPE2 = 2, + ONENET_DATA_TYPE3 = 3, + ONENET_DATA_TYPE4 = 4, + ONENET_DATA_TYPE5 = 5, + ONENET_DATA_TYPE6 = 6, + ONENET_DATA_TYPE7 = 7, + ONENET_DATA_TYPE8 = 8, //customer define data type + ONENET_DATA_TYPE9 = 9, //customer define data type + + MQTT_DATA_DEFAULT = 0xFF, +}; + +enum MQTT_CLOUD_TYPE +{ + CLOUD_TYPE_ONENET = 1, + CLOUD_TYPE_ALI, + CLOUD_TYPE_ECLIPSE, /*not use client id, user name, passwd*/ + CLOUD_TYPE_NORMAL, /*need client id, user name, passwd*/ + CLOUD_TYPE_MAX +}; + +enum MQTT_CONFIG_TYPE +{ + MQTT_CONFIG_BASE = 0, + MQTT_CONFIG_ECHOMODE, + MQTT_CONFIG_DATAFORMAT, + MQTT_CONFIG_KEEPALIVE, + MQTT_CONFIG_SEESION, + MQTT_CONFIG_KEEPALIVE_CMD_TIMEOUT, + MQTT_CONFIG_KEEPALIVE_CONN_TIMEOUT, + MQTT_CONFIG_TIMEOUT, + MQTT_CONFIG_CMD_TIMEOUT, + MQTT_CONFIG_CONN_TIMEOUT, + MQTT_CONFIG_WILL, + MQTT_CONFIG_VERSION, + MQTT_CONFIG_ALIAUTH, + MQTT_CONFIG_OPEN, + MQTT_CONFIG_CLOUD, + MQTT_CONFIG_SSL, + + MQTT_CONFIG_MAX +}; + +enum MQTT_SSL_TYPE +{ + MQTT_SSL_NONE = 0, + MQTT_SSL_HAVE = 1, + MQTT_SSL_PSK = 2, + MQTT_SSL_ECC, + MQTT_SSL_CA, +}; + +typedef struct +{ + int decParam1; + int decParam2; + int decParam3; + char *strParam1; + char *strParam2; + char *strParam3; + char *strParam4; + char *strParam5; + char *strParam6; + char *strParam7; + char *strParam8; + char *strParam9; + char *strParam10; +}mqtt_cfg_data; + + +typedef struct +{ + int cmd_type; + unsigned int reqhandle; + void * context_ptr; + void * client_ptr; + int tcp_id; + int msg_id; + int pub_mode; + int server_ack_mode; + char *sub_topic; + char *unsub_topic; + char *topic; + int qos; + int rai; + MQTTMessage message; +}mqtt_send_msg; + +typedef struct +{ + int mqtt_id; + char *mqtt_topic; + int mqtt_topic_len; + char *mqtt_payload; + int mqtt_payload_len; + int tcp_id; + int msg_id; + int ret; + int conn_ret_code; + int sub_ret_value; + int pub_ret_value; +}mqtt_message; + +typedef struct +{ + char *product_name; + char *product_key; + char *product_secret; + char *device_name; + char *device_secret; + char *device_token; + char *auth_type; /*register, regnwl*/ + char *sign_method; /*hmac_sha1, hmac_sha256, hmac_md5*/ + char *auth_mode; /*tls-psk, tls-ca*/ + char *secure_mode; /*-2, 2*/ + char *instance_id; /* */ + char *client_id; /*for regnwl */ + int dynamic_register_used; +}ali_auth; + +typedef struct +{ + int is_used; + int is_connected; + int is_mqtts; + int cloud_type; + int tcp_id; + int mqtt_id; + UINT32 reqHandle; + char *mqtt_uri; + unsigned int port; + char *mqtt_send_buf; + int mqtt_send_buf_len; + char *mqtt_read_buf; + int mqtt_read_buf_len; + + int reconnect_count; + int (*reconnect) (void *c); + MQTTPacket_connectData mqtt_connect_data; + Network* mqtt_network; + MQTTClient *mqtt_client; + messageHandler mqtt_msg_handler; +#ifdef FEATURE_MQTT_TLS_ENABLE + mqttsClientContext* mqtts_client; +#endif + int echomode; + int send_data_format; + int recv_data_format; + int keepalive; + int session; + int timeout; + int version; + int pkt_timeout; + int retry_time; + int timeout_notice; + ali_auth aliAuth; + + char *sub_topic; + char *unsub_topic; + int qos; + int retained; + int payloadType; + int ssl_type; + char *ecc_key; + char *ca_key; + char *host_name; + +}mqtt_context; + +typedef struct +{ + unsigned char cleansession; + unsigned char willFlag; + MQTTPacket_willOptions will; +}mqtt_option; + +typedef struct +{ + int dec_param1; /**/ + int dec_param2; /**/ + int dec_param3; /**/ + int dec_param4; /**/ + char *str_param1; /**/ + char *str_param2; /**/ + char *str_param3; /**/ + char *str_param4; /**/ + +}MQTT_CNF_STRUCT; + +void check_tcpip_ready(void); +int mqttReconnect(void *v); +void MQTT_messageArrived(MessageData* data); +mqtt_context *mqttFindContext(int tcpId); + +int mqtt_client_config(int cnfType, int tcpId, mqtt_cfg_data *cfgData); +int mqtt_client_open(UINT32 reqHandle, int tcpId, char *mqttUri, int mqttPort); +int mqtt_client_close(UINT32 reqHandle, int tcpId); +int mqtt_client_connect(UINT32 reqHandle, int tcpId, char *clientId, char *userName, char *passWord); +int mqtt_client_disconnect(UINT32 reqHandle, int tcpId); +int mqtt_client_sub(UINT32 reqHandle, int tcpId, int msgId, char *mqttSubTopic, int qos); +int mqtt_client_unsub(UINT32 reqHandle, int tcpId, int msgId, char *mqttSubTopic); +int mqtt_client_pub(UINT32 reqHandle, int tcpId, int msgId, int qos, int retained, int pubMode, char *mqttPubTopic, int msgLen, char *message, int cloudType, int msgType, int rai); + +int mqtt_recv_task_Init(void); +int mqttCycle(mqtt_context* context, Timer* timer); +void mqttCloseSession(MQTTClient* c); + + +#endif + + + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_sock_entity.h b/PLAT/middleware/developed/at/atentity/inc/at_sock_entity.h new file mode 100644 index 0000000..aaa896b --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_sock_entity.h @@ -0,0 +1,1257 @@ +/****************************************************************************** + * (C) Copyright 2018 AirM2M International Ltd. + * All Rights Reserved +******************************************************************************* + * Filename: at_sock_task.h + * + * Description: AT SOCKET TASK, task created by SOCKET AT COMMAND + * + * History:create by xwang + * + * Notes: + * +******************************************************************************/ +#ifndef __AT_SOCK_TASK_H__ +#define __AT_SOCK_TASK_H__ + +#include "at_util.h" +#include "lwip/api.h" +#include "cms_sock_mgr.h" + +/****************************************************************************** + ***************************************************************************** + * MARCO + ***************************************************************************** +******************************************************************************/ + + +#define ATECSKTREQ_MAGIC 0x1234 +#define ATECSKTHANDLE_PORT 60000 +#define ATECSKTREQUEST_PORT 60001 +#define ATECSKTCONNECTTIMEOUT 24 //seconds +#define ATSOCHIBTCPCONTEXTMAGIC 0xABCD +#define ATSOCHIBUDPCONTEXTMAGIC 0xDCBA + +#define AT_SOC_MAX_REF_URL_IPADDR_LEN 255 +#define AT_SOC_REF_STATE_MAX_LEN 1024 +/*AT SOCKET related define*/ +#define AT_SOC_FD_MAX (CMS_SOCK_MGR_CONTEXT_NUM_MAX - 1) +#define AT_SOC_FD_MIN 0 +#define AT_SOC_FD_DEF -2 +#define AT_SOC_FD_ALL 255 +#define AT_SOC_UL_LENGTH_MAX 1400 +#define AT_SOC_UL_LENGTH_MIN 1 +#define AT_SOC_DL_LENGTH_MAX 1358 +#define AT_SOC_DL_LENGTH_MIN 1 +#define AT_SOC_PORT_MAX 65535 +#define AT_SOC_PORT_MIN 1 +#define AT_SOC_UL_DATA_SEQUENCE_MAX 255 +#define AT_SOC_UL_DATA_SEQUENCE_MIN 1 +#define AT_SOC_UL_SEGMENT_ID_MAX 4 +#define AT_SOC_UL_SEGMENT_ID_MIN 1 +#define AT_SOC_UL_SEGMENT_NUM_MAX 4 +#define AT_SOC_UL_SEGMENT_NUM_MIN 2 +#define AT_SOC_NOTIFY_MODE_DEF 0 +#define AT_SOC_NOTIFY_MODE_MIN 0 +#define AT_SOC_NOTIFY_MODE_MAX 3 +#define AT_SOC_NOTIFY_MODE_IGNORE 254 +#define AT_SOC_NOTIFY_MODE_PRIVATE_DISABLE 255 +#define AT_SOC_PUBLIC_DL_BUFFER_DEF (2048 ) +#define AT_SOC_PUBLIC_DL_BUFFER_MAX 3072 +#define AT_SOC_PUBLIC_DL_BUFFER_MIN 1358 +#define AT_SOC_PUBLIC_DL_BUFFER_IGNORE 0XFFFF +#define AT_SOC_PRIVATE_DL_BUFFER_DEF 1358 +#define AT_SOC_PRIVATE_DL_BUFFER_MAX 2048 +#define AT_SOC_PRIVATE_DL_BUFFER_MIN 1358 +#define AT_SOC_PRIVATE_DL_BUFFER_MIN 1358 +#define AT_SOC_PRIVATE_DL_BUFFER_IGNORE 0XFFFF +#define AT_SOC_PUBLIC_DL_PKG_NUM_DEF (12) +#define AT_SOC_PUBLIC_DL_PKG_NUM_MAX 16 +#define AT_SOC_PUBLIC_DL_PKG_NUM_MIN 8 +#define AT_SOC_PUBLIC_DL_PKG_NUM_IGNORE 0XFF +#define AT_SOC_PRIVATE_DL_PKG_NUM_DEF 4 +#define AT_SOC_PRIVATE_DL_PKG_NUM_MAX 8 +#define AT_SOC_PRIVATE_DL_PKG_NUM_MIN 1 +#define AT_SOC_PRIVATE_DL_PKG_NUM_IGNORE 0XFF +#define AT_SOC_IP_ADDR_STRING_LENGTH_MAX 63 +#define AT_SOC_QUERY_UL_PENDING_LIST_RESPONSE_LENGTH_MAX 64 + + + +#define SUPPORT_MAX_SOCKET_NUM 5 + +#define SUPPORT_MAX_SOCKET_RAW_DATA_LENGTH 1400 +#define SUPPORT_MAX_SOCKET_HEX_STRING_DATA_LENGTH (SUPPORT_MAX_SOCKET_RAW_DATA_LENGTH * 2 + 1) +#define SUPPORT_MAX_TCP_SERVER_LISTEN_NUM 3 + + +#define SUPPORT_REF_MAX_SOCKET_RAW_DATA_LENGTH (1460 + 1) + + +#define SUPPORT_REF_UL_SEND_BUFFER_MAX (SUPPORT_REF_MAX_SOCKET_RAW_DATA_LENGTH * 5) + +/****************************************************************************** + ***************************************************************************** + * ENUM + ***************************************************************************** +******************************************************************************/ + +typedef enum { +/***********AT SKT **************************/ + ATECSKTREQ_CREATE = 1, + ATECSKTREQ_BIND, + ATECSKTREQ_CONNECT, + ATECSKTREQ_SEND, + ATECSKTREQ_DELETE, + ATECSKTREQ_STATUS, + ATECSKTREQ_MAX = 30, + +/***********AT QI **************************/ + ATECQIREQ_CREATE = 31, + ATECQIREQ_BIND , + ATECQIREQ_CONNECT, + ATECQIREQ_SEND, /*send the raw data,may be a present string or a Hex string */ + ATECQIREQ_SENDHEX, /*send the hex data */ + ATECQIREQ_SEND_PSTH_DATA, /*send the data with passthrough mode */ + ATECQIREQ_GSOCK, + ATECQIREQ_DELETE, + ATECQIREQ_READ, + ATECQIREQ_STATUS, + ATECQIREQ_SETDATAACCMODE, + ATECQIREQ_GETDATAACCMODE, + ATECQIREQ_MAX= 50, + +/**********AT EC SOC**********************************/ + ECSOCREQ_CREATE = 51, + ECSOCREQ_UDPSEND, + ECSOCREQ_UDPSENDF, + ECSOCREQ_QUERY, + ECSOCREQ_READ, + ECSOCREQ_TCPCONNECT, + ECSOCREQ_TCPSEND , + ECSOCREQ_CLOSE, + ECSOCREQ_NMI , + ECSOCREQ_NMIE , + ECSOCREQ_GNMI , + ECSOCREQ_GNMIE, + ECSOCREQ_STATUS, + ECSOCREQ_MAX, +/***********AT EC SRV***********************************/ + ECSRVSOCREQ_CREATETCP = 90, + ECSRVSOCREQ_CLOSELISTEN, + ECSRVSOCREQ_CLOSECLIENT, + ECSRVSOCREQ_SENDCLIENT, + ECSRVSOCREQ_STATUSLISTEN, + ECSRVSOCREQ_MAX= 110, + +/********************rsvd********************************/ + + ECSKT_MAX = 255, +}AtecSktReqId; + + + +/* + * APPL SGID: APPL_SOCKET/APPL_ECSOC, related PRIM ID +*/ +typedef enum applSockPrimId_Enum +{ + APPL_SOCKET_PRIM_BASE = 0, + + APPL_SOCKET_CREATE_CNF, // + APPL_SOCKET_BIND_CNF, + APPL_SOCKET_CONNECT_CNF, + APPL_SOCKET_SEND_CNF, + APPL_SOCKET_DELETE_CNF, + APPL_SOCKET_STATUS_CNF, + APPL_SOCKET_ERROR_IND, + APPL_SOCKET_RCV_IND, + + APPL_QISOCKET_CREATE_CNF, + APPL_QISOCKET_BIND_CNF, + APPL_QISOCKET_CONNECT_CNF, + APPL_QISOCKET_SEND_CNF, + APPL_QISOCKET_SENDHEX_CNF, + APPL_QISOCKET_SENDPSRH_CNF, + APPL_QISOCKET_READ_CNF, + APPL_QISOCKET_QUERYSOCK_CNF, + APPL_QISOCKET_DELETE_CNF, + APPL_QISOCKET_STATUS_CNF, + APPL_QISOCKET_SETMODE_CNF, + APPL_QISOCKET_GETMODE_CNF, + APPL_QISOCKET_ACCMODE_IND, + APPL_QISOCKET_ERROR_IND, + APPL_QISOCKET_RCV_IND, + APPL_QISOCKET_CREATE_IND, + APPL_QISOCKET_CLOSE_IND, + + APPL_ECSOC_CREATE_CNF, + APPL_ECSOC_UDPSEND_CNF, + APPL_ECSOC_UDPSENDF_CNF, + APPL_ECSOC_QUERY_CNF, + APPL_ECSOC_READ_CNF, + APPL_ECSOC_TCPCONNECT_CNF, + APPL_ECSOC_TCPSEND_CNF, + APPL_ECSOC_CLOSE_CNF, + APPL_ECSOC_NMI_CNF, + APPL_ECSOC_NMIE_CNF, + APPL_ECSOC_GNMI_CNF, + APPL_ECSOC_GNMIE_CNF, + APPL_ECSOC_STATUS_CNF, + APPL_ECSOC_NMI_IND, + APPL_ECSOC_CLOSE_IND, + APPL_ECSOC_QUERY_RESULT_IND, + APPL_ECSOC_GNMIE_IND, + APPL_ECSOC_ULSTATUS_IND, + APPL_ECSOC_STATUS_IND, + APPL_ECSOC_CONNECTED_IND, + + APPL_ECSRVSOC_CREATE_TCP_LISTEN_CNF, + APPL_ECSRVSOC_CLOSE_TCP_LISTEN_CNF, + APPL_ECSRVSOC_CLOSE_TCP_CLIENT_CNF, + APPL_ECSRVSOC_SEND_TCP_CLIENT_CNF, + APPL_ECSRVSOC_STATUS_TCP_LISTEN_CNF, + APPL_ECSRVSOC_CREATE_TCP_LISTEN_IND, + APPL_ECSRVSOC_SERVER_ACCEPT_CLIENT_IND, + APPL_ECSRVSOC_STATUS_TCP_LISTEN_IND, + APPL_ECSRVSOC_RECEIVE_TCP_CLIENT_IND, + APPL_ECSRVSOC_CLOSE_TCP_CONNECTION_IND, + APPL_ECSRVSOC_SERVER_REFUSE_CLIENT_IND, + + APPL_SOCKET_PRIM_MAX = 255 +}ApplSockPrimId; + + +/* + * value of "ApplRetCnf->header.rc" +*/ +typedef enum ApplSockRetCode_enum +{ + SOCKET_ACTION_OK = 0, + SOCKET_PARAM_ERROR = 1, //parameter error + SOCKET_TOO_MUCH_INST = 2, //too much socket instance + SOCKET_CREATE_SOCK_ERROR = 3, //create socket error + SOCKET_OPERATION_NOT_SUPPORT = 4, //operation not support + SOCKET_NO_FIND_CLIENT = 5, //operation not support + SOCKET_CONNECT_FAIL = 6, //connect failed + SOCKET_BIND_FAIL = 7, //bind failed + SOCKET_SEND_FAIL = 8, //send failed + SOCKET_NO_CONNECTED = 9, //connect failed + SOCKET_IS_CONNECTED = 10, //already connected + SOCKET_INVALID_STATUS, + SOCKET_CONNECT_TIMEOUT, + SOCKET_DELETE_FAIL, + SOCKET_FATAL_ERROR, //fatal error + SOCKET_NO_MEMORY, + SOCKET_NO_MORE_DL_BUFFER_RESOURCE, + SOCKET_CONNECT_IS_ONGOING, + SOCKET_UL_SEQUENCE_INVALID, + SOCKET_UNKNOWN, +}ApplSockRetCode; + + + +typedef enum AtecSktDataRelAssistInd_Tag +{ + ATEC_SKT_DATA_RAI_NO_INFO = 0, + ATEC_SKT_DATA_RAI_NO_UL_DL_FOLLOWED = 1, + ATEC_SKT_DATA_RAI_ONLY_DL_FOLLOWED = 2, + ATEC_SKT_DATA_RAI_RESERVED = 3 +}AtecSktDataRelAssistIndEnum; + +typedef enum { + ATECECSOC_FAIL = 0, + ATECECSOC_SUCCESS = 1, +}AtecEcSocUlStatus; + +typedef enum AtSocketType_Tag +{ + AT_SOCKET_ATSKT = 0, + AT_SOCKET_ECSOC = 1, + AT_SOCKET_SDKSOC = 2, +}AtSocketTypeEnum; + +typedef enum { + SOCK_CLOSED = 0, //socket delete + SOCK_INIT = 1, //socket create + SOCK_CONNECTING = 2, //socket is connecting + SOCK_CONNECTED = 3, //socket connected +}sockStatus; + +typedef enum { + MODE_PUBLIC = 0, + MODE_PRIVATE = 1, +}EcSocModeFlag; + +typedef enum { + RCV_DISABLE = 0, //diabel receive DL packet + RCV_ENABLE = 1, //enable receive DL packet +}EcSocRcvControlFlag; + +typedef enum { + NMI_MODE_0 = 0, //disable notify + NMI_MODE_1 = 1, //notify with socketid and length + NMI_MODE_2 = 2, //notify with socketid, server address&port, length and data + NMI_MODE_3 = 3, //notify with socketid, length and data +}EcSocNotifyIndMode; + +typedef enum { + EC_SOCK_VALID = 0, //EC socket available + EC_SOCK_INVALID = 1, //EC socket unavailable + EC_SOCK_FLOW_CONTROL = 2, //flow control + EC_SOCK_BACK_OFF = 3, //back off +}EcSockStatus; + + + +/****************************************************************************** + ***************************************************************************** + * STRUCT + ***************************************************************************** +******************************************************************************/ + +/******************************ATSKT related**********************************/ + +typedef struct AtecSktCreateReq_Tag{ + INT32 domain; + INT32 type; + INT32 protocol; + UINT32 reqSource; + void *eventCallback; +}AtecSktCreateReq; + +typedef struct AtecSktSendReq_Tag{ + INT32 fd; + UINT32 sendLen; + UINT8 dataRai; + BOOL dataExpect; + UINT16 rsvd; + UINT32 reqSource; + UINT8 data[]; +}AtecSktSendReq; + +typedef struct AtecSktBindReq_Tag{ + INT32 fd; + UINT16 localPort; + UINT16 reserved; + UINT32 reqSource; + ip_addr_t localAddr; +}AtecSktBindReq; + +typedef struct AtecSktConnectReq_Tag{ + INT32 fd; + UINT16 remotePort; + UINT16 reserved; + UINT32 reqSource; + ip_addr_t remoteAddr; +}AtecSktConnectReq; + +typedef struct AtecSktDeleteReq_Tag{ + INT32 fd; + UINT32 reqSource; +}AtecSktDeleteReq; + +typedef struct AtecSktStatusReq_Tag{ + INT32 fd; + UINT32 reqSource; +}AtecSktStatusReq; + +typedef struct AtecSktDlInd_Tag{ + INT32 fd; + UINT16 len; + UINT16 rsvd; +}AtecSktDlInd; + +typedef struct AtecSktCnfTag +{ + union { + UINT32 errCode; + INT32 fd; + INT32 status; + }cnfBody; +}AtecSktCnf; + +typedef struct AtecSktPriMgrContext_Tag{ + UINT16 createReqHandle; + UINT16 connectReqHandle; +}AtecSktPriMgrContext; + +/******************************ECSOC related**********************************/ + +typedef struct EcSocCreateReq_Tag{ + INT32 type; + INT32 protocol; + INT32 domain; + UINT8 receiveControl; + UINT8 reserved; + UINT16 listenPort; + UINT32 reqSource; + void *eventCallback; + ip_addr_t localAddr; +}EcSocCreateReq; + + +typedef struct EcSocUdpSendReq_Tag{ + INT32 socketId; + UINT16 remotePort; + UINT16 length; + UINT8 sequence; + UINT8 segmentId; + UINT8 segmentNum; + UINT8 exceptionFlag; + UINT8 raiInfo; + UINT8 reserved1; + UINT16 reserved2; + UINT32 reqSource; + ip_addr_t remoteAddr; + UINT8 data[]; +}EcSocUdpSendReq; + +typedef struct EcSocQueryReq_Tag{ + UINT32 reqSource; + BOOL bQueryAll; + UINT8 rsvd1; + UINT16 rsvd2; + INT32 socketId[SUPPORT_MAX_SOCKET_NUM]; +}EcSocQueryReq; + +typedef struct EcSocReadReq_Tag{ + INT32 socketId; + UINT16 length; + UINT16 reserved; + UINT32 reqSource; +}EcSocReadReq; + +typedef struct EcSocTcpConnectReq_Tag{ + INT32 socketId; + UINT16 remotePort; + UINT16 reserved; + UINT32 reqSource; + ip_addr_t remoteAddr; +}EcSocTcpConnectReq; + +typedef struct EcSocTcpSendReq_Tag{ + INT32 socketId; + UINT16 length; + UINT8 sequence; + UINT8 expectionFlag; + UINT8 raiInfo; + UINT8 reserved1; + UINT16 reserved2; + UINT32 reqSource; + UINT8 data[]; +}EcSocTcpSendReq; + +typedef struct EcSocCloseReq_Tag{ + INT32 socketId; + UINT32 reqSource; +}EcSocCloseReq; + +typedef struct EcSocNMIReq_Tag{ + UINT8 mode; + UINT8 maxPublicDlPkgNum; + UINT16 maxPublicDlBuffer; + UINT32 reqSource; +}EcSocNMIReq; + +typedef struct EcSocNMIEReq_Tag{ + INT32 socketId; + UINT8 mode; + UINT8 maxPublicDlPkgNum; + UINT16 maxPublicDlBuffer; + UINT32 reqSource; +}EcSocNMIEReq; + +typedef struct EcSocNMIGetReq_Tag{ + UINT32 reqSource; +}EcSocNMIGetReq; + +typedef struct EcSocNMIEGetReq_Tag{ + UINT32 reqSource; +}EcSocNMIEGetReq; + +typedef struct EcSocStatusReq_Tag{ + BOOL bQuryAll; + UINT8 rsvd1; + UINT16 rsvd2; + INT32 socketId; + UINT32 reqSource; +}EcSocStatusReq; + +typedef struct EcSocUlStatusReq_Tag{ + INT32 socketId; + INT32 ulStatus; + UINT32 sequenceBitMap[8]; +}EcSocUlStatusReq; + +typedef struct EcSocCreateResponse_Tag{ + INT32 socketId; +}EcSocCreateResponse; + +typedef struct EcSocUdpSendResponse_Tag{ + INT32 socketId; + UINT16 length; + UINT16 reserved; +}EcSocUdpSendResponse; + +typedef struct EcSocQueryInd_Tag{ + INT32 socketId; + UINT8 sequence; + UINT8 reserved1; + UINT16 reserved2; +}EcSocQueryInd; + +typedef struct EcSocReadResponse_Tag{ + INT32 socketId; + ip_addr_t remoteAddr; + UINT16 remotePort; + UINT16 length; + UINT16 remainingLen; + UINT8 reserved; + UINT8 data[]; +}EcSocReadResponse; + +typedef struct EcSocNMInd_Tag{ + INT32 socketId; + ip_addr_t remoteAddr; + UINT16 remotePort; + UINT16 length; + UINT8 modeNMI; + UINT8 serviceType; + UINT16 reserved2; + CHAR data[]; +}EcSocNMInd; + +typedef struct EcSocTcpSendResponse_Tag{ + INT32 socketId; + UINT16 length; + UINT16 reserved; +}EcSocTcpSendResponse; + +typedef struct EcSocGNMIResponse_Tag{ + UINT8 mode; + UINT8 maxDlPkgNum; + UINT16 maxDlBufferSize; +}EcSocGNMIResponse; + +typedef struct EcSocGNMIEInd_Tag{ + INT32 socketId; + UINT8 mode; + UINT8 maxDlPkgNum; + UINT16 maxDlBufferSize; +}EcSocGNMIEInd; + +typedef struct EcSocCloseInd_Tag{ + INT32 socketId; + INT32 errCode; + UINT8 sockStatus; + UINT8 accMode; + UINT16 reserved; +}EcSocCloseInd; + +typedef struct EcSocUlStatusInd_Tag{ + INT32 socketId; + UINT8 sequence; + UINT8 status; //AtecEcSocUlStatus + UINT16 reserved; +}EcSocUlStatusInd; + +typedef struct EcSocStatusInd_Tag{ + INT32 socketId; + UINT8 status;//EcSockStatus + UINT8 rsvd; + UINT16 backOffTimer; +}EcSocStatusInd; + +typedef struct EcSocConnectedInd_Tag{ + INT32 socketId; +}EcSocConnectedInd; + +typedef struct AtecSocCnfTag +{ + union { + UINT32 errCode; + INT32 fd; + INT32 status; + }cnfBody; +}AtecSocCnf; + +typedef struct AtecEcSocErrCnfTag +{ + UINT32 errCode; +}AtecEcSocErrCnf; + +typedef struct EcSocUlBuffer_Tag{ + UINT8 segmentId; + UINT8 reserved; + UINT16 length; + struct EcSocUlBuffer_Tag *next; + UINT8 data[]; +}EcSocUlBuffer; + +typedef struct EcSocUlList_Tag{ + UINT8 sequence; + UINT8 segmentNum; + UINT16 remotePort; + UINT8 segmentAlready; + UINT8 reserved1; + UINT16 reserved2; + ip_addr_t remoteAddr; + struct EcSocUlList_Tag *next; + EcSocUlBuffer *ulData; +}EcSocUlList; + +typedef struct EcSocDlBufferList_Tag{ + BOOL isPrivate; //default FALSE + UINT8 reserved1; + UINT16 totalLen; + UINT16 reserved; + UINT16 length; /*the actual raw data length,*/ + UINT16 offSet; + UINT16 remotePort; + ip_addr_t remoteAddr; + CmsSockMgrDataContext *dataContext; + struct EcSocDlBufferList_Tag *next; + +}EcSocDlBufferList; + +typedef struct EcSocModeSet_Tag{ + UINT8 flag:1; //EcSocModeFlag + UINT8 mode:2; //EcSocNotifyIndMode + UINT8 receiveControl:1; //EcSocRcvControlFlag + UINT8 reserved:4; +}EcSocModeSet; + +typedef struct EcSocUlSequenceStatus_Tag{ + UINT32 bitmap[8]; +}EcSocUlSequenceStatus; + +typedef struct EcSocDlPrivateSet_Tag{ + UINT16 privateDlBufferToalSize; + UINT16 privateDlBufferTotalUsage; + UINT8 privateDlPkgNumMax; + UINT8 privateDlPkgNumTotalUsage; + UINT16 reserved; +}EcSocDlPrivateSet; + +typedef struct EcSocPublicDlConfig_Tag{ + UINT32 publicDlBufferToalSize; + UINT32 dlBuffTotalUsage; + + UINT8 publicDlPkgNumMax; + UINT8 dlNumTotalUsage; + + UINT8 mode; + UINT8 receiveControl; +}EcSocPublicDlConfig; + +typedef struct EcsocPriMgrContext_Tag{ + UINT16 rsvd1; + UINT16 dlTotalLen; + UINT16 createReqHandle; + UINT16 connectReqHandle; + EcSocModeSet modeSet; + EcSocDlPrivateSet dlPriSet; + EcSocUlSequenceStatus ulSeqStatus; + EcSocUlList *ulList; //only for udp socket + EcSocDlBufferList *dlList; +}EcsocPriMgrContext; + + +#define __REF_SOCK_DEFINE_GLOBAL_VARIABLES__ + +/***************************** ref related ***********************************/ + + +typedef enum AtRefSocServiceType_Tag +{ + ATEC_REF_SOCK_TCP_CLIENT_MODE = 0, + ATEC_REF_SOCK_UDP_CLIENT_MODE, + ATEC_REF_SOCK_TCP_SERVER_MODE, + ATEC_REF_SOCK_TCP_SERVER_ACCEPT_CLIENT_MODE, + ATEC_REF_SOCK_UDP_SERVER_MODE, + ATEC_REF_SOCK_UDP_SERVER_ACCEPT_CLIENT_MODE, + ATEC_REF_SOCK_UDP_SERVER_MAX =128, +}AtRefSocServiceType; + +typedef struct atRefServiceTypeTable_Tag +{ + UINT8 serviceId; + const CHAR *serviceName; +}atRefServiceTypeTable; + + +typedef struct atRefSockAccPathTable_Tag +{ + UINT8 accId; + const CHAR *accPathName; +}atRefSockAccPathTable; + + +typedef enum AtRefDataAccessMode_tag { + ATEC_REF_DATA_ACC_BUFF_MODE = 0, + ATEC_REF_DATA_ACC_DIRECT_MODE, + ATEC_REF_DATA_ACC_PASSTHROUGH_MODE +}AtRefataAccessMode; + + +typedef enum AtRefDataSendStatus_Tag{ + ATEC_REF_DATA_SEND_TO_BUFF_SUCC =0, + ATEC_REF_DATA_SEND_TO_BUFF_FAIL =1, + ATEC_REF_DATA_SEND_TO_BUFF_ONGOING =2 +}AtRefDataSendStatus ; + + +typedef enum AtRefSockStatus_Tag{ + REF_SOCK_INIT = 0, //"initial state + REF_SOCK_OPENING = 1, //"opening" state + REF_SOCK_CONNECTED = 2, //"Connected" state + REF_SOCK_LISTENING = 3, //"Listening" state + REF_SOCK_CLOSED = 4, //"Closing" state +}AtRefSockStatus; + + +typedef enum AtRefSockAccPath_Tag{ + SOCK_ACC_USB_MODEM = 0, //"usb modem port" + SOCK_ACC_USB_AT = 1, //"usb AT port" + SOCK_ACC_UART_1_AT = 2, //UART port 1 + SOCK_ACC_MUX_1_AT = 3, //MUX port 1 + SOCK_ACC_MUX_2_AT = 4, //MUX port 2 + SOCK_ACC_MUX_3_AT = 5, //MUX port 3 + SOCK_ACC_MUX_4_AT = 6, //MUX port 4 + SOCK_ACC_MAX = 128, +}AtRefSockAccPath; + +typedef enum AtRefSockSendViewMode_Tag{ + SOCK_URC_IND_REPORT_DISABLE = 0, + SOCK_URC_IND_REPORT_ENABLE = 1, +}AtRefSockSendViewMode; + + +typedef struct AtRefSocketDlConfig_Tag{ + UINT32 dLTotaLUsage; /*dynamic statistic the total used size*/ + UINT32 dlTotalSize; /*defined the max size*/ +}AtEcSocketDlConfig; + + + +typedef struct AtRefSocCloseInd_Tag{ + UINT8 connectId; + UINT8 sockStatus; + UINT8 accMode; + UINT8 resv0; + + INT32 errCode; +}AtRefSocCloseInd; + +/*brief:AT+QISEND/AT+QISENDEX/PASSTHROUGH mode use*/ +typedef struct AtRefSocketSendInfo_Tag +{ + UINT8 connectId; + UINT8 source; + UINT16 reqHander; /*if set to zero, just means no sending request */ + + UINT16 dataOffset; + UINT16 requestId; + + UINT16 remotePort; + UINT16 dataLen; + + ip_addr_t remoteAddr; + void *pPdu; /*Dyn mem, raw data send to SOCK task, for feature, could be UlPduBlock*/ +}AtRefSocketSendInfo; + +typedef struct AtRefPassThroughSockInfo_Tag +{ + UINT8 connectId; + UINT8 resv0; + UINT16 reqHander; +}AtRefPassThroughSockInfo; /*4 bytes*/ + +typedef struct AtRefSocSendCnf_Tag{ + UINT8 primId; + UINT8 status; + UINT8 accMode; + UINT8 connectId; + + UINT16 bufFreeSize; + UINT16 resv0; + + UINT32 reqSource; + +}AtRefSocSendCnf; + +typedef struct AtRefSocPackQueryReq_Tag{ + UINT8 connectId; + UINT8 recv0; + UINT16 sendLen; + UINT32 reqSource; +}AtRefSocPackQueryReq; + +typedef struct AtRefSocPackQueryCnf_Tag{ + UINT8 connectId; + UINT8 recv0; + UINT16 recv1; + + UINT32 totallen; + UINT32 ackBytesLen; + UINT32 unAckBytesLen; + UINT32 reqSource; +}AtRefSocPackQueryCnf; + +/* AT+QIRD */ +#define MAX_READ_DATA_LEN 1500 +typedef enum AtRefQiReadType_Tag +{ + QI_READ_TYPE_TCP_UDP_INCOMING,//: "TCP"/"UDP"/"TCP INCOMING"/"UDP INCOMING" + QI_READ_TYPE_UDP_SERVICE,//: "UDP SERVICE" + QI_READ_TYPE_QUERY //,0 query read data +}AtRefQiReadType; + +typedef struct AtRefQiReadReq_Tag{ + UINT8 connectId; + BOOL lenPresent; + UINT16 length; + + UINT32 reqSource; +}AtRefQiReadReq; + +typedef struct AtRefQiReadCnf_Tag +{ + UINT8 type;//AtRefQiReadType + UINT8 resvd1; + UINT16 reqLength; + UINT32 totalRcvLen;//total receive data length + UINT32 haveRdLen;//have read length + UINT16 unreadLen;//unread length + UINT16 remotePort; + ip_addr_t remoteAddr; + CmsSockMgrDataContext *dataContext; +}AtRefQiReadCnf; + +typedef struct AtRefSocketCreateReq_Tag{ + UINT8 cid; + UINT8 serviceType; //AtRefSocServiceType + UINT8 connedId; + UINT8 accessMode; + UINT16 remotePort; + UINT16 localPort; + UINT32 reqSource; + void *eventCallback; + CHAR remote[AT_SOC_MAX_REF_URL_IPADDR_LEN+1]; +}AtRefSocketCreateReq; + +typedef struct AtRefSocCreateResponse_Tag{ + UINT8 connectId; + UINT8 accessMode; + UINT16 result; +}AtRefSocCreateResponse; + +typedef struct AtRefSocketCloseReq_Tag{ + UINT8 connetId; + UINT8 rsvd; + UINT16 timeout; + UINT32 reqSource; +}AtRefSocketCloseReq; + +typedef struct AtRefSocketDnsResolveCnf_Tag{ + UINT8 result; + UINT8 rsvd; + UINT16 rsvd1; + ip_addr_t address; + CHAR remote[AT_SOC_MAX_REF_URL_IPADDR_LEN+1]; +}AtRefSocketDnsResolveCnf; + + +/*AT+QISTATE= */ +typedef struct AtRefSocQueryStateReq_Tag{ + UINT8 reqAll; + UINT8 queryId; + UINT8 queryType; + UINT8 resv0; + + UINT32 reqSource; +}AtRefSocQueryStateReq; + +typedef struct AtRefSocQueryStateCnfMsg_Tag{ + UINT8 num; + UINT8 reserv0; + UINT16 reserv1; + UINT8 *pdata; +}AtRefSocQueryStateCnfMsg; + + +typedef struct AtRefSocStateMsgBody_Tag{ + INT32 sockId; + INT32 serverId; + + UINT8 conntextId; + UINT8 accessMode; + UINT8 serviceType; + UINT8 socketState; + + UINT8 sockAccPath; + UINT8 resv0; + UINT16 localPort; + + UINT16 remotePort; + UINT16 resv1; + ip_addr_t ipAddr; +}AtRefSocStateMsgBody; + + +/* + * Change socket (QISOCK) access mode, in case of + * 1> AT+QISWTMD=, // 0-buffer mode, 1-direct mode, 2-pass through mode + * 2> '+++'/DTR, transfer from 2 (pass throgh mode) to 0 (buffer mode) +*/ +typedef struct AtRefSocSetDataAccModeReq_Tag{ + UINT8 connectId; + UINT8 mode; /* AtRefataAccessMode, 0-buffer mode, 1-direct mode, 2-pass through mode */ + UINT8 trgSrc; /* trigger source, 0 - AT+QISWTMD, 1 - '+++', 2 - DTR */ + UINT8 resv0; + + UINT16 atHandler; /* Request AT hander, in case of "+++"/DTR, pass the old atHandler */ + UINT16 error; +}AtRefSocSetDataAccModeReq; + +typedef struct AtRefSocSetDataAccModeCnf_Tag{ + UINT8 connectId; + UINT8 setNewmode; /* AtRefataAccessMode, 0-buffer mode, 1-direct mode, 2-pass through mode */ + UINT8 resv0; + UINT8 trgSrc; /* trigger source, 0 - AT+QISWTMD, 1 - '+++', 2 - DTR */ + + UINT16 atHandler; + UINT16 rsv1; +}AtRefSocSetDataAccModeCnf; + + +typedef struct AtRefSocNotifyAccModeInd_Tag{ + UINT8 connectId; + UINT8 accmode; + UINT16 result; + UINT32 reqSource; +}AtRefSocNotifyAccModeInd; + + +typedef struct AtRefSocGetDataAccModeReq_Tag{ + UINT8 connectId; + UINT8 resv0; + UINT16 resv1 ; + UINT32 reqSource; +}AtRefSocGetDataAccModeReq; + +typedef struct AtRefSocGetDataAccModeCnf_Tag{ + UINT8 mode; + UINT8 connectId; + UINT16 resv0; +}AtRefSocGetDataAccModeCnf; + +typedef struct AtRefSocPriMgrContext_Tag +{ + UINT8 connectId :4; /*connectId 1~11*/ + UINT8 pdpContextId :4; /*pdp contextId from 0~15*/ + + UINT8 oldAccMode:2; /*record the old accmode before changed by AT+QISWTMD/ATO/+++*/ + UINT8 accessMode:2; /*accessMode 0,1,2*/ + UINT8 sockstate:3; + UINT8 resv0:1; + + UINT16 reqHandle; /*source AT request handle */ + + AtRefSocServiceType serviceType; /*serviceType,0~5*/ + UINT8 resv1; + UINT16 remotePort; + + INT32 errorCode ; /*record the sockerrno when erroc occured*/ + + UINT32 ulTotalLen; /* total ul send length,maybe this length is not the actual received length of peer */ + UINT32 ulTotalAckedLen; /* tcp ul length of has been acked by peer */ + UINT32 dlTotalLen; /* total length of DL data since socket created, add when recv new data,clear it after socket disconn*/ + UINT32 dlUnreadLen; /* unread length of DL data*/ + EcSocDlBufferList *pDlList; + CHAR remote[AT_SOC_MAX_REF_URL_IPADDR_LEN +1]; +}AtRefSocPriMgrContext; + + +typedef struct AtRefSocHibPriMgrContext_Tag +{ + UINT8 connectId ; /*connectId 1~11*/ + UINT8 pdpContextId; /*context Id*/ + UINT16 reqHandle; /*source AT request handle */ + AtRefSocServiceType serviceType; /*serviceTypeï¼?~5*/ + AtRefataAccessMode accessMode; /*accessModeï¼?,1,2*/ + AtRefSockStatus sockstate; + UINT32 dlTotalLen; + UINT32 ulTotalLen; + UINT32 ulTotalAckedLen; /* tcp ul length of has been acked by peer */ + UINT32 dlUnreadLen; /* unread length of DL data*/ +}AtRefSocHibPriMgrContext; + + + +typedef struct AtRefSocketCnf_Tag +{ + UINT32 errCode; + union{ + /*AT+QISEND/QISENDEX to send data*/ + AtRefSocSendCnf sendSocDataCnfMsg; + + /*AT+QISEND to query sock package*/ + AtRefSocPackQueryCnf queryPackCnfMsg; + + /*AT+QISTATE */ + AtRefSocQueryStateCnfMsg queryStateCnfMsg; + + /*AT+QISWTMD to set*/ + AtRefSocSetDataAccModeCnf setAccModeCnfMsg; + + /*AT+QISWTMD to get*/ + AtRefSocGetDataAccModeCnf getAccModeCnfMsg; + + + /*AT+QIRD */ + AtRefQiReadCnf readCnfMsg; + + }body; + +}AtRefSocketCnf; + + +/******************************SDKAPI related**********************************/ + +typedef struct SdkCreateConnectionReq_Tag{ + UINT32 protocol; + UINT32 reqTicks; + UINT16 localPort; + UINT16 destPort; + ip_addr_t localAddr; + ip_addr_t destAddr; + void *callback; +}SdkCreateConnectionReq; + +typedef struct SdkSendDataReq_Tag{ + INT32 connectionId; + UINT32 reqTicks; + UINT16 length; + UINT8 sequence; + UINT8 raiInfo; + UINT8 data[]; +}SdkSendDataReq; + +typedef struct SdkCloseReq_Tag{ + INT32 connectionId; +}SdkCloseReq; + +typedef struct SdkSktResult_Tag{ + INT32 result; + union { + INT32 connectionId; + UINT16 sendLen; + }body; +}SdkSktResult; +/*****************************ec server soc related****************************/ +typedef struct EcSrvSocCreateTcpReq_Tag{ + INT32 domain; + UINT8 rsvd1; + UINT8 rsvd2; + UINT16 listenPort; + UINT32 reqSource; + void *eventCallback; + ip_addr_t bindAddr; +}EcSrvSocCreateTcpReq; + +typedef struct EcSrvSocCloseTcpServerReq_Tag{ + INT32 socketId; + BOOL bCloseClient; + UINT8 rsvd1; + UINT8 rsvd2; + UINT32 reqSource; +}EcSrvSocCloseTcpServerReq; + +typedef struct EcSrvSocCloseTcpClientReq_Tag{ + INT32 socketServerId; + INT32 socketClientId; + UINT32 reqSource; +}EcSrvSocCloseTcpClientReq; + +typedef struct EcSrvSocSendTcpClientReq_Tag{ + INT32 socketClientId; + UINT32 sendLen; + UINT8 dataRai; + BOOL dataExpect; + UINT8 rsvd; + UINT8 sequence; + UINT32 reqSource; + UINT8 data[]; +}EcSrvSocSendTcpClientReq; + +typedef struct EcSrvSocStatusTcpServerReq_Tag{ + INT32 socketId; + UINT32 reqSource; +}EcSrvSocStatusTcpServerReq; + +typedef struct EcSrcSocCreateTcpListenInd_Tag{ + INT32 result; + INT32 socketId; +}EcSrcSocCreateTcpListenInd; + +typedef struct EcSrvSocTcpAcceptClientReaultInd_Tag{ + INT32 serverSocketId; + INT32 clientSocketId; + UINT16 clientPort; + UINT16 rsvd; + ip_addr_t clientAddr; +}EcSrvSocTcpAcceptClientReaultInd; + +typedef struct EcSrvSocTcpListenStatusInd_Tag{ + INT32 serverSocketId; + INT32 status; +}EcSrvSocTcpListenStatusInd; + +typedef struct EcSrvSocTcpClientReceiveInd_Tag{ + INT32 socketId; + UINT16 length; + UINT16 remoteIp; + ip_addr_t remoteAddr; + UINT8 data[]; +}EcSrvSocTcpClientReceiveInd; + +typedef struct EcSrvSocCloseInd_Tag{ + INT32 socketId; + INT32 errCode; + BOOL bServer; + UINT8 rsvd1; + UINT16 rsvd2; +}EcSrvSocCloseInd; + +typedef struct AtecEcSrvSocErrCnf_Tag +{ + UINT32 errCode; +}AtecEcSrvSocErrCnf; + + +typedef struct EcSrvSocTcpRefuseClientReaultInd_Tag{ + INT32 serverSocketId; + INT32 clientSocketId; + UINT16 clientPort; + UINT16 cause; + ip_addr_t clientAddr; +}EcSrvSocTcpRefuseClientReaultInd; + + +typedef struct EcSrvSocPriMgrContext_Tag{ + UINT16 createReqHandle; + UINT16 listenPort; + INT32 fSocketId; //father socket + ip_addr_t bindAddr; +}EcSrvSocPriMgrContext; + +typedef struct AtSocketSendInfo_Tag +{ + INT32 socketId; + UINT16 reqHander; /*if set to zero, just means no sending request */ + UINT16 dataOffset; + INT32 dataLen; + BOOL expectData; + UINT8 raiInfo; + UINT8 sequence; + UINT8 source; + UINT16 requestId; + UINT16 remotePort; + ip_addr_t remoteAddr; + UINT8 data[SUPPORT_MAX_SOCKET_HEX_STRING_DATA_LENGTH]; +}AtSocketSendInfo; + + + +/******************************common related**********************************/ +typedef struct AtecSktReq_Tag{ + UINT16 magic; //ATECSKTREQ_MAGIC + UINT16 reqId; + UINT32 reqSource; + void* reqBody; +}AtecSktReq; + +typedef struct SdkSktResponse_Tag{ + UINT16 magic; //ATECSKTREQ_MAGIC + UINT16 reqId; + SdkSktResult reqResult; +}SdkSktResponse; + + +typedef struct socketAtcmd_Tag +{ + UINT8 status; + UINT8 atSockType; //AtSocketTypeEnum + UINT16 createReqHandle; + UINT16 connectReqHandle; + UINT16 reserved; + INT32 socketId; + UINT8 domain; + UINT8 type; + UINT8 protocol; + BOOL hibEnable; + UINT32 connectTime; + EcSocModeSet modeSet; + EcSocDlPrivateSet dlPriSet; + EcSocUlSequenceStatus ulSeqStatus; + EcSocUlList *ulList; //only for udp socket + EcSocDlBufferList *dlList; + struct socketAtcmd_Tag *next; +}socketAtcmd; + +typedef struct GsocketAtcmd_Tag +{ + UINT8 socketNum; + socketAtcmd *socketList; +}GsocketAtcmd; + + +typedef struct EcsocConnHibPriContext_Tag{ + UINT8 domain; + UINT8 rsvd1; + UINT16 rsvd2; + EcSocModeSet modeSet; + UINT16 createReqHandle; + EcSocDlPrivateSet dlPriSet; +}EcsocConnHibPriContext; + +typedef struct AtsktConnHibPriContext_Tag{ + UINT8 domain; + UINT8 rsvd; + UINT16 createReqHandle; +}AtsktConnHibPriContext; + + +/****************************************************************************** + ***************************************************************************** + * FUNCTION/API + ***************************************************************************** +******************************************************************************/ + +void atecSktProessReq(CmsSockMgrRequest *atecSktReq, ip_addr_t *sourceAddr, UINT16 sourcePort, INT32 rcvRequestFd); +void atecEcsocProessReq(CmsSockMgrRequest *atecSktReq, ip_addr_t *sourceAddr, UINT16 sourcePort, INT32 rcvRequestFd); +void atecEcSrvSocProessReq(CmsSockMgrRequest *atecEcSrvSocReq, ip_addr_t *sourceAddr, UINT16 sourcePort, INT32 rcvRequestFd); +void atSktEventCallback(CmsSockMgrContext *mgrContext, CmsSockMgrEventType eventType, void *eventArg); +void atEcsocEventCallback(CmsSockMgrContext *mgrContext, CmsSockMgrEventType eventType, void *eventArg); +void atEcSrvSocEventCallback(CmsSockMgrContext *mgrContext, CmsSockMgrEventType eventType, void *eventArg); +void atSktStoreConnHibContext(CmsSockMgrContext *sockMgrContext, CmsSockMgrConnHibContext *hibContext); +void atEcsocStoreConnHibContext(CmsSockMgrContext *sockMgrContext, CmsSockMgrConnHibContext *hibContext); +void atSktRecoverConnContext(CmsSockMgrConnHibContext *hibContext); +void atecPubSocReduceDlBufferUsage(UINT16 len ); + + +void atSocketInit(void); +BOOL atSockQueryCidIsActivated(UINT8 connectId); + +void atRefSocEventCallback(CmsSockMgrContext *mgrContext, CmsSockMgrEventType eventType, void *eventArg); +UINT32 atRefSocQuerySocketByConnectId(UINT8 cid); + +CmsRetId atRefSockPsthSockResume(UINT16 reqHandle); +AtRefSocPriMgrContext *atRefSocFindPSTHConnectId(UINT8 channelId); +INT32 atRefCloseSockByConnectId(UINT8 cid); + + +#endif + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_ssl_task.h b/PLAT/middleware/developed/at/atentity/inc/at_ssl_task.h new file mode 100644 index 0000000..0419176 --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_ssl_task.h @@ -0,0 +1,202 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: at_ssl_task.h +* +* Description: Process tls client related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _AT_SSL_TASK_H +#define _AT_SSL_TASK_H +#ifdef __USER_CODE__ +#else +#include "at_util.h" +#include "atc_decoder.h" + +#include "mbedtls/net.h" +#include "mbedtls/ssl.h" +#include "mbedtls/certs.h" +#include "mbedtls/entropy.h" +#include "mbedtls/ctr_drbg.h" + +#define MAX_SSL_CLIENT_INSTANCE 12 + +typedef enum +{ + SSL3_0 = 0, + TLS1_0, + TLS1_1, + TLS1_2, + SSL_VERSION_ALL, +}sslVersion_e; + +typedef enum AT_SSL_ERROR +{ + SSLAT_OK = 0, //success + SSLAT_PARAM_ERROR = 1, //parameter error + SSLAT_CONFIG_SSL_ERROR = 2, //ssl config error + SSLAT_MBEDTLS_ERROR = 3, //mbedtls error + SSLAT_CONN_ERROR = 4, //connect error + SSLAT_HAS_CONNENT = 5, //already has a connect + SSLAT_NO_CONNENT = 6, //has no open connect + SSLAT_INTERNAL = 7, //internal error, for example can't restore from deep sleep + SSLAT_MEM_NOT_ENOUGH = 8 //memory not enough +}AtSslError_e; + +enum SSL_CMD_TYPE +{ + SSL_OPEN_COMMAND, + SSL_OPEN_DONE_COMMAND, + SSL_SEND_COMMAND, + SSL_CLOSE_TCP_COMMAND, + SSL_CLOSE_COMMAND, + SSL_STATE_COMMAND, + SSL_DISCON_COMMAND, + SSL_SEND_PT_DATA +}; + +/* + * APPL SGID: APPL_SSL, related PRIM ID +*/ +enum applSslPrimId_Enum +{ + APPL_SSL_PRIM_ID_BASE = 0, + + APPL_SSL_OPEN_CNF, + APPL_SSL_SEND_CNF, + APPL_SSL_CLOSE_CNF, + APPL_SSL_STATE_CNF, + APPL_SSL_URC_IND, + APPL_SSL_OUTPUT_IND, + APPL_SSL_PASSOUT_IND, + APPL_SSL_PRIM_ID_END = 0xFF +}; + +typedef enum { + SSLSTAT_INIT = 0, + SSLSTAT_CONNECT, + SSLSTAT_DISCONN, + SSLSTAT_CLOSE +}SSLAtStatus_e; + +typedef enum +{ + SSL_EN_SLEEP, + SSL_DIS_SLEEP +}SSLSleep_e; + +typedef struct +{ + uint8_t cmd_type; + uint32_t reqHandle; + uint8_t clientId; + uint8_t channelId; + void* ptr; +} sslCmdMsg_t; + +typedef struct +{ + void *pInd; +} sslIndMsg_t; + +typedef struct +{ + uint8_t ret; + uint8_t accessMode; + uint8_t chanId; + char rspbuf[60]; +} sslCnfCmdMsg_t; + +typedef struct sslContextTag +{ + mbedtls_ssl_context sslContext; + mbedtls_net_context netContext; + mbedtls_ssl_config sslConfig; + mbedtls_entropy_context entropyContext; + mbedtls_ctr_drbg_context ctrDrbgContext; + mbedtls_x509_crt_profile crtProfile; + mbedtls_x509_crt caCert; + mbedtls_x509_crt clientCert; + mbedtls_pk_context pkContext; +}sslContext; + +typedef struct _sslPTUlDataNode +{ + struct _sslPTUlDataNode *next; + uint16_t dataLen; /*the send raw datalength*/ + uint8_t* pData; +}sslPTUlDataNode; + +typedef struct _ssl_list_t +{ + struct _ssl_list_t * next; +} ssl_list_t; + +typedef struct sslPTUlPendingList_Tag +{ + ssl_list_t *head; + ssl_list_t *tail; + uint8_t nodeCount; + uint8_t maxNodeNum; + osMutexId_t mut; +}sslPTUlPendingList; + + +typedef struct sslClientContextTag +{ + bool isUsed; + uint8_t pdpId; + uint8_t clientId; + uint8_t sslCxtId; + uint32_t reqhandle; + uint16_t pid; + int socket; + char* serverAddr; + uint16_t serverPort; + uint8_t status; + int timeout_s; + int timeout_r; + uint8_t* sendData; + uint16_t sendDataLen; + sslContext * ssl; + char *caCert; + char *clientCert; + char *clientPk; + int32_t caCertLen; + int32_t clientCertLen; + int32_t clientPkLen; + uint8_t seclevel;//0:no verify; 1:verify server; 2:both verify + int32_t ciphersuite[2];//just like 0x0035 TLS_RSA_WITH_AES_256_CBC_SHA,ciphersuite[1] must NULL + uint8_t cache;//0:no session resumption; 1:session resumption + uint8_t sni;//0:no sni; 1:has sni + uint8_t accessMode;//0:direct mode; 1:passthrough + uint8_t ignore;//0:not ignore; 1:ignore + uint8_t channelState; +}sslClientContext; + +void sslSaveCxtList(void); +void sslEngineInit(void); +CmsRetId sslClientOpen(uint32_t reqHandle, uint8_t clientId, uint8_t channelId); +CmsRetId sslClientSend(uint8_t clientId); +CmsRetId sslClientClose(uint32_t reqHandle, uint8_t clientId); +CmsRetId sslClientState(uint32_t reqHandle, uint8_t clientId); + +void sslDisableSleep(void); + +AtSslError_e sslCheckRestore(void); +void sslNewClientContext(sslClientContext* context, uint8_t pdpId, uint8_t clientId, uint8_t sslCxtId, char* pServer, uint16_t port, uint8_t accessMode); + +CmsRetId sslPSTHAndOnlineCmdCallback(UINT8 chanId, UINT8 curChanState, AtDataAndOnlineCmdSEvt eventId, void *pArg); +bool sslQueryClientIdIsActivated(UINT8 clientId); +#endif +#endif + + diff --git a/PLAT/middleware/developed/at/atentity/inc/at_util.h b/PLAT/middleware/developed/at/atentity/inc/at_util.h new file mode 100644 index 0000000..5650ecb --- /dev/null +++ b/PLAT/middleware/developed/at/atentity/inc/at_util.h @@ -0,0 +1,199 @@ +/****************************************************************************** + * (C) Copyright 2018 AirM2M International Ltd. + * All Rights Reserved +******************************************************************************* + * Filename: at_util.h + * + * Description: AT utility + * + * History: + * + * Notes: + * +******************************************************************************/ + +#ifndef __AT_UTIL_H__ +#define __AT_UTIL_H__ + +#include "cms_util.h" +#include "cms_comm.h" +#include "at_def.h" +#include "atc_reply.h" +#include "atc_decoder.h" + +#define ALI_SHA1_KEY_IOPAD_SIZE (64) +#define ALI_SHA1_DIGEST_SIZE (20) + +#define ALI_SHA256_KEY_IOPAD_SIZE (64) +#define ALI_SHA256_DIGEST_SIZE (32) + +#define ALI_MD5_KEY_IOPAD_SIZE (64) +#define ALI_MD5_DIGEST_SIZE (16) + +#define ALI_HMAC_USED (1) +#define ALI_HMAC_NOT_USED (0) + +typedef enum +{ + AT_PARA_OK = 0, + AT_PARA_ERR, + AT_PARA_DEFAULT, + AT_PARA_MAX, +}_AtParaRet; + +typedef INT32 AtParaRet; + + +/****************************************************************************** + ***************************************************************************** + * STRUCT + ***************************************************************************** +******************************************************************************/ + +/****************************************************************************** + * CmiCnfFuncMapList + * "CamCmiCnf" handler table +******************************************************************************/ +typedef CmsRetId (*CmiCnfHandler)(UINT16 reqHandle, UINT16 rc, void *paras); +typedef struct CmiCnfFuncMapList_Tag +{ + UINT16 primId; + CmiCnfHandler cmiCnfHdr; +}CmiCnfFuncMapList; + +/****************************************************************************** + * CmiIndFuncMapList + * "CamCmiInd" handler table +******************************************************************************/ +typedef void (*CmiIndHandler)(void *paras); +typedef struct CmiIndFuncMapList_Tag +{ + UINT16 primId; + CmiIndHandler cmiIndHdr; +}CmiIndFuncMapList; + +/****************************************************************************** + * ApplCnfFuncMapList + * "applCmsCnf" handler table +******************************************************************************/ +typedef CmsRetId (*ApplCnfHandler)(UINT16 reqHandle, UINT16 rc, void *paras); +typedef struct CmsCnfFuncMapList_Tag +{ + UINT16 primId; + ApplCnfHandler applCnfHdr; +}ApplCnfFuncMapList; + +/****************************************************************************** + * ApplIndFuncMapList + * "applCmsInd" handler table +******************************************************************************/ +typedef CmsRetId (*ApplIndHandler)(UINT16 indHandle, void *paras); +typedef struct CmsIndFuncMapList_Tag +{ + UINT16 primId; + ApplIndHandler applIndHdr; +}ApplIndFuncMapList; + +/****************************************************************************** + ***************************************************************************** + * FUNCTION/API + ***************************************************************************** +******************************************************************************/ +void atByteToBitString(UINT8 *outString, UINT8 n, UINT8 strlen); +BOOL atDataToHexString(UINT8* outString, UINT8* rawData, INT32 rawDataLen); +void atDataToDecString(UINT8 *outString, UINT8 outStringLen, INT64 rawData); + +AtParaRet atGetNumValue(AtParamValueCP pAtParaList, + UINT32 index, + INT32 *pOutValue, + INT32 minValue, + INT32 maxValue, + INT32 defaultValue); + +AtParaRet atGetStrValue(AtParamValueCP pAtParaList, + UINT32 index, + UINT8 *pOutStr, + UINT16 maxOutBufLen, + UINT16 *pOutStrLen, + const CHAR *pDefaultStr); + +BOOL atBeEmptyStrParam(AtParamValueCP pAtParaList, UINT32 index); + +AtParaRet atGetJsonStrValue(AtParamValueCP pAtParaList, + UINT32 index, + UINT8 *pOutStr, + UINT16 maxOutBufLen, + UINT16 *pOutStrLen, + const CHAR *pDefaultStr); + +AtParaRet atGetMixValue(AtParamValueCP pAtParaList, + UINT32 index, + UINT32 *extValType, + UINT8 *pOutStr, + UINT16 maxOutBufLen, + UINT16 *pOutStrLen, + const CHAR *pDefaultStr, + INT32 *pOutValue, + INT32 minValue, + INT32 maxValue, + INT32 defaultValue); + +AtParaRet atGetLastMixStrValue(AtParamValueCP pAtParaList, + UINT32 index, + UINT8 *pOutStr, + UINT16 maxOutBufLen, + UINT16 *pOutStrLen, + const CHAR *pDefaultStr); + +AtParaRet atGetStrLength(AtParamValueCP pAtParaList, + UINT32 index, + UINT16 *pOutStrLen); + +BOOL atBeNumericString(const UINT8 *password); + +AtParaRet atCheckParaDefaultFlag(const AtCmdInputContext *pAtCmdReqParaPtr, UINT32 index); + +BOOL atCheckBitFormat(const UINT8 *input); + +/* + * safe strncat +*/ +BOOL atStrnCat(CHAR *pDest, UINT32 destBufSize, CHAR *pNew, UINT32 catLen); + +void atSha256(const unsigned char *input, int ilen, unsigned char *output); + +void atAliHmacSha1(const unsigned char *input, int ilen, unsigned char *output,const unsigned char *key, int keylen); +void atAliHmacSha256(const unsigned char *input, int ilen, unsigned char *output,const unsigned char *key, int keylen); +void atAliHmacMd5(const unsigned char *input, int ilen, unsigned char *output,const unsigned char *key, int keylen); +BOOL atCheckApnName(UINT8 *apn,UINT16 len); + +/* + * +*/ +BOOL atPduInit(AtOutPdu *pAtPdu, UINT16 outSize); + +/* + * +*/ +BOOL atPduInitTryHeap(AtOutPdu *pAtPdu, UINT16 outSize); + + +/* +*/ +void atPduPrintf(AtOutPdu *pAtPdu, const CHAR *fmt, ...); + +/* + * +*/ +void atPduMemcat(AtOutPdu *pAtPdu, const UINT8 *pData, UINT16 dataLen); + + + +AtParaRet atGetDynamicHexStrValue(AtParamValueCP pAtParaList, + UINT32 index, + UINT8 **pOutStr, + UINT16 *OutLen); + + +#endif + diff --git a/PLAT/middleware/developed/at/atps/inc/atec_cmd_table.h b/PLAT/middleware/developed/at/atps/inc/atec_cmd_table.h new file mode 100644 index 0000000..9e3c23a --- /dev/null +++ b/PLAT/middleware/developed/at/atps/inc/atec_cmd_table.h @@ -0,0 +1,27 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC_CONTROLLER_H +#define _ATEC_CONTROLLER_H +#include "at_util.h" + + +AtCmdPreDefInfoC* atcGetATCommandsSeqPointer(void); +UINT32 atcGetATCommandsSeqNumb(void); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atps/inc/atec_dev.h b/PLAT/middleware/developed/at/atps/inc/atec_dev.h new file mode 100644 index 0000000..63b0fbb --- /dev/null +++ b/PLAT/middleware/developed/at/atps/inc/atec_dev.h @@ -0,0 +1,405 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef _ATEC__DEV_H +#define _ATEC__DEV_H + +#include "at_util.h" + +/* AT+CFUN */ +#define ATC_CFUN_0_FUN_VAL_MIN 0 +#define ATC_CFUN_0_FUN_VAL_MAX 4 +#define ATC_CFUN_0_FUN_VAL_DEFAULT 1 +#define ATC_CFUN_1_RST_VAL_MIN 0 +#define ATC_CFUN_1_RST_VAL_MAX 1 +#define ATC_CFUN_1_RST_VAL_DEFAULT 0 + + +/* AT+ECBAND */ +#define ATC_ECBAND_0_NW_MODE_VAL_DEFAULT 2 +#define ATC_ECBAND_1_BAND_VAL_MIN 0 +#define ATC_ECBAND_1_BAND_VAL_MAX 85 +#define ATC_ECBAND_1_BAND_VAL_DEFAULT 0 + +/* AT+ECFREQ */ +#define ATC_ECFREQ_0_NW_MODE_VAL_MIN 0 +#define ATC_ECFREQ_0_NW_MODE_VAL_MAX 3 +#define ATC_ECFREQ_0_NW_MODE_VAL_DEFAULT 0 +#define ATC_ECFREQ_1_EARFCN_VAL_MIN 0 +#define ATC_ECFREQ_1_EARFCN_VAL_MAX 0x7FFFFFFF +#define ATC_ECFREQ_1_EARFCN_VAL_DEFAULT 0 +#define ATC_ECFREQ_2_PHYCELL_VAL_MIN 0 +#define ATC_ECFREQ_2_PHYCELL_VAL_MAX 503 +#define ATC_ECFREQ_2_PHYCELL_VAL_DEFAULT 0 + +/* AT+ECCGSN */ +#define ATC_CGSN_0_MAX_PARM_STR_LEN 16 +#define ATC_CGSN_0_MAX_PARM_STR_DEFAULT NULL +#define ATC_CGSN_1_MAX_PARM_STR_LEN 32 +#define ATC_CGSN_1_MAX_PARM_STR_DEFAULT NULL + +/* AT+ECCGSNLOCK */ +#define ATC_ECCGSNLOCK_0_IMEI_STR_LEN 16 +#define ATC_ECCGSNLOCK_0_IMEI_STR_DEFAULT "imeiLock" +#define ATC_ECCGSNLOCK_0_SN_STR_LEN 16 +#define ATC_ECCGSNLOCK_0_SN_STR_DEFAULT "snLock" + + +/* AT+CIOTPOWER */ +#define ATC_CIOTPOWER_0_VAL_MIN 0 +#define ATC_CIOTPOWER_0_VAL_MAX 2 +#define ATC_CIOTPOWER_0_VAL_DEFAULT 0 + + +/* AT+ECCFG */ +#define ATC_ECCFG_0_MAX_PARM_STR_LEN 32 +#define ATC_ECCFG_0_MAX_PARM_STR_DEFAULT NULL +#define ATC_ECCFG_1_GCFTEST_VAL_MIN 0 +#define ATC_ECCFG_1_GCFTEST_VAL_MAX 1 +#define ATC_ECCFG_1_GCFTEST_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_AUTOAPN_VAL_MIN 0 +#define ATC_ECCFG_1_AUTOAPN_VAL_MAX 1 +#define ATC_ECCFG_1_AUTOAPN_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_SUPPORTSMS_VAL_MIN 0 +#define ATC_ECCFG_1_SUPPORTSMS_VAL_MAX 1 +#define ATC_ECCFG_1_SUPPORTSMS_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_TAUFORSMS_VAL_MIN 0 +#define ATC_ECCFG_1_TAUFORSMS_VAL_MAX 1 +#define ATC_ECCFG_1_TAUFORSMS_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_T3324_VAL_MIN 0 +#define ATC_ECCFG_1_T3324_VAL_MAX 0xFFFFFF +#define ATC_ECCFG_1_T3324_VAL_DEFAULT 0xFFFFFF +#define ATC_ECCFG_1_BAR_VAL_MIN 1 +#define ATC_ECCFG_1_BAR_VAL_MAX 600 +#define ATC_ECCFG_1_BAR_VAL_DEFAULT 120 +#define ATC_ECCFG_1_SIMTEST_VAL_MIN 0 +#define ATC_ECCFG_1_SIMTEST_VAL_MAX 1 +#define ATC_ECCFG_1_SIMTEST_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_USIMSIMULATOR_VAL_MIN 0 +#define ATC_ECCFG_1_USIMSIMULATOR_VAL_MAX 1 +#define ATC_ECCFG_1_USIMSIMULATOR_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_SUPPORTUPRAI_VAL_MIN 0 +#define ATC_ECCFG_1_SUPPORTUPRAI_VAL_MAX 1 +#define ATC_ECCFG_1_SUPPORTUPRAI_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_DIT_VAL_MIN 0 +#define ATC_ECCFG_1_DIT_VAL_MAX 0xff +#define ATC_ECCFG_1_DIT_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_RMD_VAL_MIN 0 +#define ATC_ECCFG_1_RMD_VAL_MAX 17 +#define ATC_ECCFG_1_RMD_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_POWERLEVEL_VAL_MIN 0 +#define ATC_ECCFG_1_POWERLEVEL_VAL_MAX 4 +#define ATC_ECCFG_1_POWERLEVEL_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_REL_VERSION_VAL_MIN 13 +#define ATC_ECCFG_1_REL_VERSION_VAL_MAX 14 +#define ATC_ECCFG_1_REL_VERSION_VAL_DEFAULT 13 +#define ATC_ECCFG_1_ROHC_VAL_MIN 0 +#define ATC_ECCFG_1_ROHC_VAL_MAX 1 +#define ATC_ECCFG_1_ROHC_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_EPCO_VAL_MIN 0 +#define ATC_ECCFG_1_EPCO_VAL_MAX 1 +#define ATC_ECCFG_1_EPCO_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_MULTICARRIER_VAL_MIN 0 +#define ATC_ECCFG_1_MULTICARRIER_VAL_MAX 1 +#define ATC_ECCFG_1_MULTICARRIER_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_MULTITONE_VAL_MIN 0 +#define ATC_ECCFG_1_MULTITONE_VAL_MAX 1 +#define ATC_ECCFG_1_MULTITONE_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_IPV6RSFORTESTSIM_VAL_MIN 0 +#define ATC_ECCFG_1_IPV6RSFORTESTSIM_VAL_MAX 1 +#define ATC_ECCFG_1_IPV6RSFORTESTSIM_VAL_DEFAULT (-1) +#define ATC_ECCFG_1_POWERCFUN_VAL_MIN 0 +#define ATC_ECCFG_1_POWERCFUN_VAL_MAX 4 +#define ATC_ECCFG_1_POWERCFUN_VAL_DEFAULT 1 //CFUN1 +#define ATC_ECCFG_1_PSPOWERONMAXDEALY_VAL_MIN 0 +#define ATC_ECCFG_1_PSPOWERONMAXDEALY_VAL_MAX 0xFFFF +#define ATC_ECCFG_1_PSPOWERONMAXDEALY_VAL_DEFAULT 0 +#define ATC_ECCFG_1_IPV6RSDELAY_VAL_MIN 0 +#define ATC_ECCFG_1_IPV6RSDELAY_VAL_MAX 65535 +#define ATC_ECCFG_1_IPV6RSDELAY_VAL_DEFAULT (15) +#define ATC_ECCFG_1_DISABLENCELLMEAS_VAL_MIN (0) +#define ATC_ECCFG_1_DISABLENCELLMEAS_VAL_MAX (1) +#define ATC_ECCFG_1_DISABLENCELLMEAS_VAL_DEFAULT (0) +#define ATC_ECCFG_1_UECATEGORY_VAL_MIN (1) +#define ATC_ECCFG_1_UECATEGORY_VAL_MAX (2) //1 - CAT1, 2 - CAT1 bis +#define ATC_ECCFG_1_UECATEGORY_VAL_DEFAULT (1) + +#define ATC_ECCFG_1_PSSOFTRESET_VAL_MIN (0) +#define ATC_ECCFG_1_PSSOFTRESET_VAL_MAX (1) +#define ATC_ECCFG_1_PSSOFTRESET_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_ENABLEEAB_VAL_MIN (0) +#define ATC_ECCFG_1_ENABLE_VAL_MAX (1) +#define ATC_ECCFG_1_ENABLE_VAL_DEFAULT (1) + +#define ATC_ECCFG_1_ENABLEABCHECK_VAL_MIN (0) +#define ATC_ECCFG_1_ENABLEABCHECK_VAL_MAX (1) +#define ATC_ECCFG_1_ENABLEABCHECK_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_WEAKCELLOPT_VAL_MIN (0) +#define ATC_ECCFG_1_WEAKCELLOPT_VAL_MAX (1) +#define ATC_ECCFG_1_WEAKCELLOPT_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_QRXLEVMIN_VAL_MIN (-156) +#define ATC_ECCFG_1_QRXLEVMIN_VAL_MAX (0) +#define ATC_ECCFG_1_QRXLEVMIN_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_RESELTOWEAKNCELLOPT_VAL_MIN (0) +#define ATC_ECCFG_1_RESELTOWEAKNCELLOPT_VAL_MAX (100) +#define ATC_ECCFG_1_RESELTOWEAKNCELLOPT_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_ATTACHBEARERCID_VAL_MIN (1) +#define ATC_ECCFG_1_ATTACHBEARERCID_VAL_MAX (15) +#define ATC_ECCFG_1_ATTACHBEARERCID_VAL_DEFAULT (1) + +#define ATC_ECCFG_1_TCPTPTOPT_VAL_MIN 0 +#define ATC_ECCFG_1_TCPTPTOPT_VAL_MAX 2 +#define ATC_ECCFG_1_TCPTPTOPT_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_POWER_ATTACH_WITH_IMSI_VAL_MIN (0) +#define ATC_ECCFG_1_POWER_ATTACH_WITH_IMSI_VAL_MAX (1) +#define ATC_ECCFG_1_POWER_ATTACH_WITH_IMSI_VAL_DEFAULT (1) + +#define ATC_ECCFG_1_POWER_ATTACH_WITHOUT_EIA_VAL_MIN (0) +#define ATC_ECCFG_1_POWER_ATTACH_WITHOUT_EIA_VAL_MAX (1) +#define ATC_ECCFG_1_POWER_ATTACH_WITHOUT_EIA_VAL_DEFAULT (1) + + +#define ATC_ECCFG_1_DATACOUNTER_VAL_MIN (0) +#define ATC_ECCFG_1_DATACOUNTER_VAL_MAX (1) +#define ATC_ECCFG_1_DATACOUNTER_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_UPDATE_LOCI_CTRL_VAL_MIN (0) +#define ATC_ECCFG_1_UPDATE_LOCI_CTRL_VAL_MAX (1) +#define ATC_ECCFG_1_UPDATE_LOCI_CTRL_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_ROAM_MODE_VAL_MIN (1) +#define ATC_ECCFG_1_ROAM_MODE_VAL_MAX (255) +#define ATC_ECCFG_1_ROAM_MODE_VAL_DEFAULT (2) +#define ATC_ECCFG_2_ROAM_MODE_EFFECT_VAL_MIN (0) +#define ATC_ECCFG_2_ROAM_MODE_EFFECT_VAL_MAX (1) +#define ATC_ECCFG_2_ROAM_MODE_EFFECT_VAL_DEFAULT (1) + +#define ATC_ECCFG_1_SAVE_PLMN_SEL_MODE_VAL_MIN (0) +#define ATC_ECCFG_1_SAVE_PLMN_SEL_MODE_VAL_MAX (1) +#define ATC_ECCFG_1_SAVE_PLMN_SEL_MODE_VAL_DEFAULT (1) + +#define ATC_ECCFG_1_EMERGENCY_CAMP_VAL_MIN (0) +#define ATC_ECCFG_1_EMERGENCY_CAMP_VAL_MAX (1) +#define ATC_ECCFG_1_EMERGENCY_CAMP_VAL_DEFAULT (0) + +#define ATC_ECCFG_1_ACL_VAL_MIN (0) +#define ATC_ECCFG_1_ACL_VAL_MAX (1) +#define ATC_ECCFG_1_ACL_VAL_DEF (0) + +#define ATC_ECCFG_1_PDPREMAP_VAL_MIN (0) +#define ATC_ECCFG_1_PDPREMAP_VAL_MAX (2) +#define ATC_ECCFG_1_PDPREMAP_VAL_DEF (0) + +#define ATC_ECCFG_1_PDPREACT_VAL_MIN (0) +#define ATC_ECCFG_1_PDPREACT_VAL_MAX (1) +#define ATC_ECCFG_1_PDPREACT_VAL_DEF (0) + + + +#define ATEC_ECCFG_GET_RSP_STR_LEN 512 + +/* AT+ECSTATUS */ +#define ATC_ECSTATUS_0_MAX_PARM_STR_LEN 16 +#define ATC_ECSTATUS_0_MAX_PARM_STR_DEFAULT NULL + + +/* AT+ECRMFPLMN */ +#define ATC_ECRMFPLMN_0_VAL_MIN 0 +#define ATC_ECRMFPLMN_0_VAL_MAX 2 +#define ATC_ECRMFPLMN_0_VAL_DEFAULT 0 + +/*AT+ECBCINFO*/ +#define ATC_ECBCINFO_0_VAL_MIN 0 +#define ATC_ECBCINFO_0_VAL_MAX 2 +#define ATC_ECBCINFO_0_VAL_DEFAULT 0 + +#define ATC_ECBCINFO_1_VAL_MIN 4 +#define ATC_ECBCINFO_1_VAL_MAX 300 /*timeout, MAX: 5 mins*/ +#define ATC_ECBCINFO_1_VAL_DEFAULT 8 /*default: 8s*/ + +#define ATC_ECBCINFO_2_VAL_MIN 0 +#define ATC_ECBCINFO_2_VAL_MAX 1 /*save_for_later*/ +#define ATC_ECBCINFO_2_VAL_DEFAULT 0 /*not need to save*/ + +#define ATC_ECBCINFO_3_VAL_MIN 1 /*max_cell_number*/ +#define ATC_ECBCINFO_3_VAL_MAX 7 /*max_cell_number, 1 serving cell + 6 neighber cell */ +#define ATC_ECBCINFO_3_VAL_DEFAULT 7 + +#define ATC_ECBCINFO_4_VAL_MIN 0 /*report mode, 0 - report in AT response */ +#define ATC_ECBCINFO_4_VAL_MAX 1 /*report mode, 1 - report in URC response */ +#define ATC_ECBCINFO_4_VAL_DEFAULT 0 + + + +/* AT+CMAR */ +#define ATC_CMAR_0_VAL_MIN 0 +#define ATC_CMAR_0_VAL_MAX 2 +#define ATC_CMAR_0_VAL_DEFAULT 0 + +/* AT+CMOLR */ +#define ATC_CMOLR_0_ENABLE_VAL_MIN 0 +#define ATC_CMOLR_0_ENABLE_VAL_MAX 3 +#define ATC_CMOLR_0_ENABLE_VAL_DEFAULT 0 +#define ATC_CMOLR_1_METHOD_VAL_MIN 0 +#define ATC_CMOLR_1_METHOD_VAL_MAX 6 +#define ATC_CMOLR_1_METHOD_VAL_DEFAULT 0 +#define ATC_CMOLR_2_HORACCSET_VAL_MIN 0 +#define ATC_CMOLR_2_HORACCSET_VAL_MAX 1 +#define ATC_CMOLR_2_HORACCSET_VAL_DEFAULT 0 +#define ATC_CMOLR_3_HORACC_VAL_MIN 0 +#define ATC_CMOLR_3_HORACC_VAL_MAX 127 +#define ATC_CMOLR_3_HORACC_VAL_DEFAULT 0 +#define ATC_CMOLR_4_VERREQ_VAL_MIN 0 +#define ATC_CMOLR_4_VERREQ_VAL_MAX 1 +#define ATC_CMOLR_4_VERREQ_VAL_DEFAULT 0 +#define ATC_CMOLR_5_VERACCSET_VAL_MIN 0 +#define ATC_CMOLR_5_VERACCSET_VAL_MAX 1 +#define ATC_CMOLR_5_VERACCSET_VAL_DEFAULT 0 +#define ATC_CMOLR_6_VERACC_VAL_MIN 0 +#define ATC_CMOLR_6_VERACC_VAL_MAX 127 +#define ATC_CMOLR_6_VERACC_VAL_DEFAULT 0 +#define ATC_CMOLR_7_VELREQ_VAL_MIN 0 +#define ATC_CMOLR_7_VELREQ_VAL_MAX 4 +#define ATC_CMOLR_7_VELREQ_VAL_DEFAULT 0 +#define ATC_CMOLR_8_REQMODE_VAL_MIN 0 +#define ATC_CMOLR_8_REQMODE_VAL_MAX 1 +#define ATC_CMOLR_8_REQMODE_VAL_DEFAULT 0 +#define ATC_CMOLR_9_TIMEOUT_VAL_MIN 0 +#define ATC_CMOLR_9_TIMEOUT_VAL_MAX 65535 +#define ATC_CMOLR_9_TIMEOUT_VAL_DEFAULT 0 +#define ATC_CMOLR_10_INTERVAL_VAL_MIN 0 +#define ATC_CMOLR_10_INTERVAL_VAL_MAX 65535 +#define ATC_CMOLR_10_INTERVAL_VAL_DEFAULT 0 +#define ATC_CMOLR_11_SHAPEREQ_VAL_MIN 1 +#define ATC_CMOLR_11_SHAPEREQ_VAL_MAX 64 +#define ATC_CMOLR_11_SHAPEREQ_VAL_DEFAULT 0 +#define ATC_CMOLR_12_PLANE_VAL_MIN 0 +#define ATC_CMOLR_12_PLANE_VAL_MAX 1 +#define ATC_CMOLR_12_PLANE_VAL_DEFAULT 0 +#define ATC_CMOLR_13_NMEAREQ_STR_DEFAULT NULL +#define ATC_CMOLR_13_NMEAREQ_STR_MAX_LEN 16 +#define ATC_CMOLR_14_THIRDPARTYADDR_STR_DEFAULT NULL +#define ATC_CMOLR_14_THIRDPARTYADDR_STR_MAX_LEN 16 + +/* AT+CMTLR */ +#define ATC_CMTLR_0_VAL_MIN 0 +#define ATC_CMTLR_0_VAL_MAX 3 +#define ATC_CMTLR_0_VAL_DEFAULT 0 + +/* AT+CMTLRA */ +#define ATC_CMTLRA_0_VAL_MIN 0 +#define ATC_CMTLRA_0_VAL_MAX 1 +#define ATC_CMTLRA_0_VAL_DEFAULT 0 +#define ATC_CMTLRA_1_VAL_MIN 0 +#define ATC_CMTLRA_1_VAL_MAX 255 +#define ATC_CMTLRA_1_VAL_DEFAULT 0 + +/*AT+ECSTATIS*/ +#define ATC_ESTATIS_0_VAL_MIN 0 +#define ATC_ESTATIS_0_VAL_MAX 600 +#define ATC_ESTATIS_0_VAL_DEFAULT 0 + +/*AT+ECCGSN*/ +#define ATC_ECCGSN_MAX_PARM_STR_LEN 8 +#define ATC_ECCGSN_MAX_PARM_STR_DEFAULT NULL + +/* AT+ECPSTEST */ +#define ATC_ECPSTEST_VAL_MIN 0 +#define ATC_ECPSTEST_VAL_MAX 1 +#define ATC_ECPSTEST_VAL_DEFAULT 0 + +/* AT+ECPOWERCLASS */ +#define ATC_ECPOWERCLASS_1_VAL_MIN 0 +#define ATC_ECPOWERCLASS_1_VAL_MAX 85 +#define ATC_ECPOWERCLASS_1_VAL_DEFAULT 0 + +#define ATC_ECPOWERCLASS_2_VAL_MIN 3 +#define ATC_ECPOWERCLASS_2_VAL_MAX 6 +#define ATC_ECPOWERCLASS_2_VAL_DEFAULT 3 + +/* AT+ECEVENTSTATIS */ +#define ATC_ECEVENTSTATIS_1_VAL_MIN 0 +#define ATC_ECEVENTSTATIS_1_VAL_MAX 2 +#define ATC_ECEVENTSTATIS_1_VAL_DEFAULT 0 + +/* AT+ECNASTCFG */ +#define ATC_ECNASTCFG_0_VAL_MIN 0 +#define ATC_ECNASTCFG_0_VAL_MAX 2 +#define ATC_ECNASTCFG_0_VAL_DEF (ATC_ECNASTCFG_0_VAL_MIN) + +#define ATC_ECNASTCFG_1_VAL_MIN 0 +#define ATC_ECNASTCFG_1_VAL_MAX 0xFFFFF +#define ATC_ECNASTCFG_1_VAL_DEF 0 + +#define ATC_ECNASTCFG_2_VAL_MIN 0 +#define ATC_ECNASTCFG_2_VAL_MAX 255 +#define ATC_ECNASTCFG_2_VAL_DEF 0 + +/* AT+ECWIFISCAN */ +#define ATC_ECWIFISCAN_0_TIME_VAL_MIN 4000 +#define ATC_ECWIFISCAN_0_TIME_VAL_MAX 255000 +#define ATC_ECWIFISCAN_0_TIME_VAL_DEF 12000 + +#define ATC_ECWIFISCAN_1_ROUND_VAL_MIN 1 +#define ATC_ECWIFISCAN_1_ROUND_VAL_MAX 3 +#define ATC_ECWIFISCAN_1_ROUND_VAL_DEF 1 + +#define ATC_ECWIFISCAN_2_MAXBSSIDNUM_VAL_MIN 4 +#define ATC_ECWIFISCAN_2_MAXBSSIDNUM_VAL_MAX 10 +#define ATC_ECWIFISCAN_2_MAXBSSIDNUM_VAL_DEF 5 + +#define ATC_ECWIFISCAN_3_SCANTIMEOUT_VAL_MIN 1 +#define ATC_ECWIFISCAN_3_SCANTIMEOUT_VAL_MAX 255 +#define ATC_ECWIFISCAN_3_SCANTIMEOUT_VAL_DEF 5 + +#define ATC_ECWIFISCAN_4_PRIORITY_VAL_MIN 0 //data preferred +#define ATC_ECWIFISCAN_4_PRIORITY_VAL_MAX 1 //wifiscan preferred +#define ATC_ECWIFISCAN_4_PRIORITY_VAL_DEF 0 + + +CmsRetId devCFUN(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECBAND(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECFREQ(const AtCmdInputContext *pAtCmdReq); +//CmsRetId devCGSN(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECCGSN(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECCGSNLOCK(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECRMFPLMN(const AtCmdInputContext *pAtCmdReq); +CmsRetId devCMAR(const AtCmdInputContext *pAtCmdReq); +CmsRetId devCMOLR(const AtCmdInputContext *pAtCmdReq); +CmsRetId devCMTLR(const AtCmdInputContext *pAtCmdReq); +CmsRetId devCMTLRA(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECSTATUS(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECSTATIS(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECBCINFO(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECWIFISCAN(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECPSTEST(const AtCmdInputContext *pAtCmdReq); +//CmsRetId devECPOWERCLASS(const AtCmdInputContext *pAtCmdReq); +CmsRetId devECEVENTSTATIS(const AtCmdInputContext *pAtCmdReq); +//extern void atCmdResetSystem(uint8_t atCid, uint32_t delayMs); + + +CmsRetId devECNASTCFG(const AtCmdInputContext *pAtCmdReq); + + +#endif + diff --git a/PLAT/middleware/developed/at/atps/inc/atec_general.h b/PLAT/middleware/developed/at/atps/inc/atec_general.h new file mode 100644 index 0000000..dcfda65 --- /dev/null +++ b/PLAT/middleware/developed/at/atps/inc/atec_general.h @@ -0,0 +1,167 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_general.h +* +* Description: +* +* History: +* +* Notes: +* +******************************************************************************/ +#ifndef __ATEC_PLAT_H__ +#define __ATEC_PLAT_H__ + + +#include +#include "at_util.h" + +#include DEBUG_LOG_HEADER_FILE +#include "debug_trace.h" + +/* ATE */ +#define ATC_E_0_VAL_MIN 0 +#define ATC_E_0_VAL_MAX 1 +#define ATC_E_0_VAL_DEFAULT 0 + +/* ATQ */ +#define ATC_Q_0_VAL_MIN 0 +#define ATC_Q_0_VAL_MAX 1 +#define ATC_Q_0_VAL_DEFAULT 0 + +/* ATV */ +#define ATC_V_0_VAL_MIN 1 +#define ATC_V_0_VAL_MAX 1 +#define ATC_V_0_VAL_DEFAULT 1 + +/* ATL */ +#define ATC_L_0_VAL_MIN 0 +#define ATC_L_0_VAL_MAX 3 +#define ATC_L_0_VAL_DEFAULT 0 + +/* ATM */ +#define ATC_M_0_VAL_MIN 0 +#define ATC_M_0_VAL_MAX 2 +#define ATC_M_0_VAL_DEFAULT 0 + +/* ATS0 */ +#define ATC_S0_0_VAL_MIN 0 +#define ATC_S0_0_VAL_MAX 255 +#define ATC_S0_0_VAL_DEFAULT 0 + +/* AT&C */ +#define ATC_AND_C_0_VAL_MIN 0 +#define ATC_AND_C_0_VAL_MAX 1 +#define ATC_AND_C_0_VAL_DEFAULT 1 + +/* AT&D */ +#define ATC_AND_D_0_VAL_MIN 0 +#define ATC_AND_D_0_VAL_MAX 2 +#define ATC_AND_D_0_VAL_DEFAULT 2 + + +/* ATD */ +#define ATC_D_ALL_STR_MAX_LEN 64 +#define ATC_D_GPRS_SC_STR_MAX_LEN 2 +#define ATC_D_CALLED_ADDR_STR_MAX_LEN 15 +#define ATC_D_L2P_STR_MAX_LEN 3 +#define ATC_D_CID_STR_MAX_LEN 2 +#define ATC_D_STR_DEFAULT NULL + +/* ATO */ +#define ATC_O_0_VAL_MIN 0 +#define ATC_O_0_VAL_MAX 0 +#define ATC_O_0_VAL_DEFAULT 0 + +/* ATH */ +#define ATC_H_0_VAL_MIN 0 +#define ATC_H_0_VAL_MAX 0 +#define ATC_H_0_VAL_DEFAULT 0 + + +/* AT+CGMI */ +#define ATC_CGMI_0_VAL_MIN 0 +#define ATC_CGMI_0_VAL_MAX 2 +#define ATC_CGMI_0_VAL_DEFAULT 0 + +/* AT+CGMM */ +#define ATC_CGMM_0_VAL_MIN 0 +#define ATC_CGMM_0_VAL_MAX 2 +#define ATC_CGMM_0_VAL_DEFAULT 0 + +/* AT+CSCS */ +#define ATC_CSCS_0_VAL_MIN 0 +#define ATC_CSCS_0_VAL_MAX 2 +#define ATC_CSCS_0_VAL_DEFAULT 0 + +/* AT+CMUX */ +#define ATC_CMUX_0_VAL_MIN 0 +#define ATC_CMUX_0_VAL_MAX 2 +#define ATC_CMUX_0_VAL_DEFAULT 0 + +/* AT+CMEE */ +#define ATC_CMEE_0_VAL_MIN 0 +#define ATC_CMEE_0_VAL_MAX 2 +#define ATC_CMEE_0_VAL_DEFAULT 0 + +/* AT+CSCS */ +#define ATC_CSCS_0_STR_MAX_LEN 10 +#define ATC_CSCS_0_STR_DEFAULT NULL + +/* AT+ECURC */ +#define ATC_ECURC_0_MAX_PARM_STR_LEN 16 +#define ATC_ECURC_0_MAX_PARM_STR_DEFAULT NULL +#define ATC_ECURC_1_VAL_MIN 0 +#define ATC_ECURC_1_VAL_MAX 1 +#define ATC_ECURC_1_VAL_DEFAULT 0 +#define ATC_ECURC_GET_RSP_STR_LEN 128 + +/* AT+ECURCCFG */ +#define ATC_ECURCCFG_0_MAX_PARM_STR_LEN 32 +#define ATC_ECURCCFG_0_MAX_PARM_STR_DEFAULT NULL +#define ATC_ECURCCFG_1_TYPE_VAL_MIN 0 +#define ATC_ECURCCFG_1_TYPE_VAL_MAX 1 +#define ATC_ECURCCFG_1_TYPE_VAL_DEFAULT 1 +#define ATC_ECURCCFG_1_DELAY_VAL_MIN 0 +#define ATC_ECURCCFG_1_DELAY_VAL_MAX 10000 +#define ATC_ECURCCFG_1_DELAY_VAL_DEFAULT 0 +#define ATC_ECURCCFG_1_CACHE_VAL_MIN 0 +#define ATC_ECURCCFG_1_CACHE_VAL_MAX 1 +#define ATC_ECURCCFG_1_CACHE_VAL_DEFAULT 0 +#define ATC_ECURCCFG_2_PULSE_DURATION_VAL_MIN 1 +#define ATC_ECURCCFG_2_PULSE_DURATION_VAL_MAX 2000 +#define ATC_ECURCCFG_2_PULSE_DURATION_VAL_DEFAULT 120 +#define ATC_ECURCCFG_3_PULSE_COUNT_VAL_MIN 1 +#define ATC_ECURCCFG_3_PULSE_COUNT_VAL_MAX 5 +#define ATC_ECURCCFG_3_PULSE_COUNT_VAL_DEFAULT 1 + + +CmsRetId gcAT(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATE(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATQ(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATT(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATV(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATL(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATM(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATS0(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcCGMI(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcCGMM(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcCSCS(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcCMUX(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcCMEE(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATANDC(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATANDD(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcECURC(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcECURCCFG(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATD(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATO(const AtCmdInputContext *pAtCmdReq); +CmsRetId gcATH(const AtCmdInputContext *pAtCmdReq); + +#endif + +/* END OF FILE */ diff --git a/PLAT/middleware/developed/at/atps/inc/atec_mm.h b/PLAT/middleware/developed/at/atps/inc/atec_mm.h new file mode 100644 index 0000000..2f2e315 --- /dev/null +++ b/PLAT/middleware/developed/at/atps/inc/atec_mm.h @@ -0,0 +1,257 @@ +/****************************************************************************** + +*(C) Copyright 2018 AirM2M International Ltd. + +* All Rights Reserved + +****************************************************************************** +* Filename: atec_mm.h +* +* Description: Macro definition for network service related AT commands +* +* History: +* +* Notes: +* +******************************************************************************/ + +#ifndef _ATEC_MM_H +#define _ATEC_MM_H + +/* AT+CREG */ +#define ATC_CREG_0_VAL_MIN 0 +#define ATC_CREG_0_VAL_MAX 3 +#define ATC_CREG_0_VAL_DEFAULT 0 + + +/* AT+CSQ */ +#define ATC_CSQ_0_VAL_MIN 0 +#define ATC_CSQ_0_VAL_MAX 2 +#define ATC_CSQ_0_VAL_DEFAULT 0 + +/* AT+COPS */ +#define ATC_COPS_0_MODE_VAL_MIN 0 +#define ATC_COPS_0_MODE_VAL_MAX 4 +#define ATC_COPS_0_MODE_VAL_DEFAULT 0 /* auto */ +#define ATC_COPS_1_FORMAT_VAL_MIN 0 +#define ATC_COPS_1_FORMAT_VAL_MAX 2 +#define ATC_COPS_1_FORMAT_VAL_DEFAULT 3 /* invalid */ +#define ATC_COPS_2_OPER_STR_DEFAULT NULL +#define ATC_COPS_2_OPER_STR_MAX_LEN 16 +#define ATC_COPS_3_ACT_VAL_MIN 7 +#define ATC_COPS_3_ACT_VAL_MAX 7 +#define ATC_COPS_3_ACT_VAL_DEFAULT 7 /* E-UTRAN */ +#define ATC_COPS_GUARD_TIMER 60 /* second */ + +/* save parameters for Manual PLMN select: AT+COPS=,,, */ +typedef struct AtcCopsManulSelectInfo_Tag +{ + UINT8 mode; + UINT8 format; + UINT8 act; + UINT8 plmnName[ATC_COPS_2_OPER_STR_MAX_LEN + CMS_NULL_CHAR_LEN]; +}AtcCopsManulSelectInfo; + +typedef struct AtcCopsInfo_Tag +{ + UINT8 plmnNum; + BOOL bPendingManulPlmnSelect; + AtcCopsManulSelectInfo manulSelectInfo; + CmiNumericPlmn *plmnList; +}AtcCopsInfo; + +/* AT+CESQ */ +#define ATC_CESQ_0_VAL_MIN 0 +#define ATC_CESQ_0_VAL_MAX 2 +#define ATC_CESQ_0_VAL_DEFAULT 0 + +/* AT+CPSMS */ +#define ATC_CPSMS_0_MODE_VAL_MIN 0 +#define ATC_CPSMS_0_MODE_VAL_MAX 2 +#define ATC_CPSMS_0_MODE_VAL_DEFAULT 0 +#define ATC_CPSMS_1_PRAU_STR_DEFAULT NULL +#define ATC_CPSMS_1_PRAU_STR_MAX_LEN 8 +#define ATC_CPSMS_2_GPRS_STR_DEFAULT NULL +#define ATC_CPSMS_2_GPRS_STR_MAX_LEN 8 +#define ATC_CPSMS_3_PTAU_STR_DEFAULT "00110100" /* default 20 hours */ +#define ATC_CPSMS_3_PTAU_STR_MAX_LEN 8 +#define ATC_CPSMS_4_ACT_STR_DEFAULT "00100101" /* default 5 minutes */ +#define ATC_CPSMS_4_ACT_STR_MAX_LEN 8 + +/* AT+CEDRXS */ +#define ATC_CEDRXS_0_MODE_VAL_MIN 0 +#define ATC_CEDRXS_0_MODE_VAL_MAX 3 +#define ATC_CEDRXS_0_MODE_VAL_DEFAULT 0 +#define ATC_CEDRXS_1_VAL_MIN 0 +#define ATC_CEDRXS_1_VAL_MAX 4 +#define ATC_CEDRXS_1_VAL_DEFAULT 4 +#define ATC_CEDRXS_2_STR_DEFAULT NULL +#define ATC_CEDRXS_2_STR_MAX_LEN 4 + +/* AT+CEDRXRDP */ +#define ATC_CEDRXRDP_0_VAL_MIN 0 +#define ATC_CEDRXRDP_0_VAL_MAX 2 +#define ATC_CEDRXRDP_0_VAL_DEFAULT 0 + +/* AT+CCIOTOPT */ +#define ATC_CCIOTOPT_0_VAL_MIN 0 +#define ATC_CCIOTOPT_0_VAL_MAX 3 +#define ATC_CCIOTOPT_0_VAL_DEFAULT 7 //CMI_MM_CIOT_OPT_RPT_MODE_NOT_PRESENT +#define ATC_CCIOTOPT_1_VAL_MIN 0 /* 0 - NO OPT, 1- CP, 2 - UP, 3-UP&CP */ +#define ATC_CCIOTOPT_1_VAL_MAX 3 +#define ATC_CCIOTOPT_1_VAL_DEFAULT 0 +#define ATC_CCIOTOPT_2_VAL_MIN 0 +#define ATC_CCIOTOPT_2_VAL_MAX 2 +#define ATC_CCIOTOPT_2_VAL_DEFAULT 0 + +/* AT+CCLK */ +#define ATC_CCLK_0_STR_DEFAULT NULL +#define ATC_CCLK_0_STR_MAX_LEN 32 + +/* AT+CTZR */ +#define ATC_CTZR_0_VAL_MIN 0 +#define ATC_CTZR_0_VAL_MAX 3 +#define ATC_CTZR_0_VAL_DEFAULT 0 + +/* + * 0 disable time zone change event reporting. + * 1 Enable time zone change event reporting by unsolicited result code +CTZV: . + * 2 Enable extended time zone and local time reporting by unsolicited result code + * +CTZE: ,,[