diff --git a/bittide/src/Bittide/DoubleBufferedRAM.hs b/bittide/src/Bittide/DoubleBufferedRAM.hs
index c18ce68ac..87deaf882 100644
--- a/bittide/src/Bittide/DoubleBufferedRAM.hs
+++ b/bittide/src/Bittide/DoubleBufferedRAM.hs
@@ -77,6 +77,8 @@ doubleBufferedRAMByteAddressable initialContent switch readAddr writeFrame byteS
 
     output = mux outputSelect buffer1 buffer0
 
+-- | Blockram similar to 'blockram' with the addition that it takes a byte select signal
+-- that controls which bytes at the write address are updated.
 blockRamByteAddressable ::
   forall dom bytes depth a .
   (HiddenClockResetEnable dom, KnownNat bytes, 1 <= bytes, bytes ~ Regs a 8, KnownNat depth, Paddable a) =>
@@ -95,6 +97,8 @@ blockRamByteAddressable initRAM readAddr newEntry byteSelect =
    writeBytes = unbundle $ splitWriteInBytes <$> newEntry <*> byteSelect
    readBytes = bundle $ (`blockRam` readAddr) <$> initBytes <*> writeBytes
 
+-- | Registor similar to 'register' with the addition that it takes a byte select signal
+-- that controls which bytes are updated.
 registerByteAddressable ::
   forall dom a .
   (HiddenClockResetEnable dom, Paddable a) =>
@@ -112,6 +116,10 @@ registerByteAddressable initVal newVal byteEnables =
     case paddedToRegisters @8 $ Padded x of
       RegisterBank vec -> vec
 
+
+-- | Takes singular write operation (Maybe (Index maxIndex, writeData)) and splits it up
+-- according to a supplied byteselect bitvector into a vector of byte sized write operations
+-- (Maybe (Index maxIndex, Byte)).
 splitWriteInBytes ::
   forall maxIndex writeData .
   (Paddable writeData) =>