From fcfcfcbf85a36bdcc5d87edcd14e0ca8b20985a2 Mon Sep 17 00:00:00 2001
From: Lucas Bollen <lucas@qbaylogic.com>
Date: Mon, 5 Aug 2024 16:37:42 +0200
Subject: [PATCH] Bump all clash dependencies to current master HEAD

Do note that we currently retain our local version of `PeriodToCycles`.
This version still has the `Max` types which greatly improves usability.
Related issue: https://github.com/clash-lang/ghc-typelits-extra/issues/56
---
 .../src/Bittide/Instances/Domains.hs          |  2 +-
 .../src/Bittide/Instances/Hitl/FincFdec.hs    |  1 -
 .../Bittide/Instances/Hitl/FullMeshHwCc.hs    |  2 +-
 .../Bittide/Instances/Hitl/FullMeshSwCc.hs    |  2 +-
 .../Bittide/Instances/Hitl/HwCcTopologies.hs  |  2 +-
 .../src/Bittide/Instances/Hitl/IlaPlot.hs     |  4 ++--
 .../Bittide/Instances/Hitl/SyncInSyncOut.hs   |  2 +-
 .../src/Bittide/Instances/Pnr/Si539xSpi.hs    |  1 -
 bittide/src/Bittide/Arithmetic/Time.hs        | 23 +++++--------------
 bittide/src/Bittide/ClockControl.hs           |  4 ++--
 bittide/src/Bittide/ClockControl/Si539xSpi.hs |  2 +-
 bittide/src/Bittide/Transceiver.hs            |  2 +-
 bittide/src/Bittide/Wishbone.hs               |  3 +--
 bittide/src/Clash/Cores/UART/Extra.hs         |  3 +--
 bittide/tests/Tests/Transceiver.hs            |  4 ++--
 cabal.project                                 | 14 ++++-------
 16 files changed, 26 insertions(+), 45 deletions(-)

diff --git a/bittide-instances/src/Bittide/Instances/Domains.hs b/bittide-instances/src/Bittide/Instances/Domains.hs
index 4a2800f27..f3106cd23 100644
--- a/bittide-instances/src/Bittide/Instances/Domains.hs
+++ b/bittide-instances/src/Bittide/Instances/Domains.hs
@@ -6,7 +6,7 @@
 
 module Bittide.Instances.Domains where
 
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 
 import Bittide.ClockControl
 import Bittide.Arithmetic.Time
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs b/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs
index 77eedc17b..54e22f1f4 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/FincFdec.hs
@@ -15,7 +15,6 @@ import Clash.Explicit.Prelude
 import Clash.Prelude (withClockResetEnable)
 import Clash.Xilinx.ClockGen (clockWizardDifferential)
 
-import Bittide.Arithmetic.Time
 import Bittide.Counter (domainDiffCounter)
 import Bittide.ClockControl (SpeedChange(NoChange, SlowDown, SpeedUp), speedChangeToFincFdec)
 import Bittide.ClockControl.Si539xSpi (si539xSpi, ConfigState(Finished))
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs
index c61ef8025..ef12c4e54 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs
@@ -33,7 +33,7 @@ module Bittide.Instances.Hitl.FullMeshHwCc
   ) where
 
 import Clash.Prelude (withClockResetEnable)
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 import qualified Clash.Explicit.Prelude as E
 
 import Data.Maybe (fromMaybe)
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
index d9ec7f332..6086465d5 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -32,7 +32,7 @@ module Bittide.Instances.Hitl.FullMeshSwCc
   ) where
 
 import Clash.Prelude (withClockResetEnable)
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 import qualified Clash.Explicit.Prelude as E
 
 import Data.Maybe (fromMaybe)
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs
index b000e3a9b..6983cbfa8 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs
@@ -34,7 +34,7 @@ module Bittide.Instances.Hitl.HwCcTopologies
   ) where
 
 import Clash.Prelude (withClockResetEnable)
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 import qualified Clash.Explicit.Prelude as E
 
 import Data.Bifunctor (bimap)
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs b/bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs
index ee92be046..93190a8aa 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs
@@ -47,11 +47,11 @@ module Bittide.Instances.Hitl.IlaPlot
 
 import GHC.Stack (HasCallStack)
 
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 import Clash.Explicit.Signal.Extra
 import Clash.Sized.Extra (concatUnsigneds)
 
-import Bittide.Arithmetic.Time (Seconds, Milliseconds, PeriodToCycles, trueFor)
+import Bittide.Arithmetic.Time (PeriodToCycles, trueFor)
 import Bittide.ClockControl (SpeedChange(..), DataCount, ClockControlConfig)
 import Bittide.ClockControl.Callisto
   (CallistoResult(..), ReframingState(..), callistoClockControl)
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SyncInSyncOut.hs b/bittide-instances/src/Bittide/Instances/Hitl/SyncInSyncOut.hs
index 3641f52bd..7a9e1d3ae 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/SyncInSyncOut.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/SyncInSyncOut.hs
@@ -62,7 +62,7 @@
 --
 module Bittide.Instances.Hitl.SyncInSyncOut where
 
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 
 import Bittide.Arithmetic.Time
 import Bittide.Hitl (HitlTests, allFpgas, hitlVioBool, noConfigTest)
diff --git a/bittide-instances/src/Bittide/Instances/Pnr/Si539xSpi.hs b/bittide-instances/src/Bittide/Instances/Pnr/Si539xSpi.hs
index a70d7ca29..811b36d65 100644
--- a/bittide-instances/src/Bittide/Instances/Pnr/Si539xSpi.hs
+++ b/bittide-instances/src/Bittide/Instances/Pnr/Si539xSpi.hs
@@ -11,7 +11,6 @@ import Clash.Prelude
 
 import Clash.Annotations.TH (makeTopEntity)
 
-import Bittide.Arithmetic.Time
 import Bittide.ClockControl
 import Bittide.ClockControl.Callisto
 import Bittide.ClockControl.Si5395J
diff --git a/bittide/src/Bittide/Arithmetic/Time.hs b/bittide/src/Bittide/Arithmetic/Time.hs
index 381b00ed7..e58798f26 100644
--- a/bittide/src/Bittide/Arithmetic/Time.hs
+++ b/bittide/src/Bittide/Arithmetic/Time.hs
@@ -5,7 +5,7 @@
 module Bittide.Arithmetic.Time where
 
 import GHC.Stack (HasCallStack)
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 
 import Clash.Class.Counter (countSucc, Counter)
 import Clash.Signal.Internal (Femtoseconds (Femtoseconds), mapFemtoseconds)
@@ -13,25 +13,14 @@ import Data.Data (Proxy)
 import Data.Int (Int64)
 import Data.Kind (Type)
 
--- | Gets time in 'Picoseconds' from time in 'Seconds'.
-type Seconds      (s  :: Nat) = Milliseconds (1000 * s)
--- | Gets time in 'Picoseconds' from time in 'Milliseconds'.
-type Milliseconds (ms :: Nat) = Microseconds (1000 * ms)
--- | Gets time in 'Picoseconds' from time in 'Microseconds'.
-type Microseconds (us :: Nat) = Nanoseconds  (1000 * us)
--- | Gets time in 'Picoseconds' from time in 'Nanoseconds'.
-type Nanoseconds  (ns :: Nat) = Picoseconds  (1000 * ns)
--- | Gets time in 'Picoseconds' from time in 'Picoseconds', essentially 'id'.
-type Picoseconds  (ps :: Nat) = ps
-
--- | Number of clock cycles required at the clock frequency of @dom@ before a minimum @period@ has passed.
+-- | XXX: We currently retain this in favor of @clash-prelude@s 'PeriodToCycles'
+-- until @1 <= DomainPeriod dom@ is trivially true. Related issue:
+-- https://github.com/clash-lang/ghc-typelits-extra/issues/56
+--
+--Number of clock cycles required at the clock frequency of @dom@ before a minimum @period@ has passed.
 -- Is always at least one.
 type PeriodToCycles dom period = Max 1 (DivRU period (Max 1 (DomainPeriod dom)))
 
--- | The domain's clock frequency in Hertz, calculated based on the period stored in ps.
--- This might lead to rounding errors.
-type DomainFrequency dom = Div (Seconds 1) (DomainPeriod dom)
-
 -- | 'Index' with its 'maxBound' corresponding to the number of cycles needed to
 -- wait for /n/ milliseconds.
 type IndexMs dom n = Index (PeriodToCycles dom (Milliseconds n))
diff --git a/bittide/src/Bittide/ClockControl.hs b/bittide/src/Bittide/ClockControl.hs
index 049a92892..56fcfb203 100644
--- a/bittide/src/Bittide/ClockControl.hs
+++ b/bittide/src/Bittide/ClockControl.hs
@@ -22,7 +22,7 @@ module Bittide.ClockControl
   )
 where
 
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude  hiding (PeriodToCycles)
 import Clash.Signal.Internal (Femtoseconds(..))
 import Data.Aeson (ToJSON(toJSON))
 import Data.Proxy (Proxy(..))
@@ -32,7 +32,7 @@ import Foreign.Storable (Storable(..))
 import GHC.Stack (HasCallStack)
 
 import Bittide.Arithmetic.Ppm
-import Bittide.Arithmetic.Time (PeriodToCycles, Nanoseconds, Microseconds, microseconds)
+import Bittide.Arithmetic.Time (PeriodToCycles, microseconds)
 import Bittide.ClockControl.Foreign.Sizes
 
 import Data.Csv
diff --git a/bittide/src/Bittide/ClockControl/Si539xSpi.hs b/bittide/src/Bittide/ClockControl/Si539xSpi.hs
index 0a16dc551..723af2101 100644
--- a/bittide/src/Bittide/ClockControl/Si539xSpi.hs
+++ b/bittide/src/Bittide/ClockControl/Si539xSpi.hs
@@ -11,7 +11,7 @@
 
 module Bittide.ClockControl.Si539xSpi where
 
-import Clash.Prelude
+import Clash.Prelude hiding (PeriodToCycles)
 import Clash.Cores.SPI
 
 import Data.Maybe
diff --git a/bittide/src/Bittide/Transceiver.hs b/bittide/src/Bittide/Transceiver.hs
index 74a847f66..6a17f027c 100644
--- a/bittide/src/Bittide/Transceiver.hs
+++ b/bittide/src/Bittide/Transceiver.hs
@@ -89,7 +89,7 @@ module Bittide.Transceiver where
 
 import Clash.Explicit.Prelude
 
-import Bittide.Arithmetic.Time (Milliseconds, trueForSteps)
+import Bittide.Arithmetic.Time (trueForSteps)
 import Bittide.ElasticBuffer (sticky)
 import Clash.Cores.Xilinx.GTH (GthCore)
 import Clash.Cores.Xilinx.Ila (IlaConfig(advancedTriggers, depth, stages), ilaConfig, ila, Depth(D1024))
diff --git a/bittide/src/Bittide/Wishbone.hs b/bittide/src/Bittide/Wishbone.hs
index 8fc276379..bcf382cf2 100644
--- a/bittide/src/Bittide/Wishbone.hs
+++ b/bittide/src/Bittide/Wishbone.hs
@@ -11,7 +11,6 @@ module Bittide.Wishbone where
 
 import Clash.Prelude
 
-import Bittide.Arithmetic.Time(DomainFrequency)
 import Bittide.DoubleBufferedRam
 import Bittide.SharedTypes
 
@@ -467,7 +466,7 @@ timeWb = Circuit $ \(wbM2S, _) -> (mealy goMealy (0,0) wbM2S, ())
  where
   goMealy (frozen, count :: Unsigned 64) wbM2S = ((nextFrozen, succ count), wbS2M)
        where
-    freq = natToNum @(DomainFrequency dom) :: Unsigned 64
+    freq = natToNum @(DomainToHz dom) :: Unsigned 64
     nextFrozen = if isJust (head writes) then count else frozen
     RegisterBank (splitAtI -> (frozenMsbs, frozenLsbs)) = getRegsBe @8 frozen
     RegisterBank (splitAtI -> (freqMsbs, freqLsbs)) = getRegsBe @8 freq
diff --git a/bittide/src/Clash/Cores/UART/Extra.hs b/bittide/src/Clash/Cores/UART/Extra.hs
index cf9e5c49a..6066fa0c6 100644
--- a/bittide/src/Clash/Cores/UART/Extra.hs
+++ b/bittide/src/Clash/Cores/UART/Extra.hs
@@ -20,13 +20,12 @@ import Protocols
 import Protocols.Df hiding (catMaybes, sample, pure)
 import System.IO
 
-import Bittide.Arithmetic.Time
 import Bittide.Wishbone
 
 import qualified Protocols.Df as Df
 
 -- | The maximum baud rate for a given domain, useful for simulation purposes
-type MaxBaudRate dom = Div (DomainFrequency dom) 16
+type MaxBaudRate dom = Div (DomainToHz dom) 16
 
 -- | A simulation function for circuits that expose a UART connection.
 -- This function reads from the provided input handle and feeds that to the UART circuit.
diff --git a/bittide/tests/Tests/Transceiver.hs b/bittide/tests/Tests/Transceiver.hs
index 19f0669c0..70d3aa974 100644
--- a/bittide/tests/Tests/Transceiver.hs
+++ b/bittide/tests/Tests/Transceiver.hs
@@ -11,11 +11,11 @@
 
 module Tests.Transceiver where
 
-import Clash.Explicit.Prelude
+import Clash.Explicit.Prelude hiding (PeriodToCycles)
 import Clash.Prelude (withClock)
 import Hedgehog
 
-import Bittide.Arithmetic.Time (PeriodToCycles, Microseconds, Milliseconds)
+import Bittide.Arithmetic.Time (PeriodToCycles)
 import Bittide.SharedTypes (Bytes)
 import Clash.Annotations.Primitive (dontTranslate)
 import Clash.Cores.Xilinx.GTH (GthCore)
diff --git a/cabal.project b/cabal.project
index 5b58dcdeb..ecdf2f2bd 100644
--- a/cabal.project
+++ b/cabal.project
@@ -131,31 +131,27 @@ index-state: 2023-12-05T05:33:28Z
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-compiler.git
-  tag: 9afc2262a66cbf98c7c157d5472cbb46d0016f7f
+  tag: 1d49cd2a528fe719beb3b2887dc440362b1b3574
   subdir: clash-prelude
-
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-compiler.git
-  tag: 9afc2262a66cbf98c7c157d5472cbb46d0016f7f
+  tag: 1d49cd2a528fe719beb3b2887dc440362b1b3574
   subdir: clash-ghc
-
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-compiler.git
-  tag: 9afc2262a66cbf98c7c157d5472cbb46d0016f7f
+  tag: 1d49cd2a528fe719beb3b2887dc440362b1b3574
   subdir: clash-lib
-
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-compiler.git
-  tag: 9afc2262a66cbf98c7c157d5472cbb46d0016f7f
+  tag: 1d49cd2a528fe719beb3b2887dc440362b1b3574
   subdir: clash-prelude-hedgehog
-
 source-repository-package
   type: git
   location: https://github.com/clash-lang/clash-compiler.git
-  tag: 9afc2262a66cbf98c7c157d5472cbb46d0016f7f
+  tag: 1d49cd2a528fe719beb3b2887dc440362b1b3574
   subdir: clash-cores
 
 source-repository-package