-
Notifications
You must be signed in to change notification settings - Fork 1
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Implement fast/efficient execution deadlines in software #587
Implement fast/efficient execution deadlines in software #587
Comments
I added some measurement hardware and ran a test. With the current setup the period between clock updates fluctuates between 405 and 414 cycles @ 125MHz. |
@rslawson A little bit of clarification: while it's a lofty goal to get the iterations take exactly the same time on each node + speed them up, the goal of this issue is to hit a specific update rate. That is to say, we view a single iteration: The exact moment of FINC/FDEC submission is way less important (maybe even entirely?) for calculating a proper proportional gain than the update rate. |
I didn't realise that this would get closed when even just one of the linked PRs got closed, oops. |
We currently maintain two instances for clock control: hardware and software. We use the former because it both consistently and reliably hits a (maximum) clock control update frequency of 1 MHz. While the latter does what we want in practice (clock convergence), we don't have a good idea on how long it takes to do a single clock control update. I.e.:
We don't really mind fewer updates (say, 100 KHz) but the updates should be timed reliably to make sure we can make our theory match our practice. We currently do have some timing logic implemented in Rust (
firmware-support/bittide-sys/src/time.rs
) backed by a hardware componentbittide/src/Bittide/Wishbone.hs
=>timeWb
but this is too slow to reliably schedule microseconds.We should investigate what is needed to set a reliable update rate. There is no one valid solution that comes to mind, but in the end we should have a solution that:
Relevant code:
bittide/src/Bittide/Wishbone.hs
=>timeWb
firmware-support/bittide-sys/src/time.rs
: HAL for timing componentfirmware-support/bittide-sys/src/clock_control.rs
: HAL for FINC/FDEC buttonsfirmware-support/bittide-sys/src/callisto.rs
: Implementation of clock control algorithm ("Callisto")The text was updated successfully, but these errors were encountered: