ILAs on inactive FPGAs in topology test get garbage data

[rslawson]

As the title says, inactive FPGAs' ILAs get garbage data in the topology test. For instance, FPGA 0 from the fully connected 3 node topology is active in the test and has the following as the first few lines from its ilaPlot.csv:

Sample in Buffer,Sample in Window,TRIGGER,trigger_1,capture_1,condition,global,local,data
0,0,1,1,0,0,000100000,14c45c,000000000000000000000000000000000000
1,1,0,1,1,1,000498965,2e4c28,000000000000000000000000000000000000
2,2,0,1,1,1,000898966,6624bf,000000000000000000000000000000000000
3,3,0,1,1,2,000c98966,6624be,000000000000000000000000000000000000

But FPGA 3 has as its entire file:

Sample in Buffer,Sample in Window,TRIGGER,trigger_0,capture_0,probe_milliseconds,probe_allStable0,probe_transceiversFailedAfterUp,probe_nFincs,probe_nFdecs,probe_net_nFincs

This is the correct column headers for the fincFdecIla.csv file. I have also observed this behaviour in the software clock control topology test in my branch.

Full paths for these files:

• vivado/Bittide.Instances.Hitl.HwCcTopologies.hwCcTopologyTest/ila-data/complete/0_210308B3B272/ilaPlot.csv
• vivado/Bittide.Instances.Hitl.HwCcTopologies.hwCcTopologyTest/ila-data/complete/3_210308B0AE6D/ilaPlot.csv

[JvWesterveld]

As discussed in person: I believe this may only be relevant for the HwCcTopologies test as that one always includes all hardware targets/FPGAs in all HitlTestCases even though some aren't actually useful for all such test cases. Removing them from the HitlTestCase parameters field would prevent such FPGAs from being programmed and would prevent their ILA's from being read out, which IMHO would be the cleanest solution to this problem.

[rslawson]

The problem did in fact go away when I removed the FPGAs that were not being used from the device map. However, this presented a new problem - one of the "unused" FPGAs was being used to send a synchronisation signal to all the other FPGAs, and when it wasn't active, the tests didn't start. This is the case for the hardware clock control topologies test and the software clock control topologies test in my branch.