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goldmont_core.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2022 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Atom(TM) Processors Based on the Goldmont Microarchitecture - V13",
"DatePublished": "03/02/2018",
"Version": "13",
"Legend": ""
},
"Events": [
{
"EventCode": "0x00",
"UMask": "0x01",
"EventName": "INST_RETIRED.ANY",
"BriefDescription": "Instructions retired (Fixed event)",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"Counter": "Fixed counter 0",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "0",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x00",
"UMask": "0x02",
"EventName": "CPU_CLK_UNHALTED.CORE",
"BriefDescription": "Core cycles when core is not halted (Fixed event)",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"Counter": "Fixed counter 1",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "0",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x00",
"UMask": "0x03",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"BriefDescription": "Reference cycles when core is not halted (Fixed event)",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"Counter": "Fixed counter 2",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "0",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x03",
"UMask": "0x01",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
"PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x03",
"UMask": "0x02",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
"PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x03",
"UMask": "0x04",
"EventName": "LD_BLOCKS.4K_ALIAS",
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x03",
"UMask": "0x08",
"EventName": "LD_BLOCKS.UTLB_MISS",
"BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
"PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x03",
"UMask": "0x10",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"BriefDescription": "Loads blocked (Precise event capable)",
"PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x05",
"UMask": "0x01",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"BriefDescription": "Duration of D-side page-walks in cycles",
"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x05",
"UMask": "0x02",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"BriefDescription": "Duration of I-side pagewalks in cycles",
"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x05",
"UMask": "0x03",
"EventName": "PAGE_WALKS.CYCLES",
"BriefDescription": "Duration of page-walks in cycles",
"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x0E",
"UMask": "0x00",
"EventName": "UOPS_ISSUED.ANY",
"BriefDescription": "Uops issued to the back end per cycle",
"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x13",
"UMask": "0x02",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"BriefDescription": "Load uops that split a page (Precise event capable)",
"PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x13",
"UMask": "0x04",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"BriefDescription": "Store uops that split a page (Precise event capable)",
"PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x2E",
"UMask": "0x41",
"EventName": "LONGEST_LAT_CACHE.MISS",
"BriefDescription": "L2 cache request misses",
"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x2E",
"UMask": "0x4F",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"BriefDescription": "L2 cache requests",
"PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x30",
"UMask": "0x00",
"EventName": "L2_REJECT_XQ.ALL",
"BriefDescription": "Requests rejected by the XQ",
"PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x31",
"UMask": "0x00",
"EventName": "CORE_REJECT_L2Q.ALL",
"BriefDescription": "Requests rejected by the L2Q",
"PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x3C",
"UMask": "0x00",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"BriefDescription": "Core cycles when core is not halted",
"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x3C",
"UMask": "0x01",
"EventName": "CPU_CLK_UNHALTED.REF",
"BriefDescription": "Reference cycles when core is not halted",
"PublicDescription": "Reference cycles when core is not halted. This event uses a programmable general purpose performance counter.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x51",
"UMask": "0x01",
"EventName": "DL1.DIRTY_EVICTION",
"BriefDescription": "L1 Cache evictions for dirty data",
"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x80",
"UMask": "0x01",
"EventName": "ICACHE.HIT",
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x80",
"UMask": "0x02",
"EventName": "ICACHE.MISSES",
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x80",
"UMask": "0x03",
"EventName": "ICACHE.ACCESSES",
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x81",
"UMask": "0x04",
"EventName": "ITLB.MISS",
"BriefDescription": "ITLB misses",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x86",
"UMask": "0x00",
"EventName": "FETCH_STALL.ALL",
"BriefDescription": "Cycles code-fetch stalled due to any reason.",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events. ",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x86",
"UMask": "0x01",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x86",
"UMask": "0x02",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0x9C",
"UMask": "0x00",
"EventName": "UOPS_NOT_DELIVERED.ANY",
"BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
"PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xB7",
"UMask": "0x01,0x02",
"EventName": "OFFCORE_RESPONSE",
"BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"PublicDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "100007",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC0",
"UMask": "0x00",
"EventName": "INST_RETIRED.ANY_P",
"BriefDescription": "Instructions retired (Precise event capable)",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC2",
"UMask": "0x00",
"EventName": "UOPS_RETIRED.ANY",
"BriefDescription": "Uops retired (Precise event capable)",
"PublicDescription": "Counts uops which retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC2",
"UMask": "0x01",
"EventName": "UOPS_RETIRED.MS",
"BriefDescription": "MS uops retired (Precise event capable)",
"PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC2",
"UMask": "0x08",
"EventName": "UOPS_RETIRED.FPDIV",
"BriefDescription": "Floating point divide uops retired. (Precise Event Capable)",
"PublicDescription": "Counts the number of floating point divide uops retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC2",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.IDIV",
"BriefDescription": "Integer divide uops retired. (Precise Event Capable)",
"PublicDescription": "Counts the number of integer divide uops retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "2000003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC3",
"UMask": "0x00",
"EventName": "MACHINE_CLEARS.ALL",
"BriefDescription": "All machine clears",
"PublicDescription": "Counts machine clears for any reason.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC3",
"UMask": "0x01",
"EventName": "MACHINE_CLEARS.SMC",
"BriefDescription": "Self-Modifying Code detected",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel® architecture processors.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC3",
"UMask": "0x02",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"BriefDescription": "Machine clears due to memory ordering issue",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC3",
"UMask": "0x04",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"BriefDescription": "Machine clears due to FP assists",
"PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC3",
"UMask": "0x08",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"BriefDescription": "Machine clears due to memory disambiguation",
"PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "0",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0x00",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"BriefDescription": "Retired branch instructions (Precise event capable)",
"PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0x7E",
"EventName": "BR_INST_RETIRED.JCC",
"BriefDescription": "Retired conditional branch instructions (Precise event capable)",
"PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0x80",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"BriefDescription": "Retired taken branch instructions (Precise event capable)",
"PublicDescription": "Counts the number of taken branch instructions retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "1",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0xBF",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"BriefDescription": "Retired far branch instructions (Precise event capable)",
"PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0xEB",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)",
"PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0xF7",
"EventName": "BR_INST_RETIRED.RETURN",
"BriefDescription": "Retired near return instructions (Precise event capable)",
"PublicDescription": "Counts near return branch instructions retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0xF9",
"EventName": "BR_INST_RETIRED.CALL",
"BriefDescription": "Retired near call instructions (Precise event capable)",
"PublicDescription": "Counts near CALL branch instructions retired.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"CollectPEBSRecord": "2",
"CounterMask": "0",
"Invert": "0",
"AnyThread": "0",
"EdgeDetect": "0",
"PEBS": "2",
"Data_LA": "0",
"Errata": "0",
"Offcore": "0"
},
{
"EventCode": "0xC4",
"UMask": "0xFB",
"EventName": "BR_INST_RETIRED.IND_CALL",