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goldmont_matrix.json
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{
"Header": {
"Copyright": "Copyright (c) 2001 - 2022 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Atom(TM) Processors Based on the Goldmont Microarchitecture - V13",
"DatePublished": "03/02/2018",
"Version": "13",
"Legend": ""
},
"Events": [
{
"MATRIX_REQUEST": "DEMAND_DATA_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0001 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts demand cacheable data reads of full cache lines"
},
{
"MATRIX_REQUEST": "DEMAND_RFO",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0002 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line"
},
{
"MATRIX_REQUEST": "DEMAND_CODE_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0004 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache"
},
{
"MATRIX_REQUEST": "COREWB",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0008 ",
"MATRIX_REGISTER": "0",
"DESCRIPTION": "Counts the number of writeback transactions caused by L1 or L2 cache evictions"
},
{
"MATRIX_REQUEST": "PF_L2_DATA_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0010 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts data cacheline reads generated by hardware L2 cache prefetcher"
},
{
"MATRIX_REQUEST": "PF_L2_RFO",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0020 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts reads for ownership (RFO) requests generated by L2 prefetcher"
},
{
"MATRIX_REQUEST": "PARTIAL_READS",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0080 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types"
},
{
"MATRIX_REQUEST": "PARTIAL_WRITES",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0100 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory"
},
{
"MATRIX_REQUEST": "UC_CODE_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0200 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts code reads in uncacheable (UC) memory region"
},
{
"MATRIX_REQUEST": "BUS_LOCKS",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0400 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts bus lock and split lock requests"
},
{
"MATRIX_REQUEST": "FULL_STREAMING_STORES",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0800 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes"
},
{
"MATRIX_REQUEST": "SW_PREFETCH",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x1000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts data cache lines requests by software prefetch instructions"
},
{
"MATRIX_REQUEST": "PF_L1_DATA_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x2000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts data cache line reads generated by hardware L1 data cache prefetcher"
},
{
"MATRIX_REQUEST": "PARTIAL_STREAMING_STORES",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x4000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region"
},
{
"MATRIX_REQUEST": "STREAMING_STORES",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x4800 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts any data writes to uncacheable write combining (USWC) memory region"
},
{
"MATRIX_REQUEST": "ANY_REQUEST",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x8000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts requests to the uncore subsystem"
},
{
"MATRIX_REQUEST": "ANY_PF_DATA_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x3010 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts data reads generated by L1 or L2 prefetchers"
},
{
"MATRIX_REQUEST": "ANY_DATA_RD",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x3091",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts data reads (demand & prefetch)"
},
{
"MATRIX_REQUEST": "ANY_RFO",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x0022 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts reads for ownership (RFO) requests (demand & prefetch)"
},
{
"MATRIX_REQUEST": "ANY_READ",
"MATRIX_RESPONSE": "Null",
"MATRIX_VALUE": "0x32b7 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)"
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "ANY_RESPONSE",
"MATRIX_VALUE": "0x000001 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "have any transaction responses from the uncore subsystem."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "L2_HIT",
"MATRIX_VALUE": "0x000004 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "hit the L2 cache."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
"MATRIX_VALUE": "0x020000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "true miss for the L2 cache with a snoop miss in the other processor module."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MATRIX_VALUE": "0x040000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "L2_MISS.HITM_OTHER_CORE",
"MATRIX_VALUE": "0x100000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "miss the L2 cache with a snoop hit in the other processor module, data forwarding is required."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "L2_MISS.NON_DRAM",
"MATRIX_VALUE": "0x200000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "miss the L2 cache and targets non-DRAM system address."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "L2_MISS.ANY",
"MATRIX_VALUE": "0x360000 ",
"MATRIX_REGISTER": "0,1",
"DESCRIPTION": "miss the L2 cache."
},
{
"MATRIX_REQUEST": "Null",
"MATRIX_RESPONSE": "OUTSTANDING",
"MATRIX_VALUE": "0x400000 ",
"MATRIX_REGISTER": "0",
"DESCRIPTION": "outstanding, per cycle, from the time of the L2 miss to when any response is received."
}
]
}