rvemu.dts

/dts-v1/;

/ {
    #address-cells = <2>;
    #size-cells = <2>;
    compatible = "riscv-virtio";
    model = "riscv-virtio,qemu";

    chosen {
        bootargs = [00];
        stdout-path = "/uart@10000000";
    };

    uart@10000000 {
        interrupts = <0xa>;
        interrupt-parent = <0x2>;
        clock-frequency = <0x384000>;
        reg = <0x0 0x10000000 0x0 0x100>;
        compatible = "ns16550a";
    };

	virtio_mmio@10001000 {
		interrupts = <0x1>;
		interrupt-parent = <0x2>;
		reg = <0x0 0x10001000 0x0 0x1000>;
		compatible = "virtio,mmio";
	};

    cpus {
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        timebase-frequency = <0x989680>;

        cpu@0 {
            device_type = "cpu";
            reg = <0x0>;
            status = "okay";
            compatible = "riscv";
            riscv,isa = "rv64imafdcsu";
            mmu-type = "riscv,sv39";
            clock-frequency = <0x3b9aca00>;

            interrupt-controller {
                #interrupt-cells = <0x1>;
                interrupt-controller;
                compatible = "riscv,cpu-intc";
                linux,phandle = <0x1>;
                phandle = <0x1>;
            };
        };
    };

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x8000000>;
	};

	soc {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		compatible = "riscv-virtio-soc";
		ranges;

		interrupt-controller@c000000 {
			linux,phandle = <0x2>;
			phandle = <0x2>;
			riscv,ndev = <0xa>;
			riscv,max-priority = <0x7>;
			reg-names = "control";
			reg = <0x0 0xc000000 0x0 0x4000000>;
			interrupts-extended = <0x1 0xb 0x1 0x9>;
			interrupt-controller;
			compatible = "riscv,plic0";
			#interrupt-cells = <0x1>;
		};

		clint@2000000 {
			interrupts-extended = <0x1 0x3 0x1 0x7>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			compatible = "riscv,clint0";
		};
	};
};