From 5fb4b55c8a1dcc3a2a821864d2665b89e0aba4ac Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Wed, 22 Nov 2023 21:56:15 -0300 Subject: [PATCH] set pins and FlexSPI clock --- .../rt1020-evk-make-baremetal-builtin/hal.h | 34 ++++++++++++++++++ .../rt1020-evk-make-baremetal-builtin/main.c | 1 + .../rt1060-evk-make-baremetal-builtin/hal.h | 35 +++++++++++++++++++ .../rt1060-evk-make-baremetal-builtin/main.c | 1 + 4 files changed, 71 insertions(+) diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h index a2ab972977a..613cd8e7b77 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h @@ -301,3 +301,37 @@ static inline void ethernet_init(void) { ((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \ (OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \ } + +static inline void flash_init(void) { // QSPI in FlexSPI + // set pins + clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for SS + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT, 1); // drive peripheral from B1_07 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT, 1); // drive peripheral from B1_08 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA1 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT, 1); // drive peripheral from B1_10 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA2 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT, 1); // drive peripheral from B1_09 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for DATA3 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT, 1); // drive peripheral from B1_06 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + // set FlexSPI clock + SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(3)); // select PLL3 PFD0 /4 + clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable +} diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c index 2d1b9ed8ffe..2d286ee27d9 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c @@ -57,6 +57,7 @@ static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) { int main(void) { gpio_output(LED); // Setup blue LED uart_init(UART_DEBUG, 115200); // Initialise debug printf + flash_init(); // setup pins and clocks to access board flash ethernet_init(); // Initialise ethernet pins MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000)); diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h b/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h index 200d3752a90..4ccc569df5d 100644 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h +++ b/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h @@ -319,3 +319,38 @@ static inline void ethernet_init(void) { } // NOTE: You can fuse your own MAC and read it from OCOTP->MAC0, OCOTP->MAC1, // OCOTP->MAC2 + +static inline void flash_init(void) { // QSPI in FlexSPI + // set pins + clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT, 1); // drive peripheral from B1_05 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for SS + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT, 1); // drive peripheral from B1_07 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT, 1); // drive peripheral from B1_08 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA1 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT, 1); // drive peripheral from B1_09 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA2 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT, 1); // drive peripheral from B1_10 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for DATA3 + IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin + periph_mux_config(kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT, 1); // drive peripheral from B1_11 + gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); + // set FlexSPI clock + SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7)); // select PLL3 PFD0 /8 + clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable +} diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c index 3fd164e5152..0e1cd6e424f 100644 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c +++ b/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c @@ -34,6 +34,7 @@ static void timer_fn(void *arg) { int main(void) { gpio_output(LED); // Setup blue LED uart_init(UART_DEBUG, 115200); // Initialise debug printf + flash_init(); // setup pins and clocks to access board flash ethernet_init(); // Initialise ethernet pins MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));