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$size evaluates to the wrong value #1094

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Rodrigodd opened this issue Feb 8, 2025 · 0 comments
Open

$size evaluates to the wrong value #1094

Rodrigodd opened this issue Feb 8, 2025 · 0 comments

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@Rodrigodd
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Description

I was trying to get a existing design loaded into Synlig, but I notice that $size of a unpacked array was returning the size in bits of the full memory, instead of just the number of elements.

I am not sure if I should have filled this issue on Synlig, Surelog or here, but, from what I can tell, the code responsible for evaluating $size is mostly here.

Reproduction

If I have the file testsize.sv below:

module top();
	logic [3:0] a[1:0];
	logic b[$size(a)-1:0];
endmodule

And in the Surelog repository I run:

dbuild/bin/surelog -sv testsize.sv -top top -parse -nobuiltin -v4 -d uhdm

I can see from the output that the vpiSize of b is 8, where it should be 2.

\_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
  |vpiName:work@top
  |vpiVariables:
  \_array_var: ([email protected]), line:2:14, endln:2:15
    |vpiSize:2
  \_array_var: ([email protected]), line:3:8, endln:3:9
    |vpiSize:8
Full Output 
[INF:CM0023] Creating log file "/home/rodrigodd/repos/Surelog/slpp_all/surelog.log".
[WRN:CM0010] Command line argument "-v4" ignored.
[WRN:PA0205] /home/rodrigodd/repos/Surelog/testsize.sv:1:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0303] /home/rodrigodd/repos/Surelog/testsize.sv:1:1: Compile module "work@top".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /home/rodrigodd/repos/Surelog/testsize.sv:1:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
[INF:UH0708] Writing UHDM DB: /home/rodrigodd/repos/Surelog/slpp_all/surelog.uhdm ...
[INF:UH0709] Writing UHDM Html Coverage: /home/rodrigodd/repos/Surelog/slpp_all/checker/surelog.chk.html ...
[INF:UH0710] Loading UHDM DB: /home/rodrigodd/repos/Surelog/slpp_all/surelog.uhdm ...
[INF:UH0711] Decompiling UHDM...
====== UHDM =======
design: (work@top)
|vpiName:work@top
|uhdmallModules:
\_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
  |vpiParent:
  \_design: (work@top)
  |vpiFullName:work@top
  |vpiDefName:work@top
  |vpiNet:
  \_logic_net: ([email protected]), line:2:14, endln:2:15
    |vpiParent:
    \_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
    |vpiTypespec:
    \_ref_typespec: ([email protected])
      |vpiParent:
      \_logic_net: ([email protected]), line:2:14, endln:2:15
      |vpiFullName:[email protected]
      |vpiActual:
      \_logic_typespec: , line:2:2, endln:2:20
    |vpiName:a
    |vpiFullName:[email protected]
    |vpiNetType:36
  |vpiNet:
  \_logic_net: ([email protected]), line:3:8, endln:3:9
    |vpiParent:
    \_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
    |vpiTypespec:
    \_ref_typespec: ([email protected])
      |vpiParent:
      \_logic_net: ([email protected]), line:3:8, endln:3:9
      |vpiFullName:[email protected]
      |vpiActual:
      \_logic_typespec: , line:3:2, endln:3:23
    |vpiName:b
    |vpiFullName:[email protected]
    |vpiNetType:36
|uhdmtopModules:
\_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
  |vpiName:work@top
  |vpiVariables:
  \_array_var: ([email protected]), line:2:14, endln:2:15
    |vpiParent:
    \_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
    |vpiSize:2
    |vpiTypespec:
    \_ref_typespec: ([email protected])
      |vpiParent:
      \_array_var: ([email protected]), line:2:14, endln:2:15
      |vpiFullName:[email protected]
      |vpiActual:
      \_array_typespec: 
    |vpiName:a
    |vpiFullName:[email protected]
    |vpiRandType:1
    |vpiVisibility:1
    |vpiArrayType:1
    |vpiRange:
    \_range: , line:2:15, endln:2:20
      |vpiParent:
      \_array_var: ([email protected]), line:2:14, endln:2:15
      |vpiLeftRange:
      \_constant: , line:2:16, endln:2:17
        |vpiParent:
        \_range: , line:2:15, endln:2:20
        |vpiDecompile:1
        |vpiSize:64
        |UINT:1
        |vpiConstType:9
      |vpiRightRange:
      \_constant: , line:2:18, endln:2:19
        |vpiParent:
        \_range: , line:2:15, endln:2:20
        |vpiDecompile:0
        |vpiSize:64
        |UINT:0
        |vpiConstType:9
    |vpiReg:
    \_logic_var: ([email protected]), line:2:14, endln:2:15
      |vpiParent:
      \_array_var: ([email protected]), line:2:14, endln:2:15
      |vpiTypespec:
      \_ref_typespec: ([email protected])
        |vpiParent:
        \_logic_var: ([email protected]), line:2:14, endln:2:15
        |vpiFullName:[email protected]
        |vpiActual:
        \_logic_typespec: , line:2:2, endln:2:13
      |vpiFullName:[email protected]
  |vpiVariables:
  \_array_var: ([email protected]), line:3:8, endln:3:9
    |vpiParent:
    \_module_inst: work@top (work@top), file:/home/rodrigodd/repos/Surelog/testsize.sv, line:1:1, endln:4:10
    |vpiSize:8
    |vpiTypespec:
    \_ref_typespec: ([email protected])
      |vpiParent:
      \_array_var: ([email protected]), line:3:8, endln:3:9
      |vpiFullName:[email protected]
      |vpiActual:
      \_array_typespec: 
    |vpiName:b
    |vpiFullName:[email protected]
    |vpiRandType:1
    |vpiVisibility:1
    |vpiArrayType:1
    |vpiRange:
    \_range: , line:3:9, endln:3:23
      |vpiParent:
      \_array_var: ([email protected]), line:3:8, endln:3:9
      |vpiLeftRange:
      \_constant: , line:3:10, endln:3:18
        |vpiParent:
        \_range: , line:3:9, endln:3:23
        |vpiDecompile:7
        |vpiSize:64
        |INT:7
        |vpiConstType:7
      |vpiRightRange:
      \_constant: , line:3:21, endln:3:22
        |vpiParent:
        \_range: , line:3:9, endln:3:23
        |vpiDecompile:0
        |vpiSize:64
        |UINT:0
        |vpiConstType:9
    |vpiReg:
    \_logic_var: ([email protected]), line:3:8, endln:3:9
      |vpiParent:
      \_array_var: ([email protected]), line:3:8, endln:3:9
      |vpiTypespec:
      \_ref_typespec: ([email protected])
        |vpiParent:
        \_logic_var: ([email protected]), line:3:8, endln:3:9
        |vpiFullName:[email protected]
        |vpiActual:
        \_logic_typespec: , line:3:2, endln:3:7
      |vpiFullName:[email protected]
  |vpiDefName:work@top
  |vpiTop:1
  |vpiTopModule:1
\_weaklyReferenced:
\_logic_typespec: , line:2:2, endln:2:13
  |vpiParent:
  \_logic_var: ([email protected]), line:2:14, endln:2:15
  |vpiRange:
  \_range: , line:2:8, endln:2:13
    |vpiParent:
    \_logic_typespec: , line:2:2, endln:2:13
    |vpiLeftRange:
    \_constant: , line:2:9, endln:2:10
      |vpiParent:
      \_range: , line:2:8, endln:2:13
      |vpiDecompile:3
      |vpiSize:64
      |UINT:3
      |vpiConstType:9
    |vpiRightRange:
    \_constant: , line:2:11, endln:2:12
      |vpiParent:
      \_range: , line:2:8, endln:2:13
      |vpiDecompile:0
      |vpiSize:64
      |UINT:0
      |vpiConstType:9
\_array_typespec: 
\_logic_typespec: , line:3:2, endln:3:7
  |vpiParent:
  \_logic_var: ([email protected]), line:3:8, endln:3:9
\_array_typespec: 
\_logic_typespec: , line:2:2, endln:2:20
  |vpiRange:
  \_range: , line:2:8, endln:2:13
    |vpiParent:
    \_logic_typespec: , line:2:2, endln:2:20
    |vpiLeftRange:
    \_constant: , line:2:9, endln:2:10
      |vpiParent:
      \_range: , line:2:8, endln:2:13
      |vpiDecompile:3
      |vpiSize:64
      |UINT:3
      |vpiConstType:9
    |vpiRightRange:
    \_constant: , line:2:11, endln:2:12
      |vpiParent:
      \_range: , line:2:8, endln:2:13
      |vpiDecompile:0
      |vpiSize:64
      |UINT:0
      |vpiConstType:9
\_logic_typespec: , line:3:2, endln:3:23
===================
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 2
[   NOTE] : 5

Fix?

The patch below makes $size return the expected value in the case above, but I not sure if it will break others results, or if the function will still be wrong for other types.

diff --git a/templates/ExprEval.cpp b/templates/ExprEval.cpp
index 51ef9b3..171dc0e 100644
--- a/templates/ExprEval.cpp
+++ b/templates/ExprEval.cpp
@@ -1272,7 +1272,9 @@ uint64_t ExprEval::size(const any *ts, bool &invalidValue, const any *inst,
     case UHDM_OBJECT_TYPE::uhdmarray_typespec: {
       array_typespec *lts = (array_typespec *)ts;
       ranges = lts->Ranges();
-      if (const ref_typespec *rt = lts->Elem_typespec()) {
+      if (!full) {
+        bits = 1;
+      } else if (const ref_typespec *rt = lts->Elem_typespec()) {
         bits = size(rt->Actual_typespec(), invalidValue, inst, pexpr, full);
       }
       break;
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@Rodrigodd