From 103ba42b72649b6ee916403c39cd499c663b4b19 Mon Sep 17 00:00:00 2001
From: Unai Martinez-Corral <umartinezcorral@antmicro.com>
Date: Tue, 6 Sep 2022 21:53:36 +0200
Subject: [PATCH 1/2] mv f4pga/utils f4pga/aux/utils

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
---
 f4pga/{ => aux}/utils/eblif.py                |  0
 f4pga/{ => aux}/utils/pcf.py                  |  0
 .../utils/quicklogic/convert_compile_opts.py  |  0
 .../{ => aux}/utils/quicklogic/create_lib.py  |  0
 .../utils/quicklogic/pinmap_parse.py          |  0
 .../utils/quicklogic/pp3/arch_import.py       |  6 ++---
 .../utils/quicklogic/pp3/connections.py       |  4 ++--
 .../quicklogic/pp3/create_default_fasm.py     |  8 +++----
 .../utils/quicklogic/pp3/create_ioplace.py    |  4 ++--
 .../pp3/create_place_constraints.py           |  2 +-
 .../utils/quicklogic/pp3/data_import.py       |  8 +++----
 .../utils/quicklogic/pp3/data_structs.py      |  0
 .../quicklogic/pp3/eos-s3/iomux_config.py     |  4 ++--
 .../utils/quicklogic/pp3/fasm2bels.py         |  8 +++----
 .../quicklogic/pp3/prepare_vpr_database.py    | 12 +++++-----
 .../utils/quicklogic/pp3/routing_import.py    |  8 +++----
 .../utils/quicklogic/pp3/rr_utils.py          |  4 +---
 .../utils/quicklogic/pp3/switchbox_model.py   |  8 +++----
 .../utils/quicklogic/pp3/tile_import.py       |  6 ++---
 .../{ => aux}/utils/quicklogic/pp3/timing.py  |  6 ++---
 f4pga/{ => aux}/utils/quicklogic/pp3/utils.py |  0
 .../utils/quicklogic/pp3/verilogmodule.py     |  4 +++-
 .../utils/quicklogic/pp3/vis_switchboxes.py   |  8 +++----
 .../quicklogic/process_sdc_constraints.py     |  4 ++--
 .../quicklogic/qlf_k4n8/create_ioplace.py     |  8 +++----
 .../utils/quicklogic/repacker/README.md       |  0
 .../quicklogic/repacker/arch_xml_utils.py     |  0
 .../utils/quicklogic/repacker/block_path.py   |  0
 .../quicklogic/repacker/eblif_netlist.py      |  0
 .../quicklogic/repacker/netlist_cleaning.py   |  0
 .../quicklogic/repacker/packed_netlist.py     |  2 +-
 .../utils/quicklogic/repacker/pb_rr_graph.py  | 12 +++++-----
 .../repacker/pb_rr_graph_netlist.py           |  4 ++--
 .../quicklogic/repacker/pb_rr_graph_router.py |  2 +-
 .../utils/quicklogic/repacker/pb_type.py      |  4 ++--
 .../utils/quicklogic/repacker/repack.py       | 24 +++++++++----------
 .../eblif_roundtrip/netlist.golden.eblif      |  0
 .../eblif_roundtrip/test_eblif_roundtrip.py   |  0
 .../quicklogic/repacker/tests/identity.xsl    |  0
 .../repacker/tests/lut_padding/lut1.eblif     |  0
 .../tests/lut_padding/lut1_0.golden.eblif     |  0
 .../repacker/tests/lut_padding/lut1_0.net     |  0
 .../tests/lut_padding/lut1_1.golden.eblif     |  0
 .../repacker/tests/lut_padding/lut1_1.net     |  0
 .../tests/lut_padding/lut1_2.golden.eblif     |  0
 .../repacker/tests/lut_padding/lut1_2.net     |  0
 .../tests/lut_padding/lut1_3.golden.eblif     |  0
 .../repacker/tests/lut_padding/lut1_3.net     |  0
 .../tests/lut_padding/test_lut_padding.py     |  0
 .../netlist.golden.net                        |  0
 .../test_netlist_roundtrip.py                 |  0
 .../repacker/tests/sort_netlist.xsl           |  0
 .../quicklogic/yosys_fixup_cell_names.py      |  0
 f4pga/{ => aux}/utils/vpr_io_place.py         |  2 +-
 f4pga/{ => aux}/utils/xc7/create_ioplace.py   |  4 ++--
 .../utils/xc7/create_place_constraints.py     |  2 +-
 f4pga/{ => aux}/utils/xc7/fix_xc7_carry.py    |  0
 f4pga/{ => aux}/utils/yosys_split_inouts.py   |  0
 f4pga/flows/platforms.yml                     |  4 ++--
 f4pga/wrappers/sh/__init__.py                 |  4 ++--
 f4pga/wrappers/tcl/eos-s3.f4pga.tcl           |  4 ++--
 f4pga/wrappers/tcl/ice40.vpr.f4pga.tcl        |  2 +-
 f4pga/wrappers/tcl/qlf_k4n8.f4pga.tcl         |  2 +-
 f4pga/wrappers/tcl/xc7.f4pga.tcl              |  4 ++--
 64 files changed, 90 insertions(+), 98 deletions(-)
 rename f4pga/{ => aux}/utils/eblif.py (100%)
 rename f4pga/{ => aux}/utils/pcf.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/convert_compile_opts.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/create_lib.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/pinmap_parse.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/arch_import.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/connections.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/create_default_fasm.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/create_ioplace.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/create_place_constraints.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/data_import.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/data_structs.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/eos-s3/iomux_config.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/fasm2bels.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/prepare_vpr_database.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/routing_import.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/rr_utils.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/switchbox_model.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/tile_import.py (97%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/timing.py (97%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/utils.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/verilogmodule.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/pp3/vis_switchboxes.py (96%)
 rename f4pga/{ => aux}/utils/quicklogic/process_sdc_constraints.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/qlf_k4n8/create_ioplace.py (96%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/README.md (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/arch_xml_utils.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/block_path.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/eblif_netlist.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/netlist_cleaning.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/packed_netlist.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/pb_rr_graph.py (97%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/pb_rr_graph_netlist.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/pb_rr_graph_router.py (99%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/pb_type.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/repack.py (98%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/eblif_roundtrip/netlist.golden.eblif (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/eblif_roundtrip/test_eblif_roundtrip.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/identity.xsl (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1.eblif (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_0.golden.eblif (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_0.net (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_1.golden.eblif (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_1.net (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_2.golden.eblif (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_2.net (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_3.golden.eblif (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/lut1_3.net (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/lut_padding/test_lut_padding.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/netlist.golden.net (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/test_netlist_roundtrip.py (100%)
 rename f4pga/{ => aux}/utils/quicklogic/repacker/tests/sort_netlist.xsl (100%)
 rename f4pga/{ => aux}/utils/quicklogic/yosys_fixup_cell_names.py (100%)
 rename f4pga/{ => aux}/utils/vpr_io_place.py (99%)
 rename f4pga/{ => aux}/utils/xc7/create_ioplace.py (98%)
 rename f4pga/{ => aux}/utils/xc7/create_place_constraints.py (99%)
 rename f4pga/{ => aux}/utils/xc7/fix_xc7_carry.py (100%)
 rename f4pga/{ => aux}/utils/yosys_split_inouts.py (100%)

diff --git a/f4pga/utils/eblif.py b/f4pga/aux/utils/eblif.py
similarity index 100%
rename from f4pga/utils/eblif.py
rename to f4pga/aux/utils/eblif.py
diff --git a/f4pga/utils/pcf.py b/f4pga/aux/utils/pcf.py
similarity index 100%
rename from f4pga/utils/pcf.py
rename to f4pga/aux/utils/pcf.py
diff --git a/f4pga/utils/quicklogic/convert_compile_opts.py b/f4pga/aux/utils/quicklogic/convert_compile_opts.py
similarity index 100%
rename from f4pga/utils/quicklogic/convert_compile_opts.py
rename to f4pga/aux/utils/quicklogic/convert_compile_opts.py
diff --git a/f4pga/utils/quicklogic/create_lib.py b/f4pga/aux/utils/quicklogic/create_lib.py
similarity index 100%
rename from f4pga/utils/quicklogic/create_lib.py
rename to f4pga/aux/utils/quicklogic/create_lib.py
diff --git a/f4pga/utils/quicklogic/pinmap_parse.py b/f4pga/aux/utils/quicklogic/pinmap_parse.py
similarity index 100%
rename from f4pga/utils/quicklogic/pinmap_parse.py
rename to f4pga/aux/utils/quicklogic/pinmap_parse.py
diff --git a/f4pga/utils/quicklogic/pp3/arch_import.py b/f4pga/aux/utils/quicklogic/pp3/arch_import.py
similarity index 98%
rename from f4pga/utils/quicklogic/pp3/arch_import.py
rename to f4pga/aux/utils/quicklogic/pp3/arch_import.py
index a16878945..38850539b 100755
--- a/f4pga/utils/quicklogic/pp3/arch_import.py
+++ b/f4pga/aux/utils/quicklogic/pp3/arch_import.py
@@ -23,10 +23,10 @@
 
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.pp3.data_structs import ConnectionType, Loc
+from f4pga.aux.utils.quicklogic.pp3.data_structs import ConnectionType, Loc
 
-from f4pga.utils.quicklogic.pp3.tile_import import make_top_level_pb_type
-from f4pga.utils.quicklogic.pp3.tile_import import make_top_level_tile
+from f4pga.aux.utils.quicklogic.pp3.tile_import import make_top_level_pb_type
+from f4pga.aux.utils.quicklogic.pp3.tile_import import make_top_level_tile
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/connections.py b/f4pga/aux/utils/quicklogic/pp3/connections.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/connections.py
rename to f4pga/aux/utils/quicklogic/pp3/connections.py
index 579354a31..b71965383 100644
--- a/f4pga/utils/quicklogic/pp3/connections.py
+++ b/f4pga/aux/utils/quicklogic/pp3/connections.py
@@ -26,7 +26,7 @@
 import sys
 
 print("PYTHONPATH: {}".format(sys.path))
-from f4pga.utils.quicklogic.pp3.data_structs import (
+from f4pga.aux.utils.quicklogic.pp3.data_structs import (
     SwitchboxPinType,
     Loc,
     OPPOSITE_DIRECTION,
@@ -35,7 +35,7 @@
     ConnectionType,
     PinDirection,
 )
-from f4pga.utils.quicklogic.pp3.utils import find_cell_in_tile
+from f4pga.aux.utils.quicklogic.pp3.utils import find_cell_in_tile
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/create_default_fasm.py b/f4pga/aux/utils/quicklogic/pp3/create_default_fasm.py
similarity index 98%
rename from f4pga/utils/quicklogic/pp3/create_default_fasm.py
rename to f4pga/aux/utils/quicklogic/pp3/create_default_fasm.py
index 2b9844e99..34c74a4a4 100755
--- a/f4pga/utils/quicklogic/pp3/create_default_fasm.py
+++ b/f4pga/aux/utils/quicklogic/pp3/create_default_fasm.py
@@ -26,10 +26,10 @@
 
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.pp3.data_structs import PinDirection, SwitchboxPinType
-from f4pga.utils.quicklogic.pp3.data_import import import_data
-from f4pga.utils.quicklogic.pp3.utils import yield_muxes
-from f4pga.utils.quicklogic.pp3.switchbox_model import SwitchboxModel
+from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection, SwitchboxPinType
+from f4pga.aux.utils.quicklogic.pp3.data_import import import_data
+from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes
+from f4pga.aux.utils.quicklogic.pp3.switchbox_model import SwitchboxModel
 
 # =============================================================================
 duplicate = {}
diff --git a/f4pga/utils/quicklogic/pp3/create_ioplace.py b/f4pga/aux/utils/quicklogic/pp3/create_ioplace.py
similarity index 98%
rename from f4pga/utils/quicklogic/pp3/create_ioplace.py
rename to f4pga/aux/utils/quicklogic/pp3/create_ioplace.py
index 1bf66253c..b51486401 100755
--- a/f4pga/utils/quicklogic/pp3/create_ioplace.py
+++ b/f4pga/aux/utils/quicklogic/pp3/create_ioplace.py
@@ -23,8 +23,8 @@
 import re
 from collections import defaultdict
 
-import f4pga.utils.vpr_io_place as vpr_io_place
-from f4pga.utils.pcf import parse_simple_pcf
+import f4pga.aux.utils.vpr_io_place as vpr_io_place
+from f4pga.aux.utils.pcf import parse_simple_pcf
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/create_place_constraints.py b/f4pga/aux/utils/quicklogic/pp3/create_place_constraints.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/create_place_constraints.py
rename to f4pga/aux/utils/quicklogic/pp3/create_place_constraints.py
index 03fe6c0c6..f5ddfdc9f 100755
--- a/f4pga/utils/quicklogic/pp3/create_place_constraints.py
+++ b/f4pga/aux/utils/quicklogic/pp3/create_place_constraints.py
@@ -20,7 +20,7 @@
 import sys
 import csv
 
-import f4pga.utils.eblif as eblif
+import f4pga.aux.utils.eblif as eblif
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/data_import.py b/f4pga/aux/utils/quicklogic/pp3/data_import.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/data_import.py
rename to f4pga/aux/utils/quicklogic/pp3/data_import.py
index 6b7693b6d..d89c9600a 100755
--- a/f4pga/utils/quicklogic/pp3/data_import.py
+++ b/f4pga/aux/utils/quicklogic/pp3/data_import.py
@@ -30,7 +30,7 @@
 
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.pp3.data_structs import (
+from f4pga.aux.utils.quicklogic.pp3.data_structs import (
     Pin,
     PinDirection,
     Quadrant,
@@ -49,9 +49,9 @@
     PackagePin,
     OPPOSITE_DIRECTION,
 )
-from f4pga.utils.quicklogic.pp3.utils import yield_muxes, get_loc_of_cell, find_cell_in_tile, natural_keys
-from f4pga.utils.quicklogic.pp3.connections import build_connections, check_connections
-from f4pga.utils.quicklogic.pp3.connections import hop_to_str, get_name_and_hop, is_regular_hop_wire
+from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes, get_loc_of_cell, find_cell_in_tile, natural_keys
+from f4pga.aux.utils.quicklogic.pp3.connections import build_connections, check_connections
+from f4pga.aux.utils.quicklogic.pp3.connections import hop_to_str, get_name_and_hop, is_regular_hop_wire
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/data_structs.py b/f4pga/aux/utils/quicklogic/pp3/data_structs.py
similarity index 100%
rename from f4pga/utils/quicklogic/pp3/data_structs.py
rename to f4pga/aux/utils/quicklogic/pp3/data_structs.py
diff --git a/f4pga/utils/quicklogic/pp3/eos-s3/iomux_config.py b/f4pga/aux/utils/quicklogic/pp3/eos-s3/iomux_config.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/eos-s3/iomux_config.py
rename to f4pga/aux/utils/quicklogic/pp3/eos-s3/iomux_config.py
index be5cf3bfb..fd074461f 100755
--- a/f4pga/utils/quicklogic/pp3/eos-s3/iomux_config.py
+++ b/f4pga/aux/utils/quicklogic/pp3/eos-s3/iomux_config.py
@@ -27,8 +27,8 @@
 import re
 import sys
 
-from f4pga.utils.pcf import parse_simple_pcf
-from f4pga.utils.eblif import parse_blif
+from f4pga.aux.utils.pcf import parse_simple_pcf
+from f4pga.aux.utils.eblif import parse_blif
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/fasm2bels.py b/f4pga/aux/utils/quicklogic/pp3/fasm2bels.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/fasm2bels.py
rename to f4pga/aux/utils/quicklogic/pp3/fasm2bels.py
index 291c2142f..f40eed60e 100644
--- a/f4pga/utils/quicklogic/pp3/fasm2bels.py
+++ b/f4pga/aux/utils/quicklogic/pp3/fasm2bels.py
@@ -22,12 +22,12 @@
 from collections import defaultdict, namedtuple
 import fasm
 
-from f4pga.utils.quicklogic.pp3.connections import get_name_and_hop
+from f4pga.aux.utils.quicklogic.pp3.connections import get_name_and_hop
 
 from pathlib import Path
-from f4pga.utils.quicklogic.pp3.data_structs import Loc, SwitchboxPinLoc, PinDirection, ConnectionType
-from f4pga.utils.quicklogic.pp3.utils import get_quadrant_for_loc
-from f4pga.utils.quicklogic.pp3.verilogmodule import VModule
+from f4pga.aux.utils.quicklogic.pp3.data_structs import Loc, SwitchboxPinLoc, PinDirection, ConnectionType
+from f4pga.aux.utils.quicklogic.pp3.utils import get_quadrant_for_loc
+from f4pga.aux.utils.quicklogic.pp3.verilogmodule import VModule
 
 from quicklogic_fasm.qlfasm import load_quicklogic_database, get_db_dir
 from quicklogic_fasm.qlfasm import QL732BAssembler
diff --git a/f4pga/utils/quicklogic/pp3/prepare_vpr_database.py b/f4pga/aux/utils/quicklogic/pp3/prepare_vpr_database.py
similarity index 98%
rename from f4pga/utils/quicklogic/pp3/prepare_vpr_database.py
rename to f4pga/aux/utils/quicklogic/pp3/prepare_vpr_database.py
index ad0bcb0b1..813c83328 100755
--- a/f4pga/utils/quicklogic/pp3/prepare_vpr_database.py
+++ b/f4pga/aux/utils/quicklogic/pp3/prepare_vpr_database.py
@@ -25,7 +25,7 @@
 from sdf_timing import sdfparse
 from sdf_timing.utils import get_scale_seconds
 
-from f4pga.utils.quicklogic.pp3.data_structs import (
+from f4pga.aux.utils.quicklogic.pp3.data_structs import (
     Pin,
     PinDirection,
     Cell,
@@ -43,12 +43,12 @@
     VprSegment,
     Quadrant,
 )
-from f4pga.utils.quicklogic.pp3.utils import get_loc_of_cell, find_cell_in_tile
-from f4pga.utils.quicklogic.pp3.utils import get_pin_name
+from f4pga.aux.utils.quicklogic.pp3.utils import get_loc_of_cell, find_cell_in_tile
+from f4pga.aux.utils.quicklogic.pp3.utils import get_pin_name
 
-from f4pga.utils.quicklogic.pp3.timing import compute_switchbox_timing_model
-from f4pga.utils.quicklogic.pp3.timing import populate_switchbox_timing, copy_switchbox_timing
-from f4pga.utils.quicklogic.pp3.timing import add_vpr_switches_for_cell
+from f4pga.aux.utils.quicklogic.pp3.timing import compute_switchbox_timing_model
+from f4pga.aux.utils.quicklogic.pp3.timing import populate_switchbox_timing, copy_switchbox_timing
+from f4pga.aux.utils.quicklogic.pp3.timing import add_vpr_switches_for_cell
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/routing_import.py b/f4pga/aux/utils/quicklogic/pp3/routing_import.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/routing_import.py
rename to f4pga/aux/utils/quicklogic/pp3/routing_import.py
index 058403ac4..d9207bf3a 100755
--- a/f4pga/utils/quicklogic/pp3/routing_import.py
+++ b/f4pga/aux/utils/quicklogic/pp3/routing_import.py
@@ -25,11 +25,11 @@
 import lib.rr_graph_xml.graph2 as rr_xml
 from lib import progressbar_utils
 
-from f4pga.utils.quicklogic.pp3.data_structs import Loc, ConnectionType
-from f4pga.utils.quicklogic.pp3.utils import fixup_pin_name
+from f4pga.aux.utils.quicklogic.pp3.data_structs import Loc, ConnectionType
+from f4pga.aux.utils.quicklogic.pp3.utils import fixup_pin_name
 
-from f4pga.utils.quicklogic.pp3.rr_utils import add_node, add_track, add_edge, connect
-from f4pga.utils.quicklogic.pp3.switchbox_model import SwitchboxModel, QmuxSwitchboxModel
+from f4pga.aux.utils.quicklogic.pp3.rr_utils import add_node, add_track, add_edge, connect
+from f4pga.aux.utils.quicklogic.pp3.switchbox_model import SwitchboxModel, QmuxSwitchboxModel
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/pp3/rr_utils.py b/f4pga/aux/utils/quicklogic/pp3/rr_utils.py
similarity index 98%
rename from f4pga/utils/quicklogic/pp3/rr_utils.py
rename to f4pga/aux/utils/quicklogic/pp3/rr_utils.py
index 87d4ee92b..e25c3705c 100644
--- a/f4pga/utils/quicklogic/pp3/rr_utils.py
+++ b/f4pga/aux/utils/quicklogic/pp3/rr_utils.py
@@ -18,13 +18,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 
-from f4pga.utils.quicklogic.pp3.data_structs import Loc
+from f4pga.aux.utils.quicklogic.pp3.data_structs import Loc
 
 from lib.rr_graph import tracks
 import lib.rr_graph.graph2 as rr
 
-# =============================================================================
-
 
 def add_track(graph, track, segment_id, node_timing=None):
     """
diff --git a/f4pga/utils/quicklogic/pp3/switchbox_model.py b/f4pga/aux/utils/quicklogic/pp3/switchbox_model.py
similarity index 98%
rename from f4pga/utils/quicklogic/pp3/switchbox_model.py
rename to f4pga/aux/utils/quicklogic/pp3/switchbox_model.py
index d0ba6b6c1..fe56d2620 100644
--- a/f4pga/utils/quicklogic/pp3/switchbox_model.py
+++ b/f4pga/aux/utils/quicklogic/pp3/switchbox_model.py
@@ -20,11 +20,9 @@
 
 from collections import defaultdict
 
-from f4pga.utils.quicklogic.pp3.data_structs import PinDirection, ConnectionType
-from f4pga.utils.quicklogic.pp3.utils import yield_muxes
-from f4pga.utils.quicklogic.pp3.rr_utils import add_node, connect
-
-# =============================================================================
+from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection, ConnectionType
+from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes
+from f4pga.aux.utils.quicklogic.pp3.rr_utils import add_node, connect
 
 
 class SwitchboxModel(object):
diff --git a/f4pga/utils/quicklogic/pp3/tile_import.py b/f4pga/aux/utils/quicklogic/pp3/tile_import.py
similarity index 97%
rename from f4pga/utils/quicklogic/pp3/tile_import.py
rename to f4pga/aux/utils/quicklogic/pp3/tile_import.py
index f8df6c4d5..250daddac 100644
--- a/f4pga/utils/quicklogic/pp3/tile_import.py
+++ b/f4pga/aux/utils/quicklogic/pp3/tile_import.py
@@ -25,10 +25,8 @@
 
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.pp3.data_structs import PinDirection
-from f4pga.utils.quicklogic.pp3.utils import fixup_pin_name, get_pin_name
-
-# =============================================================================
+from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection
+from f4pga.aux.utils.quicklogic.pp3.utils import fixup_pin_name, get_pin_name
 
 
 def add_ports(xml_parent, pins, buses=True):
diff --git a/f4pga/utils/quicklogic/pp3/timing.py b/f4pga/aux/utils/quicklogic/pp3/timing.py
similarity index 97%
rename from f4pga/utils/quicklogic/pp3/timing.py
rename to f4pga/aux/utils/quicklogic/pp3/timing.py
index 2fb621126..893abddcb 100644
--- a/f4pga/utils/quicklogic/pp3/timing.py
+++ b/f4pga/aux/utils/quicklogic/pp3/timing.py
@@ -21,10 +21,8 @@
 from copy import deepcopy
 from collections import defaultdict, namedtuple
 
-from f4pga.utils.quicklogic.pp3.data_structs import VprSwitch, MuxEdgeTiming, DriverTiming, SinkTiming
-from f4pga.utils.quicklogic.pp3.utils import yield_muxes, add_named_item
-
-# =============================================================================
+from f4pga.aux.utils.quicklogic.pp3.data_structs import VprSwitch, MuxEdgeTiming, DriverTiming, SinkTiming
+from f4pga.aux.utils.quicklogic.pp3.utils import yield_muxes, add_named_item
 
 
 def linear_regression(xs, ys):
diff --git a/f4pga/utils/quicklogic/pp3/utils.py b/f4pga/aux/utils/quicklogic/pp3/utils.py
similarity index 100%
rename from f4pga/utils/quicklogic/pp3/utils.py
rename to f4pga/aux/utils/quicklogic/pp3/utils.py
diff --git a/f4pga/utils/quicklogic/pp3/verilogmodule.py b/f4pga/aux/utils/quicklogic/pp3/verilogmodule.py
similarity index 99%
rename from f4pga/utils/quicklogic/pp3/verilogmodule.py
rename to f4pga/aux/utils/quicklogic/pp3/verilogmodule.py
index 580e1b770..bfc31a337 100644
--- a/f4pga/utils/quicklogic/pp3/verilogmodule.py
+++ b/f4pga/aux/utils/quicklogic/pp3/verilogmodule.py
@@ -16,10 +16,12 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
+
+
 import re
 from collections import namedtuple, defaultdict
 
-from f4pga.utils.quicklogic.pp3.data_structs import PinDirection
+from f4pga.aux.utils.quicklogic.pp3.data_structs import PinDirection
 
 Element = namedtuple("Element", "loc type name ios")
 Wire = namedtuple("Wire", "srcloc name inverted")
diff --git a/f4pga/utils/quicklogic/pp3/vis_switchboxes.py b/f4pga/aux/utils/quicklogic/pp3/vis_switchboxes.py
similarity index 96%
rename from f4pga/utils/quicklogic/pp3/vis_switchboxes.py
rename to f4pga/aux/utils/quicklogic/pp3/vis_switchboxes.py
index 5ae30fd25..916e4e562 100755
--- a/f4pga/utils/quicklogic/pp3/vis_switchboxes.py
+++ b/f4pga/aux/utils/quicklogic/pp3/vis_switchboxes.py
@@ -16,14 +16,14 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
+
+
 import argparse
 
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.pp3.data_structs import SwitchboxPinType
-from f4pga.utils.quicklogic.pp3.data_import import import_data
-
-# =============================================================================
+from f4pga.aux.utils.quicklogic.pp3.data_structs import SwitchboxPinType
+from f4pga.aux.utils.quicklogic.pp3.data_import import import_data
 
 
 def fixup_pin_name(name):
diff --git a/f4pga/utils/quicklogic/process_sdc_constraints.py b/f4pga/aux/utils/quicklogic/process_sdc_constraints.py
similarity index 98%
rename from f4pga/utils/quicklogic/process_sdc_constraints.py
rename to f4pga/aux/utils/quicklogic/process_sdc_constraints.py
index 87f09c0e3..0d0f4f15e 100644
--- a/f4pga/utils/quicklogic/process_sdc_constraints.py
+++ b/f4pga/aux/utils/quicklogic/process_sdc_constraints.py
@@ -30,8 +30,8 @@
 import re
 import csv
 
-from f4pga.utils.pcf import parse_simple_pcf, PcfIoConstraint
-from f4pga.utils.eblif import parse_blif
+from f4pga.aux.utils.pcf import parse_simple_pcf, PcfIoConstraint
+from f4pga.aux.utils.eblif import parse_blif
 
 
 RE_INDICES = re.compile(r"(?P<name>\S+)\[(?P<i0>[0-9]+):(?P<i1>[0-9]+)\]")
diff --git a/f4pga/utils/quicklogic/qlf_k4n8/create_ioplace.py b/f4pga/aux/utils/quicklogic/qlf_k4n8/create_ioplace.py
similarity index 96%
rename from f4pga/utils/quicklogic/qlf_k4n8/create_ioplace.py
rename to f4pga/aux/utils/quicklogic/qlf_k4n8/create_ioplace.py
index 97d997368..4f02cb943 100755
--- a/f4pga/utils/quicklogic/qlf_k4n8/create_ioplace.py
+++ b/f4pga/aux/utils/quicklogic/qlf_k4n8/create_ioplace.py
@@ -25,11 +25,11 @@
 import re
 from collections import defaultdict
 
-import f4pga.utils.vpr_io_place as vpr_io_place
-from f4pga.utils.quicklogic.pinmap_parse import read_pinmapfile_data
-from f4pga.utils.quicklogic.pinmap_parse import vec_to_scalar
+import f4pga.aux.utils.vpr_io_place as vpr_io_place
+from f4pga.aux.utils.quicklogic.pinmap_parse import read_pinmapfile_data
+from f4pga.aux.utils.quicklogic.pinmap_parse import vec_to_scalar
 
-from f4pga.utils.pcf import parse_simple_pcf
+from f4pga.aux.utils.pcf import parse_simple_pcf
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/repacker/README.md b/f4pga/aux/utils/quicklogic/repacker/README.md
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/README.md
rename to f4pga/aux/utils/quicklogic/repacker/README.md
diff --git a/f4pga/utils/quicklogic/repacker/arch_xml_utils.py b/f4pga/aux/utils/quicklogic/repacker/arch_xml_utils.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/arch_xml_utils.py
rename to f4pga/aux/utils/quicklogic/repacker/arch_xml_utils.py
diff --git a/f4pga/utils/quicklogic/repacker/block_path.py b/f4pga/aux/utils/quicklogic/repacker/block_path.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/block_path.py
rename to f4pga/aux/utils/quicklogic/repacker/block_path.py
diff --git a/f4pga/utils/quicklogic/repacker/eblif_netlist.py b/f4pga/aux/utils/quicklogic/repacker/eblif_netlist.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/eblif_netlist.py
rename to f4pga/aux/utils/quicklogic/repacker/eblif_netlist.py
diff --git a/f4pga/utils/quicklogic/repacker/netlist_cleaning.py b/f4pga/aux/utils/quicklogic/repacker/netlist_cleaning.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/netlist_cleaning.py
rename to f4pga/aux/utils/quicklogic/repacker/netlist_cleaning.py
diff --git a/f4pga/utils/quicklogic/repacker/packed_netlist.py b/f4pga/aux/utils/quicklogic/repacker/packed_netlist.py
similarity index 99%
rename from f4pga/utils/quicklogic/repacker/packed_netlist.py
rename to f4pga/aux/utils/quicklogic/repacker/packed_netlist.py
index e57e8a546..b8c1aad4a 100644
--- a/f4pga/utils/quicklogic/repacker/packed_netlist.py
+++ b/f4pga/aux/utils/quicklogic/repacker/packed_netlist.py
@@ -25,7 +25,7 @@
 import re
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.repacker.block_path import PathNode
+from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/repacker/pb_rr_graph.py b/f4pga/aux/utils/quicklogic/repacker/pb_rr_graph.py
similarity index 97%
rename from f4pga/utils/quicklogic/repacker/pb_rr_graph.py
rename to f4pga/aux/utils/quicklogic/repacker/pb_rr_graph.py
index 2bbea5278..62b77ceec 100644
--- a/f4pga/utils/quicklogic/repacker/pb_rr_graph.py
+++ b/f4pga/aux/utils/quicklogic/repacker/pb_rr_graph.py
@@ -25,14 +25,14 @@
 
 from enum import Enum
 
-from f4pga.utils.quicklogic.repacker.block_path import PathNode
+from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode
 
-from f4pga.utils.quicklogic.repacker.pb_type import PortType
+from f4pga.aux.utils.quicklogic.repacker.pb_type import PortType
 
-from f4pga.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
-from f4pga.utils.quicklogic.repacker.arch_xml_utils import get_parent_pb
-from f4pga.utils.quicklogic.repacker.arch_xml_utils import yield_pb_children
-from f4pga.utils.quicklogic.repacker.arch_xml_utils import yield_pins
+from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
+from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import get_parent_pb
+from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import yield_pb_children
+from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import yield_pins
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/repacker/pb_rr_graph_netlist.py b/f4pga/aux/utils/quicklogic/repacker/pb_rr_graph_netlist.py
similarity index 98%
rename from f4pga/utils/quicklogic/repacker/pb_rr_graph_netlist.py
rename to f4pga/aux/utils/quicklogic/repacker/pb_rr_graph_netlist.py
index 34f2e7afd..9a5bacec1 100644
--- a/f4pga/utils/quicklogic/repacker/pb_rr_graph_netlist.py
+++ b/f4pga/aux/utils/quicklogic/repacker/pb_rr_graph_netlist.py
@@ -22,9 +22,9 @@
 routing information.
 """
 
-from f4pga.utils.quicklogic.repacker.block_path import PathNode
+from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode
 
-import f4pga.utils.quicklogic.repacker.packed_netlist as packed_netlist
+import f4pga.aux.utils.quicklogic.repacker.packed_netlist as packed_netlist
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/repacker/pb_rr_graph_router.py b/f4pga/aux/utils/quicklogic/repacker/pb_rr_graph_router.py
similarity index 99%
rename from f4pga/utils/quicklogic/repacker/pb_rr_graph_router.py
rename to f4pga/aux/utils/quicklogic/repacker/pb_rr_graph_router.py
index 40302e2c7..af8d4d5f5 100644
--- a/f4pga/utils/quicklogic/repacker/pb_rr_graph_router.py
+++ b/f4pga/aux/utils/quicklogic/repacker/pb_rr_graph_router.py
@@ -23,7 +23,7 @@
 
 import logging
 
-from f4pga.utils.quicklogic.repacker.pb_rr_graph import NodeType
+from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph import NodeType
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/repacker/pb_type.py b/f4pga/aux/utils/quicklogic/repacker/pb_type.py
similarity index 98%
rename from f4pga/utils/quicklogic/repacker/pb_type.py
rename to f4pga/aux/utils/quicklogic/repacker/pb_type.py
index 09b602fcb..7ce4934f5 100644
--- a/f4pga/utils/quicklogic/repacker/pb_type.py
+++ b/f4pga/aux/utils/quicklogic/repacker/pb_type.py
@@ -23,9 +23,9 @@
 from copy import deepcopy
 from enum import Enum
 
-from f4pga.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
+from f4pga.aux.utils.quicklogic.repacker.arch_xml_utils import is_leaf_pbtype
 
-from f4pga.utils.quicklogic.repacker.block_path import PathNode
+from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode
 
 # =============================================================================
 
diff --git a/f4pga/utils/quicklogic/repacker/repack.py b/f4pga/aux/utils/quicklogic/repacker/repack.py
similarity index 98%
rename from f4pga/utils/quicklogic/repacker/repack.py
rename to f4pga/aux/utils/quicklogic/repacker/repack.py
index 03701ba2f..39bccd3c9 100755
--- a/f4pga/utils/quicklogic/repacker/repack.py
+++ b/f4pga/aux/utils/quicklogic/repacker/repack.py
@@ -41,23 +41,21 @@
 import json
 import lxml.etree as ET
 
-from f4pga.utils.quicklogic.repacker.block_path import PathNode
+from f4pga.aux.utils.quicklogic.repacker.block_path import PathNode
 
-from f4pga.utils.quicklogic.repacker.eblif_netlist import Eblif, Cell
-import f4pga.utils.quicklogic.repacker.netlist_cleaning as netlist_cleaning
+from f4pga.aux.utils.quicklogic.repacker.eblif_netlist import Eblif, Cell
+import f4pga.aux.utils.quicklogic.repacker.netlist_cleaning as netlist_cleaning
 
-import f4pga.utils.quicklogic.repacker.packed_netlist as pn
-from f4pga.utils.quicklogic.repacker.packed_netlist import PackedNetlist
-from f4pga.utils.quicklogic.repacker.pb_rr_graph import Graph, NodeType
-from f4pga.utils.quicklogic.repacker.pb_rr_graph_router import Router
+import f4pga.aux.utils.quicklogic.repacker.packed_netlist as pn
+from f4pga.aux.utils.quicklogic.repacker.packed_netlist import PackedNetlist
+from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph import Graph, NodeType
+from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph_router import Router
 
-from f4pga.utils.quicklogic.repacker.pb_rr_graph_netlist import load_clb_nets_into_pb_graph
-from f4pga.utils.quicklogic.repacker.pb_rr_graph_netlist import build_packed_netlist_from_pb_graph
+from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph_netlist import load_clb_nets_into_pb_graph
+from f4pga.aux.utils.quicklogic.repacker.pb_rr_graph_netlist import build_packed_netlist_from_pb_graph
 
-from f4pga.utils.quicklogic.repacker.pb_type import PbType, Model, PortType
-from f4pga.utils.pcf import parse_simple_pcf
-
-# =============================================================================
+from f4pga.aux.utils.quicklogic.repacker.pb_type import PbType, Model, PortType
+from f4pga.aux.utils.pcf import parse_simple_pcf
 
 
 class RepackingRule:
diff --git a/f4pga/utils/quicklogic/repacker/tests/eblif_roundtrip/netlist.golden.eblif b/f4pga/aux/utils/quicklogic/repacker/tests/eblif_roundtrip/netlist.golden.eblif
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/eblif_roundtrip/netlist.golden.eblif
rename to f4pga/aux/utils/quicklogic/repacker/tests/eblif_roundtrip/netlist.golden.eblif
diff --git a/f4pga/utils/quicklogic/repacker/tests/eblif_roundtrip/test_eblif_roundtrip.py b/f4pga/aux/utils/quicklogic/repacker/tests/eblif_roundtrip/test_eblif_roundtrip.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/eblif_roundtrip/test_eblif_roundtrip.py
rename to f4pga/aux/utils/quicklogic/repacker/tests/eblif_roundtrip/test_eblif_roundtrip.py
diff --git a/f4pga/utils/quicklogic/repacker/tests/identity.xsl b/f4pga/aux/utils/quicklogic/repacker/tests/identity.xsl
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/identity.xsl
rename to f4pga/aux/utils/quicklogic/repacker/tests/identity.xsl
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1.eblif b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1.eblif
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1.eblif
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1.eblif
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_0.golden.eblif b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_0.golden.eblif
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_0.golden.eblif
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_0.golden.eblif
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_0.net b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_0.net
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_0.net
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_0.net
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_1.golden.eblif b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_1.golden.eblif
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_1.golden.eblif
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_1.golden.eblif
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_1.net b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_1.net
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_1.net
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_1.net
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_2.golden.eblif b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_2.golden.eblif
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_2.golden.eblif
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_2.golden.eblif
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_2.net b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_2.net
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_2.net
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_2.net
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_3.golden.eblif b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_3.golden.eblif
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_3.golden.eblif
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_3.golden.eblif
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_3.net b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_3.net
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/lut1_3.net
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/lut1_3.net
diff --git a/f4pga/utils/quicklogic/repacker/tests/lut_padding/test_lut_padding.py b/f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/test_lut_padding.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/lut_padding/test_lut_padding.py
rename to f4pga/aux/utils/quicklogic/repacker/tests/lut_padding/test_lut_padding.py
diff --git a/f4pga/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/netlist.golden.net b/f4pga/aux/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/netlist.golden.net
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/netlist.golden.net
rename to f4pga/aux/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/netlist.golden.net
diff --git a/f4pga/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/test_netlist_roundtrip.py b/f4pga/aux/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/test_netlist_roundtrip.py
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/test_netlist_roundtrip.py
rename to f4pga/aux/utils/quicklogic/repacker/tests/packed_netlist_roundtrip/test_netlist_roundtrip.py
diff --git a/f4pga/utils/quicklogic/repacker/tests/sort_netlist.xsl b/f4pga/aux/utils/quicklogic/repacker/tests/sort_netlist.xsl
similarity index 100%
rename from f4pga/utils/quicklogic/repacker/tests/sort_netlist.xsl
rename to f4pga/aux/utils/quicklogic/repacker/tests/sort_netlist.xsl
diff --git a/f4pga/utils/quicklogic/yosys_fixup_cell_names.py b/f4pga/aux/utils/quicklogic/yosys_fixup_cell_names.py
similarity index 100%
rename from f4pga/utils/quicklogic/yosys_fixup_cell_names.py
rename to f4pga/aux/utils/quicklogic/yosys_fixup_cell_names.py
diff --git a/f4pga/utils/vpr_io_place.py b/f4pga/aux/utils/vpr_io_place.py
similarity index 99%
rename from f4pga/utils/vpr_io_place.py
rename to f4pga/aux/utils/vpr_io_place.py
index 42757ae09..1c14e0b4b 100644
--- a/f4pga/utils/vpr_io_place.py
+++ b/f4pga/aux/utils/vpr_io_place.py
@@ -23,7 +23,7 @@
 import re
 import lxml.etree as ET
 
-from f4pga.utils.eblif import parse_blif
+from f4pga.aux.utils.eblif import parse_blif
 
 IoConstraint = namedtuple("IoConstraint", "name x y z comment")
 
diff --git a/f4pga/utils/xc7/create_ioplace.py b/f4pga/aux/utils/xc7/create_ioplace.py
similarity index 98%
rename from f4pga/utils/xc7/create_ioplace.py
rename to f4pga/aux/utils/xc7/create_ioplace.py
index df0f7fee4..b2cae51fc 100644
--- a/f4pga/utils/xc7/create_ioplace.py
+++ b/f4pga/aux/utils/xc7/create_ioplace.py
@@ -29,8 +29,8 @@
 from sys import stdout, stderr, exit as sys_exit
 from json import dump as json_dump, load as json_load
 
-from f4pga.utils.vpr_io_place import IoPlace
-from f4pga.utils.pcf import parse_simple_pcf
+from f4pga.aux.utils.vpr_io_place import IoPlace
+from f4pga.aux.utils.pcf import parse_simple_pcf
 
 
 def p_main(blif, map, net, pcf=None, output=stdout, iostandard_defs_file=None, iostandard="LVCMOS33", drive=12):
diff --git a/f4pga/utils/xc7/create_place_constraints.py b/f4pga/aux/utils/xc7/create_place_constraints.py
similarity index 99%
rename from f4pga/utils/xc7/create_place_constraints.py
rename to f4pga/aux/utils/xc7/create_place_constraints.py
index 6b78be501..f8120d26a 100644
--- a/f4pga/utils/xc7/create_place_constraints.py
+++ b/f4pga/aux/utils/xc7/create_place_constraints.py
@@ -31,7 +31,7 @@
 from pathlib import Path
 from subprocess import run as subprocess_run
 
-from f4pga.utils.eblif import parse_blif
+from f4pga.aux.utils.eblif import parse_blif
 
 
 PlaceConstraint = namedtuple("PlaceConstraint", "name x y z comment")
diff --git a/f4pga/utils/xc7/fix_xc7_carry.py b/f4pga/aux/utils/xc7/fix_xc7_carry.py
similarity index 100%
rename from f4pga/utils/xc7/fix_xc7_carry.py
rename to f4pga/aux/utils/xc7/fix_xc7_carry.py
diff --git a/f4pga/utils/yosys_split_inouts.py b/f4pga/aux/utils/yosys_split_inouts.py
similarity index 100%
rename from f4pga/utils/yosys_split_inouts.py
rename to f4pga/aux/utils/yosys_split_inouts.py
diff --git a/f4pga/flows/platforms.yml b/f4pga/flows/platforms.yml
index c0f5033ac..08d45210e 100644
--- a/f4pga/flows/platforms.yml
+++ b/f4pga/flows/platforms.yml
@@ -91,7 +91,7 @@ xc7a50t: &xc7
       params:
         stage_name: ioplace
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.xc7.create_ioplace']
+        script: ['-m', 'f4pga.aux.utils.xc7.create_ioplace']
         outputs:
           io_place:
             mode: stdout
@@ -107,7 +107,7 @@ xc7a50t: &xc7
       params:
         stage_name: place_constraints
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.xc7.create_place_constraints']
+        script: ['-m', 'f4pga.aux.utils.xc7.create_place_constraints']
         outputs:
           place_constraints:
             mode: stdout
diff --git a/f4pga/wrappers/sh/__init__.py b/f4pga/wrappers/sh/__init__.py
index 4bace9871..9c4227a54 100644
--- a/f4pga/wrappers/sh/__init__.py
+++ b/f4pga/wrappers/sh/__init__.py
@@ -38,8 +38,8 @@
 
 
 if not isQuickLogic:
-    from f4pga.utils.xc7.create_ioplace import main as xc7_create_ioplace
-    from f4pga.utils.xc7.create_place_constraints import main as xc7_create_place_constraints
+    from f4pga.aux.utils.xc7.create_ioplace import main as xc7_create_ioplace
+    from f4pga.aux.utils.xc7.create_place_constraints import main as xc7_create_place_constraints
 
 
 # Helper functions
diff --git a/f4pga/wrappers/tcl/eos-s3.f4pga.tcl b/f4pga/wrappers/tcl/eos-s3.f4pga.tcl
index ea438d95b..2fde00c3c 100644
--- a/f4pga/wrappers/tcl/eos-s3.f4pga.tcl
+++ b/f4pga/wrappers/tcl/eos-s3.f4pga.tcl
@@ -175,7 +175,7 @@ stat
 
 # Write output JSON, fixup cell names using an external Python script
 write_json $::env(OUT_JSON).org.json
-exec $::env(PYTHON3) -m f4pga.utils.quicklogic.yosys_fixup_cell_names $::env(OUT_JSON).org.json $::env(OUT_JSON)
+exec $::env(PYTHON3) -m f4pga.aux.utils.quicklogic.yosys_fixup_cell_names $::env(OUT_JSON).org.json $::env(OUT_JSON)
 
 # Read the fixed JSON back and write verilog
 design -reset
@@ -183,7 +183,7 @@ read_json $::env(OUT_JSON)
 write_verilog $::env(OUT_SYNTH_V)
 
 design -reset
-exec $::env(PYTHON3) -m f4pga.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
+exec $::env(PYTHON3) -m f4pga.aux.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
 read_json $::env(SYNTH_JSON)
 yosys -import
 opt_clean
diff --git a/f4pga/wrappers/tcl/ice40.vpr.f4pga.tcl b/f4pga/wrappers/tcl/ice40.vpr.f4pga.tcl
index a66b89604..7cda3d274 100644
--- a/f4pga/wrappers/tcl/ice40.vpr.f4pga.tcl
+++ b/f4pga/wrappers/tcl/ice40.vpr.f4pga.tcl
@@ -29,7 +29,7 @@ write_json $::env(OUT_JSON)
 write_verilog $::env(OUT_SYNTH_V)
 
 design -reset
-exec $::env(PYTHON3) -m f4pga.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
+exec $::env(PYTHON3) -m f4pga.aux.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
 read_json $::env(SYNTH_JSON)
 yosys -import
 opt_clean
diff --git a/f4pga/wrappers/tcl/qlf_k4n8.f4pga.tcl b/f4pga/wrappers/tcl/qlf_k4n8.f4pga.tcl
index 2c8b7f9d4..d65dcb8eb 100644
--- a/f4pga/wrappers/tcl/qlf_k4n8.f4pga.tcl
+++ b/f4pga/wrappers/tcl/qlf_k4n8.f4pga.tcl
@@ -32,7 +32,7 @@ write_json $::env(OUT_JSON)
 write_verilog $::env(OUT_SYNTH_V)
 
 design -reset
-exec $::env(PYTHON3) -m f4pga.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
+exec $::env(PYTHON3) -m f4pga.aux.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
 read_json $::env(SYNTH_JSON)
 yosys -import
 opt_clean
diff --git a/f4pga/wrappers/tcl/xc7.f4pga.tcl b/f4pga/wrappers/tcl/xc7.f4pga.tcl
index dbab4258c..70d97b14c 100644
--- a/f4pga/wrappers/tcl/xc7.f4pga.tcl
+++ b/f4pga/wrappers/tcl/xc7.f4pga.tcl
@@ -191,7 +191,7 @@ techmap -map  $::env(TECHMAP_PATH)/carry_map.v
 clean_processes
 write_json $::env(OUT_JSON).carry_fixup.json
 
-exec $::env(PYTHON3) -m f4pga.utils.xc7.fix_xc7_carry < $::env(OUT_JSON).carry_fixup.json > $::env(OUT_JSON).carry_fixup_out.json
+exec $::env(PYTHON3) -m f4pga.aux.utils.xc7.fix_xc7_carry < $::env(OUT_JSON).carry_fixup.json > $::env(OUT_JSON).carry_fixup_out.json
 design -push
 read_json $::env(OUT_JSON).carry_fixup_out.json
 
@@ -245,7 +245,7 @@ write_json $::env(OUT_JSON)
 write_verilog $::env(OUT_SYNTH_V)
 
 design -reset
-exec $::env(PYTHON3) -m f4pga.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
+exec $::env(PYTHON3) -m f4pga.aux.utils.yosys_split_inouts -i $::env(OUT_JSON) -o $::env(SYNTH_JSON)
 read_json $::env(SYNTH_JSON)
 yosys -import
 opt_clean

From b8ac98c0fded2b11f8b36bd76602850218de153e Mon Sep 17 00:00:00 2001
From: Pawel Czarnecki <pczarnecki@antmicro.com>
Date: Fri, 12 Aug 2022 15:26:21 +0200
Subject: [PATCH 2/2] f4pga: add f4pga utils command support and add auxDir
 builtin variable

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
---
 f4pga/flows/__init__.py                     |   6 +-
 f4pga/flows/argparser.py                    |  13 +-
 f4pga/flows/commands.py                     |  11 +-
 f4pga/flows/common.py                       |   1 +
 f4pga/flows/flow.py                         |   6 +-
 f4pga/flows/module.py                       |   4 +-
 f4pga/flows/platforms.yml                   |  27 ++--
 f4pga/flows/runner.py                       |   8 +-
 f4pga/fpga_map.json                         |  12 ++
 f4pga/setup.py                              |   3 +
 f4pga/util.py                               | 132 ++++++++++++++++++++
 f4pga/wrappers/sh/__init__.py               |  14 +--
 f4pga/wrappers/sh/quicklogic/ql.f4pga.sh    |   2 +-
 f4pga/wrappers/sh/quicklogic/synth.f4pga.sh |   2 +-
 f4pga/wrappers/tcl/eos-s3.f4pga.tcl         |   2 +-
 15 files changed, 211 insertions(+), 32 deletions(-)
 create mode 100644 f4pga/fpga_map.json
 create mode 100644 f4pga/util.py

diff --git a/f4pga/flows/__init__.py b/f4pga/flows/__init__.py
index 5663a9dd6..af61731ef 100755
--- a/f4pga/flows/__init__.py
+++ b/f4pga/flows/__init__.py
@@ -42,7 +42,7 @@
 from f4pga.flows.stage import Stage
 from f4pga.flows.common import set_verbosity_level, sfprint
 from f4pga.flows.argparser import setup_argparser
-from f4pga.flows.commands import cmd_build, cmd_show_dependencies, f4pga_done
+from f4pga.flows.commands import cmd_build, cmd_show_dependencies, cmd_run_util, f4pga_done
 
 
 def platform_stages(platform_flow, r_env):
@@ -78,6 +78,10 @@ def main():
         cmd_show_dependencies(args)
         f4pga_done()
 
+    if args.command == "utils":
+        cmd_run_util(args)
+        f4pga_done()
+
     sfprint(0, "Please use a command.\nUse `--help` flag to learn more.")
     f4pga_done()
 
diff --git a/f4pga/flows/argparser.py b/f4pga/flows/argparser.py
index 8a159180f..24ce9d124 100644
--- a/f4pga/flows/argparser.py
+++ b/f4pga/flows/argparser.py
@@ -17,7 +17,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-from argparse import ArgumentParser, Namespace
+from argparse import ArgumentParser, Namespace, REMAINDER
 from re import finditer as re_finditer
 
 
@@ -67,6 +67,14 @@ def p_setup_show_dep_parser(parser: ArgumentParser):
     p_add_flow_arg(parser)
 
 
+def _setup_utils_parser(parser: ArgumentParser):
+    parser.add_argument("--function", "-f", metavar="fun_name", type=str, help="Run specific funtion from given module")
+
+    parser.add_argument("util", metavar="util_name", type=str, help="Name of the script to call")
+
+    parser.add_argument("util_args", metavar="util_args", nargs=REMAINDER, type=str, help="Arguments for called script")
+
+
 def setup_argparser():
     """
     Set up argument parser for the program.
@@ -82,6 +90,9 @@ def setup_argparser():
     show_dep = subparsers.add_parser("showd", description="Show the value(s) assigned to a dependency")
     p_setup_show_dep_parser(show_dep)
 
+    run_util = subparsers.add_parser("utils", description="Run utility script")
+    _setup_utils_parser(run_util)
+
     return parser
 
 
diff --git a/f4pga/flows/commands.py b/f4pga/flows/commands.py
index 82784ef8a..0f171a9a9 100644
--- a/f4pga/flows/commands.py
+++ b/f4pga/flows/commands.py
@@ -30,6 +30,7 @@
 from f4pga.flows.common import (
     bin_dir_path,
     share_dir_path,
+    aux_dir_path,
     F4PGAException,
     ResolutionEnv,
     fatal,
@@ -50,6 +51,7 @@
 from f4pga.flows.flow import Flow
 from f4pga.flows.stage import Stage
 from f4pga.flows.inspector import get_module_info
+from f4pga.util import Util
 
 
 ROOT = Path(__file__).resolve().parent
@@ -121,7 +123,7 @@ def f4pga_done():
 def setup_resolution_env():
     """Sets up a ResolutionEnv with default built-ins."""
 
-    r_env = ResolutionEnv({"shareDir": share_dir_path, "binDir": bin_dir_path})
+    r_env = ResolutionEnv({"shareDir": share_dir_path, "binDir": bin_dir_path, "auxDir": aux_dir_path})
 
     def _noisy_warnings():
         """
@@ -299,3 +301,10 @@ def cmd_show_dependencies(args: Namespace):
         sfprint(0, prstr)
 
     set_verbosity_level(-1)
+
+
+def cmd_run_util(args: Namespace):
+    """Run utility script"""
+
+    util = Util(args.util, args.function, args.util_args)
+    util.exec()
diff --git a/f4pga/flows/common.py b/f4pga/flows/common.py
index 35c7bd057..c2fd96aff 100644
--- a/f4pga/flows/common.py
+++ b/f4pga/flows/common.py
@@ -30,6 +30,7 @@
 
 bin_dir_path = str(Path(sys_argv[0]).resolve().parent.parent)
 share_dir_path = str(F4PGA_SHARE_DIR)
+aux_dir_path = str(Path(__file__).resolve().parent.parent / "aux")
 
 
 class F4PGAException(Exception):
diff --git a/f4pga/flows/flow.py b/f4pga/flows/flow.py
index 9352d6208..5ee13213f 100644
--- a/f4pga/flows/flow.py
+++ b/f4pga/flows/flow.py
@@ -21,7 +21,7 @@
 
 from colorama import Fore, Style
 
-from f4pga.flows.common import deep, sfprint, bin_dir_path, share_dir_path, F4PGAException
+from f4pga.flows.common import deep, sfprint, bin_dir_path, share_dir_path, aux_dir_path, F4PGAException
 from f4pga.flows.cache import F4Cache
 from f4pga.flows.flow_config import FlowConfig
 from f4pga.flows.runner import ModRunCtx, module_map, module_exec
@@ -103,7 +103,9 @@ def _config_mod_runctx(
             elif config_paths.get(prod.name):
                 produces[prod.name] = config_paths[prod.name]
 
-        return ModRunCtx(share_dir_path, bin_dir_path, {"takes": takes, "produces": produces, "values": values})
+        return ModRunCtx(
+            share_dir_path, bin_dir_path, aux_dir_path, {"takes": takes, "produces": produces, "values": values}
+        )
 
     @staticmethod
     def _cache_deps(path: str, f4cache: F4Cache):
diff --git a/f4pga/flows/module.py b/f4pga/flows/module.py
index 0e25b7b12..47f0dfaa4 100644
--- a/f4pga/flows/module.py
+++ b/f4pga/flows/module.py
@@ -74,6 +74,7 @@ class ModuleContext:
 
     share: str  #  Absolute path to F4PGA's share directory
     bin: str  #  Absolute path to F4PGA's bin directory
+    aux: str  #  Absolute path to F4PGA's aux directory
     takes: SimpleNamespace  #  Maps symbolic dependency names to relative paths.
     produces: SimpleNamespace  #  Contains mappings for explicitely specified dependencies.
     #  Useful mostly for checking for on-demand optional outputs (such as logs) with
@@ -101,7 +102,7 @@ def _getreqmaybe(self, obj, deps: "list[str]", deps_cfg: "dict[str, ]"):
             setattr(obj, name, self.r_env.resolve(value))
 
     # `config` should be a dictionary given as modules input.
-    def __init__(self, module: Module, config: "dict[str, ]", r_env: ResolutionEnv, share: str, bin: str):
+    def __init__(self, module: Module, config: "dict[str, ]", r_env: ResolutionEnv, share: str, bin: str, aux: str):
         self.module_name = module.name
         self.takes = SimpleNamespace()
         self.produces = SimpleNamespace()
@@ -110,6 +111,7 @@ def __init__(self, module: Module, config: "dict[str, ]", r_env: ResolutionEnv,
         self.r_env = r_env
         self.share = share
         self.bin = bin
+        self.aux = aux
 
         self._getreqmaybe(self.takes, module.takes, config["takes"])
         self._getreqmaybe(self.values, module.values, config["values"])
diff --git a/f4pga/flows/platforms.yml b/f4pga/flows/platforms.yml
index 08d45210e..30e60daea 100644
--- a/f4pga/flows/platforms.yml
+++ b/f4pga/flows/platforms.yml
@@ -282,13 +282,13 @@ ql-eos-s3:
           PINMAP_FILE: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
           PCF_FILE: '${:pcf}'
           PYTHON3: '${python3}'
-          UTILS_PATH: '${shareDir}/scripts'
+          UTILS_PATH: '${auxDir}/utils'
     prepare_sdc:
       module: 'generic_script_wrapper'
       params:
         stage_name: prepare_sdc
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.quicklogic.process_sdc_constraints']
+        script: "${auxDir}/utils/quicklogic/process_sdc_constraints.py"
         outputs:
           sdc:
             mode: file
@@ -300,7 +300,7 @@ ql-eos-s3:
           sdc-out: '${:eblif[noext]}.sdc'
           pcf: '${:pcf}'
           pin-map: ''
-          $PYTHONPATH: '${shareDir}/scripts/'
+          $PYTHONPATH: "${auxDir}/utils/quicklogic"
     pack:
       module: 'pack'
       values:
@@ -342,7 +342,7 @@ ql-eos-s3:
       params:
         stage_name: ioplace
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.quicklogic.pp3.create_ioplace']
+        script: "${auxDir}/utils/quicklogic/pp3/create_ioplace.py"
         outputs:
           io_place:
             mode: stdout
@@ -352,13 +352,13 @@ ql-eos-s3:
           net: '${:net}'
           pcf: '${:pcf}'
           map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
-          $PYTHONPATH: '${shareDir}/scripts/'
+          $PYTHONPATH: "${auxDir}/utils/"
     place_constraints:
       module: 'generic_script_wrapper'
       params:
         stage_name: place_constraints
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.quicklogic.pp3.create_place_constraints']
+        script: "${auxDir}/utils/quicklogic/pp3/create_place_constraints.py"
         outputs:
           place_constraints:
             mode: stdout
@@ -367,7 +367,7 @@ ql-eos-s3:
           blif: '${:eblif}'
           map: '${shareDir}/arch/ql-eos-s3_wlcsp/clkmap_${package}.csv'
           i: '${:io_place}'
-          $PYTHONPATH: '${shareDir}/scripts/'
+          $PYTHONPATH: "${auxDir}/utils/"
     place:
       module: 'place'
     iomux_jlink:
@@ -375,7 +375,7 @@ ql-eos-s3:
       params:
         stage_name: iomux_jlink
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.quicklogic.pp3.eos-s3.iomux_config']
+        script: "${auxDir}/utils/quicklogic/pp3/eos-s3/iomux_config.py"
         outputs:
           iomux_jlink:
             mode: stdout
@@ -385,13 +385,13 @@ ql-eos-s3:
           pcf: '${:pcf}'
           map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
           output-format: jlink
-          $PYTHONPATH: '${shareDir}/scripts/'
+          $PYTHONPATH: "${auxDir}/utils/"
     iomux_openocd:
       module: 'generic_script_wrapper'
       params:
         stage_name: iomux_openocd
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.quicklogic.pp3.eos-s3.iomux_config']
+        script: "${auxDir}/utils/quicklogic/pp3/eos-s3/iomux_config.py"
         outputs:
           iomux_openocd:
             mode: stdout
@@ -401,13 +401,13 @@ ql-eos-s3:
           pcf: '${:pcf}'
           map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
           output-format: openocd
-          $PYTHONPATH: '${shareDir}/scripts/'
+          $PYTHONPATH: "${auxDir}/utils/"
     iomux_binary:
       module: 'generic_script_wrapper'
       params:
         stage_name: iomux_binary
         interpreter: '${python3}'
-        script: ['-m', 'f4pga.utils.quicklogic.pp3.eos-s3.iomux_config']
+        script: "${auxDir}/utils/quicklogic/pp3/eos-s3/iomux_config.py"
         outputs:
           iomux_binary:
             mode: stdout
@@ -417,7 +417,7 @@ ql-eos-s3:
           pcf: '${:pcf}'
           map: '${shareDir}/arch/ql-eos-s3_wlcsp/pinmap_${package}.csv'
           output-format: binary
-          $PYTHONPATH: '${shareDir}/scripts/'
+          $PYTHONPATH: "${auxDir}/utils/"
     route:
       module: 'route'
       values:
@@ -616,6 +616,7 @@ ql-eos-s3:
           $FPGA_FAM: eos-s3
           $PATH: '${shareDir}/../../conda/envs/eos-s3/bin/:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin'
           $BIN_DIR_PATH: '${binDir}'
+          $PYTHONPATH: "${auxDir}/utils/quicklogic/pp3"
 
 
 ql-k4n8_fast: &ql-k4n8
diff --git a/f4pga/flows/runner.py b/f4pga/flows/runner.py
index 92711cbec..c2418d779 100644
--- a/f4pga/flows/runner.py
+++ b/f4pga/flows/runner.py
@@ -73,11 +73,13 @@ def get_module(path: str):
 class ModRunCtx:
     share: str
     bin: str
+    aux: str
     config: "dict[str, ]"
 
-    def __init__(self, share: str, bin: str, config: "dict[str, ]"):
+    def __init__(self, share: str, bin: str, aux: str, config: "dict[str, ]"):
         self.share = share
         self.bin = bin
+        self.aux = aux
         self.config = config
 
     def make_r_env(self):
@@ -110,7 +112,7 @@ def module_io(module: Module):
 
 def module_map(module: Module, ctx: ModRunCtx):
     try:
-        mod_ctx = ModuleContext(module, ctx.config, ctx.make_r_env(), ctx.share, ctx.bin)
+        mod_ctx = ModuleContext(module, ctx.config, ctx.make_r_env(), ctx.share, ctx.bin, ctx.aux)
     except Exception as e:
         raise ModuleFailException(module.name, "map", e)
 
@@ -119,7 +121,7 @@ def module_map(module: Module, ctx: ModRunCtx):
 
 def module_exec(module: Module, ctx: ModRunCtx):
     try:
-        mod_ctx = ModuleContext(module, ctx.config, ctx.make_r_env(), ctx.share, ctx.bin)
+        mod_ctx = ModuleContext(module, ctx.config, ctx.make_r_env(), ctx.share, ctx.bin, ctx.aux)
     except Exception as e:
         raise ModuleFailException(module.name, "exec", e)
 
diff --git a/f4pga/fpga_map.json b/f4pga/fpga_map.json
new file mode 100644
index 000000000..9738b0e7a
--- /dev/null
+++ b/f4pga/fpga_map.json
@@ -0,0 +1,12 @@
+{
+	"xc7": {
+		"manufacturer": "xilinx"
+	},
+	"eos-s3": {
+		"manufacturer": "quicklogic",
+		"architecture": "pp3"
+	},
+	"qlf_k4n8": {
+		"manufacturer": "quicklogic"
+	}
+}
diff --git a/f4pga/setup.py b/f4pga/setup.py
index 44a5a8b0f..5060bcdb8 100644
--- a/f4pga/setup.py
+++ b/f4pga/setup.py
@@ -82,6 +82,9 @@ def get_requirements(file: Path) -> List[str]:
     url="https://github.com/chipsalliance/f4pga",
     package_dir={"f4pga": "."},
     package_data={
+        "f4pga": [
+            "fpga_map.json",
+        ],
         "f4pga.flows": [
             "*.yml",
         ],
diff --git a/f4pga/util.py b/f4pga/util.py
new file mode 100644
index 000000000..9ec7e3d23
--- /dev/null
+++ b/f4pga/util.py
@@ -0,0 +1,132 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+"""
+Utility scripts handler
+"""
+
+from subprocess import check_call
+from shutil import which
+from os import environ, strerror
+from pathlib import Path
+import errno
+import json
+import pkgutil
+
+# import warnings
+import importlib
+
+import f4pga.aux.utils
+from f4pga.flows.common import sfprint
+
+# from f4pga.aux.utils import *
+
+
+class Util:
+    """
+    Wrapper for internal python utils
+    """
+
+    def _set_fpga_data(self):
+        fpga_map = open(self.root_dir / "fpga_map.json")
+        fmap = json.load(fpga_map)
+
+        self.architectures = fmap.keys()
+
+        for fpga_fam, fpga_data in fmap.items():
+            if self.fpga_fam == fpga_fam:
+                self.manufacturer = fpga_data["manufacturer"]
+                if "architecture" in fpga_data.keys():
+                    self.arch = fpga_data["architecture"]
+                    self.subarch = fpga_fam
+                else:
+                    self.arch = fpga_fam
+                    self.subarch = None
+                break
+
+    def __init__(self, name, function, args):
+        self.name = name
+        self.function = function
+        self.args = args
+        self.env = environ.copy()
+        self.fpga_fam = self.env.get("FPGA_FAM", "xc7")
+        self.root_dir = Path(__file__).resolve().parent
+        self._set_fpga_data()
+
+    def _get_util_path(self):
+        man = self.manufacturer
+        arch = self.arch
+        subarch = self.subarch
+        script_name = self.name + ".py"
+
+        if subarch is not None:
+            util_path = "f4pga.aux.utils." + man + "." + arch + "." + subarch + "." + self.name
+            subarch_path = self.root_dir / "aux" / "utils" / man / arch / subarch / script_name
+            if subarch_path.is_file():
+                return util_path
+
+        util_path = "f4pga.aux.utils." + man + "." + arch + "." + self.name
+        arch_path = self.root_dir / "aux" / "utils" / man / arch / script_name
+        if arch_path.is_file():
+            return util_path
+
+        util_path = "f4pga.aux.utils." + man + "." + self.name
+        manufacturer_path = self.root_dir / "aux" / "utils" / man / script_name
+        if manufacturer_path.is_file():
+            return util_path
+
+        # Look through other directories common for the manufacturer
+        manufacturer_path = (self.root_dir / "aux" / "utils" / man).rglob("*")
+        manufacturer_dirs = [
+            man_dir.stem for man_dir in manufacturer_path if (man_dir.is_dir() and man_dir not in self.architectures)
+        ]
+        for man_dir in manufacturer_dirs:
+            util_path = "f4pga.aux.utils." + man + "." + man_dir + "." + self.name
+            manufacturer_path = self.root_dir / "aux" / "utils" / man / man_dir / script_name
+            if manufacturer_path.is_file():
+                return util_path
+
+        util_path = "f4pga.aux.utils." + self.name
+        common_path = self.root_dir / "aux" / "utils" / script_name
+        if common_path.is_file():
+            return util_path
+        else:
+            if subarch is not None:
+                raise FileNotFoundError(
+                    errno.ENOENT,
+                    strerror(errno.ENOENT),
+                    str(common_path)
+                    + " or "
+                    + str(manufacturer_path)
+                    + " or "
+                    + str(arch_path)
+                    + " or "
+                    + str(subarch_path),
+                )
+            else:
+                raise FileNotFoundError(
+                    errno.ENOENT,
+                    strerror(errno.ENOENT),
+                    str(common_path) + " or " + str(manufacturer_path) + " or " + str(arch_path),
+                )
+        return util_path
+
+    def exec(self):
+        util_path = self._get_util_path()
+        check_call([which("python3"), "-m", util_path] + self.args, env=self.env)
diff --git a/f4pga/wrappers/sh/__init__.py b/f4pga/wrappers/sh/__init__.py
index 9c4227a54..b29129758 100644
--- a/f4pga/wrappers/sh/__init__.py
+++ b/f4pga/wrappers/sh/__init__.py
@@ -411,7 +411,7 @@ def generate_constraints():
     exit -1
   fi
 
-  '{python3}' -m f4pga.utils.quicklogic.qlf_k4n8.create_ioplace \
+  f4pga utils create_ioplace \
     --pcf '{pcf}' \
     --blif '{eblif}' \
     --pinmap_xml '{archs_dir}'/"${{DEVICE_PATH}}_${{DEVICE_PATH}}/${{PINMAPXML}}" \
@@ -435,14 +435,14 @@ def generate_constraints():
   DEVICE_PATH='{device}_wlcsp'
   PINMAP='{archs_dir}'/"${{DEVICE_PATH}}/${{PINMAPCSV}}"
 
-  '{python3}' -m f4pga.utils.quicklogic.pp3.create_ioplace \
+  f4pga utils create_ioplace \
     --pcf '{pcf}' \
     --blif '{eblif}' \
     --map "$PINMAP" \
     --net '{net}' \
     > '{place_file_prefix}_io.place'
 
-  '{python3}' -m f4pga.utils.quicklogic.pp3.create_place_constraints \
+  f4pga utils create_place_constraints \
     --blif '{eblif}' \
     --map '{archs_dir}'/"${{DEVICE_PATH}}/${{CLKMAPCSV}}" \
     -i '{place_file_prefix}_io.place' \
@@ -454,7 +454,7 @@ def generate_constraints():
             + "\n".join(
                 [
                     f"""
-    '{python3}' -m f4pga.utils.quicklogic.pp3.eos-s3.iomux_config \
+    f4pga utils iomux_config \
       --eblif '{eblif}' \
       --pcf '{pcf}' \
       --map "$PINMAP" \
@@ -685,7 +685,7 @@ def repack():
 """
         + f"""
 PYTHONPATH='{F4PGA_SHARE_DIR}/scripts':$PYTHONPATH \
-  '{python3}' -m f4pga.utils.quicklogic.repacker.repack \
+  f4pga utils repack \
     --vpr-arch ${{ARCH_DEF}} \
     --repacking-rules ${{ARCH_DIR}}/${{DEVICE_NAME}}.repacking_rules.json \
     $JSON_ARGS \
@@ -748,7 +748,7 @@ def generate_libfile():
 PINMAP_XML=${ARCH_DIR}/${PINMAPXML}
 """
         + f"""
-'{python3}' -m f4pga.utils.quicklogic.create_lib \
+f4pga utils create_lib \
   -n "${{DEV}}_0P72_SSM40" \
   -m fpga_top \
   -c '{part}' \
@@ -792,7 +792,7 @@ def fasm2bels():
 
     p_run_bash_cmds(
         f"""
-'{python3}' -m f4pga.utils.quicklogic.pp3.fasm2bels '{args.bit}' \
+f4pga utils fasm2bels '{args.bit}' \
   --phy-db '{F4PGA_SHARE_DIR}/arch/{args.device}_wlcsp/db_phy.pickle' \
   --device-name "${{DEVICE/ql-/}}" \
   --package-name '{args.part}' \
diff --git a/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh b/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
index b22f86ae6..f2ca78066 100755
--- a/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
+++ b/f4pga/wrappers/sh/quicklogic/ql.f4pga.sh
@@ -339,7 +339,7 @@ all: \${BUILDDIR}/\${TOP}.${RUN_TILL}\n\
 	cd \${BUILDDIR} && symbiflow_synth -t \${TOP} -v \${VERILOG} -F \${FAMILY} -d \${DEVICE} -p \${PCF} -P \${PART} ${COMPILE_EXTRA_ARGS[*]} > $LOG_FILE 2>&1\n\
 \n\
 \${BUILDDIR}/\${TOP}.sdc: \${BUILDDIR}/\${TOP}.eblif\n\
-	python3 -m f4pga.utils.quicklogic.process_sdc_constraints --sdc-in \${SDC_IN} --sdc-out \$@ --pcf \${PCF} --eblif \${BUILDDIR}/\${TOP}.eblif --pin-map \${PINMAP_CSV}\n\
+	f4pga utils process_sdc_constraints --sdc-in \${SDC_IN} --sdc-out \$@ --pcf \${PCF} --eblif \${BUILDDIR}/\${TOP}.eblif --pin-map \${PINMAP_CSV}\n\
 \n\
 \${BUILDDIR}/\${TOP}.net: \${BUILDDIR}/\${TOP}.eblif \${BUILDDIR}/\${TOP}.sdc\n\
 	cd \${BUILDDIR} && symbiflow_pack -e \${TOP}.eblif -f \${FAMILY} -d \${DEVICE} -s \${SDC} -c \${PNR_CORNER} >> $LOG_FILE 2>&1\n\
diff --git a/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh b/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
index 232f67f07..2f2f0ad89 100755
--- a/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
+++ b/f4pga/wrappers/sh/quicklogic/synth.f4pga.sh
@@ -107,7 +107,7 @@ else
   fi
 fi
 
-yosys_cmds=`echo ${EXTRA_ARGS[*]} | python3 -m f4pga.utils.quicklogic.convert_compile_opts`
+yosys_cmds=`echo ${EXTRA_ARGS[*]} | f4pga utils convert_compile_opts`
 if [ ! -z "${yosys_cmds}" ]; then yosys_cmds="${yosys_cmds//$'\n'/'; '}; "; fi
 
 yosys_read_cmds=''
diff --git a/f4pga/wrappers/tcl/eos-s3.f4pga.tcl b/f4pga/wrappers/tcl/eos-s3.f4pga.tcl
index 2fde00c3c..d5f78ef06 100644
--- a/f4pga/wrappers/tcl/eos-s3.f4pga.tcl
+++ b/f4pga/wrappers/tcl/eos-s3.f4pga.tcl
@@ -175,7 +175,7 @@ stat
 
 # Write output JSON, fixup cell names using an external Python script
 write_json $::env(OUT_JSON).org.json
-exec $::env(PYTHON3) -m f4pga.aux.utils.quicklogic.yosys_fixup_cell_names $::env(OUT_JSON).org.json $::env(OUT_JSON)
+exec f4pga utils yosys_fixup_cell_names $::env(OUT_JSON).org.json $::env(OUT_JSON)
 
 # Read the fixed JSON back and write verilog
 design -reset