From cfdde77d8cb817f0265b8f06dd51f8cef933a1c3 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Date: Wed, 13 Dec 2023 21:01:55 -0500
Subject: [PATCH] [nfc] Fix formatting

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
---
 spec.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec.md b/spec.md
index 9ca74076..d008df51 100644
--- a/spec.md
+++ b/spec.md
@@ -825,6 +825,7 @@ For example:
 Probe<UInt<8>, A.B>     ; A.B is a layer
 RWProbe<UInt<8>, A.B>
 ```
+
 Probes are generally lowered to hierarchical names in Verilog.
 For details, see the FIRRTL ABI Specification.