From 572384b8605b8cb6a48ef1a836e807858b6a3f00 Mon Sep 17 00:00:00 2001
From: SyedHassanUlHaq <21b-029-cs@students.uit.edu>
Date: Sat, 17 Aug 2024 03:28:06 +0500
Subject: [PATCH 1/5] [GSOC] integrated support for Zvkg instructions

[GSOC] removed wrong valid vlen constraint for Zvkg

[GSOC] fixed
---
 Makefile                   |  2 +-
 Makefrag                   |  2 ++
 configs/vghsh.vv.toml      | 19 +++++++++++++++++++
 configs/vgmul.vv.toml      | 19 +++++++++++++++++++
 generator/insn_util.go     |  6 +++++-
 generator/insn_vdvs2.go    | 26 ++++++++++++++++++--------
 generator/insn_vdvs2vs1.go | 12 +++++++++++-
 main.go                    | 11 ++++++++++-
 8 files changed, 85 insertions(+), 12 deletions(-)
 create mode 100644 configs/vghsh.vv.toml
 create mode 100644 configs/vgmul.vv.toml

diff --git a/Makefile b/Makefile
index f2cb136..8b5c0cc 100644
--- a/Makefile
+++ b/Makefile
@@ -55,7 +55,7 @@ CONFIGS = configs/
 
 SPIKE = spike
 PATCHER_SPIKE = build/pspike
-MARCH = rv${XLEN}gcv_zvbb
+MARCH = rv${XLEN}gcv_zvbb_zvkg
 MABI = lp64d
 
 ifeq ($(XLEN), 32)
diff --git a/Makefrag b/Makefrag
index 3a5244a..b6f3b9a 100644
--- a/Makefrag
+++ b/Makefrag
@@ -409,6 +409,8 @@ tests = \
   vfwsub_wf-0 \
   vfwsub_wf-1 \
   vfwsub_wv-0 \
+  vghsh_vv-0 \
+  vgmul_vv-0 \
   vid_v-0 \
   vid_v-1 \
   viota_m-0 \
diff --git a/configs/vghsh.vv.toml b/configs/vghsh.vv.toml
new file mode 100644
index 0000000..125ea25
--- /dev/null
+++ b/configs/vghsh.vv.toml
@@ -0,0 +1,19 @@
+name = "vghsh.vv"
+format = "vd,vs2,vs1"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+
+sew32 = [
+    [0xfffffff8, 0x00000000],
+    [0xffffff80, 0xfffffff8],
+    [0x00007fff, 0x00000000],
+    [0x00007fff, 0x000007ff],
+    [0x00007fff, 0x00000001],
+    [0xffffffff, 0x00000000],
+    [0xffffffff, 0xffffffff]
+]
diff --git a/configs/vgmul.vv.toml b/configs/vgmul.vv.toml
new file mode 100644
index 0000000..6dfd925
--- /dev/null
+++ b/configs/vgmul.vv.toml
@@ -0,0 +1,19 @@
+name = "vgmul.vv"
+format = "vd,vs2"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+
+sew32 = [
+    [0xfffffff8, 0x00000000],
+    [0xffffff80, 0xfffffff8],
+    [0x00007fff, 0x00000000],
+    [0x00007fff, 0x000007ff],
+    [0x00007fff, 0x00000001],
+    [0xffffffff, 0x00000000],
+    [0xffffffff, 0xffffffff]
+]
diff --git a/generator/insn_util.go b/generator/insn_util.go
index da9d91d..9bd352d 100644
--- a/generator/insn_util.go
+++ b/generator/insn_util.go
@@ -83,6 +83,10 @@ func (l LMUL) String() string {
 
 type VLEN int
 
+func (v VLEN) Zvkg_validVLEN() bool{
+	return 128 <= v && v <= 4096 && v&(v-1) == 0
+}
+
 func (v VLEN) Valid() bool {
 	return 64 <= v && v <= 4096 && v&(v-1) == 0
 }
@@ -179,4 +183,4 @@ func getVRegs(lmul1 LMUL, v0 bool, seed string) (int, int, int) {
 	})
 
 	return availableOptions[0], availableOptions[1], availableOptions[2]
-}
+}
\ No newline at end of file
diff --git a/generator/insn_vdvs2.go b/generator/insn_vdvs2.go
index 80fc614..d3fa37e 100644
--- a/generator/insn_vdvs2.go
+++ b/generator/insn_vdvs2.go
@@ -9,16 +9,28 @@ import (
 )
 
 func (i *Insn) genCodeVdVs2(pos int) []string {
-	s := regexp.MustCompile(`vmv(\d)r.v`)
-	nr, err := strconv.Atoi(s.FindStringSubmatch(i.Name)[1])
-	if err != nil {
-		log.Fatal("unreachable")
+	zvkg_insn := strings.HasPrefix(i.Name, "vg")
+	sew32_only := iff(zvkg_insn, []SEW{32}, allSEWs)
+
+	var nr int
+	var err error
+
+	if match := regexp.MustCompile(`vmv(\d+)r.v`).FindStringSubmatch(i.Name); len(match) > 1 {
+		nr, err = strconv.Atoi(match[1])
+		if err != nil {
+			log.Fatalf("Error parsing register number: %v", err)
+		}
 	}
 
-	combinations := i.combinations([]LMUL{LMUL(nr)}, allSEWs, []bool{false}, i.vxrms())
+
+	combinations := i.combinations(iff(zvkg_insn, []LMUL{1, 2, 4, 8}, []LMUL{LMUL(nr)}), iff(zvkg_insn, sew32_only, allSEWs), []bool{false}, i.vxrms())
 	res := make([]string, 0, len(combinations))
 
 	for _, c := range combinations[pos:] {
+		if zvkg_insn && c.Vl % 4 != 0 {
+			c.Vl = (c.Vl + 3) / 4 * 4 
+		}
+
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
 
@@ -32,8 +44,7 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 
 		builder.WriteString("# -------------- TEST BEGIN --------------\n")
 		builder.WriteString(i.gVsetvli(c.Vl, c.SEW, c.LMUL))
-		builder.WriteString(fmt.Sprintf("%s v%d, v%d\n",
-			i.Name, vd, vs2))
+		builder.WriteString(fmt.Sprintf("%s v%d, v%d\n", i.Name, vd, vs2))
 		builder.WriteString("# -------------- TEST END   --------------\n")
 
 		builder.WriteString(i.gResultDataAddr())
@@ -41,7 +52,6 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 		builder.WriteString(i.gMagicInsn(vd, c.LMUL))
 
 		res = append(res, builder.String())
-
 	}
 
 	return res
diff --git a/generator/insn_vdvs2vs1.go b/generator/insn_vdvs2vs1.go
index 8d4a542..16aec4d 100644
--- a/generator/insn_vdvs2vs1.go
+++ b/generator/insn_vdvs2vs1.go
@@ -6,9 +6,19 @@ import (
 )
 
 func (i *Insn) genCodeVdVs2Vs1(pos int) []string {
-	combinations := i.combinations(allLMULs, allSEWs, []bool{false}, i.vxrms())
+	zvkg_insn := strings.HasPrefix(i.Name, "vg")
+	sew32_only := iff(zvkg_insn, []SEW{32}, allSEWs)
+	combinations := i.combinations(
+		iff(zvkg_insn, []LMUL{1, 2, 4, 8}, allLMULs),
+		iff(zvkg_insn, sew32_only, allSEWs),
+		[]bool{false},
+		i.vxrms(),
+	)
 	res := make([]string, 0, len(combinations))
 	for _, c := range combinations[pos:] {
+		if zvkg_insn && c.Vl % 4 != 0 {
+			c.Vl = (c.Vl + 3) / 4 * 4 
+		}
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
 
diff --git a/main.go b/main.go
index 92ed088..dace841 100644
--- a/main.go
+++ b/main.go
@@ -100,6 +100,15 @@ func main() {
 			}
 			insn, err := generator.ReadInsnFromToml(contents, option)
 			fatalIf(err)
+
+			if strings.HasPrefix(insn.Name, "vg") && !option.VLEN.Zvkg_validVLEN() {
+                lk.Lock()
+                fmt.Printf("\033[0;1;31mskipping:\033[0m %s, VLEN is not greater than or equal to 128\n", name)
+                lk.Unlock()
+                wg.Done()
+                return
+            }
+
 			if insn.Name != strings.Replace(file.Name(), ".toml", "", -1) {
 				fatalIf(errors.New("filename and instruction name unmatched"))
 			}
@@ -130,4 +139,4 @@ func writeTo(path string, name string, contents string) {
 	fatalIf(err)
 	err = os.WriteFile(filepath.Join(path, name), []byte(contents), 0644)
 	fatalIf(err)
-}
+}
\ No newline at end of file

From e91d776c3576767e1309c9fadc9b6b0bb852c4eb Mon Sep 17 00:00:00 2001
From: SyedHassanUlHaq <21b-029-cs@students.uit.edu>
Date: Mon, 19 Aug 2024 17:33:19 +0500
Subject: [PATCH 2/5] [GSOC] added configs for Zvbc insn

---
 Makefile                |  2 +-
 configs/vclmul.vv.toml  | 22 ++++++++++++++++++++++
 configs/vclmul.vx.toml  | 22 ++++++++++++++++++++++
 configs/vclmulh.vv.toml | 21 +++++++++++++++++++++
 configs/vclmulh.vx.toml | 21 +++++++++++++++++++++
 5 files changed, 87 insertions(+), 1 deletion(-)
 create mode 100644 configs/vclmul.vv.toml
 create mode 100644 configs/vclmul.vx.toml
 create mode 100644 configs/vclmulh.vv.toml
 create mode 100644 configs/vclmulh.vx.toml

diff --git a/Makefile b/Makefile
index 8b5c0cc..67c9056 100644
--- a/Makefile
+++ b/Makefile
@@ -55,7 +55,7 @@ CONFIGS = configs/
 
 SPIKE = spike
 PATCHER_SPIKE = build/pspike
-MARCH = rv${XLEN}gcv_zvbb_zvkg
+MARCH = rv${XLEN}gcv_zvbb_zvbc_zvkg
 MABI = lp64d
 
 ifeq ($(XLEN), 32)
diff --git a/configs/vclmul.vv.toml b/configs/vclmul.vv.toml
new file mode 100644
index 0000000..1436385
--- /dev/null
+++ b/configs/vclmul.vv.toml
@@ -0,0 +1,22 @@
+name = "vclmul.vv"
+format = "vd,vs2,vs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]
\ No newline at end of file
diff --git a/configs/vclmul.vx.toml b/configs/vclmul.vx.toml
new file mode 100644
index 0000000..5ed75b1
--- /dev/null
+++ b/configs/vclmul.vx.toml
@@ -0,0 +1,22 @@
+name = "vclmul.vx"
+format = "vd,vs2,rs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]
+
diff --git a/configs/vclmulh.vv.toml b/configs/vclmulh.vv.toml
new file mode 100644
index 0000000..06c7161
--- /dev/null
+++ b/configs/vclmulh.vv.toml
@@ -0,0 +1,21 @@
+name = "vclmulh.vv"
+format = "vd,vs2,vs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]
\ No newline at end of file
diff --git a/configs/vclmulh.vx.toml b/configs/vclmulh.vx.toml
new file mode 100644
index 0000000..750f4e3
--- /dev/null
+++ b/configs/vclmulh.vx.toml
@@ -0,0 +1,21 @@
+name = "vclmulh.vx"
+format = "vd,vs2,rs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]
\ No newline at end of file

From b38eb22fb76afaf8f7b590042e4df8cf07062d68 Mon Sep 17 00:00:00 2001
From: SyedHassanUlHaq <21b-029-cs@students.uit.edu>
Date: Mon, 19 Aug 2024 17:43:44 +0500
Subject: [PATCH 3/5] [GSOC] modified generator for Zvbc

---
 Makefrag                     | 6 ++++++
 generator/insn_vdvs2rs1vm.go | 4 +++-
 generator/insn_vdvs2vs1vm.go | 4 +++-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/Makefrag b/Makefrag
index b6f3b9a..925c1fd 100644
--- a/Makefrag
+++ b/Makefrag
@@ -215,6 +215,12 @@ tests = \
   vasubu_vx-9 \
   vbrev8_v-0 \
   vbrev_v-0 \
+  vclmul_vv-0 \
+  vclmul_vx-0 \
+  vclmul_vx-1 \
+  vclmulh_vv-0 \
+  vclmulh_vx-0 \
+  vclmulh_vx-1 \
   vclz_v-0 \
   vcompress_vm-0 \
   vcpop_m-0 \
diff --git a/generator/insn_vdvs2rs1vm.go b/generator/insn_vdvs2rs1vm.go
index 39b1993..0bceab9 100644
--- a/generator/insn_vdvs2rs1vm.go
+++ b/generator/insn_vdvs2rs1vm.go
@@ -9,12 +9,14 @@ import (
 func (i *Insn) genCodeVdVs2Rs1Vm(pos int) []string {
 	vdWidening := strings.HasPrefix(i.Name, "vw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wx")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdSize := iff(vdWidening, 2, 1)
 	vs2Size := iff(vs2Widening, 2, 1)
 
 	sews := iff(vdWidening || vs2Widening, allSEWs[:len(allSEWs)-1], allSEWs)
+	sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, allLMULs),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),
diff --git a/generator/insn_vdvs2vs1vm.go b/generator/insn_vdvs2vs1vm.go
index 5f65162..904b5b3 100644
--- a/generator/insn_vdvs2vs1vm.go
+++ b/generator/insn_vdvs2vs1vm.go
@@ -8,6 +8,7 @@ import (
 
 func (i *Insn) genCodeVdVs2Vs1Vm(pos int) []string {
 	float := strings.HasPrefix(i.Name, "vf") || strings.HasPrefix(i.Name, "vmf")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdWidening := strings.HasPrefix(i.Name, "vw") || strings.HasPrefix(i.Name, "vfw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wv")
 	vdSize := iff(vdWidening, 2, 1)
@@ -15,8 +16,9 @@ func (i *Insn) genCodeVdVs2Vs1Vm(pos int) []string {
 
 	sews := iff(float, floatSEWs, allSEWs)
 	sews = iff(vdWidening || vs2Widening, sews[:len(sews)-1], sews)
+	sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, allLMULs),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),

From b9c9f6d90207aaf6d6e41d7cdfbf5d3363355ae7 Mon Sep 17 00:00:00 2001
From: SyedHassanUlHaq <21b-029-cs@students.uit.edu>
Date: Tue, 20 Aug 2024 14:46:56 +0500
Subject: [PATCH 4/5] [GSOC] added allowed LMUL for Zvkg

---
 generator/insn_util.go     | 19 +++++++++++++++----
 generator/insn_vdvs2.go    | 13 ++++++++++---
 generator/insn_vdvs2vs1.go |  3 ++-
 main.go                    |  8 --------
 4 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/generator/insn_util.go b/generator/insn_util.go
index 9bd352d..3821523 100644
--- a/generator/insn_util.go
+++ b/generator/insn_util.go
@@ -81,12 +81,23 @@ func (l LMUL) String() string {
 	return fmt.Sprintf("m%d", int(l))
 }
 
-type VLEN int
-
-func (v VLEN) Zvkg_validVLEN() bool{
-	return 128 <= v && v <= 4096 && v&(v-1) == 0
+func ZvkgAllowedLMULs(vlen VLEN) []LMUL {
+	switch vlen {
+	case 64:
+		return []LMUL{2, 4, 8}
+	case 128:
+		return []LMUL{1, 2, 4, 8}
+	case 256:
+		return []LMUL{LMUL(1) / 2, 1, 2, 4, 8}
+	case 512:
+		return []LMUL{LMUL(1) / 4, LMUL(1) / 2, 1, 2, 4, 8}
+	default:
+		return allLMULs
+	}
 }
 
+type VLEN int
+
 func (v VLEN) Valid() bool {
 	return 64 <= v && v <= 4096 && v&(v-1) == 0
 }
diff --git a/generator/insn_vdvs2.go b/generator/insn_vdvs2.go
index d3fa37e..b110383 100644
--- a/generator/insn_vdvs2.go
+++ b/generator/insn_vdvs2.go
@@ -22,8 +22,9 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 		}
 	}
 
+	vlen := i.Option.VLEN
 
-	combinations := i.combinations(iff(zvkg_insn, []LMUL{1, 2, 4, 8}, []LMUL{LMUL(nr)}), iff(zvkg_insn, sew32_only, allSEWs), []bool{false}, i.vxrms())
+	combinations := i.combinations(iff(zvkg_insn, ZvkgAllowedLMULs(vlen), []LMUL{LMUL(nr)}), iff(zvkg_insn, sew32_only, allSEWs), []bool{false}, i.vxrms())
 	res := make([]string, 0, len(combinations))
 
 	for _, c := range combinations[pos:] {
@@ -33,10 +34,16 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
+		
+		var vd, vs2 int
+		if (zvkg_insn){
+			vd = int(c.LMUL1)
+			vs2 = 3 * int(c.LMUL1)
+		}else{
+			vd, vs2, _ = getVRegs(c.LMUL, true, i.Name)
+		}
 
-		vd, vs2, _ := getVRegs(c.LMUL, true, i.Name)
 		builder.WriteString(i.gWriteRandomData(c.LMUL * 2))
-
 		builder.WriteString(i.gLoadDataIntoRegisterGroup(vd, c.LMUL, c.SEW))
 		builder.WriteString(fmt.Sprintf("li t1, %d\n", int(c.LMUL)*i.vlenb()))
 		builder.WriteString(fmt.Sprintf("add a0, a0, t1\n"))
diff --git a/generator/insn_vdvs2vs1.go b/generator/insn_vdvs2vs1.go
index 16aec4d..6f9c7ca 100644
--- a/generator/insn_vdvs2vs1.go
+++ b/generator/insn_vdvs2vs1.go
@@ -8,8 +8,9 @@ import (
 func (i *Insn) genCodeVdVs2Vs1(pos int) []string {
 	zvkg_insn := strings.HasPrefix(i.Name, "vg")
 	sew32_only := iff(zvkg_insn, []SEW{32}, allSEWs)
+	vlen := i.Option.VLEN
 	combinations := i.combinations(
-		iff(zvkg_insn, []LMUL{1, 2, 4, 8}, allLMULs),
+		iff(zvkg_insn, ZvkgAllowedLMULs(vlen), allLMULs),
 		iff(zvkg_insn, sew32_only, allSEWs),
 		[]bool{false},
 		i.vxrms(),
diff --git a/main.go b/main.go
index dace841..1bb7e6d 100644
--- a/main.go
+++ b/main.go
@@ -101,14 +101,6 @@ func main() {
 			insn, err := generator.ReadInsnFromToml(contents, option)
 			fatalIf(err)
 
-			if strings.HasPrefix(insn.Name, "vg") && !option.VLEN.Zvkg_validVLEN() {
-                lk.Lock()
-                fmt.Printf("\033[0;1;31mskipping:\033[0m %s, VLEN is not greater than or equal to 128\n", name)
-                lk.Unlock()
-                wg.Done()
-                return
-            }
-
 			if insn.Name != strings.Replace(file.Name(), ".toml", "", -1) {
 				fatalIf(errors.New("filename and instruction name unmatched"))
 			}

From 22f5c5ecc7434678b680c9bcc119736c31e55faf Mon Sep 17 00:00:00 2001
From: SyedHassanUlHaq <21b-029-cs@students.uit.edu>
Date: Wed, 21 Aug 2024 03:33:05 +0500
Subject: [PATCH 5/5] [GSOC] removed unnecessary allowedLMUL func for zvkg

---
 Makefrag                   |  1 -
 generator/insn_util.go     | 15 ---------------
 generator/insn_vdvs2.go    |  6 ++----
 generator/insn_vdvs2vs1.go |  7 +++----
 4 files changed, 5 insertions(+), 24 deletions(-)

diff --git a/Makefrag b/Makefrag
index 925c1fd..62347e9 100644
--- a/Makefrag
+++ b/Makefrag
@@ -416,7 +416,6 @@ tests = \
   vfwsub_wf-1 \
   vfwsub_wv-0 \
   vghsh_vv-0 \
-  vgmul_vv-0 \
   vid_v-0 \
   vid_v-1 \
   viota_m-0 \
diff --git a/generator/insn_util.go b/generator/insn_util.go
index 3821523..4d2e426 100644
--- a/generator/insn_util.go
+++ b/generator/insn_util.go
@@ -81,21 +81,6 @@ func (l LMUL) String() string {
 	return fmt.Sprintf("m%d", int(l))
 }
 
-func ZvkgAllowedLMULs(vlen VLEN) []LMUL {
-	switch vlen {
-	case 64:
-		return []LMUL{2, 4, 8}
-	case 128:
-		return []LMUL{1, 2, 4, 8}
-	case 256:
-		return []LMUL{LMUL(1) / 2, 1, 2, 4, 8}
-	case 512:
-		return []LMUL{LMUL(1) / 4, LMUL(1) / 2, 1, 2, 4, 8}
-	default:
-		return allLMULs
-	}
-}
-
 type VLEN int
 
 func (v VLEN) Valid() bool {
diff --git a/generator/insn_vdvs2.go b/generator/insn_vdvs2.go
index b110383..b3da463 100644
--- a/generator/insn_vdvs2.go
+++ b/generator/insn_vdvs2.go
@@ -10,7 +10,7 @@ import (
 
 func (i *Insn) genCodeVdVs2(pos int) []string {
 	zvkg_insn := strings.HasPrefix(i.Name, "vg")
-	sew32_only := iff(zvkg_insn, []SEW{32}, allSEWs)
+	sews := iff(zvkg_insn, []SEW{32}, allSEWs)
 
 	var nr int
 	var err error
@@ -22,9 +22,7 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 		}
 	}
 
-	vlen := i.Option.VLEN
-
-	combinations := i.combinations(iff(zvkg_insn, ZvkgAllowedLMULs(vlen), []LMUL{LMUL(nr)}), iff(zvkg_insn, sew32_only, allSEWs), []bool{false}, i.vxrms())
+	combinations := i.combinations([]LMUL{LMUL(nr)}, sews, []bool{false}, i.vxrms())
 	res := make([]string, 0, len(combinations))
 
 	for _, c := range combinations[pos:] {
diff --git a/generator/insn_vdvs2vs1.go b/generator/insn_vdvs2vs1.go
index 6f9c7ca..0ba8be6 100644
--- a/generator/insn_vdvs2vs1.go
+++ b/generator/insn_vdvs2vs1.go
@@ -7,11 +7,10 @@ import (
 
 func (i *Insn) genCodeVdVs2Vs1(pos int) []string {
 	zvkg_insn := strings.HasPrefix(i.Name, "vg")
-	sew32_only := iff(zvkg_insn, []SEW{32}, allSEWs)
-	vlen := i.Option.VLEN
+	sews := iff(zvkg_insn, []SEW{32}, allSEWs)
 	combinations := i.combinations(
-		iff(zvkg_insn, ZvkgAllowedLMULs(vlen), allLMULs),
-		iff(zvkg_insn, sew32_only, allSEWs),
+		allLMULs,
+		sews,
 		[]bool{false},
 		i.vxrms(),
 	)