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.gitmodules
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[submodule "third_party/tests/hdlconvertor"]
path = third_party/tests/hdlconvertor
url = https://github.com/Nic30/hdlConvertor
[submodule "third_party/cores/basejump_stl"]
path = third_party/cores/basejump_stl
url = https://github.com/bespoke-silicon-group/basejump_stl
[submodule "third_party/cores/ariane"]
path = third_party/cores/ariane
url = https://github.com/pulp-platform/ariane
[submodule "third_party/tools/odin_ii"]
path = third_party/tools/odin_ii
url = https://github.com/verilog-to-routing/vtr-verilog-to-routing.git
[submodule "third_party/tools/icarus"]
path = third_party/tools/icarus
url = https://github.com/steveicarus/iverilog.git
[submodule "third_party/tools/verilator"]
path = third_party/tools/verilator
url = https://github.com/verilator/verilator.git
[submodule "third_party/tools/slang"]
path = third_party/tools/slang
url = https://github.com/MikePopoloski/slang.git
[submodule "third_party/tools/yosys"]
path = third_party/tools/yosys
url = https://github.com/YosysHQ/yosys.git
[submodule "third_party/tools/zachjs-sv2v"]
path = third_party/tools/zachjs-sv2v
url = https://github.com/zachjs/sv2v
[submodule "third_party/cores/veer-eh1"]
path = third_party/cores/veer-eh1
url = https://github.com/chipsalliance/Cores-VeeR-EH1
[submodule "third_party/cores/ibex"]
path = third_party/cores/ibex
url = https://github.com/lowRISC/ibex
[submodule "third_party/tools/tree-sitter-verilog"]
path = third_party/tools/tree-sitter-verilog
url = https://github.com/tree-sitter/tree-sitter-verilog
[submodule "third_party/tools/tree-sitter-systemverilog"]
path = third_party/tools/tree-sitter-systemverilog
url = https://github.com/gmlarumbe/tree-sitter-systemverilog
[submodule "third_party/cores/fx68k"]
path = third_party/cores/fx68k
url = https://github.com/ijor/fx68k
[submodule "third_party/tools/sv-parser"]
path = third_party/tools/sv-parser
url = https://github.com/dalance/sv-parser
[submodule "third_party/cores/scr1"]
path = third_party/cores/scr1
url = https://github.com/syntacore/scr1
[submodule "third_party/tools/verible"]
path = third_party/tools/verible
url = https://github.com/chipsalliance/verible.git
[submodule "third_party/tools/Surelog"]
path = third_party/tools/Surelog
url = https://github.com/chipsalliance/Surelog.git
[submodule "third_party/cores/rsd"]
path = third_party/cores/rsd
url = https://github.com/rsd-devel/rsd
[submodule "third_party/tests/ivtest"]
path = third_party/tests/ivtest
url = https://github.com/steveicarus/ivtest.git
[submodule "third_party/cores/opentitan"]
path = third_party/cores/opentitan
url = https://github.com/lowRISC/opentitan.git
[submodule "third_party/cores/black-parrot"]
path = third_party/cores/black-parrot
url = https://github.com/black-parrot/black-parrot
branch = dev
[submodule "third_party/tests/easyUVM"]
path = third_party/tests/easyUVM
url = https://github.com/antmicro/easyUVM.git
[submodule "third_party/tests/uvm"]
path = third_party/tests/uvm
url = https://github.com/SymbiFlow/uvm.git
[submodule "third_party/cores/tnoc"]
path = third_party/cores/tnoc
url = https://github.com/taichi-ishitani/tnoc.git
[submodule "third_party/tests/utd-sv"]
path = third_party/tests/utd-sv
url = https://github.com/SymbiFlow/utd-sv.git
[submodule "third_party/tests/axi-vip"]
path = third_party/tests/axi-vip
url = https://github.com/SymbiFlow/axi-vip.git
[submodule "third_party/tools/synlig"]
path = third_party/tools/synlig
url = https://github.com/chipsalliance/synlig.git
[submodule "third_party/tests/projf-explore"]
path = third_party/tests/projf-explore
url = https://github.com/projf/projf-explore.git
[submodule "third_party/tools/verilator-uhdm"]
path = third_party/tools/verilator-uhdm
url = https://github.com/antmicro/verilator
[submodule "third_party/tools/moore"]
path = third_party/tools/moore
url = https://github.com/fabianschuiki/moore.git
[submodule "third_party/cores/rggen-sample"]
path = third_party/cores/rggen-sample
url = https://github.com/rggen/rggen-sample.git
[submodule "third_party/cores/rggen-sv-rtl"]
path = third_party/cores/rggen-sv-rtl
url = https://github.com/rggen/rggen-sv-rtl.git
[submodule "third_party/cores/veer-el2"]
path = third_party/cores/veer-el2
url = https://github.com/chipsalliance/Cores-VeeR-EL2.git
[submodule "third_party/tools/yosys-slang"]
path = third_party/tools/yosys-slang
url = https://github.com/povik/yosys-slang.git
[submodule "third_party/tools/circt-verilog"]
path = third_party/tools/circt-verilog
url = https://github.com/llvm/circt.git
branch = main