diff --git a/configgen/generated/blastoise.json b/configgen/generated/blastoise.json
index d0e26eb82..290ef86c1 100644
--- a/configgen/generated/blastoise.json
+++ b/configgen/generated/blastoise.json
@@ -6,86 +6,6 @@
       "Zve32f"
     ],
     "t1customInstructions": [],
-    "lsuBankParameters": [
-      {
-        "name": "scalar",
-        "region": "b00??????????????????????????????",
-        "beatbyte": 8,
-        "accessScalar": true
-      },
-      {
-        "name": "ddrBank0",
-        "region": "b01???????????????????????00?????\nb10???????????????????????00?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank1",
-        "region": "b01???????????????????????01?????\nb10???????????????????????01?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank2",
-        "region": "b01???????????????????????10?????\nb10???????????????????????10?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank3",
-        "region": "b01???????????????????????11?????\nb10???????????????????????11?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank0",
-        "region": "b11000000000?????????????000?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank1",
-        "region": "b11000000000?????????????001?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank2",
-        "region": "b11000000000?????????????010?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank3",
-        "region": "b11000000000?????????????011?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank4",
-        "region": "b11000000000?????????????100?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank5",
-        "region": "b11000000000?????????????101?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank6",
-        "region": "b11000000000?????????????110?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank7",
-        "region": "b11000000000?????????????111?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      }
-    ],
     "vrfBankSize": 1,
     "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rwp1rw",
     "vfuInstantiateParameter": {
@@ -246,7 +166,8 @@
             3
           ]
         ]
-      ]
+      ],
+      "zvbbModuleParameters": []
     }
   },
   "generator": "org.chipsalliance.t1.rtl.T1"
diff --git a/configgen/generated/machamp.json b/configgen/generated/machamp.json
index dc0a4b2d9..ceeaf5e59 100644
--- a/configgen/generated/machamp.json
+++ b/configgen/generated/machamp.json
@@ -6,86 +6,6 @@
       "Zve32x"
     ],
     "t1customInstructions": [],
-    "lsuBankParameters": [
-      {
-        "name": "scalar",
-        "region": "b00??????????????????????????????",
-        "beatbyte": 8,
-        "accessScalar": true
-      },
-      {
-        "name": "ddrBank0",
-        "region": "b01??????????????????????00??????\nb10??????????????????????00??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank1",
-        "region": "b01??????????????????????01??????\nb10??????????????????????01??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank2",
-        "region": "b01??????????????????????10??????\nb10??????????????????????10??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank3",
-        "region": "b01??????????????????????11??????\nb10??????????????????????11??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank0",
-        "region": "b11000000000????????????000??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank1",
-        "region": "b11000000000????????????001??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank2",
-        "region": "b11000000000????????????010??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank3",
-        "region": "b11000000000????????????011??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank4",
-        "region": "b11000000000????????????100??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank5",
-        "region": "b11000000000????????????101??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank6",
-        "region": "b11000000000????????????110??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank7",
-        "region": "b11000000000????????????111??????",
-        "beatbyte": 8,
-        "accessScalar": false
-      }
-    ],
     "vrfBankSize": 2,
     "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rp1w",
     "vfuInstantiateParameter": {
@@ -230,7 +150,8 @@
           ]
         ]
       ],
-      "floatModuleParameters": []
+      "floatModuleParameters": [],
+      "zvbbModuleParameters": []
     }
   },
   "generator": "org.chipsalliance.t1.rtl.T1"
diff --git a/configgen/generated/psyduck.json b/configgen/generated/psyduck.json
index 97d364b3d..04a2f3572 100644
--- a/configgen/generated/psyduck.json
+++ b/configgen/generated/psyduck.json
@@ -7,86 +7,6 @@
       "Zvbb"
     ],
     "t1customInstructions": [],
-    "lsuBankParameters": [
-      {
-        "name": "scalar",
-        "region": "b00??????????????????????????????",
-        "beatbyte": 8,
-        "accessScalar": true
-      },
-      {
-        "name": "ddrBank0",
-        "region": "b01???????????????????????00?????\nb10???????????????????????00?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank1",
-        "region": "b01???????????????????????01?????\nb10???????????????????????01?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank2",
-        "region": "b01???????????????????????10?????\nb10???????????????????????10?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank3",
-        "region": "b01???????????????????????11?????\nb10???????????????????????11?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank0",
-        "region": "b11000000000?????????????000?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank1",
-        "region": "b11000000000?????????????001?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank2",
-        "region": "b11000000000?????????????010?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank3",
-        "region": "b11000000000?????????????011?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank4",
-        "region": "b11000000000?????????????100?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank5",
-        "region": "b11000000000?????????????101?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank6",
-        "region": "b11000000000?????????????110?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank7",
-        "region": "b11000000000?????????????111?????",
-        "beatbyte": 8,
-        "accessScalar": false
-      }
-    ],
     "vrfBankSize": 1,
     "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rwp1rw",
     "vfuInstantiateParameter": {
diff --git a/configgen/generated/sandslash.json b/configgen/generated/sandslash.json
index 5ae0cb6b3..688085fe1 100644
--- a/configgen/generated/sandslash.json
+++ b/configgen/generated/sandslash.json
@@ -6,134 +6,6 @@
       "Zve32x"
     ],
     "t1customInstructions": [],
-    "lsuBankParameters": [
-      {
-        "name": "scalar",
-        "region": "b00??????????????????????????????",
-        "beatbyte": 8,
-        "accessScalar": true
-      },
-      {
-        "name": "ddrBank0",
-        "region": "b01?????????????????????00???????\nb10?????????????????????00???????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank1",
-        "region": "b01?????????????????????01???????\nb10?????????????????????01???????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank2",
-        "region": "b01?????????????????????10???????\nb10?????????????????????10???????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "ddrBank3",
-        "region": "b01?????????????????????11???????\nb10?????????????????????11???????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank0",
-        "region": "b1100000000?????????0000?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank1",
-        "region": "b1100000000?????????0001?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank2",
-        "region": "b1100000000?????????0010?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank3",
-        "region": "b1100000000?????????0011?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank4",
-        "region": "b1100000000?????????0100?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank5",
-        "region": "b1100000000?????????0101?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank6",
-        "region": "b1100000000?????????0110?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank7",
-        "region": "b1100000000?????????0111?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank8",
-        "region": "b1100000000?????????1000?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank9",
-        "region": "b1100000000?????????1001?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank10",
-        "region": "b1100000000?????????1010?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank11",
-        "region": "b1100000000?????????1011?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank12",
-        "region": "b1100000000?????????1100?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank13",
-        "region": "b1100000000?????????1101?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank14",
-        "region": "b1100000000?????????1110?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      },
-      {
-        "name": "sramBank15",
-        "region": "b1100000000?????????1111?????????",
-        "beatbyte": 8,
-        "accessScalar": false
-      }
-    ],
     "vrfBankSize": 4,
     "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rw",
     "vfuInstantiateParameter": {
@@ -278,7 +150,8 @@
           ]
         ]
       ],
-      "floatModuleParameters": []
+      "floatModuleParameters": [],
+      "zvbbModuleParameters": []
     }
   },
   "generator": "org.chipsalliance.t1.rtl.T1"
diff --git a/configgen/src/Main.scala b/configgen/src/Main.scala
index 43e2c2dac..88e3bc326 100644
--- a/configgen/src/Main.scala
+++ b/configgen/src/Main.scala
@@ -119,29 +119,6 @@ object Main {
       dLen,
       extensions = Seq("Zve32f", "Zvbb"),
       t1customInstructions = Nil,
-      lsuBankParameters =
-        // scalar bank 0-1G
-        Seq(
-          BitSet(BitPat("b00??????????????????????????????"))
-        ).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
-          // ddr bank 1G-3G 512M/bank
-          Seq(
-            BitSet(BitPat("b01???????????????????????00?????"), BitPat("b10???????????????????????00?????")),
-            BitSet(BitPat("b01???????????????????????01?????"), BitPat("b10???????????????????????01?????")),
-            BitSet(BitPat("b01???????????????????????10?????"), BitPat("b10???????????????????????10?????")),
-            BitSet(BitPat("b01???????????????????????11?????"), BitPat("b10???????????????????????11?????"))
-          ).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
-          // sRam bank 3G+ 256K/bank, 8banks
-          Seq(
-            BitSet(BitPat("b11000000000?????????????000?????")),
-            BitSet(BitPat("b11000000000?????????????001?????")),
-            BitSet(BitPat("b11000000000?????????????010?????")),
-            BitSet(BitPat("b11000000000?????????????011?????")),
-            BitSet(BitPat("b11000000000?????????????100?????")),
-            BitSet(BitPat("b11000000000?????????????101?????")),
-            BitSet(BitPat("b11000000000?????????????110?????")),
-            BitSet(BitPat("b11000000000?????????????111?????"))
-          ).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
       vrfBankSize = 1,
       vrfRamType = RamType.p0rwp1rw,
       vfuInstantiateParameter = VFUInstantiateParameter(
diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala
index d38f0a53a..611986746 100644
--- a/t1/src/LaneZvbb.scala
+++ b/t1/src/LaneZvbb.scala
@@ -49,7 +49,7 @@ class LaneZvbb(val parameter: LaneZvbbParam)
   val zvbbROL = zvbbSrc.rotateLeft(zvbbRs(4, 0)).asUInt
   val zvbbROR = zvbbSrc.rotateRight(zvbbRs(4, 0)).asUInt
 
-  val zvbbSLL64 = (0.U((parameter.datapathWidth-1).W) ## zvbbSrc.zext).asUInt << zvbbRs(5, 0) 
+  val zvbbSLL64 = (0.U((parameter.datapathWidth).W) ## zvbbSrc(parameter.datapathWidth-1, 0)).asUInt << zvbbRs(5, 0)
   val zvbbSLL = zvbbSLL64(parameter.datapathWidth-1, 0)
   val zvbbSLLMSB = zvbbSLL64(2*parameter.datapathWidth-1, parameter.datapathWidth)
   
diff --git a/t1/src/decoder/attribute/isScheduler.scala b/t1/src/decoder/attribute/isScheduler.scala
index c65b78bce..423b59a35 100644
--- a/t1/src/decoder/attribute/isScheduler.scala
+++ b/t1/src/decoder/attribute/isScheduler.scala
@@ -274,5 +274,5 @@ object isScheduler {
 }
 
 case class isScheduler(value: TriState) extends BooleanDecodeAttribute {
-  override val description: String = "lane will send request to Sequencer and wait ack from Sequencer.\ninstructions that will communicate with T1 top module.*/ "
+  override val description: String = "lane will send request to Sequencer and wait ack from Sequencer. Instructions that will communicate with T1 top module.*/ "
 }