From 252e48abc111aa2b9285be8c3632c1fab3af37d7 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sun, 28 Jul 2024 16:52:21 +0800 Subject: [PATCH] [ipemu] gate dpi call with !reset to work around verilator scheduling bug --- ipemu/src/TestBench.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index d58e14513..30c30c154 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -113,7 +113,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) val issue = WireDefault(0.U.asTypeOf(new Issue)) val fence = RegInit(false.B) val outstanding = RegInit(0.U(4.W)) - val doIssue: Bool = dut.io.issue.ready && !fence + val doIssue: Bool = dut.io.issue.ready && !fence && !reset outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid // used to gate Xprop when DPI hasn't issued yet. val didIssue = RegNext(doIssue || didIssue, false.B)