From 4401ddf4eeae529e3b3c78c17df068e6f7353ac7 Mon Sep 17 00:00:00 2001
From: Clo91eaf <Clo91eaf@qq.com>
Date: Mon, 22 Jul 2024 20:22:12 +0800
Subject: [PATCH] [rocketemu] refactor AXI read functions and remove the read
 alignment

---
 rocketemu/driver/src/dpi.rs | 18 ++++++++--------
 rocketemu/driver/src/sim.rs | 42 +++++++------------------------------
 2 files changed, 16 insertions(+), 44 deletions(-)

diff --git a/rocketemu/driver/src/dpi.rs b/rocketemu/driver/src/dpi.rs
index 1a36c4d18..8731ee1f2 100644
--- a/rocketemu/driver/src/dpi.rs
+++ b/rocketemu/driver/src/dpi.rs
@@ -91,7 +91,7 @@ unsafe extern "C" fn axi_write_loadStoreAXI_rs(
   payload: *const SvBitVecVal,
 ) {
   debug!(
-    "axi_write_loadStore (channel_id={channel_id}, awid={awid}, awaddr={awaddr:#x}, \
+    "axi_write_loadStoreAXI (channel_id={channel_id}, awid={awid}, awaddr={awaddr:#x}, \
   awlen={awlen}, awsize=2^{awsize}, awburst={awburst}, awlock={awlock}, awcache={awcache}, \
   awprot={awprot}, awqos={awqos}, awregion={awregion})"
   );
@@ -118,12 +118,12 @@ unsafe extern "C" fn axi_read_loadStoreAXI_rs(
   payload: *mut SvBitVecVal,
 ) {
   debug!(
-    "axi_read_highBandwidth (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
+    "axi_read_loadStoreAXI (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
   arlen={arlen}, arsize={arsize}, arburst={arburst}, arlock={arlock}, arcache={arcache}, \
   arprot={arprot}, arqos={arqos}, arregion={arregion})"
   );
   let sim = &mut *(target as *mut Simulator);
-  let response = sim.axi_read_load_store(araddr as u32, arsize as u64);
+  let response = sim.axi_read(araddr as u32, arsize as u64);
   fill_axi_read_payload(payload, sim.dlen, &response.data);
 }
 
@@ -144,21 +144,21 @@ unsafe extern "C" fn axi_read_instructionFetchAXI_rs(
   payload: *mut SvBitVecVal,
 ) {
   debug!(
-    "axi_read_indexed (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
+    "axi_read_instructionFetchAXI (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
   arlen={arlen}, arsize={arsize}, arburst={arburst}, arlock={arlock}, arcache={arcache}, \
   arprot={arprot}, arqos={arqos}, arregion={arregion})"
   );
-  let driver = &mut *(target as *mut Simulator);
-  let response = driver.axi_read_instruction(araddr as u32, arsize as u64);
-  fill_axi_read_payload(payload, driver.dlen, &response.data);
+  let sim = &mut *(target as *mut Simulator);
+  let response = sim.axi_read(araddr as u32, arsize as u64);
+  fill_axi_read_payload(payload, sim.dlen, &response.data);
 }
 
 #[no_mangle]
 unsafe extern "C" fn cosim_init_rs(call_init: *mut SvBit) -> *mut () {
   let args = SimulationArgs::parse();
   *call_init = 1;
-  let driver = Box::new(Simulator::new(args));
-  Box::into_raw(driver) as *mut ()
+  let sim = Box::new(Simulator::new(args));
+  Box::into_raw(sim) as *mut ()
 }
 
 #[no_mangle]
diff --git a/rocketemu/driver/src/sim.rs b/rocketemu/driver/src/sim.rs
index ed2e0a137..92ee6c3d4 100644
--- a/rocketemu/driver/src/sim.rs
+++ b/rocketemu/driver/src/sim.rs
@@ -260,48 +260,20 @@ impl Simulator {
     self.write_mem(addr, self.dlen / 8, strobe, data);
   }
 
-  fn read_mem(&mut self, addr: u32, size: u32, alignment_bytes: u32) -> Vec<u8> {
+  fn read_mem(&mut self, addr: u32, size: u32) -> Vec<u8> {
     assert!(
-      addr % size == 0 || addr % alignment_bytes == 0,
-      "unaligned access addr={addr} size={size}bytes dlen={alignment_bytes}bytes"
+      addr % size == 0,
+      "unaligned access addr={addr} size={size}bytes"
     );
-    let residue_addr = addr % alignment_bytes;
-    let aligned_addr = addr - residue_addr;
-    if size < alignment_bytes {
-      // narrow
-      (0..alignment_bytes)
-        .map(|i| {
-          let i_addr = aligned_addr + i;
-          if addr <= i_addr && i_addr < addr + size {
-            self.mem[i_addr as usize]
-          } else {
-            0
-          }
-        })
-        .collect()
-    } else {
-      // normal
-      (0..size).map(|i| self.mem[(addr + i) as usize]).collect()
-    }
-  }
-
-  pub fn axi_read_instruction(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
-    let size = 1 << arsize; // size in bytes
-    let data = self.read_mem(addr, size, 4);
-    let data_hex = hex::encode(&data);
-    info!(
-      "[{}] axi_read_indexed (addr={addr:#x}, size={size}, data={data_hex})",
-      0
-    );
-    AxiReadPayload { data }
+    (0..size).map(|i| self.mem[(addr + i) as usize]).collect()
   }
 
-  pub(crate) fn axi_read_load_store(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
+  pub fn axi_read(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
     let size = 1 << arsize; // size in bytes
-    let data = self.read_mem(addr, size, self.dlen / 8);
+    let data = self.read_mem(addr, size);
     let data_hex = hex::encode(&data);
     info!(
-      "[{}] axi_read_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})",
+      "[{}] axi_read (addr={addr:#x}, size={size}, data={data_hex})",
       0
     );
     AxiReadPayload { data }