From cbdaa374ce272674f8a79bb7672a9b5afa675277 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Sun, 28 Jul 2024 17:56:56 +0800
Subject: [PATCH] [rtl] init sram.

---
 t1/src/vrf/VRF.scala | 33 ++++++++++++++++++++++++---------
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
index b142191f8..b7c7f88df 100644
--- a/t1/src/vrf/VRF.scala
+++ b/t1/src/vrf/VRF.scala
@@ -215,6 +215,14 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
   @public
   val loadDataInLSUWriteQueue: UInt = IO(Input(UInt(parameter.chainingSize.W)))
 
+  // reset sram
+  val sramReady: Bool = RegInit(false.B)
+  val sramResetCount: UInt = RegInit(0.U(log2Ceil(parameter.rfDepth).W))
+  val resetValid: Bool = !sramReady
+  when(resetValid) {
+    sramResetCount := sramResetCount + 1.U
+    when(sramResetCount.andR) { sramReady := true.B }
+  }
   // TODO: add Chaining Check Probe
 
   // todo: delete
@@ -316,7 +324,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
         // if there are additional read port for the bank.
         (bank & (~readPortCheckSelect)).orR
       }
-      v.ready := portReady
+      v.ready := portReady && sramReady
       val firstUsed = (bank & o).orR
       bankReadF(i) := bankCorrect & (~o)
       bankReadS(i) := bankCorrect & (~t) & o
@@ -325,12 +333,19 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
       (o | bankCorrect, (bankCorrect & o) | t)
   }
   // @todo @Clo91eaf check write port is ready.
-  write.ready := (parameter.ramType match {
+  write.ready := sramReady && (parameter.ramType match {
     case RamType.p0rw => (writeBank & (~firstOccupied)).orR
     case RamType.p0rp1w => true.B
     case RamType.p0rwp1rw => (writeBank & (~secondOccupied)).orR
   })
 
+  val writeData: UInt = Mux(resetValid, 0.U(parameter.datapathWidth.W), writePipe.bits.data)
+  val writeAddress: UInt =
+    Mux(
+      resetValid,
+      sramResetCount,
+      ((writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum)).asUInt
+    )
   // @todo @Clo91eaf VRF write&read singal should be captured here.
   // @todo           in the future, we need to maintain a layer to trace the original requester to each read&write.
   val rfVec: Seq[SRAMInterface[UInt]] = Seq.tabulate(parameter.rfBankNum) { bank =>
@@ -354,7 +369,7 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
        case RamType.p0rwp1rw => 2
       }
     )
-    val writeValid: Bool = writePipe.valid && writeBankPipe(bank)
+    val writeValid: Bool = writePipe.valid && writeBankPipe(bank) || resetValid
     parameter.ramType match {
       case RamType.p0rw =>
         firstReadPipe(bank).bits.address :=
@@ -362,12 +377,12 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
         firstReadPipe(bank).valid := bankReadF.map(_(bank)).reduce(_ || _)
         rf.readwritePorts.last.address := Mux(
           writeValid,
-          (writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum),
+          writeAddress,
           firstReadPipe(bank).bits.address
         )
         rf.readwritePorts.last.enable := writeValid || firstReadPipe(bank).valid
         rf.readwritePorts.last.isWrite := writeValid
-        rf.readwritePorts.last.writeData := writePipe.bits.data
+        rf.readwritePorts.last.writeData := writeData
         assert(!(writeValid && firstReadPipe(bank).valid), "port conflict")
 
         readResultF(bank) := rf.readwritePorts.head.readData
@@ -383,8 +398,8 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
         readResultS(bank) := DontCare
 
         rf.writePorts.head.enable := writeValid
-        rf.writePorts.head.address := (writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum)
-        rf.writePorts.head.data := writePipe.bits.data
+        rf.writePorts.head.address := writeAddress
+        rf.writePorts.head.data := writeData
       case RamType.p0rwp1rw =>
         firstReadPipe(bank).bits.address :=
           Mux1H(bankReadF.map(_(bank)), readRequests.map(r => (r.bits.vs ## r.bits.offset) >> log2Ceil(parameter.rfBankNum)))
@@ -403,12 +418,12 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
         secondReadPipe(bank).valid := bankReadS.map(_(bank)).reduce(_ || _)
         rf.readwritePorts.last.address := Mux(
           writeValid,
-          (writePipe.bits.vd ## writePipe.bits.offset) >> log2Ceil(parameter.rfBankNum),
+          writeAddress,
           secondReadPipe(bank).bits.address
         )
         rf.readwritePorts.last.enable := writeValid || secondReadPipe(bank).valid
         rf.readwritePorts.last.isWrite := writeValid
-        rf.readwritePorts.last.writeData := writePipe.bits.data
+        rf.readwritePorts.last.writeData := writeData
         assert(!(writeValid && secondReadPipe(bank).valid), "port conflict")
     }