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A blog post #6

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ggreif opened this issue Jan 13, 2017 · 0 comments

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ggreif commented Jan 13, 2017

http://catherineh.github.io/programming/2016/12/26/haskell-on-a-xilinx-fpga

I guess she is using the Altera timing stuff for a Xilinx device?
Does the "CLOCK_50(0) to CLOCK_50[0], same for KEY1" originate form a CLaSH tutorial?

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