adcs-fpga.cfg

# OpenOCD ADCS FPGA
#----------------------------------------
set debug 0
set regdebug 0

source memory-map/sc-obc-a1-fpga-memmap.tcl
source memory-map/adcs-memmap.tcl

source driver/sc-obc-a1-system.tcl
source driver/sc-cfgreg.tcl
source driver/i2c-master.tcl
source driver/uart-lite.tcl
source driver/adcs-system.tcl
source driver/oem7600.tcl

# System Configuration
set sysclk     48.000

# I2C Bus Alias
set temp1(bus) $ext_i2c_base
set temp1(adr) 0x4B
set temp2(bus) $ext_i2c_base
set temp2(adr) 0x4F
set cvm(bus)   $ext_i2c_base
set cvm(adr)   0x42
set cvmx(bus)  $drvx_i2c_base
set cvmx(adr)  0x40
set dpmx(bus)  $drvx_i2c_base
set dpmx(adr)  0x2E
set cvmy(bus)  $drvy_i2c_base
set cvmy(adr)  0x40
set dpmy(bus)  $drvy_i2c_base
set dpmy(adr)  0x2E
set cvmz(bus)  $drvz_i2c_base
set cvmz(adr)  0x40
set dpmz(bus)  $drvz_i2c_base
set dpmz(adr)  0x2E

# UART Alias
set console    $uartlite_base
set gps_uart   $gps_uartlite_base
#----------------------------------------
init
reset halt

# I2C Initialize
i2c_init $ext_i2c_base
i2c_init $drvx_i2c_base
i2c_init $drvy_i2c_base
i2c_init $drvz_i2c_base

# UART Initialize
uartl_init $console  $sysclk 115200
uartl_init $gps_uart $sysclk 115200