From 57722c6d03aa24da1a0c119a3ef80389e033956e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 20 Aug 2023 00:07:34 +0200 Subject: [PATCH 1/2] Added IEEE 1685-2014 IP-XACT schema files. --- ieee-1685-2014/README.md | 40 + ieee-1685-2014/abstractionDefinition.xsd | 343 +++++++ ieee-1685-2014/abstractor.xsd | 186 ++++ ieee-1685-2014/autoConfigure.xsd | 141 +++ ieee-1685-2014/busDefinition.xsd | 134 +++ ieee-1685-2014/busInterface.xsd | 642 ++++++++++++ ieee-1685-2014/catalog.xsd | 126 +++ ieee-1685-2014/commonStructures.xsd | 638 ++++++++++++ ieee-1685-2014/component.xsd | 339 +++++++ ieee-1685-2014/configurable.xsd | 50 + ieee-1685-2014/constraints.xsd | 300 ++++++ ieee-1685-2014/design.xsd | 95 ++ ieee-1685-2014/designConfig.xsd | 199 ++++ ieee-1685-2014/file.xsd | 512 ++++++++++ ieee-1685-2014/fileType.xsd | 108 ++ ieee-1685-2014/generator.xsd | 295 ++++++ ieee-1685-2014/identifier.xsd | 118 +++ ieee-1685-2014/index.xsd | 89 ++ ieee-1685-2014/memoryMap.xsd | 1158 ++++++++++++++++++++++ ieee-1685-2014/model.xsd | 397 ++++++++ ieee-1685-2014/port.xsd | 568 +++++++++++ ieee-1685-2014/signalDrivers.xsd | 236 +++++ ieee-1685-2014/simpleTypes.xsd | 284 ++++++ ieee-1685-2014/subInstances.xsd | 407 ++++++++ ieee-1685-2014/xml.xsd | 8 + 25 files changed, 7413 insertions(+) create mode 100644 ieee-1685-2014/README.md create mode 100644 ieee-1685-2014/abstractionDefinition.xsd create mode 100644 ieee-1685-2014/abstractor.xsd create mode 100644 ieee-1685-2014/autoConfigure.xsd create mode 100644 ieee-1685-2014/busDefinition.xsd create mode 100644 ieee-1685-2014/busInterface.xsd create mode 100644 ieee-1685-2014/catalog.xsd create mode 100644 ieee-1685-2014/commonStructures.xsd create mode 100644 ieee-1685-2014/component.xsd create mode 100644 ieee-1685-2014/configurable.xsd create mode 100644 ieee-1685-2014/constraints.xsd create mode 100644 ieee-1685-2014/design.xsd create mode 100644 ieee-1685-2014/designConfig.xsd create mode 100644 ieee-1685-2014/file.xsd create mode 100644 ieee-1685-2014/fileType.xsd create mode 100644 ieee-1685-2014/generator.xsd create mode 100644 ieee-1685-2014/identifier.xsd create mode 100644 ieee-1685-2014/index.xsd create mode 100644 ieee-1685-2014/memoryMap.xsd create mode 100644 ieee-1685-2014/model.xsd create mode 100644 ieee-1685-2014/port.xsd create mode 100644 ieee-1685-2014/signalDrivers.xsd create mode 100644 ieee-1685-2014/simpleTypes.xsd create mode 100644 ieee-1685-2014/subInstances.xsd create mode 100644 ieee-1685-2014/xml.xsd diff --git a/ieee-1685-2014/README.md b/ieee-1685-2014/README.md new file mode 100644 index 0000000..4e7f62c --- /dev/null +++ b/ieee-1685-2014/README.md @@ -0,0 +1,40 @@ +# IEEE Std. 1685-2014 + +Source: http://www.accellera.org/XMLSchema/IPXACT/1685-2014/ + + +From the Accellera page +----------------------- + +© Copyright 2006-2014 Accellera Systems Initiative. All rights reserved. + +These XML files are believed to be a consistent XML Schema expression for creating and validating XML documents based on +the IEEE Std 1685-2009 and 2014 Standards for IP-XACT, Standard Structure for Packaging, Integrating and Re-using IP +within Tool-flows. These files are in the format specified by the World Wide Web Consortium (W3C) as XML Schema +definition language. + +The purpose of this schema is to allow the creation and validation of XML documents conforming to the IEEE Std 1685-2009 +and 2014 Standards for IP-XACT, Standard Structure for Packaging, Integrating and Re-using IP within Tool-flows. + +**USE AT YOUR OWN RISK** + +These source files are provided on an AS IS basis. Accellera Systems Initiative disclaims any warranty express or +implied including any warranty of merchantability and fitness for use for a particular purpose. + +The user of the source files shall indemnify and hold Accellera Systems Initiative and its members harmless from any +damages or liability. + +This file may be copied, and distributed, WITHOUT modifications; this notice must be included on any copy. + +This schema shall not be modified, adapted, altered, sublicensed, nor any derivative works shall be created based upon +the schema. The intended and allowed uses of the schema include: + +* Creating and validating XML documents that conform to the schema +* Building software programs and systems based on the schema +* Distributing verbatim copy of the schema as long as the full text of this license is included in all copies of the + schema. Specifically, a tool may include full copies of the schema, and these copies may be distributed by the tool + provider directly. A link or URL to the original of the schema is inherent in the schema URI. +* Documents which are validated against this schema may also reference additional schema. These additional schemas may + provide for validation of elements and attributes at the extension points explicitly and implicitly included in the + IEEE 1685-2009 and 2014 standards. +* No right to create new schemas derived from parts of this base schema is granted pursuant to this License. diff --git a/ieee-1685-2014/abstractionDefinition.xsd b/ieee-1685-2014/abstractionDefinition.xsd new file mode 100644 index 0000000..abaa322 --- /dev/null +++ b/ieee-1685-2014/abstractionDefinition.xsd @@ -0,0 +1,343 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + If this element is present, the + existance of the port is controlled by the specified + value. valid values are 'illegal', 'required' and + 'optional'. + + + + + Group of elements used in a transactional port. + + + + + + If this element is present, the type of access is restricted to the specified value. + + + + + + + + + + + + + If this element is present, the width must match + + + + + If this element is present, the name must match + + + + + + + Group of elements used in a wire port. + + + + + + Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1. + + + + + If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface. + + + + + + Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a 'mode' bus interface or a mirrored-'mode' bus interface. Otherwise they only apply when the port appears in a 'mode' bus interface. + + + + + Specifies default constraints for the enclosing wire type port when it appears in a mirrored-'mode' bus interface. + + + + + + + + Define the ports and other information of a particular abstraction of the bus + + + + + + + Reference to the busDefinition that this abstractionDefinition implements. + + + + + Optional name of abstraction type that this abstraction definition is compatible with. This abstraction definition may change the definitions of ports in the existing abstraction definition and add new ports, the ports in the original abstraction are not deleted but may be marked illegal to disallow their use. + This abstraction definition may only extend another abstraction definition if the bus type of this abstraction definition extends the bus type of the extended abstraction definition + + + + + This is a list of logical ports defined by the bus. + + + + + + + + + + The assigned name of this port in bus specifications. + + + + + + + Port style. + + + + A port that carries logic or an array of logic values + + + + + + The type of information this port carries A wire port can carry both address and data, but may not mix this with a clock or reset + + + + + + + If this element is present, the port contains address information. + + + + + If this element is present, the port contains data information. + + + + + + If this element is present, the port contains only clock information. + + + + + Is this element is present, the port contains only reset information. + + + + + + + + Defines constraints for this port when present in a system bus interface with a matching group name. + + + + + + Used to group system ports into different groups within a common bus. + + + + + + + + + + Defines constraints for this port when present in a master bus interface. + + + + + + + + Defines constraints for this port when present in a slave bus interface. + + + + + + + + + Indicates the default value for this wire port. + + + + + + + + + + A port that carries complex information modeled at a high level of abstraction. + + + + + + The type of information this port carries A transactional port can carry both address and data information. + + + + + + If this element is present, the port contains address information. + + + + + If this element is present, the port contains data information. + + + + + + + + Defines constraints for this port when present in a system bus interface with a matching group name. + + + + + + Used to group system ports into different groups within a common bus. + + + + + + + + + + Defines constraints for this port when present in a master bus interface. + + + + + + + + Defines constraints for this port when present in a slave bus interface. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/abstractor.xsd b/ieee-1685-2014/abstractor.xsd new file mode 100644 index 0000000..a33c73b --- /dev/null +++ b/ieee-1685-2014/abstractor.xsd @@ -0,0 +1,186 @@ + + + + + + + + + + + + + + Abstractor-specific extension to abstractorType + + + + + + Define the mode for the interfaces on this abstractor. + +For master the first interface connects to the master, the second connects to the mirroredMaster + +For slave the first interface connects to the mirroredSlave the second connects to the slave + +For direct the first interface connects to the master, the second connects to the slave + +For system the first interface connects to the system, the second connects to the mirroredSystem. For system the group attribute is required + + + + + + + Define the system group if the mode is set to system + + + + + + + + + The bus type of both interfaces. Refers to bus definition using vendor, library, name, version attributes. + + + + + The interfaces supported by this abstractor + + + + + + An abstractor must have exactly 2 Interfaces. + + + + + + + + Model information. + + + + + + + + + + + + + Generator list is tools-specific. + + + + + + + + + + + + + + This is the root element for abstractors + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Mode for this abstractor + + + + + + + + + diff --git a/ieee-1685-2014/autoConfigure.xsd b/ieee-1685-2014/autoConfigure.xsd new file mode 100644 index 0000000..b16e8f5 --- /dev/null +++ b/ieee-1685-2014/autoConfigure.xsd @@ -0,0 +1,141 @@ + + + + + + + + + This is an indication on the format of the value. bit: 1-bit or more (vector) bits unsigned integer, byte: 8-bit signed integer, shortint: 16-bit signed integer, int: 32-bit signed integer, longint: 64-bit signed integer, shortreal: 32-bit signed floating point number, real: 64-bit signed floating point number, string: textual information. + + + + + + + + + + + + + + + This is an indication of the signedness of the value. + + + + + + + + + Indicates legal units for delay values. + + + + + + + + + + + + Contains the xml:id attribute used for annotating elements with a unique identifiers. See http://www.w3.org/TR/xml-id for more information. + + + + + + Choices used by elements with an attribute ipxact:choiceRef. + + + + + + Non-empty set of legal values for a elements with an attribute ipxact:choiceRef. + + + + + + Choice key, available for reference by the ipxact:choiceRef attribute. + + + + + One possible value of ipxact:choice + + + + + + + When specified, displayed in place of the ipxact:enumeration value + + + + + Text that may be displayed if the user requests help about the meaning of an element + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/busDefinition.xsd b/ieee-1685-2014/busDefinition.xsd new file mode 100644 index 0000000..e355dd3 --- /dev/null +++ b/ieee-1685-2014/busDefinition.xsd @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + Defines the structural information associated with a bus type, independent of the abstraction level. + + + + + + + This element indicates that a master interface may be directly connected to a slave interface (under certain conditions) for busses of this type. + + + + + This element indicates that this bus definition supports 'broadcast' mode. This means that it is legal to make one-to-many interface connections. + + + + + If true, indicates that this is an addressable bus. + + + + + Optional name of bus type that this bus definition is compatible with. This bus definition may change the definitions in the existing bus definition + + + + + Indicates the maximum number of masters this bus supports. If this element is not present, the number of masters allowed is unbounded. + + + + + Indicates the maximum number of slaves this bus supports. If the element is not present, the number of slaves allowed is unbounded. + + + + + Indicates the list of system group names that are defined for this bus definition. + + + + + + Indicates the name of a system group defined for this bus definition. + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/busInterface.xsd b/ieee-1685-2014/busInterface.xsd new file mode 100644 index 0000000..962d862 --- /dev/null +++ b/ieee-1685-2014/busInterface.xsd @@ -0,0 +1,642 @@ + + + + + + + + + + + + Indicates whether bit steering should be used to map this interface onto a bus of different data width. + + Values are "on", "off" or an expression which resolves to an unsigned-bit where a '1' indicates "on" and a '0' indicates "off" (defaults to "off"). + + + + + + + + + + Indicates whether bit steering should be used to map this interface onto a bus of different data width. + + Values are "on", "off" (defaults to "off"). + + + + + + + + + + + + + + + + + 'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian. + + + + + + + + + The number of bits in the least addressable unit. The default is byte addressable (8 bits). + + + + + + + + + + + + + + Describes one of the bus interfaces supported by this component. + + + + + A list of bus interfaces supported by this component. + + + + + + + + + + Type definition for a busInterface in a component + + + + + + + The bus type of this interface. Refers to bus definition using vendor, library, name, version attributes along with any configurable element values needed to configure this interface. + + + + + + Indicates the usage mode of this instance of the bus interface. + + + + + Indicates whether a connection to this interface is required for proper component functionality. + + + + + + Indicates whether bit steering should be used to map this interface onto a bus of different data width. + +Values are "on", "off" (defaults to "off"). + + + + + 'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian. + + + + + + + + + + Indicates which system interface is being mirrored. Name must match a group name present on one or more ports in the corresonding bus definition. + + + + + Lists all channel connections between mirror interfaces of this component. + + + + + + Defines a set of mirrored interfaces of this component that are connected to one another. + + + + + + + + Contains the name of one of the bus interfaces that is part of this channel. The ordering of the references may be important to the design environment. + + + + + + + + + + + + + + + + + + + + + + + Contains a list of remap state names and associated port values + + + + + + Contains a list of ports and values in remapPort and a list of registers and values that when all evaluate to true which tell the decoder to enter this remap state. The name attribute identifies the name of the state. If a list of remapPorts and/or remapRegisters is not defined then the condition for that state cannot be defined. + + + + + + + List of ports and their values that shall invoke this remap state. + + + + + + Contains the name and value of a port on the component, the value indicates the logic value which this port must take to effect the remapping. The portMapRef attribute stores the name of the port which takes that value. + + + + + + Index for a vectored type port. Must be a number between left and right for the port. + + + + + + + This attribute identifies a signal on the component which affects the component's memory layout + + + + + + + + + + + + + + + + Group of the different modes a busInterface can take on in a component + + + + + If this element is present, the bus interface can serve as a master. This element encapsulates additional information related to its role as master. + + + + + + If this master connects to an addressable bus, this element references the address space it maps to. + + + + + + + If the master's mapping to the physical address space is not zero based, the baseAddress element may be used to indicate the offset. If not specified the offset is 0. The baseAddress is in units of the addressSpace addressUnitBits + + + + Base of an address space. + + + + + + + + + + + + + If this element is present, the bus interface can serve as a slave. + + + + + + + + + + This reference is used to point the filesets that are associated with this slave port. + +Depending on the slave port function, there may be completely different software drivers associated with the different ports. + + + + + + Abritray name assigned to the collections of fileSets. + + + + + + + + + + + + + If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus. + + + + + + + + + + If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on ports are reversed relative to the specification in the bus definition. + + + + + + Represents a set of remap base addresses. + + + + + + Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The state attribute indicates the name of the remap state for which this address is valid. + + + + + + + Name of the state in which this remapped address range is valid + + + + + + + + + + The address range of mirrored slave, expressed as the number of bitsInLAU from the containing busInterface. + + + + + + + + + + + If this element is present, the bus interface represents a mirrored master interface. All directional constraints on ports are reversed relative to the specification in the bus definition. + + + + + + If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition. + + + + + + + + + + Indicates that this is a (passive) monitor interface. All of the ports in the interface must be inputs. The type of interface to be monitored is specified with the required interfaceType attribute. The ipxact:group element must be specified if monitoring a system interface. + + + + + + Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition. + + + + + + + + + + + + + + + + + + + + + + If this element is present, it indicates that the bus interface provides a transparent bridge to another master bus interface on the same component. It has a masterRef attribute which contains the name of the other bus interface. + +Any slave interface can bridge to multiple master interfaces, and multiple slave interfaces can bridge to the same master interface. + + + + + + + + The name of the master bus interface to which this interface bridges. + + + + + + + + Group of the different modes a busInterface can take on in an abstractor + + + + + If this element is present, the bus interface can serve as a master. This element encapsulates additional information related to its role as master. + + + + + If this element is present, the bus interface can serve as a slave. + + + + + If this element is present, the bus interface is a system interface, neither master nor slave, with a specific function on the bus. + + + + + + + + + + If this element is present, the bus interface represents a mirrored slave interface. All directional constraints on ports are reversed relative to the specification in the bus definition. + + + + + If this element is present, the bus interface represents a mirrored master interface. All directional constraints on ports are reversed relative to the specification in the bus definition. + + + + + If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition. + + + + + + + + + + + + Type definition for a busInterface in a component + + + + + + + + + + + + Describes one of the bus interfaces supported by this component. + + + + + A list of bus interfaces supported by this component. + + + + + + + + + + Type definition for a indirectInterface in a component + + + + + + + + + A reference to a memoryMap. This memoryMap is indirectly accessible through this interface. + + + + + + + + 'big': means the most significant element of any multi-element data field is stored at the lowest memory address. 'little' means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is 'little' endian. + + + + + + + + + + A reference to a field used for addressing the indirectly accessible memoryMap. + + + + + A reference to a field used for read/write access to the indirectly accessible memoryMap. + + + + + + + + The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes along with any configurable element values needed to configure this abstraction. Bus definition can be found through a reference in this file. + + + + + + A reference to a view name in the file for which this type applies. + + + + + Provides the VLNV of the abstraction type. + + + + + Listing of maps between component ports and bus ports. + + + + + + Maps a component's port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component. + + + + + + + Logical port from abstraction definition + + + + + + Bus port name as specified inside the abstraction definition + + + + + + + + + + Physical port from this component + + + + + + Component port name as specified inside the model port section + + + + + + + + + Identifies a value to tie this logical port to. + + + + + + When true, indicates that this portMap element is for information purpose only. + + + + + + + Indicates that the connection between the logical and physical ports should include an inversion. + + + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/catalog.xsd b/ieee-1685-2014/catalog.xsd new file mode 100644 index 0000000..4cc085b --- /dev/null +++ b/ieee-1685-2014/catalog.xsd @@ -0,0 +1,126 @@ + + + + + + + This is the IP-XACT catalog definition + + + + + + Contains a list of IP-XACT files to include. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + VLNV of the IP-XACT file being cataloged. + + + + + Name of the IP-XACT file being cataloged. + + + + + + + diff --git a/ieee-1685-2014/commonStructures.xsd b/ieee-1685-2014/commonStructures.xsd new file mode 100644 index 0000000..c3c98fb --- /dev/null +++ b/ieee-1685-2014/commonStructures.xsd @@ -0,0 +1,638 @@ + + + + + + + + + Name value pair with data type information. + + + + + + + + + The data type of the argument as pertains to the language. Example: "int", "double", "char *". + + + + + Indicates the type of the module parameter. Legal values are defined in the attribute enumeration list. Default value is 'nontyped'. + + + + + + + + + + + + + + A name value pair. The name is specified by the name element. The value is in the text content of the value element. This value element supports all configurability attributes. + + + + + Provides an expression for describing valid parameter value settings. If a assertion assert expression evaluates false, the name, displayName and/or description can be used to communicate the assertion failure. + + + + + + + + + + + + List of assertions about allowed parameter values. + + + + + + + + + + A collection of parameters and associated value assertions. + + + + + + + + + + Container for vendor specific extensions. + + + + + + Accepts any element(s) the content provider wants to put here, including elements from the ipxact namespace. + + + + + + + + A group of elements for name (xs:name), displayName and description + + + + + Unique name + + + + + + + + + + + A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views. + + + + + + + + + + + + For a multi dimensional IP-XACT object, indices can be specified to select the element the accessHandle applies to. This is an index into a multi-dimensional array and follows C-semantics for indexing. + + + + + + An index into the IP-XACT object. + + + + + + + + + + + + + + + A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views. + + + + + + + + + + + + + + + + + + + A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views. + + + + + + + + + + + + For a multi dimensional IP-XACT object, indices can be specified to select the element the accessHandle applies to. This is an index into a multi-dimensional array and follows C-semantics for indexing. + + + + + + An index into the IP-XACT object. + + + + + + + + An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view. + + + + + + + + + + + + + + + A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views. + + + + + + + + + + + + An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view. + + + + + + + + + + + + + Each slice specifies the HDL path for part of the parent IP-XACT object. The slices must be concatenated to calculate the entire path. If there is only one slice, it is assumed to be the path for the entire IP-XACT object. + + + + + The HDL path for a slice of the IP-XACT object. + + + + + + + Contains the HDL path information for a slice of the IP-XACT object. + + + + + An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view. + + + + + + + + + + A range to be applied to the concatenation of the above path segments + + + + + + + + Identifies one level of hierarchy in the view specifed by viewNameRef. This is a simple name and optionally some indices into a multi dimensional element. + + + + + One section of a HDL path + + + + + Specifies a multi-dimensional index into pathSegementName + + + + + + + + The optional element right specifies the right boundary. + + + + + The optional element left specifies the left boundary. + + + + + A group of elements for name (xs:name), displayName and description where the name is optional + + + + + Unique name + + + + + + + + + A group of elements for name(xs:NMTOKEN), displayName and description + + + + + Unique name + + + + + + + + + A group of elements for name(portName), displayName and description + + + + + Unique name + + + + + + + + + Name and value type for use in resolvable elements + + + + + + + + The value of the parameter. + + + + + + + ID attribute for uniquely identifying a parameter within its document. Attribute is used to refer to this from a configurable element. + + + + + Provides a string used to prompt the user for user-resolved property values. + + + + + For user defined properties, refers the choice element enumerating the values to choose from. + + + + + For components with auto-generated configuration forms, the user-resolved properties with order attibutes will be presented in ascending order. + + + + + Tags configurable properties so that they may be grouped together. Configurable properties with matching values for this attribute are contained in the same group. The format of this attribute is a string. There is no semantic meaning to this attribute. + + + + + For user-resolved properties with numeric values, this indicates the minimum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter-value, which is specified by the parameter-type attribute. + + + + + For user-resolved properties with numeric values, this indicates the maximum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter-value, which is specified by the parameter-type attribute. + + + + + Specifies the type of the value of the parameter. A parameter of type byte is resolved to an 8-bit integer value, shortint is resolved to a 16-bit integer value, int is resolved to a 32-bit integer value, longint is resolved to a 64-bit integer value, shortreal is resolved to a 32-bit floating point value, real is resolved to a 64-bit floating point value, bit is by default resolved to a one bit value, unless a vector size has been specified and the string type is resolved to a string value. + + + + + Specify the signedness explicitly. The data types byte, shortint, int, longint default to signed. The data type bit defaults to unsigned. When setting this values for the data types string, real and shortreal the setting is ignored. + + + + + Defines the prefix that precedes the unit of a value. The prefix is not applied to the value (e.g. in calculations). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the unit of the value. + + + + + + + + + + + + + + + + + + + + + + + + + + + Determines how a property value can be configured. + + + + Determines how a parameter is resolved. User means the value must be obtained from the user. Generated means the value will be provided by a generator. + + + + + Property content cannot be modified through configuration. + + + + + Property content can be modified through configuration. Modifications will be saved with the design. + + + + + Generators may modify this property. Modifications get saved with the design. + + + + + + + + + + + Name and value type for use in resolvable elements + + + + + + + + + + + Left and right ranges of the vector. + + + + + + + + + + + Vectored information. + + + + + + + + + + Left and right bound of a reference into a vector. + + + + + + + + + + + Bit range definition. + + + + + + + + + + + + + + + + Specific left and right array bounds. + + + + + + + + + + + + + + The value of the parameter. + + + + + A group of elements for name(xs:string), displayName and description + + + + + Unique name + + + + + + + + + Element name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the ipxact:name. + + + + + Full description string, typically for documentation + + + + + Expression that determines whether the enclosing element should be treated as present (expression evaluates to "true") or disregarded (expression evalutes to "false") + + + + + Expression that determines whether the enclosing element responds to read or write accesses to its specified address location. The expression can include dynamic values referencing register/field values and component states. If it evaluates to true, then the enclosing register can be accessed per its mapping and access specification. If it evaluates to false, the enclosing register/field cannot be accessed. If a register does not include an activeCondition or alternateRegister(s), then the register is uncondiitionally accessible. If a register does not include an activeCondition, but does include alternateRegister(s), then the condition that determines which is accessible is considered unspecified. + + + + + + + An index into an object in the referenced view. + + + + + diff --git a/ieee-1685-2014/component.xsd b/ieee-1685-2014/component.xsd new file mode 100644 index 0000000..1f03398 --- /dev/null +++ b/ieee-1685-2014/component.xsd @@ -0,0 +1,339 @@ + + + + + + + + + + + + + + Component-specific extension to componentType + + + + + + + + + + + + + Generator list is tools-specific. + + + + + + + A list of whiteboxElements + + + + + + A whiteboxElement is a useful way to identify elements of a component that can not be identified through other means such as internal signals and non-software accessible registers. + + + + + + + + cpu's in the component + + + + + + Describes a processor in this component. + + + + + + The name of the cpu instance relative to the platform core. + + + + + + Indicates which address space maps into this cpu. + + + + + Data specific to the cpu. + + + + + + + + + + + + + Defines a set of clock drivers that are not directly associated with an input port of the component. + + + + + A list of user defined resetTypes applicable to this component. + + + + + + A user defined reset policy + + + + + + + + + + + + + + + + + + + + + + This is the root element for all non platform-core components. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines a white box reference point within the component. + + + + + + + Indicates the type of the element. The pin and signal types refer to elements within the HDL description. The register type refers to a register in the memory map. The interface type refers to a group of signals addressed as a single unit. + + + + + If true, indicates that the white box element can be driven (e.g. have a new value forced into it). + + + + + + + + diff --git a/ieee-1685-2014/configurable.xsd b/ieee-1685-2014/configurable.xsd new file mode 100644 index 0000000..75e98e2 --- /dev/null +++ b/ieee-1685-2014/configurable.xsd @@ -0,0 +1,50 @@ + + + + diff --git a/ieee-1685-2014/constraints.xsd b/ieee-1685-2014/constraints.xsd new file mode 100644 index 0000000..53acf80 --- /dev/null +++ b/ieee-1685-2014/constraints.xsd @@ -0,0 +1,300 @@ + + + + + + + + + + Indicates legal cell function values. + + + + + + + + + + + + + + + + Indicates legal cell class values. + + + + + + + + + + Indicates legal cell strength values. + + + + + + + + + + + Indicates legal values for edge specification attributes. + + + + + + + + + + Indicates the type of delay value - minimum or maximum delay. + + + + + + + + + + Type used to record percentage values. + + + + + + + + + + Defines a non-negative floating point number. + + + + + + + + List of clocks associated with the component that are not associated with ports. Set the clockSource attribute on the clockDriver to indicate the source of a clock not associated with a particular component port. + + + + + + + + + Used to provide a generic description of a technology library cell. + + + + + + Defines a technology library cell in library independent fashion, based on specification of a cell function and strength. + + + + + + + + + + + + Defines a technology library cell in library independent fashion, based on specification of a cell class and strength. + + + + + + Indicates the desired strength of the specified cell. + + + + + + + Defines a timing constraint for the associated port. The constraint is relative to the clock specified by the clockName attribute. The clockEdge indicates which clock edge the constraint is associated with (default is rising edge). The delayType attribute can be specified to further refine the constraint. + + + + + + + Indicates the clock edge that a timing constraint is relative to. + + + + + Indicates the type of delay in a timing constraint - minimum or maximum. + + + + + Indicates the name of the clock to which this constraint applies. + + + + + + + + + + Defines a constraint indicating how an input is to be driven. The preferred methodology is to specify a library cell in technology independent fashion. The implemention tool should assume that the associated port is driven by the specified cell, or that the drive strength of the input port is indicated by the specified resistance value. + + + + + + + + + + Defines a constraint indicating the type of load on an output port. + + + + + + + Indicates how many loads of the specified cell are connected. If not present, 3 is assumed. + + + + + + + + Defines constraints that apply to a component port. If multiple constraintSet elements are used, each must have a unique value for the constraintSetId attribute. + + + + + + + The optional element vector specify the bits of a vector for which the constraints apply. The vaules of left and right must be within the range of the port. If the vector is not specified then the constraints apply to all the bits of the port. + + + + + + The optional elements left and right can be used to select a bit-slice of a vector. + + + + + The optional elements left and right can be used to select a bit-slice of a vector. + + + + + + + + + + + + Indicates a name for this set of constraints. Constraints are tied to a view using this name in the constraintSetRef element. + + + + + + + + List of constraintSet elements for a component port. + + + + + + + + + + A reference to a set of port constraints. + + + + + + + + + + + + Defines constraints that apply to a wire type port in an abstraction definition. + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/design.xsd b/ieee-1685-2014/design.xsd new file mode 100644 index 0000000..f713ec9 --- /dev/null +++ b/ieee-1685-2014/design.xsd @@ -0,0 +1,95 @@ + + + + + + + + + + + Root element for a platform design. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/designConfig.xsd b/ieee-1685-2014/designConfig.xsd new file mode 100644 index 0000000..77385de --- /dev/null +++ b/ieee-1685-2014/designConfig.xsd @@ -0,0 +1,199 @@ + + + + + + + + + + + Top level element for describing the current configuration of a design. Does not describe instance parameterization + + + + + + + The design to which this configuration applies + + + + + Contains the configurable information associated with a generatorChain and its generators. Note that configurable information for generators associated with components is stored in the design file. + + + + + Contains the information about the abstractors required to cross between two interfaces at with different abstractionDefs. + + + + + + + Reference to the interconnection name, monitor interconnection name or possibly a hierConnection interfaceName in a design file. + + + + + List of abstractor-instances for this interconnection. Multiple abstractor-instances elements may be present for a 1-to-many (broadcast) interconnection. In that case, the optional interfaceRef elements must reference non-overlapping interfaces from the 'many' side of the interconnection. + + + + + + + Defines the broadcast endpoint to which this chain of abstractors applies. + + + + + + + + Reference to a component instance nane. + + + + + Reference to a component bus interface name. + + + + + + + Element to hold a the abstractor reference, the configuration and viewName. If multiple elements are present then the order is the order in which the abstractors should be chained together. + + + + + + Instance name for the abstractor + + + + + + + Abstractor reference + + + + + The name of the active view for this abstractor instance. + + + + + + + + + + + + + + + + Contains the active views for each instance in the design + + + + + + + + The selected view for the instance. + + + + + + Parameter values to set in the selected configuredView. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/file.xsd b/ieee-1685-2014/file.xsd new file mode 100644 index 0000000..b723fad --- /dev/null +++ b/ieee-1685-2014/file.xsd @@ -0,0 +1,512 @@ + + + + + + + + + IP-XACT reference to a file or directory. + + + + + + Path to the file or directory. If this path is a relative path, then it is relative to the containing XML file. + + + + + + + Indicates that the current file is purely structural. + + + + + Indicate that the file is include file. + + + + + + + the File contains some declarations that are needed in top file + + + + + + + + + Logical name for this file or directory e.g. VHDL library name. + + + + + + + The logical name shall only be used as a default and another process may override this name. + + + + + + + + + Defines exported names that can be accessed externally, e.g. exported function names from a C source file. + + + + + + + + + + + + Command and flags used to build derived files from the sourceName files. If this element is present, the command and/or flags used to to build the file will override or augment any default builders at a higher level. + + + + + + Command used to build this file. + + + + + Flags given to the build command when building this file. If the optional attribute "append" is "true", this string will be appended to any existing flags, otherwise these flags will replace any existing default flags. + + + + + + + "true" indicates that the flags shall be appended to any existing flags, "false"indicates these flags will replace any existing default flags. + + + + + + + + + If true, the value of the sibling element "flags" should replace any default flags specified at a more global level. If this is true and the sibling element "flags" is empty or missing, this has the effect of clearing any default flags. + + + + + Pathname to the file that is derived (built) from the source file. + + + + + + + + + Specifies define symbols that are used in the source file. The ipxact:name element gives the name to be defined and the text content of the ipxact:value element holds the value. This element supports full configurability. + + + + + Relates the current file to a certain executable image type in the design. + + + + + + + + + + + + String for describing this file to users + + + + + + + Unique ID for this file, referenced in fileSet/function/fileRef + + + + + + + + + This element specifies a list of unique pathnames to files and directories. It may also include build instructions for the files. If compilation order is important, e.g. for VHDL files, the files have to be provided in compilation order. + + + + + Specifies an executable software image to be loaded into a processors address space. The format of the image is not specified. It could, for example, be an ELF loadfile, or it could be raw binary or ascii hex data for loading directly into a memory model instance. + + + + + + + Additional information about the load module, e.g. stack base addresses, table addresses, etc. + + + + + Default commands and flags for software language tools needed to build the executable image. + + + + + + A generic placeholder for any file builder like compilers and assemblers. It contains the file types to which the command should be applied, and the flags to be used with that command. + + + + + + + Default command used to build files of the specified fileType. + + + + + Flags given to the build command when building files of this type. + + + + + If true, replace any default flags value with the value in the sibling flags element. Otherwise, append the contents of the sibling flags element to any default flags value. + +If the value is true and the "flags" element is empty or missing, this will have the result of clearing any default flags value. + + + + + + + + + + If a languageTools element contains a linkerFlags element or a linkerCommandFile element, it shall also contain a linker element. + + + + + + + + + + + + + + + + Contains a group of file set references that indicates the set of file sets complying with the tool set of the current executable image. + + + + + + + + + + + + Unique ID for the executableImage, referenced in fileSet/function/fileRef + + + + + Open element to describe the type of image. The contents is model and/or generator specific. + + + + + + + + Specifies a linker command file. + + + + + + Linker command file name. + + + + + The command line switch to specify the linker command file. + + + + + Specifies whether to generate and enable the linker command file. + + + + + + + + + + + A reference to a fileSet. + + + + + + Refers to a fileSet defined within this description. + + + + + + + + + + Specifies a location on which files or fileSets may be dependent. Typically, this would be a directory that would contain included files. + + + + + + + + + + + + List of file sets associated with component. + + + + + + + + + + + + + Default command used to build files of the specified fileType. + + + + + Flags given to the build command when building files of this type. + + + + + If true, replace any default flags value with the value in the sibling flags element. Otherwise, append the contents of the sibling flags element to any default flags value. + +If the value is true and the "flags" element is empty or missing, this will have the result of clearing any default flags value. + + + + + + + + + + + + + + + + + + + Identifies this filleSet as belonging to a particular group or having a particular purpose. Examples might be "diagnostics", "boot", "application", "interrupt", "deviceDriver", etc. + + + + + + + + + + + + + Default command and flags used to build derived files from the sourceName files in this file set. + + + + + + Generator information if this file set describes a function. For example, this file set may describe diagnostics for which the DE can generate a diagnostics driver. + + + + + + Optional name for the function. + + + + + A reference to the file that contains the entry point function. + + + + + Function return type. Possible values are void and int. + + + + + Arguments passed in when the function is called. Arguments are passed in order. + +This is an extension of the name-value pair which includes the data type in the ipxact:dataType attribute. The argument name is in the ipxact:name element and its value is in the ipxact:value element. + + + + + + + The data type of the argument as pertains to the language. Example: "int", "double", "char *". + + + + + + + + + Specifies if the SW function is enabled. If not present the function is always enabled. + + + + + Location information for the source file of this function. + + + + + + Source file for the boot load. Relative names are searched for in the project directory and the source of the component directory. + + + + + + + + + + + + If true directs the generator to compile a separate object module for each instance of the component in the design. If false (default) the function will be called with different arguments for each instance. + + + + + + + + + + + + + Enumerates C argument data types. + + + + + + + + + + + + + + + + A reference to a generator element. + + + + + + + + + + + + + IP-XACT URI, like a standard xs:anyURI except that it can contain environment variables in the ${ } form, to be replaced by their value to provide the underlying URI + + + + + + diff --git a/ieee-1685-2014/fileType.xsd b/ieee-1685-2014/fileType.xsd new file mode 100644 index 0000000..2a958c6 --- /dev/null +++ b/ieee-1685-2014/fileType.xsd @@ -0,0 +1,108 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Enumerated file types known by IP-XACT. + + + + + + + + + + + diff --git a/ieee-1685-2014/generator.xsd b/ieee-1685-2014/generator.xsd new file mode 100644 index 0000000..aefceb1 --- /dev/null +++ b/ieee-1685-2014/generator.xsd @@ -0,0 +1,295 @@ + + + + + + + + + + + + + + + Select other generator chain files for inclusion into this chain. The boolean attribute "unique" (default false) specifies that only a single generator is valid in this context. If more that one generator is selected based on the selection criteria, DE will prompt the user to resolve to a single generator. + + + + + + + Select another generator chain using the unique identifier of this generator chain. + + + + + + Specifies that only a single generator is valid in this context. If more that one generator is selcted based on the selection criteria, DE will prompt the user to resolve to a single generator. + + + + + + + + Selects generators declared in components of the current design for inclusion into this generator chain. + + + + + + + Identifies this generator chain as belonging to the named group. This is used by other generator chains to select this chain for programmatic inclusion. + + + + + + + + + + + + + + + + + + + If this attribute is true then the generator should not be presented to the user, it may be part of a chain and has no useful meaning when invoked standalone. + + + + + + + + Specifies a set of generators. + + + + + + + + + + Specifies a set of component generators. The scope attribute applies to component generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity. + + + + + Specifies a set of abstractor generators. The scope attribute applies to abstractor generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity. + + + + + Specifies a set of group names used to select subsequent generators. The attribute "multipleGroupOperator" specifies the OR or AND selection operator if there is more than one group name (default=OR). + + + + + + Specifies a generator group name or a generator chain group name to be selected for inclusion in the generator chain. + + + + + + + + + + + + + Specifies the OR or AND selection operator if there is more than one group name. + + + + + + + + + + + + + + This is an non-negative floating point number that is used to sequence when a generator is run. The generators are run in order starting with zero. There may be multiple generators with the same phase number. In this case, the order should not matter with respect to other generators at the same phase. If no phase number is given the generator will be considered in the "last" phase and these generators will be run in the order in which they are encountered while processing generator elements. + + + + + + + + + An identifier to specify the generator group. This is used by generator chains for selecting which generators to run. + + + + + + + + + + + + + The scope attribute applies to component generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity. + + + + + + + + + + + + + + + + + + + + List of component generators. + + + + + + + + + + List of abstractor generators. + + + + + + + + + + + + + + + + + + + + + + + Types of generators + + + + + + + + Indicates the type of API used by the generator. Valid value are TGI_2009, TGI_2014_BASE, TGI_2014_EXTENDED, and none. If this element is not present, TGI_2014_BASE is assumed. The type TGI_2009 indicates a generator using the 1685-2009 version of the TGI API. This is not part of the 1685-2014 version of the standard and may not be supported by Design Environments. + + + + + + + + + + + + + + + Defines a SOAP transport protocol other than HTTP which is supported by this generator. The only other currently supported protocol is 'file'. + + + + + + + + + + + + + + + + The pathname to the executable file that implements the generator + + + + + + + If this attribute is true then the generator should not be presented to the user, it may be part of a chain and has no useful meaning when invoked standalone. + + + + + diff --git a/ieee-1685-2014/identifier.xsd b/ieee-1685-2014/identifier.xsd new file mode 100644 index 0000000..7e9dab1 --- /dev/null +++ b/ieee-1685-2014/identifier.xsd @@ -0,0 +1,118 @@ + + + + + + + + + Base IP-XACT identifier group. Identify an IP-XACT document by its by vendor, library and name. + + + + + + This group of elements identifies a top level item (e.g. a component or a bus definition) with vendor, library, name and a version number. + + + + + Name of the vendor who supplies this file. + + + + + Name of the logical library this element belongs to. + + + + + The name of the object. + + + + + Indicates the version of the named element. + + + + + + + Base IP-XACT document reference. Contains vendor, library, name and version attributes. + + + + + + + + + Base IP-XACT document reference type. Contains vendor, library, name and version attributes. + + + + Base IP-XACT document reference. Contains vendor, library, name and version attributes. + + + + + + Base IP-XACT document reference type for configurable top-level objects. Contains vendor, library, name and version attributes along with configurable element values. + + + + + + + Base IP-XACT document reference. Contains vendor, library, name and version attributes. + + + + diff --git a/ieee-1685-2014/index.xsd b/ieee-1685-2014/index.xsd new file mode 100644 index 0000000..1f18cc5 --- /dev/null +++ b/ieee-1685-2014/index.xsd @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + This IP-XACT schema documentation is part of the IP-XACT standard deliverables. The diagrams in this documentation represent the relationships between elements of the schema together with their attributes and expected values. Valid IP-XACT XML files must have a top-level type that is one of the elements listed here. + + + + + To define all elements and attributes supported when defining a bus. + + + + + + To define all elements and attributes supported when defining a component. + + + + + + To define all elements and attributes supported when defining a design and its configured components + + + + + To define all elements and attributes supported for defining generator chains. + + + + + + + diff --git a/ieee-1685-2014/memoryMap.xsd b/ieee-1685-2014/memoryMap.xsd new file mode 100644 index 0000000..5257af5 --- /dev/null +++ b/ieee-1685-2014/memoryMap.xsd @@ -0,0 +1,1158 @@ + + + + + + + + + The read/write accessability of an addess block. + + + + + + + + + + + + The sharedness of the memoryMap content. + + + + + + + + + + 'serial' or 'parallel' bank alignment. + + + + + + + + + Describes the usage of an address block. + + + + + Denotes an address range that can be used for read-write or read-only data storage. + + + + + Denotes an address block that is used to communicate with hardware. + + + + + Denotes an address range that must remain unoccupied. + + + + + + + Top level bank the specify an address + + + + + + + + + + + + + + + + Describes whether this bank's blocks are aligned in 'parallel' or 'serial'. + + + + + + + Top level bank the specify an address + + + + + + + + + + + + + + + + Describes whether this bank's blocks are aligned in 'parallel' or 'serial'. + + + + + + + Top level address block that specify an address + + + + + + + + + + + + + + + + + + + + Base type for an element which references an address space. Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary. + + + + + + + A reference to a unique address space. + + + + + + + Base type for an element which references an memory map. Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary. + + + + A reference to a unique memory map. + + + + + + Banks nested inside a bank do not specify address. + + + + + + + + + + + + + + + + + + Banks nested inside a bank do not specify address. + + + + + + + + + + + + + + + + + + Address blocks inside a bank do not specify address. + + + + + + + + + + + + + + + + + + + + Subspace references inside banks do not specify an address. + + + + + + + Any parameters that may apply to the subspace reference. + + + + + + + For subspaceMap elements, this attribute identifies the master that contains the address space to be mapped. + + + + + + + A field within a register + + + + + + + + + + + + + + Offset of this field's bit 0 from bit 0 of the register. + + + + + + + + BitField reset value + + + + + + + + + + + + + A unique identifier within a component for a field. + + + + + + A group elements for a memoryMap + + + + + + + Maps in an address subspace from across a bus bridge. Its masterRef attribute refers by name to the master bus interface on the other side of the bridge. It must match the masterRef attribute of a bridge element on the slave interface, and that bridge element must be designated as opaque. + + + + + + + Map of address space blocks on slave slave bus interface. + + + + + + + + Additional memory map elements that are dependent on the component state. + + + + + + + + + + When the value is 'yes', the contents of the memoryMap are shared by all the references to this memoryMap, when the value is 'no' the contents of the memoryMap is not shared and when the value is 'undefined' (default) the sharing of the memoryMap is undefined. + + + + + + + + + Map of address space blocks on a slave bus interface in a specific remap state. + + + + + + + + + State of the component in which the memory map is active. + + + + + + + Map of address space blocks on the local memory map of a master bus interface. + + + + + + + + + Represents a bank of memory made up of address blocks or other banks. It has a bankAlignment attribute indicating whether its blocks are aligned in 'parallel' (occupying adjacent bit fields) or 'serial' (occupying contiguous addresses). Its child blocks do not contain addresses or bit offsets. + + + + + + + + + + + + + Address subspace type. Its subspaceReference attribute references the subspace from which the dimensions are taken. + + + + Any parameters that may apply to the subspace reference. + + + + + + + Any parameters that may apply to the subspace reference. + + + + + + + For subspaceMap elements, this attribute identifies the master that contains the address space to be mapped. + + + + + Refernce to a segment of the addressSpace of the masterRef attribute. + + + + + + Indicates whether the data is volatile. + + + + + Indicates the accessibility of the data in the address bank, address block, register or field. Possible values are 'read-write', 'read-only', 'write-only', 'writeOnce' and 'read-writeOnce'. If not specified the value is inherited from the containing object. + + + + + This is a single contiguous block of memory inside a memory map. + + + + + + + + + References the address space. The name of the address space is kept in its addressSpaceRef attribute. + + + + + If this component is a bus master, this lists all the address spaces +defined by the component. + + + + + + This defines a logical space, referenced by a bus master. + + + + + + + + + Address segments withing an addressSpace + + + + + + Address segment withing an addressSpace + + + + + + + + Address offset of the segment within the containing address space. + + + + + The address range of asegment. Expressed as the number of addressable units accessible to the segment. + + + + + + + + + + + + + + + Provides the local memory map of an address space. Blocks in this memory map are accessable to master interfaces on this component that reference this address space. They are not accessable to any external master interface. + + + + + + + + + Data specific to this address space. + + + + + + + + + + + + + + + + + References the memory map. The name of the memory map is kept in its memoryMapRef attribute. + + + + + Lists all the slave memory maps defined by the component. + + + + + + The set of address blocks a bus slave contributes to the bus' address space. + + + + + + + + + + + + + + + + Represents a bank of memory made up of address blocks or other banks. It has a bankAlignment attribute indicating whether its blocks are aligned in 'parallel' (occupying adjacent bit fields) or 'serial' (occupying contiguous addresses). Its child blocks do not contain addresses or bit offsets. + + + + + + + + + Base of an address block, bank, subspace map or address space. Expressed as the number of addressable units from the containing memoryMap or localMemoryMap. + + + + + The number of data bits in an addressable unit. The default is byte addressable (8 bits). + + + + + This is a group of optional elements commonly added to various types of address blocks in a memory map. + + + + + + + + + This group of elements describes an absolute or relative address of an address block in a memory map. + +Note that this is a group, not an element. It does not appear in the XML, but its contents may. + + + + + + + + This group of elements is common to top level banks and banked banks. + + + + + + + An address block within the bank. No address information is supplied. + + + + + + + + + A nested bank of blocks within a bank. No address information is supplied. + + + + + + + + + A subspace map within the bank. No address information is supplied. + + + + + + + + + + This group of elements is common to top level banks and banked banks. + + + + + + + An address block within the bank. No address information is supplied. + + + + + + + + + A nested bank of blocks within a bank. No address information is supplied. + + + + + + + + + + + + + + This group of elements describes the number of addressable units and the width of a row of an address block in a memory map. + +Note that this is a group, not an element. It does not appear in the XML, but its contents may. + + + + + The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: + number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range + number_of_rows_in_block = number_of_bits_in_block / ipxact:width + + + + + + The bit width of a row in the address block. The range and the width are related by the following formulas: + number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range + number_of_rows_in_block = number_of_bits_in_block / ipxact:width + + + + + + + + This group of optional elements can be used to provide additional descriptions to an address block or bank. + +Note that this is a group, not an element. It does not appear in the XML, but its contents may. + + + + + Indicates the usage of this block. Possible values are 'memory', 'register' and 'reserved'. + + + + + + + Any additional parameters needed to describe this address block to the generators. + + + + + + + This group of optional elements describes the memory mapped registers of an address block + + + + + A single register + + + + + + + + + + + + + + + Dimensions a register array, the semantics for dim elements are the same as the C language standard for the layout of memory in multidimensional arrays. + + + + + + + + + + + + Offset from the address block's baseAddress or the containing register file's addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap. + + + + + + + + + + + + + + + + + A structure of registers and register files + + + + + + + Alternate definitions for the current register + + + + + + Alternate definition for the current register + + + + + + + + + + + + + + + Defines a list of grouping names that this register description belongs. + + + + + + Defines a grouping name that this register description belongs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Enumerates specific values that can be assigned to the bit field. + + + + + + Enumerates specific values that can be assigned to the bit field. The name of this enumerated value. This may be used as a token in generating code. + + + + + + + Enumerated bit field value. + + + + + + + Usage for the enumeration. 'read' for a software read access. 'write' for a software write access. 'read-write' for a software read or write access. + + + + + + + + + + + + + + + + + + + + + + This type is used to specify a value and optional mask that are configurable + + + + + + + + + + + + + + + + + + + + + + + + + + Additional field data + + + + + Indicates whether the data is volatile. The presumed value is 'false' if not present. + + + + + + + If present this element describes the modification of field data caused by a write operation. 'oneToClear' means that in a bitwise fashion each write data bit of a one will clear the corresponding bit in the field. 'oneToSet' means that in a bitwise fashion each write data bit of a one will set the corresponding bit in the field. 'oneToToggle' means that in a bitwise fashion each write data bit of a one will toggle the corresponding bit in the field. 'zeroToClear' means that in a bitwise fashion each write data bit of a zero will clear the corresponding bit in the field. 'zeroToSet' means that in a bitwise fashion each write data bit of a zero will set the corresponding bit in the field. 'zeroToToggle' means that in a bitwise fashion each write data bit of a zero will toggle the corresponding bit in the field. 'clear' means any write to this field clears the field. 'set' means any write to the field sets the field. 'modify' means any write to this field may modify that data. If this element is not present the write operation data is written. + + + + + + + + + + + + The legal values that may be written to a field. If not specified the legal values are not specified. + + + + + A list of possible actions for a read to set the field after the read. 'clear' means that after a read the field is cleared. 'set' means that after a read the field is set. 'modify' means after a read the field is modified. If not present the field value is not modified after a read. + + + + + + + + + + + + Can the field be tested with an automated register test routine. The presumed value is true if not specified. + + + + + + + Constraint for an automated register test routine. 'unconstrained' (default) means may read and write all legal values. 'restore' means may read and write legal values but the value must be restored to the initially read value before accessing another register. 'writeAsRead' has limitations on testability where only the value read before a write may be written to the field. 'readOnly' has limitations on testability where values may only be read from the field. + + + + + + + + + + + + + + + + + Indicates that the field should be documented as reserved. The presumed value is 'false' if not present. + + + + + + + A constraint on the values that can be written to this field. Absence of this element implies that any value that fits can be written to it. + + + + + writeAsRead indicates that only a value immediately read before a write is a legal value to be written. + + + + + useEnumeratedValues indicates that only write enumeration value shall be legal values to be written. + + + + + + The minimum legal value that may be written to a field + + + + + The maximum legal value that may be written to a field + + + + + + + + A structure of registers and register files + + + + + + + + + + + + + + + Dimensions a register array, the semantics for dim elements are the same as the C language standard for the layout of memory in multidimensional arrays. + + + + + + + + + + + + Offset from the address block's baseAddress or the containing register file's addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap. + + + + + + + + + + + + + + + + Field definition specific information + + + + + Identifier name used to indicate that multiple field elements contain the exact same information for the elements in the fieldDefinitionGroup. + + + + + Width of the field in bits. + + + + + + + + Register file defnition specific information + + + + + Identifier name used to indicate that multiple registerFile elements contain the exact same information except for the elements in the registerFileInstanceGroup. + + + + + The range of a register file. Expressed as the number of addressable units accessible to the block. Specified in units of addressUnitBits. + + + + + + + + Address block definition specific information + + + + + Identifier name used to indicate that multiple addressBlock elements contain the exact same information except for the elements in the addressBlockInstanceGroup. + + + + + + + + + + Register definition specific information + + + + + Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup. + + + + + Width of the register in bits. + + + + + + + + Describes individual bit fields within the register. + + + + + + + + + + + + Alternate register definition specific information + + + + + Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the alternateRegisterDefinitionGroup. + + + + + + + + Describes individual bit fields within the register. + + + + + + + + + + + + Register value at reset. + + + + + + The value itself. + + + + + Mask to be anded with the value before comparing to the reset value. + + + + + + Reference to a user defined resetType. Assumed to be HARD if not present. + + + + + + diff --git a/ieee-1685-2014/model.xsd b/ieee-1685-2014/model.xsd new file mode 100644 index 0000000..ac604e0 --- /dev/null +++ b/ieee-1685-2014/model.xsd @@ -0,0 +1,397 @@ + + + + + + + + + + + + + + + Design instantiation type. + + + + + + References an IP-XACT design document (by VLNV) that provides a design for the component. + + + + + + + + + Design configuration instantiation type. + + + + + + The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design. + + + + + References an IP-XACT design configuration document (by VLNV) that provides a configuration for the component's design. + + + + + + + + + + Component instantiation type + + + + + + When true, indicates that this component should not be netlisted. + + + + + The hardware description language used such as "verilog" or "vhdl". If the attribute "strict" is "true", this value must match the language being generated for the design. + + + + + A string specifying the library name in which the model should be compiled. If the libraryName element is not present then its value defaults to “work”. + + + + + A string describing the VHDL package containing the interface of the model. If the packageName element is not present then its value defaults to the component VLNV name concatenated with postfix “_cmp_pkg” which stands for component package. + + + + + A string describing the Verilog, SystemVerilog, or SystemC module name or the VHDL entity name. If the moduleName is not present then its value defaults to the component VLNV name + + + + + A string describing the VHDL architecture name. If the architectureName element is not present then its value defaults to “rtl”. + + + + + A string describing the Verilog, SystemVerilog, or VHDL configuration name. If the configurationName element is not present then its value defaults to the design configuration VLNV name of the design configuration associated with the active hierarchical view or, if there is no active hierarchical view, to the component VLNV name concatenated with postfix “_rtl_cfg”. + + + + + Model parameter name value pairs container + + + + + + A module parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicates how the model parameter is to be used. + + + + + + + + + Default command and flags used to build derived files from the sourceName files in the referenced file sets. + + + + + + + Container for white box element references. + + + + + + Reference to a white box element which is visible within this view. + + + + + + + + + + + + + + + Component Instantiation + + + + + Design Instantiation + + + + + Design Configuration Instantiation + + + + + + + Model information. + + + + + + Views container + + + + + + Single view of a component + + + + + + + + Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments. + + + + + + + + + + + + + + + + + + + + + Instantiations container + + + + + + Component, design, designConfiguration instantiation view of a component + + + + + + + + Port container + + + + + + + + + + + + Model information for an abstractor. + + + + + Views container + + + + + + Single view of an abstracto + + + + + + + + Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values "*Simulation" and "*Synthesis" to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments. + + + + + + + + + + + + + + + + + + + Instantiations container + + + + + + Component Instantiation + + + + + + + + Port container + + + + + + + + + + + + Model information. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Reference to a whiteboxElement within a view. The 'name' attribute must refer to a whiteboxElement defined within this component. + + + + + + The contents of each location element can be used to specified one location (HDL Path) through the referenced whiteBoxElement is accessible. + + + + + + Reference to a whiteboxElement defined within this component. + + + + + + + + + + A value of 'true' indicates that this value must match the language being generated for the design. + + + + + + + + + + + + + diff --git a/ieee-1685-2014/port.xsd b/ieee-1685-2014/port.xsd new file mode 100644 index 0000000..db8507b --- /dev/null +++ b/ieee-1685-2014/port.xsd @@ -0,0 +1,568 @@ + + + + + + + + + + + The direction of a component port. + + + + + + + + + + + A port description, giving a name and an access type for high level ports. + + + + + + + Port style + + + + Defines a port whose type resolves to simple bits. + + + + + Defines a port that implements or uses a service that can be implemented with functions or methods. + + + + + + + Port access characteristics. + + + + + + + + + A port description, giving a name and an access type for high level ports. + + + + + + + + + + Port style + + + + Defines a port whose type resolves to simple bits. + + + + + Defines a port that implements or uses a service that can be implemented with functions or methods. + + + + + + + Port access characteristics. + + + + + + + + + + + + + + + + + + + + + + + If this element is present, the type of access is restricted to the specified value. + + + + + defines the bus size in bits. This can be the result of an expression. + + + + + defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets + + + + + + + + + + + + + + + + + + Indicates how a netlister accesses a port. 'ref' means accessed by reference (default) and 'ptr' means accessed by pointer. + + + + + defines the structure of data transported by this port + + + + + + Defines the name of the payload. For example: TLM2 or TLM1 + + + + + Defines the type of the payload. + + + + + + + + + + + Defines the name of the payload extension. If attribute is not specified, it is by default optional. + + + + + + + True if the payload extension is mandatory. + + + + + + + + + + + + + list of port type parameters (e.g. template or constructor parameters for a systemC port or socket) + + + + + + + + + + + A typed parameter name value pair. The optional attribute dataType defines the type of the value and the usageType attribute indicates how the parameter is to be used. + + + + + + Definition of a single transactional type defintion + + + + + + The name of the port type. Can be any predefined type such sc_port or sc_export in SystemC or any user-defined type such as tlm_port. + + + + + + + When false, defines that the type is an abstract type that may not be related to an existing type in the language of the referenced view. + + + + + + + + + Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition. + + + + + + + + + + + + + A reference to a view name in the file for which this type applies. + + + + + + + + + + + + + + + + Definition of a single service type defintion + + + + + + The name of the service type. Can be any predefined type such as booean or integer or any user-defined type such as addr_type or data_type. + + + + + + + Defines that the typeName supplied for this service is implicit and a netlister should not declare this service in +a language specific top-level netlist + + + + + + + + + Where the definition of the type is contained if the type if not part of the language. For SystemC and SystemVerilog it is the include file containing the type definition. + + + + + + + + + + + + + + + + + Definition of a single wire type defintion that can relate to multiple views. + + + + + + The name of the logic type. Examples could be std_logic, std_ulogic, std_logic_vector, sc_logic, ... + + + + + + + Defines that the type for the port has constrainted the number of bits in the vector + + + + + + + + + Where the definition of the type is contained. For std_logic, this is contained in IEEE.std_logic_1164.all. For sc_logic, this is contained in systemc.h. For VHDL this is the library and package as defined by the "used" statement. For SystemC and SystemVerilog it is the include file required. For verilog this is not needed. + + + + + + + + + + + + A reference to a view name in the file for which this type applies. + + + + + + + + + + + + + + + + The group of type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types. + + + + + + + + + + The group of wire type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types. + + + + + + + + + + + + + + The group of transactional type definitions. If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types. + + + + + + + + + + + + + + Describes port characteristics. + + + + + Wire port type for a component. + + + + + The direction of a wire style port. The basic directions for a port are 'in' for input ports, 'out' for output port and 'inout' for bidirectional and tristate ports. +A value of 'phantom' is also allowed and define a port that exist on the IP-XACT component but not on the HDL model. + + + + + + + + + + True if logical ports with different directions from the physical port direction may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all direction value to be mapped onto the physical port. Also ignored for inout ports, since any logical port maybe mapped to a physical inout port. + + + + + + Transactional port type. + + + + + Defines how the port accesses this service. + + + + + Define the kind of transactional port + + + + + Defines the bus width in bits.This can be the result of an expression. + + + + + Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets + + + + + Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV). + + + + + Bounds number of legal connections. + + + + + + Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections. + + + + + Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1. + + + + + + + + + True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for "both" ports, since any logical port may be mapped to a physical "both" port. + + + + + + + Wire port type for an abstractor. + + + + + + + + + + + + + + + + + Indicates how a netlister accesses a port. 'ref' means accessed by reference (default) and 'ptr' means accessed through a pointer. + + + + + + + + + + + + + diff --git a/ieee-1685-2014/signalDrivers.xsd b/ieee-1685-2014/signalDrivers.xsd new file mode 100644 index 0000000..2d852ae --- /dev/null +++ b/ieee-1685-2014/signalDrivers.xsd @@ -0,0 +1,236 @@ + + + + + + + + + + Default value for a wire port. + + + + + Describes a driven clock port. + + + + + + + Indicates the name of the cllock. If not specified the name is assumed to be the name of the containing port. + + + + + + + + + Describes a driven one-shot port. + + + + + + Time in nanoseconds until start of one-shot. + + + + + Value of port after first edge of one-shot. + + + + + Duration in nanoseconds of the one shot. + + + + + + + + Specifies if a port requires a driver. Default is false. The attribute driverType can further qualify what type of driver is required. Undefined behaviour if direction is not input or inout. Driver type any indicates that any unspecified type of driver must be connected + + + + + + + Defines the type of driver that is required. The default is any type of driver. The 2 other options are a clock type driver or a singleshot type driver. + + + + + + + + + + + + + + + + Wire port driver type. + + + + + + + + + + + + + Container for wire port driver elements. + + + + + + Wire port driver element. If no range is specified, default value applies to the entire range. + + + + + + + + Wire port driver element. + + + + + If this evaluates to true, it indicates this port triggers the reset of registers and fields, if not present its value is assumed to be false. The resetTypeRef attribute indicates the triggered reset event. + + + + + + Reference to a user defined resetType. Assumed to be HARD if not present. + + + + + + + + + + + Clock period in units defined by the units attribute. Default is nanoseconds. + + + + + + + + + + + + Time until first pulse. Units are defined by the units attribute. Default is nanoseconds. + + + + + + + + + + + + Value of port after first clock edge. + + + + + Duration of first state in cycle. Units are defined by the units attribute. Default is nanoseconds. + + + + + + + + + + + + + + + Describes a clock not directly associated with an input port. The clockSource attribute can be used on these clocks to indicate the actual clock source (e.g. an output port of a clock generator cell). + + + + + + + Indicates the name of the clock. + + + + + Indicates the name of the actual clock source (e.g. an output pin of a clock generator cell). + + + + + + + diff --git a/ieee-1685-2014/simpleTypes.xsd b/ieee-1685-2014/simpleTypes.xsd new file mode 100644 index 0000000..74205d1 --- /dev/null +++ b/ieee-1685-2014/simpleTypes.xsd @@ -0,0 +1,284 @@ + + + + + + + + An unsigned longint which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to a unsigend longint value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to an unsigend longint value, this indicates the maximum value allowed. + + + + + + + + + A positive unsigned longint which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to a positive unsigned longint value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a positive unsigned longint value, this indicates the maximum value allowed. + + + + + + + + + An unsigned longint which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to a signed longint value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a signed longint value, this indicates the maximum value allowed. + + + + + + + + + An unsigned int which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed. + + + + + + + + + An positive unsigned int which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed. + + + + + + + + + A signed int which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the maximum value allowed. + + + + + + + + + A real which supports an expression value. + + + + + + For elements which can be specified using expression which are supposed to be resolved to a real value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a real value, this indicates the maximum value allowed. + + + + + + + + + Represents a string. It supports an expression value. + + + + + + + + + IP-XACT URI, like a standard xs:anyURI except that it can contain environment variables in the ${ } form, to be replaced by their value to provide the underlying URI + + + + + + + + + Represents a single-bit/bool. It supports an expression value. + + + + + + + + + Represents a bit-string. It supports an expression value. + + + + + + + + + A type for a port name string, allows letters, digits, dash, colon, underscore and period + + + + + + + + + + A type for a instance name path string, allows letters, digits, dash, colon, underscore, period and slash + + + + + + + + + + + + Represents the base-type for an expressions. + + + + + + + + + + + Represents a single-bit/bool. It supports an expression value. + + + + + + + >An unsigned longint which supports an expression value. + + + + + + + Represents the base-type for an expressions, it forces a non whitespace value to be specified. + + + + + + + diff --git a/ieee-1685-2014/subInstances.xsd b/ieee-1685-2014/subInstances.xsd new file mode 100644 index 0000000..5cc585a --- /dev/null +++ b/ieee-1685-2014/subInstances.xsd @@ -0,0 +1,407 @@ + + + + + + + + + + + An unsigned longint expression that resolves to the value set {0, 1, ...} or open or default. It is derived from longintExpression and it supports an expression value. + + + + + + + For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the minimum value allowed. + + + + + For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the maximum value allowed. + + + + + + + + + + + + + + + + + + + + + + + + + All configuration information for a contained component, generator, generator chain or abstractor instance. + + + + + + Describes the content of a configurable element. The required referenceId attribute refers to the ID attribute of the configurable element. + + + + + + + + Describes the content of a configurable element. The required referenceId attribute refers to the ID attribute of the configurable element. + + + + + + + Refers to the ID attribute of the configurable element. + + + + + + + + + + An instance name assigned to subcomponent instances and contained channels, that is unique within the parent component. + + + + + Component instance element. The instance name is contained in the unique-value instanceName attribute. + + + + + + + + + + References a component to be found in an external library. The four attributes define the VLNV of the referenced element. + + + + + + + + + + Sub instances of internal components. + + + + + + + + + + Represents an ad-hoc connection between component ports. + + + + + + + + The logic value of this connection. The value can be an unsigned longint expression or open or default. Only valid for ports of style wire. + + + + + Liist of internal and external port references involved in the adhocConnection + + + + + + + Defines a reference to a port on a component contained within the design. + + + + + + + + + A reference to the instanceName element of a component in this design. + + + + + A port on the on the referenced component from componentRef. + + + + + + + + + + + + + + + + + + + Defines the set of ad-hoc connections in a design. An ad-hoc connection represents a connection between two component pins which were not connected as a result of interface connections (i.e.the pin to pin connection was made explicitly and is represented explicitly). + + + + + + + + + + Describes a connection between two active (not monitor) busInterfaces. + + + + + + + + Describes one interface of the interconnection. + +The componentRef and busRef attributes indicate the instance name and bus interface name of one end of the connection. This interface can be connected to one or more additional active and/or hierarchical interfaces, or to one or more hierarchical interfaces or to one or more monitor interfaces. The connected interfaces are all contained within the choice element below. + + + + + + + + + + + + + + + + + Hierarchical reference to an interface + + + + + + A decending hierarchical (slash separated - example x/y/z) path to the component instance containing the specified component instance in componentRef. If not specified the componentRef instance shall exist in the current design. + + + + + + + + Describes a connection from the interface of one component to any number of monitor interfaces in the design. + +An active interface can be connected to unlimited number of monitor interfaces. + + + + + + + + Describes an active interface of the design that all the monitors will be connected to. + +The componentRef and busRef attributes indicate the instance name and bus interface name. The optional path attribute indicates the hierarchical instance name path to the component. + + + + + Describes a list of monitor interfaces that are connected to the single active interface. + +The componentRef and busRef attributes indicate the instance name and bus interface name. The optional path attribute indicates the hierarchical instance name path to the component. + + + + + + + + + + + + + + + + + Connections between internal sub components. + + + + + + + + + + + A representation of a component/bus interface relation; i.e. a bus interface belonging to a certain component. + + + + Reference to a component instance name. + + + + + Reference to the components bus interface + + + + + + + A representation of an exported interface. The busRef indicates the name of the interface in the containing component. + + + + + + + + + Reference to the components bus interface + + + + + + + Hierarchical reference to an interface being monitored or monitoring another interface. + + + + + + + + + + A decending hierarchical (slash separated - example x/y/z) path to the component instance containing the specified component instance in componentRef. If not specified the componentRef instance shall exist in the current design. + + + + + + + + + + + + + + A port on the on the referenced component from componentRef. + + + + + + + + + + + + + + + The list of physical ports to be excluded from an interface based connection. Analogous to the removing the port map element for the named ports. + + + + + + The name of a physical port to be excluded from the interface based connection. + + + + + + + + + + + + + + + + + + + diff --git a/ieee-1685-2014/xml.xsd b/ieee-1685-2014/xml.xsd new file mode 100644 index 0000000..85e0a0a --- /dev/null +++ b/ieee-1685-2014/xml.xsd @@ -0,0 +1,8 @@ + + + + + A generic mechanism for annotating elements with unique identifiers. See: http://www.w3.org/TR/xml-id/ for more information. + + + \ No newline at end of file From 9873cdbb5d774678e84b9fd54420e2b809de7a88 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sun, 20 Aug 2023 00:08:04 +0200 Subject: [PATCH 2/2] Added README entry and matching test cases. --- README.md | 2 ++ tests/unit/IPXACT.py | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/README.md b/README.md index 95e8c61..6587dc1 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,8 @@ The original source is [Accellera](https://www.accellera.org/XMLSchema/). **Unknown License State** +* [IEEE Std. 1685-2014](http://www.accellera.org/XMLSchema/IPXACT/1685-2014/) + ⚠️ local [README](ieee-1685-2014/README.md) (text provided by Accellera) contains open source threatening rules * [IEEE Std. 1685-2009](http://www.accellera.org/XMLSchema/SPIRIT/1685-2009/) ⚠️ local [README](ieee-1685-2009/README.md) (text provided by Accellera) contains open source threatening rules diff --git a/tests/unit/IPXACT.py b/tests/unit/IPXACT.py index 9e08c37..92a9820 100644 --- a/tests/unit/IPXACT.py +++ b/tests/unit/IPXACT.py @@ -138,3 +138,22 @@ def test_Schema2009(self): schemaFile = directory / file print(f" {schemaFile}") _ = XMLSchema(schemaFile) + + def test_Schema2014(self): + print() + print(f"CWD: {Path.cwd()}") + + directory = self._root / "ieee-1685-2014" + print(f"Schema directory: {directory}") + + schemaFiles = ( + "design.xsd", + "component.xsd", + "busDefinition.xsd", + "generator.xsd", + ) + print(f"Reading schemas ...") + for file in schemaFiles: + schemaFile = directory / file + print(f" {schemaFile}") + _ = XMLSchema(schemaFile)