diff --git a/.buildinfo b/.buildinfo new file mode 100644 index 00000000..ccea200f --- /dev/null +++ b/.buildinfo @@ -0,0 +1,4 @@ +# Sphinx build info version 1 +# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done. +config: 7133a5af6d992ad8f5e8918c0e42bbf0 +tags: 645f666f9bcd5a90fca523b33c5a78b7 diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 00000000..e69de29b diff --git a/ChangeLog/index.html b/ChangeLog/index.html new file mode 100644 index 00000000..012f963c --- /dev/null +++ b/ChangeLog/index.html @@ -0,0 +1,147 @@ + + + + + + + ChangeLog — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

ChangeLog

+
+

Upcoming Release

+
    +

  • tbd

    • +
+
+
+

01.09.2021

+

pyEDAA.ProjectModel was split from pyIPCMI (v1.1.6) as an independent Python package.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Dependency.html b/Dependency.html new file mode 100644 index 00000000..101cc0cc --- /dev/null +++ b/Dependency.html @@ -0,0 +1,372 @@ + + + + + + + Dependency — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
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+ +
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+
+ +
+

Dependency

+ + + + + + + + + + + +

Libraries.io

Requires.io

Libraries.io status for latest release

Requires.io

+
+

pyEDAA.ProjectModel Package

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pyTooling

≥5.0.0

Apache License, 2.0

None

pyVHDLModel

≥0.27.1

Apache License, 2.0

 +

pySVModel

≥0.3.1

Apache License, 2.0

 +

pySystemRDLModel

≥0.1.0

Apache License, 2.0

 +
+
+
+

Unit Testing / Coverage / Type Checking (Optional)

+

Additional Python packages needed for testing, code coverage collection and static type checking. These packages are +only needed for developers or on a CI server, thus sub-dependencies are not evaluated further.

+

Manually Installing Test Requirements

+

Use the tests/requirements.txt file to install all dependencies via pip3. The file will recursively install +the mandatory dependencies too.

+
pip3 install -U -r tests/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pytest

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MIT

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pytest-cov

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MIT

Not yet evaluated.

Coverage

≥7.3

Apache License, 2.0

Not yet evaluated.

mypy

≥1.5

MIT

Not yet evaluated.

typing-extensions

≥4.7.1

PSF-2.0

Not yet evaluated.

lxml

≥4.9

BSD 3-Clause

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+
+
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Sphinx Documentation (Optional)

+

Additional Python packages needed for documentation generation. These packages are only needed for developers or on a +CI server, thus sub-dependencies are not evaluated further.

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Manually Installing Documentation Requirements

+

Use the doc/requirements.txt file to install all dependencies via pip3. The file will recursively install +the mandatory dependencies too.

+
pip3 install -U -r doc/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

pyTooling

≥5.0.0

Apache License, 2.0

None

Sphinx

≥5.3.0

BSD 3-Clause

Not yet evaluated.

sphinx_btd_theme

≥0.5.2

MIT

Not yet evaluated.

!! sphinx_fontawesome

≥0.0.6

GPL 2.0

Not yet evaluated.

sphinx_autodoc_typehints

≥1.19.5

MIT

Not yet evaluated.

+
+
+

Packaging (Optional)

+

Additional Python packages needed for installation package generation. These packages are only needed for developers or +on a CI server, thus sub-dependencies are not evaluated further.

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Manually Installing Packaging Requirements

+

Use the build/requirements.txt file to install all dependencies via pip3. The file will recursively +install the mandatory dependencies too.

+
pip3 install -U -r build/requirements.txt
+
+
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Dependency List

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Package

Version

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Dependencies

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Apache License, 2.0

None

wheel

≥0.40.0

MIT

Not yet evaluated.

+
+
+

Publishing (CI-Server only)

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+

Manually Installing Publishing Requirements

+

Use the dist/requirements.txt file to install all dependencies via pip3. The file will recursively +install the mandatory dependencies too.

+
pip3 install -U -r dist/requirements.txt
+
+
+

Dependency List

+ + + + + + + + + + + + + + + + + + + + +

Package

Version

License

Dependencies

wheel

≥0.40.0

MIT

Not yet evaluated.

Twine

≥4.0.2

Apache License, 2.0

Not yet evaluated.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Doc-License.html b/Doc-License.html new file mode 100644 index 00000000..8542d67d --- /dev/null +++ b/Doc-License.html @@ -0,0 +1,486 @@ + + + + + + + Creative Commons Attribution 4.0 International — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
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+
+ + + + \ No newline at end of file diff --git a/FileTypes/index.html b/FileTypes/index.html new file mode 100644 index 00000000..81e5b6c7 --- /dev/null +++ b/FileTypes/index.html @@ -0,0 +1,183 @@ + + + + + + + File Types — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

File Types

+

Design Goal

+

TBD

+
+

Content Types

+
+ graph TD; + HRC[HumanReadableContent] --> XMLC[XMLContent]; + HRC --> YAMLC[YAMLContent]; + HRC --> JSONC[JSONContent]; + HRC --> INIC[INIContent]; + HRC --> TOMLC[TOMLContent]; + HRC --> TCLC[TCLContent] --> SDCC[SDCContent]; +
+
+

Overall Hierarchy

+
+ graph TD; + File-->TextFile; + File-->LogFile; + File-->XMLFile; + File--->SourceFile; + File-->ConstraintFile; + File-->ProjectFile; + File-->SettingFile; + SourceFile-->HDLSourceFile; + SourceFile-->NetlistFile; + NetlistFile-->EDIFNetlistFile; + HDLSourceFile-->VHDLSourceFile; + HDLSourceFile-->VerilogSourceFile; + HDLSourceFile-->SystemVerilogSourceFile; + SourceFile-->PythonSourceFile; + PythonSourceFile-->CocotbSourceFile + SourceFile-->CSourceFile; + SourceFile-->CppSourceFile; +
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Glossary.html b/Glossary.html new file mode 100644 index 00000000..6fe582dc --- /dev/null +++ b/Glossary.html @@ -0,0 +1,178 @@ + + + + + + + Glossary — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Glossary

+
+
LRM

Language Reference Manual is the name given to IEEE Standard documents defining Hardware Description Languages:

+ +
+
base-class

An ancestor class for other derived classes.

+
+
File

A representation of a physical file.

+
+
FileSet

A group of files.

+
+
Default fileset

If no fileset is specified, the pre-existing fileset named default is used to group files.

+
+
VHDLLibrary

A namespace in VHDL to group and organize VHDL design units (entity, package, configuration, context).

+
+
Design

A …

+
+
Project

A …

+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/Installation.html b/Installation.html new file mode 100644 index 00000000..bfda14d5 --- /dev/null +++ b/Installation.html @@ -0,0 +1,197 @@ + + + + + + + Installation/Updates — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Installation/Updates

+
+

Note

+

Python ≥3.7 is required for this package due to problems with meta classes and +__getattr__ in Python 3.6.

+
+
+

Using PIP

+
+

Installation from PyPI using PIP

+
pip3 install pyEDAA.ProjectModel
+
+
+
+
+

Updating from PyPI using PIP

+
pip3 install -U pyEDAA.ProjectModel
+
+
+
+
+

Uninstallation using PIP

+
pip3 uninstall pyEDAA.ProjectModel
+
+
+
+
+

Installation from local directory using PIP

+
pip3 install .
+
+
+
+
+
+

Using setup.py (legacy)

+

See sections above on how to use PIP.

+
+

Installation using setup.py

+
setup.py install
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/License.html b/License.html new file mode 100644 index 00000000..59d76c6a --- /dev/null +++ b/License.html @@ -0,0 +1,277 @@ + + + + + + + Apache License 2.0 — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Note

+

This is a local copy of the Apache License Version 2.0.

+
+
+

Attention

+

This Apache License, 2.0 applies to all source and configuration files of project, except documentation.

+
+
+

Apache License 2.0

+

Version 2.0, January 2004

+

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3. Grant of Patent License.

+

Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, +irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such +license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of +their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim +or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then +any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.

+
+
+

4. Redistribution.

+

You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, +provided that You meet the following conditions:

+
    +

  • You must give any other recipients of the Work or Derivative Works a copy of this License; and

    • +

  • You must cause any modified files to carry prominent notices stating that You changed the files; and

    • +

  • You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source +form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and

    • +

  • If the Work includes a “NOTICE” text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the +attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the +following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the +Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE +file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, +alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.

    • +
+

You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or +distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise +complies with the conditions stated in this License.

+
+
+

5. Submission of Contributions.

+

Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and +conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any +separate license agreement you may have executed with Licensor regarding such Contributions.

+
+
+

6. Trademarks.

+

This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable +and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.

+
+
+

7. Disclaimer of Warranty.

+

Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an “AS IS” BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, +MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and +assume any risks associated with Your exercise of permissions under this License.

+
+
+

8. Limitation of Liability.

+

In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or +consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages +for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been +advised of the possibility of such damages.

+
+
+

9. Accepting Warranty or Additional Liability.

+

While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other +liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.

+
+

Appendix: How to apply the Apache License to your work

+

To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets “[]” replaced with your own identifying +information. (Don’t include the brackets!) The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or +class name and description of purpose be included on the same “printed page” as the copyright notice for easier identification within third-party archives.

+
Copyright [yyyy] [name of copyright owner]
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ProjectModel/Design.html b/ProjectModel/Design.html new file mode 100644 index 00000000..3f73032b --- /dev/null +++ b/ProjectModel/Design.html @@ -0,0 +1,252 @@ + + + + + + + Design — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Design

+

Generic description of an EDA design.

+
+

Todo

+

Write documentation.

+
+

Class Relationship

+
+ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style Design fill:#ee9b00 +
+

Condensed definition of class Design

+
@export
+class Design:
+  _name:                  str
+  _project:               Nullable['Project']
+  _directory:             Nullable[Path]
+  _fileSets:              Dict[str, FileSet]
+  _defaultFileSet:        Nullable[FileSet]
+  _vhdlLibraries:         Dict[str, VHDLLibrary]
+  _vhdlVersion:           VHDLVersion
+  _verilogVersion:        VerilogVersion
+  _svVersion:             SystemVerilogVersion
+  _externalVHDLLibraries: List
+
+  def __init__(
+    self,
+    name: str,
+    directory: Path = Path("."),
+    project: 'Project' = None,
+    vhdlVersion: VHDLVersion = None,
+    verilogVersion: VerilogVersion = None,
+    svVersion: SystemVerilogVersion = None
+  ):
+
+  @property
+  def Name(self) -> str:
+
+  @property
+  def Project(self) -> Nullable['Project']:
+  @Project.setter
+  def Project(self, value: 'Project') -> None:
+
+  @property
+  def Directory(self) -> Path:
+  @Directory.setter
+  def Directory(self, value: Path) -> None:
+
+  @property
+  def ResolvedPath(self) -> Path:
+
+  @property
+  def DefaultFileSet(self) -> FileSet:
+  @DefaultFileSet.setter
+  def DefaultFileSet(self, value: Union[str, FileSet]) -> None:
+
+  @property
+  def FileSets(self) -> Dict[str, FileSet]:
+
+  def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]:
+
+  @property
+  def VHDLLibraries(self) -> List[VHDLLibrary]:
+
+  @property
+  def VHDLVersion(self) -> VHDLVersion:
+  @VHDLVersion.setter
+  def VHDLVersion(self, value: VHDLVersion) -> None:
+
+  @property
+  def VerilogVersion(self) -> VerilogVersion:
+  @VerilogVersion.setter
+  def VerilogVersion(self, value: VerilogVersion) -> None:
+
+  @property
+  def SVVersion(self) -> SystemVerilogVersion:
+  @SVVersion.setter
+  def SVVersion(self, value: SystemVerilogVersion) -> None:
+
+  @property
+  def ExternalVHDLLibraries(self) -> List:
+
+  def AddFileSet(self, fileSet: FileSet) -> None:
+
+  def AddFileSets(self, fileSets: Iterable[FileSet]) -> None:
+
+  def AddFile(self, file: File) -> None:
+
+  def AddFiles(self, files: Iterable[File]) -> None:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ProjectModel/File.html b/ProjectModel/File.html new file mode 100644 index 00000000..8cf3812b --- /dev/null +++ b/ProjectModel/File.html @@ -0,0 +1,213 @@ + + + + + + + File — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

File

+

Generic description of a file in EDA design.

+
+

Todo

+

Write documentation.

+
+

Class Relationship

+
+ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style File fill:#ee9b00 +
+

Condensed definition of class File

+
@export
+class File(metaclass=FileType):
+  _path:     Path
+  _project:  Nullable['Project']
+  _design:   Nullable['Design']
+  _fileSet:  Nullable['FileSet']
+
+  def __init__(
+    self,
+    path: Path,
+    project: 'Project' = None,
+    design: 'Design' = None,
+    fileSet: 'FileSet' = None
+  ):
+
+  @property
+  def FileType(self) -> 'FileType':
+
+  @property
+  def Path(self) -> Path:
+
+  @property
+  def ResolvedPath(self) -> Path:
+
+  @property
+  def Project(self) -> Nullable['Project']:
+  @Project.setter
+  def Project(self, value: 'Project') -> None:
+
+  @property
+  def Design(self) -> Nullable['Design']:
+  @Design.setter
+  def Design(self, value: 'Design') -> None:
+
+  @property
+  def FileSet(self) -> Nullable['FileSet']:
+  @FileSet.setter
+  def FileSet(self, value: 'FileSet') -> None:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ProjectModel/FileSet.html b/ProjectModel/FileSet.html new file mode 100644 index 00000000..22f34969 --- /dev/null +++ b/ProjectModel/FileSet.html @@ -0,0 +1,257 @@ + + + + + + + FileSet — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

FileSet

+

Generic description of an EDA file set (group of files).

+
+

Todo

+

Write documentation.

+
+

Class Relationship

+
+ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style FileSet fill:#ee9b00 +
+

Condensed definition of class FileSet

+
@export
+class FileSet:
+  _name:        str
+  _project:     Nullable['Project']
+  _design:      Nullable['Design']
+  _directory:   Nullable[Path]
+  _parent:      Nullable['FileSet']
+  _fileSets:    Dict[str, 'FileSet']
+  _files:       List[File]
+
+  _vhdlLibrary:     'VHDLLibrary'
+  _vhdlVersion:     VHDLVersion
+  _verilogVersion:  VerilogVersion
+  _svVersion:       SystemVerilogVersion
+
+  def __init__(
+    self,
+    name: str,
+    directory: Path = Path("."),
+    project: 'Project' = None,
+    design: 'Design' = None,
+    parent: Nullable['FileSet'] = None,
+    vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
+    vhdlVersion: VHDLVersion = None,
+    verilogVersion: VerilogVersion = None,
+    svVersion: SystemVerilogVersion = None
+  ):
+
+  @property
+  def Name(self) -> str:
+
+  @property
+  def Project(self) -> Nullable['Project']:
+  @Project.setter
+  def Project(self, value: 'Project') -> None:
+
+  @property
+  def Design(self) -> Nullable['Design']:
+  @Design.setter
+  def Design(self, value: 'Design') -> None:
+
+  @property
+  def Directory(self) -> Path:
+  @Directory.setter
+  def Directory(self, value: Path) -> None:
+
+  @property
+  def ResolvedPath(self) -> Path:
+
+  @property
+  def Parent(self) -> Nullable['FileSet']:
+  @Parent.setter
+  def Parent(self, value: 'FileSet') -> None:
+
+  @property
+  def FileSets(self) -> Dict[str, 'FileSet']:
+
+  def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, 'FileSet'] = None) -> Generator[File, None, None]:
+
+  def AddFile(self, file: File) -> None:
+
+  def AddFiles(self, files: Iterable[File]) -> None:
+
+  @property
+  def VHDLLibrary(self) -> 'VHDLLibrary':
+  @VHDLLibrary.setter
+  def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+
+  @property
+  def VHDLVersion(self) -> VHDLVersion:
+  @VHDLVersion.setter
+  def VHDLVersion(self, value: VHDLVersion) -> None:
+
+  @property
+  def VerilogVersion(self) -> VerilogVersion:
+  @VerilogVersion.setter
+  def VerilogVersion(self, value: VerilogVersion) -> None:
+
+  @property
+  def SVVersion(self) -> SystemVerilogVersion:
+  @SVVersion.setter
+  def SVVersion(self, value: SystemVerilogVersion) -> None:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ProjectModel/Project.html b/ProjectModel/Project.html new file mode 100644 index 00000000..20ffadfb --- /dev/null +++ b/ProjectModel/Project.html @@ -0,0 +1,221 @@ + + + + + + + Project — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Project

+

Generic description of an EDA project.

+
+

Todo

+

Write documentation.

+
+

Class Relationship

+
+ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style Project fill:#ee9b00 +
+

Condensed definition of class Project

+
@export
+class Project:
+  _name:                  str
+  _rootDirectory:         Nullable[Path]
+  _designs:               Dict[str, Design]
+  _vhdlVersion:           VHDLVersion
+  _verilogVersion:        VerilogVersion
+  _svVersion:             SystemVerilogVersion
+
+  def __init__(
+    self,
+    name: str,
+    rootDirectory: Path = Path("."),
+    vhdlVersion: VHDLVersion = None,
+    verilogVersion: VerilogVersion = None,
+    svVersion: SystemVerilogVersion = None
+  ):
+
+  @property
+  def Name(self) -> str:
+
+  @property
+  def RootDirectory(self) -> Path:
+  @RootDirectory.setter
+  def RootDirectory(self, value: Path) -> None:
+
+  @property
+  def ResolvedPath(self) -> Path:
+
+  @property
+  def Designs(self) -> Dict[str, Design]:
+
+  @property
+  def VHDLVersion(self) -> VHDLVersion:
+  @VHDLVersion.setter
+  def VHDLVersion(self, value: VHDLVersion) -> None:
+
+  @property
+  def VerilogVersion(self) -> VerilogVersion:
+  @VerilogVersion.setter
+  def VerilogVersion(self, value: VerilogVersion) -> None:
+
+  @property
+  def SVVersion(self) -> SystemVerilogVersion:
+  @SVVersion.setter
+  def SVVersion(self, value: SystemVerilogVersion) -> None:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ProjectModel/VHDLLibrary.html b/ProjectModel/VHDLLibrary.html new file mode 100644 index 00000000..f67a30be --- /dev/null +++ b/ProjectModel/VHDLLibrary.html @@ -0,0 +1,211 @@ + + + + + + + VHDL Library — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

VHDL Library

+

Generic description of a VHDL library (group of VHDL files containing VHDL primary units).

+
+

Todo

+

Write documentation.

+
+

Class Relationship

+
+ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style VHDLLibrary fill:#ee9b00 +
+

Condensed definition of class VHDLLibrary

+
@export
+class VHDLLibrary:
+  _name:        str
+  _project:     Nullable['Project']
+  _design:      Nullable['Design']
+  _files:       List[File]
+  _vhdlVersion: VHDLVersion
+
+  def __init__(
+    self,
+    name: str,
+    project: 'Project' = None,
+    design: 'Design' = None,
+    vhdlVersion: VHDLVersion = None
+  ):
+
+  @property
+  def Name(self) -> str:
+
+  @property
+  def Project(self) -> Nullable['Project']:
+  @Project.setter
+  def Project(self, value: 'Project'):
+
+  @property
+  def Design(self) -> Nullable['Design']:
+  @Design.setter
+  def Design(self, value: 'Design'):
+
+  @property
+  def Files(self) -> Generator[File, None, None]:
+
+  @property
+  def VHDLVersion(self) -> VHDLVersion:
+  @VHDLVersion.setter
+  def VHDLVersion(self, value: VHDLVersion) -> None:
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/ProjectModel/index.html b/ProjectModel/index.html new file mode 100644 index 00000000..8439acf0 --- /dev/null +++ b/ProjectModel/index.html @@ -0,0 +1,183 @@ + + + + + + + Project Model — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Project Model

+

Design Goal

+
    +

  • Clearly named classes that model the semantics of an EDA project.

    • +

  • Child objects shall have a reference to their parent.

    • +
+

Overall Hierarchy

+

An EDA project contains one or multiple variants of a EDA design. +A design then has at least one but usually multiple file sets to group source files and apply settings or attributes to that group.

+
+ graph TD; + Project-->Design_A; + Project-->Design_B; + Design_A-->VHDLLibrary_LA; + Design_A-->FileSet_DefaultA; + Design_A-->FileSet_A1; + Design_A-->FileSet_A2; + FileSet_A2-->FileSet_3 + Design_B-->VHDLLibrary_LB; + Design_B-->FileSet_DefaultB; + Design_B-->FileSet_B1; + Design_B-->FileSet_B2; + FileSet_B2-->FileSet_3 +

Elements of the Project Model

+
+ +
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_images/inheritance-063728fd2cfa34a9b138a69dd16f0b4aaea34177.svg b/_images/inheritance-063728fd2cfa34a9b138a69dd16f0b4aaea34177.svg new file mode 100644 index 00000000..736028d9 --- /dev/null +++ b/_images/inheritance-063728fd2cfa34a9b138a69dd16f0b4aaea34177.svg @@ -0,0 +1,14 @@ + + +inheritancee231accfb7 + + +HumanReadableContent + + +HumanReadableContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-2b5d7dabba4a67f31e52f4fed2225d2c7b10765f.svg b/_images/inheritance-2b5d7dabba4a67f31e52f4fed2225d2c7b10765f.svg new file mode 100644 index 00000000..4ed4bcd4 --- /dev/null +++ b/_images/inheritance-2b5d7dabba4a67f31e52f4fed2225d2c7b10765f.svg @@ -0,0 +1,29 @@ + + +inheritanceadcfb8a705 + + +HumanReadableContent + + +HumanReadableContent + + + + + +YAMLContent + + +YAMLContent + + + + + +HumanReadableContent->YAMLContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-5e17d5028d7232bdd5af9819eadc850b34d6ea50.svg b/_images/inheritance-5e17d5028d7232bdd5af9819eadc850b34d6ea50.svg new file mode 100644 index 00000000..f75bfb3c --- /dev/null +++ b/_images/inheritance-5e17d5028d7232bdd5af9819eadc850b34d6ea50.svg @@ -0,0 +1,44 @@ + + +inheritancef5edb30dd4 + + +HumanReadableContent + + +HumanReadableContent + + + + + +TCLContent + + +TCLContent + + + + + +HumanReadableContent->TCLContent + + + + + +SDCContent + + +SDCContent + + + + + +TCLContent->SDCContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-62e8393f7483867bd82a4a8aee4c9456c248b48c.svg b/_images/inheritance-62e8393f7483867bd82a4a8aee4c9456c248b48c.svg new file mode 100644 index 00000000..61b0703b --- /dev/null +++ b/_images/inheritance-62e8393f7483867bd82a4a8aee4c9456c248b48c.svg @@ -0,0 +1,29 @@ + + +inheritancec2c0e419d2 + + +HumanReadableContent + + +HumanReadableContent + + + + + +XMLContent + + +XMLContent + + + + + +HumanReadableContent->XMLContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-669ae4a4c8413fa1c5ec41beb8ba4abadefe0e89.svg b/_images/inheritance-669ae4a4c8413fa1c5ec41beb8ba4abadefe0e89.svg new file mode 100644 index 00000000..8bf4f0a3 --- /dev/null +++ b/_images/inheritance-669ae4a4c8413fa1c5ec41beb8ba4abadefe0e89.svg @@ -0,0 +1,29 @@ + + +inheritancef90e69562f + + +Attribute + + +Attribute + + + + + +KeyValueAttribute + + +KeyValueAttribute + + + + + +Attribute->KeyValueAttribute + + + + + \ No newline at end of file diff --git a/_images/inheritance-66c4490be2acf871df767ef8626ee61f66927fe4.svg b/_images/inheritance-66c4490be2acf871df767ef8626ee61f66927fe4.svg new file mode 100644 index 00000000..5b318e86 --- /dev/null +++ b/_images/inheritance-66c4490be2acf871df767ef8626ee61f66927fe4.svg @@ -0,0 +1,29 @@ + + +inheritanceed0cac69b5 + + +HumanReadableContent + + +HumanReadableContent + + + + + +TCLContent + + +TCLContent + + + + + +HumanReadableContent->TCLContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-6733c60e688669df4d723d030b94b08771b544f0.svg b/_images/inheritance-6733c60e688669df4d723d030b94b08771b544f0.svg new file mode 100644 index 00000000..54bbbab1 --- /dev/null +++ b/_images/inheritance-6733c60e688669df4d723d030b94b08771b544f0.svg @@ -0,0 +1,29 @@ + + +inheritance6b912cd543 + + +ExtendedType + + +ExtendedType + + + + + +FileType + + +FileType + + + + + +ExtendedType->FileType + + + + + \ No newline at end of file diff --git a/_images/inheritance-696f3f531383281156de220e3f4a329f3b18df01.svg b/_images/inheritance-696f3f531383281156de220e3f4a329f3b18df01.svg new file mode 100644 index 00000000..2a379120 --- /dev/null +++ b/_images/inheritance-696f3f531383281156de220e3f4a329f3b18df01.svg @@ -0,0 +1,14 @@ + + +inheritance12f794fece + + +VHDLLibrary + + +VHDLLibrary + + + + + \ No newline at end of file diff --git a/_images/inheritance-79e991b280af2f60f72a974dfab6a6ad6180cf3f.svg b/_images/inheritance-79e991b280af2f60f72a974dfab6a6ad6180cf3f.svg new file mode 100644 index 00000000..8fbb3289 --- /dev/null +++ b/_images/inheritance-79e991b280af2f60f72a974dfab6a6ad6180cf3f.svg @@ -0,0 +1,29 @@ + + +inheritancec6bf2d3a2b + + +HumanReadableContent + + +HumanReadableContent + + + + + +TOMLContent + + +TOMLContent + + + + + +HumanReadableContent->TOMLContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-85176d5ea3073d3dcf002a61a71a122dd17c682c.svg b/_images/inheritance-85176d5ea3073d3dcf002a61a71a122dd17c682c.svg new file mode 100644 index 00000000..22516378 --- /dev/null +++ b/_images/inheritance-85176d5ea3073d3dcf002a61a71a122dd17c682c.svg @@ -0,0 +1,14 @@ + + +inheritance3952958544 + + +Design + + +Design + + + + + \ No newline at end of file diff --git a/_images/inheritance-9fb593524758443f81df0dc757fb7f3be9c4a8b5.svg b/_images/inheritance-9fb593524758443f81df0dc757fb7f3be9c4a8b5.svg new file mode 100644 index 00000000..16664c0e --- /dev/null +++ b/_images/inheritance-9fb593524758443f81df0dc757fb7f3be9c4a8b5.svg @@ -0,0 +1,14 @@ + + +inheritance76eed77688 + + +Project + + +Project + + + + + \ No newline at end of file diff --git a/_images/inheritance-b7906b5ccd5adab45094b626ae926a7ec93ab2fd.svg b/_images/inheritance-b7906b5ccd5adab45094b626ae926a7ec93ab2fd.svg new file mode 100644 index 00000000..684571fa --- /dev/null +++ b/_images/inheritance-b7906b5ccd5adab45094b626ae926a7ec93ab2fd.svg @@ -0,0 +1,29 @@ + + +inheritance874f3aac8d + + +HumanReadableContent + + +HumanReadableContent + + + + + +PythonContent + + +PythonContent + + + + + +HumanReadableContent->PythonContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-c4954f78e088ea69d4e97f665cbf8389a3e1c8a3.svg b/_images/inheritance-c4954f78e088ea69d4e97f665cbf8389a3e1c8a3.svg new file mode 100644 index 00000000..6cd3fe9d --- /dev/null +++ b/_images/inheritance-c4954f78e088ea69d4e97f665cbf8389a3e1c8a3.svg @@ -0,0 +1,29 @@ + + +inheritancecfec5b17ae + + +HumanReadableContent + + +HumanReadableContent + + + + + +JSONContent + + +JSONContent + + + + + +HumanReadableContent->JSONContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-c64c581cc7329aff1cff1a11167eac6255c63094.svg b/_images/inheritance-c64c581cc7329aff1cff1a11167eac6255c63094.svg new file mode 100644 index 00000000..fc53cdb7 --- /dev/null +++ b/_images/inheritance-c64c581cc7329aff1cff1a11167eac6255c63094.svg @@ -0,0 +1,14 @@ + + +inheritance2bb1a068e1 + + +FileSet + + +FileSet + + + + + \ No newline at end of file diff --git a/_images/inheritance-c8269a4789c1b013e14920d9b73a913ecb7ebb41.svg b/_images/inheritance-c8269a4789c1b013e14920d9b73a913ecb7ebb41.svg new file mode 100644 index 00000000..cab7ee23 --- /dev/null +++ b/_images/inheritance-c8269a4789c1b013e14920d9b73a913ecb7ebb41.svg @@ -0,0 +1,29 @@ + + +inheritancee7e42b3f56 + + +HumanReadableContent + + +HumanReadableContent + + + + + +INIContent + + +INIContent + + + + + +HumanReadableContent->INIContent + + + + + \ No newline at end of file diff --git a/_images/inheritance-ca27c3d2d11b97c480dd00c3d05b875293b39e4a.svg b/_images/inheritance-ca27c3d2d11b97c480dd00c3d05b875293b39e4a.svg new file mode 100644 index 00000000..e980641f --- /dev/null +++ b/_images/inheritance-ca27c3d2d11b97c480dd00c3d05b875293b39e4a.svg @@ -0,0 +1,14 @@ + + +inheritance2935b438b8 + + +Attribute + + +Attribute + + + + + \ No newline at end of file diff --git a/_images/inheritance-d7d978395e7c4d6a16eac8705a996b77e789a75e.svg b/_images/inheritance-d7d978395e7c4d6a16eac8705a996b77e789a75e.svg new file mode 100644 index 00000000..c03e734b --- /dev/null +++ b/_images/inheritance-d7d978395e7c4d6a16eac8705a996b77e789a75e.svg @@ -0,0 +1,29 @@ + + +inheritance4df4ad03ac + + +Attribute + + +Attribute + + + + + +UsedInAttribute + + +UsedInAttribute + + + + + +Attribute->UsedInAttribute + + + + + \ No newline at end of file diff --git a/_images/logo_on_light.svg b/_images/logo_on_light.svg new file mode 100644 index 00000000..eac24d90 --- /dev/null +++ b/_images/logo_on_light.svg @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/_modules/index.html b/_modules/index.html new file mode 100644 index 00000000..b7dcc5cf --- /dev/null +++ b/_modules/index.html @@ -0,0 +1,129 @@ + + + + + + Overview: module code — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+
    +
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All modules for which code is available

+ + +
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+ + + + \ No newline at end of file diff --git a/_modules/pyEDAA/ProjectModel.html b/_modules/pyEDAA/ProjectModel.html new file mode 100644 index 00000000..0ac7efb4 --- /dev/null +++ b/_modules/pyEDAA/ProjectModel.html @@ -0,0 +1,2130 @@ + + + + + + pyEDAA.ProjectModel — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
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+
+ + +
+ +
+
+ +
+
+ +

Source code for pyEDAA.ProjectModel

+# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture     #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""An abstract model of EDA tool projects."""
+__author__ =    "Patrick Lehmann"
+__email__ =     "Paebbels@gmail.com"
+__copyright__ = "2014-2023, Patrick Lehmann, Unai Martinez-Corral"
+__license__ =   "Apache License, Version 2.0"
+__version__ =   "0.5.0"
+__keywords__ =  ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"]
+
+from os.path import relpath as path_relpath
+from pathlib import Path as pathlib_Path
+from typing  import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any
+
+from pyTooling.Decorators  import export
+from pyTooling.MetaClasses import ExtendedType
+from pyTooling.Graph       import Graph, Vertex
+from pySVModel             import SystemVerilogVersion
+from pyVHDLModel           import VHDLVersion
+from pySystemRDLModel      import SystemRDLVersion
+
+
+

+[docs]
+@export
+class Attribute(metaclass=ExtendedType):
+	KEY: str
+	VALUE_TYPE: typing_Any
+
+	@staticmethod
+	def resolve(obj: typing_Any, key: Type['Attribute']):
+		if isinstance(obj, File):
+			return obj._fileSet[key]
+		elif isinstance(obj, FileSet):
+			return obj._design[key]
+		elif isinstance(obj, Design):
+			return obj._project[key]
+		else:
+			raise Exception("Resolution error")

+
+
+
+

+[docs]
+@export
+class FileType(ExtendedType):
+	"""
+	A :term:`meta-class` to construct *FileType* classes.
+
+	Modifications done by this meta-class:
+	* Register all classes of type :class:`FileType` or derived variants in a class field :attr:`FileType.FileTypes` in this meta-class.
+	"""
+
+	FileTypes: Dict[str, 'FileType'] = {}     #: Dictionary of all classes of type :class:`FileType` or derived variants
+	Any: 'FileType'
+
+

+[docs]
+	def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs):
+		super().__init__(name, bases, dictionary, **kwargs)
+		cls.Any = cls

+
+
+

+[docs]
+	def __new__(cls, className, baseClasses, classMembers: Dict, *args, **kwargs):
+		fileType = super().__new__(cls, className, baseClasses, classMembers, *args, **kwargs)
+		cls.FileTypes[className] = fileType
+		return fileType

+
+
+	def __getattr__(cls, item) -> 'FileType':
+		if item[:2] != "__" and item[-2:] != "__":
+			return cls.FileTypes[item]
+		else:
+			return super().__getattribute__(item)
+
+	def __contains__(cls, item) -> bool:
+		return issubclass(item, cls)

+
+
+
+@export
+class File(metaclass=FileType, slots=True):
+	"""
+	A :term:`File` represents a file in a design. This :term:`base-class` is used
+	for all derived file classes.
+
+	A file can be created standalone and later associated to a fileset, design and
+	project. Or a fileset, design and/or project can be associated immediately
+	while creating a file.
+
+	:arg path:    Relative or absolute path to the file.
+	:arg project: Project the file is associated with.
+	:arg design:  Design the file is associated with.
+	:arg fileSet: Fileset the file is associated with.
+	"""
+
+	_path:       pathlib_Path
+	_fileType:   'FileType'
+	_project:    Nullable['Project']
+	_design:     Nullable['Design']
+	_fileSet:    Nullable['FileSet']
+	_attributes: Dict[Type[Attribute], typing_Any]
+
+	def __init__(
+		self,
+		path: pathlib_Path,
+		project: 'Project' = None,
+		design: 'Design' = None,
+		fileSet: 'FileSet' = None
+	):
+		self._fileType =  getattr(FileTypes, self.__class__.__name__)
+		self._path =      path
+		if project is not None:
+			self._project = project
+			self._design =  design
+			if fileSet is not None:
+				self.FileSet =  fileSet
+		elif design is not None:
+			self._project = design._project
+			self._design =  design
+			self.FileSet =  design.DefaultFileSet if fileSet is None else fileSet
+		elif fileSet is not None:
+			design = fileSet._design
+			if design is not None:
+				self._project = design._project
+			else:
+				self._project = None
+			self._design =    design
+			self.FileSet =    fileSet
+		else:
+			self._project = None
+			self._design =  None
+			self._fileSet = None
+
+		self._attributes = {}
+		self._registerAttributes()
+
+	def _registerAttributes(self):
+		pass
+
+	@property
+	def FileType(self) -> 'FileType':
+		"""Read-only property to return the file type of this file."""
+		return self._fileType
+
+	@property
+	def Path(self) -> pathlib_Path:
+		"""Read-only property returning the path of this file."""
+		return self._path
+
+	# TODO: setter?
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this file."""
+		if self._path.is_absolute():
+			return self._path.resolve()
+		elif self._fileSet is not None:
+			path = (self._fileSet.ResolvedPath / self._path).resolve()
+
+			if path.is_absolute():
+				return path
+			else:
+				# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+				return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+		else:
+			# TODO: message and exception type
+			raise Exception("")
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this file is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		self._project = value
+
+		if self._fileSet is None:
+			self._project.DefaultDesign.DefaultFileSet.AddFile(self)
+
+	@property
+	def Design(self) -> Nullable['Design']:
+		"""Property setting or returning the design this file is used in."""
+		return self._design
+
+	@Design.setter
+	def Design(self, value: 'Design') -> None:
+		self._design = value
+
+		if self._fileSet is None:
+			self._design.DefaultFileSet.AddFile(self)
+
+		if self._project is None:
+			self._project = value._project
+		elif self._project is not value._project:
+			raise Exception("The design's project is not identical to the already assigned project.")
+
+	@property
+	def FileSet(self) -> Nullable['FileSet']:
+		"""Property setting or returning the fileset this file is used in."""
+		return self._fileSet
+
+	@FileSet.setter
+	def FileSet(self, value: 'FileSet') -> None:
+		self._fileSet = value
+		value._files.append(self)
+
+	def Validate(self):
+		"""Validate this file."""
+		if self._path is None:
+			raise Exception("Validation: File has no path.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: File '{self._path}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: File '{self._path}' (={path}) does not exist.")
+		if not path.is_file():
+			raise Exception(f"Validation: File '{self._path}' (={path}) is not a file.")
+
+		if self._fileSet is None:
+			raise Exception(f"Validation: File '{self._path}' has no fileset.")
+		if self._design is None:
+			raise Exception(f"Validation: File '{self._path}' has no design.")
+		if self._project is None:
+			raise Exception(f"Validation: File '{self._path}' has no project.")
+
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this file.
+
+		:returns: The number if attributes set on this file.
+		"""
+		return len(self._attributes)
+
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this file.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)
+
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this file.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value
+
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this file.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]
+
+	def __str__(self) -> str:
+		return f"{self._path}"
+
+
+FileTypes = File
+
+
+

+[docs]
+@export
+class HumanReadableContent(metaclass=ExtendedType, mixin=True):
+	"""A file type representing human-readable contents."""

+
+
+
+

+[docs]
+@export
+class XMLContent(HumanReadableContent, mixin=True):
+	"""A file type representing XML contents."""

+
+
+
+

+[docs]
+@export
+class YAMLContent(HumanReadableContent, mixin=True):
+	"""A file type representing YAML contents."""

+
+
+
+

+[docs]
+@export
+class JSONContent(HumanReadableContent, mixin=True):
+	"""A file type representing JSON contents."""

+
+
+
+

+[docs]
+@export
+class INIContent(HumanReadableContent, mixin=True):
+	"""A file type representing INI contents."""

+
+
+
+

+[docs]
+@export
+class TOMLContent(HumanReadableContent, mixin=True):
+	"""A file type representing TOML contents."""

+
+
+
+

+[docs]
+@export
+class TCLContent(HumanReadableContent, mixin=True):
+	"""A file type representing content in TCL code."""

+
+
+
+

+[docs]
+@export
+class SDCContent(TCLContent, mixin=True):
+	"""A file type representing contents as Synopsys Design Constraints (SDC)."""

+
+
+
+

+[docs]
+@export
+class PythonContent(HumanReadableContent, mixin=True):
+	"""A file type representing contents as Python source code."""

+
+
+
+@export
+class TextFile(File, HumanReadableContent):
+	"""A text file (``*.txt``)."""
+
+
+@export
+class LogFile(File, HumanReadableContent):
+	"""A log file (``*.log``)."""
+
+
+@export
+class XMLFile(File, XMLContent):
+	"""An XML file (``*.xml``)."""
+
+
+@export
+class SourceFile(File):
+	"""Base-class of all source files."""
+
+
+@export
+class HDLSourceFile(SourceFile):
+	"""Base-class of all HDL source files."""
+
+
+@export
+class RDLSourceFile(SourceFile):
+	"""Base-class of all RDL source files."""
+
+
+@export
+class NetlistFile(SourceFile):
+	"""Base-class of all netlist source files."""
+
+
+@export
+class EDIFNetlistFile(NetlistFile):
+	"""Netlist file in EDIF (Electronic Design Interchange Format)."""
+
+
+@export
+class TCLSourceFile(SourceFile, TCLContent):
+	"""A TCL source file."""
+
+
+@export
+class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
+	"""
+	A VHDL source file (of any language version).
+
+	:arg path:        Relative or absolute path to the file.
+	:arg vhdlLibrary: VHDLLibrary this VHDL source file is associated wih.
+	:arg vhdlVersion: VHDLVersion this VHDL source file is associated wih.
+	:arg project:     Project the file is associated with.
+	:arg design:      Design the file is associated with.
+	:arg fileSet:     Fileset the file is associated with.
+	"""
+
+	_vhdlLibrary: Nullable['VHDLLibrary']
+	_vhdlVersion: VHDLVersion
+
+	def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: VHDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
+		super().__init__(path, project, design, fileSet)
+
+		if isinstance(vhdlLibrary, str):
+			if design is not None:
+				try:
+					vhdlLibrary = design.VHDLLibraries[vhdlLibrary]
+				except KeyError as ex:
+					raise Exception(f"VHDL library '{vhdlLibrary}' not found in design '{design.Name}'.") from ex
+			elif project is not None:
+				try:
+					vhdlLibrary = project.DefaultDesign.VHDLLibraries[vhdlLibrary]
+				except KeyError as ex:
+					raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex
+			else:
+				raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
+		elif isinstance(vhdlLibrary, VHDLLibrary):
+			self._vhdlLibrary = vhdlLibrary
+			vhdlLibrary.AddFile(self)
+		elif vhdlLibrary is None:
+			self._vhdlLibrary = None
+		else:
+			raise TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
+
+		self._vhdlVersion = vhdlVersion
+
+	def Validate(self) -> None:
+		"""Validate this VHDL source file."""
+		super().Validate()
+
+		try:
+			_ = self.VHDLLibrary
+		except Exception as ex:
+			raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLLibrary assigned.") from ex
+		try:
+			_ = self.VHDLVersion
+		except Exception as ex:
+			raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLVersion assigned.") from ex
+
+	@property
+	def VHDLLibrary(self) -> 'VHDLLibrary':
+		"""Property setting or returning the VHDL library this VHDL source file is used in."""
+		if self._vhdlLibrary is not None:
+			return self._vhdlLibrary
+		elif self._fileSet is not None:
+			return self._fileSet.VHDLLibrary
+		else:
+			raise Exception("VHDLLibrary was neither set locally nor globally.")
+
+	@VHDLLibrary.setter
+	def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+		self._vhdlLibrary = value
+		value._files.append(self)
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		"""Property setting or returning the VHDL version this VHDL source file is used in."""
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._fileSet is not None:
+			return self._fileSet.VHDLVersion
+		else:
+			raise Exception("VHDLVersion was neither set locally nor globally.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	def __repr__(self) -> str:
+		return f"<VHDL file: '{self.ResolvedPath}'; lib: '{self.VHDLLibrary}'; version: {self.VHDLVersion}>"
+
+
+class VerilogMixIn(metaclass=ExtendedType, mixin=True):
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the Verilog version this Verilog source file is used in."""
+		if self._version is not None:
+			return self._version
+		elif self._fileSet is not None:
+			return self._fileSet.VerilogVersion
+		else:
+			raise Exception("VerilogVersion was neither set locally nor globally.")
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._version = value
+
+
+class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True):
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the SystemVerilog version this SystemVerilog source file is used in."""
+		if self._version is not None:
+			return self._version
+		elif self._fileSet is not None:
+			return self._fileSet.SVVersion
+		else:
+			raise Exception("SVVersion was neither set locally nor globally.")
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._version = value
+
+
+@export
+class VerilogBaseFile(HDLSourceFile, HumanReadableContent):
+	_version: SystemVerilogVersion
+
+	def __init__(self, path: pathlib_Path, version: SystemVerilogVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
+		super().__init__(path, project, design, fileSet)
+
+		self._version = version
+
+
+@export
+class VerilogSourceFile(VerilogBaseFile, VerilogMixIn):
+	"""A Verilog source file (of any language version)."""
+
+
+@export
+class VerilogHeaderFile(VerilogBaseFile, VerilogMixIn):
+	"""A Verilog header file (of any language version)."""
+
+
+@export
+class SystemVerilogBaseFile(VerilogBaseFile):
+	...
+
+
+@export
+class SystemVerilogSourceFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+	"""A SystemVerilog source file (of any language version)."""
+
+
+@export
+class SystemVerilogHeaderFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+	"""A SystemVerilog header file (of any language version)."""
+
+
+@export
+class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent):
+	"""A SystemRDL source file (of any language version)."""
+
+	_srdlVersion: SystemRDLVersion
+
+	def __init__(self, path: pathlib_Path, srdlVersion: SystemRDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
+		super().__init__(path, project, design, fileSet)
+
+		self._srdlVersion = srdlVersion
+
+	@property
+	def SystemRDLVersion(self) -> SystemRDLVersion:
+		"""Property setting or returning the SystemRDL version this SystemRDL source file is used in."""
+		if self._srdlVersion is not None:
+			return self._srdlVersion
+		elif self._fileSet is not None:
+			return self._fileSet.SRDLVersion
+		else:
+			raise Exception("SRDLVersion was neither set locally nor globally.")
+
+	@SystemRDLVersion.setter
+	def SystemRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+
+@export
+class PythonSourceFile(SourceFile, PythonContent):
+	"""A Python source file."""
+
+
+# TODO: move to a Cocotb module
+@export
+class CocotbPythonFile(PythonSourceFile):
+	"""A Python source file used by Cocotb."""
+
+
+@export
+class ConstraintFile(File, HumanReadableContent):
+	"""Base-class of all constraint files."""
+
+
+@export
+class ProjectFile(File):
+	"""Base-class of all tool-specific project files."""
+
+
+@export
+class CSourceFile(SourceFile):
+	"""Base-class of all ANSI-C source files."""
+
+
+@export
+class CppSourceFile(SourceFile):
+	"""Base-class of all ANSI-C++ source files."""
+
+
+@export
+class SettingFile(File):
+	"""Base-class of all tool-specific setting files."""
+
+
+@export
+class SimulationAnalysisFile(File):
+	"""Base-class of all tool-specific analysis files."""
+
+
+@export
+class SimulationElaborationFile(File):
+	"""Base-class of all tool-specific elaboration files."""
+
+
+@export
+class SimulationStartFile(File):
+	"""Base-class of all tool-specific simulation start-up files."""
+
+
+@export
+class SimulationRunFile(File):
+	"""Base-class of all tool-specific simulation run (execution) files."""
+
+
+@export
+class WaveformConfigFile(File):
+	"""Base-class of all tool-specific waveform configuration files."""
+
+
+@export
+class WaveformDatabaseFile(File):
+	"""Base-class of all tool-specific waveform database files."""
+
+
+@export
+class WaveformExchangeFile(File):
+	"""Base-class of all tool-independent waveform exchange files."""
+
+
+

+[docs]
+@export
+class FileSet(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`FileSet` represents a group of files. Filesets can have sub-filesets.
+
+	The order of insertion is preserved. A fileset can be created standalone and
+	later associated to another fileset, design and/or project. Or a fileset,
+	design and/or project can be associated immediately while creating the
+	fileset.
+
+	:arg name:            Name of this fileset.
+	:arg topLevel:        Name of the fileset's toplevel.
+	:arg directory:       Path of this fileset (absolute or relative to a parent fileset or design).
+	:arg project:         Project the file is associated with.
+	:arg design:          Design the file is associated with.
+	:arg parent:          Parent fileset if this fileset is nested.
+	:arg vhdlLibrary:     Default VHDL library for files in this fileset, if not specified for the file itself.
+	:arg vhdlVersion:     Default VHDL version for files in this fileset, if not specified for the file itself.
+	:arg verilogVersion:  Default Verilog version for files in this fileset, if not specified for the file itself.
+	:arg svVersion:       Default SystemVerilog version for files in this fileset, if not specified for the file itself.
+	:arg srdlVersion:     Default SystemRDL version for files in this fileset, if not specified for the file itself.
+	"""
+
+	_name:            str
+	_topLevel:        Nullable[str]
+	_project:         Nullable['Project']
+	_design:          Nullable['Design']
+	_directory:       pathlib_Path
+	_parent:          Nullable['FileSet']
+	_fileSets:        Dict[str, 'FileSet']
+	_files:           List[File]
+	_set:             Set
+	_attributes:      Dict[Type[Attribute], typing_Any]
+	_vhdlLibraries:   Dict[str, 'VHDLLibrary']
+	_vhdlLibrary:     'VHDLLibrary'
+	_vhdlVersion:     VHDLVersion
+	_verilogVersion:  SystemVerilogVersion
+	_svVersion:       SystemVerilogVersion
+	_srdlVersion:     SystemRDLVersion
+
+

+[docs]
+	def __init__(
+		self,
+		name: str,
+		topLevel: str = None,
+		directory: pathlib_Path = pathlib_Path("."),
+		project: 'Project' = None,
+		design: 'Design' = None,
+		parent: Nullable['FileSet'] = None,
+		vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
+		vhdlVersion: VHDLVersion = None,
+		verilogVersion: SystemVerilogVersion = None,
+		svVersion: SystemVerilogVersion = None,
+		srdlVersion: SystemRDLVersion = None
+	):
+		self._name =      name
+		self._topLevel =  topLevel
+		if project is not None:
+			self._project = project
+			self._design =  design if design is not None else project.DefaultDesign
+
+		elif design is not None:
+			self._project = design._project
+			self._design =  design
+		else:
+			self._project = None
+			self._design =  None
+		self._directory = directory
+		self._parent =    parent
+		self._fileSets =  {}
+		self._files =     []
+		self._set =     set()
+
+		if design is not None:
+			design._fileSets[name] = self
+
+		self._attributes =      {}
+		self._vhdlLibraries =   {}
+
+		# TODO: handle if vhdlLibrary is a string
+		self._vhdlLibrary =     vhdlLibrary
+		self._vhdlVersion =     vhdlVersion
+		self._verilogVersion =  verilogVersion
+		self._svVersion =       svVersion
+		self._srdlVersion =     srdlVersion

+
+
+	@property
+	def Name(self) -> str:
+		"""Property setting or returning the fileset's name."""
+		return self._name
+
+	@Name.setter
+	def Name(self, value: str) -> None:
+		self._name = value
+
+	@property
+	def TopLevel(self) -> str:
+		"""Property setting or returning the fileset's toplevel."""
+		return self._topLevel
+
+	@TopLevel.setter
+	def TopLevel(self, value: str) -> None:
+		self._topLevel = value
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this fileset is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		self._project = value
+
+	@property
+	def Design(self) -> Nullable['Design']:
+		"""Property setting or returning the design this fileset is used in."""
+		if self._design is not None:
+			return self._design
+		elif self._parent is not None:
+			return self._parent.Design
+		else:
+			return None
+			# TODO: raise exception instead
+			# QUESTION: how to handle if design and parent is set?
+
+	@Design.setter
+	def Design(self, value: 'Design') -> None:
+		self._design = value
+		if self._project is None:
+			self._project = value._project
+		elif self._project is not value._project:
+			raise Exception("The design's project is not identical to the already assigned project.")
+
+	@property
+	def Directory(self) -> pathlib_Path:
+		"""Property setting or returning the directory this fileset is located in."""
+		return self._directory
+
+	@Directory.setter
+	def Directory(self, value: pathlib_Path) -> None:
+		self._directory = value
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this fileset."""
+		if self._directory.is_absolute():
+			return self._directory.resolve()
+		else:
+			if self._parent is not None:
+				directory = self._parent.ResolvedPath
+			elif self._design is not None:
+				directory = self._design.ResolvedPath
+			elif self._project is not None:
+				directory = self._project.ResolvedPath
+			else:
+				# TODO: message and exception type
+				raise Exception("")
+
+			directory = (directory / self._directory).resolve()
+			if directory.is_absolute():
+				return directory
+			else:
+				# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+				return pathlib_Path(path_relpath(directory, pathlib_Path.cwd()))
+
+	@property
+	def Parent(self) -> Nullable['FileSet']:
+		"""Property setting or returning the parent fileset this fileset is used in."""
+		return self._parent
+
+	@Parent.setter
+	def Parent(self, value: 'FileSet') -> None:
+		self._parent = value
+		value._fileSets[self._name] = self
+		# TODO: check it it already exists
+		# QUESTION: make an Add fileset method?
+
+	@property
+	def FileSets(self) -> Dict[str, 'FileSet']:
+		"""Read-only property returning the dictionary of sub-filesets."""
+		return self._fileSets
+
+

+[docs]
+	def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[bool, str, 'FileSet'] = None) -> Generator[File, None, None]:
+		"""
+		Method returning the files of this fileset.
+
+		:arg fileType: A filter for file types. Default: ``Any``.
+		:arg fileSet:  Specifies how to handle sub-filesets.
+		"""
+		if fileSet is False:
+			for file in self._files:
+				if file.FileType in fileType:
+					yield file
+		elif fileSet is None:
+			for fileSet in self._fileSets.values():
+				for file in fileSet.Files(fileType):
+					yield file
+			for file in self._files:
+				if file.FileType in fileType:
+					yield file
+		else:
+			if isinstance(fileSet, str):
+				fileSetName = fileSet
+				try:
+					fileSet = self._fileSets[fileSetName]
+				except KeyError as ex:
+					raise Exception(f"Fileset {fileSetName} not bound to fileset {self.Name}.") from ex
+			elif not isinstance(fileSet, FileSet):
+				raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+
+			for file in fileSet.Files(fileType):
+				yield file

+
+
+

+[docs]
+	def AddFileSet(self, fileSet: "FileSet") -> None:
+		"""
+		Method to add a single sub-fileset to this fileset.
+
+		:arg fileSet: A fileset to add to this fileset as sub-fileset.
+		"""
+		if not isinstance(fileSet, FileSet):
+			raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+		elif fileSet in self._fileSets:
+			raise Exception("Sub-fileset already contains this fileset.")
+		elif fileSet.Name in self._fileSets.keys():
+			raise Exception(f"Fileset already contains a sub-fileset named '{fileSet.Name}'.")
+
+		self._fileSets[fileSet.Name] = fileSet
+		fileSet._parent = self

+
+
+

+[docs]
+	def AddFileSets(self, fileSets: Iterable["FileSet"]) -> None:
+		"""
+		Method to add a multiple sub-filesets to this fileset.
+
+		:arg fileSets: An iterable of filesets to add each to the fileset.
+		"""
+		for fileSet in fileSets:
+			self.AddFileSet(fileSet)

+
+
+	@property
+	def FileSetCount(self) -> int:
+		"""Returns number of file sets excl. sub-filesets."""
+		return len(self._fileSets)
+
+	@property
+	def TotalFileSetCount(self) -> int:
+		"""Returns number of file sets incl. sub-filesets."""
+		fileSetCount = len(self._fileSets)
+		for fileSet in self._fileSets.values():
+			fileSetCount += fileSet.TotalFileSetCount
+
+		return fileSetCount
+
+

+[docs]
+	def AddFile(self, file: File) -> None:
+		"""
+		Method to add a single file to this fileset.
+
+		:arg file: A file to add to this fileset.
+		"""
+		if not isinstance(file, File):
+			raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
+		elif file._fileSet is not None:
+			ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
+			ex.add_note(f"A file can't be assigned to another fileset.")
+			raise ex
+		elif file in self._set:
+			ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
+			ex.add_note(f"A file can't be added twice to a fileset.")
+			raise ex
+
+		self._files.append(file)
+		self._set.add(file)
+		file._fileSet = self

+
+
+

+[docs]
+	def AddFiles(self, files: Iterable[File]) -> None:
+		"""
+		Method to add a multiple files to this fileset.
+
+		:arg files: An iterable of files to add each to the fileset.
+		"""
+		for file in files:
+			self.AddFile(file)

+
+
+	@property
+	def FileCount(self) -> int:
+		"""Returns number of files excl. sub-filesets."""
+		return len(self._files)
+
+	@property
+	def TotalFileCount(self) -> int:
+		"""Returns number of files incl. the files in sub-filesets."""
+		fileCount = len(self._files)
+		for fileSet in self._fileSets.values():
+			fileCount += fileSet.FileCount
+
+		return fileCount
+
+

+[docs]
+	def Validate(self) -> None:
+		"""Validate this fileset."""
+		if self._name is None or self._name == "":
+			raise Exception("Validation: FileSet has no name.")
+
+		if self._directory is None:
+			raise Exception(f"Validation: FileSet '{self._name}' has no directory.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: FileSet '{self._name}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' does not exist.")
+		if not path.is_dir():
+			raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' is not a directory.")
+
+		if self._design is None:
+			raise Exception(f"Validation: FileSet '{self._directory}' has no design.")
+		if self._project is None:
+			raise Exception(f"Validation: FileSet '{self._directory}' has no project.")
+
+		for fileSet in self._fileSets.values():
+			fileSet.Validate()
+		for file in self._files:
+			file.Validate()

+
+
+	def GetOrCreateVHDLLibrary(self, name) -> 'VHDLLibrary':
+		if name in self._vhdlLibraries:
+			return self._vhdlLibraries[name]
+		elif name in self._design._vhdlLibraries:
+			library = self._design._vhdlLibraries[name]
+			self._vhdlLibraries[name] = library
+			return library
+		else:
+			library = VHDLLibrary(name, design=self._design, vhdlVersion=self._vhdlVersion)
+			self._vhdlLibraries[name] = library
+			return library
+
+	@property
+	def VHDLLibrary(self) -> 'VHDLLibrary':
+		"""Property setting or returning the VHDL library of this fileset."""
+		if self._vhdlLibrary is not None:
+			return self._vhdlLibrary
+		elif self._parent is not None:
+			return self._parent.VHDLLibrary
+		elif self._design is not None:
+			return self._design.VHDLLibrary
+		else:
+			raise Exception("VHDLLibrary was neither set locally nor globally.")
+
+	@VHDLLibrary.setter
+	def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+		self._vhdlLibrary = value
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		"""Property setting or returning the VHDL version of this fileset."""
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._parent is not None:
+			return self._parent.VHDLVersion
+		elif self._design is not None:
+			return self._design.VHDLVersion
+		else:
+			raise Exception("VHDLVersion was neither set locally nor globally.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the Verilog version of this fileset."""
+		if self._verilogVersion is not None:
+			return self._verilogVersion
+		elif self._parent is not None:
+			return self._parent.VerilogVersion
+		elif self._design is not None:
+			return self._design.VerilogVersion
+		else:
+			raise Exception("VerilogVersion was neither set locally nor globally.")
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._verilogVersion = value
+
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the SystemVerilog version of this fileset."""
+		if self._svVersion is not None:
+			return self._svVersion
+		elif self._parent is not None:
+			return self._parent.SVVersion
+		elif self._design is not None:
+			return self._design.SVVersion
+		else:
+			raise Exception("SVVersion was neither set locally nor globally.")
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._svVersion = value
+
+	@property
+	def SRDLVersion(self) -> SystemRDLVersion:
+		if self._srdlVersion is not None:
+			return self._srdlVersion
+		elif self._parent is not None:
+			return self._parent.SRDLVersion
+		elif self._design is not None:
+			return self._design.SRDLVersion
+		else:
+			raise Exception("SRDLVersion was neither set locally nor globally.")
+
+	@SRDLVersion.setter
+	def SRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+

+[docs]
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this fileset.
+
+		:returns: The number if attributes set on this fileset.
+		"""
+		return len(self._attributes)

+
+
+

+[docs]
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this fileset.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)

+
+
+

+[docs]
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this fileset.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value

+
+
+

+[docs]
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this fileset.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]

+
+
+

+[docs]
+	def __str__(self) -> str:
+		"""Returns the fileset's name."""
+		return self._name

+

+
+
+
+

+[docs]
+@export
+class VHDLLibrary(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library.
+
+	:arg name:        The VHDL libraries' name.
+	:arg project:     Project the VHDL library is associated with.
+	:arg design:      Design the VHDL library is associated with.
+	:arg vhdlVersion: Default VHDL version for files in this VHDL library, if not specified for the file itself.
+	"""
+
+	_name:        str
+	_project:     Nullable['Project']
+	_design:      Nullable['Design']
+	_files:       List[File]
+	_vhdlVersion: VHDLVersion
+
+	_dependencyNode: Vertex
+
+

+[docs]
+	def __init__(
+		self,
+		name: str,
+		project: 'Project' = None,
+		design: 'Design' = None,
+		vhdlVersion: VHDLVersion = None
+	):
+		self._name =    name
+		if project is not None:
+			self._project = project
+			self._design = project._defaultDesign if design is None else design
+			self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+
+			if name in self._design._vhdlLibraries:
+				raise Exception(f"Library '{name}' already in design '{self._design.Name}'.")
+			else:
+				self._design._vhdlLibraries[name] = self
+
+		elif design is not None:
+			self._project = design._project
+			self._design = design
+			self._dependencyNode = Vertex(value=self, graph=design._vhdlLibraryDependencyGraph)
+
+			if name in design._vhdlLibraries:
+				raise Exception(f"Library '{name}' already in design '{design.Name}'.")
+			else:
+				design._vhdlLibraries[name] = self
+
+		else:
+			self._project = None
+			self._design =  None
+			self._dependencyNode = None
+
+		self._files =     []
+		self._vhdlVersion = vhdlVersion

+
+
+	@property
+	def Name(self) -> str:
+		return self._name
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this VHDL library is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		if not isinstance(value, Project):
+			raise TypeError("Parameter 'value' is not of type 'Project'.")
+
+		if value is None:
+			# TODO: unlink VHDLLibrary from project
+			self._project = None
+		else:
+			self._project = value
+			if self._design is None:
+				self._design = value._defaultDesign
+
+	@property
+	def Design(self) -> Nullable['Design']:
+		"""Property setting or returning the design this VHDL library is used in."""
+		return self._design
+
+	@Design.setter
+	def Design(self, value: 'Design') -> None:
+		if not isinstance(value, Design):
+			raise TypeError("Parameter 'value' is not of type 'Design'.")
+
+		if value is None:
+			# TODO: unlink VHDLLibrary from design
+			self._design = None
+		else:
+			if self._design is None:
+				self._design = value
+				self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+			elif self._design is not value:
+				# TODO: move VHDLLibrary to other design
+				# TODO: create new vertex in dependency graph and remove vertex from old graph
+				self._design = value
+			else:
+				pass
+
+			if self._project is None:
+				self._project = value._project
+			elif self._project is not value._project:
+				raise Exception("The design's project is not identical to the already assigned project.")
+
+	@property
+	def Files(self) -> Generator[File, None, None]:
+		"""Read-only property to return all files in this VHDL library."""
+		for file in self._files:
+			yield file
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		"""Property setting or returning the VHDL version of this VHDL library."""
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._design is not None:
+			return self._design.VHDLVersion
+		else:
+			raise Exception("VHDLVersion is not set on VHDLLibrary nor parent object.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	def AddDependency(self, library: 'VHDLLibrary') -> None:
+		library.parent = self
+
+	def AddFile(self, vhdlFile: VHDLSourceFile) -> None:
+		if not isinstance(vhdlFile, VHDLSourceFile):
+			raise TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
+
+		self._files.append(vhdlFile)
+
+	def AddFiles(self, vhdlFiles: Iterable[VHDLSourceFile]) -> None:
+		for vhdlFile in vhdlFiles:
+			if not isinstance(vhdlFile, VHDLSourceFile):
+				raise TypeError(f"Item '{vhdlFile}' in parameter 'vhdlFiles' is not a 'VHDLSourceFile'.")
+
+			self._files.append(vhdlFile)
+
+	@property
+	def FileCount(self) -> int:
+		"""Returns number of files."""
+		return len(self._files)
+
+

+[docs]
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this VHDL library.
+
+		:returns: The number if attributes set on this VHDL library.
+		"""
+		return len(self._attributes)

+
+
+

+[docs]
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this VHDL library.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)

+
+
+

+[docs]
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this VHDL library.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value

+
+
+

+[docs]
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this VHDL library.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]

+
+
+

+[docs]
+	def __str__(self) -> str:
+		"""Returns the VHDL library's name."""
+		return self._name

+

+
+
+
+

+[docs]
+@export
+class Design(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`Design` represents a group of filesets and the source files therein.
+
+	Each design contains at least one fileset - the :term:`default fileset`. For
+	designs with VHDL source files, a independent `VHDLLibraries` overlay structure
+	exists.
+
+	:arg name:            The design's name.
+	:arg topLevel:        Name of the design's toplevel.
+	:arg directory:       Path of this design (absolute or relative to the project).
+	:arg project:         Project the design is associated with.
+	:arg vhdlVersion:     Default VHDL version for files in this design, if not specified for the file itself.
+	:arg verilogVersion:  Default Verilog version for files in this design, if not specified for the file itself.
+	:arg svVersion:       Default SystemVerilog version for files in this design, if not specified for the file itself.
+	:arg srdlVersion:     Default SystemRDL version for files in this fileset, if not specified for the file itself.
+	"""
+
+	_name:                  str
+	_topLevel:              Nullable[str]
+	_project:               Nullable['Project']
+	_directory:             pathlib_Path
+	_fileSets:              Dict[str, FileSet]
+	_defaultFileSet:        Nullable[FileSet]
+	_attributes:            Dict[Type[Attribute], typing_Any]
+
+	_vhdlLibraries:         Dict[str, VHDLLibrary]
+	_vhdlVersion:           VHDLVersion
+	_verilogVersion:        SystemVerilogVersion
+	_svVersion:             SystemVerilogVersion
+	_srdlVersion:           SystemRDLVersion
+	_externalVHDLLibraries: List
+
+	_vhdlLibraryDependencyGraph: Graph
+	_fileDependencyGraph:        Graph
+
+

+[docs]
+	def __init__(
+		self,
+		name: str,
+		topLevel: str = None,
+		directory: pathlib_Path = pathlib_Path("."),
+		project: 'Project' = None,
+		vhdlVersion: VHDLVersion = None,
+		verilogVersion: SystemVerilogVersion = None,
+		svVersion: SystemVerilogVersion = None,
+		srdlVersion: SystemRDLVersion = None
+	):
+		self._name =                  name
+		self._topLevel =              topLevel
+		self._project =               project
+		if project is not None:
+			project._designs[name] = self
+		self._directory =             directory
+		self._fileSets =              {}
+		self._defaultFileSet =        FileSet("default", project=project, design=self)
+		self._attributes =            {}
+		self._vhdlLibraries =         {}
+		self._vhdlVersion =           vhdlVersion
+		self._verilogVersion =        verilogVersion
+		self._svVersion =             svVersion
+		self._srdlVersion =           srdlVersion
+		self._externalVHDLLibraries = []
+
+		self._vhdlLibraryDependencyGraph = Graph()
+		self._fileDependencyGraph = Graph()

+
+
+	@property
+	def Name(self) -> str:
+		"""Property setting or returning the design's name."""
+		return self._name
+
+	@Name.setter
+	def Name(self, value: str) -> None:
+		self._name = value
+
+	@property
+	def TopLevel(self) -> str:
+		"""Property setting or returning the fileset's toplevel."""
+		return self._topLevel
+
+	@TopLevel.setter
+	def TopLevel(self, value: str) -> None:
+		self._topLevel = value
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this design is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		self._project = value
+
+	@property
+	def Directory(self) -> pathlib_Path:
+		"""Property setting or returning the directory this design is located in."""
+		return self._directory
+
+	@Directory.setter
+	def Directory(self, value: pathlib_Path) -> None:
+		self._directory = value
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this fileset."""
+		if self._directory.is_absolute():
+			return self._directory.resolve()
+		elif self._project is not None:
+			path = (self._project.ResolvedPath / self._directory).resolve()
+
+			if path.is_absolute():
+				return path
+			else:
+				# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+				return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+		else:
+			# TODO: message and exception type
+			raise Exception("")
+
+	@property
+	def DefaultFileSet(self) -> FileSet:
+		"""Property setting or returning the default fileset of this design."""
+		return self._defaultFileSet
+
+	@DefaultFileSet.setter
+	def DefaultFileSet(self, value: Union[str, FileSet]) -> None:
+		if isinstance(value, str):
+			if value not in self._fileSets.keys():
+				raise Exception(f"Fileset '{value}' is not in this design.")
+
+			self._defaultFileSet = self._fileSets[value]
+		elif isinstance(value, FileSet):
+			if value not in self.FileSets:
+				raise Exception(f"Fileset '{value}' is not associated to this design.")
+
+			self._defaultFileSet = value
+		else:
+			raise ValueError("Unsupported parameter type for 'value'.")
+
+	# TODO: return generator with another method
+	@property
+	def FileSets(self) -> Dict[str, FileSet]:
+		"""Read-only property returning the dictionary of filesets."""
+		return self._fileSets
+
+

+[docs]
+	def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]:
+		"""
+		Method returning the files of this design.
+
+		:arg fileType: A filter for file types. Default: ``Any``.
+		:arg fileSet:  Specifies if all files from all filesets (``fileSet=None``) are files from a single fileset are returned.
+		"""
+		if fileSet is None:
+			for fileSet in self._fileSets.values():
+				for file in fileSet.Files(fileType):
+					yield file
+		else:
+			if isinstance(fileSet, str):
+				try:
+					fileSet = self._fileSets[fileSet]
+				except KeyError as ex:
+					raise Exception(f"Fileset {fileSet.Name} not bound to design {self.Name}.") from ex
+			elif not isinstance(fileSet, FileSet):
+				raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+
+			for file in fileSet.Files(fileType):
+				yield file

+
+
+

+[docs]
+	def Validate(self) -> None:
+		"""Validate this design."""
+		if self._name is None or self._name == "":
+			raise Exception("Validation: Design has no name.")
+
+		if self._directory is None:
+			raise Exception(f"Validation: Design '{self._name}' has no directory.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: Design '{self._name}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: Design '{self._name}'s directory '{path}' does not exist.")
+		if not path.is_dir():
+			raise Exception(f"Validation: Design '{self._name}'s directory '{path}' is not a directory.")
+
+		if len(self._fileSets) == 0:
+			raise Exception(f"Validation: Design '{self._name}' has no fileset.")
+		try:
+			if self._defaultFileSet is not self._fileSets[self._defaultFileSet.Name]:
+				raise Exception(f"Validation: Design '{self._name}'s default fileset is the same as listed in filesets.")
+		except KeyError as ex:
+			raise Exception(f"Validation: Design '{self._name}'s default fileset is not in list of filesets.") from ex
+		if self._project is None:
+			raise Exception(f"Validation: Design '{self._path}' has no project.")
+
+		for fileSet in self._fileSets.values():
+			fileSet.Validate()

+
+
+	@property
+	def VHDLLibraries(self) -> Dict[str, VHDLLibrary]:
+		return self._vhdlLibraries
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._project is not None:
+			return self._project.VHDLVersion
+		else:
+			raise Exception("VHDLVersion was neither set locally nor globally.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		if self._verilogVersion is not None:
+			return self._verilogVersion
+		elif self._project is not None:
+			return self._project.VerilogVersion
+		else:
+			raise Exception("VerilogVersion was neither set locally nor globally.")
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._verilogVersion = value
+
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		if self._svVersion is not None:
+			return self._svVersion
+		elif self._project is not None:
+			return self._project.SVVersion
+		else:
+			raise Exception("SVVersion was neither set locally nor globally.")
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._svVersion = value
+
+	@property
+	def SRDLVersion(self) -> SystemRDLVersion:
+		if self._srdlVersion is not None:
+			return self._srdlVersion
+		elif self._project is not None:
+			return self._project.SRDLVersion
+		else:
+			raise Exception("SRDLVersion was neither set locally nor globally.")
+
+	@SRDLVersion.setter
+	def SRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+	@property
+	def ExternalVHDLLibraries(self) -> List:
+		return self._externalVHDLLibraries
+
+	def AddFileSet(self, fileSet: FileSet) -> None:
+		if not isinstance(fileSet, FileSet):
+			raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+		elif fileSet in self._fileSets:
+			raise Exception("Design already contains this fileset.")
+		elif fileSet.Name in self._fileSets.keys():
+			raise Exception(f"Design already contains a fileset named '{fileSet.Name}'.")
+
+		self._fileSets[fileSet.Name] = fileSet
+		fileSet.Design = self
+		fileSet._parent = self
+
+	def AddFileSets(self, fileSets: Iterable[FileSet]) -> None:
+		for fileSet in fileSets:
+			self.AddFileSet(fileSet)
+
+	@property
+	def FileSetCount(self) -> int:
+		"""Returns number of file sets excl. sub-filesets."""
+		return len(self._fileSets)
+
+	@property
+	def TotalFileSetCount(self) -> int:
+		"""Returns number of file sets incl. sub-filesets."""
+		fileSetCount = len(self._fileSets)
+		for fileSet in self._fileSets.values():
+			fileSetCount += fileSet.TotalFileSetCount
+
+		return fileSetCount
+
+	def AddFile(self, file: File) -> None:
+		if file.FileSet is None:
+			self._defaultFileSet.AddFile(file)
+		else:
+			raise ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}' and can't be assigned via Design to a default fileset.")
+
+	def AddFiles(self, files: Iterable[File]) -> None:
+		for file in files:
+			self.AddFile(file)
+
+	def AddVHDLLibrary(self, vhdlLibrary: VHDLLibrary) -> None:
+		if vhdlLibrary.Name in self._vhdlLibraries:
+			if self._vhdlLibraries[vhdlLibrary.Name] is vhdlLibrary:
+				raise Exception(f"The VHDLLibrary '{vhdlLibrary.Name}' was already added to the design.")
+			else:
+				raise Exception(f"A VHDLLibrary with same name ('{vhdlLibrary.Name}') already exists for this design.")
+
+
+

+[docs]
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this design.
+
+		:returns: The number if attributes set on this design.
+		"""
+		return len(self._attributes)

+
+
+

+[docs]
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this design.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)

+
+
+

+[docs]
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this design.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value

+
+
+

+[docs]
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this design.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return self._name

+

+
+
+
+

+[docs]
+@export
+class Project(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`Project` represents a group of designs and the source files therein.
+
+	:arg name:            The project's name.
+	:arg rootDirectory:   Base-path to the project.
+	:arg vhdlVersion:     Default VHDL version for files in this project, if not specified for the file itself.
+	:arg verilogVersion:  Default Verilog version for files in this project, if not specified for the file itself.
+	:arg svVersion:       Default SystemVerilog version for files in this project, if not specified for the file itself.
+	"""
+
+	_name:            str
+	_rootDirectory:   pathlib_Path
+	_designs:         Dict[str, Design]
+	_defaultDesign:   Design
+	_attributes:      Dict[Type[Attribute], typing_Any]
+
+	_vhdlVersion:     VHDLVersion
+	_verilogVersion:  SystemVerilogVersion
+	_svVersion:       SystemVerilogVersion
+	_srdlVersion:     SystemRDLVersion
+
+

+[docs]
+	def __init__(
+		self,
+		name: str,
+		rootDirectory: pathlib_Path = pathlib_Path("."),
+		vhdlVersion: VHDLVersion = None,
+		verilogVersion: SystemVerilogVersion = None,
+		svVersion: SystemVerilogVersion = None
+	):
+		self._name =            name
+		self._rootDirectory =   rootDirectory
+		self._designs =         {}
+		self._defaultDesign =   Design("default", project=self)
+		self._attributes =      {}
+		self._vhdlVersion =     vhdlVersion
+		self._verilogVersion =  verilogVersion
+		self._svVersion =       svVersion

+
+
+	@property
+	def Name(self) -> str:
+		"""Property setting or returning the project's name."""
+		return self._name
+
+	@property
+	def RootDirectory(self) -> pathlib_Path:
+		"""Property setting or returning the root directory this project is located in."""
+		return self._rootDirectory
+
+	@RootDirectory.setter
+	def RootDirectory(self, value: pathlib_Path) -> None:
+		self._rootDirectory = value
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this fileset."""
+		path = self._rootDirectory.resolve()
+		if self._rootDirectory.is_absolute():
+			return path
+		else:
+			# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+			return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+
+	# TODO: return generator with another method
+	@property
+	def Designs(self) -> Dict[str, Design]:
+		return self._designs
+
+	@property
+	def DefaultDesign(self) -> Design:
+		return self._defaultDesign
+
+

+[docs]
+	def Validate(self) -> None:
+		"""Validate this project."""
+		if self._name is None or self._name == "":
+			raise Exception("Validation: Project has no name.")
+
+		if self._rootDirectory is None:
+			raise Exception(f"Validation: Project '{self._name}' has no root directory.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: Project '{self._name}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: Project '{self._name}'s directory '{path}' does not exist.")
+		if not path.is_dir():
+			raise Exception(f"Validation: Project '{self._name}'s directory '{path}' is not a directory.")
+
+		if len(self._designs) == 0:
+			raise Exception(f"Validation: Project '{self._name}' has no design.")
+		try:
+			if self._defaultDesign is not self._designs[self._defaultDesign.Name]:
+				raise Exception(f"Validation: Project '{self._name}'s default design is the same as listed in designs.")
+		except KeyError as ex:
+			raise Exception(f"Validation: Project '{self._name}'s default design is not in list of designs.") from ex
+
+		for design in self._designs.values():
+			design.Validate()

+
+
+	@property
+	def DesignCount(self) -> int:
+		"""Returns number of designs."""
+		return len(self._designs)
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		# TODO: check for None and return exception
+		return self._vhdlVersion
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		# TODO: check for None and return exception
+		return self._verilogVersion
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._verilogVersion = value
+
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		# TODO: check for None and return exception
+		return self._svVersion
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._svVersion = value
+
+	@property
+	def SRDLVersion(self) -> SystemRDLVersion:
+		# TODO: check for None and return exception
+		return self._srdlVersion
+
+	@SRDLVersion.setter
+	def SRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+

+[docs]
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this project.
+
+		:returns: The number if attributes set on this project.
+		"""
+		return len(self._attributes)

+
+
+

+[docs]
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this project.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)

+
+
+

+[docs]
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this project.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value

+
+
+

+[docs]
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this project.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]

+
+
+

+[docs]
+	def __str__(self) -> str:
+		return self._name

+

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyEDAA/ProjectModel/Attributes.html b/_modules/pyEDAA/ProjectModel/Attributes.html new file mode 100644 index 00000000..29c4d85b --- /dev/null +++ b/_modules/pyEDAA/ProjectModel/Attributes.html @@ -0,0 +1,187 @@ + + + + + + pyEDAA.ProjectModel.Attributes — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +

Source code for pyEDAA.ProjectModel.Attributes

+# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""A set of common attributes to store meta information on ProjectModel entities (project, design, fileset, file, ...)."""
+from typing               import Dict
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel  import Attribute
+
+
+

+[docs]
+@export
+class KeyValueAttribute(Attribute):
+	KEY = "ID"
+
+	_keyValuePairs: Dict[str, str]
+
+

+[docs]
+	def __init__(self):
+		super().__init__()
+
+		self._keyValuePairs = {}

+
+
+	def __getitem__(self, item: str) -> str:
+		return self._keyValuePairs[item]
+
+	def __setitem__(self, key: str, value: str) -> None:
+		self._keyValuePairs[key] = value

+
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_modules/pyEDAA/ProjectModel/Xilinx/Vivado.html b/_modules/pyEDAA/ProjectModel/Xilinx/Vivado.html new file mode 100644 index 00000000..5704d1f4 --- /dev/null +++ b/_modules/pyEDAA/ProjectModel/Xilinx/Vivado.html @@ -0,0 +1,336 @@ + + + + + + pyEDAA.ProjectModel.Xilinx.Vivado — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +

Source code for pyEDAA.ProjectModel.Xilinx.Vivado

+# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Xilinx Vivado."""
+from pathlib import Path
+from typing import Iterable
+
+from xml.dom import minidom, Node
+
+from pyTooling.MetaClasses import ExtendedType
+from pyVHDLModel import VHDLVersion
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design
+from pyEDAA.ProjectModel import File as Model_File
+from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
+from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
+from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
+
+
+

+[docs]
+@export
+class UsedInAttribute(Attribute):
+	KEY = "UsedIn"
+	VALUE_TYPE = Iterable[str]

+
+
+
+@export
+class File(Model_File):
+	pass
+
+
+class VivadoFileMixIn(metaclass=ExtendedType, mixin=True):
+	def _registerAttributes(self):
+		self._attributes[UsedInAttribute] = []
+
+
+@export
+class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn):
+	def _registerAttributes(self):
+		super()._registerAttributes()
+		VivadoFileMixIn._registerAttributes(self)
+
+
+@export
+class VerilogSourceFile(Model_VerilogSourceFile):
+	def _registerAttributes(self):
+		super()._registerAttributes()
+		VivadoFileMixIn._registerAttributes(self)
+
+
+@export
+class VHDLSourceFile(Model_VHDLSourceFile):
+	def _registerAttributes(self):
+		super()._registerAttributes()
+		VivadoFileMixIn._registerAttributes(self)
+
+
+@export
+class VivadoProjectFile(ProjectFile, XMLContent):
+	"""A Vivado project file (``*.xpr``)."""
+
+	_xprProject: Project
+
+	def __init__(
+		self,
+		path: Path,
+		project: Project = None,
+		design: Design = None,
+		fileSet: FileSet = None
+	):
+		super().__init__(path, project, design, fileSet)
+
+		self._xprProject = None
+
+	@property
+	def ProjectModel(self) -> Project:
+		return self._xprProject
+
+	def Parse(self):
+		if not self._path.exists():
+			raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.")
+
+		try:
+			root = minidom.parse(str(self._path)).documentElement
+		except Exception as ex:
+			raise Exception(f"Couldn't open '{self._path!s}'.") from ex
+
+		self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent)
+		self._ParseRootElement(root)
+
+	def _ParseRootElement(self, root):
+		for rootNode in root.childNodes:
+			if rootNode.nodeName == "FileSets":
+				self._ParseFileSets(rootNode)
+				break
+
+	def _ParseFileSets(self, filesetsNode):
+		for fileSetsNode in filesetsNode.childNodes:
+			if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet":
+				self._ParseFileSet(fileSetsNode)
+
+	def _ParseFileSet(self, filesetNode):
+		filesetName = filesetNode.getAttribute("Name")
+		fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign)
+
+		for fileNode in filesetNode.childNodes:
+			if fileNode.nodeType == Node.ELEMENT_NODE:
+				if fileNode.tagName == "File":
+					self._ParseFile(fileNode, fileset)
+				elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config":
+					self._ParseFileSetConfig(fileNode, fileset)
+
+	def _ParseFile(self, fileNode, fileset):
+		croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "")
+		filePath = Path(croppedPath)
+		if filePath.suffix in (".vhd", ".vhdl"):
+			self._ParseVHDLFile(fileNode, filePath, fileset)
+		elif filePath.suffix == ".xdc":
+			self._ParseXDCFile(fileNode, filePath, fileset)
+		elif filePath.suffix == ".v":
+			self._ParseVerilogFile(fileNode, filePath, fileset)
+		elif filePath.suffix == ".xci":
+			self._ParseXCIFile(fileNode, filePath, fileset)
+		else:
+			self._ParseDefaultFile(fileNode, filePath, fileset)
+
+	def _ParseVHDLFile(self, fileNode, path, fileset):
+		vhdlFile = VHDLSourceFile(path)
+		fileset.AddFile(vhdlFile)
+		usedInAttr = vhdlFile[UsedInAttribute]
+
+		for childNode in fileNode.childNodes:
+			if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo":
+				if childNode.getAttribute("SFType") == "VHDL2008":
+					vhdlFile.VHDLVersion = VHDLVersion.VHDL2008
+				else:
+					vhdlFile.VHDLVersion = VHDLVersion.VHDL93
+
+				for fileAttribute in childNode.childNodes:
+					if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr":
+						if fileAttribute.getAttribute("Name") == "Library":
+							libraryName = fileAttribute.getAttribute("Val")
+							vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName)
+						elif fileAttribute.getAttribute("Val") == "UsedIn":
+							usedInAttr.append(fileAttribute.getAttribute("Val"))
+
+	def _ParseDefaultFile(self, _, path, fileset):
+		File(path, fileSet=fileset)
+
+	def _ParseXDCFile(self, _, path, fileset):
+		XDCConstraintFile(path, fileSet=fileset)
+
+	def _ParseVerilogFile(self, _, path, fileset):
+		VerilogSourceFile(path, fileSet=fileset)
+
+	def _ParseXCIFile(self, _, path, fileset):
+		IPCoreInstantiationFile(path, fileSet=fileset)
+
+	def _ParseFileSetConfig(self, fileNode, fileset):
+		for option in fileNode.childNodes:
+			if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
+				if option.getAttribute("Name") == "TopModule":
+					fileset.TopLevel = option.getAttribute("Val")
+
+
+@export
+class XDCConstraintFile(ConstraintFile, SDCContent):
+	"""A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``)."""
+
+
+@export
+class IPCoreDescriptionFile(XMLFile):
+	pass
+
+
+@export
+class IPCoreInstantiationFile(XMLFile):
+	"""A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``)."""
+
+ +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/_sources/ChangeLog/index.rst.txt b/_sources/ChangeLog/index.rst.txt new file mode 100644 index 00000000..168996de --- /dev/null +++ b/_sources/ChangeLog/index.rst.txt @@ -0,0 +1,12 @@ +ChangeLog +######### + +Upcoming Release +================ + +* tbd + +01.09.2021 +========== + +`pyEDAA.ProjectModel` was split from `pyIPCMI` (v1.1.6) as an independent Python package. diff --git a/_sources/Dependency.rst.txt b/_sources/Dependency.rst.txt new file mode 100644 index 00000000..b50b55f9 --- /dev/null +++ b/_sources/Dependency.rst.txt @@ -0,0 +1,172 @@ +.. _dependency: + +Dependency +########## + +.. |img-ProjectModel-lib-status| image:: https://img.shields.io/librariesio/release/pypi/pyEDAA.ProjectModel + :alt: Libraries.io status for latest release + :height: 22 + :target: https://libraries.io/github/edaa-org/pyEDAA.ProjectModel +.. |img-ProjectModel-req-status| image:: https://img.shields.io/requires/github/edaa-org/pyEDAA.ProjectModel + :alt: Requires.io + :height: 22 + :target: https://requires.io/github/edaa-org/pyEDAA.ProjectModel/requirements/?branch=main + ++------------------------------------------+------------------------------------------+ +| `Libraries.io `_ | `Requires.io `_ | ++==========================================+==========================================+ +| |img-ProjectModel-lib-status| | |img-ProjectModel-req-status| | ++------------------------------------------+------------------------------------------+ + + +.. _dependency-package: + +pyEDAA.ProjectModel Package +*************************** + ++------------------------------------------------------------------------+-------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++========================================================================+=============+===========================================================================================+========================================================================================================================================================+ +| `pyTooling `__ | ≥5.0.0 | `Apache License, 2.0 `__ | *None* | ++------------------------------------------------------------------------+-------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `pyVHDLModel `__ | ≥0.27.1 | `Apache License, 2.0 `__ | * `pyTooling `__ (`Apache License, 2.0 `__) | ++------------------------------------------------------------------------+-------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `pySVModel `__ | ≥0.3.1 | `Apache License, 2.0 `__ | * `pyTooling `__ (`Apache License, 2.0 `__) | ++------------------------------------------------------------------------+-------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `pySystemRDLModel `__ | ≥0.1.0 | `Apache License, 2.0 `__ | * `pyTooling `__ (`Apache License, 2.0 `__) | ++------------------------------------------------------------------------+-------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +.. _dependency-testing: + +Unit Testing / Coverage / Type Checking (Optional) +************************************************** + +Additional Python packages needed for testing, code coverage collection and static type checking. These packages are +only needed for developers or on a CI server, thus sub-dependencies are not evaluated further. + + +.. rubric:: Manually Installing Test Requirements + +Use the :file:`tests/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively install +the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r tests/requirements.txt + + +.. rubric:: Dependency List + ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++=====================================================================+=============+========================================================================================+======================+ +| `pytest `__ | ≥7.4.0 | `MIT `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `pytest-cov `__ | ≥4.1.0 | `MIT `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `Coverage `__ | ≥7.3 | `Apache License, 2.0 `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `mypy `__ | ≥1.5 | `MIT `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `typing-extensions `__ | ≥4.7.1 | `PSF-2.0 `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ +| `lxml `__ | ≥4.9 | `BSD 3-Clause `__ | *Not yet evaluated.* | ++---------------------------------------------------------------------+-------------+----------------------------------------------------------------------------------------+----------------------+ + + +.. _dependency-documentation: + +Sphinx Documentation (Optional) +******************************* + +Additional Python packages needed for documentation generation. These packages are only needed for developers or on a +CI server, thus sub-dependencies are not evaluated further. + + +.. rubric:: Manually Installing Documentation Requirements + +Use the :file:`doc/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively install +the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r doc/requirements.txt + + +.. rubric:: Dependency List + ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++=================================================================================================+==============+==========================================================================================================+======================================================================================================================================================+ +| `pyTooling `__ | ≥5.0.0 | `Apache License, 2.0 `__ | *None* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `Sphinx `__ | ≥5.3.0 | `BSD 3-Clause `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `sphinx_btd_theme `__ | ≥0.5.2 | `MIT `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| !! `sphinx_fontawesome `__ | ≥0.0.6 | `GPL 2.0 `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `sphinx_autodoc_typehints `__ | ≥1.19.5 | `MIT `__ | *Not yet evaluated.* | ++-------------------------------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +.. _dependency-packaging: + +Packaging (Optional) +******************** + +Additional Python packages needed for installation package generation. These packages are only needed for developers or +on a CI server, thus sub-dependencies are not evaluated further. + + +.. rubric:: Manually Installing Packaging Requirements + +Use the :file:`build/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively +install the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r build/requirements.txt + + +.. rubric:: Dependency List + ++----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++============================================================================+==============+==========================================================================================================+======================================================================================================================================================+ +| `pyTooling `__ | ≥5.0.0 | `Apache License, 2.0 `__ | *None* | ++----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +| `wheel `__ | ≥0.40.0 | `MIT `__ | *Not yet evaluated.* | ++----------------------------------------------------------------------------+--------------+----------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ + + +.. _dependency-publishing: + +Publishing (CI-Server only) +*************************** + +Additional Python packages needed for publishing the generated installation package to e.g, PyPI or any equivalent +services. These packages are only needed for maintainers or on a CI server, thus sub-dependencies are not evaluated +further. + + +.. rubric:: Manually Installing Publishing Requirements + +Use the :file:`dist/requirements.txt` file to install all dependencies via ``pip3``. The file will recursively +install the mandatory dependencies too. + +.. code-block:: shell + + pip3 install -U -r dist/requirements.txt + + +.. rubric:: Dependency List + ++----------------------------------------------------------+--------------+-------------------------------------------------------------------------------------------+----------------------+ +| **Package** | **Version** | **License** | **Dependencies** | ++==========================================================+==============+===========================================================================================+======================+ +| `wheel `__ | ≥0.40.0 | `MIT `__ | *Not yet evaluated.* | ++----------------------------------------------------------+--------------+-------------------------------------------------------------------------------------------+----------------------+ +| `Twine `__ | ≥4.0.2 | `Apache License, 2.0 `__ | *Not yet evaluated.* | ++----------------------------------------------------------+--------------+-------------------------------------------------------------------------------------------+----------------------+ diff --git a/_sources/Doc-License.rst.txt b/_sources/Doc-License.rst.txt new file mode 100644 index 00000000..1258fbc2 --- /dev/null +++ b/_sources/Doc-License.rst.txt @@ -0,0 +1,353 @@ +.. _DOCLICENSE: + +.. Note:: This is a local copy of the `Creative Commons - Attribution 4.0 International (CC BY 4.0) `__. + +.. Attention:: This **CC BY 4.0** license applies only to the **documentation** of this project. + + +Creative Commons Attribution 4.0 International +############################################## + +Creative Commons Corporation (“Creative Commons”) is not a law firm and does not +provide legal services or legal advice. Distribution of Creative Commons public +licenses does not create a lawyer-client or other relationship. Creative Commons +makes its licenses and related information available on an “as-is” basis. +Creative Commons gives no warranties regarding its licenses, any material +licensed under their terms and conditions, or any related information. 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We also recommend that a file or +class name and description of purpose be included on the same "printed page" as the copyright notice for easier identification within third-party archives. + +.. code-block:: none + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/_sources/ProjectModel/Design.rst.txt b/_sources/ProjectModel/Design.rst.txt new file mode 100644 index 00000000..bc6c2b80 --- /dev/null +++ b/_sources/ProjectModel/Design.rst.txt @@ -0,0 +1,108 @@ +.. _projectmodel-design: + +Design +###### + +Generic description of an EDA design. + +.. todo:: + + Write documentation. + + +.. rubric:: Class Relationship + +.. mermaid:: + + graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style Design fill:#ee9b00 + + +Condensed definition of class :class:`~pyEDAA.ProjectModel.Design` +================================================================== + +.. code-block:: Python + + @export + class Design: + _name: str + _project: Nullable['Project'] + _directory: Nullable[Path] + _fileSets: Dict[str, FileSet] + _defaultFileSet: Nullable[FileSet] + _vhdlLibraries: Dict[str, VHDLLibrary] + _vhdlVersion: VHDLVersion + _verilogVersion: VerilogVersion + _svVersion: SystemVerilogVersion + _externalVHDLLibraries: List + + def __init__( + self, + name: str, + directory: Path = Path("."), + project: 'Project' = None, + vhdlVersion: VHDLVersion = None, + verilogVersion: VerilogVersion = None, + svVersion: SystemVerilogVersion = None + ): + + @property + def Name(self) -> str: + + @property + def Project(self) -> Nullable['Project']: + @Project.setter + def Project(self, value: 'Project') -> None: + + @property + def Directory(self) -> Path: + @Directory.setter + def Directory(self, value: Path) -> None: + + @property + def ResolvedPath(self) -> Path: + + @property + def DefaultFileSet(self) -> FileSet: + @DefaultFileSet.setter + def DefaultFileSet(self, value: Union[str, FileSet]) -> None: + + @property + def FileSets(self) -> Dict[str, FileSet]: + + def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]: + + @property + def VHDLLibraries(self) -> List[VHDLLibrary]: + + @property + def VHDLVersion(self) -> VHDLVersion: + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + + @property + def VerilogVersion(self) -> VerilogVersion: + @VerilogVersion.setter + def VerilogVersion(self, value: VerilogVersion) -> None: + + @property + def SVVersion(self) -> SystemVerilogVersion: + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: + + @property + def ExternalVHDLLibraries(self) -> List: + + def AddFileSet(self, fileSet: FileSet) -> None: + + def AddFileSets(self, fileSets: Iterable[FileSet]) -> None: + + def AddFile(self, file: File) -> None: + + def AddFiles(self, files: Iterable[File]) -> None: diff --git a/_sources/ProjectModel/File.rst.txt b/_sources/ProjectModel/File.rst.txt new file mode 100644 index 00000000..063cf66d --- /dev/null +++ b/_sources/ProjectModel/File.rst.txt @@ -0,0 +1,69 @@ +.. _projectmodel-file: + +File +#### + +Generic description of a file in EDA design. + +.. todo:: + + Write documentation. + + +.. rubric:: Class Relationship + +.. mermaid:: + + graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style File fill:#ee9b00 + + +Condensed definition of class :class:`~pyEDAA.ProjectModel.File` +================================================================ + +.. code-block:: Python + + @export + class File(metaclass=FileType): + _path: Path + _project: Nullable['Project'] + _design: Nullable['Design'] + _fileSet: Nullable['FileSet'] + + def __init__( + self, + path: Path, + project: 'Project' = None, + design: 'Design' = None, + fileSet: 'FileSet' = None + ): + + @property + def FileType(self) -> 'FileType': + + @property + def Path(self) -> Path: + + @property + def ResolvedPath(self) -> Path: + + @property + def Project(self) -> Nullable['Project']: + @Project.setter + def Project(self, value: 'Project') -> None: + + @property + def Design(self) -> Nullable['Design']: + @Design.setter + def Design(self, value: 'Design') -> None: + + @property + def FileSet(self) -> Nullable['FileSet']: + @FileSet.setter + def FileSet(self, value: 'FileSet') -> None: diff --git a/_sources/ProjectModel/FileSet.rst.txt b/_sources/ProjectModel/FileSet.rst.txt new file mode 100644 index 00000000..b63e06d1 --- /dev/null +++ b/_sources/ProjectModel/FileSet.rst.txt @@ -0,0 +1,113 @@ +.. _projectmodel-fileset: + +FileSet +####### + +Generic description of an EDA file set (group of files). + +.. todo:: + + Write documentation. + + +.. rubric:: Class Relationship + +.. mermaid:: + + graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style FileSet fill:#ee9b00 + + +Condensed definition of class :class:`~pyEDAA.ProjectModel.FileSet` +=================================================================== + +.. code-block:: Python + + @export + class FileSet: + _name: str + _project: Nullable['Project'] + _design: Nullable['Design'] + _directory: Nullable[Path] + _parent: Nullable['FileSet'] + _fileSets: Dict[str, 'FileSet'] + _files: List[File] + + _vhdlLibrary: 'VHDLLibrary' + _vhdlVersion: VHDLVersion + _verilogVersion: VerilogVersion + _svVersion: SystemVerilogVersion + + def __init__( + self, + name: str, + directory: Path = Path("."), + project: 'Project' = None, + design: 'Design' = None, + parent: Nullable['FileSet'] = None, + vhdlLibrary: Union[str, 'VHDLLibrary'] = None, + vhdlVersion: VHDLVersion = None, + verilogVersion: VerilogVersion = None, + svVersion: SystemVerilogVersion = None + ): + + @property + def Name(self) -> str: + + @property + def Project(self) -> Nullable['Project']: + @Project.setter + def Project(self, value: 'Project') -> None: + + @property + def Design(self) -> Nullable['Design']: + @Design.setter + def Design(self, value: 'Design') -> None: + + @property + def Directory(self) -> Path: + @Directory.setter + def Directory(self, value: Path) -> None: + + @property + def ResolvedPath(self) -> Path: + + @property + def Parent(self) -> Nullable['FileSet']: + @Parent.setter + def Parent(self, value: 'FileSet') -> None: + + @property + def FileSets(self) -> Dict[str, 'FileSet']: + + def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, 'FileSet'] = None) -> Generator[File, None, None]: + + def AddFile(self, file: File) -> None: + + def AddFiles(self, files: Iterable[File]) -> None: + + @property + def VHDLLibrary(self) -> 'VHDLLibrary': + @VHDLLibrary.setter + def VHDLLibrary(self, value: 'VHDLLibrary') -> None: + + @property + def VHDLVersion(self) -> VHDLVersion: + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + + @property + def VerilogVersion(self) -> VerilogVersion: + @VerilogVersion.setter + def VerilogVersion(self, value: VerilogVersion) -> None: + + @property + def SVVersion(self) -> SystemVerilogVersion: + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: diff --git a/_sources/ProjectModel/Project.rst.txt b/_sources/ProjectModel/Project.rst.txt new file mode 100644 index 00000000..cc0b2022 --- /dev/null +++ b/_sources/ProjectModel/Project.rst.txt @@ -0,0 +1,77 @@ +.. _projectmodel-project: + +Project +####### + +Generic description of an EDA project. + +.. todo:: + + Write documentation. + + +.. rubric:: Class Relationship + +.. mermaid:: + + graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style Project fill:#ee9b00 + + +Condensed definition of class :class:`~pyEDAA.ProjectModel.Project` +=================================================================== + +.. code-block:: Python + + @export + class Project: + _name: str + _rootDirectory: Nullable[Path] + _designs: Dict[str, Design] + _vhdlVersion: VHDLVersion + _verilogVersion: VerilogVersion + _svVersion: SystemVerilogVersion + + def __init__( + self, + name: str, + rootDirectory: Path = Path("."), + vhdlVersion: VHDLVersion = None, + verilogVersion: VerilogVersion = None, + svVersion: SystemVerilogVersion = None + ): + + @property + def Name(self) -> str: + + @property + def RootDirectory(self) -> Path: + @RootDirectory.setter + def RootDirectory(self, value: Path) -> None: + + @property + def ResolvedPath(self) -> Path: + + @property + def Designs(self) -> Dict[str, Design]: + + @property + def VHDLVersion(self) -> VHDLVersion: + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + + @property + def VerilogVersion(self) -> VerilogVersion: + @VerilogVersion.setter + def VerilogVersion(self, value: VerilogVersion) -> None: + + @property + def SVVersion(self) -> SystemVerilogVersion: + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: diff --git a/_sources/ProjectModel/VHDLLibrary.rst.txt b/_sources/ProjectModel/VHDLLibrary.rst.txt new file mode 100644 index 00000000..fe4e8b02 --- /dev/null +++ b/_sources/ProjectModel/VHDLLibrary.rst.txt @@ -0,0 +1,67 @@ +.. _projectmodel-vhdllib: + +VHDL Library +############ + +Generic description of a VHDL library (group of VHDL files containing VHDL primary units). + +.. todo:: + + Write documentation. + + +.. rubric:: Class Relationship + +.. mermaid:: + + graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style VHDLLibrary fill:#ee9b00 + + +Condensed definition of class :class:`~pyEDAA.ProjectModel.VHDLLibrary` +======================================================================= + +.. code-block:: Python + + @export + class VHDLLibrary: + _name: str + _project: Nullable['Project'] + _design: Nullable['Design'] + _files: List[File] + _vhdlVersion: VHDLVersion + + def __init__( + self, + name: str, + project: 'Project' = None, + design: 'Design' = None, + vhdlVersion: VHDLVersion = None + ): + + @property + def Name(self) -> str: + + @property + def Project(self) -> Nullable['Project']: + @Project.setter + def Project(self, value: 'Project'): + + @property + def Design(self) -> Nullable['Design']: + @Design.setter + def Design(self, value: 'Design'): + + @property + def Files(self) -> Generator[File, None, None]: + + @property + def VHDLVersion(self) -> VHDLVersion: + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: diff --git a/_sources/ProjectModel/index.rst.txt b/_sources/ProjectModel/index.rst.txt new file mode 100644 index 00000000..789b7be8 --- /dev/null +++ b/_sources/ProjectModel/index.rst.txt @@ -0,0 +1,43 @@ +.. _projectmodel: + +Project Model +############# + +.. rubric:: Design Goal + +* Clearly named classes that model the semantics of an EDA project. +* Child objects shall have a reference to their parent. + + +.. rubric:: Overall Hierarchy + +An EDA project contains one or multiple variants of a EDA design. +A design then has at least one but usually multiple file sets to group source files and apply settings or attributes to that group. + +.. mermaid:: + + graph TD; + Project-->Design_A; + Project-->Design_B; + Design_A-->VHDLLibrary_LA; + Design_A-->FileSet_DefaultA; + Design_A-->FileSet_A1; + Design_A-->FileSet_A2; + FileSet_A2-->FileSet_3 + Design_B-->VHDLLibrary_LB; + Design_B-->FileSet_DefaultB; + Design_B-->FileSet_B1; + Design_B-->FileSet_B2; + FileSet_B2-->FileSet_3 + + +.. rubric:: Elements of the Project Model + +.. toctree:: + :maxdepth: 1 + + Project + Design + VHDLLibrary + FileSet + File diff --git a/_sources/coverage/index.rst.txt b/_sources/coverage/index.rst.txt new file mode 100644 index 00000000..80bbad2e --- /dev/null +++ b/_sources/coverage/index.rst.txt @@ -0,0 +1,4 @@ +Coverage Report +############### + +*Placeholder for the Coverage report generated with* ``pytest`` *and* ``coverage``. diff --git a/_sources/genindex.rst.txt b/_sources/genindex.rst.txt new file mode 100644 index 00000000..c07da40d --- /dev/null +++ b/_sources/genindex.rst.txt @@ -0,0 +1,4 @@ +.. This file is a placeholder and will be replaced + +Index +##### diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt new file mode 100644 index 00000000..e346302e --- /dev/null +++ b/_sources/index.rst.txt @@ -0,0 +1,184 @@ +.. include:: shields.inc + +.. image:: _static/logo_on_light.svg + :height: 90 px + :align: center + :target: https://GitHub.com/edaa-org/pyEDAA.ProjectModel + +.. raw:: html + +
+ +.. raw:: latex + + \part{Introduction} + +.. only:: html + + | |SHIELD:svg:ProjectModel-github| |SHIELD:svg:ProjectModel-src-license| |SHIELD:svg:ProjectModel-ghp-doc| |SHIELD:svg:ProjectModel-doc-license| |SHIELD:svg:ProjectModel-gitter| + | |SHIELD:svg:ProjectModel-pypi-tag| |SHIELD:svg:ProjectModel-pypi-status| |SHIELD:svg:ProjectModel-pypi-python| + | |SHIELD:svg:ProjectModel-gha-test| |SHIELD:svg:ProjectModel-lib-status| |SHIELD:svg:ProjectModel-codacy-quality| |SHIELD:svg:ProjectModel-codacy-coverage| |SHIELD:svg:ProjectModel-codecov-coverage| + +.. Disabled shields: |SHIELD:svg:ProjectModel-lib-dep| |SHIELD:svg:ProjectModel-req-status| |SHIELD:svg:ProjectModel-lib-rank| + +.. only:: latex + + |SHIELD:png:ProjectModel-github| |SHIELD:png:ProjectModel-src-license| |SHIELD:png:ProjectModel-ghp-doc| |SHIELD:png:ProjectModel-doc-license| |SHIELD:svg:ProjectModel-gitter| + |SHIELD:png:ProjectModel-pypi-tag| |SHIELD:png:ProjectModel-pypi-status| |SHIELD:png:ProjectModel-pypi-python| + |SHIELD:png:ProjectModel-gha-test| |SHIELD:png:ProjectModel-lib-status| |SHIELD:png:ProjectModel-codacy-quality| |SHIELD:png:ProjectModel-codacy-coverage| |SHIELD:png:ProjectModel-codecov-coverage| + +.. Disabled shields: |SHIELD:png:ProjectModel-lib-dep| |SHIELD:png:ProjectModel-req-status| |SHIELD:png:ProjectModel-lib-rank| + +-------------------------------------------------------------------------------- + +The pyEDAA.ProjectModel Documentation +##################################### + +An abstract model of HDL design projects and EDA tooling. + + +.. _goals: + +Main Goals +********** + +This package provides a unified abstract project model for HDL designs and EDA tools. +Third-party frameworks can derive own classes and implement additional logic to create a concrete project model for +their tools. + +Frameworks consuming this model can build higher level features and services on top of such a model, while supporting +multiple input sources. + + +.. _usecase: + +Use Cases +********* + +* Describing HDL projects for open source simulation and synthesis tools: + `GHDL `__, + `Icarus Verilog `__, + `Verilator `__, + `Yosys `__, + `Verilog to Routing (VTR) `__, + `nextpnr `__, + etc. +* Managing IP cores and projects with `pyIPCMI `__. + + +.. _news: + +News +**** + +.. only:: html + + Oct. 2021 - Reading ``*.xpr`` and ``*.pro`` Files + ================================================= + +.. only:: latex + + .. rubric:: Reading ``*.xpr`` and ``*.pro`` Files + +* Xilinx Vivado's ``*.xpr`` and OSVVM's ``*.pro`` files can now be read. +* Filesets can be nested. +* The dataset can be validated. + + +.. only:: html + + Sep. 2021 - Extracted ProjectModel from pyIPCMI + =============================================== + +.. only:: latex + + .. rubric:: Extracted ProjectModel from pyIPCMI + +* The project model has been extracted from `pyIPCMI `__. +* ProjectModel became first citizen of `EDA² `__ and got integrated into the `pyEDAA` namespace at PyPI. + + +.. _contributors: + +Contributors +************ + +* `Patrick Lehmann `__ (Maintainer) +* `Unai Martinez-Corral `__ (Maintainer) +* `and more... `__ + + +License +******* + +.. only:: html + + This Python package (source code) is licensed under `Apache License 2.0 `__. |br| + The accompanying documentation is licensed under `Creative Commons - Attribution 4.0 (CC-BY 4.0) `__. + +.. only:: latex + + This Python package (source code) is licensed under **Apache License 2.0**. |br| + The accompanying documentation is licensed under **Creative Commons - Attribution 4.0 (CC-BY 4.0)**. + +------------------------------------ + +.. |docdate| date:: %d.%b %Y - %H:%M + +.. only:: html + + This document was generated on |docdate|. + + +.. toctree:: + :hidden: + + Used as a layer of EDA² ➚ + + +.. toctree:: + :caption: Introduction + :hidden: + + Installation + Dependency + + +.. raw:: latex + + \part{Main Documentation} + +.. toctree:: + :caption: Main Documentation + :hidden: + + ProjectModel/index + FileTypes/index + + +.. raw:: latex + + \part{References} + +.. toctree:: + :caption: References + :hidden: + + pyEDAA.ProjectModel/index + + +.. raw:: latex + + \part{Appendix} + +.. toctree:: + :caption: Appendix + :hidden: + + Coverage Report ➚ + Static Type Check Report ➚ + License + Doc-License + Glossary + genindex + py-modindex diff --git a/_sources/py-modindex.rst.txt b/_sources/py-modindex.rst.txt new file mode 100644 index 00000000..23167be6 --- /dev/null +++ b/_sources/py-modindex.rst.txt @@ -0,0 +1,4 @@ +.. This file is a placeholder and will be replaced + +Module Index +############ diff --git a/_sources/pyEDAA.ProjectModel/index.rst.txt b/_sources/pyEDAA.ProjectModel/index.rst.txt new file mode 100644 index 00000000..118a264a --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/index.rst.txt @@ -0,0 +1,8 @@ +Python Class Reference +###################### + +Reference of all packages and modules: + +.. toctree:: + + pyEDAA.ProjectModel diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus.rst.txt new file mode 100644 index 00000000..6daa1fec --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus.rst.txt @@ -0,0 +1,36 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================================== +``pyEDAA.ProjectModel.Altera.Quartus`` +====================================== + +.. py:module:: pyEDAA.ProjectModel.Altera.Quartus + + +.. currentmodule:: pyEDAA.ProjectModel.Altera.Quartus + + +**Classes** + +- :py:class:`QuartusProjectFile`: + A Quartus project file (``*.qpf``). + +- :py:class:`SDCConstraintFile`: + A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``). + + +.. autoclass:: QuartusProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: QuartusProjectFile + :parts: 1 + +.. autoclass:: SDCConstraintFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SDCConstraintFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.rst.txt new file mode 100644 index 00000000..b0014038 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.rst.txt @@ -0,0 +1,20 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +============================== +``pyEDAA.ProjectModel.Altera`` +============================== + +.. py:module:: pyEDAA.ProjectModel.Altera + + + +**Submodules** + + +.. toctree:: + + pyEDAA.ProjectModel.Altera.Quartus + +.. currentmodule:: pyEDAA.ProjectModel.Altera diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes.rst.txt new file mode 100644 index 00000000..82c84cec --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes.rst.txt @@ -0,0 +1,26 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================================== +``pyEDAA.ProjectModel.Attributes`` +================================== + +.. py:module:: pyEDAA.ProjectModel.Attributes + + +.. currentmodule:: pyEDAA.ProjectModel.Attributes + + +**Classes** + +- :py:class:`KeyValueAttribute`: + Undocumented. + + +.. autoclass:: KeyValueAttribute + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: KeyValueAttribute + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL.rst.txt new file mode 100644 index 00000000..2a9c44f6 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL.rst.txt @@ -0,0 +1,26 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +============================ +``pyEDAA.ProjectModel.GHDL`` +============================ + +.. py:module:: pyEDAA.ProjectModel.GHDL + + +.. currentmodule:: pyEDAA.ProjectModel.GHDL + + +**Classes** + +- :py:class:`GHDLWaveformFile`: + GHDL's waveform file (``*.ghw``) supporting VHDL and Verilog simulation results. + + +.. autoclass:: GHDLWaveformFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: GHDLWaveformFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime.rst.txt new file mode 100644 index 00000000..dda32146 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime.rst.txt @@ -0,0 +1,36 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +========================================== +``pyEDAA.ProjectModel.Intel.QuartusPrime`` +========================================== + +.. py:module:: pyEDAA.ProjectModel.Intel.QuartusPrime + + +.. currentmodule:: pyEDAA.ProjectModel.Intel.QuartusPrime + + +**Classes** + +- :py:class:`QuartusProjectFile`: + A Quartus project file (``*.qpf``). + +- :py:class:`SDCConstraintFile`: + A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``). + + +.. autoclass:: QuartusProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: QuartusProjectFile + :parts: 1 + +.. autoclass:: SDCConstraintFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SDCConstraintFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.rst.txt new file mode 100644 index 00000000..7ee5c6ce --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.rst.txt @@ -0,0 +1,20 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +============================= +``pyEDAA.ProjectModel.Intel`` +============================= + +.. py:module:: pyEDAA.ProjectModel.Intel + + + +**Submodules** + + +.. toctree:: + + pyEDAA.ProjectModel.Intel.QuartusPrime + +.. currentmodule:: pyEDAA.ProjectModel.Intel diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.ModelSim.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.ModelSim.rst.txt new file mode 100644 index 00000000..7f78d569 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.ModelSim.rst.txt @@ -0,0 +1,46 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +=============================================== +``pyEDAA.ProjectModel.MentorGraphics.ModelSim`` +=============================================== + +.. py:module:: pyEDAA.ProjectModel.MentorGraphics.ModelSim + + +.. currentmodule:: pyEDAA.ProjectModel.MentorGraphics.ModelSim + + +**Classes** + +- :py:class:`ModelSimProjectFile`: + Base-class of all tool-specific project files. + +- :py:class:`ModelSimINIFile`: + Base-class of all tool-specific setting files. + +- :py:class:`WaveDoFile`: + Base-class of all tool-specific waveform configuration files. + + +.. autoclass:: ModelSimProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ModelSimProjectFile + :parts: 1 + +.. autoclass:: ModelSimINIFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ModelSimINIFile + :parts: 1 + +.. autoclass:: WaveDoFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: WaveDoFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.QuestaSim.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.QuestaSim.rst.txt new file mode 100644 index 00000000..a2037c55 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.QuestaSim.rst.txt @@ -0,0 +1,46 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================================================ +``pyEDAA.ProjectModel.MentorGraphics.QuestaSim`` +================================================ + +.. py:module:: pyEDAA.ProjectModel.MentorGraphics.QuestaSim + + +.. currentmodule:: pyEDAA.ProjectModel.MentorGraphics.QuestaSim + + +**Classes** + +- :py:class:`ModelSimProjectFile`: + Base-class of all tool-specific project files. + +- :py:class:`ModelSimINIFile`: + Base-class of all tool-specific setting files. + +- :py:class:`WaveDoFile`: + Base-class of all tool-specific waveform configuration files. + + +.. autoclass:: ModelSimProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ModelSimProjectFile + :parts: 1 + +.. autoclass:: ModelSimINIFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ModelSimINIFile + :parts: 1 + +.. autoclass:: WaveDoFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: WaveDoFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.rst.txt new file mode 100644 index 00000000..2ea420ee --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.rst.txt @@ -0,0 +1,21 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +====================================== +``pyEDAA.ProjectModel.MentorGraphics`` +====================================== + +.. py:module:: pyEDAA.ProjectModel.MentorGraphics + + + +**Submodules** + + +.. toctree:: + + pyEDAA.ProjectModel.MentorGraphics.ModelSim + pyEDAA.ProjectModel.MentorGraphics.QuestaSim + +.. currentmodule:: pyEDAA.ProjectModel.MentorGraphics diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.OSVVM.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.OSVVM.rst.txt new file mode 100644 index 00000000..59c9f259 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.OSVVM.rst.txt @@ -0,0 +1,26 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +============================= +``pyEDAA.ProjectModel.OSVVM`` +============================= + +.. py:module:: pyEDAA.ProjectModel.OSVVM + + +.. currentmodule:: pyEDAA.ProjectModel.OSVVM + + +**Classes** + +- :py:class:`OSVVMProjectFile`: + An OSVVM project file (``*.pro``). + + +.. autoclass:: OSVVMProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: OSVVMProjectFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.VHDL.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.VHDL.rst.txt new file mode 100644 index 00000000..127c1981 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.VHDL.rst.txt @@ -0,0 +1,12 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +============================ +``pyEDAA.ProjectModel.VHDL`` +============================ + +.. py:module:: pyEDAA.ProjectModel.VHDL + + +.. currentmodule:: pyEDAA.ProjectModel.VHDL diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Verilog.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Verilog.rst.txt new file mode 100644 index 00000000..0c626261 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Verilog.rst.txt @@ -0,0 +1,26 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +=============================== +``pyEDAA.ProjectModel.Verilog`` +=============================== + +.. py:module:: pyEDAA.ProjectModel.Verilog + + +.. currentmodule:: pyEDAA.ProjectModel.Verilog + + +**Classes** + +- :py:class:`ValueChangeDumpFile`: + Verilog's waveform file (``*.vcd``) for exchanging value changes as defined by IEEE Std. 1364. + + +.. autoclass:: ValueChangeDumpFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ValueChangeDumpFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.ISE.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.ISE.rst.txt new file mode 100644 index 00000000..b9518792 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.ISE.rst.txt @@ -0,0 +1,36 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +================================== +``pyEDAA.ProjectModel.Xilinx.ISE`` +================================== + +.. py:module:: pyEDAA.ProjectModel.Xilinx.ISE + + +.. currentmodule:: pyEDAA.ProjectModel.Xilinx.ISE + + +**Classes** + +- :py:class:`ISEProjectFile`: + Base-class of all tool-specific project files. + +- :py:class:`UCFConstraintFile`: + Base-class of all constraint files. + + +.. autoclass:: ISEProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ISEProjectFile + :parts: 1 + +.. autoclass:: UCFConstraintFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: UCFConstraintFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.Vivado.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.Vivado.rst.txt new file mode 100644 index 00000000..2cd98c6b --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.Vivado.rst.txt @@ -0,0 +1,106 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +===================================== +``pyEDAA.ProjectModel.Xilinx.Vivado`` +===================================== + +.. py:module:: pyEDAA.ProjectModel.Xilinx.Vivado + + +.. currentmodule:: pyEDAA.ProjectModel.Xilinx.Vivado + + +**Classes** + +- :py:class:`UsedInAttribute`: + Undocumented. + +- :py:class:`File`: + A :term:`File` represents a file in a design. This :term:`base-class` is used + +- :py:class:`ConstraintFile`: + Base-class of all constraint files. + +- :py:class:`VerilogSourceFile`: + A Verilog source file (of any language version). + +- :py:class:`VHDLSourceFile`: + A VHDL source file (of any language version). + +- :py:class:`VivadoProjectFile`: + A Vivado project file (``*.xpr``). + +- :py:class:`XDCConstraintFile`: + A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``). + +- :py:class:`IPCoreDescriptionFile`: + An XML file (``*.xml``). + +- :py:class:`IPCoreInstantiationFile`: + A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``). + + +.. autoclass:: UsedInAttribute + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: UsedInAttribute + :parts: 1 + +.. autoclass:: File + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: File + :parts: 1 + +.. autoclass:: ConstraintFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ConstraintFile + :parts: 1 + +.. autoclass:: VerilogSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VerilogSourceFile + :parts: 1 + +.. autoclass:: VHDLSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VHDLSourceFile + :parts: 1 + +.. autoclass:: VivadoProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VivadoProjectFile + :parts: 1 + +.. autoclass:: XDCConstraintFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: XDCConstraintFile + :parts: 1 + +.. autoclass:: IPCoreDescriptionFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: IPCoreDescriptionFile + :parts: 1 + +.. autoclass:: IPCoreInstantiationFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: IPCoreInstantiationFile + :parts: 1 diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.rst.txt new file mode 100644 index 00000000..e73f2a01 --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.rst.txt @@ -0,0 +1,21 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +============================== +``pyEDAA.ProjectModel.Xilinx`` +============================== + +.. py:module:: pyEDAA.ProjectModel.Xilinx + + + +**Submodules** + + +.. toctree:: + + pyEDAA.ProjectModel.Xilinx.ISE + pyEDAA.ProjectModel.Xilinx.Vivado + +.. currentmodule:: pyEDAA.ProjectModel.Xilinx diff --git a/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.rst.txt b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.rst.txt new file mode 100644 index 00000000..a425e57a --- /dev/null +++ b/_sources/pyEDAA.ProjectModel/pyEDAA.ProjectModel.rst.txt @@ -0,0 +1,502 @@ +.. # Template modified by Patrick Lehmann + * removed automodule on top, because private members are activated for autodoc (no doubled documentation). + * Made sections like 'submodules' bold text, but no headlines to reduce number of ToC levels. + +======================= +``pyEDAA.ProjectModel`` +======================= + +.. py:module:: pyEDAA.ProjectModel + + + +**Submodules** + + +.. toctree:: + + pyEDAA.ProjectModel.Altera + pyEDAA.ProjectModel.Attributes + pyEDAA.ProjectModel.GHDL + pyEDAA.ProjectModel.Intel + pyEDAA.ProjectModel.MentorGraphics + pyEDAA.ProjectModel.OSVVM + pyEDAA.ProjectModel.VHDL + pyEDAA.ProjectModel.Verilog + pyEDAA.ProjectModel.Xilinx + +.. currentmodule:: pyEDAA.ProjectModel + + +**Classes** + +- :py:class:`Attribute`: + Undocumented. + +- :py:class:`FileType`: + A :term:`meta-class` to construct *FileType* classes. + +- :py:class:`File`: + A :term:`File` represents a file in a design. This :term:`base-class` is used + +- :py:class:`HumanReadableContent`: + A file type representing human-readable contents. + +- :py:class:`XMLContent`: + A file type representing XML contents. + +- :py:class:`YAMLContent`: + A file type representing YAML contents. + +- :py:class:`JSONContent`: + A file type representing JSON contents. + +- :py:class:`INIContent`: + A file type representing INI contents. + +- :py:class:`TOMLContent`: + A file type representing TOML contents. + +- :py:class:`TCLContent`: + A file type representing content in TCL code. + +- :py:class:`SDCContent`: + A file type representing contents as Synopsys Design Constraints (SDC). + +- :py:class:`PythonContent`: + A file type representing contents as Python source code. + +- :py:class:`TextFile`: + A text file (``*.txt``). + +- :py:class:`LogFile`: + A log file (``*.log``). + +- :py:class:`XMLFile`: + An XML file (``*.xml``). + +- :py:class:`SourceFile`: + Base-class of all source files. + +- :py:class:`HDLSourceFile`: + Base-class of all HDL source files. + +- :py:class:`RDLSourceFile`: + Base-class of all RDL source files. + +- :py:class:`NetlistFile`: + Base-class of all netlist source files. + +- :py:class:`EDIFNetlistFile`: + Netlist file in EDIF (Electronic Design Interchange Format). + +- :py:class:`TCLSourceFile`: + A TCL source file. + +- :py:class:`VHDLSourceFile`: + A VHDL source file (of any language version). + +- :py:class:`VerilogBaseFile`: + Base-class of all HDL source files. + +- :py:class:`VerilogSourceFile`: + A Verilog source file (of any language version). + +- :py:class:`VerilogHeaderFile`: + A Verilog header file (of any language version). + +- :py:class:`SystemVerilogBaseFile`: + Base-class of all HDL source files. + +- :py:class:`SystemVerilogSourceFile`: + A SystemVerilog source file (of any language version). + +- :py:class:`SystemVerilogHeaderFile`: + A SystemVerilog header file (of any language version). + +- :py:class:`SystemRDLSourceFile`: + A SystemRDL source file (of any language version). + +- :py:class:`PythonSourceFile`: + A Python source file. + +- :py:class:`CocotbPythonFile`: + A Python source file used by Cocotb. + +- :py:class:`ConstraintFile`: + Base-class of all constraint files. + +- :py:class:`ProjectFile`: + Base-class of all tool-specific project files. + +- :py:class:`CSourceFile`: + Base-class of all ANSI-C source files. + +- :py:class:`CppSourceFile`: + Base-class of all ANSI-C++ source files. + +- :py:class:`SettingFile`: + Base-class of all tool-specific setting files. + +- :py:class:`SimulationAnalysisFile`: + Base-class of all tool-specific analysis files. + +- :py:class:`SimulationElaborationFile`: + Base-class of all tool-specific elaboration files. + +- :py:class:`SimulationStartFile`: + Base-class of all tool-specific simulation start-up files. + +- :py:class:`SimulationRunFile`: + Base-class of all tool-specific simulation run (execution) files. + +- :py:class:`WaveformConfigFile`: + Base-class of all tool-specific waveform configuration files. + +- :py:class:`WaveformDatabaseFile`: + Base-class of all tool-specific waveform database files. + +- :py:class:`WaveformExchangeFile`: + Base-class of all tool-independent waveform exchange files. + +- :py:class:`FileSet`: + A :term:`FileSet` represents a group of files. Filesets can have sub-filesets. + +- :py:class:`VHDLLibrary`: + A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library. + +- :py:class:`Design`: + A :term:`Design` represents a group of filesets and the source files therein. + +- :py:class:`Project`: + A :term:`Project` represents a group of designs and the source files therein. + + +.. autoclass:: Attribute + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: Attribute + :parts: 1 + +.. autoclass:: FileType + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: FileType + :parts: 1 + +.. autoclass:: File + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: File + :parts: 1 + +.. autoclass:: HumanReadableContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: HumanReadableContent + :parts: 1 + +.. autoclass:: XMLContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: XMLContent + :parts: 1 + +.. autoclass:: YAMLContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: YAMLContent + :parts: 1 + +.. autoclass:: JSONContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: JSONContent + :parts: 1 + +.. autoclass:: INIContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: INIContent + :parts: 1 + +.. autoclass:: TOMLContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: TOMLContent + :parts: 1 + +.. autoclass:: TCLContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: TCLContent + :parts: 1 + +.. autoclass:: SDCContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SDCContent + :parts: 1 + +.. autoclass:: PythonContent + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: PythonContent + :parts: 1 + +.. autoclass:: TextFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: TextFile + :parts: 1 + +.. autoclass:: LogFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: LogFile + :parts: 1 + +.. autoclass:: XMLFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: XMLFile + :parts: 1 + +.. autoclass:: SourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SourceFile + :parts: 1 + +.. autoclass:: HDLSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: HDLSourceFile + :parts: 1 + +.. autoclass:: RDLSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: RDLSourceFile + :parts: 1 + +.. autoclass:: NetlistFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: NetlistFile + :parts: 1 + +.. autoclass:: EDIFNetlistFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: EDIFNetlistFile + :parts: 1 + +.. autoclass:: TCLSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: TCLSourceFile + :parts: 1 + +.. autoclass:: VHDLSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VHDLSourceFile + :parts: 1 + +.. autoclass:: VerilogBaseFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VerilogBaseFile + :parts: 1 + +.. autoclass:: VerilogSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VerilogSourceFile + :parts: 1 + +.. autoclass:: VerilogHeaderFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VerilogHeaderFile + :parts: 1 + +.. autoclass:: SystemVerilogBaseFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SystemVerilogBaseFile + :parts: 1 + +.. autoclass:: SystemVerilogSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SystemVerilogSourceFile + :parts: 1 + +.. autoclass:: SystemVerilogHeaderFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SystemVerilogHeaderFile + :parts: 1 + +.. autoclass:: SystemRDLSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SystemRDLSourceFile + :parts: 1 + +.. autoclass:: PythonSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: PythonSourceFile + :parts: 1 + +.. autoclass:: CocotbPythonFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: CocotbPythonFile + :parts: 1 + +.. autoclass:: ConstraintFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ConstraintFile + :parts: 1 + +.. autoclass:: ProjectFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: ProjectFile + :parts: 1 + +.. autoclass:: CSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: CSourceFile + :parts: 1 + +.. autoclass:: CppSourceFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: CppSourceFile + :parts: 1 + +.. autoclass:: SettingFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SettingFile + :parts: 1 + +.. autoclass:: SimulationAnalysisFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SimulationAnalysisFile + :parts: 1 + +.. autoclass:: SimulationElaborationFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SimulationElaborationFile + :parts: 1 + +.. autoclass:: SimulationStartFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SimulationStartFile + :parts: 1 + +.. autoclass:: SimulationRunFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: SimulationRunFile + :parts: 1 + +.. autoclass:: WaveformConfigFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: WaveformConfigFile + :parts: 1 + +.. autoclass:: WaveformDatabaseFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: WaveformDatabaseFile + :parts: 1 + +.. autoclass:: WaveformExchangeFile + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: WaveformExchangeFile + :parts: 1 + +.. autoclass:: FileSet + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: FileSet + :parts: 1 + +.. autoclass:: VHDLLibrary + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: VHDLLibrary + :parts: 1 + +.. autoclass:: Design + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: Design + :parts: 1 + +.. autoclass:: Project + :members: + + .. rubric:: Inheritance + .. inheritance-diagram:: Project + :parts: 1 diff --git a/_sources/typing/index.rst.txt b/_sources/typing/index.rst.txt new file mode 100644 index 00000000..97d4ae2a --- /dev/null +++ b/_sources/typing/index.rst.txt @@ -0,0 +1,4 @@ +Static Type Checking Report +########################### + +*Placeholder for the Static Type Checking report generated with* ``mypy``. diff --git a/_static/basic.css b/_static/basic.css new file mode 100644 index 00000000..30fee9d0 --- /dev/null +++ b/_static/basic.css @@ -0,0 +1,925 @@ +/* + * basic.css + * ~~~~~~~~~ + * + * Sphinx stylesheet -- basic theme. + * + * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + 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p.context { + color: #888; + margin: 2px 0 0 30px; + text-align: left; +} + +ul.keywordmatches li.goodmatch a { + font-weight: bold; +} + +/* -- index page ------------------------------------------------------------ */ + +table.contentstable { + width: 90%; + margin-left: auto; + margin-right: auto; +} + +table.contentstable p.biglink { + line-height: 150%; +} + +a.biglink { + font-size: 1.3em; +} + +span.linkdescr { + font-style: italic; + padding-top: 5px; + font-size: 90%; +} + +/* -- general index --------------------------------------------------------- */ + +table.indextable { + width: 100%; +} + +table.indextable td { + text-align: left; + vertical-align: top; +} + +table.indextable ul { + margin-top: 0; + margin-bottom: 0; + list-style-type: none; +} + +table.indextable > tbody > tr > td > ul { + padding-left: 0em; +} + +table.indextable tr.pcap { + height: 10px; +} + +table.indextable tr.cap { + margin-top: 10px; + background-color: #f2f2f2; +} + +img.toggler { + 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+p.admonition-title { + margin: 0px 10px 5px 0px; + font-weight: bold; +} + +div.body p.centered { + text-align: center; + margin-top: 25px; +} + +/* -- content of sidebars/topics/admonitions -------------------------------- */ + +div.sidebar > :last-child, +aside.sidebar > :last-child, +nav.contents > :last-child, +aside.topic > :last-child, +div.topic > :last-child, +div.admonition > :last-child { + margin-bottom: 0; +} + +div.sidebar::after, +aside.sidebar::after, +nav.contents::after, +aside.topic::after, +div.topic::after, +div.admonition::after, +blockquote::after { + display: block; + content: ''; + clear: both; +} + +/* -- tables ---------------------------------------------------------------- */ + +table.docutils { + margin-top: 10px; + margin-bottom: 10px; + border: 0; + border-collapse: collapse; +} + +table.align-center { + margin-left: auto; + margin-right: auto; +} + +table.align-default { + margin-left: auto; + margin-right: auto; +} + +table caption span.caption-number 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// [C]VC[V] is m=1 + var mgr1 = "^(" + C + ")?" + V + C + V + C; // [C]VCVC... is m>1 + var s_v = "^(" + C + ")?" + v; // vowel in stem + + this.stemWord = function (w) { + var stem; + var suffix; + var firstch; + var origword = w; + + if (w.length < 3) + return w; + + var re; + var re2; + var re3; + var re4; + + firstch = w.substr(0,1); + if (firstch == "y") + w = firstch.toUpperCase() + w.substr(1); + + // Step 1a + re = /^(.+?)(ss|i)es$/; + re2 = /^(.+?)([^s])s$/; + + if (re.test(w)) + w = w.replace(re,"$1$2"); + else if (re2.test(w)) + w = w.replace(re2,"$1$2"); + + // Step 1b + re = /^(.+?)eed$/; + re2 = /^(.+?)(ed|ing)$/; + if (re.test(w)) { + var fp = re.exec(w); + re = new RegExp(mgr0); + if (re.test(fp[1])) { + re = /.$/; + w = w.replace(re,""); + } + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1]; + re2 = new RegExp(s_v); + if (re2.test(stem)) { + w = stem; + re2 = /(at|bl|iz)$/; + re3 = new RegExp("([^aeiouylsz])\\1$"); + re4 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re2.test(w)) + w = w + "e"; + else if (re3.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + else if (re4.test(w)) + w = w + "e"; + } + } + + // Step 1c + re = /^(.+?)y$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(s_v); + if (re.test(stem)) + w = stem + "i"; + } + + // Step 2 + re = /^(.+?)(ational|tional|enci|anci|izer|bli|alli|entli|eli|ousli|ization|ation|ator|alism|iveness|fulness|ousness|aliti|iviti|biliti|logi)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step2list[suffix]; + } + + // Step 3 + re = /^(.+?)(icate|ative|alize|iciti|ical|ful|ness)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step3list[suffix]; + } + + // Step 4 + re = /^(.+?)(al|ance|ence|er|ic|able|ible|ant|ement|ment|ent|ou|ism|ate|iti|ous|ive|ize)$/; + re2 = /^(.+?)(s|t)(ion)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + if (re.test(stem)) + w = stem; + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1] + fp[2]; + re2 = new RegExp(mgr1); + if (re2.test(stem)) + w = stem; + } + + // Step 5 + re = /^(.+?)e$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + re2 = new RegExp(meq1); + re3 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re.test(stem) || (re2.test(stem) && !(re3.test(stem)))) + w = stem; + } + re = /ll$/; + re2 = new RegExp(mgr1); + if (re.test(w) && re2.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + + // and turn initial Y back to y + if (firstch == "y") + w = firstch.toLowerCase() + w.substr(1); + return w; + } +} + diff --git a/_static/logo_on_dark.svg b/_static/logo_on_dark.svg new file mode 100644 index 00000000..24e8576a --- /dev/null +++ b/_static/logo_on_dark.svg @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/_static/logo_on_light.svg b/_static/logo_on_light.svg new file mode 100644 index 00000000..eac24d90 --- /dev/null +++ b/_static/logo_on_light.svg @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/_static/minus.png b/_static/minus.png new file mode 100644 index 00000000..d96755fd Binary files /dev/null and b/_static/minus.png differ diff --git a/_static/plus.png b/_static/plus.png new file mode 100644 index 00000000..7107cec9 Binary files /dev/null and b/_static/plus.png differ diff --git a/_static/pygments.css b/_static/pygments.css new file mode 100644 index 00000000..6bae782c --- /dev/null +++ b/_static/pygments.css @@ -0,0 +1,85 @@ +pre { line-height: 125%; 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+} + +const _removeChildren = (element) => { + while (element && element.lastChild) element.removeChild(element.lastChild); +}; + +/** + * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Guide/Regular_Expressions#escaping + */ +const _escapeRegExp = (string) => + string.replace(/[.*+\-?^${}()|[\]\\]/g, "\\$&"); // $& means the whole matched string + +const _displayItem = (item, searchTerms, highlightTerms) => { + const docBuilder = DOCUMENTATION_OPTIONS.BUILDER; + const docFileSuffix = DOCUMENTATION_OPTIONS.FILE_SUFFIX; + const docLinkSuffix = DOCUMENTATION_OPTIONS.LINK_SUFFIX; + const showSearchSummary = DOCUMENTATION_OPTIONS.SHOW_SEARCH_SUMMARY; + const contentRoot = document.documentElement.dataset.content_root; + + const [docName, title, anchor, descr, score, _filename] = item; + + let listItem = document.createElement("li"); + let requestUrl; + let linkUrl; + if (docBuilder === "dirhtml") { + // dirhtml builder + let dirname = docName + "/"; + if (dirname.match(/\/index\/$/)) + dirname = dirname.substring(0, dirname.length - 6); + else if (dirname === "index/") dirname = ""; + requestUrl = contentRoot + dirname; + linkUrl = requestUrl; + } else { + // normal html builders + requestUrl = contentRoot + docName + docFileSuffix; + linkUrl = docName + docLinkSuffix; + } + let linkEl = listItem.appendChild(document.createElement("a")); + linkEl.href = linkUrl + anchor; + linkEl.dataset.score = score; + linkEl.innerHTML = title; + if (descr) { + listItem.appendChild(document.createElement("span")).innerHTML = + " (" + descr + ")"; + // highlight search terms in the description + if (SPHINX_HIGHLIGHT_ENABLED) // set in sphinx_highlight.js + highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted")); + } + else if (showSearchSummary) + fetch(requestUrl) + .then((responseData) => responseData.text()) + .then((data) => { + if (data) + listItem.appendChild( + Search.makeSearchSummary(data, searchTerms) + ); + // highlight search terms in the summary + if (SPHINX_HIGHLIGHT_ENABLED) // set in sphinx_highlight.js + highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted")); + }); + Search.output.appendChild(listItem); +}; +const _finishSearch = (resultCount) => { + Search.stopPulse(); + Search.title.innerText = _("Search Results"); + if (!resultCount) + Search.status.innerText = Documentation.gettext( + "Your search did not match any documents. Please make sure that all words are spelled correctly and that you've selected enough categories." + ); + else + Search.status.innerText = _( + `Search finished, found ${resultCount} page(s) matching the search query.` + ); +}; +const _displayNextItem = ( + results, + resultCount, + searchTerms, + highlightTerms, +) => { + // results left, load the summary and display it + // this is intended to be dynamic (don't sub resultsCount) + if (results.length) { + _displayItem(results.pop(), searchTerms, highlightTerms); + setTimeout( + () => _displayNextItem(results, resultCount, searchTerms, highlightTerms), + 5 + ); + } + // search finished, update title and status message + else _finishSearch(resultCount); +}; + +/** + * Default splitQuery function. Can be overridden in ``sphinx.search`` with a + * custom function per language. + * + * The regular expression works by splitting the string on consecutive characters + * that are not Unicode letters, numbers, underscores, or emoji characters. + * This is the same as ``\W+`` in Python, preserving the surrogate pair area. + */ +if (typeof splitQuery === "undefined") { + var splitQuery = (query) => query + .split(/[^\p{Letter}\p{Number}_\p{Emoji_Presentation}]+/gu) + .filter(term => term) // remove remaining empty strings +} + +/** + * Search Module + */ +const Search = { + _index: null, + _queued_query: null, + _pulse_status: -1, + + htmlToText: (htmlString) => { + const htmlElement = new DOMParser().parseFromString(htmlString, 'text/html'); + htmlElement.querySelectorAll(".headerlink").forEach((el) => { el.remove() }); + const docContent = htmlElement.querySelector('[role="main"]'); + if (docContent !== undefined) return docContent.textContent; + console.warn( + "Content block not found. Sphinx search tries to obtain it via '[role=main]'. Could you check your theme or template." + ); + return ""; + }, + + init: () => { + const query = new URLSearchParams(window.location.search).get("q"); + document + .querySelectorAll('input[name="q"]') + .forEach((el) => (el.value = query)); + if (query) Search.performSearch(query); + }, + + loadIndex: (url) => + (document.body.appendChild(document.createElement("script")).src = url), + + setIndex: (index) => { + Search._index = index; + if (Search._queued_query !== null) { + const query = Search._queued_query; + Search._queued_query = null; + Search.query(query); + } + }, + + hasIndex: () => Search._index !== null, + + deferQuery: (query) => (Search._queued_query = query), + + stopPulse: () => (Search._pulse_status = -1), + + startPulse: () => { + if (Search._pulse_status >= 0) return; + + const pulse = () => { + Search._pulse_status = (Search._pulse_status + 1) % 4; + Search.dots.innerText = ".".repeat(Search._pulse_status); + if (Search._pulse_status >= 0) window.setTimeout(pulse, 500); + }; + pulse(); + }, + + /** + * perform a search for something (or wait until index is loaded) + */ + performSearch: (query) => { + // create the required interface elements + const searchText = document.createElement("h2"); + searchText.textContent = _("Searching"); + const searchSummary = document.createElement("p"); + searchSummary.classList.add("search-summary"); + searchSummary.innerText = ""; + const searchList = document.createElement("ul"); + searchList.classList.add("search"); + + const out = document.getElementById("search-results"); + Search.title = out.appendChild(searchText); + Search.dots = Search.title.appendChild(document.createElement("span")); + Search.status = out.appendChild(searchSummary); + Search.output = out.appendChild(searchList); + + const searchProgress = document.getElementById("search-progress"); + // Some themes don't use the search progress node + if (searchProgress) { + searchProgress.innerText = _("Preparing search..."); + } + Search.startPulse(); + + // index already loaded, the browser was quick! + if (Search.hasIndex()) Search.query(query); + else Search.deferQuery(query); + }, + + /** + * execute search (requires search index to be loaded) + */ + query: (query) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + const allTitles = Search._index.alltitles; + const indexEntries = Search._index.indexentries; + + // stem the search terms and add them to the correct list + const stemmer = new Stemmer(); + const searchTerms = new Set(); + const excludedTerms = new Set(); + const highlightTerms = new Set(); + const objectTerms = new Set(splitQuery(query.toLowerCase().trim())); + splitQuery(query.trim()).forEach((queryTerm) => { + const queryTermLower = queryTerm.toLowerCase(); + + // maybe skip this "word" + // stopwords array is from language_data.js + if ( + stopwords.indexOf(queryTermLower) !== -1 || + queryTerm.match(/^\d+$/) + ) + return; + + // stem the word + let word = stemmer.stemWord(queryTermLower); + // select the correct list + if (word[0] === "-") excludedTerms.add(word.substr(1)); + else { + searchTerms.add(word); + highlightTerms.add(queryTermLower); + } + }); + + if (SPHINX_HIGHLIGHT_ENABLED) { // set in sphinx_highlight.js + localStorage.setItem("sphinx_highlight_terms", [...highlightTerms].join(" ")) + } + + // console.debug("SEARCH: searching for:"); + // console.info("required: ", [...searchTerms]); + // console.info("excluded: ", [...excludedTerms]); + + // array of [docname, title, anchor, descr, score, filename] + let results = []; + _removeChildren(document.getElementById("search-progress")); + + const queryLower = query.toLowerCase(); + for (const [title, foundTitles] of Object.entries(allTitles)) { + if (title.toLowerCase().includes(queryLower) && (queryLower.length >= title.length/2)) { + for (const [file, id] of foundTitles) { + let score = Math.round(100 * queryLower.length / title.length) + results.push([ + docNames[file], + titles[file] !== title ? `${titles[file]} > ${title}` : title, + id !== null ? "#" + id : "", + null, + score, + filenames[file], + ]); + } + } + } + + // search for explicit entries in index directives + for (const [entry, foundEntries] of Object.entries(indexEntries)) { + if (entry.includes(queryLower) && (queryLower.length >= entry.length/2)) { + for (const [file, id] of foundEntries) { + let score = Math.round(100 * queryLower.length / entry.length) + results.push([ + docNames[file], + titles[file], + id ? "#" + id : "", + null, + score, + filenames[file], + ]); + } + } + } + + // lookup as object + objectTerms.forEach((term) => + results.push(...Search.performObjectSearch(term, objectTerms)) + ); + + // lookup as search terms in fulltext + results.push(...Search.performTermsSearch(searchTerms, excludedTerms)); + + // let the scorer override scores with a custom scoring function + if (Scorer.score) results.forEach((item) => (item[4] = Scorer.score(item))); + + // now sort the results by score (in opposite order of appearance, since the + // display function below uses pop() to retrieve items) and then + // alphabetically + results.sort((a, b) => { + const leftScore = a[4]; + const rightScore = b[4]; + if (leftScore === rightScore) { + // same score: sort alphabetically + const leftTitle = a[1].toLowerCase(); + const rightTitle = b[1].toLowerCase(); + if (leftTitle === rightTitle) return 0; + return leftTitle > rightTitle ? -1 : 1; // inverted is intentional + } + return leftScore > rightScore ? 1 : -1; + }); + + // remove duplicate search results + // note the reversing of results, so that in the case of duplicates, the highest-scoring entry is kept + let seen = new Set(); + results = results.reverse().reduce((acc, result) => { + let resultStr = result.slice(0, 4).concat([result[5]]).map(v => String(v)).join(','); + if (!seen.has(resultStr)) { + acc.push(result); + seen.add(resultStr); + } + return acc; + }, []); + + results = results.reverse(); + + // for debugging + //Search.lastresults = results.slice(); // a copy + // console.info("search results:", Search.lastresults); + + // print the results + _displayNextItem(results, results.length, searchTerms, highlightTerms); + }, + + /** + * search for object names + */ + performObjectSearch: (object, objectTerms) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const objects = Search._index.objects; + const objNames = Search._index.objnames; + const titles = Search._index.titles; + + const results = []; + + const objectSearchCallback = (prefix, match) => { + const name = match[4] + const fullname = (prefix ? prefix + "." : "") + name; + const fullnameLower = fullname.toLowerCase(); + if (fullnameLower.indexOf(object) < 0) return; + + let score = 0; + const parts = fullnameLower.split("."); + + // check for different match types: exact matches of full name or + // "last name" (i.e. last dotted part) + if (fullnameLower === object || parts.slice(-1)[0] === object) + score += Scorer.objNameMatch; + else if (parts.slice(-1)[0].indexOf(object) > -1) + score += Scorer.objPartialMatch; // matches in last name + + const objName = objNames[match[1]][2]; + const title = titles[match[0]]; + + // If more than one term searched for, we require other words to be + // found in the name/title/description + const otherTerms = new Set(objectTerms); + otherTerms.delete(object); + if (otherTerms.size > 0) { + const haystack = `${prefix} ${name} ${objName} ${title}`.toLowerCase(); + if ( + [...otherTerms].some((otherTerm) => haystack.indexOf(otherTerm) < 0) + ) + return; + } + + let anchor = match[3]; + if (anchor === "") anchor = fullname; + else if (anchor === "-") anchor = objNames[match[1]][1] + "-" + fullname; + + const descr = objName + _(", in ") + title; + + // add custom score for some objects according to scorer + if (Scorer.objPrio.hasOwnProperty(match[2])) + score += Scorer.objPrio[match[2]]; + else score += Scorer.objPrioDefault; + + results.push([ + docNames[match[0]], + fullname, + "#" + anchor, + descr, + score, + filenames[match[0]], + ]); + }; + Object.keys(objects).forEach((prefix) => + objects[prefix].forEach((array) => + objectSearchCallback(prefix, array) + ) + ); + return results; + }, + + /** + * search for full-text terms in the index + */ + performTermsSearch: (searchTerms, excludedTerms) => { + // prepare search + const terms = Search._index.terms; + const titleTerms = Search._index.titleterms; + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + + const scoreMap = new Map(); + const fileMap = new Map(); + + // perform the search on the required terms + searchTerms.forEach((word) => { + const files = []; + const arr = [ + { files: terms[word], score: Scorer.term }, + { files: titleTerms[word], score: Scorer.title }, + ]; + // add support for partial matches + if (word.length > 2) { + const escapedWord = _escapeRegExp(word); + Object.keys(terms).forEach((term) => { + if (term.match(escapedWord) && !terms[word]) + arr.push({ files: terms[term], score: Scorer.partialTerm }); + }); + Object.keys(titleTerms).forEach((term) => { + if (term.match(escapedWord) && !titleTerms[word]) + arr.push({ files: titleTerms[word], score: Scorer.partialTitle }); + }); + } + + // no match but word was a required one + if (arr.every((record) => record.files === undefined)) return; + + // found search word in contents + arr.forEach((record) => { + if (record.files === undefined) return; + + let recordFiles = record.files; + if (recordFiles.length === undefined) recordFiles = [recordFiles]; + files.push(...recordFiles); + + // set score for the word in each file + recordFiles.forEach((file) => { + if (!scoreMap.has(file)) scoreMap.set(file, {}); + scoreMap.get(file)[word] = record.score; + }); + }); + + // create the mapping + files.forEach((file) => { + if (fileMap.has(file) && fileMap.get(file).indexOf(word) === -1) + fileMap.get(file).push(word); + else fileMap.set(file, [word]); + }); + }); + + // now check if the files don't contain excluded terms + const results = []; + for (const [file, wordList] of fileMap) { + // check if all requirements are matched + + // as search terms with length < 3 are discarded + const filteredTermCount = [...searchTerms].filter( + (term) => term.length > 2 + ).length; + if ( + wordList.length !== searchTerms.size && + wordList.length !== filteredTermCount + ) + continue; + + // ensure that none of the excluded terms is in the search result + if ( + [...excludedTerms].some( + (term) => + terms[term] === file || + titleTerms[term] === file || + (terms[term] || []).includes(file) || + (titleTerms[term] || []).includes(file) + ) + ) + break; + + // select one (max) score for the file. + const score = Math.max(...wordList.map((w) => scoreMap.get(file)[w])); + // add result to the result list + results.push([ + docNames[file], + titles[file], + "", + null, + score, + filenames[file], + ]); + } + return results; + }, + + /** + * helper function to return a node containing the + * search summary for a given text. keywords is a list + * of stemmed words. + */ + makeSearchSummary: (htmlText, keywords) => { + const text = Search.htmlToText(htmlText); + if (text === "") return null; + + const textLower = text.toLowerCase(); + const actualStartPosition = [...keywords] + .map((k) => textLower.indexOf(k.toLowerCase())) + .filter((i) => i > -1) + .slice(-1)[0]; + const startWithContext = Math.max(actualStartPosition - 120, 0); + + const top = startWithContext === 0 ? "" : "..."; + const tail = startWithContext + 240 < text.length ? "..." : ""; + + let summary = document.createElement("p"); + summary.classList.add("context"); + summary.textContent = top + text.substr(startWithContext, 240).trim() + tail; + + return summary; + }, +}; + +_ready(Search.init); diff --git a/_static/sphinx_highlight.js b/_static/sphinx_highlight.js new file mode 100644 index 00000000..8a96c69a --- /dev/null +++ b/_static/sphinx_highlight.js @@ -0,0 +1,154 @@ +/* Highlighting utilities for Sphinx HTML documentation. */ +"use strict"; + +const SPHINX_HIGHLIGHT_ENABLED = true + +/** + * highlight a given string on a node by wrapping it in + * span elements with the given class name. + */ +const _highlight = (node, addItems, text, className) => { + if (node.nodeType === Node.TEXT_NODE) { + const val = node.nodeValue; + const parent = node.parentNode; + const pos = val.toLowerCase().indexOf(text); + if ( + pos >= 0 && + !parent.classList.contains(className) && + !parent.classList.contains("nohighlight") + ) { + let span; + + const closestNode = parent.closest("body, svg, foreignObject"); + const isInSVG = closestNode && closestNode.matches("svg"); + if (isInSVG) { + span = document.createElementNS("http://www.w3.org/2000/svg", "tspan"); + } else { + span = document.createElement("span"); + span.classList.add(className); + } + + span.appendChild(document.createTextNode(val.substr(pos, text.length))); + const rest = document.createTextNode(val.substr(pos + text.length)); + parent.insertBefore( + span, + parent.insertBefore( + rest, + node.nextSibling + ) + ); + node.nodeValue = val.substr(0, pos); + /* There may be more occurrences of search term in this node. So call this + * function recursively on the remaining fragment. + */ + _highlight(rest, addItems, text, className); + + if (isInSVG) { + const rect = document.createElementNS( + "http://www.w3.org/2000/svg", + "rect" + ); + const bbox = parent.getBBox(); + rect.x.baseVal.value = bbox.x; + rect.y.baseVal.value = bbox.y; + rect.width.baseVal.value = bbox.width; + rect.height.baseVal.value = bbox.height; + rect.setAttribute("class", className); + addItems.push({ parent: parent, target: rect }); + } + } + } else if (node.matches && !node.matches("button, select, textarea")) { + node.childNodes.forEach((el) => _highlight(el, addItems, text, className)); + } +}; +const _highlightText = (thisNode, text, className) => { + let addItems = []; + _highlight(thisNode, addItems, text, className); + addItems.forEach((obj) => + obj.parent.insertAdjacentElement("beforebegin", obj.target) + ); +}; + +/** + * Small JavaScript module for the documentation. + */ +const SphinxHighlight = { + + /** + * highlight the search words provided in localstorage in the text + */ + highlightSearchWords: () => { + if (!SPHINX_HIGHLIGHT_ENABLED) return; // bail if no highlight + + // get and clear terms from localstorage + const url = new URL(window.location); + const highlight = + localStorage.getItem("sphinx_highlight_terms") + || url.searchParams.get("highlight") + || ""; + localStorage.removeItem("sphinx_highlight_terms") + url.searchParams.delete("highlight"); + window.history.replaceState({}, "", url); + + // get individual terms from highlight string + const terms = highlight.toLowerCase().split(/\s+/).filter(x => x); + if (terms.length === 0) return; // nothing to do + + // There should never be more than one element matching "div.body" + const divBody = document.querySelectorAll("div.body"); + const body = divBody.length ? divBody[0] : document.querySelector("body"); + window.setTimeout(() => { + terms.forEach((term) => _highlightText(body, term, "highlighted")); + }, 10); + + const searchBox = document.getElementById("searchbox"); + if (searchBox === null) return; + searchBox.appendChild( + document + .createRange() + .createContextualFragment( + '

' + + '' + + _("Hide Search Matches") + + "

" + ) + ); + }, + + /** + * helper function to hide the search marks again + */ + hideSearchWords: () => { + document + .querySelectorAll("#searchbox .highlight-link") + .forEach((el) => el.remove()); + document + .querySelectorAll("span.highlighted") + .forEach((el) => el.classList.remove("highlighted")); + localStorage.removeItem("sphinx_highlight_terms") + }, + + initEscapeListener: () => { + // only install a listener if it is really needed + if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) return; + + document.addEventListener("keydown", (event) => { + // bail for input elements + if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return; + // bail with special keys + if (event.shiftKey || event.altKey || event.ctrlKey || event.metaKey) return; + if (DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS && (event.key === "Escape")) { + SphinxHighlight.hideSearchWords(); + event.preventDefault(); + } + }); + }, +}; + +_ready(() => { + /* Do not call highlightSearchWords() when we are on the search page. + * It will highlight words from the *previous* search query. + */ + if (typeof Search === "undefined") SphinxHighlight.highlightSearchWords(); + SphinxHighlight.initEscapeListener(); +}); diff --git a/coverage/coverage_html.js b/coverage/coverage_html.js new file mode 100644 index 00000000..59348828 --- /dev/null +++ b/coverage/coverage_html.js @@ -0,0 +1,624 @@ +// Licensed under the Apache License: http://www.apache.org/licenses/LICENSE-2.0 +// For details: https://github.com/nedbat/coveragepy/blob/master/NOTICE.txt + +// Coverage.py HTML report browser code. +/*jslint browser: true, sloppy: true, vars: true, plusplus: true, maxerr: 50, indent: 4 */ +/*global coverage: true, document, window, $ */ + +coverage = {}; + +// General helpers +function debounce(callback, wait) { + let timeoutId = null; + return function(...args) { + clearTimeout(timeoutId); + timeoutId = setTimeout(() => { + callback.apply(this, args); + }, wait); + }; +}; + +function checkVisible(element) { + const rect = element.getBoundingClientRect(); + const viewBottom = Math.max(document.documentElement.clientHeight, window.innerHeight); + const viewTop = 30; + return !(rect.bottom < viewTop || rect.top >= viewBottom); +} + +function on_click(sel, fn) { + const elt = document.querySelector(sel); + if (elt) { + elt.addEventListener("click", fn); + } +} + +// Helpers for table sorting +function getCellValue(row, column = 0) { + const cell = row.cells[column] // nosemgrep: eslint.detect-object-injection + if (cell.childElementCount == 1) { + const child = cell.firstElementChild + if (child instanceof HTMLTimeElement && child.dateTime) { + return child.dateTime + } else if (child instanceof HTMLDataElement && child.value) { + return child.value + } + } + return cell.innerText || cell.textContent; +} + +function rowComparator(rowA, rowB, column = 0) { + let valueA = getCellValue(rowA, column); + let valueB = getCellValue(rowB, column); + if (!isNaN(valueA) && !isNaN(valueB)) { + return valueA - valueB + } + return valueA.localeCompare(valueB, undefined, {numeric: true}); +} + +function sortColumn(th) { + // Get the current sorting direction of the selected header, + // clear state on other headers and then set the new sorting direction + const currentSortOrder = th.getAttribute("aria-sort"); + [...th.parentElement.cells].forEach(header => header.setAttribute("aria-sort", "none")); + if (currentSortOrder === "none") { + th.setAttribute("aria-sort", th.dataset.defaultSortOrder || "ascending"); + } else { + th.setAttribute("aria-sort", currentSortOrder === "ascending" ? "descending" : "ascending"); + } + + const column = [...th.parentElement.cells].indexOf(th) + + // Sort all rows and afterwards append them in order to move them in the DOM + Array.from(th.closest("table").querySelectorAll("tbody tr")) + .sort((rowA, rowB) => rowComparator(rowA, rowB, column) * (th.getAttribute("aria-sort") === "ascending" ? 1 : -1)) + .forEach(tr => tr.parentElement.appendChild(tr) ); +} + +// Find all the elements with data-shortcut attribute, and use them to assign a shortcut key. +coverage.assign_shortkeys = function () { + document.querySelectorAll("[data-shortcut]").forEach(element => { + document.addEventListener("keypress", event => { + if (event.target.tagName.toLowerCase() === "input") { + return; // ignore keypress from search filter + } + if (event.key === element.dataset.shortcut) { + element.click(); + } + }); + }); +}; + +// Create the events for the filter box. +coverage.wire_up_filter = function () { + // Cache elements. + const table = document.querySelector("table.index"); + const table_body_rows = table.querySelectorAll("tbody tr"); + const no_rows = document.getElementById("no_rows"); + + // Observe filter keyevents. + document.getElementById("filter").addEventListener("input", debounce(event => { + // Keep running total of each metric, first index contains number of shown rows + const totals = new Array(table.rows[0].cells.length).fill(0); + // Accumulate the percentage as fraction + totals[totals.length - 1] = { "numer": 0, "denom": 0 }; // nosemgrep: eslint.detect-object-injection + + // Hide / show elements. + table_body_rows.forEach(row => { + if (!row.cells[0].textContent.includes(event.target.value)) { + // hide + row.classList.add("hidden"); + return; + } + + // show + row.classList.remove("hidden"); + totals[0]++; + + for (let column = 1; column < totals.length; column++) { + // Accumulate dynamic totals + cell = row.cells[column] // nosemgrep: eslint.detect-object-injection + if (column === totals.length - 1) { + // Last column contains percentage + const [numer, denom] = cell.dataset.ratio.split(" "); + totals[column]["numer"] += parseInt(numer, 10); // nosemgrep: eslint.detect-object-injection + totals[column]["denom"] += parseInt(denom, 10); // nosemgrep: eslint.detect-object-injection + } else { + totals[column] += parseInt(cell.textContent, 10); // nosemgrep: eslint.detect-object-injection + } + } + }); + + // Show placeholder if no rows will be displayed. + if (!totals[0]) { + // Show placeholder, hide table. + no_rows.style.display = "block"; + table.style.display = "none"; + return; + } + + // Hide placeholder, show table. + no_rows.style.display = null; + table.style.display = null; + + const footer = table.tFoot.rows[0]; + // Calculate new dynamic sum values based on visible rows. + for (let column = 1; column < totals.length; column++) { + // Get footer cell element. + const cell = footer.cells[column]; // nosemgrep: eslint.detect-object-injection + + // Set value into dynamic footer cell element. + if (column === totals.length - 1) { + // Percentage column uses the numerator and denominator, + // and adapts to the number of decimal places. + const match = /\.([0-9]+)/.exec(cell.textContent); + const places = match ? match[1].length : 0; + const { numer, denom } = totals[column]; // nosemgrep: eslint.detect-object-injection + cell.dataset.ratio = `${numer} ${denom}`; + // Check denom to prevent NaN if filtered files contain no statements + cell.textContent = denom + ? `${(numer * 100 / denom).toFixed(places)}%` + : `${(100).toFixed(places)}%`; + } else { + cell.textContent = totals[column]; // nosemgrep: eslint.detect-object-injection + } + } + })); + + // Trigger change event on setup, to force filter on page refresh + // (filter value may still be present). + document.getElementById("filter").dispatchEvent(new Event("input")); +}; + +coverage.INDEX_SORT_STORAGE = "COVERAGE_INDEX_SORT_2"; + +// Loaded on index.html +coverage.index_ready = function () { + coverage.assign_shortkeys(); + coverage.wire_up_filter(); + document.querySelectorAll("[data-sortable] th[aria-sort]").forEach( + th => th.addEventListener("click", e => sortColumn(e.target)) + ); + + // Look for a localStorage item containing previous sort settings: + const stored_list = localStorage.getItem(coverage.INDEX_SORT_STORAGE); + + if (stored_list) { + const {column, direction} = JSON.parse(stored_list); + const th = document.querySelector("[data-sortable]").tHead.rows[0].cells[column]; // nosemgrep: eslint.detect-object-injection + th.setAttribute("aria-sort", direction === "ascending" ? "descending" : "ascending"); + th.click() + } + + // Watch for page unload events so we can save the final sort settings: + window.addEventListener("unload", function () { + const th = document.querySelector('[data-sortable] th[aria-sort="ascending"], [data-sortable] [aria-sort="descending"]'); + if (!th) { + return; + } + localStorage.setItem(coverage.INDEX_SORT_STORAGE, JSON.stringify({ + column: [...th.parentElement.cells].indexOf(th), + direction: th.getAttribute("aria-sort"), + })); + }); + + on_click(".button_prev_file", coverage.to_prev_file); + on_click(".button_next_file", coverage.to_next_file); + + on_click(".button_show_hide_help", coverage.show_hide_help); +}; + +// -- pyfile stuff -- + +coverage.LINE_FILTERS_STORAGE = "COVERAGE_LINE_FILTERS"; + +coverage.pyfile_ready = function () { + // If we're directed to a particular line number, highlight the line. + var frag = location.hash; + if (frag.length > 2 && frag[1] === "t") { + document.querySelector(frag).closest(".n").classList.add("highlight"); + coverage.set_sel(parseInt(frag.substr(2), 10)); + } else { + coverage.set_sel(0); + } + + on_click(".button_toggle_run", coverage.toggle_lines); + on_click(".button_toggle_mis", coverage.toggle_lines); + on_click(".button_toggle_exc", coverage.toggle_lines); + on_click(".button_toggle_par", coverage.toggle_lines); + + on_click(".button_next_chunk", coverage.to_next_chunk_nicely); + on_click(".button_prev_chunk", coverage.to_prev_chunk_nicely); + on_click(".button_top_of_page", coverage.to_top); + on_click(".button_first_chunk", coverage.to_first_chunk); + + on_click(".button_prev_file", coverage.to_prev_file); + on_click(".button_next_file", coverage.to_next_file); + on_click(".button_to_index", coverage.to_index); + + on_click(".button_show_hide_help", coverage.show_hide_help); + + coverage.filters = undefined; + try { + coverage.filters = localStorage.getItem(coverage.LINE_FILTERS_STORAGE); + } catch(err) {} + + if (coverage.filters) { + coverage.filters = JSON.parse(coverage.filters); + } + else { + coverage.filters = {run: false, exc: true, mis: true, par: true}; + } + + for (cls in coverage.filters) { + coverage.set_line_visibilty(cls, coverage.filters[cls]); // nosemgrep: eslint.detect-object-injection + } + + coverage.assign_shortkeys(); + coverage.init_scroll_markers(); + coverage.wire_up_sticky_header(); + + document.querySelectorAll("[id^=ctxs]").forEach( + cbox => cbox.addEventListener("click", coverage.expand_contexts) + ); + + // Rebuild scroll markers when the window height changes. + window.addEventListener("resize", coverage.build_scroll_markers); +}; + +coverage.toggle_lines = function (event) { + const btn = event.target.closest("button"); + const category = btn.value + const show = !btn.classList.contains("show_" + category); + coverage.set_line_visibilty(category, show); + coverage.build_scroll_markers(); + coverage.filters[category] = show; + try { + localStorage.setItem(coverage.LINE_FILTERS_STORAGE, JSON.stringify(coverage.filters)); + } catch(err) {} +}; + +coverage.set_line_visibilty = function (category, should_show) { + const cls = "show_" + category; + const btn = document.querySelector(".button_toggle_" + category); + if (btn) { + if (should_show) { + document.querySelectorAll("#source ." + category).forEach(e => e.classList.add(cls)); + btn.classList.add(cls); + } + else { + document.querySelectorAll("#source ." + category).forEach(e => e.classList.remove(cls)); + btn.classList.remove(cls); + } + } +}; + +// Return the nth line div. +coverage.line_elt = function (n) { + return document.getElementById("t" + n)?.closest("p"); +}; + +// Set the selection. b and e are line numbers. +coverage.set_sel = function (b, e) { + // The first line selected. + coverage.sel_begin = b; + // The next line not selected. + coverage.sel_end = (e === undefined) ? b+1 : e; +}; + +coverage.to_top = function () { + coverage.set_sel(0, 1); + coverage.scroll_window(0); +}; + +coverage.to_first_chunk = function () { + coverage.set_sel(0, 1); + coverage.to_next_chunk(); +}; + +coverage.to_prev_file = function () { + window.location = document.getElementById("prevFileLink").href; +} + +coverage.to_next_file = function () { + window.location = document.getElementById("nextFileLink").href; +} + +coverage.to_index = function () { + location.href = document.getElementById("indexLink").href; +} + +coverage.show_hide_help = function () { + const helpCheck = document.getElementById("help_panel_state") + helpCheck.checked = !helpCheck.checked; +} + +// Return a string indicating what kind of chunk this line belongs to, +// or null if not a chunk. +coverage.chunk_indicator = function (line_elt) { + const classes = line_elt?.className; + if (!classes) { + return null; + } + const match = classes.match(/\bshow_\w+\b/); + if (!match) { + return null; + } + return match[0]; +}; + +coverage.to_next_chunk = function () { + const c = coverage; + + // Find the start of the next colored chunk. + var probe = c.sel_end; + var chunk_indicator, probe_line; + while (true) { + probe_line = c.line_elt(probe); + if (!probe_line) { + return; + } + chunk_indicator = c.chunk_indicator(probe_line); + if (chunk_indicator) { + break; + } + probe++; + } + + // There's a next chunk, `probe` points to it. + var begin = probe; + + // Find the end of this chunk. + var next_indicator = chunk_indicator; + while (next_indicator === chunk_indicator) { + probe++; + probe_line = c.line_elt(probe); + next_indicator = c.chunk_indicator(probe_line); + } + c.set_sel(begin, probe); + c.show_selection(); +}; + +coverage.to_prev_chunk = function () { + const c = coverage; + + // Find the end of the prev colored chunk. + var probe = c.sel_begin-1; + var probe_line = c.line_elt(probe); + if (!probe_line) { + return; + } + var chunk_indicator = c.chunk_indicator(probe_line); + while (probe > 1 && !chunk_indicator) { + probe--; + probe_line = c.line_elt(probe); + if (!probe_line) { + return; + } + chunk_indicator = c.chunk_indicator(probe_line); + } + + // There's a prev chunk, `probe` points to its last line. + var end = probe+1; + + // Find the beginning of this chunk. + var prev_indicator = chunk_indicator; + while (prev_indicator === chunk_indicator) { + probe--; + if (probe <= 0) { + return; + } + probe_line = c.line_elt(probe); + prev_indicator = c.chunk_indicator(probe_line); + } + c.set_sel(probe+1, end); + c.show_selection(); +}; + +// Returns 0, 1, or 2: how many of the two ends of the selection are on +// the screen right now? +coverage.selection_ends_on_screen = function () { + if (coverage.sel_begin === 0) { + return 0; + } + + const begin = coverage.line_elt(coverage.sel_begin); + const end = coverage.line_elt(coverage.sel_end-1); + + return ( + (checkVisible(begin) ? 1 : 0) + + (checkVisible(end) ? 1 : 0) + ); +}; + +coverage.to_next_chunk_nicely = function () { + if (coverage.selection_ends_on_screen() === 0) { + // The selection is entirely off the screen: + // Set the top line on the screen as selection. + + // This will select the top-left of the viewport + // As this is most likely the span with the line number we take the parent + const line = document.elementFromPoint(0, 0).parentElement; + if (line.parentElement !== document.getElementById("source")) { + // The element is not a source line but the header or similar + coverage.select_line_or_chunk(1); + } else { + // We extract the line number from the id + coverage.select_line_or_chunk(parseInt(line.id.substring(1), 10)); + } + } + coverage.to_next_chunk(); +}; + +coverage.to_prev_chunk_nicely = function () { + if (coverage.selection_ends_on_screen() === 0) { + // The selection is entirely off the screen: + // Set the lowest line on the screen as selection. + + // This will select the bottom-left of the viewport + // As this is most likely the span with the line number we take the parent + const line = document.elementFromPoint(document.documentElement.clientHeight-1, 0).parentElement; + if (line.parentElement !== document.getElementById("source")) { + // The element is not a source line but the header or similar + coverage.select_line_or_chunk(coverage.lines_len); + } else { + // We extract the line number from the id + coverage.select_line_or_chunk(parseInt(line.id.substring(1), 10)); + } + } + coverage.to_prev_chunk(); +}; + +// Select line number lineno, or if it is in a colored chunk, select the +// entire chunk +coverage.select_line_or_chunk = function (lineno) { + var c = coverage; + var probe_line = c.line_elt(lineno); + if (!probe_line) { + return; + } + var the_indicator = c.chunk_indicator(probe_line); + if (the_indicator) { + // The line is in a highlighted chunk. + // Search backward for the first line. + var probe = lineno; + var indicator = the_indicator; + while (probe > 0 && indicator === the_indicator) { + probe--; + probe_line = c.line_elt(probe); + if (!probe_line) { + break; + } + indicator = c.chunk_indicator(probe_line); + } + var begin = probe + 1; + + // Search forward for the last line. + probe = lineno; + indicator = the_indicator; + while (indicator === the_indicator) { + probe++; + probe_line = c.line_elt(probe); + indicator = c.chunk_indicator(probe_line); + } + + coverage.set_sel(begin, probe); + } + else { + coverage.set_sel(lineno); + } +}; + +coverage.show_selection = function () { + // Highlight the lines in the chunk + document.querySelectorAll("#source .highlight").forEach(e => e.classList.remove("highlight")); + for (let probe = coverage.sel_begin; probe < coverage.sel_end; probe++) { + coverage.line_elt(probe).querySelector(".n").classList.add("highlight"); + } + + coverage.scroll_to_selection(); +}; + +coverage.scroll_to_selection = function () { + // Scroll the page if the chunk isn't fully visible. + if (coverage.selection_ends_on_screen() < 2) { + const element = coverage.line_elt(coverage.sel_begin); + coverage.scroll_window(element.offsetTop - 60); + } +}; + +coverage.scroll_window = function (to_pos) { + window.scroll({top: to_pos, behavior: "smooth"}); +}; + +coverage.init_scroll_markers = function () { + // Init some variables + coverage.lines_len = document.querySelectorAll("#source > p").length; + + // Build html + coverage.build_scroll_markers(); +}; + +coverage.build_scroll_markers = function () { + const temp_scroll_marker = document.getElementById("scroll_marker") + if (temp_scroll_marker) temp_scroll_marker.remove(); + // Don't build markers if the window has no scroll bar. + if (document.body.scrollHeight <= window.innerHeight) { + return; + } + + const marker_scale = window.innerHeight / document.body.scrollHeight; + const line_height = Math.min(Math.max(3, window.innerHeight / coverage.lines_len), 10); + + let previous_line = -99, last_mark, last_top; + + const scroll_marker = document.createElement("div"); + scroll_marker.id = "scroll_marker"; + document.getElementById("source").querySelectorAll( + "p.show_run, p.show_mis, p.show_exc, p.show_exc, p.show_par" + ).forEach(element => { + const line_top = Math.floor(element.offsetTop * marker_scale); + const line_number = parseInt(element.querySelector(".n a").id.substr(1)); + + if (line_number === previous_line + 1) { + // If this solid missed block just make previous mark higher. + last_mark.style.height = `${line_top + line_height - last_top}px`; + } else { + // Add colored line in scroll_marker block. + last_mark = document.createElement("div"); + last_mark.id = `m${line_number}`; + last_mark.classList.add("marker"); + last_mark.style.height = `${line_height}px`; + last_mark.style.top = `${line_top}px`; + scroll_marker.append(last_mark); + last_top = line_top; + } + + previous_line = line_number; + }); + + // Append last to prevent layout calculation + document.body.append(scroll_marker); +}; + +coverage.wire_up_sticky_header = function () { + const header = document.querySelector("header"); + const header_bottom = ( + header.querySelector(".content h2").getBoundingClientRect().top - + header.getBoundingClientRect().top + ); + + function updateHeader() { + if (window.scrollY > header_bottom) { + header.classList.add("sticky"); + } else { + header.classList.remove("sticky"); + } + } + + window.addEventListener("scroll", updateHeader); + updateHeader(); +}; + +coverage.expand_contexts = function (e) { + var ctxs = e.target.parentNode.querySelector(".ctxs"); + + if (!ctxs.classList.contains("expanded")) { + var ctxs_text = ctxs.textContent; + var width = Number(ctxs_text[0]); + ctxs.textContent = ""; + for (var i = 1; i < ctxs_text.length; i += width) { + key = ctxs_text.substring(i, i + width).trim(); + ctxs.appendChild(document.createTextNode(contexts[key])); + ctxs.appendChild(document.createElement("br")); + } + ctxs.classList.add("expanded"); + } +}; + +document.addEventListener("DOMContentLoaded", () => { + if (document.body.classList.contains("indexfile")) { + coverage.index_ready(); + } else { + coverage.pyfile_ready(); + } +}); diff --git a/coverage/d_bb657af29d23493a_Attributes_py.html b/coverage/d_bb657af29d23493a_Attributes_py.html new file mode 100644 index 00000000..81cedfe0 --- /dev/null +++ b/coverage/d_bb657af29d23493a_Attributes_py.html @@ -0,0 +1,152 @@ + + + + + Coverage for pyEDAA/ProjectModel/Attributes.py: 100% + + + + + +
+
+

+ Coverage for pyEDAA/ProjectModel/Attributes.py: + 100% +

+ +

+ 15 statements   + + + + +

+

+ « prev     + ^ index     + » next +       + coverage.py v7.3.0, + created at 2023-08-24 21:52 +0000 +

+ +
+
+
+

1# ==================================================================================================================== # 

+

2# _____ ____ _ _ ____ _ _ __ __ _ _ # 

+

3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # 

+

4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # 

+

5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # 

+

6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # 

+

7# |_| |___/ |__/ # 

+

8# ==================================================================================================================== # 

+

9# Authors: # 

+

10# Patrick Lehmann # 

+

11# # 

+

12# License: # 

+

13# ==================================================================================================================== # 

+

14# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany # 

+

15# # 

+

16# Licensed under the Apache License, Version 2.0 (the "License"); # 

+

17# you may not use this file except in compliance with the License. # 

+

18# You may obtain a copy of the License at # 

+

19# # 

+

20# http://www.apache.org/licenses/LICENSE-2.0 # 

+

21# # 

+

22# Unless required by applicable law or agreed to in writing, software # 

+

23# distributed under the License is distributed on an "AS IS" BASIS, # 

+

24# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # 

+

25# See the License for the specific language governing permissions and # 

+

26# limitations under the License. # 

+

27# # 

+

28# SPDX-License-Identifier: Apache-2.0 # 

+

29# ==================================================================================================================== # 

+

30# 

+

31"""A set of common attributes to store meta information on ProjectModel entities (project, design, fileset, file, ...).""" 

+

32from typing import Dict 

+

33from pyTooling.Decorators import export 

+

34 

+

35from pyEDAA.ProjectModel import Attribute 

+

36 

+

37 

+

38@export 

+

39class KeyValueAttribute(Attribute): 

+

40 KEY = "ID" 

+

41 

+

42 _keyValuePairs: Dict[str, str] 

+

43 

+

44 def __init__(self): 

+

45 super().__init__() 

+

46 

+

47 self._keyValuePairs = {} 

+

48 

+

49 def __getitem__(self, item: str) -> str: 

+

50 return self._keyValuePairs[item] 

+

51 

+

52 def __setitem__(self, key: str, value: str) -> None: 

+

53 self._keyValuePairs[key] = value 

+
+ + + diff --git a/coverage/d_bb657af29d23493a___init___py.html b/coverage/d_bb657af29d23493a___init___py.html new file mode 100644 index 00000000..e2e42b9c --- /dev/null +++ b/coverage/d_bb657af29d23493a___init___py.html @@ -0,0 +1,1952 @@ + + + + + Coverage for pyEDAA/ProjectModel/__init__.py: 73% + + + + + +
+
+

+ Coverage for pyEDAA/ProjectModel/__init__.py: + 73% +

+ +

+ 1064 statements   + + + + +

+

+ « prev     + ^ index     + » next +       + coverage.py v7.3.0, + created at 2023-08-24 21:52 +0000 +

+ +
+
+
+

1# ==================================================================================================================== # 

+

2# _____ ____ _ _ ____ _ _ __ __ _ _ # 

+

3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # 

+

4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # 

+

5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # 

+

6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # 

+

7# |_| |___/ |__/ # 

+

8# ==================================================================================================================== # 

+

9# Authors: # 

+

10# Patrick Lehmann # 

+

11# # 

+

12# License: # 

+

13# ==================================================================================================================== # 

+

14# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany # 

+

15# Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture # 

+

16# # 

+

17# Licensed under the Apache License, Version 2.0 (the "License"); # 

+

18# you may not use this file except in compliance with the License. # 

+

19# You may obtain a copy of the License at # 

+

20# # 

+

21# http://www.apache.org/licenses/LICENSE-2.0 # 

+

22# # 

+

23# Unless required by applicable law or agreed to in writing, software # 

+

24# distributed under the License is distributed on an "AS IS" BASIS, # 

+

25# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # 

+

26# See the License for the specific language governing permissions and # 

+

27# limitations under the License. # 

+

28# # 

+

29# SPDX-License-Identifier: Apache-2.0 # 

+

30# ==================================================================================================================== # 

+

31# 

+

32"""An abstract model of EDA tool projects.""" 

+

33__author__ = "Patrick Lehmann" 

+

34__email__ = "Paebbels@gmail.com" 

+

35__copyright__ = "2014-2023, Patrick Lehmann, Unai Martinez-Corral" 

+

36__license__ = "Apache License, Version 2.0" 

+

37__version__ = "0.5.0" 

+

38__keywords__ = ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"] 

+

39 

+

40from os.path import relpath as path_relpath 

+

41from pathlib import Path as pathlib_Path 

+

42from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any 

+

43 

+

44from pyTooling.Decorators import export 

+

45from pyTooling.MetaClasses import ExtendedType 

+

46from pyTooling.Graph import Graph, Vertex 

+

47from pySVModel import SystemVerilogVersion 

+

48from pyVHDLModel import VHDLVersion 

+

49from pySystemRDLModel import SystemRDLVersion 

+

50 

+

51 

+

52@export 

+

53class Attribute(metaclass=ExtendedType): 

+

54 KEY: str 

+

55 VALUE_TYPE: typing_Any 

+

56 

+

57 @staticmethod 

+

58 def resolve(obj: typing_Any, key: Type['Attribute']): 

+

59 if isinstance(obj, File): 59 ↛ 61line 59 didn't jump to line 61, because the condition on line 59 was never false

+

60 return obj._fileSet[key] 

+

61 elif isinstance(obj, FileSet): 

+

62 return obj._design[key] 

+

63 elif isinstance(obj, Design): 

+

64 return obj._project[key] 

+

65 else: 

+

66 raise Exception("Resolution error") 

+

67 

+

68 

+

69@export 

+

70class FileType(ExtendedType): 

+

71 """ 

+

72 A :term:`meta-class` to construct *FileType* classes. 

+

73 

+

74 Modifications done by this meta-class: 

+

75 * Register all classes of type :class:`FileType` or derived variants in a class field :attr:`FileType.FileTypes` in this meta-class. 

+

76 """ 

+

77 

+

78 FileTypes: Dict[str, 'FileType'] = {} #: Dictionary of all classes of type :class:`FileType` or derived variants 

+

79 Any: 'FileType' 

+

80 

+

81 def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs): 

+

82 super().__init__(name, bases, dictionary, **kwargs) 

+

83 cls.Any = cls 

+

84 

+

85 def __new__(cls, className, baseClasses, classMembers: Dict, *args, **kwargs): 

+

86 fileType = super().__new__(cls, className, baseClasses, classMembers, *args, **kwargs) 

+

87 cls.FileTypes[className] = fileType 

+

88 return fileType 

+

89 

+

90 def __getattr__(cls, item) -> 'FileType': 

+

91 if item[:2] != "__" and item[-2:] != "__": 

+

92 return cls.FileTypes[item] 

+

93 else: 

+

94 return super().__getattribute__(item) 

+

95 

+

96 def __contains__(cls, item) -> bool: 

+

97 return issubclass(item, cls) 

+

98 

+

99 

+

100@export 

+

101class File(metaclass=FileType, slots=True): 

+

102 """ 

+

103 A :term:`File` represents a file in a design. This :term:`base-class` is used 

+

104 for all derived file classes. 

+

105 

+

106 A file can be created standalone and later associated to a fileset, design and 

+

107 project. Or a fileset, design and/or project can be associated immediately 

+

108 while creating a file. 

+

109 

+

110 :arg path: Relative or absolute path to the file. 

+

111 :arg project: Project the file is associated with. 

+

112 :arg design: Design the file is associated with. 

+

113 :arg fileSet: Fileset the file is associated with. 

+

114 """ 

+

115 

+

116 _path: pathlib_Path 

+

117 _fileType: 'FileType' 

+

118 _project: Nullable['Project'] 

+

119 _design: Nullable['Design'] 

+

120 _fileSet: Nullable['FileSet'] 

+

121 _attributes: Dict[Type[Attribute], typing_Any] 

+

122 

+

123 def __init__( 

+

124 self, 

+

125 path: pathlib_Path, 

+

126 project: 'Project' = None, 

+

127 design: 'Design' = None, 

+

128 fileSet: 'FileSet' = None 

+

129 ): 

+

130 self._fileType = getattr(FileTypes, self.__class__.__name__) 

+

131 self._path = path 

+

132 if project is not None: 

+

133 self._project = project 

+

134 self._design = design 

+

135 if fileSet is not None: 135 ↛ 136line 135 didn't jump to line 136, because the condition on line 135 was never true

+

136 self.FileSet = fileSet 

+

137 elif design is not None: 

+

138 self._project = design._project 

+

139 self._design = design 

+

140 self.FileSet = design.DefaultFileSet if fileSet is None else fileSet 

+

141 elif fileSet is not None: 

+

142 design = fileSet._design 

+

143 if design is not None: 

+

144 self._project = design._project 

+

145 else: 

+

146 self._project = None 

+

147 self._design = design 

+

148 self.FileSet = fileSet 

+

149 else: 

+

150 self._project = None 

+

151 self._design = None 

+

152 self._fileSet = None 

+

153 

+

154 self._attributes = {} 

+

155 self._registerAttributes() 

+

156 

+

157 def _registerAttributes(self): 

+

158 pass 

+

159 

+

160 @property 

+

161 def FileType(self) -> 'FileType': 

+

162 """Read-only property to return the file type of this file.""" 

+

163 return self._fileType 

+

164 

+

165 @property 

+

166 def Path(self) -> pathlib_Path: 

+

167 """Read-only property returning the path of this file.""" 

+

168 return self._path 

+

169 

+

170 # TODO: setter? 

+

171 

+

172 @property 

+

173 def ResolvedPath(self) -> pathlib_Path: 

+

174 """Read-only property returning the resolved path of this file.""" 

+

175 if self._path.is_absolute(): 175 ↛ 176line 175 didn't jump to line 176, because the condition on line 175 was never true

+

176 return self._path.resolve() 

+

177 elif self._fileSet is not None: 177 ↛ 187line 177 didn't jump to line 187, because the condition on line 177 was never false

+

178 path = (self._fileSet.ResolvedPath / self._path).resolve() 

+

179 

+

180 if path.is_absolute(): 180 ↛ 184line 180 didn't jump to line 184, because the condition on line 180 was never false

+

181 return path 

+

182 else: 

+

183 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath 

+

184 return pathlib_Path(path_relpath(path, pathlib_Path.cwd())) 

+

185 else: 

+

186 # TODO: message and exception type 

+

187 raise Exception("") 

+

188 

+

189 @property 

+

190 def Project(self) -> Nullable['Project']: 

+

191 """Property setting or returning the project this file is used in.""" 

+

192 return self._project 

+

193 

+

194 @Project.setter 

+

195 def Project(self, value: 'Project') -> None: 

+

196 self._project = value 

+

197 

+

198 if self._fileSet is None: 198 ↛ exitline 198 didn't return from function 'Project', because the condition on line 198 was never false

+

199 self._project.DefaultDesign.DefaultFileSet.AddFile(self) 

+

200 

+

201 @property 

+

202 def Design(self) -> Nullable['Design']: 

+

203 """Property setting or returning the design this file is used in.""" 

+

204 return self._design 

+

205 

+

206 @Design.setter 

+

207 def Design(self, value: 'Design') -> None: 

+

208 self._design = value 

+

209 

+

210 if self._fileSet is None: 210 ↛ 213line 210 didn't jump to line 213, because the condition on line 210 was never false

+

211 self._design.DefaultFileSet.AddFile(self) 

+

212 

+

213 if self._project is None: 213 ↛ 215line 213 didn't jump to line 215, because the condition on line 213 was never false

+

214 self._project = value._project 

+

215 elif self._project is not value._project: 

+

216 raise Exception("The design's project is not identical to the already assigned project.") 

+

217 

+

218 @property 

+

219 def FileSet(self) -> Nullable['FileSet']: 

+

220 """Property setting or returning the fileset this file is used in.""" 

+

221 return self._fileSet 

+

222 

+

223 @FileSet.setter 

+

224 def FileSet(self, value: 'FileSet') -> None: 

+

225 self._fileSet = value 

+

226 value._files.append(self) 

+

227 

+

228 def Validate(self): 

+

229 """Validate this file.""" 

+

230 if self._path is None: 230 ↛ 231line 230 didn't jump to line 231, because the condition on line 230 was never true

+

231 raise Exception("Validation: File has no path.") 

+

232 try: 

+

233 path = self.ResolvedPath 

+

234 except Exception as ex: 

+

235 raise Exception(f"Validation: File '{self._path}' could not compute resolved path.") from ex 

+

236 if not path.exists(): 236 ↛ 237line 236 didn't jump to line 237, because the condition on line 236 was never true

+

237 raise Exception(f"Validation: File '{self._path}' (={path}) does not exist.") 

+

238 if not path.is_file(): 238 ↛ 239line 238 didn't jump to line 239, because the condition on line 238 was never true

+

239 raise Exception(f"Validation: File '{self._path}' (={path}) is not a file.") 

+

240 

+

241 if self._fileSet is None: 241 ↛ 242line 241 didn't jump to line 242, because the condition on line 241 was never true

+

242 raise Exception(f"Validation: File '{self._path}' has no fileset.") 

+

243 if self._design is None: 243 ↛ 244line 243 didn't jump to line 244, because the condition on line 243 was never true

+

244 raise Exception(f"Validation: File '{self._path}' has no design.") 

+

245 if self._project is None: 245 ↛ 246line 245 didn't jump to line 246, because the condition on line 245 was never true

+

246 raise Exception(f"Validation: File '{self._path}' has no project.") 

+

247 

+

248 def __len__(self) -> int: 

+

249 """ 

+

250 Returns number of attributes set on this file. 

+

251 

+

252 :returns: The number if attributes set on this file. 

+

253 """ 

+

254 return len(self._attributes) 

+

255 

+

256 def __getitem__(self, key: Type[Attribute]) -> Any: 

+

257 """Index access for returning attributes on this file. 

+

258 

+

259 :param key: The attribute type. 

+

260 :returns: The attribute's value. 

+

261 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

262 """ 

+

263 if not issubclass(key, Attribute): 263 ↛ 264line 263 didn't jump to line 264, because the condition on line 263 was never true

+

264 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

265 

+

266 try: 

+

267 return self._attributes[key] 

+

268 except KeyError: 

+

269 return key.resolve(self, key) 

+

270 

+

271 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: 

+

272 """ 

+

273 Index access for adding or setting attributes on this file. 

+

274 

+

275 :param key: The attribute type. 

+

276 :param value: The attributes value. 

+

277 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

278 """ 

+

279 if not issubclass(key, Attribute): 279 ↛ 280line 279 didn't jump to line 280, because the condition on line 279 was never true

+

280 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

281 

+

282 self._attributes[key] = value 

+

283 

+

284 def __delitem__(self, key: Type[Attribute]) -> None: 

+

285 """ 

+

286 Index access for deleting attributes on this file. 

+

287 

+

288 :param key: The attribute type. 

+

289 """ 

+

290 if not issubclass(key, Attribute): 

+

291 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

292 

+

293 del self._attributes[key] 

+

294 

+

295 def __str__(self) -> str: 

+

296 return f"{self._path}" 

+

297 

+

298 

+

299FileTypes = File 

+

300 

+

301 

+

302@export 

+

303class HumanReadableContent(metaclass=ExtendedType, mixin=True): 

+

304 """A file type representing human-readable contents.""" 

+

305 

+

306 

+

307@export 

+

308class XMLContent(HumanReadableContent, mixin=True): 

+

309 """A file type representing XML contents.""" 

+

310 

+

311 

+

312@export 

+

313class YAMLContent(HumanReadableContent, mixin=True): 

+

314 """A file type representing YAML contents.""" 

+

315 

+

316 

+

317@export 

+

318class JSONContent(HumanReadableContent, mixin=True): 

+

319 """A file type representing JSON contents.""" 

+

320 

+

321 

+

322@export 

+

323class INIContent(HumanReadableContent, mixin=True): 

+

324 """A file type representing INI contents.""" 

+

325 

+

326 

+

327@export 

+

328class TOMLContent(HumanReadableContent, mixin=True): 

+

329 """A file type representing TOML contents.""" 

+

330 

+

331 

+

332@export 

+

333class TCLContent(HumanReadableContent, mixin=True): 

+

334 """A file type representing content in TCL code.""" 

+

335 

+

336 

+

337@export 

+

338class SDCContent(TCLContent, mixin=True): 

+

339 """A file type representing contents as Synopsys Design Constraints (SDC).""" 

+

340 

+

341 

+

342@export 

+

343class PythonContent(HumanReadableContent, mixin=True): 

+

344 """A file type representing contents as Python source code.""" 

+

345 

+

346 

+

347@export 

+

348class TextFile(File, HumanReadableContent): 

+

349 """A text file (``*.txt``).""" 

+

350 

+

351 

+

352@export 

+

353class LogFile(File, HumanReadableContent): 

+

354 """A log file (``*.log``).""" 

+

355 

+

356 

+

357@export 

+

358class XMLFile(File, XMLContent): 

+

359 """An XML file (``*.xml``).""" 

+

360 

+

361 

+

362@export 

+

363class SourceFile(File): 

+

364 """Base-class of all source files.""" 

+

365 

+

366 

+

367@export 

+

368class HDLSourceFile(SourceFile): 

+

369 """Base-class of all HDL source files.""" 

+

370 

+

371 

+

372@export 

+

373class RDLSourceFile(SourceFile): 

+

374 """Base-class of all RDL source files.""" 

+

375 

+

376 

+

377@export 

+

378class NetlistFile(SourceFile): 

+

379 """Base-class of all netlist source files.""" 

+

380 

+

381 

+

382@export 

+

383class EDIFNetlistFile(NetlistFile): 

+

384 """Netlist file in EDIF (Electronic Design Interchange Format).""" 

+

385 

+

386 

+

387@export 

+

388class TCLSourceFile(SourceFile, TCLContent): 

+

389 """A TCL source file.""" 

+

390 

+

391 

+

392@export 

+

393class VHDLSourceFile(HDLSourceFile, HumanReadableContent): 

+

394 """ 

+

395 A VHDL source file (of any language version). 

+

396 

+

397 :arg path: Relative or absolute path to the file. 

+

398 :arg vhdlLibrary: VHDLLibrary this VHDL source file is associated wih. 

+

399 :arg vhdlVersion: VHDLVersion this VHDL source file is associated wih. 

+

400 :arg project: Project the file is associated with. 

+

401 :arg design: Design the file is associated with. 

+

402 :arg fileSet: Fileset the file is associated with. 

+

403 """ 

+

404 

+

405 _vhdlLibrary: Nullable['VHDLLibrary'] 

+

406 _vhdlVersion: VHDLVersion 

+

407 

+

408 def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: VHDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None): 

+

409 super().__init__(path, project, design, fileSet) 

+

410 

+

411 if isinstance(vhdlLibrary, str): 411 ↛ 412line 411 didn't jump to line 412, because the condition on line 411 was never true

+

412 if design is not None: 

+

413 try: 

+

414 vhdlLibrary = design.VHDLLibraries[vhdlLibrary] 

+

415 except KeyError as ex: 

+

416 raise Exception(f"VHDL library '{vhdlLibrary}' not found in design '{design.Name}'.") from ex 

+

417 elif project is not None: 

+

418 try: 

+

419 vhdlLibrary = project.DefaultDesign.VHDLLibraries[vhdlLibrary] 

+

420 except KeyError as ex: 

+

421 raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex 

+

422 else: 

+

423 raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.") 

+

424 elif isinstance(vhdlLibrary, VHDLLibrary): 

+

425 self._vhdlLibrary = vhdlLibrary 

+

426 vhdlLibrary.AddFile(self) 

+

427 elif vhdlLibrary is None: 427 ↛ 430line 427 didn't jump to line 430, because the condition on line 427 was never false

+

428 self._vhdlLibrary = None 

+

429 else: 

+

430 raise TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.") 

+

431 

+

432 self._vhdlVersion = vhdlVersion 

+

433 

+

434 def Validate(self) -> None: 

+

435 """Validate this VHDL source file.""" 

+

436 super().Validate() 

+

437 

+

438 try: 

+

439 _ = self.VHDLLibrary 

+

440 except Exception as ex: 

+

441 raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLLibrary assigned.") from ex 

+

442 try: 

+

443 _ = self.VHDLVersion 

+

444 except Exception as ex: 

+

445 raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLVersion assigned.") from ex 

+

446 

+

447 @property 

+

448 def VHDLLibrary(self) -> 'VHDLLibrary': 

+

449 """Property setting or returning the VHDL library this VHDL source file is used in.""" 

+

450 if self._vhdlLibrary is not None: 

+

451 return self._vhdlLibrary 

+

452 elif self._fileSet is not None: 

+

453 return self._fileSet.VHDLLibrary 

+

454 else: 

+

455 raise Exception("VHDLLibrary was neither set locally nor globally.") 

+

456 

+

457 @VHDLLibrary.setter 

+

458 def VHDLLibrary(self, value: 'VHDLLibrary') -> None: 

+

459 self._vhdlLibrary = value 

+

460 value._files.append(self) 

+

461 

+

462 @property 

+

463 def VHDLVersion(self) -> VHDLVersion: 

+

464 """Property setting or returning the VHDL version this VHDL source file is used in.""" 

+

465 if self._vhdlVersion is not None: 

+

466 return self._vhdlVersion 

+

467 elif self._fileSet is not None: 

+

468 return self._fileSet.VHDLVersion 

+

469 else: 

+

470 raise Exception("VHDLVersion was neither set locally nor globally.") 

+

471 

+

472 @VHDLVersion.setter 

+

473 def VHDLVersion(self, value: VHDLVersion) -> None: 

+

474 self._vhdlVersion = value 

+

475 

+

476 def __repr__(self) -> str: 

+

477 return f"<VHDL file: '{self.ResolvedPath}'; lib: '{self.VHDLLibrary}'; version: {self.VHDLVersion}>" 

+

478 

+

479 

+

480class VerilogMixIn(metaclass=ExtendedType, mixin=True): 

+

481 @property 

+

482 def VerilogVersion(self) -> SystemVerilogVersion: 

+

483 """Property setting or returning the Verilog version this Verilog source file is used in.""" 

+

484 if self._version is not None: 

+

485 return self._version 

+

486 elif self._fileSet is not None: 

+

487 return self._fileSet.VerilogVersion 

+

488 else: 

+

489 raise Exception("VerilogVersion was neither set locally nor globally.") 

+

490 

+

491 @VerilogVersion.setter 

+

492 def VerilogVersion(self, value: SystemVerilogVersion) -> None: 

+

493 self._version = value 

+

494 

+

495 

+

496class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True): 

+

497 @property 

+

498 def SVVersion(self) -> SystemVerilogVersion: 

+

499 """Property setting or returning the SystemVerilog version this SystemVerilog source file is used in.""" 

+

500 if self._version is not None: 

+

501 return self._version 

+

502 elif self._fileSet is not None: 

+

503 return self._fileSet.SVVersion 

+

504 else: 

+

505 raise Exception("SVVersion was neither set locally nor globally.") 

+

506 

+

507 @SVVersion.setter 

+

508 def SVVersion(self, value: SystemVerilogVersion) -> None: 

+

509 self._version = value 

+

510 

+

511 

+

512@export 

+

513class VerilogBaseFile(HDLSourceFile, HumanReadableContent): 

+

514 _version: SystemVerilogVersion 

+

515 

+

516 def __init__(self, path: pathlib_Path, version: SystemVerilogVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None): 

+

517 super().__init__(path, project, design, fileSet) 

+

518 

+

519 self._version = version 

+

520 

+

521 

+

522@export 

+

523class VerilogSourceFile(VerilogBaseFile, VerilogMixIn): 

+

524 """A Verilog source file (of any language version).""" 

+

525 

+

526 

+

527@export 

+

528class VerilogHeaderFile(VerilogBaseFile, VerilogMixIn): 

+

529 """A Verilog header file (of any language version).""" 

+

530 

+

531 

+

532@export 

+

533class SystemVerilogBaseFile(VerilogBaseFile): 

+

534 ... 

+

535 

+

536 

+

537@export 

+

538class SystemVerilogSourceFile(SystemVerilogBaseFile, SystemVerilogMixIn): 

+

539 """A SystemVerilog source file (of any language version).""" 

+

540 

+

541 

+

542@export 

+

543class SystemVerilogHeaderFile(SystemVerilogBaseFile, SystemVerilogMixIn): 

+

544 """A SystemVerilog header file (of any language version).""" 

+

545 

+

546 

+

547@export 

+

548class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent): 

+

549 """A SystemRDL source file (of any language version).""" 

+

550 

+

551 _srdlVersion: SystemRDLVersion 

+

552 

+

553 def __init__(self, path: pathlib_Path, srdlVersion: SystemRDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None): 

+

554 super().__init__(path, project, design, fileSet) 

+

555 

+

556 self._srdlVersion = srdlVersion 

+

557 

+

558 @property 

+

559 def SystemRDLVersion(self) -> SystemRDLVersion: 

+

560 """Property setting or returning the SystemRDL version this SystemRDL source file is used in.""" 

+

561 if self._srdlVersion is not None: 

+

562 return self._srdlVersion 

+

563 elif self._fileSet is not None: 

+

564 return self._fileSet.SRDLVersion 

+

565 else: 

+

566 raise Exception("SRDLVersion was neither set locally nor globally.") 

+

567 

+

568 @SystemRDLVersion.setter 

+

569 def SystemRDLVersion(self, value: SystemRDLVersion) -> None: 

+

570 self._srdlVersion = value 

+

571 

+

572 

+

573@export 

+

574class PythonSourceFile(SourceFile, PythonContent): 

+

575 """A Python source file.""" 

+

576 

+

577 

+

578# TODO: move to a Cocotb module 

+

579@export 

+

580class CocotbPythonFile(PythonSourceFile): 

+

581 """A Python source file used by Cocotb.""" 

+

582 

+

583 

+

584@export 

+

585class ConstraintFile(File, HumanReadableContent): 

+

586 """Base-class of all constraint files.""" 

+

587 

+

588 

+

589@export 

+

590class ProjectFile(File): 

+

591 """Base-class of all tool-specific project files.""" 

+

592 

+

593 

+

594@export 

+

595class CSourceFile(SourceFile): 

+

596 """Base-class of all ANSI-C source files.""" 

+

597 

+

598 

+

599@export 

+

600class CppSourceFile(SourceFile): 

+

601 """Base-class of all ANSI-C++ source files.""" 

+

602 

+

603 

+

604@export 

+

605class SettingFile(File): 

+

606 """Base-class of all tool-specific setting files.""" 

+

607 

+

608 

+

609@export 

+

610class SimulationAnalysisFile(File): 

+

611 """Base-class of all tool-specific analysis files.""" 

+

612 

+

613 

+

614@export 

+

615class SimulationElaborationFile(File): 

+

616 """Base-class of all tool-specific elaboration files.""" 

+

617 

+

618 

+

619@export 

+

620class SimulationStartFile(File): 

+

621 """Base-class of all tool-specific simulation start-up files.""" 

+

622 

+

623 

+

624@export 

+

625class SimulationRunFile(File): 

+

626 """Base-class of all tool-specific simulation run (execution) files.""" 

+

627 

+

628 

+

629@export 

+

630class WaveformConfigFile(File): 

+

631 """Base-class of all tool-specific waveform configuration files.""" 

+

632 

+

633 

+

634@export 

+

635class WaveformDatabaseFile(File): 

+

636 """Base-class of all tool-specific waveform database files.""" 

+

637 

+

638 

+

639@export 

+

640class WaveformExchangeFile(File): 

+

641 """Base-class of all tool-independent waveform exchange files.""" 

+

642 

+

643 

+

644@export 

+

645class FileSet(metaclass=ExtendedType, slots=True): 

+

646 """ 

+

647 A :term:`FileSet` represents a group of files. Filesets can have sub-filesets. 

+

648 

+

649 The order of insertion is preserved. A fileset can be created standalone and 

+

650 later associated to another fileset, design and/or project. Or a fileset, 

+

651 design and/or project can be associated immediately while creating the 

+

652 fileset. 

+

653 

+

654 :arg name: Name of this fileset. 

+

655 :arg topLevel: Name of the fileset's toplevel. 

+

656 :arg directory: Path of this fileset (absolute or relative to a parent fileset or design). 

+

657 :arg project: Project the file is associated with. 

+

658 :arg design: Design the file is associated with. 

+

659 :arg parent: Parent fileset if this fileset is nested. 

+

660 :arg vhdlLibrary: Default VHDL library for files in this fileset, if not specified for the file itself. 

+

661 :arg vhdlVersion: Default VHDL version for files in this fileset, if not specified for the file itself. 

+

662 :arg verilogVersion: Default Verilog version for files in this fileset, if not specified for the file itself. 

+

663 :arg svVersion: Default SystemVerilog version for files in this fileset, if not specified for the file itself. 

+

664 :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself. 

+

665 """ 

+

666 

+

667 _name: str 

+

668 _topLevel: Nullable[str] 

+

669 _project: Nullable['Project'] 

+

670 _design: Nullable['Design'] 

+

671 _directory: pathlib_Path 

+

672 _parent: Nullable['FileSet'] 

+

673 _fileSets: Dict[str, 'FileSet'] 

+

674 _files: List[File] 

+

675 _set: Set 

+

676 _attributes: Dict[Type[Attribute], typing_Any] 

+

677 _vhdlLibraries: Dict[str, 'VHDLLibrary'] 

+

678 _vhdlLibrary: 'VHDLLibrary' 

+

679 _vhdlVersion: VHDLVersion 

+

680 _verilogVersion: SystemVerilogVersion 

+

681 _svVersion: SystemVerilogVersion 

+

682 _srdlVersion: SystemRDLVersion 

+

683 

+

684 def __init__( 

+

685 self, 

+

686 name: str, 

+

687 topLevel: str = None, 

+

688 directory: pathlib_Path = pathlib_Path("."), 

+

689 project: 'Project' = None, 

+

690 design: 'Design' = None, 

+

691 parent: Nullable['FileSet'] = None, 

+

692 vhdlLibrary: Union[str, 'VHDLLibrary'] = None, 

+

693 vhdlVersion: VHDLVersion = None, 

+

694 verilogVersion: SystemVerilogVersion = None, 

+

695 svVersion: SystemVerilogVersion = None, 

+

696 srdlVersion: SystemRDLVersion = None 

+

697 ): 

+

698 self._name = name 

+

699 self._topLevel = topLevel 

+

700 if project is not None: 

+

701 self._project = project 

+

702 self._design = design if design is not None else project.DefaultDesign 

+

703 

+

704 elif design is not None: 

+

705 self._project = design._project 

+

706 self._design = design 

+

707 else: 

+

708 self._project = None 

+

709 self._design = None 

+

710 self._directory = directory 

+

711 self._parent = parent 

+

712 self._fileSets = {} 

+

713 self._files = [] 

+

714 self._set = set() 

+

715 

+

716 if design is not None: 

+

717 design._fileSets[name] = self 

+

718 

+

719 self._attributes = {} 

+

720 self._vhdlLibraries = {} 

+

721 

+

722 # TODO: handle if vhdlLibrary is a string 

+

723 self._vhdlLibrary = vhdlLibrary 

+

724 self._vhdlVersion = vhdlVersion 

+

725 self._verilogVersion = verilogVersion 

+

726 self._svVersion = svVersion 

+

727 self._srdlVersion = srdlVersion 

+

728 

+

729 @property 

+

730 def Name(self) -> str: 

+

731 """Property setting or returning the fileset's name.""" 

+

732 return self._name 

+

733 

+

734 @Name.setter 

+

735 def Name(self, value: str) -> None: 

+

736 self._name = value 

+

737 

+

738 @property 

+

739 def TopLevel(self) -> str: 

+

740 """Property setting or returning the fileset's toplevel.""" 

+

741 return self._topLevel 

+

742 

+

743 @TopLevel.setter 

+

744 def TopLevel(self, value: str) -> None: 

+

745 self._topLevel = value 

+

746 

+

747 @property 

+

748 def Project(self) -> Nullable['Project']: 

+

749 """Property setting or returning the project this fileset is used in.""" 

+

750 return self._project 

+

751 

+

752 @Project.setter 

+

753 def Project(self, value: 'Project') -> None: 

+

754 self._project = value 

+

755 

+

756 @property 

+

757 def Design(self) -> Nullable['Design']: 

+

758 """Property setting or returning the design this fileset is used in.""" 

+

759 if self._design is not None: 

+

760 return self._design 

+

761 elif self._parent is not None: 761 ↛ 762line 761 didn't jump to line 762, because the condition on line 761 was never true

+

762 return self._parent.Design 

+

763 else: 

+

764 return None 

+

765 # TODO: raise exception instead 

+

766 # QUESTION: how to handle if design and parent is set? 

+

767 

+

768 @Design.setter 

+

769 def Design(self, value: 'Design') -> None: 

+

770 self._design = value 

+

771 if self._project is None: 771 ↛ 773line 771 didn't jump to line 773, because the condition on line 771 was never false

+

772 self._project = value._project 

+

773 elif self._project is not value._project: 

+

774 raise Exception("The design's project is not identical to the already assigned project.") 

+

775 

+

776 @property 

+

777 def Directory(self) -> pathlib_Path: 

+

778 """Property setting or returning the directory this fileset is located in.""" 

+

779 return self._directory 

+

780 

+

781 @Directory.setter 

+

782 def Directory(self, value: pathlib_Path) -> None: 

+

783 self._directory = value 

+

784 

+

785 @property 

+

786 def ResolvedPath(self) -> pathlib_Path: 

+

787 """Read-only property returning the resolved path of this fileset.""" 

+

788 if self._directory.is_absolute(): 788 ↛ 789line 788 didn't jump to line 789, because the condition on line 788 was never true

+

789 return self._directory.resolve() 

+

790 else: 

+

791 if self._parent is not None: 791 ↛ 792line 791 didn't jump to line 792, because the condition on line 791 was never true

+

792 directory = self._parent.ResolvedPath 

+

793 elif self._design is not None: 793 ↛ 795line 793 didn't jump to line 795, because the condition on line 793 was never false

+

794 directory = self._design.ResolvedPath 

+

795 elif self._project is not None: 

+

796 directory = self._project.ResolvedPath 

+

797 else: 

+

798 # TODO: message and exception type 

+

799 raise Exception("") 

+

800 

+

801 directory = (directory / self._directory).resolve() 

+

802 if directory.is_absolute(): 802 ↛ 806line 802 didn't jump to line 806, because the condition on line 802 was never false

+

803 return directory 

+

804 else: 

+

805 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath 

+

806 return pathlib_Path(path_relpath(directory, pathlib_Path.cwd())) 

+

807 

+

808 @property 

+

809 def Parent(self) -> Nullable['FileSet']: 

+

810 """Property setting or returning the parent fileset this fileset is used in.""" 

+

811 return self._parent 

+

812 

+

813 @Parent.setter 

+

814 def Parent(self, value: 'FileSet') -> None: 

+

815 self._parent = value 

+

816 value._fileSets[self._name] = self 

+

817 # TODO: check it it already exists 

+

818 # QUESTION: make an Add fileset method? 

+

819 

+

820 @property 

+

821 def FileSets(self) -> Dict[str, 'FileSet']: 

+

822 """Read-only property returning the dictionary of sub-filesets.""" 

+

823 return self._fileSets 

+

824 

+

825 def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[bool, str, 'FileSet'] = None) -> Generator[File, None, None]: 

+

826 """ 

+

827 Method returning the files of this fileset. 

+

828 

+

829 :arg fileType: A filter for file types. Default: ``Any``. 

+

830 :arg fileSet: Specifies how to handle sub-filesets. 

+

831 """ 

+

832 if fileSet is False: 832 ↛ 833line 832 didn't jump to line 833, because the condition on line 832 was never true

+

833 for file in self._files: 

+

834 if file.FileType in fileType: 

+

835 yield file 

+

836 elif fileSet is None: 836 ↛ 844line 836 didn't jump to line 844, because the condition on line 836 was never false

+

837 for fileSet in self._fileSets.values(): 837 ↛ 838line 837 didn't jump to line 838, because the loop on line 837 never started

+

838 for file in fileSet.Files(fileType): 

+

839 yield file 

+

840 for file in self._files: 

+

841 if file.FileType in fileType: 

+

842 yield file 

+

843 else: 

+

844 if isinstance(fileSet, str): 

+

845 fileSetName = fileSet 

+

846 try: 

+

847 fileSet = self._fileSets[fileSetName] 

+

848 except KeyError as ex: 

+

849 raise Exception(f"Fileset {fileSetName} not bound to fileset {self.Name}.") from ex 

+

850 elif not isinstance(fileSet, FileSet): 

+

851 raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.") 

+

852 

+

853 for file in fileSet.Files(fileType): 

+

854 yield file 

+

855 

+

856 def AddFileSet(self, fileSet: "FileSet") -> None: 

+

857 """ 

+

858 Method to add a single sub-fileset to this fileset. 

+

859 

+

860 :arg fileSet: A fileset to add to this fileset as sub-fileset. 

+

861 """ 

+

862 if not isinstance(fileSet, FileSet): 862 ↛ 863line 862 didn't jump to line 863, because the condition on line 862 was never true

+

863 raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.") 

+

864 elif fileSet in self._fileSets: 864 ↛ 865line 864 didn't jump to line 865, because the condition on line 864 was never true

+

865 raise Exception("Sub-fileset already contains this fileset.") 

+

866 elif fileSet.Name in self._fileSets.keys(): 866 ↛ 867line 866 didn't jump to line 867, because the condition on line 866 was never true

+

867 raise Exception(f"Fileset already contains a sub-fileset named '{fileSet.Name}'.") 

+

868 

+

869 self._fileSets[fileSet.Name] = fileSet 

+

870 fileSet._parent = self 

+

871 

+

872 def AddFileSets(self, fileSets: Iterable["FileSet"]) -> None: 

+

873 """ 

+

874 Method to add a multiple sub-filesets to this fileset. 

+

875 

+

876 :arg fileSets: An iterable of filesets to add each to the fileset. 

+

877 """ 

+

878 for fileSet in fileSets: 

+

879 self.AddFileSet(fileSet) 

+

880 

+

881 @property 

+

882 def FileSetCount(self) -> int: 

+

883 """Returns number of file sets excl. sub-filesets.""" 

+

884 return len(self._fileSets) 

+

885 

+

886 @property 

+

887 def TotalFileSetCount(self) -> int: 

+

888 """Returns number of file sets incl. sub-filesets.""" 

+

889 fileSetCount = len(self._fileSets) 

+

890 for fileSet in self._fileSets.values(): 

+

891 fileSetCount += fileSet.TotalFileSetCount 

+

892 

+

893 return fileSetCount 

+

894 

+

895 def AddFile(self, file: File) -> None: 

+

896 """ 

+

897 Method to add a single file to this fileset. 

+

898 

+

899 :arg file: A file to add to this fileset. 

+

900 """ 

+

901 if not isinstance(file, File): 

+

902 raise TypeError("Parameter 'file' is not of type ProjectModel.File.") 

+

903 elif file._fileSet is not None: 

+

904 ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.") 

+

905 ex.add_note(f"A file can't be assigned to another fileset.") 

+

906 raise ex 

+

907 elif file in self._set: 907 ↛ 908line 907 didn't jump to line 908, because the condition on line 907 was never true

+

908 ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.") 

+

909 ex.add_note(f"A file can't be added twice to a fileset.") 

+

910 raise ex 

+

911 

+

912 self._files.append(file) 

+

913 self._set.add(file) 

+

914 file._fileSet = self 

+

915 

+

916 def AddFiles(self, files: Iterable[File]) -> None: 

+

917 """ 

+

918 Method to add a multiple files to this fileset. 

+

919 

+

920 :arg files: An iterable of files to add each to the fileset. 

+

921 """ 

+

922 for file in files: 

+

923 self.AddFile(file) 

+

924 

+

925 @property 

+

926 def FileCount(self) -> int: 

+

927 """Returns number of files excl. sub-filesets.""" 

+

928 return len(self._files) 

+

929 

+

930 @property 

+

931 def TotalFileCount(self) -> int: 

+

932 """Returns number of files incl. the files in sub-filesets.""" 

+

933 fileCount = len(self._files) 

+

934 for fileSet in self._fileSets.values(): 

+

935 fileCount += fileSet.FileCount 

+

936 

+

937 return fileCount 

+

938 

+

939 def Validate(self) -> None: 

+

940 """Validate this fileset.""" 

+

941 if self._name is None or self._name == "": 941 ↛ 942line 941 didn't jump to line 942, because the condition on line 941 was never true

+

942 raise Exception("Validation: FileSet has no name.") 

+

943 

+

944 if self._directory is None: 944 ↛ 945line 944 didn't jump to line 945, because the condition on line 944 was never true

+

945 raise Exception(f"Validation: FileSet '{self._name}' has no directory.") 

+

946 try: 

+

947 path = self.ResolvedPath 

+

948 except Exception as ex: 

+

949 raise Exception(f"Validation: FileSet '{self._name}' could not compute resolved path.") from ex 

+

950 if not path.exists(): 950 ↛ 951line 950 didn't jump to line 951, because the condition on line 950 was never true

+

951 raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' does not exist.") 

+

952 if not path.is_dir(): 952 ↛ 953line 952 didn't jump to line 953, because the condition on line 952 was never true

+

953 raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' is not a directory.") 

+

954 

+

955 if self._design is None: 955 ↛ 956line 955 didn't jump to line 956, because the condition on line 955 was never true

+

956 raise Exception(f"Validation: FileSet '{self._directory}' has no design.") 

+

957 if self._project is None: 957 ↛ 958line 957 didn't jump to line 958, because the condition on line 957 was never true

+

958 raise Exception(f"Validation: FileSet '{self._directory}' has no project.") 

+

959 

+

960 for fileSet in self._fileSets.values(): 960 ↛ 961line 960 didn't jump to line 961, because the loop on line 960 never started

+

961 fileSet.Validate() 

+

962 for file in self._files: 962 ↛ 963line 962 didn't jump to line 963, because the loop on line 962 never started

+

963 file.Validate() 

+

964 

+

965 def GetOrCreateVHDLLibrary(self, name) -> 'VHDLLibrary': 

+

966 if name in self._vhdlLibraries: 

+

967 return self._vhdlLibraries[name] 

+

968 elif name in self._design._vhdlLibraries: 

+

969 library = self._design._vhdlLibraries[name] 

+

970 self._vhdlLibraries[name] = library 

+

971 return library 

+

972 else: 

+

973 library = VHDLLibrary(name, design=self._design, vhdlVersion=self._vhdlVersion) 

+

974 self._vhdlLibraries[name] = library 

+

975 return library 

+

976 

+

977 @property 

+

978 def VHDLLibrary(self) -> 'VHDLLibrary': 

+

979 """Property setting or returning the VHDL library of this fileset.""" 

+

980 if self._vhdlLibrary is not None: 

+

981 return self._vhdlLibrary 

+

982 elif self._parent is not None: 982 ↛ 984line 982 didn't jump to line 984, because the condition on line 982 was never false

+

983 return self._parent.VHDLLibrary 

+

984 elif self._design is not None: 

+

985 return self._design.VHDLLibrary 

+

986 else: 

+

987 raise Exception("VHDLLibrary was neither set locally nor globally.") 

+

988 

+

989 @VHDLLibrary.setter 

+

990 def VHDLLibrary(self, value: 'VHDLLibrary') -> None: 

+

991 self._vhdlLibrary = value 

+

992 

+

993 @property 

+

994 def VHDLVersion(self) -> VHDLVersion: 

+

995 """Property setting or returning the VHDL version of this fileset.""" 

+

996 if self._vhdlVersion is not None: 

+

997 return self._vhdlVersion 

+

998 elif self._parent is not None: 

+

999 return self._parent.VHDLVersion 

+

1000 elif self._design is not None: 1000 ↛ 1003line 1000 didn't jump to line 1003, because the condition on line 1000 was never false

+

1001 return self._design.VHDLVersion 

+

1002 else: 

+

1003 raise Exception("VHDLVersion was neither set locally nor globally.") 

+

1004 

+

1005 @VHDLVersion.setter 

+

1006 def VHDLVersion(self, value: VHDLVersion) -> None: 

+

1007 self._vhdlVersion = value 

+

1008 

+

1009 @property 

+

1010 def VerilogVersion(self) -> SystemVerilogVersion: 

+

1011 """Property setting or returning the Verilog version of this fileset.""" 

+

1012 if self._verilogVersion is not None: 

+

1013 return self._verilogVersion 

+

1014 elif self._parent is not None: 

+

1015 return self._parent.VerilogVersion 

+

1016 elif self._design is not None: 1016 ↛ 1019line 1016 didn't jump to line 1019, because the condition on line 1016 was never false

+

1017 return self._design.VerilogVersion 

+

1018 else: 

+

1019 raise Exception("VerilogVersion was neither set locally nor globally.") 

+

1020 

+

1021 @VerilogVersion.setter 

+

1022 def VerilogVersion(self, value: SystemVerilogVersion) -> None: 

+

1023 self._verilogVersion = value 

+

1024 

+

1025 @property 

+

1026 def SVVersion(self) -> SystemVerilogVersion: 

+

1027 """Property setting or returning the SystemVerilog version of this fileset.""" 

+

1028 if self._svVersion is not None: 

+

1029 return self._svVersion 

+

1030 elif self._parent is not None: 

+

1031 return self._parent.SVVersion 

+

1032 elif self._design is not None: 1032 ↛ 1035line 1032 didn't jump to line 1035, because the condition on line 1032 was never false

+

1033 return self._design.SVVersion 

+

1034 else: 

+

1035 raise Exception("SVVersion was neither set locally nor globally.") 

+

1036 

+

1037 @SVVersion.setter 

+

1038 def SVVersion(self, value: SystemVerilogVersion) -> None: 

+

1039 self._svVersion = value 

+

1040 

+

1041 @property 

+

1042 def SRDLVersion(self) -> SystemRDLVersion: 

+

1043 if self._srdlVersion is not None: 

+

1044 return self._srdlVersion 

+

1045 elif self._parent is not None: 

+

1046 return self._parent.SRDLVersion 

+

1047 elif self._design is not None: 

+

1048 return self._design.SRDLVersion 

+

1049 else: 

+

1050 raise Exception("SRDLVersion was neither set locally nor globally.") 

+

1051 

+

1052 @SRDLVersion.setter 

+

1053 def SRDLVersion(self, value: SystemRDLVersion) -> None: 

+

1054 self._srdlVersion = value 

+

1055 

+

1056 def __len__(self) -> int: 

+

1057 """ 

+

1058 Returns number of attributes set on this fileset. 

+

1059 

+

1060 :returns: The number if attributes set on this fileset. 

+

1061 """ 

+

1062 return len(self._attributes) 

+

1063 

+

1064 def __getitem__(self, key: Type[Attribute]) -> Any: 

+

1065 """Index access for returning attributes on this fileset. 

+

1066 

+

1067 :param key: The attribute type. 

+

1068 :returns: The attribute's value. 

+

1069 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1070 """ 

+

1071 if not issubclass(key, Attribute): 1071 ↛ 1072line 1071 didn't jump to line 1072, because the condition on line 1071 was never true

+

1072 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1073 

+

1074 try: 

+

1075 return self._attributes[key] 

+

1076 except KeyError: 

+

1077 return key.resolve(self, key) 

+

1078 

+

1079 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: 

+

1080 """ 

+

1081 Index access for adding or setting attributes on this fileset. 

+

1082 

+

1083 :param key: The attribute type. 

+

1084 :param value: The attributes value. 

+

1085 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1086 """ 

+

1087 if not issubclass(key, Attribute): 1087 ↛ 1088line 1087 didn't jump to line 1088, because the condition on line 1087 was never true

+

1088 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1089 

+

1090 self._attributes[key] = value 

+

1091 

+

1092 def __delitem__(self, key: Type[Attribute]) -> None: 

+

1093 """ 

+

1094 Index access for deleting attributes on this fileset. 

+

1095 

+

1096 :param key: The attribute type. 

+

1097 """ 

+

1098 if not issubclass(key, Attribute): 1098 ↛ 1099line 1098 didn't jump to line 1099, because the condition on line 1098 was never true

+

1099 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1100 

+

1101 del self._attributes[key] 

+

1102 

+

1103 def __str__(self) -> str: 

+

1104 """Returns the fileset's name.""" 

+

1105 return self._name 

+

1106 

+

1107 

+

1108@export 

+

1109class VHDLLibrary(metaclass=ExtendedType, slots=True): 

+

1110 """ 

+

1111 A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library. 

+

1112 

+

1113 :arg name: The VHDL libraries' name. 

+

1114 :arg project: Project the VHDL library is associated with. 

+

1115 :arg design: Design the VHDL library is associated with. 

+

1116 :arg vhdlVersion: Default VHDL version for files in this VHDL library, if not specified for the file itself. 

+

1117 """ 

+

1118 

+

1119 _name: str 

+

1120 _project: Nullable['Project'] 

+

1121 _design: Nullable['Design'] 

+

1122 _files: List[File] 

+

1123 _vhdlVersion: VHDLVersion 

+

1124 

+

1125 _dependencyNode: Vertex 

+

1126 

+

1127 def __init__( 

+

1128 self, 

+

1129 name: str, 

+

1130 project: 'Project' = None, 

+

1131 design: 'Design' = None, 

+

1132 vhdlVersion: VHDLVersion = None 

+

1133 ): 

+

1134 self._name = name 

+

1135 if project is not None: 

+

1136 self._project = project 

+

1137 self._design = project._defaultDesign if design is None else design 

+

1138 self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph) 

+

1139 

+

1140 if name in self._design._vhdlLibraries: 1140 ↛ 1141line 1140 didn't jump to line 1141, because the condition on line 1140 was never true

+

1141 raise Exception(f"Library '{name}' already in design '{self._design.Name}'.") 

+

1142 else: 

+

1143 self._design._vhdlLibraries[name] = self 

+

1144 

+

1145 elif design is not None: 

+

1146 self._project = design._project 

+

1147 self._design = design 

+

1148 self._dependencyNode = Vertex(value=self, graph=design._vhdlLibraryDependencyGraph) 

+

1149 

+

1150 if name in design._vhdlLibraries: 1150 ↛ 1151line 1150 didn't jump to line 1151, because the condition on line 1150 was never true

+

1151 raise Exception(f"Library '{name}' already in design '{design.Name}'.") 

+

1152 else: 

+

1153 design._vhdlLibraries[name] = self 

+

1154 

+

1155 else: 

+

1156 self._project = None 

+

1157 self._design = None 

+

1158 self._dependencyNode = None 

+

1159 

+

1160 self._files = [] 

+

1161 self._vhdlVersion = vhdlVersion 

+

1162 

+

1163 @property 

+

1164 def Name(self) -> str: 

+

1165 return self._name 

+

1166 

+

1167 @property 

+

1168 def Project(self) -> Nullable['Project']: 

+

1169 """Property setting or returning the project this VHDL library is used in.""" 

+

1170 return self._project 

+

1171 

+

1172 @Project.setter 

+

1173 def Project(self, value: 'Project') -> None: 

+

1174 if not isinstance(value, Project): 1174 ↛ 1175line 1174 didn't jump to line 1175, because the condition on line 1174 was never true

+

1175 raise TypeError("Parameter 'value' is not of type 'Project'.") 

+

1176 

+

1177 if value is None: 1177 ↛ 1179line 1177 didn't jump to line 1179, because the condition on line 1177 was never true

+

1178 # TODO: unlink VHDLLibrary from project 

+

1179 self._project = None 

+

1180 else: 

+

1181 self._project = value 

+

1182 if self._design is None: 1182 ↛ exitline 1182 didn't return from function 'Project', because the condition on line 1182 was never false

+

1183 self._design = value._defaultDesign 

+

1184 

+

1185 @property 

+

1186 def Design(self) -> Nullable['Design']: 

+

1187 """Property setting or returning the design this VHDL library is used in.""" 

+

1188 return self._design 

+

1189 

+

1190 @Design.setter 

+

1191 def Design(self, value: 'Design') -> None: 

+

1192 if not isinstance(value, Design): 

+

1193 raise TypeError("Parameter 'value' is not of type 'Design'.") 

+

1194 

+

1195 if value is None: 

+

1196 # TODO: unlink VHDLLibrary from design 

+

1197 self._design = None 

+

1198 else: 

+

1199 if self._design is None: 

+

1200 self._design = value 

+

1201 self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph) 

+

1202 elif self._design is not value: 

+

1203 # TODO: move VHDLLibrary to other design 

+

1204 # TODO: create new vertex in dependency graph and remove vertex from old graph 

+

1205 self._design = value 

+

1206 else: 

+

1207 pass 

+

1208 

+

1209 if self._project is None: 

+

1210 self._project = value._project 

+

1211 elif self._project is not value._project: 

+

1212 raise Exception("The design's project is not identical to the already assigned project.") 

+

1213 

+

1214 @property 

+

1215 def Files(self) -> Generator[File, None, None]: 

+

1216 """Read-only property to return all files in this VHDL library.""" 

+

1217 for file in self._files: 

+

1218 yield file 

+

1219 

+

1220 @property 

+

1221 def VHDLVersion(self) -> VHDLVersion: 

+

1222 """Property setting or returning the VHDL version of this VHDL library.""" 

+

1223 if self._vhdlVersion is not None: 

+

1224 return self._vhdlVersion 

+

1225 elif self._design is not None: 1225 ↛ 1228line 1225 didn't jump to line 1228, because the condition on line 1225 was never false

+

1226 return self._design.VHDLVersion 

+

1227 else: 

+

1228 raise Exception("VHDLVersion is not set on VHDLLibrary nor parent object.") 

+

1229 

+

1230 @VHDLVersion.setter 

+

1231 def VHDLVersion(self, value: VHDLVersion) -> None: 

+

1232 self._vhdlVersion = value 

+

1233 

+

1234 def AddDependency(self, library: 'VHDLLibrary') -> None: 

+

1235 library.parent = self 

+

1236 

+

1237 def AddFile(self, vhdlFile: VHDLSourceFile) -> None: 

+

1238 if not isinstance(vhdlFile, VHDLSourceFile): 1238 ↛ 1239line 1238 didn't jump to line 1239, because the condition on line 1238 was never true

+

1239 raise TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.") 

+

1240 

+

1241 self._files.append(vhdlFile) 

+

1242 

+

1243 def AddFiles(self, vhdlFiles: Iterable[VHDLSourceFile]) -> None: 

+

1244 for vhdlFile in vhdlFiles: 

+

1245 if not isinstance(vhdlFile, VHDLSourceFile): 

+

1246 raise TypeError(f"Item '{vhdlFile}' in parameter 'vhdlFiles' is not a 'VHDLSourceFile'.") 

+

1247 

+

1248 self._files.append(vhdlFile) 

+

1249 

+

1250 @property 

+

1251 def FileCount(self) -> int: 

+

1252 """Returns number of files.""" 

+

1253 return len(self._files) 

+

1254 

+

1255 def __len__(self) -> int: 

+

1256 """ 

+

1257 Returns number of attributes set on this VHDL library. 

+

1258 

+

1259 :returns: The number if attributes set on this VHDL library. 

+

1260 """ 

+

1261 return len(self._attributes) 

+

1262 

+

1263 def __getitem__(self, key: Type[Attribute]) -> Any: 

+

1264 """Index access for returning attributes on this VHDL library. 

+

1265 

+

1266 :param key: The attribute type. 

+

1267 :returns: The attribute's value. 

+

1268 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1269 """ 

+

1270 if not issubclass(key, Attribute): 

+

1271 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1272 

+

1273 try: 

+

1274 return self._attributes[key] 

+

1275 except KeyError: 

+

1276 return key.resolve(self, key) 

+

1277 

+

1278 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: 

+

1279 """ 

+

1280 Index access for adding or setting attributes on this VHDL library. 

+

1281 

+

1282 :param key: The attribute type. 

+

1283 :param value: The attributes value. 

+

1284 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1285 """ 

+

1286 if not issubclass(key, Attribute): 

+

1287 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1288 

+

1289 self._attributes[key] = value 

+

1290 

+

1291 def __delitem__(self, key: Type[Attribute]) -> None: 

+

1292 """ 

+

1293 Index access for deleting attributes on this VHDL library. 

+

1294 

+

1295 :param key: The attribute type. 

+

1296 """ 

+

1297 if not issubclass(key, Attribute): 

+

1298 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1299 

+

1300 del self._attributes[key] 

+

1301 

+

1302 def __str__(self) -> str: 

+

1303 """Returns the VHDL library's name.""" 

+

1304 return self._name 

+

1305 

+

1306 

+

1307@export 

+

1308class Design(metaclass=ExtendedType, slots=True): 

+

1309 """ 

+

1310 A :term:`Design` represents a group of filesets and the source files therein. 

+

1311 

+

1312 Each design contains at least one fileset - the :term:`default fileset`. For 

+

1313 designs with VHDL source files, a independent `VHDLLibraries` overlay structure 

+

1314 exists. 

+

1315 

+

1316 :arg name: The design's name. 

+

1317 :arg topLevel: Name of the design's toplevel. 

+

1318 :arg directory: Path of this design (absolute or relative to the project). 

+

1319 :arg project: Project the design is associated with. 

+

1320 :arg vhdlVersion: Default VHDL version for files in this design, if not specified for the file itself. 

+

1321 :arg verilogVersion: Default Verilog version for files in this design, if not specified for the file itself. 

+

1322 :arg svVersion: Default SystemVerilog version for files in this design, if not specified for the file itself. 

+

1323 :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself. 

+

1324 """ 

+

1325 

+

1326 _name: str 

+

1327 _topLevel: Nullable[str] 

+

1328 _project: Nullable['Project'] 

+

1329 _directory: pathlib_Path 

+

1330 _fileSets: Dict[str, FileSet] 

+

1331 _defaultFileSet: Nullable[FileSet] 

+

1332 _attributes: Dict[Type[Attribute], typing_Any] 

+

1333 

+

1334 _vhdlLibraries: Dict[str, VHDLLibrary] 

+

1335 _vhdlVersion: VHDLVersion 

+

1336 _verilogVersion: SystemVerilogVersion 

+

1337 _svVersion: SystemVerilogVersion 

+

1338 _srdlVersion: SystemRDLVersion 

+

1339 _externalVHDLLibraries: List 

+

1340 

+

1341 _vhdlLibraryDependencyGraph: Graph 

+

1342 _fileDependencyGraph: Graph 

+

1343 

+

1344 def __init__( 

+

1345 self, 

+

1346 name: str, 

+

1347 topLevel: str = None, 

+

1348 directory: pathlib_Path = pathlib_Path("."), 

+

1349 project: 'Project' = None, 

+

1350 vhdlVersion: VHDLVersion = None, 

+

1351 verilogVersion: SystemVerilogVersion = None, 

+

1352 svVersion: SystemVerilogVersion = None, 

+

1353 srdlVersion: SystemRDLVersion = None 

+

1354 ): 

+

1355 self._name = name 

+

1356 self._topLevel = topLevel 

+

1357 self._project = project 

+

1358 if project is not None: 

+

1359 project._designs[name] = self 

+

1360 self._directory = directory 

+

1361 self._fileSets = {} 

+

1362 self._defaultFileSet = FileSet("default", project=project, design=self) 

+

1363 self._attributes = {} 

+

1364 self._vhdlLibraries = {} 

+

1365 self._vhdlVersion = vhdlVersion 

+

1366 self._verilogVersion = verilogVersion 

+

1367 self._svVersion = svVersion 

+

1368 self._srdlVersion = srdlVersion 

+

1369 self._externalVHDLLibraries = [] 

+

1370 

+

1371 self._vhdlLibraryDependencyGraph = Graph() 

+

1372 self._fileDependencyGraph = Graph() 

+

1373 

+

1374 @property 

+

1375 def Name(self) -> str: 

+

1376 """Property setting or returning the design's name.""" 

+

1377 return self._name 

+

1378 

+

1379 @Name.setter 

+

1380 def Name(self, value: str) -> None: 

+

1381 self._name = value 

+

1382 

+

1383 @property 

+

1384 def TopLevel(self) -> str: 

+

1385 """Property setting or returning the fileset's toplevel.""" 

+

1386 return self._topLevel 

+

1387 

+

1388 @TopLevel.setter 

+

1389 def TopLevel(self, value: str) -> None: 

+

1390 self._topLevel = value 

+

1391 

+

1392 @property 

+

1393 def Project(self) -> Nullable['Project']: 

+

1394 """Property setting or returning the project this design is used in.""" 

+

1395 return self._project 

+

1396 

+

1397 @Project.setter 

+

1398 def Project(self, value: 'Project') -> None: 

+

1399 self._project = value 

+

1400 

+

1401 @property 

+

1402 def Directory(self) -> pathlib_Path: 

+

1403 """Property setting or returning the directory this design is located in.""" 

+

1404 return self._directory 

+

1405 

+

1406 @Directory.setter 

+

1407 def Directory(self, value: pathlib_Path) -> None: 

+

1408 self._directory = value 

+

1409 

+

1410 @property 

+

1411 def ResolvedPath(self) -> pathlib_Path: 

+

1412 """Read-only property returning the resolved path of this fileset.""" 

+

1413 if self._directory.is_absolute(): 1413 ↛ 1414line 1413 didn't jump to line 1414, because the condition on line 1413 was never true

+

1414 return self._directory.resolve() 

+

1415 elif self._project is not None: 1415 ↛ 1425line 1415 didn't jump to line 1425, because the condition on line 1415 was never false

+

1416 path = (self._project.ResolvedPath / self._directory).resolve() 

+

1417 

+

1418 if path.is_absolute(): 1418 ↛ 1422line 1418 didn't jump to line 1422, because the condition on line 1418 was never false

+

1419 return path 

+

1420 else: 

+

1421 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath 

+

1422 return pathlib_Path(path_relpath(path, pathlib_Path.cwd())) 

+

1423 else: 

+

1424 # TODO: message and exception type 

+

1425 raise Exception("") 

+

1426 

+

1427 @property 

+

1428 def DefaultFileSet(self) -> FileSet: 

+

1429 """Property setting or returning the default fileset of this design.""" 

+

1430 return self._defaultFileSet 

+

1431 

+

1432 @DefaultFileSet.setter 

+

1433 def DefaultFileSet(self, value: Union[str, FileSet]) -> None: 

+

1434 if isinstance(value, str): 

+

1435 if value not in self._fileSets.keys(): 

+

1436 raise Exception(f"Fileset '{value}' is not in this design.") 

+

1437 

+

1438 self._defaultFileSet = self._fileSets[value] 

+

1439 elif isinstance(value, FileSet): 

+

1440 if value not in self.FileSets: 

+

1441 raise Exception(f"Fileset '{value}' is not associated to this design.") 

+

1442 

+

1443 self._defaultFileSet = value 

+

1444 else: 

+

1445 raise ValueError("Unsupported parameter type for 'value'.") 

+

1446 

+

1447 # TODO: return generator with another method 

+

1448 @property 

+

1449 def FileSets(self) -> Dict[str, FileSet]: 

+

1450 """Read-only property returning the dictionary of filesets.""" 

+

1451 return self._fileSets 

+

1452 

+

1453 def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]: 

+

1454 """ 

+

1455 Method returning the files of this design. 

+

1456 

+

1457 :arg fileType: A filter for file types. Default: ``Any``. 

+

1458 :arg fileSet: Specifies if all files from all filesets (``fileSet=None``) are files from a single fileset are returned. 

+

1459 """ 

+

1460 if fileSet is None: 

+

1461 for fileSet in self._fileSets.values(): 

+

1462 for file in fileSet.Files(fileType): 

+

1463 yield file 

+

1464 else: 

+

1465 if isinstance(fileSet, str): 1465 ↛ 1470line 1465 didn't jump to line 1470, because the condition on line 1465 was never false

+

1466 try: 

+

1467 fileSet = self._fileSets[fileSet] 

+

1468 except KeyError as ex: 

+

1469 raise Exception(f"Fileset {fileSet.Name} not bound to design {self.Name}.") from ex 

+

1470 elif not isinstance(fileSet, FileSet): 

+

1471 raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.") 

+

1472 

+

1473 for file in fileSet.Files(fileType): 

+

1474 yield file 

+

1475 

+

1476 def Validate(self) -> None: 

+

1477 """Validate this design.""" 

+

1478 if self._name is None or self._name == "": 1478 ↛ 1479line 1478 didn't jump to line 1479, because the condition on line 1478 was never true

+

1479 raise Exception("Validation: Design has no name.") 

+

1480 

+

1481 if self._directory is None: 1481 ↛ 1482line 1481 didn't jump to line 1482, because the condition on line 1481 was never true

+

1482 raise Exception(f"Validation: Design '{self._name}' has no directory.") 

+

1483 try: 

+

1484 path = self.ResolvedPath 

+

1485 except Exception as ex: 

+

1486 raise Exception(f"Validation: Design '{self._name}' could not compute resolved path.") from ex 

+

1487 if not path.exists(): 1487 ↛ 1488line 1487 didn't jump to line 1488, because the condition on line 1487 was never true

+

1488 raise Exception(f"Validation: Design '{self._name}'s directory '{path}' does not exist.") 

+

1489 if not path.is_dir(): 1489 ↛ 1490line 1489 didn't jump to line 1490, because the condition on line 1489 was never true

+

1490 raise Exception(f"Validation: Design '{self._name}'s directory '{path}' is not a directory.") 

+

1491 

+

1492 if len(self._fileSets) == 0: 1492 ↛ 1493line 1492 didn't jump to line 1493, because the condition on line 1492 was never true

+

1493 raise Exception(f"Validation: Design '{self._name}' has no fileset.") 

+

1494 try: 

+

1495 if self._defaultFileSet is not self._fileSets[self._defaultFileSet.Name]: 1495 ↛ 1496line 1495 didn't jump to line 1496, because the condition on line 1495 was never true

+

1496 raise Exception(f"Validation: Design '{self._name}'s default fileset is the same as listed in filesets.") 

+

1497 except KeyError as ex: 

+

1498 raise Exception(f"Validation: Design '{self._name}'s default fileset is not in list of filesets.") from ex 

+

1499 if self._project is None: 1499 ↛ 1500line 1499 didn't jump to line 1500, because the condition on line 1499 was never true

+

1500 raise Exception(f"Validation: Design '{self._path}' has no project.") 

+

1501 

+

1502 for fileSet in self._fileSets.values(): 

+

1503 fileSet.Validate() 

+

1504 

+

1505 @property 

+

1506 def VHDLLibraries(self) -> Dict[str, VHDLLibrary]: 

+

1507 return self._vhdlLibraries 

+

1508 

+

1509 @property 

+

1510 def VHDLVersion(self) -> VHDLVersion: 

+

1511 if self._vhdlVersion is not None: 

+

1512 return self._vhdlVersion 

+

1513 elif self._project is not None: 1513 ↛ 1516line 1513 didn't jump to line 1516, because the condition on line 1513 was never false

+

1514 return self._project.VHDLVersion 

+

1515 else: 

+

1516 raise Exception("VHDLVersion was neither set locally nor globally.") 

+

1517 

+

1518 @VHDLVersion.setter 

+

1519 def VHDLVersion(self, value: VHDLVersion) -> None: 

+

1520 self._vhdlVersion = value 

+

1521 

+

1522 @property 

+

1523 def VerilogVersion(self) -> SystemVerilogVersion: 

+

1524 if self._verilogVersion is not None: 

+

1525 return self._verilogVersion 

+

1526 elif self._project is not None: 1526 ↛ 1529line 1526 didn't jump to line 1529, because the condition on line 1526 was never false

+

1527 return self._project.VerilogVersion 

+

1528 else: 

+

1529 raise Exception("VerilogVersion was neither set locally nor globally.") 

+

1530 

+

1531 @VerilogVersion.setter 

+

1532 def VerilogVersion(self, value: SystemVerilogVersion) -> None: 

+

1533 self._verilogVersion = value 

+

1534 

+

1535 @property 

+

1536 def SVVersion(self) -> SystemVerilogVersion: 

+

1537 if self._svVersion is not None: 

+

1538 return self._svVersion 

+

1539 elif self._project is not None: 1539 ↛ 1542line 1539 didn't jump to line 1542, because the condition on line 1539 was never false

+

1540 return self._project.SVVersion 

+

1541 else: 

+

1542 raise Exception("SVVersion was neither set locally nor globally.") 

+

1543 

+

1544 @SVVersion.setter 

+

1545 def SVVersion(self, value: SystemVerilogVersion) -> None: 

+

1546 self._svVersion = value 

+

1547 

+

1548 @property 

+

1549 def SRDLVersion(self) -> SystemRDLVersion: 

+

1550 if self._srdlVersion is not None: 

+

1551 return self._srdlVersion 

+

1552 elif self._project is not None: 

+

1553 return self._project.SRDLVersion 

+

1554 else: 

+

1555 raise Exception("SRDLVersion was neither set locally nor globally.") 

+

1556 

+

1557 @SRDLVersion.setter 

+

1558 def SRDLVersion(self, value: SystemRDLVersion) -> None: 

+

1559 self._srdlVersion = value 

+

1560 

+

1561 @property 

+

1562 def ExternalVHDLLibraries(self) -> List: 

+

1563 return self._externalVHDLLibraries 

+

1564 

+

1565 def AddFileSet(self, fileSet: FileSet) -> None: 

+

1566 if not isinstance(fileSet, FileSet): 

+

1567 raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.") 

+

1568 elif fileSet in self._fileSets: 

+

1569 raise Exception("Design already contains this fileset.") 

+

1570 elif fileSet.Name in self._fileSets.keys(): 

+

1571 raise Exception(f"Design already contains a fileset named '{fileSet.Name}'.") 

+

1572 

+

1573 self._fileSets[fileSet.Name] = fileSet 

+

1574 fileSet.Design = self 

+

1575 fileSet._parent = self 

+

1576 

+

1577 def AddFileSets(self, fileSets: Iterable[FileSet]) -> None: 

+

1578 for fileSet in fileSets: 

+

1579 self.AddFileSet(fileSet) 

+

1580 

+

1581 @property 

+

1582 def FileSetCount(self) -> int: 

+

1583 """Returns number of file sets excl. sub-filesets.""" 

+

1584 return len(self._fileSets) 

+

1585 

+

1586 @property 

+

1587 def TotalFileSetCount(self) -> int: 

+

1588 """Returns number of file sets incl. sub-filesets.""" 

+

1589 fileSetCount = len(self._fileSets) 

+

1590 for fileSet in self._fileSets.values(): 

+

1591 fileSetCount += fileSet.TotalFileSetCount 

+

1592 

+

1593 return fileSetCount 

+

1594 

+

1595 def AddFile(self, file: File) -> None: 

+

1596 if file.FileSet is None: 1596 ↛ 1599line 1596 didn't jump to line 1599, because the condition on line 1596 was never false

+

1597 self._defaultFileSet.AddFile(file) 

+

1598 else: 

+

1599 raise ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}' and can't be assigned via Design to a default fileset.") 

+

1600 

+

1601 def AddFiles(self, files: Iterable[File]) -> None: 

+

1602 for file in files: 

+

1603 self.AddFile(file) 

+

1604 

+

1605 def AddVHDLLibrary(self, vhdlLibrary: VHDLLibrary) -> None: 

+

1606 if vhdlLibrary.Name in self._vhdlLibraries: 

+

1607 if self._vhdlLibraries[vhdlLibrary.Name] is vhdlLibrary: 

+

1608 raise Exception(f"The VHDLLibrary '{vhdlLibrary.Name}' was already added to the design.") 

+

1609 else: 

+

1610 raise Exception(f"A VHDLLibrary with same name ('{vhdlLibrary.Name}') already exists for this design.") 

+

1611 

+

1612 

+

1613 def __len__(self) -> int: 

+

1614 """ 

+

1615 Returns number of attributes set on this design. 

+

1616 

+

1617 :returns: The number if attributes set on this design. 

+

1618 """ 

+

1619 return len(self._attributes) 

+

1620 

+

1621 def __getitem__(self, key: Type[Attribute]) -> Any: 

+

1622 """Index access for returning attributes on this design. 

+

1623 

+

1624 :param key: The attribute type. 

+

1625 :returns: The attribute's value. 

+

1626 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1627 """ 

+

1628 if not issubclass(key, Attribute): 

+

1629 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1630 

+

1631 try: 

+

1632 return self._attributes[key] 

+

1633 except KeyError: 

+

1634 return key.resolve(self, key) 

+

1635 

+

1636 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: 

+

1637 """ 

+

1638 Index access for adding or setting attributes on this design. 

+

1639 

+

1640 :param key: The attribute type. 

+

1641 :param value: The attributes value. 

+

1642 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1643 """ 

+

1644 if not issubclass(key, Attribute): 

+

1645 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1646 

+

1647 self._attributes[key] = value 

+

1648 

+

1649 def __delitem__(self, key: Type[Attribute]) -> None: 

+

1650 """ 

+

1651 Index access for deleting attributes on this design. 

+

1652 

+

1653 :param key: The attribute type. 

+

1654 """ 

+

1655 if not issubclass(key, Attribute): 

+

1656 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1657 

+

1658 del self._attributes[key] 

+

1659 

+

1660 def __str__(self) -> str: 

+

1661 return self._name 

+

1662 

+

1663 

+

1664@export 

+

1665class Project(metaclass=ExtendedType, slots=True): 

+

1666 """ 

+

1667 A :term:`Project` represents a group of designs and the source files therein. 

+

1668 

+

1669 :arg name: The project's name. 

+

1670 :arg rootDirectory: Base-path to the project. 

+

1671 :arg vhdlVersion: Default VHDL version for files in this project, if not specified for the file itself. 

+

1672 :arg verilogVersion: Default Verilog version for files in this project, if not specified for the file itself. 

+

1673 :arg svVersion: Default SystemVerilog version for files in this project, if not specified for the file itself. 

+

1674 """ 

+

1675 

+

1676 _name: str 

+

1677 _rootDirectory: pathlib_Path 

+

1678 _designs: Dict[str, Design] 

+

1679 _defaultDesign: Design 

+

1680 _attributes: Dict[Type[Attribute], typing_Any] 

+

1681 

+

1682 _vhdlVersion: VHDLVersion 

+

1683 _verilogVersion: SystemVerilogVersion 

+

1684 _svVersion: SystemVerilogVersion 

+

1685 _srdlVersion: SystemRDLVersion 

+

1686 

+

1687 def __init__( 

+

1688 self, 

+

1689 name: str, 

+

1690 rootDirectory: pathlib_Path = pathlib_Path("."), 

+

1691 vhdlVersion: VHDLVersion = None, 

+

1692 verilogVersion: SystemVerilogVersion = None, 

+

1693 svVersion: SystemVerilogVersion = None 

+

1694 ): 

+

1695 self._name = name 

+

1696 self._rootDirectory = rootDirectory 

+

1697 self._designs = {} 

+

1698 self._defaultDesign = Design("default", project=self) 

+

1699 self._attributes = {} 

+

1700 self._vhdlVersion = vhdlVersion 

+

1701 self._verilogVersion = verilogVersion 

+

1702 self._svVersion = svVersion 

+

1703 

+

1704 @property 

+

1705 def Name(self) -> str: 

+

1706 """Property setting or returning the project's name.""" 

+

1707 return self._name 

+

1708 

+

1709 @property 

+

1710 def RootDirectory(self) -> pathlib_Path: 

+

1711 """Property setting or returning the root directory this project is located in.""" 

+

1712 return self._rootDirectory 

+

1713 

+

1714 @RootDirectory.setter 

+

1715 def RootDirectory(self, value: pathlib_Path) -> None: 

+

1716 self._rootDirectory = value 

+

1717 

+

1718 @property 

+

1719 def ResolvedPath(self) -> pathlib_Path: 

+

1720 """Read-only property returning the resolved path of this fileset.""" 

+

1721 path = self._rootDirectory.resolve() 

+

1722 if self._rootDirectory.is_absolute(): 

+

1723 return path 

+

1724 else: 

+

1725 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath 

+

1726 return pathlib_Path(path_relpath(path, pathlib_Path.cwd())) 

+

1727 

+

1728 # TODO: return generator with another method 

+

1729 @property 

+

1730 def Designs(self) -> Dict[str, Design]: 

+

1731 return self._designs 

+

1732 

+

1733 @property 

+

1734 def DefaultDesign(self) -> Design: 

+

1735 return self._defaultDesign 

+

1736 

+

1737 def Validate(self) -> None: 

+

1738 """Validate this project.""" 

+

1739 if self._name is None or self._name == "": 1739 ↛ 1740line 1739 didn't jump to line 1740, because the condition on line 1739 was never true

+

1740 raise Exception("Validation: Project has no name.") 

+

1741 

+

1742 if self._rootDirectory is None: 1742 ↛ 1743line 1742 didn't jump to line 1743, because the condition on line 1742 was never true

+

1743 raise Exception(f"Validation: Project '{self._name}' has no root directory.") 

+

1744 try: 

+

1745 path = self.ResolvedPath 

+

1746 except Exception as ex: 

+

1747 raise Exception(f"Validation: Project '{self._name}' could not compute resolved path.") from ex 

+

1748 if not path.exists(): 1748 ↛ 1749line 1748 didn't jump to line 1749, because the condition on line 1748 was never true

+

1749 raise Exception(f"Validation: Project '{self._name}'s directory '{path}' does not exist.") 

+

1750 if not path.is_dir(): 1750 ↛ 1751line 1750 didn't jump to line 1751, because the condition on line 1750 was never true

+

1751 raise Exception(f"Validation: Project '{self._name}'s directory '{path}' is not a directory.") 

+

1752 

+

1753 if len(self._designs) == 0: 1753 ↛ 1754line 1753 didn't jump to line 1754, because the condition on line 1753 was never true

+

1754 raise Exception(f"Validation: Project '{self._name}' has no design.") 

+

1755 try: 

+

1756 if self._defaultDesign is not self._designs[self._defaultDesign.Name]: 1756 ↛ 1757line 1756 didn't jump to line 1757, because the condition on line 1756 was never true

+

1757 raise Exception(f"Validation: Project '{self._name}'s default design is the same as listed in designs.") 

+

1758 except KeyError as ex: 

+

1759 raise Exception(f"Validation: Project '{self._name}'s default design is not in list of designs.") from ex 

+

1760 

+

1761 for design in self._designs.values(): 

+

1762 design.Validate() 

+

1763 

+

1764 @property 

+

1765 def DesignCount(self) -> int: 

+

1766 """Returns number of designs.""" 

+

1767 return len(self._designs) 

+

1768 

+

1769 @property 

+

1770 def VHDLVersion(self) -> VHDLVersion: 

+

1771 # TODO: check for None and return exception 

+

1772 return self._vhdlVersion 

+

1773 

+

1774 @VHDLVersion.setter 

+

1775 def VHDLVersion(self, value: VHDLVersion) -> None: 

+

1776 self._vhdlVersion = value 

+

1777 

+

1778 @property 

+

1779 def VerilogVersion(self) -> SystemVerilogVersion: 

+

1780 # TODO: check for None and return exception 

+

1781 return self._verilogVersion 

+

1782 

+

1783 @VerilogVersion.setter 

+

1784 def VerilogVersion(self, value: SystemVerilogVersion) -> None: 

+

1785 self._verilogVersion = value 

+

1786 

+

1787 @property 

+

1788 def SVVersion(self) -> SystemVerilogVersion: 

+

1789 # TODO: check for None and return exception 

+

1790 return self._svVersion 

+

1791 

+

1792 @SVVersion.setter 

+

1793 def SVVersion(self, value: SystemVerilogVersion) -> None: 

+

1794 self._svVersion = value 

+

1795 

+

1796 @property 

+

1797 def SRDLVersion(self) -> SystemRDLVersion: 

+

1798 # TODO: check for None and return exception 

+

1799 return self._srdlVersion 

+

1800 

+

1801 @SRDLVersion.setter 

+

1802 def SRDLVersion(self, value: SystemRDLVersion) -> None: 

+

1803 self._srdlVersion = value 

+

1804 

+

1805 def __len__(self) -> int: 

+

1806 """ 

+

1807 Returns number of attributes set on this project. 

+

1808 

+

1809 :returns: The number if attributes set on this project. 

+

1810 """ 

+

1811 return len(self._attributes) 

+

1812 

+

1813 def __getitem__(self, key: Type[Attribute]) -> Any: 

+

1814 """Index access for returning attributes on this project. 

+

1815 

+

1816 :param key: The attribute type. 

+

1817 :returns: The attribute's value. 

+

1818 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1819 """ 

+

1820 if not issubclass(key, Attribute): 

+

1821 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1822 

+

1823 try: 

+

1824 return self._attributes[key] 

+

1825 except KeyError: 

+

1826 return key.resolve(self, key) 

+

1827 

+

1828 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: 

+

1829 """ 

+

1830 Index access for adding or setting attributes on this project. 

+

1831 

+

1832 :param key: The attribute type. 

+

1833 :param value: The attributes value. 

+

1834 :raises TypeError: When parameter 'key' is not a subclass of Attribute. 

+

1835 """ 

+

1836 if not issubclass(key, Attribute): 

+

1837 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1838 

+

1839 self._attributes[key] = value 

+

1840 

+

1841 def __delitem__(self, key: Type[Attribute]) -> None: 

+

1842 """ 

+

1843 Index access for deleting attributes on this project. 

+

1844 

+

1845 :param key: The attribute type. 

+

1846 """ 

+

1847 if not issubclass(key, Attribute): 

+

1848 raise TypeError("Parameter 'key' is not an 'Attribute'.") 

+

1849 

+

1850 del self._attributes[key] 

+

1851 

+

1852 def __str__(self) -> str: 

+

1853 return self._name 

+
+ + + diff --git a/coverage/d_f31a6c1cb708999d_Vivado_py.html b/coverage/d_f31a6c1cb708999d_Vivado_py.html new file mode 100644 index 00000000..ab708519 --- /dev/null +++ b/coverage/d_f31a6c1cb708999d_Vivado_py.html @@ -0,0 +1,304 @@ + + + + + Coverage for pyEDAA/ProjectModel/Xilinx/Vivado.py: 88% + + + + + +
+
+

+ Coverage for pyEDAA/ProjectModel/Xilinx/Vivado.py: + 88% +

+ +

+ 121 statements   + + + + +

+

+ « prev     + ^ index     + » next +       + coverage.py v7.3.0, + created at 2023-08-24 21:52 +0000 +

+ +
+
+
+

1# ==================================================================================================================== # 

+

2# _____ ____ _ _ ____ _ _ __ __ _ _ # 

+

3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # 

+

4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # 

+

5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # 

+

6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # 

+

7# |_| |___/ |__/ # 

+

8# ==================================================================================================================== # 

+

9# Authors: # 

+

10# Patrick Lehmann # 

+

11# # 

+

12# License: # 

+

13# ==================================================================================================================== # 

+

14# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany # 

+

15# # 

+

16# Licensed under the Apache License, Version 2.0 (the "License"); # 

+

17# you may not use this file except in compliance with the License. # 

+

18# You may obtain a copy of the License at # 

+

19# # 

+

20# http://www.apache.org/licenses/LICENSE-2.0 # 

+

21# # 

+

22# Unless required by applicable law or agreed to in writing, software # 

+

23# distributed under the License is distributed on an "AS IS" BASIS, # 

+

24# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # 

+

25# See the License for the specific language governing permissions and # 

+

26# limitations under the License. # 

+

27# # 

+

28# SPDX-License-Identifier: Apache-2.0 # 

+

29# ==================================================================================================================== # 

+

30# 

+

31"""Specific file types and attributes for Xilinx Vivado.""" 

+

32from pathlib import Path 

+

33from typing import Iterable 

+

34 

+

35from xml.dom import minidom, Node 

+

36 

+

37from pyTooling.MetaClasses import ExtendedType 

+

38from pyVHDLModel import VHDLVersion 

+

39from pyTooling.Decorators import export 

+

40 

+

41from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design 

+

42from pyEDAA.ProjectModel import File as Model_File 

+

43from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile 

+

44from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile 

+

45from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile 

+

46 

+

47 

+

48@export 

+

49class UsedInAttribute(Attribute): 

+

50 KEY = "UsedIn" 

+

51 VALUE_TYPE = Iterable[str] 

+

52 

+

53 

+

54@export 

+

55class File(Model_File): 

+

56 pass 

+

57 

+

58 

+

59class VivadoFileMixIn(metaclass=ExtendedType, mixin=True): 

+

60 def _registerAttributes(self): 

+

61 self._attributes[UsedInAttribute] = [] 

+

62 

+

63 

+

64@export 

+

65class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn): 

+

66 def _registerAttributes(self): 

+

67 super()._registerAttributes() 

+

68 VivadoFileMixIn._registerAttributes(self) 

+

69 

+

70 

+

71@export 

+

72class VerilogSourceFile(Model_VerilogSourceFile): 

+

73 def _registerAttributes(self): 

+

74 super()._registerAttributes() 

+

75 VivadoFileMixIn._registerAttributes(self) 

+

76 

+

77 

+

78@export 

+

79class VHDLSourceFile(Model_VHDLSourceFile): 

+

80 def _registerAttributes(self): 

+

81 super()._registerAttributes() 

+

82 VivadoFileMixIn._registerAttributes(self) 

+

83 

+

84 

+

85@export 

+

86class VivadoProjectFile(ProjectFile, XMLContent): 

+

87 """A Vivado project file (``*.xpr``).""" 

+

88 

+

89 _xprProject: Project 

+

90 

+

91 def __init__( 

+

92 self, 

+

93 path: Path, 

+

94 project: Project = None, 

+

95 design: Design = None, 

+

96 fileSet: FileSet = None 

+

97 ): 

+

98 super().__init__(path, project, design, fileSet) 

+

99 

+

100 self._xprProject = None 

+

101 

+

102 @property 

+

103 def ProjectModel(self) -> Project: 

+

104 return self._xprProject 

+

105 

+

106 def Parse(self): 

+

107 if not self._path.exists(): 107 ↛ 108line 107 didn't jump to line 108, because the condition on line 107 was never true

+

108 raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.") 

+

109 

+

110 try: 

+

111 root = minidom.parse(str(self._path)).documentElement 

+

112 except Exception as ex: 

+

113 raise Exception(f"Couldn't open '{self._path!s}'.") from ex 

+

114 

+

115 self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent) 

+

116 self._ParseRootElement(root) 

+

117 

+

118 def _ParseRootElement(self, root): 

+

119 for rootNode in root.childNodes: 119 ↛ exitline 119 didn't return from function '_ParseRootElement', because the loop on line 119 didn't complete

+

120 if rootNode.nodeName == "FileSets": 

+

121 self._ParseFileSets(rootNode) 

+

122 break 

+

123 

+

124 def _ParseFileSets(self, filesetsNode): 

+

125 for fileSetsNode in filesetsNode.childNodes: 

+

126 if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet": 

+

127 self._ParseFileSet(fileSetsNode) 

+

128 

+

129 def _ParseFileSet(self, filesetNode): 

+

130 filesetName = filesetNode.getAttribute("Name") 

+

131 fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign) 

+

132 

+

133 for fileNode in filesetNode.childNodes: 

+

134 if fileNode.nodeType == Node.ELEMENT_NODE: 

+

135 if fileNode.tagName == "File": 

+

136 self._ParseFile(fileNode, fileset) 

+

137 elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config": 

+

138 self._ParseFileSetConfig(fileNode, fileset) 

+

139 

+

140 def _ParseFile(self, fileNode, fileset): 

+

141 croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "") 

+

142 filePath = Path(croppedPath) 

+

143 if filePath.suffix in (".vhd", ".vhdl"): 

+

144 self._ParseVHDLFile(fileNode, filePath, fileset) 

+

145 elif filePath.suffix == ".xdc": 145 ↛ 147line 145 didn't jump to line 147, because the condition on line 145 was never false

+

146 self._ParseXDCFile(fileNode, filePath, fileset) 

+

147 elif filePath.suffix == ".v": 

+

148 self._ParseVerilogFile(fileNode, filePath, fileset) 

+

149 elif filePath.suffix == ".xci": 

+

150 self._ParseXCIFile(fileNode, filePath, fileset) 

+

151 else: 

+

152 self._ParseDefaultFile(fileNode, filePath, fileset) 

+

153 

+

154 def _ParseVHDLFile(self, fileNode, path, fileset): 

+

155 vhdlFile = VHDLSourceFile(path) 

+

156 fileset.AddFile(vhdlFile) 

+

157 usedInAttr = vhdlFile[UsedInAttribute] 

+

158 

+

159 for childNode in fileNode.childNodes: 

+

160 if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo": 

+

161 if childNode.getAttribute("SFType") == "VHDL2008": 

+

162 vhdlFile.VHDLVersion = VHDLVersion.VHDL2008 

+

163 else: 

+

164 vhdlFile.VHDLVersion = VHDLVersion.VHDL93 

+

165 

+

166 for fileAttribute in childNode.childNodes: 

+

167 if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr": 

+

168 if fileAttribute.getAttribute("Name") == "Library": 

+

169 libraryName = fileAttribute.getAttribute("Val") 

+

170 vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName) 

+

171 elif fileAttribute.getAttribute("Val") == "UsedIn": 171 ↛ 172line 171 didn't jump to line 172, because the condition on line 171 was never true

+

172 usedInAttr.append(fileAttribute.getAttribute("Val")) 

+

173 

+

174 def _ParseDefaultFile(self, _, path, fileset): 

+

175 File(path, fileSet=fileset) 

+

176 

+

177 def _ParseXDCFile(self, _, path, fileset): 

+

178 XDCConstraintFile(path, fileSet=fileset) 

+

179 

+

180 def _ParseVerilogFile(self, _, path, fileset): 

+

181 VerilogSourceFile(path, fileSet=fileset) 

+

182 

+

183 def _ParseXCIFile(self, _, path, fileset): 

+

184 IPCoreInstantiationFile(path, fileSet=fileset) 

+

185 

+

186 def _ParseFileSetConfig(self, fileNode, fileset): 

+

187 for option in fileNode.childNodes: 

+

188 if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option": 

+

189 if option.getAttribute("Name") == "TopModule": 

+

190 fileset.TopLevel = option.getAttribute("Val") 

+

191 

+

192 

+

193@export 

+

194class XDCConstraintFile(ConstraintFile, SDCContent): 

+

195 """A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``).""" 

+

196 

+

197 

+

198@export 

+

199class IPCoreDescriptionFile(XMLFile): 

+

200 pass 

+

201 

+

202 

+

203@export 

+

204class IPCoreInstantiationFile(XMLFile): 

+

205 """A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``).""" 

+
+ + + diff --git a/coverage/d_f31a6c1cb708999d___init___py.html b/coverage/d_f31a6c1cb708999d___init___py.html new file mode 100644 index 00000000..f0df9b0a --- /dev/null +++ b/coverage/d_f31a6c1cb708999d___init___py.html @@ -0,0 +1,130 @@ + + + + + Coverage for pyEDAA/ProjectModel/Xilinx/__init__.py: 100% + + + + + +
+
+

+ Coverage for pyEDAA/ProjectModel/Xilinx/__init__.py: + 100% +

+ +

+ 1 statements   + + + + +

+

+ « prev     + ^ index     + » next +       + coverage.py v7.3.0, + created at 2023-08-24 21:52 +0000 +

+ +
+
+
+

1# ==================================================================================================================== # 

+

2# _____ ____ _ _ ____ _ _ __ __ _ _ # 

+

3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # 

+

4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # 

+

5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # 

+

6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # 

+

7# |_| |___/ |__/ # 

+

8# ==================================================================================================================== # 

+

9# Authors: # 

+

10# Patrick Lehmann # 

+

11# # 

+

12# License: # 

+

13# ==================================================================================================================== # 

+

14# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany # 

+

15# # 

+

16# Licensed under the Apache License, Version 2.0 (the "License"); # 

+

17# you may not use this file except in compliance with the License. # 

+

18# You may obtain a copy of the License at # 

+

19# # 

+

20# http://www.apache.org/licenses/LICENSE-2.0 # 

+

21# # 

+

22# Unless required by applicable law or agreed to in writing, software # 

+

23# distributed under the License is distributed on an "AS IS" BASIS, # 

+

24# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # 

+

25# See the License for the specific language governing permissions and # 

+

26# limitations under the License. # 

+

27# # 

+

28# SPDX-License-Identifier: Apache-2.0 # 

+

29# ==================================================================================================================== # 

+

30# 

+

31"""A vendor specific package for Xilinx.""" 

+
+ + + diff --git a/coverage/favicon_32.png b/coverage/favicon_32.png new file mode 100644 index 00000000..8649f047 Binary files /dev/null and b/coverage/favicon_32.png differ diff --git a/coverage/index.html b/coverage/index.html new file mode 100644 index 00000000..62b52e7a --- /dev/null +++ b/coverage/index.html @@ -0,0 +1,137 @@ + + + + + Code Coverage of pyEDAA.ProjectModel + + + + + +
+
+

Code Coverage of pyEDAA.ProjectModel: + 75% +

+ +
+ +
+

+ coverage.py v7.3.0, + created at 2023-08-24 21:52 +0000 +

+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Modulestatementsmissingexcludedbranchespartialcoverage
pyEDAA/ProjectModel/Attributes.py150020100%
pyEDAA/ProjectModel/Xilinx/Vivado.py12114066488%
pyEDAA/ProjectModel/Xilinx/__init__.py10000100%
pyEDAA/ProjectModel/__init__.py106427106387473%
Total120128507067875%
+

+ No items found using the specified filter. +

+
+ + + diff --git a/coverage/keybd_closed.png b/coverage/keybd_closed.png new file mode 100644 index 00000000..ba119c47 Binary files /dev/null and b/coverage/keybd_closed.png differ diff --git a/coverage/keybd_open.png b/coverage/keybd_open.png new file mode 100644 index 00000000..a8bac6c9 Binary files /dev/null and b/coverage/keybd_open.png differ diff --git a/coverage/status.json b/coverage/status.json new file mode 100644 index 00000000..d5efff6b --- /dev/null +++ b/coverage/status.json @@ -0,0 +1 @@ +{"format":2,"version":"7.3.0","globals":"4f6d1111ff6046ef71afc1c84401bcc0","files":{"d_bb657af29d23493a_Attributes_py":{"hash":"2d109a6f130898ae14d80216b05d4985","index":{"nums":[0,1,15,0,0,2,0,0],"html_filename":"d_bb657af29d23493a_Attributes_py.html","relative_filename":"pyEDAA/ProjectModel/Attributes.py"}},"d_f31a6c1cb708999d_Vivado_py":{"hash":"af20e5045bf37245dd542f7cd81670c7","index":{"nums":[0,1,121,0,14,66,4,8],"html_filename":"d_f31a6c1cb708999d_Vivado_py.html","relative_filename":"pyEDAA/ProjectModel/Xilinx/Vivado.py"}},"d_f31a6c1cb708999d___init___py":{"hash":"c6180f9a62d25d25641f0fd1e83c025b","index":{"nums":[0,1,1,0,0,0,0,0],"html_filename":"d_f31a6c1cb708999d___init___py.html","relative_filename":"pyEDAA/ProjectModel/Xilinx/__init__.py"}},"d_bb657af29d23493a___init___py":{"hash":"aa2e16bc4c746c41931c33d94589563e","index":{"nums":[0,1,1064,0,271,638,74,184],"html_filename":"d_bb657af29d23493a___init___py.html","relative_filename":"pyEDAA/ProjectModel/__init__.py"}}}} \ No newline at end of file diff --git a/coverage/style.css b/coverage/style.css new file mode 100644 index 00000000..11b24c4e --- /dev/null +++ b/coverage/style.css @@ -0,0 +1,309 @@ +@charset "UTF-8"; +/* Licensed under the Apache License: http://www.apache.org/licenses/LICENSE-2.0 */ +/* For details: https://github.com/nedbat/coveragepy/blob/master/NOTICE.txt */ +/* Don't edit this .css file. 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} } + +#index th[aria-sort="ascending"]::after { font-family: sans-serif; content: " ↑"; } + +#index th[aria-sort="descending"]::after { font-family: sans-serif; content: " ↓"; } + +#index td.name a { text-decoration: none; color: inherit; } + +#index tr.total td, #index tr.total_dynamic td { font-weight: bold; border-top: 1px solid #ccc; border-bottom: none; } + +#index tr.file:hover { background: #eee; } + +@media (prefers-color-scheme: dark) { #index tr.file:hover { background: #333; } } + +#index tr.file:hover td.name { text-decoration: underline; color: inherit; } + +#scroll_marker { position: fixed; z-index: 3; right: 0; top: 0; width: 16px; height: 100%; background: #fff; border-left: 1px solid #eee; will-change: transform; } + +@media (prefers-color-scheme: dark) { #scroll_marker { background: #1e1e1e; } } + +@media (prefers-color-scheme: dark) { #scroll_marker { border-color: #333; } } + +#scroll_marker .marker { background: #ccc; position: absolute; min-height: 3px; width: 100%; } + +@media (prefers-color-scheme: dark) { #scroll_marker .marker { background: #444; } } diff --git a/genindex.html b/genindex.html new file mode 100644 index 00000000..de957466 --- /dev/null +++ b/genindex.html @@ -0,0 +1,715 @@ + + + + + + Index — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ + +

Index

+ +
+ _ + | A + | B + | D + | F + | H + | I + | J + | K + | L + | M + | N + | P + | R + | S + | T + | U + | V + | X + | Y + +
+

_

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+ +

A

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F

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+ + +
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+ + +
+ +

L

+ + +
+ +

M

+ + + +
+ +

N

+ + +
+ +

P

+ + + +
    +
  • + pyEDAA.ProjectModel.MentorGraphics + +
    • +
  • + pyEDAA.ProjectModel.MentorGraphics.ModelSim + +
    • +
  • + pyEDAA.ProjectModel.MentorGraphics.QuestaSim + +
    • +
  • + pyEDAA.ProjectModel.OSVVM + +
    • +
  • + pyEDAA.ProjectModel.Verilog + +
    • +
  • + pyEDAA.ProjectModel.VHDL + +
    • +
  • + pyEDAA.ProjectModel.Xilinx + +
    • +
  • + pyEDAA.ProjectModel.Xilinx.ISE + +
    • +
  • + pyEDAA.ProjectModel.Xilinx.Vivado + +
    • +
  • PythonContent (class in pyEDAA.ProjectModel) +
    • +
+ +

R

+ + + +
+ +

S

+ + + +
+ +

T

+ + + +
+ +

U

+ + +
+ +

V

+ + + +
+ +

X

+ + +
+ +

Y

+ + +
+ + + +
+
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+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/index.html b/index.html new file mode 100644 index 00000000..0e937523 --- /dev/null +++ b/index.html @@ -0,0 +1,202 @@ + + + + + + + The pyEDAA.ProjectModel Documentation — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+
+ + _images/logo_on_light.svg +
+
Sourcecode on GitHub Code license Documentation - Read Now! Documentation License Documentation License
+
PyPI - Tag PyPI - Status PyPI - Python Version
+
GitHub Workflow - Build and Test Status Libraries.io status for latest release Codacy - Quality Codacy - Line Coverage Codecov - Branch Coverage
+
+
+
+

The pyEDAA.ProjectModel Documentation

+

An abstract model of HDL design projects and EDA tooling.

+
+

Main Goals

+

This package provides a unified abstract project model for HDL designs and EDA tools. +Third-party frameworks can derive own classes and implement additional logic to create a concrete project model for +their tools.

+

Frameworks consuming this model can build higher level features and services on top of such a model, while supporting +multiple input sources.

+
+
+

Use Cases

+ +
+
+

News

+
+

Oct. 2021 - Reading *.xpr and *.pro Files

+
+
    +

  • Xilinx Vivado’s *.xpr and OSVVM’s *.pro files can now be read.

    • +

  • Filesets can be nested.

    • +

  • The dataset can be validated.

    • +
+
+

Sep. 2021 - Extracted ProjectModel from pyIPCMI

+
+
    +

  • The project model has been extracted from pyIPCMI.

    • +

  • ProjectModel became first citizen of EDA² and got integrated into the pyEDAA namespace at PyPI.

    • +
+
+
+

Contributors

+ +
+
+

License

+

This Python package (source code) is licensed under Apache License 2.0.
+The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).

+
+

This document was generated on 24.Aug 2023 - 21:52.

+
+
+
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+
+
+
+
+
+
+
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/objects.inv b/objects.inv new file mode 100644 index 00000000..c702f35c Binary files /dev/null and b/objects.inv differ diff --git a/py-modindex.html b/py-modindex.html new file mode 100644 index 00000000..b388e82e --- /dev/null +++ b/py-modindex.html @@ -0,0 +1,227 @@ + + + + + + Python Module Index — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + + +
+ + +
+ +
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+ + +
+ +
+
+ +
+
+ + +

Python Module Index

+ +
+ p +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 
+ p
+ pyEDAA +
    + pyEDAA.ProjectModel +
    + pyEDAA.ProjectModel.Altera +
    + pyEDAA.ProjectModel.Altera.Quartus +
    + pyEDAA.ProjectModel.Attributes +
    + pyEDAA.ProjectModel.GHDL +
    + pyEDAA.ProjectModel.Intel +
    + pyEDAA.ProjectModel.Intel.QuartusPrime +
    + pyEDAA.ProjectModel.MentorGraphics +
    + pyEDAA.ProjectModel.MentorGraphics.ModelSim +
    + pyEDAA.ProjectModel.MentorGraphics.QuestaSim +
    + pyEDAA.ProjectModel.OSVVM +
    + pyEDAA.ProjectModel.Verilog +
    + pyEDAA.ProjectModel.VHDL +
    + pyEDAA.ProjectModel.Xilinx +
    + pyEDAA.ProjectModel.Xilinx.ISE +
    + pyEDAA.ProjectModel.Xilinx.Vivado +
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/index.html b/pyEDAA.ProjectModel/index.html new file mode 100644 index 00000000..6a4afa6c --- /dev/null +++ b/pyEDAA.ProjectModel/index.html @@ -0,0 +1,300 @@ + + + + + + + Python Class Reference — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
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+ + +
+ +
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+ +
+
+ +
+

Python Class Reference

+

Reference of all packages and modules:

+
+ +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus.html new file mode 100644 index 00000000..c1476ef2 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus.html @@ -0,0 +1,184 @@ + + + + + + + pyEDAA.ProjectModel.Altera.Quartus — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
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+ + +
+ +
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+ +
+
+ +
+

pyEDAA.ProjectModel.Altera.Quartus

+

Classes

+
    +

  • QuartusProjectFile: +A Quartus project file (*.qpf).

    • +

  • SDCConstraintFile: +A Quartus constraint file (Synopsys Design Constraints; *.sdc).

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.html new file mode 100644 index 00000000..11bf1a43 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.html @@ -0,0 +1,182 @@ + + + + + + + pyEDAA.ProjectModel.Altera — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
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+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Altera

+

Submodules

+
+ +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes.html new file mode 100644 index 00000000..648cb093 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes.html @@ -0,0 +1,194 @@ + + + + + + + pyEDAA.ProjectModel.Attributes — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
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+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Attributes

+

Classes

+ +
+
+class pyEDAA.ProjectModel.Attributes.KeyValueAttribute[source]
+

Inheritance

+
+

Inheritance diagram of KeyValueAttribute

+
+
+__init__()[source]
+
+ +
+ +
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL.html new file mode 100644 index 00000000..d275f237 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL.html @@ -0,0 +1,178 @@ + + + + + + + pyEDAA.ProjectModel.GHDL — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.GHDL

+

Classes

+
    +

  • GHDLWaveformFile: +GHDL’s waveform file (*.ghw) supporting VHDL and Verilog simulation results.

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime.html new file mode 100644 index 00000000..f26a98a9 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime.html @@ -0,0 +1,184 @@ + + + + + + + pyEDAA.ProjectModel.Intel.QuartusPrime — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Intel.QuartusPrime

+

Classes

+
    +

  • QuartusProjectFile: +A Quartus project file (*.qpf).

    • +

  • SDCConstraintFile: +A Quartus constraint file (Synopsys Design Constraints; *.sdc).

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.html new file mode 100644 index 00000000..725ce662 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.html @@ -0,0 +1,182 @@ + + + + + + + pyEDAA.ProjectModel.Intel — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Intel

+

Submodules

+
+ +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.ModelSim.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.ModelSim.html new file mode 100644 index 00000000..26155f51 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.ModelSim.html @@ -0,0 +1,187 @@ + + + + + + + pyEDAA.ProjectModel.MentorGraphics.ModelSim — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.MentorGraphics.ModelSim

+

Classes

+
    +

  • ModelSimProjectFile: +Base-class of all tool-specific project files.

    • +

  • ModelSimINIFile: +Base-class of all tool-specific setting files.

    • +

  • WaveDoFile: +Base-class of all tool-specific waveform configuration files.

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.QuestaSim.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.QuestaSim.html new file mode 100644 index 00000000..64f8fc2b --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.QuestaSim.html @@ -0,0 +1,187 @@ + + + + + + + pyEDAA.ProjectModel.MentorGraphics.QuestaSim — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.MentorGraphics.QuestaSim

+

Classes

+
    +

  • ModelSimProjectFile: +Base-class of all tool-specific project files.

    • +

  • ModelSimINIFile: +Base-class of all tool-specific setting files.

    • +

  • WaveDoFile: +Base-class of all tool-specific waveform configuration files.

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.html new file mode 100644 index 00000000..4f2fd312 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics.html @@ -0,0 +1,184 @@ + + + + + + + pyEDAA.ProjectModel.MentorGraphics — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.MentorGraphics

+

Submodules

+
+ +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.OSVVM.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.OSVVM.html new file mode 100644 index 00000000..b7a40571 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.OSVVM.html @@ -0,0 +1,178 @@ + + + + + + + pyEDAA.ProjectModel.OSVVM — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.OSVVM

+

Classes

+
    +

  • OSVVMProjectFile: +An OSVVM project file (*.pro).

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.VHDL.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.VHDL.html new file mode 100644 index 00000000..7e36000f --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.VHDL.html @@ -0,0 +1,173 @@ + + + + + + + pyEDAA.ProjectModel.VHDL — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.VHDL

+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Verilog.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Verilog.html new file mode 100644 index 00000000..047e0ab9 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Verilog.html @@ -0,0 +1,178 @@ + + + + + + + pyEDAA.ProjectModel.Verilog — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Verilog

+

Classes

+
    +

  • ValueChangeDumpFile: +Verilog’s waveform file (*.vcd) for exchanging value changes as defined by IEEE Std. 1364.

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.ISE.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.ISE.html new file mode 100644 index 00000000..bfa31405 --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.ISE.html @@ -0,0 +1,185 @@ + + + + + + + pyEDAA.ProjectModel.Xilinx.ISE — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Xilinx.ISE

+

Classes

+
    +

  • ISEProjectFile: +Base-class of all tool-specific project files.

    • +

  • UCFConstraintFile: +Base-class of all constraint files.

    • +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.Vivado.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.Vivado.html new file mode 100644 index 00000000..e9923a1b --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.Vivado.html @@ -0,0 +1,207 @@ + + + + + + + pyEDAA.ProjectModel.Xilinx.Vivado — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Xilinx.Vivado

+

Classes

+
    +

  • UsedInAttribute: +Undocumented.

    • +

  • File: +A File represents a file in a design. This base-class is used

    • +

  • ConstraintFile: +Base-class of all constraint files.

    • +

  • VerilogSourceFile: +A Verilog source file (of any language version).

    • +

  • VHDLSourceFile: +A VHDL source file (of any language version).

    • +

  • VivadoProjectFile: +A Vivado project file (*.xpr).

    • +

  • XDCConstraintFile: +A Vivado constraint file (Xilinx Design Constraints; *.xdc).

    • +

  • IPCoreDescriptionFile: +An XML file (*.xml).

    • +

  • IPCoreInstantiationFile: +A Vivado IP core instantiation file (Xilinx IPCore Instance; *.xci).

    • +
+
+
+class pyEDAA.ProjectModel.Xilinx.Vivado.UsedInAttribute[source]
+

Inheritance

+
+

Inheritance diagram of UsedInAttribute

+
+ +
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.html new file mode 100644 index 00000000..a67eb8aa --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.Xilinx.html @@ -0,0 +1,187 @@ + + + + + + + pyEDAA.ProjectModel.Xilinx — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel.Xilinx

+

Submodules

+
+ +
+
+ + +
+
+
+ +
+ +
+

© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/pyEDAA.ProjectModel/pyEDAA.ProjectModel.html b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.html new file mode 100644 index 00000000..62e5409f --- /dev/null +++ b/pyEDAA.ProjectModel/pyEDAA.ProjectModel.html @@ -0,0 +1,1602 @@ + + + + + + + pyEDAA.ProjectModel — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

pyEDAA.ProjectModel

+

Submodules

+
+ +
+

Classes

+
    +

  • Attribute: +Undocumented.

    • +

  • FileType: +A meta-class to construct FileType classes.

    • +

  • File: +A File represents a file in a design. This base-class is used

    • +

  • HumanReadableContent: +A file type representing human-readable contents.

    • +

  • XMLContent: +A file type representing XML contents.

    • +

  • YAMLContent: +A file type representing YAML contents.

    • +

  • JSONContent: +A file type representing JSON contents.

    • +

  • INIContent: +A file type representing INI contents.

    • +

  • TOMLContent: +A file type representing TOML contents.

    • +

  • TCLContent: +A file type representing content in TCL code.

    • +

  • SDCContent: +A file type representing contents as Synopsys Design Constraints (SDC).

    • +

  • PythonContent: +A file type representing contents as Python source code.

    • +

  • TextFile: +A text file (*.txt).

    • +

  • LogFile: +A log file (*.log).

    • +

  • XMLFile: +An XML file (*.xml).

    • +

  • SourceFile: +Base-class of all source files.

    • +

  • HDLSourceFile: +Base-class of all HDL source files.

    • +

  • RDLSourceFile: +Base-class of all RDL source files.

    • +

  • NetlistFile: +Base-class of all netlist source files.

    • +

  • EDIFNetlistFile: +Netlist file in EDIF (Electronic Design Interchange Format).

    • +

  • TCLSourceFile: +A TCL source file.

    • +

  • VHDLSourceFile: +A VHDL source file (of any language version).

    • +

  • VerilogBaseFile: +Base-class of all HDL source files.

    • +

  • VerilogSourceFile: +A Verilog source file (of any language version).

    • +

  • VerilogHeaderFile: +A Verilog header file (of any language version).

    • +

  • SystemVerilogBaseFile: +Base-class of all HDL source files.

    • +

  • SystemVerilogSourceFile: +A SystemVerilog source file (of any language version).

    • +

  • SystemVerilogHeaderFile: +A SystemVerilog header file (of any language version).

    • +

  • SystemRDLSourceFile: +A SystemRDL source file (of any language version).

    • +

  • PythonSourceFile: +A Python source file.

    • +

  • CocotbPythonFile: +A Python source file used by Cocotb.

    • +

  • ConstraintFile: +Base-class of all constraint files.

    • +

  • ProjectFile: +Base-class of all tool-specific project files.

    • +

  • CSourceFile: +Base-class of all ANSI-C source files.

    • +

  • CppSourceFile: +Base-class of all ANSI-C++ source files.

    • +

  • SettingFile: +Base-class of all tool-specific setting files.

    • +

  • SimulationAnalysisFile: +Base-class of all tool-specific analysis files.

    • +

  • SimulationElaborationFile: +Base-class of all tool-specific elaboration files.

    • +

  • SimulationStartFile: +Base-class of all tool-specific simulation start-up files.

    • +

  • SimulationRunFile: +Base-class of all tool-specific simulation run (execution) files.

    • +

  • WaveformConfigFile: +Base-class of all tool-specific waveform configuration files.

    • +

  • WaveformDatabaseFile: +Base-class of all tool-specific waveform database files.

    • +

  • WaveformExchangeFile: +Base-class of all tool-independent waveform exchange files.

    • +

  • FileSet: +A FileSet represents a group of files. Filesets can have sub-filesets.

    • +

  • VHDLLibrary: +A VHDLLibrary represents a group of VHDL source files compiled into the same VHDL library.

    • +

  • Design: +A Design represents a group of filesets and the source files therein.

    • +

  • Project: +A Project represents a group of designs and the source files therein.

    • +
+
+
+class pyEDAA.ProjectModel.Attribute[source]
+

Inheritance

+
+

Inheritance diagram of Attribute

+
+ +
+
+class pyEDAA.ProjectModel.FileType(name, bases, dictionary, **kwargs)[source]
+

A meta-class to construct FileType classes.

+

Modifications done by this meta-class: +* Register all classes of type FileType or derived variants in a class field FileType.FileTypes in this meta-class.

+

Inheritance

+
+

Inheritance diagram of FileType

+
+
Parameters:
+

classMembers (Dict) –

+
+
+
+
+FileTypes: Dict[str, FileType] = {'CSourceFile': <class 'pyEDAA.ProjectModel.CSourceFile'>, 'CocotbPythonFile': <class 'pyEDAA.ProjectModel.CocotbPythonFile'>, 'ConstraintFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.ConstraintFile'>, 'CppSourceFile': <class 'pyEDAA.ProjectModel.CppSourceFile'>, 'EDIFNetlistFile': <class 'pyEDAA.ProjectModel.EDIFNetlistFile'>, 'File': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.File'>, 'GHDLWaveformFile': <class 'pyEDAA.ProjectModel.GHDL.GHDLWaveformFile'>, 'HDLSourceFile': <class 'pyEDAA.ProjectModel.HDLSourceFile'>, 'IPCoreDescriptionFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.IPCoreDescriptionFile'>, 'IPCoreInstantiationFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.IPCoreInstantiationFile'>, 'ISEProjectFile': <class 'pyEDAA.ProjectModel.Xilinx.ISE.ISEProjectFile'>, 'LogFile': <class 'pyEDAA.ProjectModel.LogFile'>, 'ModelSimINIFile': <class 'pyEDAA.ProjectModel.MentorGraphics.QuestaSim.ModelSimINIFile'>, 'ModelSimProjectFile': <class 'pyEDAA.ProjectModel.MentorGraphics.QuestaSim.ModelSimProjectFile'>, 'NetlistFile': <class 'pyEDAA.ProjectModel.NetlistFile'>, 'OSVVMProjectFile': <class 'pyEDAA.ProjectModel.OSVVM.OSVVMProjectFile'>, 'ProjectFile': <class 'pyEDAA.ProjectModel.ProjectFile'>, 'PythonSourceFile': <class 'pyEDAA.ProjectModel.PythonSourceFile'>, 'QuartusProjectFile': <class 'pyEDAA.ProjectModel.Intel.QuartusPrime.QuartusProjectFile'>, 'RDLSourceFile': <class 'pyEDAA.ProjectModel.RDLSourceFile'>, 'SDCConstraintFile': <class 'pyEDAA.ProjectModel.Intel.QuartusPrime.SDCConstraintFile'>, 'SettingFile': <class 'pyEDAA.ProjectModel.SettingFile'>, 'SimulationAnalysisFile': <class 'pyEDAA.ProjectModel.SimulationAnalysisFile'>, 'SimulationElaborationFile': <class 'pyEDAA.ProjectModel.SimulationElaborationFile'>, 'SimulationRunFile': <class 'pyEDAA.ProjectModel.SimulationRunFile'>, 'SimulationStartFile': <class 'pyEDAA.ProjectModel.SimulationStartFile'>, 'SourceFile': <class 'pyEDAA.ProjectModel.SourceFile'>, 'SystemRDLSourceFile': <class 'pyEDAA.ProjectModel.SystemRDLSourceFile'>, 'SystemVerilogBaseFile': <class 'pyEDAA.ProjectModel.SystemVerilogBaseFile'>, 'SystemVerilogHeaderFile': <class 'pyEDAA.ProjectModel.SystemVerilogHeaderFile'>, 'SystemVerilogSourceFile': <class 'pyEDAA.ProjectModel.SystemVerilogSourceFile'>, 'TCLSourceFile': <class 'pyEDAA.ProjectModel.TCLSourceFile'>, 'TextFile': <class 'pyEDAA.ProjectModel.TextFile'>, 'UCFConstraintFile': <class 'pyEDAA.ProjectModel.Xilinx.ISE.UCFConstraintFile'>, 'VHDLSourceFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.VHDLSourceFile'>, 'ValueChangeDumpFile': <class 'pyEDAA.ProjectModel.Verilog.ValueChangeDumpFile'>, 'VerilogBaseFile': <class 'pyEDAA.ProjectModel.VerilogBaseFile'>, 'VerilogHeaderFile': <class 'pyEDAA.ProjectModel.VerilogHeaderFile'>, 'VerilogSourceFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.VerilogSourceFile'>, 'VivadoProjectFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.VivadoProjectFile'>, 'WaveDoFile': <class 'pyEDAA.ProjectModel.MentorGraphics.QuestaSim.WaveDoFile'>, 'WaveformConfigFile': <class 'pyEDAA.ProjectModel.WaveformConfigFile'>, 'WaveformDatabaseFile': <class 'pyEDAA.ProjectModel.WaveformDatabaseFile'>, 'WaveformExchangeFile': <class 'pyEDAA.ProjectModel.WaveformExchangeFile'>, 'XDCConstraintFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.XDCConstraintFile'>, 'XMLFile': <class 'pyEDAA.ProjectModel.XMLFile'>}
+

Dictionary of all classes of type FileType or derived variants

+
+ +
+
+__init__(name, bases, dictionary, **kwargs)[source]
+
+
Parameters:
+
+
+
+
+ +
+
+static __new__(cls, className, baseClasses, classMembers, *args, **kwargs)[source]
+

Construct a new class using this meta-class.

+
+
Parameters:
+
    +

  • className – The name of the class to construct.

    • +

  • baseClasses – The tuple of base-classes the class is derived from.

    • +

  • members – The dictionary of members for the constructed class.

    • +

  • slots – If true, store object attributes in __slots__ instead of __dict__.

    • +

  • mixin – If true, make the class a Mixin-Class. +If false, create slots if slots is true. +If none, preserve behavior of primary base-class.

    • +

  • singleton – If true, make the class a Singleton.

    • +

  • classMembers (Dict) –

    • +
+
+
Returns:
+

The new class.

+
+
Raises:
+
+
+
+
+ +
+
+__base__
+

alias of ExtendedType

+
+ +
+
+__call__(*args, **kwargs)
+

Call self as a function.

+
+ +
+
+__delattr__(name, /)
+

Implement delattr(self, name).

+
+ +
+
+__dir__()
+

Specialized __dir__ implementation for types.

+
+ +
+
+__getattribute__(name, /)
+

Return getattr(self, name).

+
+ +
+
+__instancecheck__(instance, /)
+

Check if an object is an instance.

+
+ +
+
+__or__(value, /)
+

Return self|value.

+
+ +
+
+classmethod __prepare__(className, baseClasses, slots=False, mixin=False, singleton=False)
+

used to create the namespace for the class statement

+
+
Parameters:
+
    +

  • slots (bool) –

    • +

  • mixin (bool) –

    • +

  • singleton (bool) –

    • +
+
+
+
+ +
+
+__repr__()
+

Return repr(self).

+
+ +
+
+__ror__(value, /)
+

Return value|self.

+
+ +
+
+__setattr__(name, value, /)
+

Implement setattr(self, name, value).

+
+ +
+
+__sizeof__()
+

Return memory consumption of the type object.

+
+ +
+
+__subclasscheck__(subclass, /)
+

Check if a class is a subclass.

+
+ +
+
+__subclasses__()
+

Return a list of immediate subclasses.

+
+ +
+
+__text_signature__ = None
+
+ +
+
+classmethod _checkForAbstractMethods(baseClasses, members)
+

Check if the current class contains abstract methods and return a tuple of them.

+

These abstract methods might be inherited from any base-class. If there are inherited abstract methods, check if +they are now implemented (overridden) by the current class that’s right now constructed.

+
+
Parameters:
+
    +

  • baseClasses (Tuple[type]) – The tuple of base-classes the class is derived from.

    • +

  • members (Dict[str, Any]) – The dictionary of members for the constructed class.

    • +
+
+
Return type:
+

Tuple[Dict[str, Callable], Dict[str, Any]]

+
+
Returns:
+

A tuple of abstract method’s names.

+
+
+
+ +
+
+classmethod _iterateBaseClassPaths(baseClasses)
+

Return a generator to iterate all possible inheritance paths for a given list of base-classes.

+

An inheritance path is expressed as a tuple of base-classes from current base-class (left-most item) to +object (right-most item).

+
+
Parameters:
+

baseClasses (Tuple[type]) – List (tuple) of base-classes.

+
+
Return type:
+

Generator[Tuple[type, ...], None, None]

+
+
Returns:
+

Generator to iterate all inheritance paths. An inheritance path is a tuple of types (base-classes).

+
+
+
+ +
+
+classmethod _wrapNewMethodIfAbstract(newClass)
+

If the class has abstract methods, replace the _new__ method, so it raises an exception.

+
+
Parameters:
+

newClass – The newly constructed class for further modifications.

+
+
Return type:
+

bool

+
+
Returns:
+

True, if the class is abstract.

+
+
Raises:
+

AbstractClassError – If the class is abstract and can’t be instantiated.

+
+
+
+ +
+
+classmethod _wrapNewMethodIfSingleton(newClass, singleton)
+

If a class is a singleton, wrap the _new__ method, so it returns a cached object, if a first object was created.

+

Only the first object creation initializes the object.

+

This implementation is threadsafe.

+
+
Parameters:
+
    +

  • newClass – The newly constructed class for further modifications.

    • +

  • singleton (bool) – If True, the class allows only a single instance to exist.

    • +
+
+
Return type:
+

bool

+
+
Returns:
+

True, if the class is a singleton.

+
+
+
+ +
+
+mro()
+

Return a type’s method resolution order.

+
+ +
+ +
+
+class pyEDAA.ProjectModel.HumanReadableContent[source]
+

A file type representing human-readable contents.

+

Inheritance

+
+

Inheritance diagram of HumanReadableContent

+
+ +
+
+class pyEDAA.ProjectModel.XMLContent[source]
+

A file type representing XML contents.

+

Inheritance

+
+

Inheritance diagram of XMLContent

+
+ +
+
+class pyEDAA.ProjectModel.YAMLContent[source]
+

A file type representing YAML contents.

+

Inheritance

+
+

Inheritance diagram of YAMLContent

+
+ +
+
+class pyEDAA.ProjectModel.JSONContent[source]
+

A file type representing JSON contents.

+

Inheritance

+
+

Inheritance diagram of JSONContent

+
+ +
+
+class pyEDAA.ProjectModel.INIContent[source]
+

A file type representing INI contents.

+

Inheritance

+
+

Inheritance diagram of INIContent

+
+ +
+
+class pyEDAA.ProjectModel.TOMLContent[source]
+

A file type representing TOML contents.

+

Inheritance

+
+

Inheritance diagram of TOMLContent

+
+ +
+
+class pyEDAA.ProjectModel.TCLContent[source]
+

A file type representing content in TCL code.

+

Inheritance

+
+

Inheritance diagram of TCLContent

+
+ +
+
+class pyEDAA.ProjectModel.SDCContent[source]
+

A file type representing contents as Synopsys Design Constraints (SDC).

+

Inheritance

+
+

Inheritance diagram of SDCContent

+
+ +
+
+class pyEDAA.ProjectModel.PythonContent[source]
+

A file type representing contents as Python source code.

+

Inheritance

+
+

Inheritance diagram of PythonContent

+
+ +
+
+class pyEDAA.ProjectModel.FileSet(name, topLevel=None, directory=PosixPath('.'), project=None, design=None, parent=None, vhdlLibrary=None, vhdlVersion=None, verilogVersion=None, svVersion=None, srdlVersion=None)[source]
+

A FileSet represents a group of files. Filesets can have sub-filesets.

+

The order of insertion is preserved. A fileset can be created standalone and +later associated to another fileset, design and/or project. Or a fileset, +design and/or project can be associated immediately while creating the +fileset.

+
+
Parameters:
+
    +

  • name (str) – Name of this fileset.

    • +

  • topLevel (str) – Name of the fileset’s toplevel.

    • +

  • directory (Path) – Path of this fileset (absolute or relative to a parent fileset or design).

    • +

  • project (Project) – Project the file is associated with.

    • +

  • design (Design) – Design the file is associated with.

    • +

  • parent (Optional[FileSet]) – Parent fileset if this fileset is nested.

    • +

  • vhdlLibrary (Union[str, VHDLLibrary]) – Default VHDL library for files in this fileset, if not specified for the file itself.

    • +

  • vhdlVersion (VHDLVersion) – Default VHDL version for files in this fileset, if not specified for the file itself.

    • +

  • verilogVersion (SystemVerilogVersion) – Default Verilog version for files in this fileset, if not specified for the file itself.

    • +

  • svVersion (SystemVerilogVersion) – Default SystemVerilog version for files in this fileset, if not specified for the file itself.

    • +

  • srdlVersion (SystemRDLVersion) – Default SystemRDL version for files in this fileset, if not specified for the file itself.

    • +

  • name –

    • +

  • topLevel –

    • +

  • directory –

    • +

  • project –

    • +

  • design –

    • +

  • parent –

    • +

  • vhdlLibrary –

    • +

  • vhdlVersion –

    • +

  • verilogVersion –

    • +

  • svVersion –

    • +

  • srdlVersion –

    • +
+
+
+

Inheritance

+
+

Inheritance diagram of FileSet

+
+
+__init__(name, topLevel=None, directory=PosixPath('.'), project=None, design=None, parent=None, vhdlLibrary=None, vhdlVersion=None, verilogVersion=None, svVersion=None, srdlVersion=None)[source]
+
+
Parameters:
+
    +

  • name (str) –

    • +

  • topLevel (str) –

    • +

  • directory (Path) –

    • +

  • project (Project) –

    • +

  • design (Design) –

    • +

  • parent (FileSet | None) –

    • +

  • vhdlLibrary (str | VHDLLibrary) –

    • +

  • vhdlVersion (VHDLVersion) –

    • +

  • verilogVersion (SystemVerilogVersion) –

    • +

  • svVersion (SystemVerilogVersion) –

    • +

  • srdlVersion (SystemRDLVersion) –

    • +
+
+
+
+ +
+
+property Name: str
+

Property setting or returning the fileset’s name.

+
+ +
+
+property TopLevel: str
+

Property setting or returning the fileset’s toplevel.

+
+ +
+
+property Project: Project | None
+

Property setting or returning the project this fileset is used in.

+
+ +
+
+property Design: Design | None
+

Property setting or returning the design this fileset is used in.

+
+ +
+
+property Directory: Path
+

Property setting or returning the directory this fileset is located in.

+
+ +
+
+property ResolvedPath: Path
+

Read-only property returning the resolved path of this fileset.

+
+ +
+
+property Parent: FileSet | None
+

Property setting or returning the parent fileset this fileset is used in.

+
+ +
+
+property FileSets: Dict[str, FileSet]
+

Read-only property returning the dictionary of sub-filesets.

+
+ +
+
+Files(fileType=<class 'pyEDAA.ProjectModel.File'>, fileSet=None)[source]
+

Method returning the files of this fileset.

+
+
Parameters:
+
    +

  • fileType (FileType) – A filter for file types. Default: Any.

    • +

  • fileSet (Union[bool, str, FileSet]) – Specifies how to handle sub-filesets.

    • +

  • fileType –

    • +

  • fileSet –

    • +
+
+
Return type:
+

Generator[File, None, None]

+
+
+
+ +
+
+AddFileSet(fileSet)[source]
+

Method to add a single sub-fileset to this fileset.

+
+
Parameters:
+
    +

  • fileSet (FileSet) – A fileset to add to this fileset as sub-fileset.

    • +

  • fileSet –

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+AddFileSets(fileSets)[source]
+

Method to add a multiple sub-filesets to this fileset.

+
+
Parameters:
+
    +

  • fileSets (Iterable[FileSet]) – An iterable of filesets to add each to the fileset.

    • +

  • fileSets –

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property FileSetCount: int
+

Returns number of file sets excl. sub-filesets.

+
+ +
+
+property TotalFileSetCount: int
+

Returns number of file sets incl. sub-filesets.

+
+ +
+
+AddFile(file)[source]
+

Method to add a single file to this fileset.

+
+
Parameters:
+
    +

  • file (File) – A file to add to this fileset.

    • +

  • file –

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+AddFiles(files)[source]
+

Method to add a multiple files to this fileset.

+
+
Parameters:
+
    +

  • files (Iterable[File]) – An iterable of files to add each to the fileset.

    • +

  • files –

    • +
+
+
Return type:
+

None

+
+
+
+ +
+
+property FileCount: int
+

Returns number of files excl. sub-filesets.

+
+ +
+
+property TotalFileCount: int
+

Returns number of files incl. the files in sub-filesets.

+
+ +
+
+Validate()[source]
+

Validate this fileset.

+
+
Return type:
+

None

+
+
+
+ +
+
+property VHDLLibrary: VHDLLibrary
+

Property setting or returning the VHDL library of this fileset.

+
+ +
+
+property VHDLVersion: VHDLVersion
+

Property setting or returning the VHDL version of this fileset.

+
+ +
+
+property VerilogVersion: SystemVerilogVersion
+

Property setting or returning the Verilog version of this fileset.

+
+ +
+
+property SVVersion: SystemVerilogVersion
+

Property setting or returning the SystemVerilog version of this fileset.

+
+ +
+
+__len__()[source]
+

Returns number of attributes set on this fileset.

+
+
Return type:
+

int

+
+
Returns:
+

The number if attributes set on this fileset.

+
+
+
+ +
+
+__getitem__(key)[source]
+

Index access for returning attributes on this fileset.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

Any

+
+
Returns:
+

The attribute’s value.

+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
+
+ +
+
+__setitem__(key, value)[source]
+

Index access for adding or setting attributes on this fileset.

+
+
Parameters:
+
    +

  • key (Type[Attribute]) – The attribute type.

    • +

  • value (Any) – The attributes value.

    • +
+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
Return type:
+

None

+
+
+
+ +
+
+__delitem__(key)[source]
+

Index access for deleting attributes on this fileset.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Returns the fileset’s name.

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyEDAA.ProjectModel.VHDLLibrary(name, project=None, design=None, vhdlVersion=None)[source]
+

A VHDLLibrary represents a group of VHDL source files compiled into the same VHDL library.

+
+
Parameters:
+
    +

  • name (str) – The VHDL libraries’ name.

    • +

  • project (Project) – Project the VHDL library is associated with.

    • +

  • design (Design) – Design the VHDL library is associated with.

    • +

  • vhdlVersion (VHDLVersion) – Default VHDL version for files in this VHDL library, if not specified for the file itself.

    • +

  • name –

    • +

  • project –

    • +

  • design –

    • +

  • vhdlVersion –

    • +
+
+
+

Inheritance

+
+

Inheritance diagram of VHDLLibrary

+
+
+__init__(name, project=None, design=None, vhdlVersion=None)[source]
+
+
Parameters:
+
    +

  • name (str) –

    • +

  • project (Project) –

    • +

  • design (Design) –

    • +

  • vhdlVersion (VHDLVersion) –

    • +
+
+
+
+ +
+
+property Project: Project | None
+

Property setting or returning the project this VHDL library is used in.

+
+ +
+
+property Design: Design | None
+

Property setting or returning the design this VHDL library is used in.

+
+ +
+
+property Files: Generator[File, None, None]
+

Read-only property to return all files in this VHDL library.

+
+ +
+
+property VHDLVersion: VHDLVersion
+

Property setting or returning the VHDL version of this VHDL library.

+
+ +
+
+property FileCount: int
+

Returns number of files.

+
+ +
+
+__len__()[source]
+

Returns number of attributes set on this VHDL library.

+
+
Return type:
+

int

+
+
Returns:
+

The number if attributes set on this VHDL library.

+
+
+
+ +
+
+__getitem__(key)[source]
+

Index access for returning attributes on this VHDL library.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

Any

+
+
Returns:
+

The attribute’s value.

+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
+
+ +
+
+__setitem__(key, value)[source]
+

Index access for adding or setting attributes on this VHDL library.

+
+
Parameters:
+
    +

  • key (Type[Attribute]) – The attribute type.

    • +

  • value (Any) – The attributes value.

    • +
+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
Return type:
+

None

+
+
+
+ +
+
+__delitem__(key)[source]
+

Index access for deleting attributes on this VHDL library.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Returns the VHDL library’s name.

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyEDAA.ProjectModel.Design(name, topLevel=None, directory=PosixPath('.'), project=None, vhdlVersion=None, verilogVersion=None, svVersion=None, srdlVersion=None)[source]
+

A Design represents a group of filesets and the source files therein.

+

Each design contains at least one fileset - the default fileset. For +designs with VHDL source files, a independent VHDLLibraries overlay structure +exists.

+
+
Parameters:
+
    +

  • name (str) – The design’s name.

    • +

  • topLevel (str) – Name of the design’s toplevel.

    • +

  • directory (Path) – Path of this design (absolute or relative to the project).

    • +

  • project (Project) – Project the design is associated with.

    • +

  • vhdlVersion (VHDLVersion) – Default VHDL version for files in this design, if not specified for the file itself.

    • +

  • verilogVersion (SystemVerilogVersion) – Default Verilog version for files in this design, if not specified for the file itself.

    • +

  • svVersion (SystemVerilogVersion) – Default SystemVerilog version for files in this design, if not specified for the file itself.

    • +

  • srdlVersion (SystemRDLVersion) – Default SystemRDL version for files in this fileset, if not specified for the file itself.

    • +

  • name –

    • +

  • topLevel –

    • +

  • directory –

    • +

  • project –

    • +

  • vhdlVersion –

    • +

  • verilogVersion –

    • +

  • svVersion –

    • +

  • srdlVersion –

    • +
+
+
+

Inheritance

+
+

Inheritance diagram of Design

+
+
+__init__(name, topLevel=None, directory=PosixPath('.'), project=None, vhdlVersion=None, verilogVersion=None, svVersion=None, srdlVersion=None)[source]
+
+
Parameters:
+
    +

  • name (str) –

    • +

  • topLevel (str) –

    • +

  • directory (Path) –

    • +

  • project (Project) –

    • +

  • vhdlVersion (VHDLVersion) –

    • +

  • verilogVersion (SystemVerilogVersion) –

    • +

  • svVersion (SystemVerilogVersion) –

    • +

  • srdlVersion (SystemRDLVersion) –

    • +
+
+
+
+ +
+
+property Name: str
+

Property setting or returning the design’s name.

+
+ +
+
+property TopLevel: str
+

Property setting or returning the fileset’s toplevel.

+
+ +
+
+property Project: Project | None
+

Property setting or returning the project this design is used in.

+
+ +
+
+property Directory: Path
+

Property setting or returning the directory this design is located in.

+
+ +
+
+property ResolvedPath: Path
+

Read-only property returning the resolved path of this fileset.

+
+ +
+
+property DefaultFileSet: FileSet
+

Property setting or returning the default fileset of this design.

+
+ +
+
+property FileSets: Dict[str, FileSet]
+

Read-only property returning the dictionary of filesets.

+
+ +
+
+Files(fileType=<class 'pyEDAA.ProjectModel.File'>, fileSet=None)[source]
+

Method returning the files of this design.

+
+
Parameters:
+
    +

  • fileType (FileType) – A filter for file types. Default: Any.

    • +

  • fileSet (Union[str, FileSet]) – Specifies if all files from all filesets (fileSet=None) are files from a single fileset are returned.

    • +

  • fileType –

    • +

  • fileSet –

    • +
+
+
Return type:
+

Generator[File, None, None]

+
+
+
+ +
+
+Validate()[source]
+

Validate this design.

+
+
Return type:
+

None

+
+
+
+ +
+
+property FileSetCount: int
+

Returns number of file sets excl. sub-filesets.

+
+ +
+
+property TotalFileSetCount: int
+

Returns number of file sets incl. sub-filesets.

+
+ +
+
+__len__()[source]
+

Returns number of attributes set on this design.

+
+
Return type:
+

int

+
+
Returns:
+

The number if attributes set on this design.

+
+
+
+ +
+
+__getitem__(key)[source]
+

Index access for returning attributes on this design.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

Any

+
+
Returns:
+

The attribute’s value.

+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
+
+ +
+
+__setitem__(key, value)[source]
+

Index access for adding or setting attributes on this design.

+
+
Parameters:
+
    +

  • key (Type[Attribute]) – The attribute type.

    • +

  • value (Any) – The attributes value.

    • +
+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
Return type:
+

None

+
+
+
+ +
+
+__delitem__(key)[source]
+

Index access for deleting attributes on this design.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

+
+
+
+ +
+ +
+
+class pyEDAA.ProjectModel.Project(name, rootDirectory=PosixPath('.'), vhdlVersion=None, verilogVersion=None, svVersion=None)[source]
+

A Project represents a group of designs and the source files therein.

+
+
Parameters:
+
    +

  • name (str) – The project’s name.

    • +

  • rootDirectory (Path) – Base-path to the project.

    • +

  • vhdlVersion (VHDLVersion) – Default VHDL version for files in this project, if not specified for the file itself.

    • +

  • verilogVersion (SystemVerilogVersion) – Default Verilog version for files in this project, if not specified for the file itself.

    • +

  • svVersion (SystemVerilogVersion) – Default SystemVerilog version for files in this project, if not specified for the file itself.

    • +

  • name –

    • +

  • rootDirectory –

    • +

  • vhdlVersion –

    • +

  • verilogVersion –

    • +

  • svVersion –

    • +
+
+
+

Inheritance

+
+

Inheritance diagram of Project

+
+
+__init__(name, rootDirectory=PosixPath('.'), vhdlVersion=None, verilogVersion=None, svVersion=None)[source]
+
+
Parameters:
+
    +

  • name (str) –

    • +

  • rootDirectory (Path) –

    • +

  • vhdlVersion (VHDLVersion) –

    • +

  • verilogVersion (SystemVerilogVersion) –

    • +

  • svVersion (SystemVerilogVersion) –

    • +
+
+
+
+ +
+
+property Name: str
+

Property setting or returning the project’s name.

+
+ +
+
+property RootDirectory: Path
+

Property setting or returning the root directory this project is located in.

+
+ +
+
+property ResolvedPath: Path
+

Read-only property returning the resolved path of this fileset.

+
+ +
+
+Validate()[source]
+

Validate this project.

+
+
Return type:
+

None

+
+
+
+ +
+
+property DesignCount: int
+

Returns number of designs.

+
+ +
+
+__len__()[source]
+

Returns number of attributes set on this project.

+
+
Return type:
+

int

+
+
Returns:
+

The number if attributes set on this project.

+
+
+
+ +
+
+__getitem__(key)[source]
+

Index access for returning attributes on this project.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

Any

+
+
Returns:
+

The attribute’s value.

+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
+
+ +
+
+__setitem__(key, value)[source]
+

Index access for adding or setting attributes on this project.

+
+
Parameters:
+
    +

  • key (Type[Attribute]) – The attribute type.

    • +

  • value (Any) – The attributes value.

    • +
+
+
Raises:
+

TypeError – When parameter ‘key’ is not a subclass of Attribute.

+
+
Return type:
+

None

+
+
+
+ +
+
+__delitem__(key)[source]
+

Index access for deleting attributes on this project.

+
+
Parameters:
+

key (Type[Attribute]) – The attribute type.

+
+
Return type:
+

None

+
+
+
+ +
+
+__str__()[source]
+

Return str(self).

+
+
Return type:
+

str

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+
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+ +
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© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

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+ + + + \ No newline at end of file diff --git a/search.html b/search.html new file mode 100644 index 00000000..60a04396 --- /dev/null +++ b/search.html @@ -0,0 +1,146 @@ + + + + + + Search — pyEDAA.ProjectModel 0.5.0 documentation + + + + + + + + + + + + + + + + + + + +
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© Copyright 2014-2023, Patrick Lehmann, Unai Martinez-Corral. + Last updated on 24.08.2023. +

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
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+ + + + + + + + + \ No newline at end of file diff --git a/searchindex.js b/searchindex.js new file mode 100644 index 00000000..5de0ab74 --- /dev/null +++ b/searchindex.js @@ -0,0 +1 @@ +Search.setIndex({"docnames": ["ChangeLog/index", "Dependency", "Doc-License", "FileTypes/index", "Glossary", "Installation", "License", "ProjectModel/Design", "ProjectModel/File", "ProjectModel/FileSet", "ProjectModel/Project", "ProjectModel/VHDLLibrary", "ProjectModel/index", "coverage/index", "genindex", "index", "py-modindex", "pyEDAA.ProjectModel/index", "pyEDAA.ProjectModel/pyEDAA.ProjectModel", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.Altera.Quartus", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.Attributes", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.GHDL", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.Intel.QuartusPrime", "pyEDAA.ProjectModel/pyEDAA.ProjectModel.MentorGraphics", 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"__subclasses__() (pyedaa.projectmodel.filetype method)": [[18, "pyEDAA.ProjectModel.FileType.__subclasses__"]], "__text_signature__ (pyedaa.projectmodel.filetype attribute)": [[18, "pyEDAA.ProjectModel.FileType.__text_signature__"]], "_checkforabstractmethods() (pyedaa.projectmodel.filetype class method)": [[18, "pyEDAA.ProjectModel.FileType._checkForAbstractMethods"]], "_iteratebaseclasspaths() (pyedaa.projectmodel.filetype class method)": [[18, "pyEDAA.ProjectModel.FileType._iterateBaseClassPaths"]], "_wrapnewmethodifabstract() (pyedaa.projectmodel.filetype class method)": [[18, "pyEDAA.ProjectModel.FileType._wrapNewMethodIfAbstract"]], "_wrapnewmethodifsingleton() (pyedaa.projectmodel.filetype class method)": [[18, "pyEDAA.ProjectModel.FileType._wrapNewMethodIfSingleton"]], "module": [[18, "module-pyEDAA.ProjectModel"], [19, "module-pyEDAA.ProjectModel.Altera"], [20, "module-pyEDAA.ProjectModel.Altera.Quartus"], [21, "module-pyEDAA.ProjectModel.Attributes"], [22, "module-pyEDAA.ProjectModel.GHDL"], [23, "module-pyEDAA.ProjectModel.Intel"], [24, "module-pyEDAA.ProjectModel.Intel.QuartusPrime"], [25, "module-pyEDAA.ProjectModel.MentorGraphics"], [26, "module-pyEDAA.ProjectModel.MentorGraphics.ModelSim"], [27, "module-pyEDAA.ProjectModel.MentorGraphics.QuestaSim"], [28, "module-pyEDAA.ProjectModel.OSVVM"], [29, "module-pyEDAA.ProjectModel.VHDL"], [30, "module-pyEDAA.ProjectModel.Verilog"], [31, "module-pyEDAA.ProjectModel.Xilinx"], [32, "module-pyEDAA.ProjectModel.Xilinx.ISE"], [33, "module-pyEDAA.ProjectModel.Xilinx.Vivado"]], "mro() (pyedaa.projectmodel.filetype method)": [[18, "pyEDAA.ProjectModel.FileType.mro"]], "pyedaa.projectmodel": [[18, "module-pyEDAA.ProjectModel"]], "pyedaa.projectmodel.altera": [[19, "module-pyEDAA.ProjectModel.Altera"]], "pyedaa.projectmodel.altera.quartus": [[20, "module-pyEDAA.ProjectModel.Altera.Quartus"]], "keyvalueattribute (class in pyedaa.projectmodel.attributes)": [[21, "pyEDAA.ProjectModel.Attributes.KeyValueAttribute"]], "__init__() (pyedaa.projectmodel.attributes.keyvalueattribute method)": [[21, "pyEDAA.ProjectModel.Attributes.KeyValueAttribute.__init__"]], "pyedaa.projectmodel.attributes": [[21, "module-pyEDAA.ProjectModel.Attributes"]], "pyedaa.projectmodel.ghdl": [[22, "module-pyEDAA.ProjectModel.GHDL"]], "pyedaa.projectmodel.intel": [[23, "module-pyEDAA.ProjectModel.Intel"]], "pyedaa.projectmodel.intel.quartusprime": [[24, "module-pyEDAA.ProjectModel.Intel.QuartusPrime"]], "pyedaa.projectmodel.mentorgraphics": [[25, "module-pyEDAA.ProjectModel.MentorGraphics"]], "pyedaa.projectmodel.mentorgraphics.modelsim": [[26, "module-pyEDAA.ProjectModel.MentorGraphics.ModelSim"]], "pyedaa.projectmodel.mentorgraphics.questasim": [[27, "module-pyEDAA.ProjectModel.MentorGraphics.QuestaSim"]], "pyedaa.projectmodel.osvvm": [[28, "module-pyEDAA.ProjectModel.OSVVM"]], "pyedaa.projectmodel.vhdl": [[29, "module-pyEDAA.ProjectModel.VHDL"]], "pyedaa.projectmodel.verilog": [[30, "module-pyEDAA.ProjectModel.Verilog"]], "pyedaa.projectmodel.xilinx": [[31, "module-pyEDAA.ProjectModel.Xilinx"]], "pyedaa.projectmodel.xilinx.ise": [[32, "module-pyEDAA.ProjectModel.Xilinx.ISE"]], "usedinattribute (class in pyedaa.projectmodel.xilinx.vivado)": [[33, "pyEDAA.ProjectModel.Xilinx.Vivado.UsedInAttribute"]], "pyedaa.projectmodel.xilinx.vivado": [[33, "module-pyEDAA.ProjectModel.Xilinx.Vivado"]]}}) \ No newline at end of file diff --git a/typing/html/ProjectModel/Altera/Quartus.py.html b/typing/html/ProjectModel/Altera/Quartus.py.html new file mode 100644 index 00000000..f1b492ae --- /dev/null +++ b/typing/html/ProjectModel/Altera/Quartus.py.html @@ -0,0 +1,106 @@ + + + + + + +

ProjectModel.Altera.Quartus

+ + + + + + +
ProjectModel/Altera/Quartus.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Altera Quartus."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, SDCContent, TCLContent
+
+
+@export
+class QuartusProjectFile(ProjectFile, TCLContent):
+	"""A Quartus project file (``*.qpf``)."""
+
+
+@export
+class SDCConstraintFile(ConstraintFile, SDCContent):
+	"""A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``)."""
+
+ + diff --git a/typing/html/ProjectModel/Altera/__init__.py.html b/typing/html/ProjectModel/Altera/__init__.py.html new file mode 100644 index 00000000..59fb7972 --- /dev/null +++ b/typing/html/ProjectModel/Altera/__init__.py.html @@ -0,0 +1,78 @@ + + + + + + +

ProjectModel.Altera

+ + + + + + +
ProjectModel/Altera/__init__.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""A vendor specific package for Altera (now Intel FPGA)."""
+
+ + diff --git a/typing/html/ProjectModel/Attributes.py.html b/typing/html/ProjectModel/Attributes.py.html new file mode 100644 index 00000000..663c9e3f --- /dev/null +++ b/typing/html/ProjectModel/Attributes.py.html @@ -0,0 +1,125 @@ + + + + + + +

ProjectModel.Attributes

+ + + + + + +
ProjectModel/Attributes.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""A set of common attributes to store meta information on ProjectModel entities (project, design, fileset, file, ...)."""
+from typing               import Dict
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel  import Attribute
+
+
+@export
+class KeyValueAttribute(Attribute):
+	KEY = "ID"
+
+	_keyValuePairs: Dict[str, str]
+
+	def __init__(self):
+		super().__init__()
+
+		self._keyValuePairs = {}
+
+	def __getitem__(self, item: str) -> str:
+		return self._keyValuePairs[item]
+
+	def __setitem__(self, key: str, value: str) -> None:
+		self._keyValuePairs[key] = value
+
+ + diff --git a/typing/html/ProjectModel/GHDL.py.html b/typing/html/ProjectModel/GHDL.py.html new file mode 100644 index 00000000..745543a7 --- /dev/null +++ b/typing/html/ProjectModel/GHDL.py.html @@ -0,0 +1,95 @@ + + + + + + +

ProjectModel.GHDL

+ + + + + + +
ProjectModel/GHDL.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for `GHDL <https://github.com/ghdl>`__."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import WaveformExchangeFile
+
+
+@export
+class GHDLWaveformFile(WaveformExchangeFile):
+	"""GHDL's waveform file (``*.ghw``) supporting VHDL and Verilog simulation results."""
+
+ + diff --git a/typing/html/ProjectModel/Intel/QuartusPrime.py.html b/typing/html/ProjectModel/Intel/QuartusPrime.py.html new file mode 100644 index 00000000..5ad7d97c --- /dev/null +++ b/typing/html/ProjectModel/Intel/QuartusPrime.py.html @@ -0,0 +1,106 @@ + + + + + + +

ProjectModel.Intel.QuartusPrime

+ + + + + + +
ProjectModel/Intel/QuartusPrime.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Intel FPGA Quartus Prime."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, SDCContent, TCLContent
+
+
+@export
+class QuartusProjectFile(ProjectFile, TCLContent):
+	"""A Quartus project file (``*.qpf``)."""
+
+
+@export
+class SDCConstraintFile(ConstraintFile, SDCContent):
+	"""A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``)."""
+
+ + diff --git a/typing/html/ProjectModel/Intel/__init__.py.html b/typing/html/ProjectModel/Intel/__init__.py.html new file mode 100644 index 00000000..96b47437 --- /dev/null +++ b/typing/html/ProjectModel/Intel/__init__.py.html @@ -0,0 +1,78 @@ + + + + + + +

ProjectModel.Intel

+ + + + + + +
ProjectModel/Intel/__init__.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""A vendor specific package for Intel FPGA (formerly Altera)."""
+
+ + diff --git a/typing/html/ProjectModel/MentorGraphics/ModelSim.py.html b/typing/html/ProjectModel/MentorGraphics/ModelSim.py.html new file mode 100644 index 00000000..a554726b --- /dev/null +++ b/typing/html/ProjectModel/MentorGraphics/ModelSim.py.html @@ -0,0 +1,117 @@ + + + + + + +

ProjectModel.MentorGraphics.ModelSim

+ + + + + + +
ProjectModel/MentorGraphics/ModelSim.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Mentor Graphics ModelSim."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ProjectFile, SettingFile, INIContent, WaveformConfigFile, TCLContent
+
+
+@export
+class ModelSimProjectFile(ProjectFile):
+	pass
+
+
+@export
+class ModelSimINIFile(SettingFile, INIContent):
+	pass
+
+
+@export
+class WaveDoFile(WaveformConfigFile, TCLContent):
+	pass
+
+ + diff --git a/typing/html/ProjectModel/MentorGraphics/QuestaSim.py.html b/typing/html/ProjectModel/MentorGraphics/QuestaSim.py.html new file mode 100644 index 00000000..b0921474 --- /dev/null +++ b/typing/html/ProjectModel/MentorGraphics/QuestaSim.py.html @@ -0,0 +1,117 @@ + + + + + + +

ProjectModel.MentorGraphics.QuestaSim

+ + + + + + +
ProjectModel/MentorGraphics/QuestaSim.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Mentor Graphics QuestaSim."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ProjectFile, SettingFile, INIContent, WaveformConfigFile, TCLContent
+
+
+@export
+class ModelSimProjectFile(ProjectFile):
+	pass
+
+
+@export
+class ModelSimINIFile(SettingFile, INIContent):
+	pass
+
+
+@export
+class WaveDoFile(WaveformConfigFile, TCLContent):
+	pass
+
+ + diff --git a/typing/html/ProjectModel/MentorGraphics/__init__.py.html b/typing/html/ProjectModel/MentorGraphics/__init__.py.html new file mode 100644 index 00000000..f22a8021 --- /dev/null +++ b/typing/html/ProjectModel/MentorGraphics/__init__.py.html @@ -0,0 +1,78 @@ + + + + + + +

ProjectModel.MentorGraphics

+ + + + + + +
ProjectModel/MentorGraphics/__init__.py
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# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""A vendor specific package for Mentor Graphics (now Siemens EDA)."""
+
+ + diff --git a/typing/html/ProjectModel/OSVVM.py.html b/typing/html/ProjectModel/OSVVM.py.html new file mode 100644 index 00000000..3475c334 --- /dev/null +++ b/typing/html/ProjectModel/OSVVM.py.html @@ -0,0 +1,482 @@ + + + + + + +

ProjectModel.OSVVM

+ + + + + + +
ProjectModel/OSVVM.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for `OSVVM <https://github.com/OSVVM>`__."""
+from pathlib import Path
+
+from pyTooling.Decorators import export
+from typing import Optional as Nullable, List
+
+from pyEDAA.ProjectModel import ProjectFile, TCLContent, Project, Design, FileSet, VHDLLibrary, VHDLSourceFile
+
+
+@export
+class OSVVMProjectFile(ProjectFile, TCLContent):
+	"""An OSVVM project file (``*.pro``)."""
+
+	_osvvmProject: Nullable[Project]
+
+	def __init__(
+		self,
+		path: Path,
+		project: Project = None,
+		design: Design = None,
+		fileSet: FileSet = None
+	):
+		super().__init__(path, project, design, fileSet)
+
+		self._osvvmProject = None
+
+	@property
+	def ProjectModel(self) -> Project:
+		return self._osvvmProject
+
+	class Instruction:
+		_line: int
+
+		def __init__(self, line: int):
+			self._line = line
+
+	class Empty(Instruction):
+		def __init__(self, line: int):
+			super().__init__(line)
+
+	class Comment(Instruction):
+		_commentText: str
+
+		def __init__(self, line: int, commentText: str):
+			super().__init__(line)
+			self._commentText = commentText.rstrip()
+
+		@property
+		def CommentText(self) -> str:
+			return self._commentText
+
+	class Analyze(Instruction):
+		_vhdlSourceFile: VHDLSourceFile
+
+		def __init__(self, line: int, parameterText: str):
+			super().__init__(line)
+			self._vhdlSourceFile = VHDLSourceFile(Path(parameterText.strip()))
+
+		@property
+		def VHDLSourceFile(self) -> VHDLSourceFile:
+			return self._vhdlSourceFile
+
+	class Library(Instruction):
+		_vhdlLibrary: VHDLLibrary
+
+		def __init__(self, line: int, parameterText: str):
+			super().__init__(line)
+			self._vhdlLibrary = VHDLLibrary(parameterText.strip())
+
+		@property
+		def VHDLLibrary(self) -> VHDLLibrary:
+			return self._vhdlLibrary
+
+	class Include(Instruction):
+		_osvvmProjectFile: 'OSVVMProjectFile'
+		_fileSet:          FileSet
+
+		def __init__(self, line: int, workingDirectory: Path, parameterText: str):
+			super().__init__(line)
+
+			includeFile = Path(parameterText.strip())
+			includePath = (workingDirectory / includeFile).resolve()
+
+			self._fileSet = FileSet(includeFile.name, directory=includeFile.parent)
+			self._osvvmProjectFile = OSVVMProjectFile(includePath)
+
+		@property
+		def OSVVMProjectFile(self) -> 'OSVVMProjectFile':
+			return self._osvvmProjectFile
+
+		def Parse(self, fileSet: FileSet):
+			self._fileSet.Parent = fileSet
+
+			for instruction in self._osvvmProjectFile._Parse():
+				if isinstance(instruction, OSVVMProjectFile.Include):
+					instruction.Parse(self._fileSet)
+				elif isinstance(instruction, OSVVMProjectFile.Analyze):
+					self._fileSet.AddFile(instruction.VHDLSourceFile)
+				elif isinstance(instruction, OSVVMProjectFile.Library):
+					self._fileSet.Design.AddVHDLLibrary(instruction.VHDLLibrary)
+#				elif isinstance(instruction, OSVVMProjectFile.Build):
+
+				elif not isinstance(instruction, (OSVVMProjectFile.Empty, OSVVMProjectFile.Comment)):
+					raise Exception(f"Unknown instruction '{instruction.__class__.__name__}' in OSVVM project file '{self._osvvmProjectFile.ResolvedPath}'")
+
+	def Parse(self):
+		projectName = self._path.name
+		self._osvvmProject = Project(projectName, rootDirectory=self._path.parent)
+
+		fileSet = self._osvvmProject.DefaultDesign.DefaultFileSet
+
+		for instruction in self._Parse():
+			if isinstance(instruction, OSVVMProjectFile.Include):
+				instruction.Parse(fileSet)
+			elif isinstance(instruction, OSVVMProjectFile.Analyze):
+				fileSet.AddFile(instruction.VHDLSourceFile)
+			elif not isinstance(instruction, (OSVVMProjectFile.Empty, OSVVMProjectFile.Comment)):
+				raise Exception(f"Unknown instruction '{instruction.__class__.__name__}' in OSVVM project file '{self.ResolvedPath}'")
+
+	def _Parse(self):
+		path = self.ResolvedPath
+		if not path.exists():
+			raise Exception(f"OSVVM project file '{path}' not found.") from FileNotFoundError(f"File '{path}' not found.")
+
+		instructions: List = []
+		print()
+		with path.open("r") as file:
+			i = 1
+			for line in file:
+				line = line.lstrip()
+
+				if line.startswith("#"):
+					comment = OSVVMProjectFile.Comment(i, line[1:])
+					instructions.append(comment)
+
+				elif line.startswith("analyze"):
+					vhdlFile = OSVVMProjectFile.Analyze(i, line[8:])
+					instructions.append(vhdlFile)
+
+				elif line.startswith("library"):
+					vhdlLibrary = OSVVMProjectFile.Library(i, line[8:])
+					instructions.append(vhdlLibrary)
+
+				elif line.startswith("include"):
+					include = OSVVMProjectFile.Include(i, path.parent, line[8:])
+					instructions.append(include)
+
+				elif line.startswith("build"):
+					parameter = line[6:]
+					print(f"BUILD: {parameter}")
+				elif line.startswith("if"):
+					print(f"IF (line={i}): {line[3:].rstrip()}")
+				elif line.startswith("}"):
+					print(f"}} (line={i}): {line[2:].rstrip()}")
+				elif len(line) == 0:
+					instructions.append(OSVVMProjectFile.Empty(i))
+				else:
+					print(f"UNKNOWN (line={i}): '{line.rstrip()}'")
+
+				i += 1
+
+		return instructions
+
+ + diff --git a/typing/html/ProjectModel/VHDL.py.html b/typing/html/ProjectModel/VHDL.py.html new file mode 100644 index 00000000..4cb8715d --- /dev/null +++ b/typing/html/ProjectModel/VHDL.py.html @@ -0,0 +1,16 @@ + + + + + + +

ProjectModel.VHDL

+ + + + + + +
ProjectModel/VHDL.py

+
+
diff --git a/typing/html/ProjectModel/Verilog.py.html b/typing/html/ProjectModel/Verilog.py.html
new file mode 100644
index 00000000..6685f71d
--- /dev/null
+++ b/typing/html/ProjectModel/Verilog.py.html
@@ -0,0 +1,95 @@
+
+
+
+
+
+
+
ProjectModel.Verilog

+
+
+
+
+
+
+
ProjectModel/Verilog.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Verilog."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import WaveformExchangeFile
+
+
+@export
+class ValueChangeDumpFile(WaveformExchangeFile):
+	"""Verilog's waveform file (``*.vcd``) for exchanging value changes as defined by IEEE Std. 1364."""
+

+
+
diff --git a/typing/html/ProjectModel/Xilinx/ISE.py.html b/typing/html/ProjectModel/Xilinx/ISE.py.html
new file mode 100644
index 00000000..90382f24
--- /dev/null
+++ b/typing/html/ProjectModel/Xilinx/ISE.py.html
@@ -0,0 +1,106 @@
+
+
+
+
+
+
+
ProjectModel.Xilinx.ISE

+
+
+
+
+
+
+
ProjectModel/Xilinx/ISE.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Xilinx ISE."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, HumanReadableContent
+
+
+@export
+class ISEProjectFile(ProjectFile):
+	pass
+
+
+@export
+class UCFConstraintFile(ConstraintFile, HumanReadableContent):
+	pass
+

+
+
diff --git a/typing/html/ProjectModel/Xilinx/Vivado.py.html b/typing/html/ProjectModel/Xilinx/Vivado.py.html
new file mode 100644
index 00000000..96906608
--- /dev/null
+++ b/typing/html/ProjectModel/Xilinx/Vivado.py.html
@@ -0,0 +1,506 @@
+
+
+
+
+
+
+
ProjectModel.Xilinx.Vivado

+
+
+
+
+
+
+
ProjectModel/Xilinx/Vivado.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Xilinx Vivado."""
+from pathlib import Path
+from typing import Iterable
+
+from xml.dom import minidom, Node
+
+from pyTooling.MetaClasses import ExtendedType
+from pyVHDLModel import VHDLVersion
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design
+from pyEDAA.ProjectModel import File as Model_File
+from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
+from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
+from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
+
+
+@export
+class UsedInAttribute(Attribute):
+	KEY = "UsedIn"
+	VALUE_TYPE = Iterable[str]
+
+
+@export
+class File(Model_File):
+	pass
+
+
+class VivadoFileMixIn(metaclass=ExtendedType, mixin=True):
+	def _registerAttributes(self):
+		self._attributes[UsedInAttribute] = []
+
+
+@export
+class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn):
+	def _registerAttributes(self):
+		super()._registerAttributes()
+		VivadoFileMixIn._registerAttributes(self)
+
+
+@export
+class VerilogSourceFile(Model_VerilogSourceFile):
+	def _registerAttributes(self):
+		super()._registerAttributes()
+		VivadoFileMixIn._registerAttributes(self)
+
+
+@export
+class VHDLSourceFile(Model_VHDLSourceFile):
+	def _registerAttributes(self):
+		super()._registerAttributes()
+		VivadoFileMixIn._registerAttributes(self)
+
+
+@export
+class VivadoProjectFile(ProjectFile, XMLContent):
+	"""A Vivado project file (``*.xpr``)."""
+
+	_xprProject: Project
+
+	def __init__(
+		self,
+		path: Path,
+		project: Project = None,
+		design: Design = None,
+		fileSet: FileSet = None
+	):
+		super().__init__(path, project, design, fileSet)
+
+		self._xprProject = None
+
+	@property
+	def ProjectModel(self) -> Project:
+		return self._xprProject
+
+	def Parse(self):
+		if not self._path.exists():
+			raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.")
+
+		try:
+			root = minidom.parse(str(self._path)).documentElement
+		except Exception as ex:
+			raise Exception(f"Couldn't open '{self._path!s}'.") from ex
+
+		self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent)
+		self._ParseRootElement(root)
+
+	def _ParseRootElement(self, root):
+		for rootNode in root.childNodes:
+			if rootNode.nodeName == "FileSets":
+				self._ParseFileSets(rootNode)
+				break
+
+	def _ParseFileSets(self, filesetsNode):
+		for fileSetsNode in filesetsNode.childNodes:
+			if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet":
+				self._ParseFileSet(fileSetsNode)
+
+	def _ParseFileSet(self, filesetNode):
+		filesetName = filesetNode.getAttribute("Name")
+		fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign)
+
+		for fileNode in filesetNode.childNodes:
+			if fileNode.nodeType == Node.ELEMENT_NODE:
+				if fileNode.tagName == "File":
+					self._ParseFile(fileNode, fileset)
+				elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config":
+					self._ParseFileSetConfig(fileNode, fileset)
+
+	def _ParseFile(self, fileNode, fileset):
+		croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "")
+		filePath = Path(croppedPath)
+		if filePath.suffix in (".vhd", ".vhdl"):
+			self._ParseVHDLFile(fileNode, filePath, fileset)
+		elif filePath.suffix == ".xdc":
+			self._ParseXDCFile(fileNode, filePath, fileset)
+		elif filePath.suffix == ".v":
+			self._ParseVerilogFile(fileNode, filePath, fileset)
+		elif filePath.suffix == ".xci":
+			self._ParseXCIFile(fileNode, filePath, fileset)
+		else:
+			self._ParseDefaultFile(fileNode, filePath, fileset)
+
+	def _ParseVHDLFile(self, fileNode, path, fileset):
+		vhdlFile = VHDLSourceFile(path)
+		fileset.AddFile(vhdlFile)
+		usedInAttr = vhdlFile[UsedInAttribute]
+
+		for childNode in fileNode.childNodes:
+			if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo":
+				if childNode.getAttribute("SFType") == "VHDL2008":
+					vhdlFile.VHDLVersion = VHDLVersion.VHDL2008
+				else:
+					vhdlFile.VHDLVersion = VHDLVersion.VHDL93
+
+				for fileAttribute in childNode.childNodes:
+					if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr":
+						if fileAttribute.getAttribute("Name") == "Library":
+							libraryName = fileAttribute.getAttribute("Val")
+							vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName)
+						elif fileAttribute.getAttribute("Val") == "UsedIn":
+							usedInAttr.append(fileAttribute.getAttribute("Val"))
+
+	def _ParseDefaultFile(self, _, path, fileset):
+		File(path, fileSet=fileset)
+
+	def _ParseXDCFile(self, _, path, fileset):
+		XDCConstraintFile(path, fileSet=fileset)
+
+	def _ParseVerilogFile(self, _, path, fileset):
+		VerilogSourceFile(path, fileSet=fileset)
+
+	def _ParseXCIFile(self, _, path, fileset):
+		IPCoreInstantiationFile(path, fileSet=fileset)
+
+	def _ParseFileSetConfig(self, fileNode, fileset):
+		for option in fileNode.childNodes:
+			if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
+				if option.getAttribute("Name") == "TopModule":
+					fileset.TopLevel = option.getAttribute("Val")
+
+
+@export
+class XDCConstraintFile(ConstraintFile, SDCContent):
+	"""A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``)."""
+
+
+@export
+class IPCoreDescriptionFile(XMLFile):
+	pass
+
+
+@export
+class IPCoreInstantiationFile(XMLFile):
+	"""A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``)."""
+

+
+
diff --git a/typing/html/ProjectModel/Xilinx/__init__.py.html b/typing/html/ProjectModel/Xilinx/__init__.py.html
new file mode 100644
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+
+
+
+
+
+
+
ProjectModel.Xilinx

+
+
+
+
+
+
+
ProjectModel/Xilinx/__init__.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""A vendor specific package for Xilinx."""
+

+
+
diff --git a/typing/html/ProjectModel/__init__.py.html b/typing/html/ProjectModel/__init__.py.html
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+
+
+
+
+
+
+
ProjectModel

+
+
+
+
+
+
+
ProjectModel/__init__.py
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+
# ==================================================================================================================== #
+#               _____ ____    _        _      ____            _           _   __  __           _      _                #
+#   _ __  _   _| ____|  _ \  / \      / \    |  _ \ _ __ ___ (_) ___  ___| |_|  \/  | ___   __| | ___| |               #
+#  | '_ \| | | |  _| | | | |/ _ \    / _ \   | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ |               #
+#  | |_) | |_| | |___| |_| / ___ \  / ___ \ _|  __/| | | (_) | |  __/ (__| |_| |  | | (_) | (_| |  __/ |               #
+#  | .__/ \__, |_____|____/_/   \_\/_/   \_(_)_|   |_|  \___// |\___|\___|\__|_|  |_|\___/ \__,_|\___|_|               #
+#  |_|    |___/                                            |__/                                                        #
+# ==================================================================================================================== #
+# Authors:                                                                                                             #
+#   Patrick Lehmann                                                                                                    #
+#                                                                                                                      #
+# License:                                                                                                             #
+# ==================================================================================================================== #
+# Copyright 2017-2023 Patrick Lehmann - Boetzingen, Germany                                                            #
+# Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture     #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#   http://www.apache.org/licenses/LICENSE-2.0                                                                         #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+#                                                                                                                      #
+# SPDX-License-Identifier: Apache-2.0                                                                                  #
+# ==================================================================================================================== #
+#
+"""An abstract model of EDA tool projects."""
+__author__ =    "Patrick Lehmann"
+__email__ =     "Paebbels@gmail.com"
+__copyright__ = "2014-2023, Patrick Lehmann, Unai Martinez-Corral"
+__license__ =   "Apache License, Version 2.0"
+__version__ =   "0.5.0"
+__keywords__ =  ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"]
+
+from os.path import relpath as path_relpath
+from pathlib import Path as pathlib_Path
+from typing  import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any
+
+from pyTooling.Decorators  import export
+from pyTooling.MetaClasses import ExtendedType
+from pyTooling.Graph       import Graph, Vertex
+from pySVModel             import SystemVerilogVersion
+from pyVHDLModel           import VHDLVersion
+from pySystemRDLModel      import SystemRDLVersion
+
+
+@export
+class Attribute(metaclass=ExtendedType):
+	KEY: str
+	VALUE_TYPE: typing_Any
+
+	@staticmethod
+	def resolve(obj: typing_Any, key: Type['Attribute']):
+		if isinstance(obj, File):
+			return obj._fileSet[key]
+		elif isinstance(obj, FileSet):
+			return obj._design[key]
+		elif isinstance(obj, Design):
+			return obj._project[key]
+		else:
+			raise Exception("Resolution error")
+
+
+@export
+class FileType(ExtendedType):
+	"""
+	A :term:`meta-class` to construct *FileType* classes.
+
+	Modifications done by this meta-class:
+	* Register all classes of type :class:`FileType` or derived variants in a class field :attr:`FileType.FileTypes` in this meta-class.
+	"""
+
+	FileTypes: Dict[str, 'FileType'] = {}     #: Dictionary of all classes of type :class:`FileType` or derived variants
+	Any: 'FileType'
+
+	def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs):
+		super().__init__(name, bases, dictionary, **kwargs)
+		cls.Any = cls
+
+	def __new__(cls, className, baseClasses, classMembers: Dict, *args, **kwargs):
+		fileType = super().__new__(cls, className, baseClasses, classMembers, *args, **kwargs)
+		cls.FileTypes[className] = fileType
+		return fileType
+
+	def __getattr__(cls, item) -> 'FileType':
+		if item[:2] != "__" and item[-2:] != "__":
+			return cls.FileTypes[item]
+		else:
+			return super().__getattribute__(item)
+
+	def __contains__(cls, item) -> bool:
+		return issubclass(item, cls)
+
+
+@export
+class File(metaclass=FileType, slots=True):
+	"""
+	A :term:`File` represents a file in a design. This :term:`base-class` is used
+	for all derived file classes.
+
+	A file can be created standalone and later associated to a fileset, design and
+	project. Or a fileset, design and/or project can be associated immediately
+	while creating a file.
+
+	:arg path:    Relative or absolute path to the file.
+	:arg project: Project the file is associated with.
+	:arg design:  Design the file is associated with.
+	:arg fileSet: Fileset the file is associated with.
+	"""
+
+	_path:       pathlib_Path
+	_fileType:   'FileType'
+	_project:    Nullable['Project']
+	_design:     Nullable['Design']
+	_fileSet:    Nullable['FileSet']
+	_attributes: Dict[Type[Attribute], typing_Any]
+
+	def __init__(
+		self,
+		path: pathlib_Path,
+		project: 'Project' = None,
+		design: 'Design' = None,
+		fileSet: 'FileSet' = None
+	):
+		self._fileType =  getattr(FileTypes, self.__class__.__name__)
+		self._path =      path
+		if project is not None:
+			self._project = project
+			self._design =  design
+			if fileSet is not None:
+				self.FileSet =  fileSet
+		elif design is not None:
+			self._project = design._project
+			self._design =  design
+			self.FileSet =  design.DefaultFileSet if fileSet is None else fileSet
+		elif fileSet is not None:
+			design = fileSet._design
+			if design is not None:
+				self._project = design._project
+			else:
+				self._project = None
+			self._design =    design
+			self.FileSet =    fileSet
+		else:
+			self._project = None
+			self._design =  None
+			self._fileSet = None
+
+		self._attributes = {}
+		self._registerAttributes()
+
+	def _registerAttributes(self):
+		pass
+
+	@property
+	def FileType(self) -> 'FileType':
+		"""Read-only property to return the file type of this file."""
+		return self._fileType
+
+	@property
+	def Path(self) -> pathlib_Path:
+		"""Read-only property returning the path of this file."""
+		return self._path
+
+	# TODO: setter?
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this file."""
+		if self._path.is_absolute():
+			return self._path.resolve()
+		elif self._fileSet is not None:
+			path = (self._fileSet.ResolvedPath / self._path).resolve()
+
+			if path.is_absolute():
+				return path
+			else:
+				# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+				return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+		else:
+			# TODO: message and exception type
+			raise Exception("")
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this file is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		self._project = value
+
+		if self._fileSet is None:
+			self._project.DefaultDesign.DefaultFileSet.AddFile(self)
+
+	@property
+	def Design(self) -> Nullable['Design']:
+		"""Property setting or returning the design this file is used in."""
+		return self._design
+
+	@Design.setter
+	def Design(self, value: 'Design') -> None:
+		self._design = value
+
+		if self._fileSet is None:
+			self._design.DefaultFileSet.AddFile(self)
+
+		if self._project is None:
+			self._project = value._project
+		elif self._project is not value._project:
+			raise Exception("The design's project is not identical to the already assigned project.")
+
+	@property
+	def FileSet(self) -> Nullable['FileSet']:
+		"""Property setting or returning the fileset this file is used in."""
+		return self._fileSet
+
+	@FileSet.setter
+	def FileSet(self, value: 'FileSet') -> None:
+		self._fileSet = value
+		value._files.append(self)
+
+	def Validate(self):
+		"""Validate this file."""
+		if self._path is None:
+			raise Exception("Validation: File has no path.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: File '{self._path}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: File '{self._path}' (={path}) does not exist.")
+		if not path.is_file():
+			raise Exception(f"Validation: File '{self._path}' (={path}) is not a file.")
+
+		if self._fileSet is None:
+			raise Exception(f"Validation: File '{self._path}' has no fileset.")
+		if self._design is None:
+			raise Exception(f"Validation: File '{self._path}' has no design.")
+		if self._project is None:
+			raise Exception(f"Validation: File '{self._path}' has no project.")
+
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this file.
+
+		:returns: The number if attributes set on this file.
+		"""
+		return len(self._attributes)
+
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this file.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)
+
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this file.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value
+
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this file.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]
+
+	def __str__(self) -> str:
+		return f"{self._path}"
+
+
+FileTypes = File
+
+
+@export
+class HumanReadableContent(metaclass=ExtendedType, mixin=True):
+	"""A file type representing human-readable contents."""
+
+
+@export
+class XMLContent(HumanReadableContent, mixin=True):
+	"""A file type representing XML contents."""
+
+
+@export
+class YAMLContent(HumanReadableContent, mixin=True):
+	"""A file type representing YAML contents."""
+
+
+@export
+class JSONContent(HumanReadableContent, mixin=True):
+	"""A file type representing JSON contents."""
+
+
+@export
+class INIContent(HumanReadableContent, mixin=True):
+	"""A file type representing INI contents."""
+
+
+@export
+class TOMLContent(HumanReadableContent, mixin=True):
+	"""A file type representing TOML contents."""
+
+
+@export
+class TCLContent(HumanReadableContent, mixin=True):
+	"""A file type representing content in TCL code."""
+
+
+@export
+class SDCContent(TCLContent, mixin=True):
+	"""A file type representing contents as Synopsys Design Constraints (SDC)."""
+
+
+@export
+class PythonContent(HumanReadableContent, mixin=True):
+	"""A file type representing contents as Python source code."""
+
+
+@export
+class TextFile(File, HumanReadableContent):
+	"""A text file (``*.txt``)."""
+
+
+@export
+class LogFile(File, HumanReadableContent):
+	"""A log file (``*.log``)."""
+
+
+@export
+class XMLFile(File, XMLContent):
+	"""An XML file (``*.xml``)."""
+
+
+@export
+class SourceFile(File):
+	"""Base-class of all source files."""
+
+
+@export
+class HDLSourceFile(SourceFile):
+	"""Base-class of all HDL source files."""
+
+
+@export
+class RDLSourceFile(SourceFile):
+	"""Base-class of all RDL source files."""
+
+
+@export
+class NetlistFile(SourceFile):
+	"""Base-class of all netlist source files."""
+
+
+@export
+class EDIFNetlistFile(NetlistFile):
+	"""Netlist file in EDIF (Electronic Design Interchange Format)."""
+
+
+@export
+class TCLSourceFile(SourceFile, TCLContent):
+	"""A TCL source file."""
+
+
+@export
+class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
+	"""
+	A VHDL source file (of any language version).
+
+	:arg path:        Relative or absolute path to the file.
+	:arg vhdlLibrary: VHDLLibrary this VHDL source file is associated wih.
+	:arg vhdlVersion: VHDLVersion this VHDL source file is associated wih.
+	:arg project:     Project the file is associated with.
+	:arg design:      Design the file is associated with.
+	:arg fileSet:     Fileset the file is associated with.
+	"""
+
+	_vhdlLibrary: Nullable['VHDLLibrary']
+	_vhdlVersion: VHDLVersion
+
+	def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: VHDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
+		super().__init__(path, project, design, fileSet)
+
+		if isinstance(vhdlLibrary, str):
+			if design is not None:
+				try:
+					vhdlLibrary = design.VHDLLibraries[vhdlLibrary]
+				except KeyError as ex:
+					raise Exception(f"VHDL library '{vhdlLibrary}' not found in design '{design.Name}'.") from ex
+			elif project is not None:
+				try:
+					vhdlLibrary = project.DefaultDesign.VHDLLibraries[vhdlLibrary]
+				except KeyError as ex:
+					raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex
+			else:
+				raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
+		elif isinstance(vhdlLibrary, VHDLLibrary):
+			self._vhdlLibrary = vhdlLibrary
+			vhdlLibrary.AddFile(self)
+		elif vhdlLibrary is None:
+			self._vhdlLibrary = None
+		else:
+			raise TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
+
+		self._vhdlVersion = vhdlVersion
+
+	def Validate(self) -> None:
+		"""Validate this VHDL source file."""
+		super().Validate()
+
+		try:
+			_ = self.VHDLLibrary
+		except Exception as ex:
+			raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLLibrary assigned.") from ex
+		try:
+			_ = self.VHDLVersion
+		except Exception as ex:
+			raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLVersion assigned.") from ex
+
+	@property
+	def VHDLLibrary(self) -> 'VHDLLibrary':
+		"""Property setting or returning the VHDL library this VHDL source file is used in."""
+		if self._vhdlLibrary is not None:
+			return self._vhdlLibrary
+		elif self._fileSet is not None:
+			return self._fileSet.VHDLLibrary
+		else:
+			raise Exception("VHDLLibrary was neither set locally nor globally.")
+
+	@VHDLLibrary.setter
+	def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+		self._vhdlLibrary = value
+		value._files.append(self)
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		"""Property setting or returning the VHDL version this VHDL source file is used in."""
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._fileSet is not None:
+			return self._fileSet.VHDLVersion
+		else:
+			raise Exception("VHDLVersion was neither set locally nor globally.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	def __repr__(self) -> str:
+		return f"<VHDL file: '{self.ResolvedPath}'; lib: '{self.VHDLLibrary}'; version: {self.VHDLVersion}>"
+
+
+class VerilogMixIn(metaclass=ExtendedType, mixin=True):
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the Verilog version this Verilog source file is used in."""
+		if self._version is not None:
+			return self._version
+		elif self._fileSet is not None:
+			return self._fileSet.VerilogVersion
+		else:
+			raise Exception("VerilogVersion was neither set locally nor globally.")
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._version = value
+
+
+class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True):
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the SystemVerilog version this SystemVerilog source file is used in."""
+		if self._version is not None:
+			return self._version
+		elif self._fileSet is not None:
+			return self._fileSet.SVVersion
+		else:
+			raise Exception("SVVersion was neither set locally nor globally.")
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._version = value
+
+
+@export
+class VerilogBaseFile(HDLSourceFile, HumanReadableContent):
+	_version: SystemVerilogVersion
+
+	def __init__(self, path: pathlib_Path, version: SystemVerilogVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
+		super().__init__(path, project, design, fileSet)
+
+		self._version = version
+
+
+@export
+class VerilogSourceFile(VerilogBaseFile, VerilogMixIn):
+	"""A Verilog source file (of any language version)."""
+
+
+@export
+class VerilogHeaderFile(VerilogBaseFile, VerilogMixIn):
+	"""A Verilog header file (of any language version)."""
+
+
+@export
+class SystemVerilogBaseFile(VerilogBaseFile):
+	...
+
+
+@export
+class SystemVerilogSourceFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+	"""A SystemVerilog source file (of any language version)."""
+
+
+@export
+class SystemVerilogHeaderFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+	"""A SystemVerilog header file (of any language version)."""
+
+
+@export
+class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent):
+	"""A SystemRDL source file (of any language version)."""
+
+	_srdlVersion: SystemRDLVersion
+
+	def __init__(self, path: pathlib_Path, srdlVersion: SystemRDLVersion = None, project: 'Project' = None, design: 'Design' = None, fileSet: 'FileSet' = None):
+		super().__init__(path, project, design, fileSet)
+
+		self._srdlVersion = srdlVersion
+
+	@property
+	def SystemRDLVersion(self) -> SystemRDLVersion:
+		"""Property setting or returning the SystemRDL version this SystemRDL source file is used in."""
+		if self._srdlVersion is not None:
+			return self._srdlVersion
+		elif self._fileSet is not None:
+			return self._fileSet.SRDLVersion
+		else:
+			raise Exception("SRDLVersion was neither set locally nor globally.")
+
+	@SystemRDLVersion.setter
+	def SystemRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+
+@export
+class PythonSourceFile(SourceFile, PythonContent):
+	"""A Python source file."""
+
+
+# TODO: move to a Cocotb module
+@export
+class CocotbPythonFile(PythonSourceFile):
+	"""A Python source file used by Cocotb."""
+
+
+@export
+class ConstraintFile(File, HumanReadableContent):
+	"""Base-class of all constraint files."""
+
+
+@export
+class ProjectFile(File):
+	"""Base-class of all tool-specific project files."""
+
+
+@export
+class CSourceFile(SourceFile):
+	"""Base-class of all ANSI-C source files."""
+
+
+@export
+class CppSourceFile(SourceFile):
+	"""Base-class of all ANSI-C++ source files."""
+
+
+@export
+class SettingFile(File):
+	"""Base-class of all tool-specific setting files."""
+
+
+@export
+class SimulationAnalysisFile(File):
+	"""Base-class of all tool-specific analysis files."""
+
+
+@export
+class SimulationElaborationFile(File):
+	"""Base-class of all tool-specific elaboration files."""
+
+
+@export
+class SimulationStartFile(File):
+	"""Base-class of all tool-specific simulation start-up files."""
+
+
+@export
+class SimulationRunFile(File):
+	"""Base-class of all tool-specific simulation run (execution) files."""
+
+
+@export
+class WaveformConfigFile(File):
+	"""Base-class of all tool-specific waveform configuration files."""
+
+
+@export
+class WaveformDatabaseFile(File):
+	"""Base-class of all tool-specific waveform database files."""
+
+
+@export
+class WaveformExchangeFile(File):
+	"""Base-class of all tool-independent waveform exchange files."""
+
+
+@export
+class FileSet(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`FileSet` represents a group of files. Filesets can have sub-filesets.
+
+	The order of insertion is preserved. A fileset can be created standalone and
+	later associated to another fileset, design and/or project. Or a fileset,
+	design and/or project can be associated immediately while creating the
+	fileset.
+
+	:arg name:            Name of this fileset.
+	:arg topLevel:        Name of the fileset's toplevel.
+	:arg directory:       Path of this fileset (absolute or relative to a parent fileset or design).
+	:arg project:         Project the file is associated with.
+	:arg design:          Design the file is associated with.
+	:arg parent:          Parent fileset if this fileset is nested.
+	:arg vhdlLibrary:     Default VHDL library for files in this fileset, if not specified for the file itself.
+	:arg vhdlVersion:     Default VHDL version for files in this fileset, if not specified for the file itself.
+	:arg verilogVersion:  Default Verilog version for files in this fileset, if not specified for the file itself.
+	:arg svVersion:       Default SystemVerilog version for files in this fileset, if not specified for the file itself.
+	:arg srdlVersion:     Default SystemRDL version for files in this fileset, if not specified for the file itself.
+	"""
+
+	_name:            str
+	_topLevel:        Nullable[str]
+	_project:         Nullable['Project']
+	_design:          Nullable['Design']
+	_directory:       pathlib_Path
+	_parent:          Nullable['FileSet']
+	_fileSets:        Dict[str, 'FileSet']
+	_files:           List[File]
+	_set:             Set
+	_attributes:      Dict[Type[Attribute], typing_Any]
+	_vhdlLibraries:   Dict[str, 'VHDLLibrary']
+	_vhdlLibrary:     'VHDLLibrary'
+	_vhdlVersion:     VHDLVersion
+	_verilogVersion:  SystemVerilogVersion
+	_svVersion:       SystemVerilogVersion
+	_srdlVersion:     SystemRDLVersion
+
+	def __init__(
+		self,
+		name: str,
+		topLevel: str = None,
+		directory: pathlib_Path = pathlib_Path("."),
+		project: 'Project' = None,
+		design: 'Design' = None,
+		parent: Nullable['FileSet'] = None,
+		vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
+		vhdlVersion: VHDLVersion = None,
+		verilogVersion: SystemVerilogVersion = None,
+		svVersion: SystemVerilogVersion = None,
+		srdlVersion: SystemRDLVersion = None
+	):
+		self._name =      name
+		self._topLevel =  topLevel
+		if project is not None:
+			self._project = project
+			self._design =  design if design is not None else project.DefaultDesign
+
+		elif design is not None:
+			self._project = design._project
+			self._design =  design
+		else:
+			self._project = None
+			self._design =  None
+		self._directory = directory
+		self._parent =    parent
+		self._fileSets =  {}
+		self._files =     []
+		self._set =     set()
+
+		if design is not None:
+			design._fileSets[name] = self
+
+		self._attributes =      {}
+		self._vhdlLibraries =   {}
+
+		# TODO: handle if vhdlLibrary is a string
+		self._vhdlLibrary =     vhdlLibrary
+		self._vhdlVersion =     vhdlVersion
+		self._verilogVersion =  verilogVersion
+		self._svVersion =       svVersion
+		self._srdlVersion =     srdlVersion
+
+	@property
+	def Name(self) -> str:
+		"""Property setting or returning the fileset's name."""
+		return self._name
+
+	@Name.setter
+	def Name(self, value: str) -> None:
+		self._name = value
+
+	@property
+	def TopLevel(self) -> str:
+		"""Property setting or returning the fileset's toplevel."""
+		return self._topLevel
+
+	@TopLevel.setter
+	def TopLevel(self, value: str) -> None:
+		self._topLevel = value
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this fileset is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		self._project = value
+
+	@property
+	def Design(self) -> Nullable['Design']:
+		"""Property setting or returning the design this fileset is used in."""
+		if self._design is not None:
+			return self._design
+		elif self._parent is not None:
+			return self._parent.Design
+		else:
+			return None
+			# TODO: raise exception instead
+			# QUESTION: how to handle if design and parent is set?
+
+	@Design.setter
+	def Design(self, value: 'Design') -> None:
+		self._design = value
+		if self._project is None:
+			self._project = value._project
+		elif self._project is not value._project:
+			raise Exception("The design's project is not identical to the already assigned project.")
+
+	@property
+	def Directory(self) -> pathlib_Path:
+		"""Property setting or returning the directory this fileset is located in."""
+		return self._directory
+
+	@Directory.setter
+	def Directory(self, value: pathlib_Path) -> None:
+		self._directory = value
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this fileset."""
+		if self._directory.is_absolute():
+			return self._directory.resolve()
+		else:
+			if self._parent is not None:
+				directory = self._parent.ResolvedPath
+			elif self._design is not None:
+				directory = self._design.ResolvedPath
+			elif self._project is not None:
+				directory = self._project.ResolvedPath
+			else:
+				# TODO: message and exception type
+				raise Exception("")
+
+			directory = (directory / self._directory).resolve()
+			if directory.is_absolute():
+				return directory
+			else:
+				# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+				return pathlib_Path(path_relpath(directory, pathlib_Path.cwd()))
+
+	@property
+	def Parent(self) -> Nullable['FileSet']:
+		"""Property setting or returning the parent fileset this fileset is used in."""
+		return self._parent
+
+	@Parent.setter
+	def Parent(self, value: 'FileSet') -> None:
+		self._parent = value
+		value._fileSets[self._name] = self
+		# TODO: check it it already exists
+		# QUESTION: make an Add fileset method?
+
+	@property
+	def FileSets(self) -> Dict[str, 'FileSet']:
+		"""Read-only property returning the dictionary of sub-filesets."""
+		return self._fileSets
+
+	def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[bool, str, 'FileSet'] = None) -> Generator[File, None, None]:
+		"""
+		Method returning the files of this fileset.
+
+		:arg fileType: A filter for file types. Default: ``Any``.
+		:arg fileSet:  Specifies how to handle sub-filesets.
+		"""
+		if fileSet is False:
+			for file in self._files:
+				if file.FileType in fileType:
+					yield file
+		elif fileSet is None:
+			for fileSet in self._fileSets.values():
+				for file in fileSet.Files(fileType):
+					yield file
+			for file in self._files:
+				if file.FileType in fileType:
+					yield file
+		else:
+			if isinstance(fileSet, str):
+				fileSetName = fileSet
+				try:
+					fileSet = self._fileSets[fileSetName]
+				except KeyError as ex:
+					raise Exception(f"Fileset {fileSetName} not bound to fileset {self.Name}.") from ex
+			elif not isinstance(fileSet, FileSet):
+				raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+
+			for file in fileSet.Files(fileType):
+				yield file
+
+	def AddFileSet(self, fileSet: "FileSet") -> None:
+		"""
+		Method to add a single sub-fileset to this fileset.
+
+		:arg fileSet: A fileset to add to this fileset as sub-fileset.
+		"""
+		if not isinstance(fileSet, FileSet):
+			raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+		elif fileSet in self._fileSets:
+			raise Exception("Sub-fileset already contains this fileset.")
+		elif fileSet.Name in self._fileSets.keys():
+			raise Exception(f"Fileset already contains a sub-fileset named '{fileSet.Name}'.")
+
+		self._fileSets[fileSet.Name] = fileSet
+		fileSet._parent = self
+
+	def AddFileSets(self, fileSets: Iterable["FileSet"]) -> None:
+		"""
+		Method to add a multiple sub-filesets to this fileset.
+
+		:arg fileSets: An iterable of filesets to add each to the fileset.
+		"""
+		for fileSet in fileSets:
+			self.AddFileSet(fileSet)
+
+	@property
+	def FileSetCount(self) -> int:
+		"""Returns number of file sets excl. sub-filesets."""
+		return len(self._fileSets)
+
+	@property
+	def TotalFileSetCount(self) -> int:
+		"""Returns number of file sets incl. sub-filesets."""
+		fileSetCount = len(self._fileSets)
+		for fileSet in self._fileSets.values():
+			fileSetCount += fileSet.TotalFileSetCount
+
+		return fileSetCount
+
+	def AddFile(self, file: File) -> None:
+		"""
+		Method to add a single file to this fileset.
+
+		:arg file: A file to add to this fileset.
+		"""
+		if not isinstance(file, File):
+			raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
+		elif file._fileSet is not None:
+			ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
+			ex.add_note(f"A file can't be assigned to another fileset.")
+			raise ex
+		elif file in self._set:
+			ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
+			ex.add_note(f"A file can't be added twice to a fileset.")
+			raise ex
+
+		self._files.append(file)
+		self._set.add(file)
+		file._fileSet = self
+
+	def AddFiles(self, files: Iterable[File]) -> None:
+		"""
+		Method to add a multiple files to this fileset.
+
+		:arg files: An iterable of files to add each to the fileset.
+		"""
+		for file in files:
+			self.AddFile(file)
+
+	@property
+	def FileCount(self) -> int:
+		"""Returns number of files excl. sub-filesets."""
+		return len(self._files)
+
+	@property
+	def TotalFileCount(self) -> int:
+		"""Returns number of files incl. the files in sub-filesets."""
+		fileCount = len(self._files)
+		for fileSet in self._fileSets.values():
+			fileCount += fileSet.FileCount
+
+		return fileCount
+
+	def Validate(self) -> None:
+		"""Validate this fileset."""
+		if self._name is None or self._name == "":
+			raise Exception("Validation: FileSet has no name.")
+
+		if self._directory is None:
+			raise Exception(f"Validation: FileSet '{self._name}' has no directory.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: FileSet '{self._name}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' does not exist.")
+		if not path.is_dir():
+			raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' is not a directory.")
+
+		if self._design is None:
+			raise Exception(f"Validation: FileSet '{self._directory}' has no design.")
+		if self._project is None:
+			raise Exception(f"Validation: FileSet '{self._directory}' has no project.")
+
+		for fileSet in self._fileSets.values():
+			fileSet.Validate()
+		for file in self._files:
+			file.Validate()
+
+	def GetOrCreateVHDLLibrary(self, name) -> 'VHDLLibrary':
+		if name in self._vhdlLibraries:
+			return self._vhdlLibraries[name]
+		elif name in self._design._vhdlLibraries:
+			library = self._design._vhdlLibraries[name]
+			self._vhdlLibraries[name] = library
+			return library
+		else:
+			library = VHDLLibrary(name, design=self._design, vhdlVersion=self._vhdlVersion)
+			self._vhdlLibraries[name] = library
+			return library
+
+	@property
+	def VHDLLibrary(self) -> 'VHDLLibrary':
+		"""Property setting or returning the VHDL library of this fileset."""
+		if self._vhdlLibrary is not None:
+			return self._vhdlLibrary
+		elif self._parent is not None:
+			return self._parent.VHDLLibrary
+		elif self._design is not None:
+			return self._design.VHDLLibrary
+		else:
+			raise Exception("VHDLLibrary was neither set locally nor globally.")
+
+	@VHDLLibrary.setter
+	def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+		self._vhdlLibrary = value
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		"""Property setting or returning the VHDL version of this fileset."""
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._parent is not None:
+			return self._parent.VHDLVersion
+		elif self._design is not None:
+			return self._design.VHDLVersion
+		else:
+			raise Exception("VHDLVersion was neither set locally nor globally.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the Verilog version of this fileset."""
+		if self._verilogVersion is not None:
+			return self._verilogVersion
+		elif self._parent is not None:
+			return self._parent.VerilogVersion
+		elif self._design is not None:
+			return self._design.VerilogVersion
+		else:
+			raise Exception("VerilogVersion was neither set locally nor globally.")
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._verilogVersion = value
+
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		"""Property setting or returning the SystemVerilog version of this fileset."""
+		if self._svVersion is not None:
+			return self._svVersion
+		elif self._parent is not None:
+			return self._parent.SVVersion
+		elif self._design is not None:
+			return self._design.SVVersion
+		else:
+			raise Exception("SVVersion was neither set locally nor globally.")
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._svVersion = value
+
+	@property
+	def SRDLVersion(self) -> SystemRDLVersion:
+		if self._srdlVersion is not None:
+			return self._srdlVersion
+		elif self._parent is not None:
+			return self._parent.SRDLVersion
+		elif self._design is not None:
+			return self._design.SRDLVersion
+		else:
+			raise Exception("SRDLVersion was neither set locally nor globally.")
+
+	@SRDLVersion.setter
+	def SRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this fileset.
+
+		:returns: The number if attributes set on this fileset.
+		"""
+		return len(self._attributes)
+
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this fileset.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)
+
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this fileset.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value
+
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this fileset.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]
+
+	def __str__(self) -> str:
+		"""Returns the fileset's name."""
+		return self._name
+
+
+@export
+class VHDLLibrary(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library.
+
+	:arg name:        The VHDL libraries' name.
+	:arg project:     Project the VHDL library is associated with.
+	:arg design:      Design the VHDL library is associated with.
+	:arg vhdlVersion: Default VHDL version for files in this VHDL library, if not specified for the file itself.
+	"""
+
+	_name:        str
+	_project:     Nullable['Project']
+	_design:      Nullable['Design']
+	_files:       List[File]
+	_vhdlVersion: VHDLVersion
+
+	_dependencyNode: Vertex
+
+	def __init__(
+		self,
+		name: str,
+		project: 'Project' = None,
+		design: 'Design' = None,
+		vhdlVersion: VHDLVersion = None
+	):
+		self._name =    name
+		if project is not None:
+			self._project = project
+			self._design = project._defaultDesign if design is None else design
+			self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+
+			if name in self._design._vhdlLibraries:
+				raise Exception(f"Library '{name}' already in design '{self._design.Name}'.")
+			else:
+				self._design._vhdlLibraries[name] = self
+
+		elif design is not None:
+			self._project = design._project
+			self._design = design
+			self._dependencyNode = Vertex(value=self, graph=design._vhdlLibraryDependencyGraph)
+
+			if name in design._vhdlLibraries:
+				raise Exception(f"Library '{name}' already in design '{design.Name}'.")
+			else:
+				design._vhdlLibraries[name] = self
+
+		else:
+			self._project = None
+			self._design =  None
+			self._dependencyNode = None
+
+		self._files =     []
+		self._vhdlVersion = vhdlVersion
+
+	@property
+	def Name(self) -> str:
+		return self._name
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this VHDL library is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		if not isinstance(value, Project):
+			raise TypeError("Parameter 'value' is not of type 'Project'.")
+
+		if value is None:
+			# TODO: unlink VHDLLibrary from project
+			self._project = None
+		else:
+			self._project = value
+			if self._design is None:
+				self._design = value._defaultDesign
+
+	@property
+	def Design(self) -> Nullable['Design']:
+		"""Property setting or returning the design this VHDL library is used in."""
+		return self._design
+
+	@Design.setter
+	def Design(self, value: 'Design') -> None:
+		if not isinstance(value, Design):
+			raise TypeError("Parameter 'value' is not of type 'Design'.")
+
+		if value is None:
+			# TODO: unlink VHDLLibrary from design
+			self._design = None
+		else:
+			if self._design is None:
+				self._design = value
+				self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+			elif self._design is not value:
+				# TODO: move VHDLLibrary to other design
+				# TODO: create new vertex in dependency graph and remove vertex from old graph
+				self._design = value
+			else:
+				pass
+
+			if self._project is None:
+				self._project = value._project
+			elif self._project is not value._project:
+				raise Exception("The design's project is not identical to the already assigned project.")
+
+	@property
+	def Files(self) -> Generator[File, None, None]:
+		"""Read-only property to return all files in this VHDL library."""
+		for file in self._files:
+			yield file
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		"""Property setting or returning the VHDL version of this VHDL library."""
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._design is not None:
+			return self._design.VHDLVersion
+		else:
+			raise Exception("VHDLVersion is not set on VHDLLibrary nor parent object.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	def AddDependency(self, library: 'VHDLLibrary') -> None:
+		library.parent = self
+
+	def AddFile(self, vhdlFile: VHDLSourceFile) -> None:
+		if not isinstance(vhdlFile, VHDLSourceFile):
+			raise TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
+
+		self._files.append(vhdlFile)
+
+	def AddFiles(self, vhdlFiles: Iterable[VHDLSourceFile]) -> None:
+		for vhdlFile in vhdlFiles:
+			if not isinstance(vhdlFile, VHDLSourceFile):
+				raise TypeError(f"Item '{vhdlFile}' in parameter 'vhdlFiles' is not a 'VHDLSourceFile'.")
+
+			self._files.append(vhdlFile)
+
+	@property
+	def FileCount(self) -> int:
+		"""Returns number of files."""
+		return len(self._files)
+
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this VHDL library.
+
+		:returns: The number if attributes set on this VHDL library.
+		"""
+		return len(self._attributes)
+
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this VHDL library.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)
+
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this VHDL library.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value
+
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this VHDL library.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]
+
+	def __str__(self) -> str:
+		"""Returns the VHDL library's name."""
+		return self._name
+
+
+@export
+class Design(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`Design` represents a group of filesets and the source files therein.
+
+	Each design contains at least one fileset - the :term:`default fileset`. For
+	designs with VHDL source files, a independent `VHDLLibraries` overlay structure
+	exists.
+
+	:arg name:            The design's name.
+	:arg topLevel:        Name of the design's toplevel.
+	:arg directory:       Path of this design (absolute or relative to the project).
+	:arg project:         Project the design is associated with.
+	:arg vhdlVersion:     Default VHDL version for files in this design, if not specified for the file itself.
+	:arg verilogVersion:  Default Verilog version for files in this design, if not specified for the file itself.
+	:arg svVersion:       Default SystemVerilog version for files in this design, if not specified for the file itself.
+	:arg srdlVersion:     Default SystemRDL version for files in this fileset, if not specified for the file itself.
+	"""
+
+	_name:                  str
+	_topLevel:              Nullable[str]
+	_project:               Nullable['Project']
+	_directory:             pathlib_Path
+	_fileSets:              Dict[str, FileSet]
+	_defaultFileSet:        Nullable[FileSet]
+	_attributes:            Dict[Type[Attribute], typing_Any]
+
+	_vhdlLibraries:         Dict[str, VHDLLibrary]
+	_vhdlVersion:           VHDLVersion
+	_verilogVersion:        SystemVerilogVersion
+	_svVersion:             SystemVerilogVersion
+	_srdlVersion:           SystemRDLVersion
+	_externalVHDLLibraries: List
+
+	_vhdlLibraryDependencyGraph: Graph
+	_fileDependencyGraph:        Graph
+
+	def __init__(
+		self,
+		name: str,
+		topLevel: str = None,
+		directory: pathlib_Path = pathlib_Path("."),
+		project: 'Project' = None,
+		vhdlVersion: VHDLVersion = None,
+		verilogVersion: SystemVerilogVersion = None,
+		svVersion: SystemVerilogVersion = None,
+		srdlVersion: SystemRDLVersion = None
+	):
+		self._name =                  name
+		self._topLevel =              topLevel
+		self._project =               project
+		if project is not None:
+			project._designs[name] = self
+		self._directory =             directory
+		self._fileSets =              {}
+		self._defaultFileSet =        FileSet("default", project=project, design=self)
+		self._attributes =            {}
+		self._vhdlLibraries =         {}
+		self._vhdlVersion =           vhdlVersion
+		self._verilogVersion =        verilogVersion
+		self._svVersion =             svVersion
+		self._srdlVersion =           srdlVersion
+		self._externalVHDLLibraries = []
+
+		self._vhdlLibraryDependencyGraph = Graph()
+		self._fileDependencyGraph = Graph()
+
+	@property
+	def Name(self) -> str:
+		"""Property setting or returning the design's name."""
+		return self._name
+
+	@Name.setter
+	def Name(self, value: str) -> None:
+		self._name = value
+
+	@property
+	def TopLevel(self) -> str:
+		"""Property setting or returning the fileset's toplevel."""
+		return self._topLevel
+
+	@TopLevel.setter
+	def TopLevel(self, value: str) -> None:
+		self._topLevel = value
+
+	@property
+	def Project(self) -> Nullable['Project']:
+		"""Property setting or returning the project this design is used in."""
+		return self._project
+
+	@Project.setter
+	def Project(self, value: 'Project') -> None:
+		self._project = value
+
+	@property
+	def Directory(self) -> pathlib_Path:
+		"""Property setting or returning the directory this design is located in."""
+		return self._directory
+
+	@Directory.setter
+	def Directory(self, value: pathlib_Path) -> None:
+		self._directory = value
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this fileset."""
+		if self._directory.is_absolute():
+			return self._directory.resolve()
+		elif self._project is not None:
+			path = (self._project.ResolvedPath / self._directory).resolve()
+
+			if path.is_absolute():
+				return path
+			else:
+				# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+				return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+		else:
+			# TODO: message and exception type
+			raise Exception("")
+
+	@property
+	def DefaultFileSet(self) -> FileSet:
+		"""Property setting or returning the default fileset of this design."""
+		return self._defaultFileSet
+
+	@DefaultFileSet.setter
+	def DefaultFileSet(self, value: Union[str, FileSet]) -> None:
+		if isinstance(value, str):
+			if value not in self._fileSets.keys():
+				raise Exception(f"Fileset '{value}' is not in this design.")
+
+			self._defaultFileSet = self._fileSets[value]
+		elif isinstance(value, FileSet):
+			if value not in self.FileSets:
+				raise Exception(f"Fileset '{value}' is not associated to this design.")
+
+			self._defaultFileSet = value
+		else:
+			raise ValueError("Unsupported parameter type for 'value'.")
+
+	# TODO: return generator with another method
+	@property
+	def FileSets(self) -> Dict[str, FileSet]:
+		"""Read-only property returning the dictionary of filesets."""
+		return self._fileSets
+
+	def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]:
+		"""
+		Method returning the files of this design.
+
+		:arg fileType: A filter for file types. Default: ``Any``.
+		:arg fileSet:  Specifies if all files from all filesets (``fileSet=None``) are files from a single fileset are returned.
+		"""
+		if fileSet is None:
+			for fileSet in self._fileSets.values():
+				for file in fileSet.Files(fileType):
+					yield file
+		else:
+			if isinstance(fileSet, str):
+				try:
+					fileSet = self._fileSets[fileSet]
+				except KeyError as ex:
+					raise Exception(f"Fileset {fileSet.Name} not bound to design {self.Name}.") from ex
+			elif not isinstance(fileSet, FileSet):
+				raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+
+			for file in fileSet.Files(fileType):
+				yield file
+
+	def Validate(self) -> None:
+		"""Validate this design."""
+		if self._name is None or self._name == "":
+			raise Exception("Validation: Design has no name.")
+
+		if self._directory is None:
+			raise Exception(f"Validation: Design '{self._name}' has no directory.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: Design '{self._name}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: Design '{self._name}'s directory '{path}' does not exist.")
+		if not path.is_dir():
+			raise Exception(f"Validation: Design '{self._name}'s directory '{path}' is not a directory.")
+
+		if len(self._fileSets) == 0:
+			raise Exception(f"Validation: Design '{self._name}' has no fileset.")
+		try:
+			if self._defaultFileSet is not self._fileSets[self._defaultFileSet.Name]:
+				raise Exception(f"Validation: Design '{self._name}'s default fileset is the same as listed in filesets.")
+		except KeyError as ex:
+			raise Exception(f"Validation: Design '{self._name}'s default fileset is not in list of filesets.") from ex
+		if self._project is None:
+			raise Exception(f"Validation: Design '{self._path}' has no project.")
+
+		for fileSet in self._fileSets.values():
+			fileSet.Validate()
+
+	@property
+	def VHDLLibraries(self) -> Dict[str, VHDLLibrary]:
+		return self._vhdlLibraries
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		if self._vhdlVersion is not None:
+			return self._vhdlVersion
+		elif self._project is not None:
+			return self._project.VHDLVersion
+		else:
+			raise Exception("VHDLVersion was neither set locally nor globally.")
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		if self._verilogVersion is not None:
+			return self._verilogVersion
+		elif self._project is not None:
+			return self._project.VerilogVersion
+		else:
+			raise Exception("VerilogVersion was neither set locally nor globally.")
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._verilogVersion = value
+
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		if self._svVersion is not None:
+			return self._svVersion
+		elif self._project is not None:
+			return self._project.SVVersion
+		else:
+			raise Exception("SVVersion was neither set locally nor globally.")
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._svVersion = value
+
+	@property
+	def SRDLVersion(self) -> SystemRDLVersion:
+		if self._srdlVersion is not None:
+			return self._srdlVersion
+		elif self._project is not None:
+			return self._project.SRDLVersion
+		else:
+			raise Exception("SRDLVersion was neither set locally nor globally.")
+
+	@SRDLVersion.setter
+	def SRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+	@property
+	def ExternalVHDLLibraries(self) -> List:
+		return self._externalVHDLLibraries
+
+	def AddFileSet(self, fileSet: FileSet) -> None:
+		if not isinstance(fileSet, FileSet):
+			raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+		elif fileSet in self._fileSets:
+			raise Exception("Design already contains this fileset.")
+		elif fileSet.Name in self._fileSets.keys():
+			raise Exception(f"Design already contains a fileset named '{fileSet.Name}'.")
+
+		self._fileSets[fileSet.Name] = fileSet
+		fileSet.Design = self
+		fileSet._parent = self
+
+	def AddFileSets(self, fileSets: Iterable[FileSet]) -> None:
+		for fileSet in fileSets:
+			self.AddFileSet(fileSet)
+
+	@property
+	def FileSetCount(self) -> int:
+		"""Returns number of file sets excl. sub-filesets."""
+		return len(self._fileSets)
+
+	@property
+	def TotalFileSetCount(self) -> int:
+		"""Returns number of file sets incl. sub-filesets."""
+		fileSetCount = len(self._fileSets)
+		for fileSet in self._fileSets.values():
+			fileSetCount += fileSet.TotalFileSetCount
+
+		return fileSetCount
+
+	def AddFile(self, file: File) -> None:
+		if file.FileSet is None:
+			self._defaultFileSet.AddFile(file)
+		else:
+			raise ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}' and can't be assigned via Design to a default fileset.")
+
+	def AddFiles(self, files: Iterable[File]) -> None:
+		for file in files:
+			self.AddFile(file)
+
+	def AddVHDLLibrary(self, vhdlLibrary: VHDLLibrary) -> None:
+		if vhdlLibrary.Name in self._vhdlLibraries:
+			if self._vhdlLibraries[vhdlLibrary.Name] is vhdlLibrary:
+				raise Exception(f"The VHDLLibrary '{vhdlLibrary.Name}' was already added to the design.")
+			else:
+				raise Exception(f"A VHDLLibrary with same name ('{vhdlLibrary.Name}') already exists for this design.")
+
+
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this design.
+
+		:returns: The number if attributes set on this design.
+		"""
+		return len(self._attributes)
+
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this design.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)
+
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this design.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value
+
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this design.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]
+
+	def __str__(self) -> str:
+		return self._name
+
+
+@export
+class Project(metaclass=ExtendedType, slots=True):
+	"""
+	A :term:`Project` represents a group of designs and the source files therein.
+
+	:arg name:            The project's name.
+	:arg rootDirectory:   Base-path to the project.
+	:arg vhdlVersion:     Default VHDL version for files in this project, if not specified for the file itself.
+	:arg verilogVersion:  Default Verilog version for files in this project, if not specified for the file itself.
+	:arg svVersion:       Default SystemVerilog version for files in this project, if not specified for the file itself.
+	"""
+
+	_name:            str
+	_rootDirectory:   pathlib_Path
+	_designs:         Dict[str, Design]
+	_defaultDesign:   Design
+	_attributes:      Dict[Type[Attribute], typing_Any]
+
+	_vhdlVersion:     VHDLVersion
+	_verilogVersion:  SystemVerilogVersion
+	_svVersion:       SystemVerilogVersion
+	_srdlVersion:     SystemRDLVersion
+
+	def __init__(
+		self,
+		name: str,
+		rootDirectory: pathlib_Path = pathlib_Path("."),
+		vhdlVersion: VHDLVersion = None,
+		verilogVersion: SystemVerilogVersion = None,
+		svVersion: SystemVerilogVersion = None
+	):
+		self._name =            name
+		self._rootDirectory =   rootDirectory
+		self._designs =         {}
+		self._defaultDesign =   Design("default", project=self)
+		self._attributes =      {}
+		self._vhdlVersion =     vhdlVersion
+		self._verilogVersion =  verilogVersion
+		self._svVersion =       svVersion
+
+	@property
+	def Name(self) -> str:
+		"""Property setting or returning the project's name."""
+		return self._name
+
+	@property
+	def RootDirectory(self) -> pathlib_Path:
+		"""Property setting or returning the root directory this project is located in."""
+		return self._rootDirectory
+
+	@RootDirectory.setter
+	def RootDirectory(self, value: pathlib_Path) -> None:
+		self._rootDirectory = value
+
+	@property
+	def ResolvedPath(self) -> pathlib_Path:
+		"""Read-only property returning the resolved path of this fileset."""
+		path = self._rootDirectory.resolve()
+		if self._rootDirectory.is_absolute():
+			return path
+		else:
+			# WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+			return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+
+	# TODO: return generator with another method
+	@property
+	def Designs(self) -> Dict[str, Design]:
+		return self._designs
+
+	@property
+	def DefaultDesign(self) -> Design:
+		return self._defaultDesign
+
+	def Validate(self) -> None:
+		"""Validate this project."""
+		if self._name is None or self._name == "":
+			raise Exception("Validation: Project has no name.")
+
+		if self._rootDirectory is None:
+			raise Exception(f"Validation: Project '{self._name}' has no root directory.")
+		try:
+			path = self.ResolvedPath
+		except Exception as ex:
+			raise Exception(f"Validation: Project '{self._name}' could not compute resolved path.") from ex
+		if not path.exists():
+			raise Exception(f"Validation: Project '{self._name}'s directory '{path}' does not exist.")
+		if not path.is_dir():
+			raise Exception(f"Validation: Project '{self._name}'s directory '{path}' is not a directory.")
+
+		if len(self._designs) == 0:
+			raise Exception(f"Validation: Project '{self._name}' has no design.")
+		try:
+			if self._defaultDesign is not self._designs[self._defaultDesign.Name]:
+				raise Exception(f"Validation: Project '{self._name}'s default design is the same as listed in designs.")
+		except KeyError as ex:
+			raise Exception(f"Validation: Project '{self._name}'s default design is not in list of designs.") from ex
+
+		for design in self._designs.values():
+			design.Validate()
+
+	@property
+	def DesignCount(self) -> int:
+		"""Returns number of designs."""
+		return len(self._designs)
+
+	@property
+	def VHDLVersion(self) -> VHDLVersion:
+		# TODO: check for None and return exception
+		return self._vhdlVersion
+
+	@VHDLVersion.setter
+	def VHDLVersion(self, value: VHDLVersion) -> None:
+		self._vhdlVersion = value
+
+	@property
+	def VerilogVersion(self) -> SystemVerilogVersion:
+		# TODO: check for None and return exception
+		return self._verilogVersion
+
+	@VerilogVersion.setter
+	def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+		self._verilogVersion = value
+
+	@property
+	def SVVersion(self) -> SystemVerilogVersion:
+		# TODO: check for None and return exception
+		return self._svVersion
+
+	@SVVersion.setter
+	def SVVersion(self, value: SystemVerilogVersion) -> None:
+		self._svVersion = value
+
+	@property
+	def SRDLVersion(self) -> SystemRDLVersion:
+		# TODO: check for None and return exception
+		return self._srdlVersion
+
+	@SRDLVersion.setter
+	def SRDLVersion(self, value: SystemRDLVersion) -> None:
+		self._srdlVersion = value
+
+	def __len__(self) -> int:
+		"""
+		Returns number of attributes set on this project.
+
+		:returns: The number if attributes set on this project.
+		"""
+		return len(self._attributes)
+
+	def __getitem__(self, key: Type[Attribute]) -> Any:
+		"""Index access for returning attributes on this project.
+
+		:param key:        The attribute type.
+		:returns:          The attribute's value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		try:
+			return self._attributes[key]
+		except KeyError:
+			return key.resolve(self, key)
+
+	def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+		"""
+		Index access for adding or setting attributes on this project.
+
+		:param key:        The attribute type.
+		:param value:      The attributes value.
+		:raises TypeError: When parameter 'key' is not a subclass of Attribute.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		self._attributes[key] = value
+
+	def __delitem__(self, key: Type[Attribute]) -> None:
+		"""
+		Index access for deleting attributes on this project.
+
+		:param key: The attribute type.
+		"""
+		if not issubclass(key, Attribute):
+			raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+		del self._attributes[key]
+
+	def __str__(self) -> str:
+		return self._name
+

+
+
diff --git a/typing/index.html b/typing/index.html
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+
+
+
+
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+
+
Mypy Type Check Coverage Summary

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Summary from index
FileImprecisionLines
Total14.11% imprecise2735 LOC
ProjectModel11.49% imprecise1853 LOC
ProjectModel.Altera0.00% imprecise31 LOC
ProjectModel.Altera.Quartus2.27% imprecise44 LOC
ProjectModel.Attributes7.55% imprecise53 LOC
ProjectModel.GHDL2.56% imprecise39 LOC
ProjectModel.Intel0.00% imprecise31 LOC
ProjectModel.Intel.QuartusPrime2.27% imprecise44 LOC
ProjectModel.MentorGraphics0.00% imprecise31 LOC
ProjectModel.MentorGraphics.ModelSim2.04% imprecise49 LOC
ProjectModel.MentorGraphics.QuestaSim2.04% imprecise49 LOC
ProjectModel.OSVVM38.02% imprecise192 LOC
ProjectModel.VHDL0.00% imprecise0 LOC
ProjectModel.Verilog2.56% imprecise39 LOC
ProjectModel.Xilinx0.00% imprecise31 LOC
ProjectModel.Xilinx.ISE2.27% imprecise44 LOC
ProjectModel.Xilinx.Vivado43.41% imprecise205 LOC

+
+
diff --git a/typing/mypy-html.css b/typing/mypy-html.css
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+/* CSS for type check coverage reports */
+
+/*
+    Used by both summary and file.
+*/
+body {
+    font-family: "Helvetica Neue", sans-serif;
+}
+
+/*
+    Used only by summary.
+*/
+
+h1 {
+    text-align: center;
+    font-size: 135%;
+    margin: 20px;
+}
+
+table.summary {
+    border-collapse: collapse;
+    margin-left: 7%;
+    margin-right: 7%;
+    width: 85%;
+}
+
+table caption {
+    margin: 1em;
+}
+
+table.summary, tr.summary, th.summary, td.summary {
+    border: 1px solid #aaa;
+}
+
+th.summary, td.summary {
+    padding: 0.4em;
+}
+
+td.summary a {
+    text-decoration: none;
+}
+
+.summary-quality-0 {
+    background-color: #dfd;
+}
+
+.summary-quality-1 {
+    background-color: #ffa;
+}
+
+.summary-quality-2 {
+    background-color: #faa;
+}
+
+td.summary-filename, th.summary-filename {
+    text-align: left;
+}
+
+td.summary-filename {
+    width: 50%;
+}
+
+.summary-precision {
+    text-align: center;
+}
+
+.summary-lines {
+    text-align: center;
+}
+
+/*
+    Used only by file.
+*/
+
+td.table-lines {
+    text-align: right;
+    padding-right: 0.5em;
+}
+
+td.table-code { }
+
+span.lineno {
+    text-align: right;
+}
+
+a:link.lineno, a:visited.lineno {
+    color: #999; text-decoration: none;
+}
+
+a:hover.lineno, a:active.lineno {
+    color: #000; text-decoration: underline;
+}
+
+.line-empty, .line-precise {
+    background-color: #dfd;
+}
+
+.line-imprecise {
+    background-color: #ffa;
+}
+
+.line-any, .line-unanalyzed {
+    background-color: #faa;
+}