Introduction
+ +Main Documentation
+ +References
+ +Appendix
+| + | + |
|---|---|
Package |
+Version |
+License |
+Dependencies |
+
|---|---|---|---|
| + | ≥7.0 |
++ | None |
+
| + | ≥0.27.1 |
++ | + | +
| + | ≥0.3.1 |
++ | + | +
| + | ≥0.1.0 |
++ | + | +
Additional Python packages needed for testing, code coverage collection and static type checking. These packages are +only needed for developers or on a CI server, thus sub-dependencies are not evaluated further.
+Manually Installing Test Requirements
+Use the tests/requirements.txt file to install all dependencies via pip3. The file will recursively install
+the mandatory dependencies too.
+ 
pip3 install -U -r tests/requirements.txt
+Dependency List
+Additional Python packages needed for documentation generation. These packages are only needed for developers or on a +CI server, thus sub-dependencies are not evaluated further.
+Manually Installing Documentation Requirements
+Use the doc/requirements.txt file to install all dependencies via pip3. The file will recursively install
+the mandatory dependencies too.
pip3 install -U -r doc/requirements.txt
+Dependency List
+Package |
+Version |
+License |
+Dependencies |
+
|---|---|---|---|
| + | ≥7.0 |
++ | None |
+
| + | ≥8.1 |
++ | Not yet evaluated. |
+
| + | ≥0.5.2 |
++ | Not yet evaluated. |
+
| + | ≥0.0.6 |
++ | Not yet evaluated. |
+
| + | ≥2.5 |
++ | Not yet evaluated. |
+
Additional Python packages needed for installation package generation. These packages are only needed for developers or +on a CI server, thus sub-dependencies are not evaluated further.
+Manually Installing Packaging Requirements
+Use the build/requirements.txt file to install all dependencies via pip3. The file will recursively
+install the mandatory dependencies too.
pip3 install -U -r build/requirements.txt
+Dependency List
+Package |
+Version |
+License |
+Dependencies |
+
|---|---|---|---|
| + | ≥7.0 |
++ | None |
+
| + | ≥0.44 |
++ | Not yet evaluated. |
+
Additional Python packages needed for publishing the generated installation package to e.g, PyPI or any equivalent +services. These packages are only needed for maintainers or on a CI server, thus sub-dependencies are not evaluated +further.
+Manually Installing Publishing Requirements
+Use the dist/requirements.txt file to install all dependencies via pip3. The file will recursively
+install the mandatory dependencies too.
pip3 install -U -r dist/requirements.txt
+Dependency List
+Package |
+Version |
+License |
+Dependencies |
+
|---|---|---|---|
| + | ≥0.44 |
++ | Not yet evaluated. |
+
| + | ≥5.1 |
++ | Not yet evaluated. |
+
Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Note
+This is a local copy of the Creative Commons - Attribution 4.0 International (CC BY 4.0).
+Attention
+This CC BY 4.0 license applies only to the documentation of this project.
+Creative Commons Corporation (“Creative Commons”) is not a law firm and does not +provide legal services or legal advice. Distribution of Creative Commons public +licenses does not create a lawyer-client or other relationship. Creative Commons +makes its licenses and related information available on an “as-is” basis. +Creative Commons gives no warranties regarding its licenses, any material +licensed under their terms and conditions, or any related information. Creative +Commons disclaims all liability for damages resulting from their use to the +fullest extent possible.
+ +:xlarge:`Creative Commons Attribution 4.0 International Public License`
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Share means to provide material to the public by any means or process +that requires permission under the Licensed Rights, such as reproduction, +public display, public performance, distribution, dissemination, +communication, or importation, and to make material available to the public +including in ways that members of the public may access the material from a +place and at a time individually chosen by them.
Sui Generis Database Rights means rights other than copyright +resulting from Directive 96/9/EC of the European Parliament and of the +Council of 11 March 1996 on the legal protection of databases, as amended +and/or succeeded, as well as other essentially equivalent rights anywhere +in the world.
You means the individual or entity exercising the Licensed Rights +under this Public License. Your has a corresponding meaning.
License grant.
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++++
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:underline:`Downstream recipients.`
++++
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- +
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Other rights.
+Moral rights, such as the right of integrity, are not licensed under this +Public License, nor are publicity, privacy, and/or other similar +personality rights; however, to the extent possible, the Licensor waives +and/or agrees not to assert any such rights held by the Licensor to the +limited extent necessary to allow You to exercise the Licensed Rights, but +not otherwise.
Patent and trademark rights are not licensed under this Public License.
To the extent possible, the Licensor waives any right to collect royalties +from You for the exercise of the Licensed Rights, whether directly or +through a collecting society under any voluntary or waivable statutory or +compulsory licensing scheme. In all other cases the Licensor expressly +reserves any right to collect such royalties.
Your exercise of the Licensed Rights is expressly made subject to the following conditions.
+Attribution.
+If You Share the Licensed Material (including in modified form), You must:
++++
+- +
retain the following if it is supplied by the Licensor with the +Licensed Material:
+++
+- +
identification of the creator(s) of the Licensed Material and any +others designated to receive attribution, in any reasonable manner +requested by the Licensor (including by pseudonym if designated);
- +
a copyright notice;
- +
a notice that refers to this Public License;
- +
a notice that refers to the disclaimer of warranties;
- +
a URI or hyperlink to the Licensed Material to the extent reasonably +practicable;
+
+- +
indicate if You modified the Licensed Material and retain an +indication of any previous modifications; and
- +
indicate the Licensed Material is licensed under this Public License, +and include the text of, or the URI or hyperlink to, this Public +License.
You may satisfy the conditions in Section 3(a)(1) in any reasonable manner +based on the medium, means, and context in which You Share the Licensed +Material. For example, it may be reasonable to satisfy the conditions by +providing a URI or hyperlink to a resource that includes the required +information.
If requested by the Licensor, You must remove any of the information +required by Section 3(a)(1)(A) to the extent reasonably practicable.
If You Share Adapted Material You produce, the Adapter’s License You apply +must not prevent recipients of the Adapted Material from complying with +this Public License.
Where the Licensed Rights include Sui Generis Database Rights that apply to Your +use of the Licensed Material:
+for the avoidance of doubt, Section 2(a)(1) grants You the right to extract, +reuse, reproduce, and Share all or a substantial portion of the contents of +the database;
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For the avoidance of doubt, this Section 4 supplements and does not replace +Your obligations under this Public License where the Licensed Rights include +other Copyright and Similar Rights.
+Unless otherwise separately undertaken by the Licensor, to the extent +possible, the Licensor offers the Licensed Material as-is and as-available, +and makes no representations or warranties of any kind concerning the +Licensed Material, whether express, implied, statutory, or other. This +includes, without limitation, warranties of title, merchantability, +fitness for a particular purpose, non-infringement, absence of latent or +other defects, accuracy, or the presence or absence of errors, whether or +not known or discoverable. Where disclaimers of warranties are not allowed +in full or in part, this disclaimer may not apply to You.
To the extent possible, in no event will the Licensor be liable to You +on any legal theory (including, without limitation, negligence) or +otherwise for any direct, special, indirect, incidental, consequential, +punitive, exemplary, or other losses, costs, expenses, or damages arising +out of this Public License or use of the Licensed Material, even if the +Licensor has been advised of the possibility of such losses, costs, expenses, +or damages. Where a limitation of liability is not allowed in full or in +part, this limitation may not apply to You.
The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability.
This Public License applies for the term of the Copyright and Similar Rights +licensed here. However, if You fail to comply with this Public License, then +Your rights under this Public License terminate automatically.
Where Your right to use the Licensed Material has terminated under +Section 6(a), it reinstates:
+automatically as of the date the violation is cured, provided it is cured +within 30 days of Your discovery of the violation; or
upon express reinstatement by the Licensor.
For the avoidance of doubt, this Section 6(b) does not affect any right the +Licensor may have to seek remedies for Your violations of this Public License.
+For the avoidance of doubt, the Licensor may also offer the Licensed Material +under separate terms or conditions or stop distributing the Licensed Material +at any time; however, doing so will not terminate this Public License.
Sections 1, 5, 6, 7, and 8 survive termination of this Public License.
The Licensor shall not be bound by any additional or different terms or +conditions communicated by You unless expressly agreed.
Any arrangements, understandings, or agreements regarding the Licensed +Material not stated herein are separate from and independent of the terms +and conditions of this Public License.
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To the extent possible, if any provision of this Public License is deemed +unenforceable, it shall be automatically reformed to the minimum extent +necessary to make it enforceable. If the provision cannot be reformed, it +shall be severed from this Public License without affecting the +enforceability of the remaining terms and conditions.
No term or condition of this Public License will be waived and no failure to +comply consented to unless expressly agreed to by the Licensor.
Nothing in this Public License constitutes or may be interpreted as a +limitation upon, or waiver of, any privileges and immunities that apply to +the Licensor or You, including from the legal processes of any jurisdiction +or authority.
Creative Commons is not a party to its public licenses. Notwithstanding, +Creative Commons may elect to apply one of its public licenses to material it +publishes and in those instances will be considered the “Licensor.” Except for +the limited purpose of indicating that material is shared under a Creative +Commons public license or as otherwise permitted by the Creative Commons +policies published at creativecommons.org/policies, +Creative Commons does not authorize the use of the trademark “Creative Commons” +or any other trademark or logo of Creative Commons without its prior written +consent including, without limitation, in connection with any unauthorized +modifications to any of its public licenses or any other arrangements, +understandings, or agreements concerning use of licensed material. For the +avoidance of doubt, this paragraph does not form part of the public licenses.
+Creative Commons may be contacted at creativecommons.org
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Design Goals
+TBD
++ graph TD; + HRC[HumanReadableContent] --> XMLC[XMLContent]; + HRC --> YAMLC[YAMLContent]; + HRC --> JSONC[JSONContent]; + HRC --> INIC[INIContent]; + HRC --> TOMLC[TOMLContent]; + HRC --> TCLC[TCLContent] --> SDCC[SDCContent]; +
+ graph TD; + File-->TextFile; + File-->LogFile; + File-->XMLFile; + File--->SourceFile; + File-->ConstraintFile; + File-->ProjectFile; + File-->SettingFile; + SourceFile-->HDLSourceFile; + SourceFile-->NetlistFile; + NetlistFile-->EDIFNetlistFile; + HDLSourceFile-->VHDLSourceFile; + HDLSourceFile-->VerilogSourceFile; + HDLSourceFile-->SystemVerilogSourceFile; + SourceFile-->PythonSourceFile; + PythonSourceFile-->CocotbSourceFile + SourceFile-->CSourceFile; + SourceFile-->CppSourceFile; +
Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Language Reference Manual is the name given to IEEE Standard documents defining Hardware Description Languages:
+ +An ancestor class for other derived classes.
+A representation of a physical file.
+A group of files.
+If no fileset is specified, the pre-existing fileset named default is used to group files.
A namespace in VHDL to group and organize VHDL design units (entity, package, configuration, context).
+A …
+A …
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Note
+Python ≥3.7 is required for this package due to problems with meta classes and
+__getattr__ in Python 3.6.
+ pip3 install pyEDAA.ProjectModel
+pip3 install -U pyEDAA.ProjectModel
+pip3 uninstall pyEDAA.ProjectModel
+pip3 install .
+setup.py (legacy)¶See sections above on how to use PIP.
+setup.py¶setup.py install
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Note
+This is a local copy of the Apache License Version 2.0.
+Attention
+This Apache License, 2.0 applies to all source and configuration files of project, except documentation.
+Version 2.0, January 2004
+:xlarge:`TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION`
+“License” shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
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+“You” (or “Your”) shall mean an individual or Legal Entity exercising permissions granted by this License.
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+“Work” shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is +included in or attached to the work (an example is provided in the Appendix below).
+“Derivative Works” shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, +annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works +shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
+“Contribution” shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative +Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to +submit on behalf of the copyright owner. For the purposes of this definition, “submitted” means any form of electronic, verbal, or written communication +sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue +tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is +conspicuously marked or otherwise designated in writing by the copyright owner as “Not a Contribution.”
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+Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and +conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any +separate license agreement you may have executed with Licensor regarding such Contributions.
+This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable +and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
+Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an “AS IS” BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, +MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and +assume any risks associated with Your exercise of permissions under this License.
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+While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other +liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
+:xlarge:`Appendix: How to apply the Apache License to your work`
+To apply the Apache License to your work, attach the following boilerplate notice, with the fields enclosed by brackets “[]” replaced with your own identifying +information. (Don’t include the brackets!) The text should be enclosed in the appropriate comment syntax for the file format. We also recommend that a file or +class name and description of purpose be included on the same “printed page” as the copyright notice for easier identification within third-party archives.
+Copyright [yyyy] [name of copyright owner]
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Generic description of an EDA design.
+Todo
+Write documentation.
+Class Relationship
++ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style Design fill:#ee9b00 +
Design¶@export
+class Design:
+ _name: str
+ _project: Nullable['Project']
+ _directory: Nullable[Path]
+ _fileSets: Dict[str, FileSet]
+ _defaultFileSet: Nullable[FileSet]
+ _vhdlLibraries: Dict[str, VHDLLibrary]
+ _vhdlVersion: VHDLVersion
+ _verilogVersion: VerilogVersion
+ _svVersion: SystemVerilogVersion
+ _externalVHDLLibraries: List
+
+ def __init__(
+ self,
+ name: str,
+ directory: Path = Path("."),
+ project: 'Project' = None,
+ vhdlVersion: VHDLVersion = None,
+ verilogVersion: VerilogVersion = None,
+ svVersion: SystemVerilogVersion = None
+ ):
+
+ @property
+ def Name(self) -> str:
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+
+ @property
+ def Directory(self) -> Path:
+ @Directory.setter
+ def Directory(self, value: Path) -> None:
+
+ @property
+ def ResolvedPath(self) -> Path:
+
+ @property
+ def DefaultFileSet(self) -> FileSet:
+ @DefaultFileSet.setter
+ def DefaultFileSet(self, value: Union[str, FileSet]) -> None:
+
+ @property
+ def FileSets(self) -> Dict[str, FileSet]:
+
+ def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]:
+
+ @property
+ def VHDLLibraries(self) -> List[VHDLLibrary]:
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+
+ @property
+ def VerilogVersion(self) -> VerilogVersion:
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: VerilogVersion) -> None:
+
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+
+ @property
+ def ExternalVHDLLibraries(self) -> List:
+
+ def AddFileSet(self, fileSet: FileSet) -> None:
+
+ def AddFileSets(self, fileSets: Iterable[FileSet]) -> None:
+
+ def AddFile(self, file: File) -> None:
+
+ def AddFiles(self, files: Iterable[File]) -> None:
+Introduction
+ +Main Documentation
+References
+ +Appendix
+Generic description of a file in EDA design.
+Todo
+Write documentation.
+Class Relationship
++ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style File fill:#ee9b00 +
File¶@export
+class File(metaclass=FileType):
+ _path: Path
+ _project: Nullable['Project']
+ _design: Nullable['Design']
+ _fileSet: Nullable['FileSet']
+
+ def __init__(
+ self,
+ path: Path,
+ project: 'Project' = None,
+ design: 'Design' = None,
+ fileSet: 'FileSet' = None
+ ):
+
+ @property
+ def FileType(self) -> 'FileType':
+
+ @property
+ def Path(self) -> Path:
+
+ @property
+ def ResolvedPath(self) -> Path:
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+
+ @property
+ def Design(self) -> Nullable['Design']:
+ @Design.setter
+ def Design(self, value: 'Design') -> None:
+
+ @property
+ def FileSet(self) -> Nullable['FileSet']:
+ @FileSet.setter
+ def FileSet(self, value: 'FileSet') -> None:
+Introduction
+ +Main Documentation
+References
+ +Appendix
+Generic description of an EDA file set (group of files).
+Todo
+Write documentation.
+Class Relationship
++ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style FileSet fill:#ee9b00 +
FileSet¶@export
+class FileSet:
+ _name: str
+ _project: Nullable['Project']
+ _design: Nullable['Design']
+ _directory: Nullable[Path]
+ _parent: Nullable['FileSet']
+ _fileSets: Dict[str, 'FileSet']
+ _files: List[File]
+
+ _vhdlLibrary: 'VHDLLibrary'
+ _vhdlVersion: VHDLVersion
+ _verilogVersion: VerilogVersion
+ _svVersion: SystemVerilogVersion
+
+ def __init__(
+ self,
+ name: str,
+ directory: Path = Path("."),
+ project: 'Project' = None,
+ design: 'Design' = None,
+ parent: Nullable['FileSet'] = None,
+ vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
+ vhdlVersion: VHDLVersion = None,
+ verilogVersion: VerilogVersion = None,
+ svVersion: SystemVerilogVersion = None
+ ):
+
+ @property
+ def Name(self) -> str:
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+
+ @property
+ def Design(self) -> Nullable['Design']:
+ @Design.setter
+ def Design(self, value: 'Design') -> None:
+
+ @property
+ def Directory(self) -> Path:
+ @Directory.setter
+ def Directory(self, value: Path) -> None:
+
+ @property
+ def ResolvedPath(self) -> Path:
+
+ @property
+ def Parent(self) -> Nullable['FileSet']:
+ @Parent.setter
+ def Parent(self, value: 'FileSet') -> None:
+
+ @property
+ def FileSets(self) -> Dict[str, 'FileSet']:
+
+ def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, 'FileSet'] = None) -> Generator[File, None, None]:
+
+ def AddFile(self, file: File) -> None:
+
+ def AddFiles(self, files: Iterable[File]) -> None:
+
+ @property
+ def VHDLLibrary(self) -> 'VHDLLibrary':
+ @VHDLLibrary.setter
+ def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+
+ @property
+ def VerilogVersion(self) -> VerilogVersion:
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: VerilogVersion) -> None:
+
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+Introduction
+ +Main Documentation
+References
+ +Appendix
+Generic description of an EDA project.
+Todo
+Write documentation.
+Class Relationship
++ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style Project fill:#ee9b00 +
Project¶@export
+class Project:
+ _name: str
+ _rootDirectory: Nullable[Path]
+ _designs: Dict[str, Design]
+ _vhdlVersion: VHDLVersion
+ _verilogVersion: VerilogVersion
+ _svVersion: SystemVerilogVersion
+
+ def __init__(
+ self,
+ name: str,
+ rootDirectory: Path = Path("."),
+ vhdlVersion: VHDLVersion = None,
+ verilogVersion: VerilogVersion = None,
+ svVersion: SystemVerilogVersion = None
+ ):
+
+ @property
+ def Name(self) -> str:
+
+ @property
+ def RootDirectory(self) -> Path:
+ @RootDirectory.setter
+ def RootDirectory(self, value: Path) -> None:
+
+ @property
+ def ResolvedPath(self) -> Path:
+
+ @property
+ def Designs(self) -> Dict[str, Design]:
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+
+ @property
+ def VerilogVersion(self) -> VerilogVersion:
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: VerilogVersion) -> None:
+
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+Introduction
+ +Main Documentation
+References
+ +Appendix
+Generic description of a VHDL library (group of VHDL files containing VHDL primary units).
+Todo
+Write documentation.
+Class Relationship
++ graph TD; + Project --> Design; + Design --> VHDLLibrary; + Design --> FileSet; + VHDLLibrary --> File; + FileSet --> File + + style VHDLLibrary fill:#ee9b00 +
VHDLLibrary¶@export
+class VHDLLibrary:
+ _name: str
+ _project: Nullable['Project']
+ _design: Nullable['Design']
+ _files: List[File]
+ _vhdlVersion: VHDLVersion
+
+ def __init__(
+ self,
+ name: str,
+ project: 'Project' = None,
+ design: 'Design' = None,
+ vhdlVersion: VHDLVersion = None
+ ):
+
+ @property
+ def Name(self) -> str:
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ @Project.setter
+ def Project(self, value: 'Project'):
+
+ @property
+ def Design(self) -> Nullable['Design']:
+ @Design.setter
+ def Design(self, value: 'Design'):
+
+ @property
+ def Files(self) -> Generator[File, None, None]:
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+Introduction
+ +Main Documentation
+References
+ +Appendix
+Design Goals
+Clearly named classes that model the semantics of an EDA project.
Child objects shall have a reference to their parent.
Overall Hierarchy
+An EDA project contains one or multiple variants of a EDA design. +A design then has at least one but usually multiple file sets to group source files and apply settings or attributes to that group.
++ graph TD; + Project-->Design_A; + Project-->Design_B; + Design_A-->VHDLLibrary_LA; + Design_A-->FileSet_DefaultA; + Design_A-->FileSet_A1; + Design_A-->FileSet_A2; + FileSet_A2-->FileSet_3 + Design_B-->VHDLLibrary_LB; + Design_B-->FileSet_DefaultB; + Design_B-->FileSet_B1; + Design_B-->FileSet_B2; + FileSet_B2-->FileSet_3 +
Elements of the Project Model
+Introduction
+ +Main Documentation
+References
+ +Appendix
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""An abstract model of EDA tool projects."""
+__author__ = "Patrick Lehmann"
+__email__ = "Paebbels@gmail.com"
+__copyright__ = "2014-2024, Patrick Lehmann, Unai Martinez-Corral"
+__license__ = "Apache License, Version 2.0"
+__version__ = "0.5.0"
+__keywords__ = ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"]
+
+from os.path import relpath as path_relpath
+from pathlib import Path as pathlib_Path
+from sys import version_info
+from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any
+
+from pyTooling.Common import getFullyQualifiedName
+from pyTooling.Decorators import export
+from pyTooling.MetaClasses import ExtendedType
+from pyTooling.Graph import Graph, Vertex
+from pySVModel import SystemVerilogVersion
+from pyVHDLModel import VHDLVersion
+from pySystemRDLModel import SystemRDLVersion
+
+
+
+[docs]
+@export
+class Attribute(metaclass=ExtendedType):
+ KEY: str
+ VALUE_TYPE: typing_Any
+
+ @staticmethod
+ def resolve(obj: typing_Any, key: Type['Attribute']):
+ if isinstance(obj, File):
+ return obj._fileSet[key]
+ elif isinstance(obj, FileSet):
+ return obj._design[key]
+ elif isinstance(obj, Design):
+ return obj._project[key]
+ else:
+ raise Exception("Resolution error")
+
+
+
+
+[docs]
+@export
+class FileType(ExtendedType):
+ """
+ A :term:`meta-class` to construct *FileType* classes.
+
+ Modifications done by this meta-class:
+ * Register all classes of type :class:`FileType` or derived variants in a class field :attr:`FileType.FileTypes` in this meta-class.
+ """
+
+ FileTypes: Dict[str, 'FileType'] = {} #: Dictionary of all classes of type :class:`FileType` or derived variants
+ Any: 'FileType'
+
+
+[docs]
+ def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs):
+ super().__init__(name, bases, dictionary, **kwargs)
+ cls.Any = cls
+
+
+
+[docs]
+ def __new__(cls, className, baseClasses, classMembers: Dict, *args, **kwargs):
+ fileType = super().__new__(cls, className, baseClasses, classMembers, *args, **kwargs)
+ cls.FileTypes[className] = fileType
+ return fileType
+
+
+ def __getattr__(cls, item) -> 'FileType':
+ if item[:2] != "__" and item[-2:] != "__":
+ return cls.FileTypes[item]
+ else:
+ return super().__getattribute__(item)
+
+ def __contains__(cls, item) -> bool:
+ return issubclass(item, cls)
+
+
+
+
+[docs]
+@export
+class File(metaclass=FileType, slots=True):
+ """
+ A :term:`File` represents a file in a design. This :term:`base-class` is used
+ for all derived file classes.
+
+ A file can be created standalone and later associated to a fileset, design and
+ project. Or a fileset, design and/or project can be associated immediately
+ while creating a file.
+
+ :arg path: Relative or absolute path to the file.
+ :arg project: Project the file is associated with.
+ :arg design: Design the file is associated with.
+ :arg fileSet: Fileset the file is associated with.
+ """
+
+ _path: pathlib_Path
+ _fileType: 'FileType'
+ _project: Nullable['Project']
+ _design: Nullable['Design']
+ _fileSet: Nullable['FileSet']
+ _attributes: Dict[Type[Attribute], typing_Any]
+
+
+[docs]
+ def __init__(
+ self,
+ path: pathlib_Path,
+ project: Nullable["Project"] = None,
+ design: Nullable["Design"] = None,
+ fileSet: Nullable["FileSet"] = None
+ ):
+ self._fileType = getattr(FileTypes, self.__class__.__name__)
+ self._path = path
+ if project is not None:
+ self._project = project
+ self._design = design
+ if fileSet is not None:
+ self.FileSet = fileSet
+ elif design is not None:
+ self._project = design._project
+ self._design = design
+ self.FileSet = design.DefaultFileSet if fileSet is None else fileSet
+ elif fileSet is not None:
+ design = fileSet._design
+ if design is not None:
+ self._project = design._project
+ else:
+ self._project = None
+ self._design = design
+ self.FileSet = fileSet
+ else:
+ self._project = None
+ self._design = None
+ self._fileSet = None
+
+ self._attributes = {}
+ self._registerAttributes()
+
+
+ def _registerAttributes(self) -> None:
+ pass
+
+ @property
+ def FileType(self) -> 'FileType':
+ """Read-only property to return the file type of this file."""
+ return self._fileType
+
+ @property
+ def Path(self) -> pathlib_Path:
+ """Read-only property returning the path of this file."""
+ return self._path
+
+ # TODO: setter?
+
+ @property
+ def ResolvedPath(self) -> pathlib_Path:
+ """Read-only property returning the resolved path of this file."""
+ if self._path.is_absolute():
+ return self._path.resolve()
+ elif self._fileSet is not None:
+ path = (self._fileSet.ResolvedPath / self._path).resolve()
+
+ if path.is_absolute():
+ return path
+ else:
+ # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+ return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+ else:
+ # TODO: message and exception type
+ raise Exception("")
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ """Property setting or returning the project this file is used in."""
+ return self._project
+
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+ self._project = value
+
+ if self._fileSet is None:
+ self._project.DefaultDesign.DefaultFileSet.AddFile(self)
+
+ @property
+ def Design(self) -> Nullable['Design']:
+ """Property setting or returning the design this file is used in."""
+ return self._design
+
+ @Design.setter
+ def Design(self, value: 'Design') -> None:
+ self._design = value
+
+ if self._fileSet is None:
+ self._design.DefaultFileSet.AddFile(self)
+
+ if self._project is None:
+ self._project = value._project
+ elif self._project is not value._project:
+ raise Exception("The design's project is not identical to the already assigned project.")
+
+ @property
+ def FileSet(self) -> Nullable['FileSet']:
+ """Property setting or returning the fileset this file is used in."""
+ return self._fileSet
+
+ @FileSet.setter
+ def FileSet(self, value: 'FileSet') -> None:
+ self._fileSet = value
+ value._files.append(self)
+
+
+[docs]
+ def Validate(self) -> None:
+ """Validate this file."""
+ if self._path is None:
+ raise Exception("Validation: File has no path.")
+ try:
+ path = self.ResolvedPath
+ except Exception as ex:
+ raise Exception(f"Validation: File '{self._path}' could not compute resolved path.") from ex
+ if not path.exists():
+ raise Exception(f"Validation: File '{self._path}' (={path}) does not exist.")
+ if not path.is_file():
+ raise Exception(f"Validation: File '{self._path}' (={path}) is not a file.")
+
+ if self._fileSet is None:
+ raise Exception(f"Validation: File '{self._path}' has no fileset.")
+ if self._design is None:
+ raise Exception(f"Validation: File '{self._path}' has no design.")
+ if self._project is None:
+ raise Exception(f"Validation: File '{self._path}' has no project.")
+
+
+
+[docs]
+ def __len__(self) -> int:
+ """
+ Returns number of attributes set on this file.
+
+ :returns: The number if attributes set on this file.
+ """
+ return len(self._attributes)
+
+
+
+[docs]
+ def __getitem__(self, key: Type[Attribute]) -> Any:
+ """Index access for returning attributes on this file.
+
+ :param key: The attribute type.
+ :returns: The attribute's value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ try:
+ return self._attributes[key]
+ except KeyError:
+ try:
+ return key.resolve(self, key)
+ except KeyError:
+ attribute = key()
+ self._attributes[key] = attribute
+ return attribute
+
+
+
+[docs]
+ def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+ """
+ Index access for adding or setting attributes on this file.
+
+ :param key: The attribute type.
+ :param value: The attributes value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ self._attributes[key] = value
+
+
+
+[docs]
+ def __delitem__(self, key: Type[Attribute]) -> None:
+ """
+ Index access for deleting attributes on this file.
+
+ :param key: The attribute type.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ del self._attributes[key]
+
+
+
+
+
+
+
+FileTypes = File
+
+
+
+[docs]
+@export
+class HumanReadableContent(metaclass=ExtendedType, mixin=True):
+ """A file type representing human-readable contents."""
+
+
+
+
+[docs]
+@export
+class XMLContent(HumanReadableContent, mixin=True):
+ """A file type representing XML contents."""
+
+
+
+
+[docs]
+@export
+class YAMLContent(HumanReadableContent, mixin=True):
+ """A file type representing YAML contents."""
+
+
+
+
+[docs]
+@export
+class JSONContent(HumanReadableContent, mixin=True):
+ """A file type representing JSON contents."""
+
+
+
+
+[docs]
+@export
+class INIContent(HumanReadableContent, mixin=True):
+ """A file type representing INI contents."""
+
+
+
+
+[docs]
+@export
+class TOMLContent(HumanReadableContent, mixin=True):
+ """A file type representing TOML contents."""
+
+
+
+
+[docs]
+@export
+class TCLContent(HumanReadableContent, mixin=True):
+ """A file type representing content in TCL code."""
+
+
+
+
+[docs]
+@export
+class SDCContent(TCLContent, mixin=True):
+ """A file type representing contents as Synopsys Design Constraints (SDC)."""
+
+
+
+
+[docs]
+@export
+class PythonContent(HumanReadableContent, mixin=True):
+ """A file type representing contents as Python source code."""
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+[docs]
+@export
+class EDIFNetlistFile(NetlistFile):
+ """Netlist file in EDIF (Electronic Design Interchange Format)."""
+
+
+
+
+
+
+
+
+[docs]
+@export
+class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
+ """
+ A VHDL source file (of any language version).
+
+ :arg path: Relative or absolute path to the file.
+ :arg vhdlLibrary: VHDLLibrary this VHDL source file is associated wih.
+ :arg vhdlVersion: VHDLVersion this VHDL source file is associated wih.
+ :arg project: Project the file is associated with.
+ :arg design: Design the file is associated with.
+ :arg fileSet: Fileset the file is associated with.
+ """
+
+ _vhdlLibrary: Nullable['VHDLLibrary']
+ _vhdlVersion: VHDLVersion
+
+
+[docs]
+ def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: Nullable[VHDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
+ super().__init__(path, project, design, fileSet)
+
+ if isinstance(vhdlLibrary, str):
+ if design is not None:
+ try:
+ vhdlLibrary = design.VHDLLibraries[vhdlLibrary]
+ except KeyError as ex:
+ raise Exception(f"VHDL library '{vhdlLibrary}' not found in design '{design.Name}'.") from ex
+ elif project is not None:
+ try:
+ vhdlLibrary = project.DefaultDesign.VHDLLibraries[vhdlLibrary]
+ except KeyError as ex:
+ raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex
+ else:
+ raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
+ elif isinstance(vhdlLibrary, VHDLLibrary):
+ self._vhdlLibrary = vhdlLibrary
+ vhdlLibrary.AddFile(self)
+ elif vhdlLibrary is None:
+ self._vhdlLibrary = None
+ else:
+ ex = TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
+ if version_info >= (3, 11): # pragma: no cover
+ ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.")
+ raise ex
+
+ self._vhdlVersion = vhdlVersion
+
+
+
+[docs]
+ def Validate(self) -> None:
+ """Validate this VHDL source file."""
+ super().Validate()
+
+ try:
+ _ = self.VHDLLibrary
+ except Exception as ex:
+ raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLLibrary assigned.") from ex
+ try:
+ _ = self.VHDLVersion
+ except Exception as ex:
+ raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLVersion assigned.") from ex
+
+
+ @property
+ def VHDLLibrary(self) -> 'VHDLLibrary':
+ """Property setting or returning the VHDL library this VHDL source file is used in."""
+ if self._vhdlLibrary is not None:
+ return self._vhdlLibrary
+ elif self._fileSet is not None:
+ return self._fileSet.VHDLLibrary
+ else:
+ raise Exception("VHDLLibrary was neither set locally nor globally.")
+
+ @VHDLLibrary.setter
+ def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+ self._vhdlLibrary = value
+ value._files.append(self)
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ """Property setting or returning the VHDL version this VHDL source file is used in."""
+ if self._vhdlVersion is not None:
+ return self._vhdlVersion
+ elif self._fileSet is not None:
+ return self._fileSet.VHDLVersion
+ else:
+ raise Exception("VHDLVersion was neither set locally nor globally.")
+
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+ self._vhdlVersion = value
+
+
+[docs]
+ def __repr__(self) -> str:
+ return f"<VHDL file: '{self.ResolvedPath}'; lib: '{self.VHDLLibrary}'; version: {self.VHDLVersion}>"
+
+
+
+
+class VerilogMixIn(metaclass=ExtendedType, mixin=True):
+ @property
+ def VerilogVersion(self) -> SystemVerilogVersion:
+ """Property setting or returning the Verilog version this Verilog source file is used in."""
+ if self._version is not None:
+ return self._version
+ elif self._fileSet is not None:
+ return self._fileSet.VerilogVersion
+ else:
+ raise Exception("VerilogVersion was neither set locally nor globally.")
+
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+ self._version = value
+
+
+class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True):
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ """Property setting or returning the SystemVerilog version this SystemVerilog source file is used in."""
+ if self._version is not None:
+ return self._version
+ elif self._fileSet is not None:
+ return self._fileSet.SVVersion
+ else:
+ raise Exception("SVVersion was neither set locally nor globally.")
+
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+ self._version = value
+
+
+
+[docs]
+@export
+class VerilogBaseFile(HDLSourceFile, HumanReadableContent):
+ _version: SystemVerilogVersion
+
+
+[docs]
+ def __init__(self, path: pathlib_Path, version: Nullable[SystemVerilogVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
+ super().__init__(path, project, design, fileSet)
+
+ self._version = version
+
+
+
+
+
+[docs]
+@export
+class VerilogSourceFile(VerilogBaseFile, VerilogMixIn):
+ """A Verilog source file (of any language version)."""
+
+
+
+
+[docs]
+@export
+class VerilogHeaderFile(VerilogBaseFile, VerilogMixIn):
+ """A Verilog header file (of any language version)."""
+
+
+
+
+
+
+
+
+[docs]
+@export
+class SystemVerilogSourceFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+ """A SystemVerilog source file (of any language version)."""
+
+
+
+
+[docs]
+@export
+class SystemVerilogHeaderFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+ """A SystemVerilog header file (of any language version)."""
+
+
+
+
+[docs]
+@export
+class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent):
+ """A SystemRDL source file (of any language version)."""
+
+ _srdlVersion: SystemRDLVersion
+
+
+[docs]
+ def __init__(self, path: pathlib_Path, srdlVersion: Nullable[SystemRDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
+ super().__init__(path, project, design, fileSet)
+
+ self._srdlVersion = srdlVersion
+
+
+ @property
+ def SystemRDLVersion(self) -> SystemRDLVersion:
+ """Property setting or returning the SystemRDL version this SystemRDL source file is used in."""
+ if self._srdlVersion is not None:
+ return self._srdlVersion
+ elif self._fileSet is not None:
+ return self._fileSet.SRDLVersion
+ else:
+ raise Exception("SRDLVersion was neither set locally nor globally.")
+
+ @SystemRDLVersion.setter
+ def SystemRDLVersion(self, value: SystemRDLVersion) -> None:
+ self._srdlVersion = value
+
+
+
+
+
+
+
+# TODO: move to a Cocotb module
+
+[docs]
+@export
+class CocotbPythonFile(PythonSourceFile):
+ """A Python source file used by Cocotb."""
+
+
+
+
+[docs]
+@export
+class ConstraintFile(File, HumanReadableContent):
+ """Base-class of all constraint files."""
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+[docs]
+@export
+class SimulationAnalysisFile(File):
+ """Base-class of all tool-specific analysis files."""
+
+
+
+
+[docs]
+@export
+class SimulationElaborationFile(File):
+ """Base-class of all tool-specific elaboration files."""
+
+
+
+
+[docs]
+@export
+class SimulationStartFile(File):
+ """Base-class of all tool-specific simulation start-up files."""
+
+
+
+
+[docs]
+@export
+class SimulationRunFile(File):
+ """Base-class of all tool-specific simulation run (execution) files."""
+
+
+
+
+[docs]
+@export
+class WaveformConfigFile(File):
+ """Base-class of all tool-specific waveform configuration files."""
+
+
+
+
+[docs]
+@export
+class WaveformDatabaseFile(File):
+ """Base-class of all tool-specific waveform database files."""
+
+
+
+
+[docs]
+@export
+class WaveformExchangeFile(File):
+ """Base-class of all tool-independent waveform exchange files."""
+
+
+
+
+[docs]
+@export
+class FileSet(metaclass=ExtendedType, slots=True):
+ """
+ A :term:`FileSet` represents a group of files. Filesets can have sub-filesets.
+
+ The order of insertion is preserved. A fileset can be created standalone and
+ later associated to another fileset, design and/or project. Or a fileset,
+ design and/or project can be associated immediately while creating the
+ fileset.
+
+ :arg name: Name of this fileset.
+ :arg topLevel: Name of the fileset's toplevel.
+ :arg directory: Path of this fileset (absolute or relative to a parent fileset or design).
+ :arg project: Project the file is associated with.
+ :arg design: Design the file is associated with.
+ :arg parent: Parent fileset if this fileset is nested.
+ :arg vhdlLibrary: Default VHDL library for files in this fileset, if not specified for the file itself.
+ :arg vhdlVersion: Default VHDL version for files in this fileset, if not specified for the file itself.
+ :arg verilogVersion: Default Verilog version for files in this fileset, if not specified for the file itself.
+ :arg svVersion: Default SystemVerilog version for files in this fileset, if not specified for the file itself.
+ :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself.
+ """
+
+ _name: str
+ _topLevel: Nullable[str]
+ _project: Nullable['Project']
+ _design: Nullable['Design']
+ _directory: pathlib_Path
+ _parent: Nullable['FileSet']
+ _fileSets: Dict[str, 'FileSet']
+ _files: List[File]
+ _set: Set
+ _attributes: Dict[Type[Attribute], typing_Any]
+ _vhdlLibraries: Dict[str, 'VHDLLibrary']
+ _vhdlLibrary: 'VHDLLibrary'
+ _vhdlVersion: VHDLVersion
+ _verilogVersion: SystemVerilogVersion
+ _svVersion: SystemVerilogVersion
+ _srdlVersion: SystemRDLVersion
+
+
+[docs]
+ def __init__(
+ self,
+ name: str,
+ topLevel: Nullable[str] = None,
+ directory: pathlib_Path = pathlib_Path("."),
+ project: Nullable["Project"] = None,
+ design: Nullable["Design"] = None,
+ parent: Nullable['FileSet'] = None,
+ vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
+ vhdlVersion: Nullable[VHDLVersion] = None,
+ verilogVersion: Nullable[SystemVerilogVersion] = None,
+ svVersion: Nullable[SystemVerilogVersion] = None,
+ srdlVersion: Nullable[SystemRDLVersion] = None
+ ):
+ self._name = name
+ self._topLevel = topLevel
+ if project is not None:
+ self._project = project
+ self._design = design if design is not None else project.DefaultDesign
+
+ elif design is not None:
+ self._project = design._project
+ self._design = design
+ else:
+ self._project = None
+ self._design = None
+ self._directory = directory
+ self._parent = parent
+ self._fileSets = {}
+ self._files = []
+ self._set = set()
+
+ if design is not None:
+ design._fileSets[name] = self
+
+ self._attributes = {}
+ self._vhdlLibraries = {}
+
+ # TODO: handle if vhdlLibrary is a string
+ self._vhdlLibrary = vhdlLibrary
+ self._vhdlVersion = vhdlVersion
+ self._verilogVersion = verilogVersion
+ self._svVersion = svVersion
+ self._srdlVersion = srdlVersion
+
+
+ @property
+ def Name(self) -> str:
+ """Property setting or returning the fileset's name."""
+ return self._name
+
+ @Name.setter
+ def Name(self, value: str) -> None:
+ self._name = value
+
+ @property
+ def TopLevel(self) -> str:
+ """Property setting or returning the fileset's toplevel."""
+ return self._topLevel
+
+ @TopLevel.setter
+ def TopLevel(self, value: str) -> None:
+ self._topLevel = value
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ """Property setting or returning the project this fileset is used in."""
+ return self._project
+
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+ self._project = value
+
+ @property
+ def Design(self) -> Nullable['Design']:
+ """Property setting or returning the design this fileset is used in."""
+ if self._design is not None:
+ return self._design
+ elif self._parent is not None:
+ return self._parent.Design
+ else:
+ return None
+ # TODO: raise exception instead
+ # QUESTION: how to handle if design and parent is set?
+
+ @Design.setter
+ def Design(self, value: 'Design') -> None:
+ self._design = value
+ if self._project is None:
+ self._project = value._project
+ elif self._project is not value._project:
+ raise Exception("The design's project is not identical to the already assigned project.")
+
+ @property
+ def Directory(self) -> pathlib_Path:
+ """Property setting or returning the directory this fileset is located in."""
+ return self._directory
+
+ @Directory.setter
+ def Directory(self, value: pathlib_Path) -> None:
+ self._directory = value
+
+ @property
+ def ResolvedPath(self) -> pathlib_Path:
+ """Read-only property returning the resolved path of this fileset."""
+ if self._directory.is_absolute():
+ return self._directory.resolve()
+ else:
+ if self._parent is not None:
+ directory = self._parent.ResolvedPath
+ elif self._design is not None:
+ directory = self._design.ResolvedPath
+ elif self._project is not None:
+ directory = self._project.ResolvedPath
+ else:
+ # TODO: message and exception type
+ raise Exception("")
+
+ directory = (directory / self._directory).resolve()
+ if directory.is_absolute():
+ return directory
+ else:
+ # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+ return pathlib_Path(path_relpath(directory, pathlib_Path.cwd()))
+
+ @property
+ def Parent(self) -> Nullable['FileSet']:
+ """Property setting or returning the parent fileset this fileset is used in."""
+ return self._parent
+
+ @Parent.setter
+ def Parent(self, value: 'FileSet') -> None:
+ self._parent = value
+ value._fileSets[self._name] = self
+ # TODO: check it it already exists
+ # QUESTION: make an Add fileset method?
+
+ @property
+ def FileSets(self) -> Dict[str, 'FileSet']:
+ """Read-only property returning the dictionary of sub-filesets."""
+ return self._fileSets
+
+
+[docs]
+ def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[bool, str, 'FileSet'] = None) -> Generator[File, None, None]:
+ """
+ Method returning the files of this fileset.
+
+ :arg fileType: A filter for file types. Default: ``Any``.
+ :arg fileSet: Specifies how to handle sub-filesets.
+ """
+ if fileSet is False:
+ for file in self._files:
+ if file.FileType in fileType:
+ yield file
+ elif fileSet is None:
+ for fileSet in self._fileSets.values():
+ for file in fileSet.Files(fileType):
+ yield file
+ for file in self._files:
+ if file.FileType in fileType:
+ yield file
+ else:
+ if isinstance(fileSet, str):
+ fileSetName = fileSet
+ try:
+ fileSet = self._fileSets[fileSetName]
+ except KeyError as ex:
+ raise Exception(f"Fileset {fileSetName} not bound to fileset {self.Name}.") from ex
+ elif not isinstance(fileSet, FileSet):
+ raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+
+ for file in fileSet.Files(fileType):
+ yield file
+
+
+
+[docs]
+ def AddFileSet(self, fileSet: "FileSet") -> None:
+ """
+ Method to add a single sub-fileset to this fileset.
+
+ :arg fileSet: A fileset to add to this fileset as sub-fileset.
+ """
+ if not isinstance(fileSet, FileSet):
+ raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+ elif fileSet in self._fileSets:
+ raise Exception("Sub-fileset already contains this fileset.")
+ elif fileSet.Name in self._fileSets.keys():
+ raise Exception(f"Fileset already contains a sub-fileset named '{fileSet.Name}'.")
+
+ self._fileSets[fileSet.Name] = fileSet
+ fileSet._parent = self
+
+
+
+[docs]
+ def AddFileSets(self, fileSets: Iterable["FileSet"]) -> None:
+ """
+ Method to add a multiple sub-filesets to this fileset.
+
+ :arg fileSets: An iterable of filesets to add each to the fileset.
+ """
+ for fileSet in fileSets:
+ self.AddFileSet(fileSet)
+
+
+ @property
+ def FileSetCount(self) -> int:
+ """Returns number of file sets excl. sub-filesets."""
+ return len(self._fileSets)
+
+ @property
+ def TotalFileSetCount(self) -> int:
+ """Returns number of file sets incl. sub-filesets."""
+ fileSetCount = len(self._fileSets)
+ for fileSet in self._fileSets.values():
+ fileSetCount += fileSet.TotalFileSetCount
+
+ return fileSetCount
+
+
+[docs]
+ def AddFile(self, file: File) -> None:
+ """
+ Method to add a single file to this fileset.
+
+ :arg file: A file to add to this fileset.
+ """
+ if not isinstance(file, File):
+ raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
+ elif file._fileSet is not None:
+ ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
+ if version_info >= (3, 11): # pragma: no cover
+ ex.add_note(f"A file can't be assigned to another fileset.")
+ raise ex
+ elif file in self._set:
+ ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
+ if version_info >= (3, 11): # pragma: no cover
+ ex.add_note(f"A file can't be added twice to a fileset.")
+ raise ex
+
+ self._files.append(file)
+ self._set.add(file)
+ file._fileSet = self
+
+
+
+[docs]
+ def AddFiles(self, files: Iterable[File]) -> None:
+ """
+ Method to add a multiple files to this fileset.
+
+ :arg files: An iterable of files to add each to the fileset.
+ """
+ for file in files:
+ self.AddFile(file)
+
+
+ @property
+ def FileCount(self) -> int:
+ """Returns number of files excl. sub-filesets."""
+ return len(self._files)
+
+ @property
+ def TotalFileCount(self) -> int:
+ """Returns number of files incl. the files in sub-filesets."""
+ fileCount = len(self._files)
+ for fileSet in self._fileSets.values():
+ fileCount += fileSet.FileCount
+
+ return fileCount
+
+
+[docs]
+ def Validate(self) -> None:
+ """Validate this fileset."""
+ if self._name is None or self._name == "":
+ raise Exception("Validation: FileSet has no name.")
+
+ if self._directory is None:
+ raise Exception(f"Validation: FileSet '{self._name}' has no directory.")
+ try:
+ path = self.ResolvedPath
+ except Exception as ex:
+ raise Exception(f"Validation: FileSet '{self._name}' could not compute resolved path.") from ex
+ if not path.exists():
+ raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' does not exist.")
+ if not path.is_dir():
+ raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' is not a directory.")
+
+ if self._design is None:
+ raise Exception(f"Validation: FileSet '{self._directory}' has no design.")
+ if self._project is None:
+ raise Exception(f"Validation: FileSet '{self._directory}' has no project.")
+
+ for fileSet in self._fileSets.values():
+ fileSet.Validate()
+ for file in self._files:
+ file.Validate()
+
+
+ def GetOrCreateVHDLLibrary(self, name) -> 'VHDLLibrary':
+ if name in self._vhdlLibraries:
+ return self._vhdlLibraries[name]
+ elif name in self._design._vhdlLibraries:
+ library = self._design._vhdlLibraries[name]
+ self._vhdlLibraries[name] = library
+ return library
+ else:
+ library = VHDLLibrary(name, design=self._design, vhdlVersion=self._vhdlVersion)
+ self._vhdlLibraries[name] = library
+ return library
+
+ @property
+ def VHDLLibrary(self) -> 'VHDLLibrary':
+ """Property setting or returning the VHDL library of this fileset."""
+ if self._vhdlLibrary is not None:
+ return self._vhdlLibrary
+ elif self._parent is not None:
+ return self._parent.VHDLLibrary
+ elif self._design is not None:
+ return self._design.VHDLLibrary
+ else:
+ raise Exception("VHDLLibrary was neither set locally nor globally.")
+
+ @VHDLLibrary.setter
+ def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+ self._vhdlLibrary = value
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ """Property setting or returning the VHDL version of this fileset."""
+ if self._vhdlVersion is not None:
+ return self._vhdlVersion
+ elif self._parent is not None:
+ return self._parent.VHDLVersion
+ elif self._design is not None:
+ return self._design.VHDLVersion
+ else:
+ raise Exception("VHDLVersion was neither set locally nor globally.")
+
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+ self._vhdlVersion = value
+
+ @property
+ def VerilogVersion(self) -> SystemVerilogVersion:
+ """Property setting or returning the Verilog version of this fileset."""
+ if self._verilogVersion is not None:
+ return self._verilogVersion
+ elif self._parent is not None:
+ return self._parent.VerilogVersion
+ elif self._design is not None:
+ return self._design.VerilogVersion
+ else:
+ raise Exception("VerilogVersion was neither set locally nor globally.")
+
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+ self._verilogVersion = value
+
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ """Property setting or returning the SystemVerilog version of this fileset."""
+ if self._svVersion is not None:
+ return self._svVersion
+ elif self._parent is not None:
+ return self._parent.SVVersion
+ elif self._design is not None:
+ return self._design.SVVersion
+ else:
+ raise Exception("SVVersion was neither set locally nor globally.")
+
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+ self._svVersion = value
+
+ @property
+ def SRDLVersion(self) -> SystemRDLVersion:
+ if self._srdlVersion is not None:
+ return self._srdlVersion
+ elif self._parent is not None:
+ return self._parent.SRDLVersion
+ elif self._design is not None:
+ return self._design.SRDLVersion
+ else:
+ raise Exception("SRDLVersion was neither set locally nor globally.")
+
+ @SRDLVersion.setter
+ def SRDLVersion(self, value: SystemRDLVersion) -> None:
+ self._srdlVersion = value
+
+
+[docs]
+ def __len__(self) -> int:
+ """
+ Returns number of attributes set on this fileset.
+
+ :returns: The number if attributes set on this fileset.
+ """
+ return len(self._attributes)
+
+
+
+[docs]
+ def __getitem__(self, key: Type[Attribute]) -> Any:
+ """Index access for returning attributes on this fileset.
+
+ :param key: The attribute type.
+ :returns: The attribute's value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ try:
+ return self._attributes[key]
+ except KeyError:
+ return key.resolve(self, key)
+
+
+
+[docs]
+ def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+ """
+ Index access for adding or setting attributes on this fileset.
+
+ :param key: The attribute type.
+ :param value: The attributes value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ self._attributes[key] = value
+
+
+
+[docs]
+ def __delitem__(self, key: Type[Attribute]) -> None:
+ """
+ Index access for deleting attributes on this fileset.
+
+ :param key: The attribute type.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ del self._attributes[key]
+
+
+
+
+
+
+
+
+[docs]
+@export
+class VHDLLibrary(metaclass=ExtendedType, slots=True):
+ """
+ A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library.
+
+ :arg name: The VHDL libraries' name.
+ :arg project: Project the VHDL library is associated with.
+ :arg design: Design the VHDL library is associated with.
+ :arg vhdlVersion: Default VHDL version for files in this VHDL library, if not specified for the file itself.
+ """
+
+ _name: str
+ _project: Nullable['Project']
+ _design: Nullable['Design']
+ _files: List[File]
+ _vhdlVersion: VHDLVersion
+
+ _dependencyNode: Vertex
+
+
+[docs]
+ def __init__(
+ self,
+ name: str,
+ project: Nullable["Project"] = None,
+ design: Nullable["Design"] = None,
+ vhdlVersion: Nullable[VHDLVersion] = None
+ ):
+ self._name = name
+ if project is not None:
+ self._project = project
+ self._design = project._defaultDesign if design is None else design
+ self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+
+ if name in self._design._vhdlLibraries:
+ raise Exception(f"Library '{name}' already in design '{self._design.Name}'.")
+ else:
+ self._design._vhdlLibraries[name] = self
+
+ elif design is not None:
+ self._project = design._project
+ self._design = design
+ self._dependencyNode = Vertex(value=self, graph=design._vhdlLibraryDependencyGraph)
+
+ if name in design._vhdlLibraries:
+ raise Exception(f"Library '{name}' already in design '{design.Name}'.")
+ else:
+ design._vhdlLibraries[name] = self
+
+ else:
+ self._project = None
+ self._design = None
+ self._dependencyNode = None
+
+ self._files = []
+ self._vhdlVersion = vhdlVersion
+
+
+ @property
+ def Name(self) -> str:
+ return self._name
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ """Property setting or returning the project this VHDL library is used in."""
+ return self._project
+
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+ if not isinstance(value, Project):
+ raise TypeError("Parameter 'value' is not of type 'Project'.")
+
+ if value is None:
+ # TODO: unlink VHDLLibrary from project
+ self._project = None
+ else:
+ self._project = value
+ if self._design is None:
+ self._design = value._defaultDesign
+
+ @property
+ def Design(self) -> Nullable['Design']:
+ """Property setting or returning the design this VHDL library is used in."""
+ return self._design
+
+ @Design.setter
+ def Design(self, value: 'Design') -> None:
+ if not isinstance(value, Design):
+ raise TypeError("Parameter 'value' is not of type 'Design'.")
+
+ if value is None:
+ # TODO: unlink VHDLLibrary from design
+ self._design = None
+ else:
+ if self._design is None:
+ self._design = value
+ self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+ elif self._design is not value:
+ # TODO: move VHDLLibrary to other design
+ # TODO: create new vertex in dependency graph and remove vertex from old graph
+ self._design = value
+ else:
+ pass
+
+ if self._project is None:
+ self._project = value._project
+ elif self._project is not value._project:
+ raise Exception("The design's project is not identical to the already assigned project.")
+
+ @property
+ def Files(self) -> Generator[File, None, None]:
+ """Read-only property to return all files in this VHDL library."""
+ for file in self._files:
+ yield file
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ """Property setting or returning the VHDL version of this VHDL library."""
+ if self._vhdlVersion is not None:
+ return self._vhdlVersion
+ elif self._design is not None:
+ return self._design.VHDLVersion
+ else:
+ raise Exception("VHDLVersion is not set on VHDLLibrary nor parent object.")
+
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+ self._vhdlVersion = value
+
+ def AddDependency(self, library: 'VHDLLibrary') -> None:
+ library.parent = self
+
+ def AddFile(self, vhdlFile: VHDLSourceFile) -> None:
+ if not isinstance(vhdlFile, VHDLSourceFile):
+ ex = TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
+ if version_info >= (3, 11): # pragma: no cover
+ ex.add_note(f"Got type '{getFullyQualifiedName(vhdlFile)}'.")
+ raise ex
+
+ self._files.append(vhdlFile)
+
+ def AddFiles(self, vhdlFiles: Iterable[VHDLSourceFile]) -> None:
+ for vhdlFile in vhdlFiles:
+ if not isinstance(vhdlFile, VHDLSourceFile):
+ raise TypeError(f"Item '{vhdlFile}' in parameter 'vhdlFiles' is not a 'VHDLSourceFile'.")
+
+ self._files.append(vhdlFile)
+
+ @property
+ def FileCount(self) -> int:
+ """Returns number of files."""
+ return len(self._files)
+
+
+[docs]
+ def __len__(self) -> int:
+ """
+ Returns number of attributes set on this VHDL library.
+
+ :returns: The number if attributes set on this VHDL library.
+ """
+ return len(self._attributes)
+
+
+
+[docs]
+ def __getitem__(self, key: Type[Attribute]) -> Any:
+ """Index access for returning attributes on this VHDL library.
+
+ :param key: The attribute type.
+ :returns: The attribute's value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ try:
+ return self._attributes[key]
+ except KeyError:
+ return key.resolve(self, key)
+
+
+
+[docs]
+ def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+ """
+ Index access for adding or setting attributes on this VHDL library.
+
+ :param key: The attribute type.
+ :param value: The attributes value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ self._attributes[key] = value
+
+
+
+[docs]
+ def __delitem__(self, key: Type[Attribute]) -> None:
+ """
+ Index access for deleting attributes on this VHDL library.
+
+ :param key: The attribute type.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ del self._attributes[key]
+
+
+
+
+
+
+
+
+[docs]
+@export
+class Design(metaclass=ExtendedType, slots=True):
+ """
+ A :term:`Design` represents a group of filesets and the source files therein.
+
+ Each design contains at least one fileset - the :term:`default fileset`. For
+ designs with VHDL source files, a independent `VHDLLibraries` overlay structure
+ exists.
+
+ :arg name: The design's name.
+ :arg topLevel: Name of the design's toplevel.
+ :arg directory: Path of this design (absolute or relative to the project).
+ :arg project: Project the design is associated with.
+ :arg vhdlVersion: Default VHDL version for files in this design, if not specified for the file itself.
+ :arg verilogVersion: Default Verilog version for files in this design, if not specified for the file itself.
+ :arg svVersion: Default SystemVerilog version for files in this design, if not specified for the file itself.
+ :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself.
+ """
+
+ _name: str
+ _topLevel: Nullable[str]
+ _project: Nullable['Project']
+ _directory: pathlib_Path
+ _fileSets: Dict[str, FileSet]
+ _defaultFileSet: Nullable[FileSet]
+ _attributes: Dict[Type[Attribute], typing_Any]
+
+ _vhdlLibraries: Dict[str, VHDLLibrary]
+ _vhdlVersion: VHDLVersion
+ _verilogVersion: SystemVerilogVersion
+ _svVersion: SystemVerilogVersion
+ _srdlVersion: SystemRDLVersion
+ _externalVHDLLibraries: List
+
+ _vhdlLibraryDependencyGraph: Graph
+ _fileDependencyGraph: Graph
+
+
+[docs]
+ def __init__(
+ self,
+ name: str,
+ topLevel: Nullable[str] = None,
+ directory: pathlib_Path = pathlib_Path("."),
+ project: Nullable["Project"] = None,
+ vhdlVersion: Nullable[VHDLVersion] = None,
+ verilogVersion: Nullable[SystemVerilogVersion] = None,
+ svVersion: Nullable[SystemVerilogVersion] = None,
+ srdlVersion: Nullable[SystemRDLVersion] = None
+ ):
+ self._name = name
+ self._topLevel = topLevel
+ self._project = project
+ if project is not None:
+ project._designs[name] = self
+ self._directory = directory
+ self._fileSets = {}
+ self._defaultFileSet = FileSet("default", project=project, design=self)
+ self._attributes = {}
+ self._vhdlLibraries = {}
+ self._vhdlVersion = vhdlVersion
+ self._verilogVersion = verilogVersion
+ self._svVersion = svVersion
+ self._srdlVersion = srdlVersion
+ self._externalVHDLLibraries = []
+
+ self._vhdlLibraryDependencyGraph = Graph()
+ self._fileDependencyGraph = Graph()
+
+
+ @property
+ def Name(self) -> str:
+ """Property setting or returning the design's name."""
+ return self._name
+
+ @Name.setter
+ def Name(self, value: str) -> None:
+ self._name = value
+
+ @property
+ def TopLevel(self) -> str:
+ """Property setting or returning the fileset's toplevel."""
+ return self._topLevel
+
+ @TopLevel.setter
+ def TopLevel(self, value: str) -> None:
+ self._topLevel = value
+
+ @property
+ def Project(self) -> Nullable['Project']:
+ """Property setting or returning the project this design is used in."""
+ return self._project
+
+ @Project.setter
+ def Project(self, value: 'Project') -> None:
+ self._project = value
+
+ @property
+ def Directory(self) -> pathlib_Path:
+ """Property setting or returning the directory this design is located in."""
+ return self._directory
+
+ @Directory.setter
+ def Directory(self, value: pathlib_Path) -> None:
+ self._directory = value
+
+ @property
+ def ResolvedPath(self) -> pathlib_Path:
+ """Read-only property returning the resolved path of this fileset."""
+ if self._directory.is_absolute():
+ return self._directory.resolve()
+ elif self._project is not None:
+ path = (self._project.ResolvedPath / self._directory).resolve()
+
+ if path.is_absolute():
+ return path
+ else:
+ # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+ return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+ else:
+ # TODO: message and exception type
+ raise Exception("")
+
+ @property
+ def DefaultFileSet(self) -> FileSet:
+ """Property setting or returning the default fileset of this design."""
+ return self._defaultFileSet
+
+ @DefaultFileSet.setter
+ def DefaultFileSet(self, value: Union[str, FileSet]) -> None:
+ if isinstance(value, str):
+ if value not in self._fileSets.keys():
+ raise Exception(f"Fileset '{value}' is not in this design.")
+
+ self._defaultFileSet = self._fileSets[value]
+ elif isinstance(value, FileSet):
+ if value not in self.FileSets:
+ raise Exception(f"Fileset '{value}' is not associated to this design.")
+
+ self._defaultFileSet = value
+ else:
+ raise ValueError("Unsupported parameter type for 'value'.")
+
+ # TODO: return generator with another method
+ @property
+ def FileSets(self) -> Dict[str, FileSet]:
+ """Read-only property returning the dictionary of filesets."""
+ return self._fileSets
+
+
+[docs]
+ def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]:
+ """
+ Method returning the files of this design.
+
+ :arg fileType: A filter for file types. Default: ``Any``.
+ :arg fileSet: Specifies if all files from all filesets (``fileSet=None``) are files from a single fileset are returned.
+ """
+ if fileSet is None:
+ for fileSet in self._fileSets.values():
+ for file in fileSet.Files(fileType):
+ yield file
+ else:
+ if isinstance(fileSet, str):
+ try:
+ fileSet = self._fileSets[fileSet]
+ except KeyError as ex:
+ raise Exception(f"Fileset {fileSet.Name} not bound to design {self.Name}.") from ex
+ elif not isinstance(fileSet, FileSet):
+ raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+
+ for file in fileSet.Files(fileType):
+ yield file
+
+
+
+[docs]
+ def Validate(self) -> None:
+ """Validate this design."""
+ if self._name is None or self._name == "":
+ raise Exception("Validation: Design has no name.")
+
+ if self._directory is None:
+ raise Exception(f"Validation: Design '{self._name}' has no directory.")
+ try:
+ path = self.ResolvedPath
+ except Exception as ex:
+ raise Exception(f"Validation: Design '{self._name}' could not compute resolved path.") from ex
+ if not path.exists():
+ raise Exception(f"Validation: Design '{self._name}'s directory '{path}' does not exist.")
+ if not path.is_dir():
+ raise Exception(f"Validation: Design '{self._name}'s directory '{path}' is not a directory.")
+
+ if len(self._fileSets) == 0:
+ raise Exception(f"Validation: Design '{self._name}' has no fileset.")
+ try:
+ if self._defaultFileSet is not self._fileSets[self._defaultFileSet.Name]:
+ raise Exception(f"Validation: Design '{self._name}'s default fileset is the same as listed in filesets.")
+ except KeyError as ex:
+ raise Exception(f"Validation: Design '{self._name}'s default fileset is not in list of filesets.") from ex
+ if self._project is None:
+ raise Exception(f"Validation: Design '{self._path}' has no project.")
+
+ for fileSet in self._fileSets.values():
+ fileSet.Validate()
+
+
+ @property
+ def VHDLLibraries(self) -> Dict[str, VHDLLibrary]:
+ return self._vhdlLibraries
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ if self._vhdlVersion is not None:
+ return self._vhdlVersion
+ elif self._project is not None:
+ return self._project.VHDLVersion
+ else:
+ raise Exception("VHDLVersion was neither set locally nor globally.")
+
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+ self._vhdlVersion = value
+
+ @property
+ def VerilogVersion(self) -> SystemVerilogVersion:
+ if self._verilogVersion is not None:
+ return self._verilogVersion
+ elif self._project is not None:
+ return self._project.VerilogVersion
+ else:
+ raise Exception("VerilogVersion was neither set locally nor globally.")
+
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+ self._verilogVersion = value
+
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ if self._svVersion is not None:
+ return self._svVersion
+ elif self._project is not None:
+ return self._project.SVVersion
+ else:
+ raise Exception("SVVersion was neither set locally nor globally.")
+
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+ self._svVersion = value
+
+ @property
+ def SRDLVersion(self) -> SystemRDLVersion:
+ if self._srdlVersion is not None:
+ return self._srdlVersion
+ elif self._project is not None:
+ return self._project.SRDLVersion
+ else:
+ raise Exception("SRDLVersion was neither set locally nor globally.")
+
+ @SRDLVersion.setter
+ def SRDLVersion(self, value: SystemRDLVersion) -> None:
+ self._srdlVersion = value
+
+ @property
+ def ExternalVHDLLibraries(self) -> List:
+ return self._externalVHDLLibraries
+
+ def AddFileSet(self, fileSet: FileSet) -> None:
+ if not isinstance(fileSet, FileSet):
+ raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+ elif fileSet in self._fileSets:
+ raise Exception("Design already contains this fileset.")
+ elif fileSet.Name in self._fileSets.keys():
+ raise Exception(f"Design already contains a fileset named '{fileSet.Name}'.")
+
+ self._fileSets[fileSet.Name] = fileSet
+ fileSet.Design = self
+ fileSet._parent = self
+
+ def AddFileSets(self, fileSets: Iterable[FileSet]) -> None:
+ for fileSet in fileSets:
+ self.AddFileSet(fileSet)
+
+ @property
+ def FileSetCount(self) -> int:
+ """Returns number of file sets excl. sub-filesets."""
+ return len(self._fileSets)
+
+ @property
+ def TotalFileSetCount(self) -> int:
+ """Returns number of file sets incl. sub-filesets."""
+ fileSetCount = len(self._fileSets)
+ for fileSet in self._fileSets.values():
+ fileSetCount += fileSet.TotalFileSetCount
+
+ return fileSetCount
+
+ def AddFile(self, file: File) -> None:
+ if file.FileSet is None:
+ self._defaultFileSet.AddFile(file)
+ else:
+ raise ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}' and can't be assigned via Design to a default fileset.")
+
+ def AddFiles(self, files: Iterable[File]) -> None:
+ for file in files:
+ self.AddFile(file)
+
+ def AddVHDLLibrary(self, vhdlLibrary: VHDLLibrary) -> None:
+ if vhdlLibrary.Name in self._vhdlLibraries:
+ if self._vhdlLibraries[vhdlLibrary.Name] is vhdlLibrary:
+ raise Exception(f"The VHDLLibrary '{vhdlLibrary.Name}' was already added to the design.")
+ else:
+ raise Exception(f"A VHDLLibrary with same name ('{vhdlLibrary.Name}') already exists for this design.")
+
+
+
+[docs]
+ def __len__(self) -> int:
+ """
+ Returns number of attributes set on this design.
+
+ :returns: The number if attributes set on this design.
+ """
+ return len(self._attributes)
+
+
+
+[docs]
+ def __getitem__(self, key: Type[Attribute]) -> Any:
+ """Index access for returning attributes on this design.
+
+ :param key: The attribute type.
+ :returns: The attribute's value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ try:
+ return self._attributes[key]
+ except KeyError:
+ return key.resolve(self, key)
+
+
+
+[docs]
+ def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+ """
+ Index access for adding or setting attributes on this design.
+
+ :param key: The attribute type.
+ :param value: The attributes value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ self._attributes[key] = value
+
+
+
+[docs]
+ def __delitem__(self, key: Type[Attribute]) -> None:
+ """
+ Index access for deleting attributes on this design.
+
+ :param key: The attribute type.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ del self._attributes[key]
+
+
+
+
+
+
+
+
+[docs]
+@export
+class Project(metaclass=ExtendedType, slots=True):
+ """
+ A :term:`Project` represents a group of designs and the source files therein.
+
+ :arg name: The project's name.
+ :arg rootDirectory: Base-path to the project.
+ :arg vhdlVersion: Default VHDL version for files in this project, if not specified for the file itself.
+ :arg verilogVersion: Default Verilog version for files in this project, if not specified for the file itself.
+ :arg svVersion: Default SystemVerilog version for files in this project, if not specified for the file itself.
+ """
+
+ _name: str
+ _rootDirectory: pathlib_Path
+ _designs: Dict[str, Design]
+ _defaultDesign: Design
+ _attributes: Dict[Type[Attribute], typing_Any]
+
+ _vhdlVersion: VHDLVersion
+ _verilogVersion: SystemVerilogVersion
+ _svVersion: SystemVerilogVersion
+ _srdlVersion: SystemRDLVersion
+
+
+[docs]
+ def __init__(
+ self,
+ name: str,
+ rootDirectory: pathlib_Path = pathlib_Path("."),
+ vhdlVersion: Nullable[VHDLVersion] = None,
+ verilogVersion: Nullable[SystemVerilogVersion] = None,
+ svVersion: Nullable[SystemVerilogVersion] = None
+ ):
+ self._name = name
+ self._rootDirectory = rootDirectory
+ self._designs = {}
+ self._defaultDesign = Design("default", project=self)
+ self._attributes = {}
+ self._vhdlVersion = vhdlVersion
+ self._verilogVersion = verilogVersion
+ self._svVersion = svVersion
+
+
+ @property
+ def Name(self) -> str:
+ """Property setting or returning the project's name."""
+ return self._name
+
+ @property
+ def RootDirectory(self) -> pathlib_Path:
+ """Property setting or returning the root directory this project is located in."""
+ return self._rootDirectory
+
+ @RootDirectory.setter
+ def RootDirectory(self, value: pathlib_Path) -> None:
+ self._rootDirectory = value
+
+ @property
+ def ResolvedPath(self) -> pathlib_Path:
+ """Read-only property returning the resolved path of this fileset."""
+ path = self._rootDirectory.resolve()
+ if self._rootDirectory.is_absolute():
+ return path
+ else:
+ # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+ return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+
+ # TODO: return generator with another method
+ @property
+ def Designs(self) -> Dict[str, Design]:
+ return self._designs
+
+ @property
+ def DefaultDesign(self) -> Design:
+ return self._defaultDesign
+
+
+[docs]
+ def Validate(self) -> None:
+ """Validate this project."""
+ if self._name is None or self._name == "":
+ raise Exception("Validation: Project has no name.")
+
+ if self._rootDirectory is None:
+ raise Exception(f"Validation: Project '{self._name}' has no root directory.")
+ try:
+ path = self.ResolvedPath
+ except Exception as ex:
+ raise Exception(f"Validation: Project '{self._name}' could not compute resolved path.") from ex
+ if not path.exists():
+ raise Exception(f"Validation: Project '{self._name}'s directory '{path}' does not exist.")
+ if not path.is_dir():
+ raise Exception(f"Validation: Project '{self._name}'s directory '{path}' is not a directory.")
+
+ if len(self._designs) == 0:
+ raise Exception(f"Validation: Project '{self._name}' has no design.")
+ try:
+ if self._defaultDesign is not self._designs[self._defaultDesign.Name]:
+ raise Exception(f"Validation: Project '{self._name}'s default design is the same as listed in designs.")
+ except KeyError as ex:
+ raise Exception(f"Validation: Project '{self._name}'s default design is not in list of designs.") from ex
+
+ for design in self._designs.values():
+ design.Validate()
+
+
+ @property
+ def DesignCount(self) -> int:
+ """Returns number of designs."""
+ return len(self._designs)
+
+ @property
+ def VHDLVersion(self) -> VHDLVersion:
+ # TODO: check for None and return exception
+ return self._vhdlVersion
+
+ @VHDLVersion.setter
+ def VHDLVersion(self, value: VHDLVersion) -> None:
+ self._vhdlVersion = value
+
+ @property
+ def VerilogVersion(self) -> SystemVerilogVersion:
+ # TODO: check for None and return exception
+ return self._verilogVersion
+
+ @VerilogVersion.setter
+ def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+ self._verilogVersion = value
+
+ @property
+ def SVVersion(self) -> SystemVerilogVersion:
+ # TODO: check for None and return exception
+ return self._svVersion
+
+ @SVVersion.setter
+ def SVVersion(self, value: SystemVerilogVersion) -> None:
+ self._svVersion = value
+
+ @property
+ def SRDLVersion(self) -> SystemRDLVersion:
+ # TODO: check for None and return exception
+ return self._srdlVersion
+
+ @SRDLVersion.setter
+ def SRDLVersion(self, value: SystemRDLVersion) -> None:
+ self._srdlVersion = value
+
+
+[docs]
+ def __len__(self) -> int:
+ """
+ Returns number of attributes set on this project.
+
+ :returns: The number if attributes set on this project.
+ """
+ return len(self._attributes)
+
+
+
+[docs]
+ def __getitem__(self, key: Type[Attribute]) -> Any:
+ """Index access for returning attributes on this project.
+
+ :param key: The attribute type.
+ :returns: The attribute's value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ try:
+ return self._attributes[key]
+ except KeyError:
+ return key.resolve(self, key)
+
+
+
+[docs]
+ def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+ """
+ Index access for adding or setting attributes on this project.
+
+ :param key: The attribute type.
+ :param value: The attributes value.
+ :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ self._attributes[key] = value
+
+
+
+[docs]
+ def __delitem__(self, key: Type[Attribute]) -> None:
+ """
+ Index access for deleting attributes on this project.
+
+ :param key: The attribute type.
+ """
+ if not issubclass(key, Attribute):
+ raise TypeError("Parameter 'key' is not an 'Attribute'.")
+
+ del self._attributes[key]
+
+
+
+
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Altera Quartus."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, SDCContent, TCLContent
+
+
+
+[docs]
+@export
+class QuartusProjectFile(ProjectFile, TCLContent):
+ """A Quartus project file (``*.qpf``)."""
+
+
+
+
+[docs]
+@export
+class SDCConstraintFile(ConstraintFile, SDCContent):
+ """A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``)."""
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""A set of common attributes to store meta information on ProjectModel entities (project, design, fileset, file, ...)."""
+from typing import Dict
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import Attribute
+
+
+
+[docs]
+@export
+class KeyValueAttribute(Attribute):
+ KEY = "ID"
+
+ _keyValuePairs: Dict[str, str]
+
+
+
+
+ def __getitem__(self, item: str) -> str:
+ return self._keyValuePairs[item]
+
+ def __setitem__(self, key: str, value: str) -> None:
+ self._keyValuePairs[key] = value
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for `GHDL <https://github.com/ghdl>`__."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import WaveformExchangeFile
+
+
+
+[docs]
+@export
+class GHDLWaveformFile(WaveformExchangeFile):
+ """GHDL's waveform file (``*.ghw``) supporting VHDL and Verilog simulation results."""
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Intel FPGA Quartus Prime."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, SDCContent, TCLContent
+
+
+
+[docs]
+@export
+class QuartusProjectFile(ProjectFile, TCLContent):
+ """A Quartus project file (``*.qpf``)."""
+
+
+
+
+[docs]
+@export
+class SDCConstraintFile(ConstraintFile, SDCContent):
+ """A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``)."""
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Mentor Graphics ModelSim."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ProjectFile, SettingFile, INIContent, WaveformConfigFile, TCLContent
+
+
+
+
+
+
+
+
+
+
+
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Mentor Graphics QuestaSim."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ProjectFile, SettingFile, INIContent, WaveformConfigFile, TCLContent
+
+
+
+
+
+
+
+
+
+
+
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for `OSVVM <https://github.com/OSVVM>`__."""
+from pathlib import Path
+
+from pyTooling.Decorators import export
+from typing import Optional as Nullable, List
+
+from pyEDAA.ProjectModel import ProjectFile, TCLContent, Project, Design, FileSet, VHDLLibrary, VHDLSourceFile
+
+
+
+[docs]
+@export
+class OSVVMProjectFile(ProjectFile, TCLContent):
+ """An OSVVM project file (``*.pro``)."""
+
+ _osvvmProject: Nullable[Project]
+
+
+[docs]
+ def __init__(
+ self,
+ path: Path,
+ project: Nullable[Project] = None,
+ design: Nullable[Design] = None,
+ fileSet: Nullable[FileSet] = None
+ ):
+ super().__init__(path, project, design, fileSet)
+
+ self._osvvmProject = None
+
+
+ @property
+ def ProjectModel(self) -> Project:
+ return self._osvvmProject
+
+ class Instruction:
+ _line: int
+
+ def __init__(self, line: int):
+ self._line = line
+
+ class Empty(Instruction):
+ def __init__(self, line: int):
+ super().__init__(line)
+
+ class Comment(Instruction):
+ _commentText: str
+
+ def __init__(self, line: int, commentText: str):
+ super().__init__(line)
+ self._commentText = commentText.rstrip()
+
+ @property
+ def CommentText(self) -> str:
+ return self._commentText
+
+ class Analyze(Instruction):
+ _vhdlSourceFile: VHDLSourceFile
+
+ def __init__(self, line: int, parameterText: str):
+ super().__init__(line)
+ self._vhdlSourceFile = VHDLSourceFile(Path(parameterText.strip()))
+
+ @property
+ def VHDLSourceFile(self) -> VHDLSourceFile:
+ return self._vhdlSourceFile
+
+ class Library(Instruction):
+ _vhdlLibrary: VHDLLibrary
+
+ def __init__(self, line: int, parameterText: str):
+ super().__init__(line)
+ self._vhdlLibrary = VHDLLibrary(parameterText.strip())
+
+ @property
+ def VHDLLibrary(self) -> VHDLLibrary:
+ return self._vhdlLibrary
+
+ class Include(Instruction):
+ _osvvmProjectFile: 'OSVVMProjectFile'
+ _fileSet: FileSet
+
+ def __init__(self, line: int, workingDirectory: Path, parameterText: str):
+ super().__init__(line)
+
+ includeFile = Path(parameterText.strip())
+ includePath = (workingDirectory / includeFile).resolve()
+
+ self._fileSet = FileSet(includeFile.name, directory=includeFile.parent)
+ self._osvvmProjectFile = OSVVMProjectFile(includePath)
+
+ @property
+ def OSVVMProjectFile(self) -> 'OSVVMProjectFile':
+ return self._osvvmProjectFile
+
+ def Parse(self, fileSet: FileSet):
+ self._fileSet.Parent = fileSet
+
+ for instruction in self._osvvmProjectFile._Parse():
+ if isinstance(instruction, OSVVMProjectFile.Include):
+ instruction.Parse(self._fileSet)
+ elif isinstance(instruction, OSVVMProjectFile.Analyze):
+ self._fileSet.AddFile(instruction.VHDLSourceFile)
+ elif isinstance(instruction, OSVVMProjectFile.Library):
+ self._fileSet.Design.AddVHDLLibrary(instruction.VHDLLibrary)
+# elif isinstance(instruction, OSVVMProjectFile.Build):
+
+ elif not isinstance(instruction, (OSVVMProjectFile.Empty, OSVVMProjectFile.Comment)):
+ raise Exception(f"Unknown instruction '{instruction.__class__.__name__}' in OSVVM project file '{self._osvvmProjectFile.ResolvedPath}'")
+
+ def Parse(self) -> None:
+ projectName = self._path.name
+ self._osvvmProject = Project(projectName, rootDirectory=self._path.parent)
+
+ fileSet = self._osvvmProject.DefaultDesign.DefaultFileSet
+
+ for instruction in self._Parse():
+ if isinstance(instruction, OSVVMProjectFile.Include):
+ instruction.Parse(fileSet)
+ elif isinstance(instruction, OSVVMProjectFile.Analyze):
+ fileSet.AddFile(instruction.VHDLSourceFile)
+ elif not isinstance(instruction, (OSVVMProjectFile.Empty, OSVVMProjectFile.Comment)):
+ raise Exception(f"Unknown instruction '{instruction.__class__.__name__}' in OSVVM project file '{self.ResolvedPath}'")
+
+ def _Parse(self) -> List:
+ path = self.ResolvedPath
+ if not path.exists():
+ raise Exception(f"OSVVM project file '{path}' not found.") from FileNotFoundError(f"File '{path}' not found.")
+
+ instructions: List = []
+ print()
+ with path.open("r", encoding="utf-8") as file:
+ i = 1
+ for line in file:
+ line = line.lstrip()
+
+ if line.startswith("#"):
+ comment = OSVVMProjectFile.Comment(i, line[1:])
+ instructions.append(comment)
+
+ elif line.startswith("analyze"):
+ vhdlFile = OSVVMProjectFile.Analyze(i, line[8:])
+ instructions.append(vhdlFile)
+
+ elif line.startswith("library"):
+ vhdlLibrary = OSVVMProjectFile.Library(i, line[8:])
+ instructions.append(vhdlLibrary)
+
+ elif line.startswith("include"):
+ include = OSVVMProjectFile.Include(i, path.parent, line[8:])
+ instructions.append(include)
+
+ elif line.startswith("build"):
+ parameter = line[6:]
+ print(f"BUILD: {parameter}")
+ elif line.startswith("if"):
+ print(f"IF (line={i}): {line[3:].rstrip()}")
+ elif line.startswith("}"):
+ print(f"}} (line={i}): {line[2:].rstrip()}")
+ elif len(line) == 0:
+ instructions.append(OSVVMProjectFile.Empty(i))
+ else:
+ print(f"UNKNOWN (line={i}): '{line.rstrip()}'")
+
+ i += 1
+
+ return instructions
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Verilog."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import WaveformExchangeFile
+
+
+
+[docs]
+@export
+class ValueChangeDumpFile(WaveformExchangeFile):
+ """Verilog's waveform file (``*.vcd``) for exchanging value changes as defined by IEEE Std. 1364."""
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Xilinx ISE."""
+from pyTooling.Decorators import export
+
+from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, HumanReadableContent
+
+
+
+
+
+
+
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+# ==================================================================================================================== #
+# _____ ____ _ _ ____ _ _ __ __ _ _ #
+# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+# |_| |___/ |__/ #
+# ==================================================================================================================== #
+# Authors: #
+# Patrick Lehmann #
+# #
+# License: #
+# ==================================================================================================================== #
+# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+# #
+# SPDX-License-Identifier: Apache-2.0 #
+# ==================================================================================================================== #
+#
+"""Specific file types and attributes for Xilinx Vivado."""
+from pathlib import Path
+from typing import Iterable, Optional as Nullable
+from xml.dom import minidom, Node
+
+from pyTooling.Decorators import export
+from pyTooling.MetaClasses import ExtendedType
+from pyVHDLModel import VHDLVersion
+
+from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design
+from pyEDAA.ProjectModel import File as Model_File
+from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
+from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
+from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
+
+
+
+
+
+
+
+
+
+
+class VivadoFileMixIn(metaclass=ExtendedType, mixin=True):
+ def _registerAttributes(self) -> None:
+ self._attributes[UsedInAttribute] = []
+
+
+
+[docs]
+@export
+class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn):
+ def _registerAttributes(self) -> None:
+ super()._registerAttributes()
+ VivadoFileMixIn._registerAttributes(self)
+
+
+
+
+[docs]
+@export
+class VerilogSourceFile(Model_VerilogSourceFile):
+ def _registerAttributes(self) -> None:
+ super()._registerAttributes()
+ VivadoFileMixIn._registerAttributes(self)
+
+
+
+
+[docs]
+@export
+class VHDLSourceFile(Model_VHDLSourceFile):
+ def _registerAttributes(self) -> None:
+ super()._registerAttributes()
+ VivadoFileMixIn._registerAttributes(self)
+
+
+
+
+[docs]
+@export
+class VivadoProjectFile(ProjectFile, XMLContent):
+ """A Vivado project file (``*.xpr``)."""
+
+ _xprProject: Project
+
+
+[docs]
+ def __init__(
+ self,
+ path: Path,
+ project: Nullable[Project] = None,
+ design: Nullable[Design] = None,
+ fileSet: Nullable[FileSet] = None
+ ) -> None:
+ super().__init__(path, project, design, fileSet)
+
+ self._xprProject = None
+
+
+ @property
+ def ProjectModel(self) -> Project:
+ return self._xprProject
+
+ def Parse(self) -> None:
+ if not self._path.exists():
+ raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.")
+
+ try:
+ root = minidom.parse(str(self._path)).documentElement
+ except Exception as ex:
+ raise Exception(f"Couldn't open '{self._path!s}'.") from ex
+
+ self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent)
+ self._ParseRootElement(root)
+
+ def _ParseRootElement(self, root) -> None:
+ for rootNode in root.childNodes:
+ if rootNode.nodeName == "FileSets":
+ self._ParseFileSets(rootNode)
+ break
+
+ def _ParseFileSets(self, filesetsNode) -> None:
+ for fileSetsNode in filesetsNode.childNodes:
+ if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet":
+ self._ParseFileSet(fileSetsNode)
+
+ def _ParseFileSet(self, filesetNode) -> None:
+ filesetName = filesetNode.getAttribute("Name")
+ fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign)
+
+ for fileNode in filesetNode.childNodes:
+ if fileNode.nodeType == Node.ELEMENT_NODE:
+ if fileNode.tagName == "File":
+ self._ParseFile(fileNode, fileset)
+ elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config":
+ self._ParseFileSetConfig(fileNode, fileset)
+
+ def _ParseFile(self, fileNode, fileset) -> None:
+ croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "")
+ filePath = Path(croppedPath)
+ if filePath.suffix in (".vhd", ".vhdl"):
+ self._ParseVHDLFile(fileNode, filePath, fileset)
+ elif filePath.suffix == ".xdc":
+ self._ParseXDCFile(fileNode, filePath, fileset)
+ elif filePath.suffix == ".v":
+ self._ParseVerilogFile(fileNode, filePath, fileset)
+ elif filePath.suffix == ".xci":
+ self._ParseXCIFile(fileNode, filePath, fileset)
+ else:
+ self._ParseDefaultFile(fileNode, filePath, fileset)
+
+ def _ParseVHDLFile(self, fileNode, path, fileset) -> None:
+ vhdlFile = VHDLSourceFile(path)
+ fileset.AddFile(vhdlFile)
+ usedInAttr = vhdlFile[UsedInAttribute]
+
+ for childNode in fileNode.childNodes:
+ if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo":
+ if childNode.getAttribute("SFType") == "VHDL2008":
+ vhdlFile.VHDLVersion = VHDLVersion.VHDL2008
+ else:
+ vhdlFile.VHDLVersion = VHDLVersion.VHDL93
+
+ for fileAttribute in childNode.childNodes:
+ if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr":
+ if fileAttribute.getAttribute("Name") == "Library":
+ libraryName = fileAttribute.getAttribute("Val")
+ vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName)
+ elif fileAttribute.getAttribute("Val") == "UsedIn":
+ usedInAttr.append(fileAttribute.getAttribute("Val"))
+
+ def _ParseDefaultFile(self, _, path, fileset) -> None:
+ File(path, fileSet=fileset)
+
+ def _ParseXDCFile(self, _, path, fileset) -> None:
+ XDCConstraintFile(path, fileSet=fileset)
+
+ def _ParseVerilogFile(self, _, path, fileset) -> None:
+ VerilogSourceFile(path, fileSet=fileset)
+
+ def _ParseXCIFile(self, _, path, fileset) -> None:
+ IPCoreInstantiationFile(path, fileSet=fileset)
+
+ def _ParseFileSetConfig(self, fileNode, fileset) -> None:
+ for option in fileNode.childNodes:
+ if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
+ if option.getAttribute("Name") == "TopModule":
+ fileset.TopLevel = option.getAttribute("Val")
+
+
+
+
+[docs]
+@export
+class XDCConstraintFile(ConstraintFile, SDCContent):
+ """A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``)."""
+
+
+
+
+
+
+
+
+[docs]
+@export
+class IPCoreInstantiationFile(XMLFile):
+ """A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``)."""
+
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+' + + '' + + _("Hide Search Matches") + + "
" + ) + ); + }, + + /** + * helper function to hide the search marks again + */ + hideSearchWords: () => { + document + .querySelectorAll("#searchbox .highlight-link") + .forEach((el) => el.remove()); + document + .querySelectorAll("span.highlighted") + .forEach((el) => el.classList.remove("highlighted")); + localStorage.removeItem("sphinx_highlight_terms") + }, + + initEscapeListener: () => { + // only install a listener if it is really needed + if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) return; + + document.addEventListener("keydown", (event) => { + // bail for input elements + if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return; + // bail with special keys + if (event.shiftKey || event.altKey || event.ctrlKey || event.metaKey) return; + if (DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS && (event.key === "Escape")) { + SphinxHighlight.hideSearchWords(); + event.preventDefault(); + } + }); + }, +}; + +_ready(() => { + /* Do not call highlightSearchWords() when we are on the search page. + * It will highlight words from the *previous* search query. + */ + if (typeof Search === "undefined") SphinxHighlight.highlightSearchWords(); + SphinxHighlight.initEscapeListener(); +}); diff --git a/coverage/class_index.html b/coverage/class_index.html new file mode 100644 index 00000000..ef1600d9 --- /dev/null +++ b/coverage/class_index.html @@ -0,0 +1,324 @@ + + + + ++ coverage.py v7.6.4, + created at 2024-11-08 22:18 +0000 +
+| File | +class | +statements | +missing | +excluded | +branches | +partial | +coverage | +
|---|---|---|---|---|---|---|---|
| pyEDAA/ProjectModel/Attributes.py | +KeyValueAttribute | +4 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/Attributes.py | +(no class) | +10 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +VivadoFileMixIn | +1 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +ConstraintFile | +2 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +VerilogSourceFile | +2 | +2 | +0 | +0 | +0 | +0% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +VHDLSourceFile | +2 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +VivadoProjectFile | +60 | +12 | +0 | +46 | +4 | +81% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +(no class) | +53 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/__init__.py | +Attribute | +7 | +5 | +0 | +6 | +1 | +23% | +
| pyEDAA/ProjectModel/__init__.py | +FileType | +9 | +0 | +0 | +2 | +0 | +100% | +
| pyEDAA/ProjectModel/__init__.py | +File | +84 | +23 | +0 | +42 | +16 | +67% | +
| pyEDAA/ProjectModel/__init__.py | +VHDLSourceFile | +44 | +18 | +2 | +18 | +2 | +61% | +
| pyEDAA/ProjectModel/__init__.py | +VerilogMixIn | +6 | +0 | +0 | +4 | +0 | +100% | +
| pyEDAA/ProjectModel/__init__.py | +SystemVerilogMixIn | +6 | +0 | +0 | +4 | +0 | +100% | +
| pyEDAA/ProjectModel/__init__.py | +VerilogBaseFile | +2 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/__init__.py | +SystemRDLSourceFile | +8 | +8 | +0 | +4 | +0 | +0% | +
| pyEDAA/ProjectModel/__init__.py | +FileSet | +196 | +73 | +4 | +122 | +28 | +59% | +
| pyEDAA/ProjectModel/__init__.py | +VHDLLibrary | +76 | +43 | +2 | +44 | +7 | +38% | +
| pyEDAA/ProjectModel/__init__.py | +Design | +145 | +70 | +0 | +84 | +18 | +48% | +
| pyEDAA/ProjectModel/__init__.py | +Project | +61 | +20 | +0 | +22 | +9 | +65% | +
| pyEDAA/ProjectModel/__init__.py | +(no class) | +426 | +0 | +0 | +0 | +0 | +100% | +
| Total | ++ | 1204 | +274 | +8 | +398 | +85 | +71% | +
+ No items found using the specified filter. +
+42 empty classes skipped.
++ coverage.py v7.6.4, + created at 2024-11-08 22:18 +0000 +
++ No items found using the specified filter. +
++ coverage.py v7.6.4, + created at 2024-11-08 22:18 +0000 +
+| File | +statements | +missing | +excluded | +branches | +partial | +coverage | +
|---|---|---|---|---|---|---|
| pyEDAA/ProjectModel/Attributes.py | +14 | +0 | +0 | +0 | +0 | +100% | +
| pyEDAA/ProjectModel/Xilinx/Vivado.py | +120 | +14 | +0 | +46 | +4 | +87% | +
| pyEDAA/ProjectModel/__init__.py | +1070 | +260 | +8 | +352 | +81 | +69% | +
| Total | +1204 | +274 | +8 | +398 | +85 | +71% | +
+ No items found using the specified filter. +
+1 empty file skipped.
++ « prev + ^ index + » next + + coverage.py v7.6.4, + created at 2024-11-08 22:18 +0000 +
+ +1# ==================================================================================================================== #
+2# _____ ____ _ _ ____ _ _ __ __ _ _ #
+3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+7# |_| |___/ |__/ #
+8# ==================================================================================================================== #
+9# Authors: #
+10# Patrick Lehmann #
+11# #
+12# License: #
+13# ==================================================================================================================== #
+14# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+15# #
+16# Licensed under the Apache License, Version 2.0 (the "License"); #
+17# you may not use this file except in compliance with the License. #
+18# You may obtain a copy of the License at #
+19# #
+20# http://www.apache.org/licenses/LICENSE-2.0 #
+21# #
+22# Unless required by applicable law or agreed to in writing, software #
+23# distributed under the License is distributed on an "AS IS" BASIS, #
+24# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+25# See the License for the specific language governing permissions and #
+26# limitations under the License. #
+27# #
+28# SPDX-License-Identifier: Apache-2.0 #
+29# ==================================================================================================================== #
+30#
+31"""A set of common attributes to store meta information on ProjectModel entities (project, design, fileset, file, ...)."""
+32from typing import Dict
+33from pyTooling.Decorators import export
+ +35from pyEDAA.ProjectModel import Attribute
+ + +38@export
+39class KeyValueAttribute(Attribute):
+40 KEY = "ID"
+ +42 _keyValuePairs: Dict[str, str]
+ +44 def __init__(self) -> None:
+45 super().__init__()
+ +47 self._keyValuePairs = {}
+ +49 def __getitem__(self, item: str) -> str:
+50 return self._keyValuePairs[item]
+ +52 def __setitem__(self, key: str, value: str) -> None:
+53 self._keyValuePairs[key] = value
++ « prev + ^ index + » next + + coverage.py v7.6.4, + created at 2024-11-08 22:18 +0000 +
+ +1# ==================================================================================================================== #
+2# _____ ____ _ _ ____ _ _ __ __ _ _ #
+3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+7# |_| |___/ |__/ #
+8# ==================================================================================================================== #
+9# Authors: #
+10# Patrick Lehmann #
+11# #
+12# License: #
+13# ==================================================================================================================== #
+14# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+15# Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture #
+16# #
+17# Licensed under the Apache License, Version 2.0 (the "License"); #
+18# you may not use this file except in compliance with the License. #
+19# You may obtain a copy of the License at #
+20# #
+21# http://www.apache.org/licenses/LICENSE-2.0 #
+22# #
+23# Unless required by applicable law or agreed to in writing, software #
+24# distributed under the License is distributed on an "AS IS" BASIS, #
+25# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+26# See the License for the specific language governing permissions and #
+27# limitations under the License. #
+28# #
+29# SPDX-License-Identifier: Apache-2.0 #
+30# ==================================================================================================================== #
+31#
+32"""An abstract model of EDA tool projects."""
+33__author__ = "Patrick Lehmann"
+34__email__ = "Paebbels@gmail.com"
+35__copyright__ = "2014-2024, Patrick Lehmann, Unai Martinez-Corral"
+36__license__ = "Apache License, Version 2.0"
+37__version__ = "0.5.0"
+38__keywords__ = ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"]
+ +40from os.path import relpath as path_relpath
+41from pathlib import Path as pathlib_Path
+42from sys import version_info
+43from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any
+ +45from pyTooling.Common import getFullyQualifiedName
+46from pyTooling.Decorators import export
+47from pyTooling.MetaClasses import ExtendedType
+48from pyTooling.Graph import Graph, Vertex
+49from pySVModel import SystemVerilogVersion
+50from pyVHDLModel import VHDLVersion
+51from pySystemRDLModel import SystemRDLVersion
+ + +54@export
+55class Attribute(metaclass=ExtendedType):
+56 KEY: str
+57 VALUE_TYPE: typing_Any
+ +59 @staticmethod
+60 def resolve(obj: typing_Any, key: Type['Attribute']):
+61 if isinstance(obj, File): 61 ↛ 63line 61 didn't jump to line 63 because the condition on line 61 was always true
+62 return obj._fileSet[key]
+63 elif isinstance(obj, FileSet):
+64 return obj._design[key]
+65 elif isinstance(obj, Design):
+66 return obj._project[key]
+67 else:
+68 raise Exception("Resolution error")
+ + +71@export
+72class FileType(ExtendedType):
+73 """
+74 A :term:`meta-class` to construct *FileType* classes.
+ +76 Modifications done by this meta-class:
+77 * Register all classes of type :class:`FileType` or derived variants in a class field :attr:`FileType.FileTypes` in this meta-class.
+78 """
+ +80 FileTypes: Dict[str, 'FileType'] = {} #: Dictionary of all classes of type :class:`FileType` or derived variants
+81 Any: 'FileType'
+ +83 def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs):
+84 super().__init__(name, bases, dictionary, **kwargs)
+85 cls.Any = cls
+ +87 def __new__(cls, className, baseClasses, classMembers: Dict, *args, **kwargs):
+88 fileType = super().__new__(cls, className, baseClasses, classMembers, *args, **kwargs)
+89 cls.FileTypes[className] = fileType
+90 return fileType
+ +92 def __getattr__(cls, item) -> 'FileType':
+93 if item[:2] != "__" and item[-2:] != "__":
+94 return cls.FileTypes[item]
+95 else:
+96 return super().__getattribute__(item)
+ +98 def __contains__(cls, item) -> bool:
+99 return issubclass(item, cls)
+ + +102@export
+103class File(metaclass=FileType, slots=True):
+104 """
+105 A :term:`File` represents a file in a design. This :term:`base-class` is used
+106 for all derived file classes.
+ +108 A file can be created standalone and later associated to a fileset, design and
+109 project. Or a fileset, design and/or project can be associated immediately
+110 while creating a file.
+ +112 :arg path: Relative or absolute path to the file.
+113 :arg project: Project the file is associated with.
+114 :arg design: Design the file is associated with.
+115 :arg fileSet: Fileset the file is associated with.
+116 """
+ +118 _path: pathlib_Path
+119 _fileType: 'FileType'
+120 _project: Nullable['Project']
+121 _design: Nullable['Design']
+122 _fileSet: Nullable['FileSet']
+123 _attributes: Dict[Type[Attribute], typing_Any]
+ +125 def __init__(
+126 self,
+127 path: pathlib_Path,
+128 project: Nullable["Project"] = None,
+129 design: Nullable["Design"] = None,
+130 fileSet: Nullable["FileSet"] = None
+131 ):
+132 self._fileType = getattr(FileTypes, self.__class__.__name__)
+133 self._path = path
+134 if project is not None:
+135 self._project = project
+136 self._design = design
+137 if fileSet is not None: 137 ↛ 138line 137 didn't jump to line 138 because the condition on line 137 was never true
+138 self.FileSet = fileSet
+139 elif design is not None:
+140 self._project = design._project
+141 self._design = design
+142 self.FileSet = design.DefaultFileSet if fileSet is None else fileSet
+143 elif fileSet is not None:
+144 design = fileSet._design
+145 if design is not None:
+146 self._project = design._project
+147 else:
+148 self._project = None
+149 self._design = design
+150 self.FileSet = fileSet
+151 else:
+152 self._project = None
+153 self._design = None
+154 self._fileSet = None
+ +156 self._attributes = {}
+157 self._registerAttributes()
+ +159 def _registerAttributes(self) -> None:
+160 pass
+ +162 @property
+163 def FileType(self) -> 'FileType':
+164 """Read-only property to return the file type of this file."""
+165 return self._fileType
+ +167 @property
+168 def Path(self) -> pathlib_Path:
+169 """Read-only property returning the path of this file."""
+170 return self._path
+ +172 # TODO: setter?
+ +174 @property
+175 def ResolvedPath(self) -> pathlib_Path:
+176 """Read-only property returning the resolved path of this file."""
+177 if self._path.is_absolute(): 177 ↛ 178line 177 didn't jump to line 178 because the condition on line 177 was never true
+178 return self._path.resolve()
+179 elif self._fileSet is not None: 179 ↛ 189line 179 didn't jump to line 189 because the condition on line 179 was always true
+180 path = (self._fileSet.ResolvedPath / self._path).resolve()
+ +182 if path.is_absolute(): 182 ↛ 186line 182 didn't jump to line 186 because the condition on line 182 was always true
+183 return path
+184 else:
+185 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+186 return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+187 else:
+188 # TODO: message and exception type
+189 raise Exception("")
+ +191 @property
+192 def Project(self) -> Nullable['Project']:
+193 """Property setting or returning the project this file is used in."""
+194 return self._project
+ +196 @Project.setter
+197 def Project(self, value: 'Project') -> None:
+198 self._project = value
+ +200 if self._fileSet is None: 200 ↛ exitline 200 didn't return from function 'Project' because the condition on line 200 was always true
+201 self._project.DefaultDesign.DefaultFileSet.AddFile(self)
+ +203 @property
+204 def Design(self) -> Nullable['Design']:
+205 """Property setting or returning the design this file is used in."""
+206 return self._design
+ +208 @Design.setter
+209 def Design(self, value: 'Design') -> None:
+210 self._design = value
+ +212 if self._fileSet is None: 212 ↛ 215line 212 didn't jump to line 215 because the condition on line 212 was always true
+213 self._design.DefaultFileSet.AddFile(self)
+ +215 if self._project is None: 215 ↛ 217line 215 didn't jump to line 217 because the condition on line 215 was always true
+216 self._project = value._project
+217 elif self._project is not value._project:
+218 raise Exception("The design's project is not identical to the already assigned project.")
+ +220 @property
+221 def FileSet(self) -> Nullable['FileSet']:
+222 """Property setting or returning the fileset this file is used in."""
+223 return self._fileSet
+ +225 @FileSet.setter
+226 def FileSet(self, value: 'FileSet') -> None:
+227 self._fileSet = value
+228 value._files.append(self)
+ +230 def Validate(self) -> None:
+231 """Validate this file."""
+232 if self._path is None: 232 ↛ 233line 232 didn't jump to line 233 because the condition on line 232 was never true
+233 raise Exception("Validation: File has no path.")
+234 try:
+235 path = self.ResolvedPath
+236 except Exception as ex:
+237 raise Exception(f"Validation: File '{self._path}' could not compute resolved path.") from ex
+238 if not path.exists(): 238 ↛ 239line 238 didn't jump to line 239 because the condition on line 238 was never true
+239 raise Exception(f"Validation: File '{self._path}' (={path}) does not exist.")
+240 if not path.is_file(): 240 ↛ 241line 240 didn't jump to line 241 because the condition on line 240 was never true
+241 raise Exception(f"Validation: File '{self._path}' (={path}) is not a file.")
+ +243 if self._fileSet is None: 243 ↛ 244line 243 didn't jump to line 244 because the condition on line 243 was never true
+244 raise Exception(f"Validation: File '{self._path}' has no fileset.")
+245 if self._design is None: 245 ↛ 246line 245 didn't jump to line 246 because the condition on line 245 was never true
+246 raise Exception(f"Validation: File '{self._path}' has no design.")
+247 if self._project is None: 247 ↛ 248line 247 didn't jump to line 248 because the condition on line 247 was never true
+248 raise Exception(f"Validation: File '{self._path}' has no project.")
+ +250 def __len__(self) -> int:
+251 """
+252 Returns number of attributes set on this file.
+ +254 :returns: The number if attributes set on this file.
+255 """
+256 return len(self._attributes)
+ +258 def __getitem__(self, key: Type[Attribute]) -> Any:
+259 """Index access for returning attributes on this file.
+ +261 :param key: The attribute type.
+262 :returns: The attribute's value.
+263 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+264 """
+265 if not issubclass(key, Attribute): 265 ↛ 266line 265 didn't jump to line 266 because the condition on line 265 was never true
+266 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +268 try:
+269 return self._attributes[key]
+270 except KeyError:
+271 try:
+272 return key.resolve(self, key)
+273 except KeyError:
+274 attribute = key()
+275 self._attributes[key] = attribute
+276 return attribute
+ +278 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+279 """
+280 Index access for adding or setting attributes on this file.
+ +282 :param key: The attribute type.
+283 :param value: The attributes value.
+284 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+285 """
+286 if not issubclass(key, Attribute): 286 ↛ 287line 286 didn't jump to line 287 because the condition on line 286 was never true
+287 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +289 self._attributes[key] = value
+ +291 def __delitem__(self, key: Type[Attribute]) -> None:
+292 """
+293 Index access for deleting attributes on this file.
+ +295 :param key: The attribute type.
+296 """
+297 if not issubclass(key, Attribute): 297 ↛ 298line 297 didn't jump to line 298 because the condition on line 297 was never true
+298 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +300 del self._attributes[key]
+ +302 def __str__(self) -> str:
+303 return f"{self._path}"
+ + +306FileTypes = File
+ + +309@export
+310class HumanReadableContent(metaclass=ExtendedType, mixin=True):
+311 """A file type representing human-readable contents."""
+ + +314@export
+315class XMLContent(HumanReadableContent, mixin=True):
+316 """A file type representing XML contents."""
+ + +319@export
+320class YAMLContent(HumanReadableContent, mixin=True):
+321 """A file type representing YAML contents."""
+ + +324@export
+325class JSONContent(HumanReadableContent, mixin=True):
+326 """A file type representing JSON contents."""
+ + +329@export
+330class INIContent(HumanReadableContent, mixin=True):
+331 """A file type representing INI contents."""
+ + +334@export
+335class TOMLContent(HumanReadableContent, mixin=True):
+336 """A file type representing TOML contents."""
+ + +339@export
+340class TCLContent(HumanReadableContent, mixin=True):
+341 """A file type representing content in TCL code."""
+ + +344@export
+345class SDCContent(TCLContent, mixin=True):
+346 """A file type representing contents as Synopsys Design Constraints (SDC)."""
+ + +349@export
+350class PythonContent(HumanReadableContent, mixin=True):
+351 """A file type representing contents as Python source code."""
+ + +354@export
+355class TextFile(File, HumanReadableContent):
+356 """A text file (``*.txt``)."""
+ + +359@export
+360class LogFile(File, HumanReadableContent):
+361 """A log file (``*.log``)."""
+ + +364@export
+365class XMLFile(File, XMLContent):
+366 """An XML file (``*.xml``)."""
+ + +369@export
+370class SourceFile(File):
+371 """Base-class of all source files."""
+ + +374@export
+375class HDLSourceFile(SourceFile):
+376 """Base-class of all HDL source files."""
+ + +379@export
+380class RDLSourceFile(SourceFile):
+381 """Base-class of all RDL source files."""
+ + +384@export
+385class NetlistFile(SourceFile):
+386 """Base-class of all netlist source files."""
+ + +389@export
+390class EDIFNetlistFile(NetlistFile):
+391 """Netlist file in EDIF (Electronic Design Interchange Format)."""
+ + +394@export
+395class TCLSourceFile(SourceFile, TCLContent):
+396 """A TCL source file."""
+ + +399@export
+400class VHDLSourceFile(HDLSourceFile, HumanReadableContent):
+401 """
+402 A VHDL source file (of any language version).
+ +404 :arg path: Relative or absolute path to the file.
+405 :arg vhdlLibrary: VHDLLibrary this VHDL source file is associated wih.
+406 :arg vhdlVersion: VHDLVersion this VHDL source file is associated wih.
+407 :arg project: Project the file is associated with.
+408 :arg design: Design the file is associated with.
+409 :arg fileSet: Fileset the file is associated with.
+410 """
+ +412 _vhdlLibrary: Nullable['VHDLLibrary']
+413 _vhdlVersion: VHDLVersion
+ +415 def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: Nullable[VHDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
+416 super().__init__(path, project, design, fileSet)
+ +418 if isinstance(vhdlLibrary, str): 418 ↛ 419line 418 didn't jump to line 419 because the condition on line 418 was never true
+419 if design is not None:
+420 try:
+421 vhdlLibrary = design.VHDLLibraries[vhdlLibrary]
+422 except KeyError as ex:
+423 raise Exception(f"VHDL library '{vhdlLibrary}' not found in design '{design.Name}'.") from ex
+424 elif project is not None:
+425 try:
+426 vhdlLibrary = project.DefaultDesign.VHDLLibraries[vhdlLibrary]
+427 except KeyError as ex:
+428 raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex
+429 else:
+430 raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.")
+431 elif isinstance(vhdlLibrary, VHDLLibrary):
+432 self._vhdlLibrary = vhdlLibrary
+433 vhdlLibrary.AddFile(self)
+434 elif vhdlLibrary is None: 434 ↛ 437line 434 didn't jump to line 437 because the condition on line 434 was always true
+435 self._vhdlLibrary = None
+436 else:
+437 ex = TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.")
+438 if version_info >= (3, 11): # pragma: no cover
+439 ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.")
+440 raise ex
+ +442 self._vhdlVersion = vhdlVersion
+ +444 def Validate(self) -> None:
+445 """Validate this VHDL source file."""
+446 super().Validate()
+ +448 try:
+449 _ = self.VHDLLibrary
+450 except Exception as ex:
+451 raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLLibrary assigned.") from ex
+452 try:
+453 _ = self.VHDLVersion
+454 except Exception as ex:
+455 raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLVersion assigned.") from ex
+ +457 @property
+458 def VHDLLibrary(self) -> 'VHDLLibrary':
+459 """Property setting or returning the VHDL library this VHDL source file is used in."""
+460 if self._vhdlLibrary is not None:
+461 return self._vhdlLibrary
+462 elif self._fileSet is not None:
+463 return self._fileSet.VHDLLibrary
+464 else:
+465 raise Exception("VHDLLibrary was neither set locally nor globally.")
+ +467 @VHDLLibrary.setter
+468 def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+469 self._vhdlLibrary = value
+470 value._files.append(self)
+ +472 @property
+473 def VHDLVersion(self) -> VHDLVersion:
+474 """Property setting or returning the VHDL version this VHDL source file is used in."""
+475 if self._vhdlVersion is not None:
+476 return self._vhdlVersion
+477 elif self._fileSet is not None:
+478 return self._fileSet.VHDLVersion
+479 else:
+480 raise Exception("VHDLVersion was neither set locally nor globally.")
+ +482 @VHDLVersion.setter
+483 def VHDLVersion(self, value: VHDLVersion) -> None:
+484 self._vhdlVersion = value
+ +486 def __repr__(self) -> str:
+487 return f"<VHDL file: '{self.ResolvedPath}'; lib: '{self.VHDLLibrary}'; version: {self.VHDLVersion}>"
+ + +490class VerilogMixIn(metaclass=ExtendedType, mixin=True):
+491 @property
+492 def VerilogVersion(self) -> SystemVerilogVersion:
+493 """Property setting or returning the Verilog version this Verilog source file is used in."""
+494 if self._version is not None:
+495 return self._version
+496 elif self._fileSet is not None:
+497 return self._fileSet.VerilogVersion
+498 else:
+499 raise Exception("VerilogVersion was neither set locally nor globally.")
+ +501 @VerilogVersion.setter
+502 def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+503 self._version = value
+ + +506class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True):
+507 @property
+508 def SVVersion(self) -> SystemVerilogVersion:
+509 """Property setting or returning the SystemVerilog version this SystemVerilog source file is used in."""
+510 if self._version is not None:
+511 return self._version
+512 elif self._fileSet is not None:
+513 return self._fileSet.SVVersion
+514 else:
+515 raise Exception("SVVersion was neither set locally nor globally.")
+ +517 @SVVersion.setter
+518 def SVVersion(self, value: SystemVerilogVersion) -> None:
+519 self._version = value
+ + +522@export
+523class VerilogBaseFile(HDLSourceFile, HumanReadableContent):
+524 _version: SystemVerilogVersion
+ +526 def __init__(self, path: pathlib_Path, version: Nullable[SystemVerilogVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
+527 super().__init__(path, project, design, fileSet)
+ +529 self._version = version
+ + +532@export
+533class VerilogSourceFile(VerilogBaseFile, VerilogMixIn):
+534 """A Verilog source file (of any language version)."""
+ + +537@export
+538class VerilogHeaderFile(VerilogBaseFile, VerilogMixIn):
+539 """A Verilog header file (of any language version)."""
+ + +542@export
+543class SystemVerilogBaseFile(VerilogBaseFile):
+544 ...
+ + +547@export
+548class SystemVerilogSourceFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+549 """A SystemVerilog source file (of any language version)."""
+ + +552@export
+553class SystemVerilogHeaderFile(SystemVerilogBaseFile, SystemVerilogMixIn):
+554 """A SystemVerilog header file (of any language version)."""
+ + +557@export
+558class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent):
+559 """A SystemRDL source file (of any language version)."""
+ +561 _srdlVersion: SystemRDLVersion
+ +563 def __init__(self, path: pathlib_Path, srdlVersion: Nullable[SystemRDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None):
+564 super().__init__(path, project, design, fileSet)
+ +566 self._srdlVersion = srdlVersion
+ +568 @property
+569 def SystemRDLVersion(self) -> SystemRDLVersion:
+570 """Property setting or returning the SystemRDL version this SystemRDL source file is used in."""
+571 if self._srdlVersion is not None:
+572 return self._srdlVersion
+573 elif self._fileSet is not None:
+574 return self._fileSet.SRDLVersion
+575 else:
+576 raise Exception("SRDLVersion was neither set locally nor globally.")
+ +578 @SystemRDLVersion.setter
+579 def SystemRDLVersion(self, value: SystemRDLVersion) -> None:
+580 self._srdlVersion = value
+ + +583@export
+584class PythonSourceFile(SourceFile, PythonContent):
+585 """A Python source file."""
+ + +588# TODO: move to a Cocotb module
+589@export
+590class CocotbPythonFile(PythonSourceFile):
+591 """A Python source file used by Cocotb."""
+ + +594@export
+595class ConstraintFile(File, HumanReadableContent):
+596 """Base-class of all constraint files."""
+ + +599@export
+600class ProjectFile(File):
+601 """Base-class of all tool-specific project files."""
+ + +604@export
+605class CSourceFile(SourceFile):
+606 """Base-class of all ANSI-C source files."""
+ + +609@export
+610class CppSourceFile(SourceFile):
+611 """Base-class of all ANSI-C++ source files."""
+ + +614@export
+615class SettingFile(File):
+616 """Base-class of all tool-specific setting files."""
+ + +619@export
+620class SimulationAnalysisFile(File):
+621 """Base-class of all tool-specific analysis files."""
+ + +624@export
+625class SimulationElaborationFile(File):
+626 """Base-class of all tool-specific elaboration files."""
+ + +629@export
+630class SimulationStartFile(File):
+631 """Base-class of all tool-specific simulation start-up files."""
+ + +634@export
+635class SimulationRunFile(File):
+636 """Base-class of all tool-specific simulation run (execution) files."""
+ + +639@export
+640class WaveformConfigFile(File):
+641 """Base-class of all tool-specific waveform configuration files."""
+ + +644@export
+645class WaveformDatabaseFile(File):
+646 """Base-class of all tool-specific waveform database files."""
+ + +649@export
+650class WaveformExchangeFile(File):
+651 """Base-class of all tool-independent waveform exchange files."""
+ + +654@export
+655class FileSet(metaclass=ExtendedType, slots=True):
+656 """
+657 A :term:`FileSet` represents a group of files. Filesets can have sub-filesets.
+ +659 The order of insertion is preserved. A fileset can be created standalone and
+660 later associated to another fileset, design and/or project. Or a fileset,
+661 design and/or project can be associated immediately while creating the
+662 fileset.
+ +664 :arg name: Name of this fileset.
+665 :arg topLevel: Name of the fileset's toplevel.
+666 :arg directory: Path of this fileset (absolute or relative to a parent fileset or design).
+667 :arg project: Project the file is associated with.
+668 :arg design: Design the file is associated with.
+669 :arg parent: Parent fileset if this fileset is nested.
+670 :arg vhdlLibrary: Default VHDL library for files in this fileset, if not specified for the file itself.
+671 :arg vhdlVersion: Default VHDL version for files in this fileset, if not specified for the file itself.
+672 :arg verilogVersion: Default Verilog version for files in this fileset, if not specified for the file itself.
+673 :arg svVersion: Default SystemVerilog version for files in this fileset, if not specified for the file itself.
+674 :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself.
+675 """
+ +677 _name: str
+678 _topLevel: Nullable[str]
+679 _project: Nullable['Project']
+680 _design: Nullable['Design']
+681 _directory: pathlib_Path
+682 _parent: Nullable['FileSet']
+683 _fileSets: Dict[str, 'FileSet']
+684 _files: List[File]
+685 _set: Set
+686 _attributes: Dict[Type[Attribute], typing_Any]
+687 _vhdlLibraries: Dict[str, 'VHDLLibrary']
+688 _vhdlLibrary: 'VHDLLibrary'
+689 _vhdlVersion: VHDLVersion
+690 _verilogVersion: SystemVerilogVersion
+691 _svVersion: SystemVerilogVersion
+692 _srdlVersion: SystemRDLVersion
+ +694 def __init__(
+695 self,
+696 name: str,
+697 topLevel: Nullable[str] = None,
+698 directory: pathlib_Path = pathlib_Path("."),
+699 project: Nullable["Project"] = None,
+700 design: Nullable["Design"] = None,
+701 parent: Nullable['FileSet'] = None,
+702 vhdlLibrary: Union[str, 'VHDLLibrary'] = None,
+703 vhdlVersion: Nullable[VHDLVersion] = None,
+704 verilogVersion: Nullable[SystemVerilogVersion] = None,
+705 svVersion: Nullable[SystemVerilogVersion] = None,
+706 srdlVersion: Nullable[SystemRDLVersion] = None
+707 ):
+708 self._name = name
+709 self._topLevel = topLevel
+710 if project is not None:
+711 self._project = project
+712 self._design = design if design is not None else project.DefaultDesign
+ +714 elif design is not None:
+715 self._project = design._project
+716 self._design = design
+717 else:
+718 self._project = None
+719 self._design = None
+720 self._directory = directory
+721 self._parent = parent
+722 self._fileSets = {}
+723 self._files = []
+724 self._set = set()
+ +726 if design is not None:
+727 design._fileSets[name] = self
+ +729 self._attributes = {}
+730 self._vhdlLibraries = {}
+ +732 # TODO: handle if vhdlLibrary is a string
+733 self._vhdlLibrary = vhdlLibrary
+734 self._vhdlVersion = vhdlVersion
+735 self._verilogVersion = verilogVersion
+736 self._svVersion = svVersion
+737 self._srdlVersion = srdlVersion
+ +739 @property
+740 def Name(self) -> str:
+741 """Property setting or returning the fileset's name."""
+742 return self._name
+ +744 @Name.setter
+745 def Name(self, value: str) -> None:
+746 self._name = value
+ +748 @property
+749 def TopLevel(self) -> str:
+750 """Property setting or returning the fileset's toplevel."""
+751 return self._topLevel
+ +753 @TopLevel.setter
+754 def TopLevel(self, value: str) -> None:
+755 self._topLevel = value
+ +757 @property
+758 def Project(self) -> Nullable['Project']:
+759 """Property setting or returning the project this fileset is used in."""
+760 return self._project
+ +762 @Project.setter
+763 def Project(self, value: 'Project') -> None:
+764 self._project = value
+ +766 @property
+767 def Design(self) -> Nullable['Design']:
+768 """Property setting or returning the design this fileset is used in."""
+769 if self._design is not None:
+770 return self._design
+771 elif self._parent is not None: 771 ↛ 772line 771 didn't jump to line 772 because the condition on line 771 was never true
+772 return self._parent.Design
+773 else:
+774 return None
+775 # TODO: raise exception instead
+776 # QUESTION: how to handle if design and parent is set?
+ +778 @Design.setter
+779 def Design(self, value: 'Design') -> None:
+780 self._design = value
+781 if self._project is None: 781 ↛ 783line 781 didn't jump to line 783 because the condition on line 781 was always true
+782 self._project = value._project
+783 elif self._project is not value._project:
+784 raise Exception("The design's project is not identical to the already assigned project.")
+ +786 @property
+787 def Directory(self) -> pathlib_Path:
+788 """Property setting or returning the directory this fileset is located in."""
+789 return self._directory
+ +791 @Directory.setter
+792 def Directory(self, value: pathlib_Path) -> None:
+793 self._directory = value
+ +795 @property
+796 def ResolvedPath(self) -> pathlib_Path:
+797 """Read-only property returning the resolved path of this fileset."""
+798 if self._directory.is_absolute(): 798 ↛ 799line 798 didn't jump to line 799 because the condition on line 798 was never true
+799 return self._directory.resolve()
+800 else:
+801 if self._parent is not None: 801 ↛ 802line 801 didn't jump to line 802 because the condition on line 801 was never true
+802 directory = self._parent.ResolvedPath
+803 elif self._design is not None: 803 ↛ 805line 803 didn't jump to line 805 because the condition on line 803 was always true
+804 directory = self._design.ResolvedPath
+805 elif self._project is not None:
+806 directory = self._project.ResolvedPath
+807 else:
+808 # TODO: message and exception type
+809 raise Exception("")
+ +811 directory = (directory / self._directory).resolve()
+812 if directory.is_absolute(): 812 ↛ 816line 812 didn't jump to line 816 because the condition on line 812 was always true
+813 return directory
+814 else:
+815 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+816 return pathlib_Path(path_relpath(directory, pathlib_Path.cwd()))
+ +818 @property
+819 def Parent(self) -> Nullable['FileSet']:
+820 """Property setting or returning the parent fileset this fileset is used in."""
+821 return self._parent
+ +823 @Parent.setter
+824 def Parent(self, value: 'FileSet') -> None:
+825 self._parent = value
+826 value._fileSets[self._name] = self
+827 # TODO: check it it already exists
+828 # QUESTION: make an Add fileset method?
+ +830 @property
+831 def FileSets(self) -> Dict[str, 'FileSet']:
+832 """Read-only property returning the dictionary of sub-filesets."""
+833 return self._fileSets
+ +835 def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[bool, str, 'FileSet'] = None) -> Generator[File, None, None]:
+836 """
+837 Method returning the files of this fileset.
+ +839 :arg fileType: A filter for file types. Default: ``Any``.
+840 :arg fileSet: Specifies how to handle sub-filesets.
+841 """
+842 if fileSet is False: 842 ↛ 843line 842 didn't jump to line 843 because the condition on line 842 was never true
+843 for file in self._files:
+844 if file.FileType in fileType:
+845 yield file
+846 elif fileSet is None: 846 ↛ 854line 846 didn't jump to line 854 because the condition on line 846 was always true
+847 for fileSet in self._fileSets.values(): 847 ↛ 848line 847 didn't jump to line 848 because the loop on line 847 never started
+848 for file in fileSet.Files(fileType):
+849 yield file
+850 for file in self._files:
+851 if file.FileType in fileType:
+852 yield file
+853 else:
+854 if isinstance(fileSet, str):
+855 fileSetName = fileSet
+856 try:
+857 fileSet = self._fileSets[fileSetName]
+858 except KeyError as ex:
+859 raise Exception(f"Fileset {fileSetName} not bound to fileset {self.Name}.") from ex
+860 elif not isinstance(fileSet, FileSet):
+861 raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+ +863 for file in fileSet.Files(fileType):
+864 yield file
+ +866 def AddFileSet(self, fileSet: "FileSet") -> None:
+867 """
+868 Method to add a single sub-fileset to this fileset.
+ +870 :arg fileSet: A fileset to add to this fileset as sub-fileset.
+871 """
+872 if not isinstance(fileSet, FileSet): 872 ↛ 873line 872 didn't jump to line 873 because the condition on line 872 was never true
+873 raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+874 elif fileSet in self._fileSets: 874 ↛ 875line 874 didn't jump to line 875 because the condition on line 874 was never true
+875 raise Exception("Sub-fileset already contains this fileset.")
+876 elif fileSet.Name in self._fileSets.keys(): 876 ↛ 877line 876 didn't jump to line 877 because the condition on line 876 was never true
+877 raise Exception(f"Fileset already contains a sub-fileset named '{fileSet.Name}'.")
+ +879 self._fileSets[fileSet.Name] = fileSet
+880 fileSet._parent = self
+ +882 def AddFileSets(self, fileSets: Iterable["FileSet"]) -> None:
+883 """
+884 Method to add a multiple sub-filesets to this fileset.
+ +886 :arg fileSets: An iterable of filesets to add each to the fileset.
+887 """
+888 for fileSet in fileSets:
+889 self.AddFileSet(fileSet)
+ +891 @property
+892 def FileSetCount(self) -> int:
+893 """Returns number of file sets excl. sub-filesets."""
+894 return len(self._fileSets)
+ +896 @property
+897 def TotalFileSetCount(self) -> int:
+898 """Returns number of file sets incl. sub-filesets."""
+899 fileSetCount = len(self._fileSets)
+900 for fileSet in self._fileSets.values():
+901 fileSetCount += fileSet.TotalFileSetCount
+ +903 return fileSetCount
+ +905 def AddFile(self, file: File) -> None:
+906 """
+907 Method to add a single file to this fileset.
+ +909 :arg file: A file to add to this fileset.
+910 """
+911 if not isinstance(file, File):
+912 raise TypeError("Parameter 'file' is not of type ProjectModel.File.")
+913 elif file._fileSet is not None:
+914 ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.")
+915 if version_info >= (3, 11): # pragma: no cover
+916 ex.add_note(f"A file can't be assigned to another fileset.")
+917 raise ex
+918 elif file in self._set: 918 ↛ 919line 918 didn't jump to line 919 because the condition on line 918 was never true
+919 ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.")
+920 if version_info >= (3, 11): # pragma: no cover
+921 ex.add_note(f"A file can't be added twice to a fileset.")
+922 raise ex
+ +924 self._files.append(file)
+925 self._set.add(file)
+926 file._fileSet = self
+ +928 def AddFiles(self, files: Iterable[File]) -> None:
+929 """
+930 Method to add a multiple files to this fileset.
+ +932 :arg files: An iterable of files to add each to the fileset.
+933 """
+934 for file in files:
+935 self.AddFile(file)
+ +937 @property
+938 def FileCount(self) -> int:
+939 """Returns number of files excl. sub-filesets."""
+940 return len(self._files)
+ +942 @property
+943 def TotalFileCount(self) -> int:
+944 """Returns number of files incl. the files in sub-filesets."""
+945 fileCount = len(self._files)
+946 for fileSet in self._fileSets.values():
+947 fileCount += fileSet.FileCount
+ +949 return fileCount
+ +951 def Validate(self) -> None:
+952 """Validate this fileset."""
+953 if self._name is None or self._name == "": 953 ↛ 954line 953 didn't jump to line 954 because the condition on line 953 was never true
+954 raise Exception("Validation: FileSet has no name.")
+ +956 if self._directory is None: 956 ↛ 957line 956 didn't jump to line 957 because the condition on line 956 was never true
+957 raise Exception(f"Validation: FileSet '{self._name}' has no directory.")
+958 try:
+959 path = self.ResolvedPath
+960 except Exception as ex:
+961 raise Exception(f"Validation: FileSet '{self._name}' could not compute resolved path.") from ex
+962 if not path.exists(): 962 ↛ 963line 962 didn't jump to line 963 because the condition on line 962 was never true
+963 raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' does not exist.")
+964 if not path.is_dir(): 964 ↛ 965line 964 didn't jump to line 965 because the condition on line 964 was never true
+965 raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' is not a directory.")
+ +967 if self._design is None: 967 ↛ 968line 967 didn't jump to line 968 because the condition on line 967 was never true
+968 raise Exception(f"Validation: FileSet '{self._directory}' has no design.")
+969 if self._project is None: 969 ↛ 970line 969 didn't jump to line 970 because the condition on line 969 was never true
+970 raise Exception(f"Validation: FileSet '{self._directory}' has no project.")
+ +972 for fileSet in self._fileSets.values(): 972 ↛ 973line 972 didn't jump to line 973 because the loop on line 972 never started
+973 fileSet.Validate()
+974 for file in self._files: 974 ↛ 975line 974 didn't jump to line 975 because the loop on line 974 never started
+975 file.Validate()
+ +977 def GetOrCreateVHDLLibrary(self, name) -> 'VHDLLibrary':
+978 if name in self._vhdlLibraries:
+979 return self._vhdlLibraries[name]
+980 elif name in self._design._vhdlLibraries:
+981 library = self._design._vhdlLibraries[name]
+982 self._vhdlLibraries[name] = library
+983 return library
+984 else:
+985 library = VHDLLibrary(name, design=self._design, vhdlVersion=self._vhdlVersion)
+986 self._vhdlLibraries[name] = library
+987 return library
+ +989 @property
+990 def VHDLLibrary(self) -> 'VHDLLibrary':
+991 """Property setting or returning the VHDL library of this fileset."""
+992 if self._vhdlLibrary is not None:
+993 return self._vhdlLibrary
+994 elif self._parent is not None: 994 ↛ 996line 994 didn't jump to line 996 because the condition on line 994 was always true
+995 return self._parent.VHDLLibrary
+996 elif self._design is not None:
+997 return self._design.VHDLLibrary
+998 else:
+999 raise Exception("VHDLLibrary was neither set locally nor globally.")
+ +1001 @VHDLLibrary.setter
+1002 def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
+1003 self._vhdlLibrary = value
+ +1005 @property
+1006 def VHDLVersion(self) -> VHDLVersion:
+1007 """Property setting or returning the VHDL version of this fileset."""
+1008 if self._vhdlVersion is not None:
+1009 return self._vhdlVersion
+1010 elif self._parent is not None:
+1011 return self._parent.VHDLVersion
+1012 elif self._design is not None: 1012 ↛ 1015line 1012 didn't jump to line 1015 because the condition on line 1012 was always true
+1013 return self._design.VHDLVersion
+1014 else:
+1015 raise Exception("VHDLVersion was neither set locally nor globally.")
+ +1017 @VHDLVersion.setter
+1018 def VHDLVersion(self, value: VHDLVersion) -> None:
+1019 self._vhdlVersion = value
+ +1021 @property
+1022 def VerilogVersion(self) -> SystemVerilogVersion:
+1023 """Property setting or returning the Verilog version of this fileset."""
+1024 if self._verilogVersion is not None:
+1025 return self._verilogVersion
+1026 elif self._parent is not None:
+1027 return self._parent.VerilogVersion
+1028 elif self._design is not None: 1028 ↛ 1031line 1028 didn't jump to line 1031 because the condition on line 1028 was always true
+1029 return self._design.VerilogVersion
+1030 else:
+1031 raise Exception("VerilogVersion was neither set locally nor globally.")
+ +1033 @VerilogVersion.setter
+1034 def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+1035 self._verilogVersion = value
+ +1037 @property
+1038 def SVVersion(self) -> SystemVerilogVersion:
+1039 """Property setting or returning the SystemVerilog version of this fileset."""
+1040 if self._svVersion is not None:
+1041 return self._svVersion
+1042 elif self._parent is not None:
+1043 return self._parent.SVVersion
+1044 elif self._design is not None: 1044 ↛ 1047line 1044 didn't jump to line 1047 because the condition on line 1044 was always true
+1045 return self._design.SVVersion
+1046 else:
+1047 raise Exception("SVVersion was neither set locally nor globally.")
+ +1049 @SVVersion.setter
+1050 def SVVersion(self, value: SystemVerilogVersion) -> None:
+1051 self._svVersion = value
+ +1053 @property
+1054 def SRDLVersion(self) -> SystemRDLVersion:
+1055 if self._srdlVersion is not None:
+1056 return self._srdlVersion
+1057 elif self._parent is not None:
+1058 return self._parent.SRDLVersion
+1059 elif self._design is not None:
+1060 return self._design.SRDLVersion
+1061 else:
+1062 raise Exception("SRDLVersion was neither set locally nor globally.")
+ +1064 @SRDLVersion.setter
+1065 def SRDLVersion(self, value: SystemRDLVersion) -> None:
+1066 self._srdlVersion = value
+ +1068 def __len__(self) -> int:
+1069 """
+1070 Returns number of attributes set on this fileset.
+ +1072 :returns: The number if attributes set on this fileset.
+1073 """
+1074 return len(self._attributes)
+ +1076 def __getitem__(self, key: Type[Attribute]) -> Any:
+1077 """Index access for returning attributes on this fileset.
+ +1079 :param key: The attribute type.
+1080 :returns: The attribute's value.
+1081 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1082 """
+1083 if not issubclass(key, Attribute): 1083 ↛ 1084line 1083 didn't jump to line 1084 because the condition on line 1083 was never true
+1084 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1086 try:
+1087 return self._attributes[key]
+1088 except KeyError:
+1089 return key.resolve(self, key)
+ +1091 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+1092 """
+1093 Index access for adding or setting attributes on this fileset.
+ +1095 :param key: The attribute type.
+1096 :param value: The attributes value.
+1097 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1098 """
+1099 if not issubclass(key, Attribute): 1099 ↛ 1100line 1099 didn't jump to line 1100 because the condition on line 1099 was never true
+1100 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1102 self._attributes[key] = value
+ +1104 def __delitem__(self, key: Type[Attribute]) -> None:
+1105 """
+1106 Index access for deleting attributes on this fileset.
+ +1108 :param key: The attribute type.
+1109 """
+1110 if not issubclass(key, Attribute): 1110 ↛ 1111line 1110 didn't jump to line 1111 because the condition on line 1110 was never true
+1111 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1113 del self._attributes[key]
+ +1115 def __str__(self) -> str:
+1116 """Returns the fileset's name."""
+1117 return self._name
+ + +1120@export
+1121class VHDLLibrary(metaclass=ExtendedType, slots=True):
+1122 """
+1123 A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library.
+ +1125 :arg name: The VHDL libraries' name.
+1126 :arg project: Project the VHDL library is associated with.
+1127 :arg design: Design the VHDL library is associated with.
+1128 :arg vhdlVersion: Default VHDL version for files in this VHDL library, if not specified for the file itself.
+1129 """
+ +1131 _name: str
+1132 _project: Nullable['Project']
+1133 _design: Nullable['Design']
+1134 _files: List[File]
+1135 _vhdlVersion: VHDLVersion
+ +1137 _dependencyNode: Vertex
+ +1139 def __init__(
+1140 self,
+1141 name: str,
+1142 project: Nullable["Project"] = None,
+1143 design: Nullable["Design"] = None,
+1144 vhdlVersion: Nullable[VHDLVersion] = None
+1145 ):
+1146 self._name = name
+1147 if project is not None:
+1148 self._project = project
+1149 self._design = project._defaultDesign if design is None else design
+1150 self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+ +1152 if name in self._design._vhdlLibraries: 1152 ↛ 1153line 1152 didn't jump to line 1153 because the condition on line 1152 was never true
+1153 raise Exception(f"Library '{name}' already in design '{self._design.Name}'.")
+1154 else:
+1155 self._design._vhdlLibraries[name] = self
+ +1157 elif design is not None:
+1158 self._project = design._project
+1159 self._design = design
+1160 self._dependencyNode = Vertex(value=self, graph=design._vhdlLibraryDependencyGraph)
+ +1162 if name in design._vhdlLibraries: 1162 ↛ 1163line 1162 didn't jump to line 1163 because the condition on line 1162 was never true
+1163 raise Exception(f"Library '{name}' already in design '{design.Name}'.")
+1164 else:
+1165 design._vhdlLibraries[name] = self
+ +1167 else:
+1168 self._project = None
+1169 self._design = None
+1170 self._dependencyNode = None
+ +1172 self._files = []
+1173 self._vhdlVersion = vhdlVersion
+ +1175 @property
+1176 def Name(self) -> str:
+1177 return self._name
+ +1179 @property
+1180 def Project(self) -> Nullable['Project']:
+1181 """Property setting or returning the project this VHDL library is used in."""
+1182 return self._project
+ +1184 @Project.setter
+1185 def Project(self, value: 'Project') -> None:
+1186 if not isinstance(value, Project): 1186 ↛ 1187line 1186 didn't jump to line 1187 because the condition on line 1186 was never true
+1187 raise TypeError("Parameter 'value' is not of type 'Project'.")
+ +1189 if value is None: 1189 ↛ 1191line 1189 didn't jump to line 1191 because the condition on line 1189 was never true
+1190 # TODO: unlink VHDLLibrary from project
+1191 self._project = None
+1192 else:
+1193 self._project = value
+1194 if self._design is None: 1194 ↛ exitline 1194 didn't return from function 'Project' because the condition on line 1194 was always true
+1195 self._design = value._defaultDesign
+ +1197 @property
+1198 def Design(self) -> Nullable['Design']:
+1199 """Property setting or returning the design this VHDL library is used in."""
+1200 return self._design
+ +1202 @Design.setter
+1203 def Design(self, value: 'Design') -> None:
+1204 if not isinstance(value, Design):
+1205 raise TypeError("Parameter 'value' is not of type 'Design'.")
+ +1207 if value is None:
+1208 # TODO: unlink VHDLLibrary from design
+1209 self._design = None
+1210 else:
+1211 if self._design is None:
+1212 self._design = value
+1213 self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph)
+1214 elif self._design is not value:
+1215 # TODO: move VHDLLibrary to other design
+1216 # TODO: create new vertex in dependency graph and remove vertex from old graph
+1217 self._design = value
+1218 else:
+1219 pass
+ +1221 if self._project is None:
+1222 self._project = value._project
+1223 elif self._project is not value._project:
+1224 raise Exception("The design's project is not identical to the already assigned project.")
+ +1226 @property
+1227 def Files(self) -> Generator[File, None, None]:
+1228 """Read-only property to return all files in this VHDL library."""
+1229 for file in self._files:
+1230 yield file
+ +1232 @property
+1233 def VHDLVersion(self) -> VHDLVersion:
+1234 """Property setting or returning the VHDL version of this VHDL library."""
+1235 if self._vhdlVersion is not None:
+1236 return self._vhdlVersion
+1237 elif self._design is not None: 1237 ↛ 1240line 1237 didn't jump to line 1240 because the condition on line 1237 was always true
+1238 return self._design.VHDLVersion
+1239 else:
+1240 raise Exception("VHDLVersion is not set on VHDLLibrary nor parent object.")
+ +1242 @VHDLVersion.setter
+1243 def VHDLVersion(self, value: VHDLVersion) -> None:
+1244 self._vhdlVersion = value
+ +1246 def AddDependency(self, library: 'VHDLLibrary') -> None:
+1247 library.parent = self
+ +1249 def AddFile(self, vhdlFile: VHDLSourceFile) -> None:
+1250 if not isinstance(vhdlFile, VHDLSourceFile): 1250 ↛ 1251line 1250 didn't jump to line 1251 because the condition on line 1250 was never true
+1251 ex = TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.")
+1252 if version_info >= (3, 11): # pragma: no cover
+1253 ex.add_note(f"Got type '{getFullyQualifiedName(vhdlFile)}'.")
+1254 raise ex
+ +1256 self._files.append(vhdlFile)
+ +1258 def AddFiles(self, vhdlFiles: Iterable[VHDLSourceFile]) -> None:
+1259 for vhdlFile in vhdlFiles:
+1260 if not isinstance(vhdlFile, VHDLSourceFile):
+1261 raise TypeError(f"Item '{vhdlFile}' in parameter 'vhdlFiles' is not a 'VHDLSourceFile'.")
+ +1263 self._files.append(vhdlFile)
+ +1265 @property
+1266 def FileCount(self) -> int:
+1267 """Returns number of files."""
+1268 return len(self._files)
+ +1270 def __len__(self) -> int:
+1271 """
+1272 Returns number of attributes set on this VHDL library.
+ +1274 :returns: The number if attributes set on this VHDL library.
+1275 """
+1276 return len(self._attributes)
+ +1278 def __getitem__(self, key: Type[Attribute]) -> Any:
+1279 """Index access for returning attributes on this VHDL library.
+ +1281 :param key: The attribute type.
+1282 :returns: The attribute's value.
+1283 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1284 """
+1285 if not issubclass(key, Attribute):
+1286 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1288 try:
+1289 return self._attributes[key]
+1290 except KeyError:
+1291 return key.resolve(self, key)
+ +1293 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+1294 """
+1295 Index access for adding or setting attributes on this VHDL library.
+ +1297 :param key: The attribute type.
+1298 :param value: The attributes value.
+1299 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1300 """
+1301 if not issubclass(key, Attribute):
+1302 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1304 self._attributes[key] = value
+ +1306 def __delitem__(self, key: Type[Attribute]) -> None:
+1307 """
+1308 Index access for deleting attributes on this VHDL library.
+ +1310 :param key: The attribute type.
+1311 """
+1312 if not issubclass(key, Attribute):
+1313 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1315 del self._attributes[key]
+ +1317 def __str__(self) -> str:
+1318 """Returns the VHDL library's name."""
+1319 return self._name
+ + +1322@export
+1323class Design(metaclass=ExtendedType, slots=True):
+1324 """
+1325 A :term:`Design` represents a group of filesets and the source files therein.
+ +1327 Each design contains at least one fileset - the :term:`default fileset`. For
+1328 designs with VHDL source files, a independent `VHDLLibraries` overlay structure
+1329 exists.
+ +1331 :arg name: The design's name.
+1332 :arg topLevel: Name of the design's toplevel.
+1333 :arg directory: Path of this design (absolute or relative to the project).
+1334 :arg project: Project the design is associated with.
+1335 :arg vhdlVersion: Default VHDL version for files in this design, if not specified for the file itself.
+1336 :arg verilogVersion: Default Verilog version for files in this design, if not specified for the file itself.
+1337 :arg svVersion: Default SystemVerilog version for files in this design, if not specified for the file itself.
+1338 :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself.
+1339 """
+ +1341 _name: str
+1342 _topLevel: Nullable[str]
+1343 _project: Nullable['Project']
+1344 _directory: pathlib_Path
+1345 _fileSets: Dict[str, FileSet]
+1346 _defaultFileSet: Nullable[FileSet]
+1347 _attributes: Dict[Type[Attribute], typing_Any]
+ +1349 _vhdlLibraries: Dict[str, VHDLLibrary]
+1350 _vhdlVersion: VHDLVersion
+1351 _verilogVersion: SystemVerilogVersion
+1352 _svVersion: SystemVerilogVersion
+1353 _srdlVersion: SystemRDLVersion
+1354 _externalVHDLLibraries: List
+ +1356 _vhdlLibraryDependencyGraph: Graph
+1357 _fileDependencyGraph: Graph
+ +1359 def __init__(
+1360 self,
+1361 name: str,
+1362 topLevel: Nullable[str] = None,
+1363 directory: pathlib_Path = pathlib_Path("."),
+1364 project: Nullable["Project"] = None,
+1365 vhdlVersion: Nullable[VHDLVersion] = None,
+1366 verilogVersion: Nullable[SystemVerilogVersion] = None,
+1367 svVersion: Nullable[SystemVerilogVersion] = None,
+1368 srdlVersion: Nullable[SystemRDLVersion] = None
+1369 ):
+1370 self._name = name
+1371 self._topLevel = topLevel
+1372 self._project = project
+1373 if project is not None:
+1374 project._designs[name] = self
+1375 self._directory = directory
+1376 self._fileSets = {}
+1377 self._defaultFileSet = FileSet("default", project=project, design=self)
+1378 self._attributes = {}
+1379 self._vhdlLibraries = {}
+1380 self._vhdlVersion = vhdlVersion
+1381 self._verilogVersion = verilogVersion
+1382 self._svVersion = svVersion
+1383 self._srdlVersion = srdlVersion
+1384 self._externalVHDLLibraries = []
+ +1386 self._vhdlLibraryDependencyGraph = Graph()
+1387 self._fileDependencyGraph = Graph()
+ +1389 @property
+1390 def Name(self) -> str:
+1391 """Property setting or returning the design's name."""
+1392 return self._name
+ +1394 @Name.setter
+1395 def Name(self, value: str) -> None:
+1396 self._name = value
+ +1398 @property
+1399 def TopLevel(self) -> str:
+1400 """Property setting or returning the fileset's toplevel."""
+1401 return self._topLevel
+ +1403 @TopLevel.setter
+1404 def TopLevel(self, value: str) -> None:
+1405 self._topLevel = value
+ +1407 @property
+1408 def Project(self) -> Nullable['Project']:
+1409 """Property setting or returning the project this design is used in."""
+1410 return self._project
+ +1412 @Project.setter
+1413 def Project(self, value: 'Project') -> None:
+1414 self._project = value
+ +1416 @property
+1417 def Directory(self) -> pathlib_Path:
+1418 """Property setting or returning the directory this design is located in."""
+1419 return self._directory
+ +1421 @Directory.setter
+1422 def Directory(self, value: pathlib_Path) -> None:
+1423 self._directory = value
+ +1425 @property
+1426 def ResolvedPath(self) -> pathlib_Path:
+1427 """Read-only property returning the resolved path of this fileset."""
+1428 if self._directory.is_absolute(): 1428 ↛ 1429line 1428 didn't jump to line 1429 because the condition on line 1428 was never true
+1429 return self._directory.resolve()
+1430 elif self._project is not None: 1430 ↛ 1440line 1430 didn't jump to line 1440 because the condition on line 1430 was always true
+1431 path = (self._project.ResolvedPath / self._directory).resolve()
+ +1433 if path.is_absolute(): 1433 ↛ 1437line 1433 didn't jump to line 1437 because the condition on line 1433 was always true
+1434 return path
+1435 else:
+1436 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+1437 return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+1438 else:
+1439 # TODO: message and exception type
+1440 raise Exception("")
+ +1442 @property
+1443 def DefaultFileSet(self) -> FileSet:
+1444 """Property setting or returning the default fileset of this design."""
+1445 return self._defaultFileSet
+ +1447 @DefaultFileSet.setter
+1448 def DefaultFileSet(self, value: Union[str, FileSet]) -> None:
+1449 if isinstance(value, str):
+1450 if value not in self._fileSets.keys():
+1451 raise Exception(f"Fileset '{value}' is not in this design.")
+ +1453 self._defaultFileSet = self._fileSets[value]
+1454 elif isinstance(value, FileSet):
+1455 if value not in self.FileSets:
+1456 raise Exception(f"Fileset '{value}' is not associated to this design.")
+ +1458 self._defaultFileSet = value
+1459 else:
+1460 raise ValueError("Unsupported parameter type for 'value'.")
+ +1462 # TODO: return generator with another method
+1463 @property
+1464 def FileSets(self) -> Dict[str, FileSet]:
+1465 """Read-only property returning the dictionary of filesets."""
+1466 return self._fileSets
+ +1468 def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]:
+1469 """
+1470 Method returning the files of this design.
+ +1472 :arg fileType: A filter for file types. Default: ``Any``.
+1473 :arg fileSet: Specifies if all files from all filesets (``fileSet=None``) are files from a single fileset are returned.
+1474 """
+1475 if fileSet is None:
+1476 for fileSet in self._fileSets.values():
+1477 for file in fileSet.Files(fileType):
+1478 yield file
+1479 else:
+1480 if isinstance(fileSet, str): 1480 ↛ 1485line 1480 didn't jump to line 1485 because the condition on line 1480 was always true
+1481 try:
+1482 fileSet = self._fileSets[fileSet]
+1483 except KeyError as ex:
+1484 raise Exception(f"Fileset {fileSet.Name} not bound to design {self.Name}.") from ex
+1485 elif not isinstance(fileSet, FileSet):
+1486 raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.")
+ +1488 for file in fileSet.Files(fileType):
+1489 yield file
+ +1491 def Validate(self) -> None:
+1492 """Validate this design."""
+1493 if self._name is None or self._name == "": 1493 ↛ 1494line 1493 didn't jump to line 1494 because the condition on line 1493 was never true
+1494 raise Exception("Validation: Design has no name.")
+ +1496 if self._directory is None: 1496 ↛ 1497line 1496 didn't jump to line 1497 because the condition on line 1496 was never true
+1497 raise Exception(f"Validation: Design '{self._name}' has no directory.")
+1498 try:
+1499 path = self.ResolvedPath
+1500 except Exception as ex:
+1501 raise Exception(f"Validation: Design '{self._name}' could not compute resolved path.") from ex
+1502 if not path.exists(): 1502 ↛ 1503line 1502 didn't jump to line 1503 because the condition on line 1502 was never true
+1503 raise Exception(f"Validation: Design '{self._name}'s directory '{path}' does not exist.")
+1504 if not path.is_dir(): 1504 ↛ 1505line 1504 didn't jump to line 1505 because the condition on line 1504 was never true
+1505 raise Exception(f"Validation: Design '{self._name}'s directory '{path}' is not a directory.")
+ +1507 if len(self._fileSets) == 0: 1507 ↛ 1508line 1507 didn't jump to line 1508 because the condition on line 1507 was never true
+1508 raise Exception(f"Validation: Design '{self._name}' has no fileset.")
+1509 try:
+1510 if self._defaultFileSet is not self._fileSets[self._defaultFileSet.Name]: 1510 ↛ 1511line 1510 didn't jump to line 1511 because the condition on line 1510 was never true
+1511 raise Exception(f"Validation: Design '{self._name}'s default fileset is the same as listed in filesets.")
+1512 except KeyError as ex:
+1513 raise Exception(f"Validation: Design '{self._name}'s default fileset is not in list of filesets.") from ex
+1514 if self._project is None: 1514 ↛ 1515line 1514 didn't jump to line 1515 because the condition on line 1514 was never true
+1515 raise Exception(f"Validation: Design '{self._path}' has no project.")
+ +1517 for fileSet in self._fileSets.values():
+1518 fileSet.Validate()
+ +1520 @property
+1521 def VHDLLibraries(self) -> Dict[str, VHDLLibrary]:
+1522 return self._vhdlLibraries
+ +1524 @property
+1525 def VHDLVersion(self) -> VHDLVersion:
+1526 if self._vhdlVersion is not None:
+1527 return self._vhdlVersion
+1528 elif self._project is not None: 1528 ↛ 1531line 1528 didn't jump to line 1531 because the condition on line 1528 was always true
+1529 return self._project.VHDLVersion
+1530 else:
+1531 raise Exception("VHDLVersion was neither set locally nor globally.")
+ +1533 @VHDLVersion.setter
+1534 def VHDLVersion(self, value: VHDLVersion) -> None:
+1535 self._vhdlVersion = value
+ +1537 @property
+1538 def VerilogVersion(self) -> SystemVerilogVersion:
+1539 if self._verilogVersion is not None:
+1540 return self._verilogVersion
+1541 elif self._project is not None: 1541 ↛ 1544line 1541 didn't jump to line 1544 because the condition on line 1541 was always true
+1542 return self._project.VerilogVersion
+1543 else:
+1544 raise Exception("VerilogVersion was neither set locally nor globally.")
+ +1546 @VerilogVersion.setter
+1547 def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+1548 self._verilogVersion = value
+ +1550 @property
+1551 def SVVersion(self) -> SystemVerilogVersion:
+1552 if self._svVersion is not None:
+1553 return self._svVersion
+1554 elif self._project is not None: 1554 ↛ 1557line 1554 didn't jump to line 1557 because the condition on line 1554 was always true
+1555 return self._project.SVVersion
+1556 else:
+1557 raise Exception("SVVersion was neither set locally nor globally.")
+ +1559 @SVVersion.setter
+1560 def SVVersion(self, value: SystemVerilogVersion) -> None:
+1561 self._svVersion = value
+ +1563 @property
+1564 def SRDLVersion(self) -> SystemRDLVersion:
+1565 if self._srdlVersion is not None:
+1566 return self._srdlVersion
+1567 elif self._project is not None:
+1568 return self._project.SRDLVersion
+1569 else:
+1570 raise Exception("SRDLVersion was neither set locally nor globally.")
+ +1572 @SRDLVersion.setter
+1573 def SRDLVersion(self, value: SystemRDLVersion) -> None:
+1574 self._srdlVersion = value
+ +1576 @property
+1577 def ExternalVHDLLibraries(self) -> List:
+1578 return self._externalVHDLLibraries
+ +1580 def AddFileSet(self, fileSet: FileSet) -> None:
+1581 if not isinstance(fileSet, FileSet):
+1582 raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.")
+1583 elif fileSet in self._fileSets:
+1584 raise Exception("Design already contains this fileset.")
+1585 elif fileSet.Name in self._fileSets.keys():
+1586 raise Exception(f"Design already contains a fileset named '{fileSet.Name}'.")
+ +1588 self._fileSets[fileSet.Name] = fileSet
+1589 fileSet.Design = self
+1590 fileSet._parent = self
+ +1592 def AddFileSets(self, fileSets: Iterable[FileSet]) -> None:
+1593 for fileSet in fileSets:
+1594 self.AddFileSet(fileSet)
+ +1596 @property
+1597 def FileSetCount(self) -> int:
+1598 """Returns number of file sets excl. sub-filesets."""
+1599 return len(self._fileSets)
+ +1601 @property
+1602 def TotalFileSetCount(self) -> int:
+1603 """Returns number of file sets incl. sub-filesets."""
+1604 fileSetCount = len(self._fileSets)
+1605 for fileSet in self._fileSets.values():
+1606 fileSetCount += fileSet.TotalFileSetCount
+ +1608 return fileSetCount
+ +1610 def AddFile(self, file: File) -> None:
+1611 if file.FileSet is None: 1611 ↛ 1614line 1611 didn't jump to line 1614 because the condition on line 1611 was always true
+1612 self._defaultFileSet.AddFile(file)
+1613 else:
+1614 raise ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}' and can't be assigned via Design to a default fileset.")
+ +1616 def AddFiles(self, files: Iterable[File]) -> None:
+1617 for file in files:
+1618 self.AddFile(file)
+ +1620 def AddVHDLLibrary(self, vhdlLibrary: VHDLLibrary) -> None:
+1621 if vhdlLibrary.Name in self._vhdlLibraries:
+1622 if self._vhdlLibraries[vhdlLibrary.Name] is vhdlLibrary:
+1623 raise Exception(f"The VHDLLibrary '{vhdlLibrary.Name}' was already added to the design.")
+1624 else:
+1625 raise Exception(f"A VHDLLibrary with same name ('{vhdlLibrary.Name}') already exists for this design.")
+ + +1628 def __len__(self) -> int:
+1629 """
+1630 Returns number of attributes set on this design.
+ +1632 :returns: The number if attributes set on this design.
+1633 """
+1634 return len(self._attributes)
+ +1636 def __getitem__(self, key: Type[Attribute]) -> Any:
+1637 """Index access for returning attributes on this design.
+ +1639 :param key: The attribute type.
+1640 :returns: The attribute's value.
+1641 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1642 """
+1643 if not issubclass(key, Attribute): 1643 ↛ 1644line 1643 didn't jump to line 1644 because the condition on line 1643 was never true
+1644 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1646 try:
+1647 return self._attributes[key]
+1648 except KeyError:
+1649 return key.resolve(self, key)
+ +1651 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+1652 """
+1653 Index access for adding or setting attributes on this design.
+ +1655 :param key: The attribute type.
+1656 :param value: The attributes value.
+1657 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1658 """
+1659 if not issubclass(key, Attribute): 1659 ↛ 1660line 1659 didn't jump to line 1660 because the condition on line 1659 was never true
+1660 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1662 self._attributes[key] = value
+ +1664 def __delitem__(self, key: Type[Attribute]) -> None:
+1665 """
+1666 Index access for deleting attributes on this design.
+ +1668 :param key: The attribute type.
+1669 """
+1670 if not issubclass(key, Attribute): 1670 ↛ 1671line 1670 didn't jump to line 1671 because the condition on line 1670 was never true
+1671 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1673 del self._attributes[key]
+ +1675 def __str__(self) -> str:
+1676 return self._name
+ + +1679@export
+1680class Project(metaclass=ExtendedType, slots=True):
+1681 """
+1682 A :term:`Project` represents a group of designs and the source files therein.
+ +1684 :arg name: The project's name.
+1685 :arg rootDirectory: Base-path to the project.
+1686 :arg vhdlVersion: Default VHDL version for files in this project, if not specified for the file itself.
+1687 :arg verilogVersion: Default Verilog version for files in this project, if not specified for the file itself.
+1688 :arg svVersion: Default SystemVerilog version for files in this project, if not specified for the file itself.
+1689 """
+ +1691 _name: str
+1692 _rootDirectory: pathlib_Path
+1693 _designs: Dict[str, Design]
+1694 _defaultDesign: Design
+1695 _attributes: Dict[Type[Attribute], typing_Any]
+ +1697 _vhdlVersion: VHDLVersion
+1698 _verilogVersion: SystemVerilogVersion
+1699 _svVersion: SystemVerilogVersion
+1700 _srdlVersion: SystemRDLVersion
+ +1702 def __init__(
+1703 self,
+1704 name: str,
+1705 rootDirectory: pathlib_Path = pathlib_Path("."),
+1706 vhdlVersion: Nullable[VHDLVersion] = None,
+1707 verilogVersion: Nullable[SystemVerilogVersion] = None,
+1708 svVersion: Nullable[SystemVerilogVersion] = None
+1709 ):
+1710 self._name = name
+1711 self._rootDirectory = rootDirectory
+1712 self._designs = {}
+1713 self._defaultDesign = Design("default", project=self)
+1714 self._attributes = {}
+1715 self._vhdlVersion = vhdlVersion
+1716 self._verilogVersion = verilogVersion
+1717 self._svVersion = svVersion
+ +1719 @property
+1720 def Name(self) -> str:
+1721 """Property setting or returning the project's name."""
+1722 return self._name
+ +1724 @property
+1725 def RootDirectory(self) -> pathlib_Path:
+1726 """Property setting or returning the root directory this project is located in."""
+1727 return self._rootDirectory
+ +1729 @RootDirectory.setter
+1730 def RootDirectory(self, value: pathlib_Path) -> None:
+1731 self._rootDirectory = value
+ +1733 @property
+1734 def ResolvedPath(self) -> pathlib_Path:
+1735 """Read-only property returning the resolved path of this fileset."""
+1736 path = self._rootDirectory.resolve()
+1737 if self._rootDirectory.is_absolute():
+1738 return path
+1739 else:
+1740 # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath
+1741 return pathlib_Path(path_relpath(path, pathlib_Path.cwd()))
+ +1743 # TODO: return generator with another method
+1744 @property
+1745 def Designs(self) -> Dict[str, Design]:
+1746 return self._designs
+ +1748 @property
+1749 def DefaultDesign(self) -> Design:
+1750 return self._defaultDesign
+ +1752 def Validate(self) -> None:
+1753 """Validate this project."""
+1754 if self._name is None or self._name == "": 1754 ↛ 1755line 1754 didn't jump to line 1755 because the condition on line 1754 was never true
+1755 raise Exception("Validation: Project has no name.")
+ +1757 if self._rootDirectory is None: 1757 ↛ 1758line 1757 didn't jump to line 1758 because the condition on line 1757 was never true
+1758 raise Exception(f"Validation: Project '{self._name}' has no root directory.")
+1759 try:
+1760 path = self.ResolvedPath
+1761 except Exception as ex:
+1762 raise Exception(f"Validation: Project '{self._name}' could not compute resolved path.") from ex
+1763 if not path.exists(): 1763 ↛ 1764line 1763 didn't jump to line 1764 because the condition on line 1763 was never true
+1764 raise Exception(f"Validation: Project '{self._name}'s directory '{path}' does not exist.")
+1765 if not path.is_dir(): 1765 ↛ 1766line 1765 didn't jump to line 1766 because the condition on line 1765 was never true
+1766 raise Exception(f"Validation: Project '{self._name}'s directory '{path}' is not a directory.")
+ +1768 if len(self._designs) == 0: 1768 ↛ 1769line 1768 didn't jump to line 1769 because the condition on line 1768 was never true
+1769 raise Exception(f"Validation: Project '{self._name}' has no design.")
+1770 try:
+1771 if self._defaultDesign is not self._designs[self._defaultDesign.Name]: 1771 ↛ 1772line 1771 didn't jump to line 1772 because the condition on line 1771 was never true
+1772 raise Exception(f"Validation: Project '{self._name}'s default design is the same as listed in designs.")
+1773 except KeyError as ex:
+1774 raise Exception(f"Validation: Project '{self._name}'s default design is not in list of designs.") from ex
+ +1776 for design in self._designs.values():
+1777 design.Validate()
+ +1779 @property
+1780 def DesignCount(self) -> int:
+1781 """Returns number of designs."""
+1782 return len(self._designs)
+ +1784 @property
+1785 def VHDLVersion(self) -> VHDLVersion:
+1786 # TODO: check for None and return exception
+1787 return self._vhdlVersion
+ +1789 @VHDLVersion.setter
+1790 def VHDLVersion(self, value: VHDLVersion) -> None:
+1791 self._vhdlVersion = value
+ +1793 @property
+1794 def VerilogVersion(self) -> SystemVerilogVersion:
+1795 # TODO: check for None and return exception
+1796 return self._verilogVersion
+ +1798 @VerilogVersion.setter
+1799 def VerilogVersion(self, value: SystemVerilogVersion) -> None:
+1800 self._verilogVersion = value
+ +1802 @property
+1803 def SVVersion(self) -> SystemVerilogVersion:
+1804 # TODO: check for None and return exception
+1805 return self._svVersion
+ +1807 @SVVersion.setter
+1808 def SVVersion(self, value: SystemVerilogVersion) -> None:
+1809 self._svVersion = value
+ +1811 @property
+1812 def SRDLVersion(self) -> SystemRDLVersion:
+1813 # TODO: check for None and return exception
+1814 return self._srdlVersion
+ +1816 @SRDLVersion.setter
+1817 def SRDLVersion(self, value: SystemRDLVersion) -> None:
+1818 self._srdlVersion = value
+ +1820 def __len__(self) -> int:
+1821 """
+1822 Returns number of attributes set on this project.
+ +1824 :returns: The number if attributes set on this project.
+1825 """
+1826 return len(self._attributes)
+ +1828 def __getitem__(self, key: Type[Attribute]) -> Any:
+1829 """Index access for returning attributes on this project.
+ +1831 :param key: The attribute type.
+1832 :returns: The attribute's value.
+1833 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1834 """
+1835 if not issubclass(key, Attribute): 1835 ↛ 1836line 1835 didn't jump to line 1836 because the condition on line 1835 was never true
+1836 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1838 try:
+1839 return self._attributes[key]
+1840 except KeyError:
+1841 return key.resolve(self, key)
+ +1843 def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None:
+1844 """
+1845 Index access for adding or setting attributes on this project.
+ +1847 :param key: The attribute type.
+1848 :param value: The attributes value.
+1849 :raises TypeError: When parameter 'key' is not a subclass of Attribute.
+1850 """
+1851 if not issubclass(key, Attribute): 1851 ↛ 1852line 1851 didn't jump to line 1852 because the condition on line 1851 was never true
+1852 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1854 self._attributes[key] = value
+ +1856 def __delitem__(self, key: Type[Attribute]) -> None:
+1857 """
+1858 Index access for deleting attributes on this project.
+ +1860 :param key: The attribute type.
+1861 """
+1862 if not issubclass(key, Attribute): 1862 ↛ 1863line 1862 didn't jump to line 1863 because the condition on line 1862 was never true
+1863 raise TypeError("Parameter 'key' is not an 'Attribute'.")
+ +1865 del self._attributes[key]
+ +1867 def __str__(self) -> str:
+1868 return self._name
++ « prev + ^ index + » next + + coverage.py v7.6.4, + created at 2024-11-08 22:18 +0000 +
+ +1# ==================================================================================================================== #
+2# _____ ____ _ _ ____ _ _ __ __ _ _ #
+3# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | #
+4# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | #
+5# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | #
+6# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| #
+7# |_| |___/ |__/ #
+8# ==================================================================================================================== #
+9# Authors: #
+10# Patrick Lehmann #
+11# #
+12# License: #
+13# ==================================================================================================================== #
+14# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany #
+15# #
+16# Licensed under the Apache License, Version 2.0 (the "License"); #
+17# you may not use this file except in compliance with the License. #
+18# You may obtain a copy of the License at #
+19# #
+20# http://www.apache.org/licenses/LICENSE-2.0 #
+21# #
+22# Unless required by applicable law or agreed to in writing, software #
+23# distributed under the License is distributed on an "AS IS" BASIS, #
+24# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+25# See the License for the specific language governing permissions and #
+26# limitations under the License. #
+27# #
+28# SPDX-License-Identifier: Apache-2.0 #
+29# ==================================================================================================================== #
+30#
+31"""Specific file types and attributes for Xilinx Vivado."""
+32from pathlib import Path
+33from typing import Iterable, Optional as Nullable
+34from xml.dom import minidom, Node
+ +36from pyTooling.Decorators import export
+37from pyTooling.MetaClasses import ExtendedType
+38from pyVHDLModel import VHDLVersion
+ +40from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design
+41from pyEDAA.ProjectModel import File as Model_File
+42from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
+43from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
+44from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
+ + +47@export
+48class UsedInAttribute(Attribute):
+49 KEY = "UsedIn"
+50 VALUE_TYPE = Iterable[str]
+ + +53@export
+54class File(Model_File):
+55 pass
+ + +58class VivadoFileMixIn(metaclass=ExtendedType, mixin=True):
+59 def _registerAttributes(self) -> None:
+60 self._attributes[UsedInAttribute] = []
+ + +63@export
+64class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn):
+65 def _registerAttributes(self) -> None:
+66 super()._registerAttributes()
+67 VivadoFileMixIn._registerAttributes(self)
+ + +70@export
+71class VerilogSourceFile(Model_VerilogSourceFile):
+72 def _registerAttributes(self) -> None:
+73 super()._registerAttributes()
+74 VivadoFileMixIn._registerAttributes(self)
+ + +77@export
+78class VHDLSourceFile(Model_VHDLSourceFile):
+79 def _registerAttributes(self) -> None:
+80 super()._registerAttributes()
+81 VivadoFileMixIn._registerAttributes(self)
+ + +84@export
+85class VivadoProjectFile(ProjectFile, XMLContent):
+86 """A Vivado project file (``*.xpr``)."""
+ +88 _xprProject: Project
+ +90 def __init__(
+91 self,
+92 path: Path,
+93 project: Nullable[Project] = None,
+94 design: Nullable[Design] = None,
+95 fileSet: Nullable[FileSet] = None
+96 ) -> None:
+97 super().__init__(path, project, design, fileSet)
+ +99 self._xprProject = None
+ +101 @property
+102 def ProjectModel(self) -> Project:
+103 return self._xprProject
+ +105 def Parse(self) -> None:
+106 if not self._path.exists(): 106 ↛ 107line 106 didn't jump to line 107 because the condition on line 106 was never true
+107 raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.")
+ +109 try:
+110 root = minidom.parse(str(self._path)).documentElement
+111 except Exception as ex:
+112 raise Exception(f"Couldn't open '{self._path!s}'.") from ex
+ +114 self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent)
+115 self._ParseRootElement(root)
+ +117 def _ParseRootElement(self, root) -> None:
+118 for rootNode in root.childNodes: 118 ↛ exitline 118 didn't return from function '_ParseRootElement' because the loop on line 118 didn't complete
+119 if rootNode.nodeName == "FileSets":
+120 self._ParseFileSets(rootNode)
+121 break
+ +123 def _ParseFileSets(self, filesetsNode) -> None:
+124 for fileSetsNode in filesetsNode.childNodes:
+125 if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet":
+126 self._ParseFileSet(fileSetsNode)
+ +128 def _ParseFileSet(self, filesetNode) -> None:
+129 filesetName = filesetNode.getAttribute("Name")
+130 fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign)
+ +132 for fileNode in filesetNode.childNodes:
+133 if fileNode.nodeType == Node.ELEMENT_NODE:
+134 if fileNode.tagName == "File":
+135 self._ParseFile(fileNode, fileset)
+136 elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config":
+137 self._ParseFileSetConfig(fileNode, fileset)
+ +139 def _ParseFile(self, fileNode, fileset) -> None:
+140 croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "")
+141 filePath = Path(croppedPath)
+142 if filePath.suffix in (".vhd", ".vhdl"):
+143 self._ParseVHDLFile(fileNode, filePath, fileset)
+144 elif filePath.suffix == ".xdc": 144 ↛ 146line 144 didn't jump to line 146 because the condition on line 144 was always true
+145 self._ParseXDCFile(fileNode, filePath, fileset)
+146 elif filePath.suffix == ".v":
+147 self._ParseVerilogFile(fileNode, filePath, fileset)
+148 elif filePath.suffix == ".xci":
+149 self._ParseXCIFile(fileNode, filePath, fileset)
+150 else:
+151 self._ParseDefaultFile(fileNode, filePath, fileset)
+ +153 def _ParseVHDLFile(self, fileNode, path, fileset) -> None:
+154 vhdlFile = VHDLSourceFile(path)
+155 fileset.AddFile(vhdlFile)
+156 usedInAttr = vhdlFile[UsedInAttribute]
+ +158 for childNode in fileNode.childNodes:
+159 if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo":
+160 if childNode.getAttribute("SFType") == "VHDL2008":
+161 vhdlFile.VHDLVersion = VHDLVersion.VHDL2008
+162 else:
+163 vhdlFile.VHDLVersion = VHDLVersion.VHDL93
+ +165 for fileAttribute in childNode.childNodes:
+166 if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr":
+167 if fileAttribute.getAttribute("Name") == "Library":
+168 libraryName = fileAttribute.getAttribute("Val")
+169 vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName)
+170 elif fileAttribute.getAttribute("Val") == "UsedIn": 170 ↛ 171line 170 didn't jump to line 171 because the condition on line 170 was never true
+171 usedInAttr.append(fileAttribute.getAttribute("Val"))
+ +173 def _ParseDefaultFile(self, _, path, fileset) -> None:
+174 File(path, fileSet=fileset)
+ +176 def _ParseXDCFile(self, _, path, fileset) -> None:
+177 XDCConstraintFile(path, fileSet=fileset)
+ +179 def _ParseVerilogFile(self, _, path, fileset) -> None:
+180 VerilogSourceFile(path, fileSet=fileset)
+ +182 def _ParseXCIFile(self, _, path, fileset) -> None:
+183 IPCoreInstantiationFile(path, fileSet=fileset)
+ +185 def _ParseFileSetConfig(self, fileNode, fileset) -> None:
+186 for option in fileNode.childNodes:
+187 if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
+188 if option.getAttribute("Name") == "TopModule":
+189 fileset.TopLevel = option.getAttribute("Val")
+ + +192@export
+193class XDCConstraintFile(ConstraintFile, SDCContent):
+194 """A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``)."""
+ + +197@export
+198class IPCoreDescriptionFile(XMLFile):
+199 pass
+ + +202@export
+203class IPCoreInstantiationFile(XMLFile):
+204 """A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``)."""
+
|
+
| + | + |
| + |
| + |
| + | + |
| + | + |
| + |
| + |
| + |
|
+
| + | + |
| + |
| + |
| + | + |
| + | + |
| + | + |
| + | + |
| + |
Introduction
+ +Main Documentation
+ +References
+ +Appendix
+
+
+
An abstract model of HDL design projects and EDA tooling.
+This package provides a unified abstract project model for HDL designs and EDA tools. +Third-party frameworks can derive own classes and implement additional logic to create a concrete project model for +their tools.
+Frameworks consuming this model can build higher level features and services on top of such a model, while supporting +multiple input sources.
+Describing HDL projects for open source simulation and synthesis tools: +GHDL, +Icarus Verilog, +Verilator, +Yosys, +Verilog to Routing (VTR), +nextpnr, +etc.
Managing IP cores and projects with pyIPCMI.
*.xpr and *.pro Files¶Xilinx Vivado’s *.xpr and OSVVM’s *.pro files can now be read.
Filesets can be nested.
The dataset can be validated.
Patrick Lehmann (Maintainer)
Unai Martinez-Corral (Maintainer)
This Python package (source code) is licensed under Apache License 2.0. |br| +The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).
+This document was generated on 08.Nov 2024 - 22:19.
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+| + p | ||
| + |
+ pyEDAA | + |
| + |
+ pyEDAA.ProjectModel | + |
| + |
+ pyEDAA.ProjectModel.Altera | + |
| + |
+ pyEDAA.ProjectModel.Altera.Quartus | + |
| + |
+ pyEDAA.ProjectModel.Attributes | + |
| + |
+ pyEDAA.ProjectModel.GHDL | + |
| + |
+ pyEDAA.ProjectModel.Intel | + |
| + |
+ pyEDAA.ProjectModel.Intel.QuartusPrime | + |
| + |
+ pyEDAA.ProjectModel.MentorGraphics | + |
| + |
+ pyEDAA.ProjectModel.MentorGraphics.ModelSim | + |
| + |
+ pyEDAA.ProjectModel.MentorGraphics.QuestaSim | + |
| + |
+ pyEDAA.ProjectModel.OSVVM | + |
| + |
+ pyEDAA.ProjectModel.Verilog | + |
| + |
+ pyEDAA.ProjectModel.VHDL | + |
| + |
+ pyEDAA.ProjectModel.Xilinx | + |
| + |
+ pyEDAA.ProjectModel.Xilinx.ISE | + |
| + |
+ pyEDAA.ProjectModel.Xilinx.Vivado | + |
Introduction
+ +Main Documentation
+ +References
+ +Appendix
+Reference of all packages and modules:
+
pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.Altera.QuartusQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()pyEDAA.ProjectModel.Attributes
+pyEDAA.ProjectModel.GHDLGHDLWaveformFileGHDLWaveformFile.AnyGHDLWaveformFile.DesignGHDLWaveformFile.FileSetGHDLWaveformFile.FileTypeGHDLWaveformFile.PathGHDLWaveformFile.ProjectGHDLWaveformFile.ResolvedPathGHDLWaveformFile.Validate()GHDLWaveformFile.__delitem__()GHDLWaveformFile.__getitem__()GHDLWaveformFile.__init__()GHDLWaveformFile.__len__()GHDLWaveformFile.__setitem__()GHDLWaveformFile.__str__()pyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.Intel.QuartusPrimeQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()pyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.MentorGraphics.ModelSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.MentorGraphics.QuestaSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.OSVVMOSVVMProjectFileOSVVMProjectFile.__init__()OSVVMProjectFile.AnyOSVVMProjectFile.DesignOSVVMProjectFile.FileSetOSVVMProjectFile.FileTypeOSVVMProjectFile.PathOSVVMProjectFile.ProjectOSVVMProjectFile.ResolvedPathOSVVMProjectFile.Validate()OSVVMProjectFile.__delitem__()OSVVMProjectFile.__getitem__()OSVVMProjectFile.__len__()OSVVMProjectFile.__setitem__()OSVVMProjectFile.__str__()pyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogValueChangeDumpFileValueChangeDumpFile.AnyValueChangeDumpFile.DesignValueChangeDumpFile.FileSetValueChangeDumpFile.FileTypeValueChangeDumpFile.PathValueChangeDumpFile.ProjectValueChangeDumpFile.ResolvedPathValueChangeDumpFile.Validate()ValueChangeDumpFile.__delitem__()ValueChangeDumpFile.__getitem__()ValueChangeDumpFile.__init__()ValueChangeDumpFile.__len__()ValueChangeDumpFile.__setitem__()ValueChangeDumpFile.__str__()pyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.ISEISEProjectFileISEProjectFile.AnyISEProjectFile.DesignISEProjectFile.FileSetISEProjectFile.FileTypeISEProjectFile.PathISEProjectFile.ProjectISEProjectFile.ResolvedPathISEProjectFile.Validate()ISEProjectFile.__delitem__()ISEProjectFile.__getitem__()ISEProjectFile.__init__()ISEProjectFile.__len__()ISEProjectFile.__setitem__()ISEProjectFile.__str__()UCFConstraintFileUCFConstraintFile.AnyUCFConstraintFile.DesignUCFConstraintFile.FileSetUCFConstraintFile.FileTypeUCFConstraintFile.PathUCFConstraintFile.ProjectUCFConstraintFile.ResolvedPathUCFConstraintFile.Validate()UCFConstraintFile.__delitem__()UCFConstraintFile.__getitem__()UCFConstraintFile.__init__()UCFConstraintFile.__len__()UCFConstraintFile.__setitem__()UCFConstraintFile.__str__()pyEDAA.ProjectModel.Xilinx.VivadoUsedInAttributeFile
+ConstraintFileConstraintFile.AnyConstraintFile.DesignConstraintFile.FileSetConstraintFile.FileTypeConstraintFile.PathConstraintFile.ProjectConstraintFile.ResolvedPathConstraintFile.Validate()ConstraintFile.__delitem__()ConstraintFile.__getitem__()ConstraintFile.__init__()ConstraintFile.__len__()ConstraintFile.__setitem__()ConstraintFile.__str__()VerilogSourceFileVerilogSourceFile.AnyVerilogSourceFile.DesignVerilogSourceFile.FileSetVerilogSourceFile.FileTypeVerilogSourceFile.PathVerilogSourceFile.ProjectVerilogSourceFile.ResolvedPathVerilogSourceFile.Validate()VerilogSourceFile.VerilogVersionVerilogSourceFile.__delitem__()VerilogSourceFile.__getitem__()VerilogSourceFile.__init__()VerilogSourceFile.__len__()VerilogSourceFile.__setitem__()VerilogSourceFile.__str__()VHDLSourceFileVHDLSourceFile.AnyVHDLSourceFile.DesignVHDLSourceFile.FileSetVHDLSourceFile.FileTypeVHDLSourceFile.PathVHDLSourceFile.ProjectVHDLSourceFile.ResolvedPathVHDLSourceFile.VHDLLibraryVHDLSourceFile.VHDLVersionVHDLSourceFile.Validate()VHDLSourceFile.__delitem__()VHDLSourceFile.__getitem__()VHDLSourceFile.__init__()VHDLSourceFile.__len__()VHDLSourceFile.__repr__()VHDLSourceFile.__setitem__()VHDLSourceFile.__str__()VivadoProjectFileVivadoProjectFile.__init__()VivadoProjectFile.AnyVivadoProjectFile.DesignVivadoProjectFile.FileSetVivadoProjectFile.FileTypeVivadoProjectFile.PathVivadoProjectFile.ProjectVivadoProjectFile.ResolvedPathVivadoProjectFile.Validate()VivadoProjectFile.__delitem__()VivadoProjectFile.__getitem__()VivadoProjectFile.__len__()VivadoProjectFile.__setitem__()VivadoProjectFile.__str__()XDCConstraintFileXDCConstraintFile.AnyXDCConstraintFile.DesignXDCConstraintFile.FileSetXDCConstraintFile.FileTypeXDCConstraintFile.PathXDCConstraintFile.ProjectXDCConstraintFile.ResolvedPathXDCConstraintFile.Validate()XDCConstraintFile.__delitem__()XDCConstraintFile.__getitem__()XDCConstraintFile.__init__()XDCConstraintFile.__len__()XDCConstraintFile.__setitem__()XDCConstraintFile.__str__()IPCoreDescriptionFileIPCoreDescriptionFile.AnyIPCoreDescriptionFile.DesignIPCoreDescriptionFile.FileSetIPCoreDescriptionFile.FileTypeIPCoreDescriptionFile.PathIPCoreDescriptionFile.ProjectIPCoreDescriptionFile.ResolvedPathIPCoreDescriptionFile.Validate()IPCoreDescriptionFile.__delitem__()IPCoreDescriptionFile.__getitem__()IPCoreDescriptionFile.__init__()IPCoreDescriptionFile.__len__()IPCoreDescriptionFile.__setitem__()IPCoreDescriptionFile.__str__()IPCoreInstantiationFileIPCoreInstantiationFile.AnyIPCoreInstantiationFile.DesignIPCoreInstantiationFile.FileSetIPCoreInstantiationFile.FileTypeIPCoreInstantiationFile.PathIPCoreInstantiationFile.ProjectIPCoreInstantiationFile.ResolvedPathIPCoreInstantiationFile.Validate()IPCoreInstantiationFile.__delitem__()IPCoreInstantiationFile.__getitem__()IPCoreInstantiationFile.__init__()IPCoreInstantiationFile.__len__()IPCoreInstantiationFile.__setitem__()IPCoreInstantiationFile.__str__()AttributeFileTypeFileType.FileTypesFileType.__init__()FileType.__new__()FileType.HasClassAttributesFileType.HasMethodAttributesFileType.__base__FileType.__call__()FileType.__delattr__()FileType.__dir__()FileType.__getattribute__()FileType.__instancecheck__()FileType.__or__()FileType.__prepare__()FileType.__repr__()FileType.__ror__()FileType.__setattr__()FileType.__sizeof__()FileType.__subclasscheck__()FileType.__subclasses__()FileType._checkForAbstractMethods()FileType._iterateBaseClassPaths()FileType._wrapNewMethodIfAbstract()FileType._wrapNewMethodIfSingleton()FileType.mro()File
+HumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFile
+LogFile
+XMLFile
+SourceFileSourceFile.AnySourceFile.DesignSourceFile.FileSetSourceFile.FileTypeSourceFile.PathSourceFile.ProjectSourceFile.ResolvedPathSourceFile.Validate()SourceFile.__delitem__()SourceFile.__getitem__()SourceFile.__init__()SourceFile.__len__()SourceFile.__setitem__()SourceFile.__str__()HDLSourceFileHDLSourceFile.AnyHDLSourceFile.DesignHDLSourceFile.FileSetHDLSourceFile.FileTypeHDLSourceFile.PathHDLSourceFile.ProjectHDLSourceFile.ResolvedPathHDLSourceFile.Validate()HDLSourceFile.__delitem__()HDLSourceFile.__getitem__()HDLSourceFile.__init__()HDLSourceFile.__len__()HDLSourceFile.__setitem__()HDLSourceFile.__str__()RDLSourceFileRDLSourceFile.AnyRDLSourceFile.DesignRDLSourceFile.FileSetRDLSourceFile.FileTypeRDLSourceFile.PathRDLSourceFile.ProjectRDLSourceFile.ResolvedPathRDLSourceFile.Validate()RDLSourceFile.__delitem__()RDLSourceFile.__getitem__()RDLSourceFile.__init__()RDLSourceFile.__len__()RDLSourceFile.__setitem__()RDLSourceFile.__str__()NetlistFileNetlistFile.AnyNetlistFile.DesignNetlistFile.FileSetNetlistFile.FileTypeNetlistFile.PathNetlistFile.ProjectNetlistFile.ResolvedPathNetlistFile.Validate()NetlistFile.__delitem__()NetlistFile.__getitem__()NetlistFile.__init__()NetlistFile.__len__()NetlistFile.__setitem__()NetlistFile.__str__()EDIFNetlistFileEDIFNetlistFile.AnyEDIFNetlistFile.DesignEDIFNetlistFile.FileSetEDIFNetlistFile.FileTypeEDIFNetlistFile.PathEDIFNetlistFile.ProjectEDIFNetlistFile.ResolvedPathEDIFNetlistFile.Validate()EDIFNetlistFile.__delitem__()EDIFNetlistFile.__getitem__()EDIFNetlistFile.__init__()EDIFNetlistFile.__len__()EDIFNetlistFile.__setitem__()EDIFNetlistFile.__str__()TCLSourceFileTCLSourceFile.AnyTCLSourceFile.DesignTCLSourceFile.FileSetTCLSourceFile.FileTypeTCLSourceFile.PathTCLSourceFile.ProjectTCLSourceFile.ResolvedPathTCLSourceFile.Validate()TCLSourceFile.__delitem__()TCLSourceFile.__getitem__()TCLSourceFile.__init__()TCLSourceFile.__len__()TCLSourceFile.__setitem__()TCLSourceFile.__str__()VHDLSourceFileVHDLSourceFile.__init__()VHDLSourceFile.Validate()VHDLSourceFile.VHDLLibraryVHDLSourceFile.VHDLVersionVHDLSourceFile.__repr__()VHDLSourceFile.AnyVHDLSourceFile.DesignVHDLSourceFile.FileSetVHDLSourceFile.FileTypeVHDLSourceFile.PathVHDLSourceFile.ProjectVHDLSourceFile.ResolvedPathVHDLSourceFile.__delitem__()VHDLSourceFile.__getitem__()VHDLSourceFile.__len__()VHDLSourceFile.__setitem__()VHDLSourceFile.__str__()VerilogBaseFileVerilogBaseFile.__init__()VerilogBaseFile.AnyVerilogBaseFile.DesignVerilogBaseFile.FileSetVerilogBaseFile.FileTypeVerilogBaseFile.PathVerilogBaseFile.ProjectVerilogBaseFile.ResolvedPathVerilogBaseFile.Validate()VerilogBaseFile.__delitem__()VerilogBaseFile.__getitem__()VerilogBaseFile.__len__()VerilogBaseFile.__setitem__()VerilogBaseFile.__str__()VerilogSourceFileVerilogSourceFile.AnyVerilogSourceFile.DesignVerilogSourceFile.FileSetVerilogSourceFile.FileTypeVerilogSourceFile.PathVerilogSourceFile.ProjectVerilogSourceFile.ResolvedPathVerilogSourceFile.Validate()VerilogSourceFile.VerilogVersionVerilogSourceFile.__delitem__()VerilogSourceFile.__getitem__()VerilogSourceFile.__init__()VerilogSourceFile.__len__()VerilogSourceFile.__setitem__()VerilogSourceFile.__str__()VerilogHeaderFileVerilogHeaderFile.AnyVerilogHeaderFile.DesignVerilogHeaderFile.FileSetVerilogHeaderFile.FileTypeVerilogHeaderFile.PathVerilogHeaderFile.ProjectVerilogHeaderFile.ResolvedPathVerilogHeaderFile.Validate()VerilogHeaderFile.VerilogVersionVerilogHeaderFile.__delitem__()VerilogHeaderFile.__getitem__()VerilogHeaderFile.__init__()VerilogHeaderFile.__len__()VerilogHeaderFile.__setitem__()VerilogHeaderFile.__str__()SystemVerilogBaseFileSystemVerilogBaseFile.AnySystemVerilogBaseFile.DesignSystemVerilogBaseFile.FileSetSystemVerilogBaseFile.FileTypeSystemVerilogBaseFile.PathSystemVerilogBaseFile.ProjectSystemVerilogBaseFile.ResolvedPathSystemVerilogBaseFile.Validate()SystemVerilogBaseFile.__delitem__()SystemVerilogBaseFile.__getitem__()SystemVerilogBaseFile.__init__()SystemVerilogBaseFile.__len__()SystemVerilogBaseFile.__setitem__()SystemVerilogBaseFile.__str__()SystemVerilogSourceFileSystemVerilogSourceFile.AnySystemVerilogSourceFile.DesignSystemVerilogSourceFile.FileSetSystemVerilogSourceFile.FileTypeSystemVerilogSourceFile.PathSystemVerilogSourceFile.ProjectSystemVerilogSourceFile.ResolvedPathSystemVerilogSourceFile.SVVersionSystemVerilogSourceFile.Validate()SystemVerilogSourceFile.__delitem__()SystemVerilogSourceFile.__getitem__()SystemVerilogSourceFile.__init__()SystemVerilogSourceFile.__len__()SystemVerilogSourceFile.__setitem__()SystemVerilogSourceFile.__str__()SystemVerilogHeaderFileSystemVerilogHeaderFile.AnySystemVerilogHeaderFile.DesignSystemVerilogHeaderFile.FileSetSystemVerilogHeaderFile.FileTypeSystemVerilogHeaderFile.PathSystemVerilogHeaderFile.ProjectSystemVerilogHeaderFile.ResolvedPathSystemVerilogHeaderFile.SVVersionSystemVerilogHeaderFile.Validate()SystemVerilogHeaderFile.__delitem__()SystemVerilogHeaderFile.__getitem__()SystemVerilogHeaderFile.__init__()SystemVerilogHeaderFile.__len__()SystemVerilogHeaderFile.__setitem__()SystemVerilogHeaderFile.__str__()SystemRDLSourceFileSystemRDLSourceFile.__init__()SystemRDLSourceFile.SystemRDLVersionSystemRDLSourceFile.AnySystemRDLSourceFile.DesignSystemRDLSourceFile.FileSetSystemRDLSourceFile.FileTypeSystemRDLSourceFile.PathSystemRDLSourceFile.ProjectSystemRDLSourceFile.ResolvedPathSystemRDLSourceFile.Validate()SystemRDLSourceFile.__delitem__()SystemRDLSourceFile.__getitem__()SystemRDLSourceFile.__len__()SystemRDLSourceFile.__setitem__()SystemRDLSourceFile.__str__()PythonSourceFilePythonSourceFile.AnyPythonSourceFile.DesignPythonSourceFile.FileSetPythonSourceFile.FileTypePythonSourceFile.PathPythonSourceFile.ProjectPythonSourceFile.ResolvedPathPythonSourceFile.Validate()PythonSourceFile.__delitem__()PythonSourceFile.__getitem__()PythonSourceFile.__init__()PythonSourceFile.__len__()PythonSourceFile.__setitem__()PythonSourceFile.__str__()CocotbPythonFileCocotbPythonFile.AnyCocotbPythonFile.DesignCocotbPythonFile.FileSetCocotbPythonFile.FileTypeCocotbPythonFile.PathCocotbPythonFile.ProjectCocotbPythonFile.ResolvedPathCocotbPythonFile.Validate()CocotbPythonFile.__delitem__()CocotbPythonFile.__getitem__()CocotbPythonFile.__init__()CocotbPythonFile.__len__()CocotbPythonFile.__setitem__()CocotbPythonFile.__str__()ConstraintFileConstraintFile.AnyConstraintFile.DesignConstraintFile.FileSetConstraintFile.FileTypeConstraintFile.PathConstraintFile.ProjectConstraintFile.ResolvedPathConstraintFile.Validate()ConstraintFile.__delitem__()ConstraintFile.__getitem__()ConstraintFile.__init__()ConstraintFile.__len__()ConstraintFile.__setitem__()ConstraintFile.__str__()ProjectFileProjectFile.AnyProjectFile.DesignProjectFile.FileSetProjectFile.FileTypeProjectFile.PathProjectFile.ProjectProjectFile.ResolvedPathProjectFile.Validate()ProjectFile.__delitem__()ProjectFile.__getitem__()ProjectFile.__init__()ProjectFile.__len__()ProjectFile.__setitem__()ProjectFile.__str__()CSourceFileCSourceFile.AnyCSourceFile.DesignCSourceFile.FileSetCSourceFile.FileTypeCSourceFile.PathCSourceFile.ProjectCSourceFile.ResolvedPathCSourceFile.Validate()CSourceFile.__delitem__()CSourceFile.__getitem__()CSourceFile.__init__()CSourceFile.__len__()CSourceFile.__setitem__()CSourceFile.__str__()CppSourceFileCppSourceFile.AnyCppSourceFile.DesignCppSourceFile.FileSetCppSourceFile.FileTypeCppSourceFile.PathCppSourceFile.ProjectCppSourceFile.ResolvedPathCppSourceFile.Validate()CppSourceFile.__delitem__()CppSourceFile.__getitem__()CppSourceFile.__init__()CppSourceFile.__len__()CppSourceFile.__setitem__()CppSourceFile.__str__()SettingFileSettingFile.AnySettingFile.DesignSettingFile.FileSetSettingFile.FileTypeSettingFile.PathSettingFile.ProjectSettingFile.ResolvedPathSettingFile.Validate()SettingFile.__delitem__()SettingFile.__getitem__()SettingFile.__init__()SettingFile.__len__()SettingFile.__setitem__()SettingFile.__str__()SimulationAnalysisFileSimulationAnalysisFile.AnySimulationAnalysisFile.DesignSimulationAnalysisFile.FileSetSimulationAnalysisFile.FileTypeSimulationAnalysisFile.PathSimulationAnalysisFile.ProjectSimulationAnalysisFile.ResolvedPathSimulationAnalysisFile.Validate()SimulationAnalysisFile.__delitem__()SimulationAnalysisFile.__getitem__()SimulationAnalysisFile.__init__()SimulationAnalysisFile.__len__()SimulationAnalysisFile.__setitem__()SimulationAnalysisFile.__str__()SimulationElaborationFileSimulationElaborationFile.AnySimulationElaborationFile.DesignSimulationElaborationFile.FileSetSimulationElaborationFile.FileTypeSimulationElaborationFile.PathSimulationElaborationFile.ProjectSimulationElaborationFile.ResolvedPathSimulationElaborationFile.Validate()SimulationElaborationFile.__delitem__()SimulationElaborationFile.__getitem__()SimulationElaborationFile.__init__()SimulationElaborationFile.__len__()SimulationElaborationFile.__setitem__()SimulationElaborationFile.__str__()SimulationStartFileSimulationStartFile.AnySimulationStartFile.DesignSimulationStartFile.FileSetSimulationStartFile.FileTypeSimulationStartFile.PathSimulationStartFile.ProjectSimulationStartFile.ResolvedPathSimulationStartFile.Validate()SimulationStartFile.__delitem__()SimulationStartFile.__getitem__()SimulationStartFile.__init__()SimulationStartFile.__len__()SimulationStartFile.__setitem__()SimulationStartFile.__str__()SimulationRunFileSimulationRunFile.AnySimulationRunFile.DesignSimulationRunFile.FileSetSimulationRunFile.FileTypeSimulationRunFile.PathSimulationRunFile.ProjectSimulationRunFile.ResolvedPathSimulationRunFile.Validate()SimulationRunFile.__delitem__()SimulationRunFile.__getitem__()SimulationRunFile.__init__()SimulationRunFile.__len__()SimulationRunFile.__setitem__()SimulationRunFile.__str__()WaveformConfigFileWaveformConfigFile.AnyWaveformConfigFile.DesignWaveformConfigFile.FileSetWaveformConfigFile.FileTypeWaveformConfigFile.PathWaveformConfigFile.ProjectWaveformConfigFile.ResolvedPathWaveformConfigFile.Validate()WaveformConfigFile.__delitem__()WaveformConfigFile.__getitem__()WaveformConfigFile.__init__()WaveformConfigFile.__len__()WaveformConfigFile.__setitem__()WaveformConfigFile.__str__()WaveformDatabaseFileWaveformDatabaseFile.AnyWaveformDatabaseFile.DesignWaveformDatabaseFile.FileSetWaveformDatabaseFile.FileTypeWaveformDatabaseFile.PathWaveformDatabaseFile.ProjectWaveformDatabaseFile.ResolvedPathWaveformDatabaseFile.Validate()WaveformDatabaseFile.__delitem__()WaveformDatabaseFile.__getitem__()WaveformDatabaseFile.__init__()WaveformDatabaseFile.__len__()WaveformDatabaseFile.__setitem__()WaveformDatabaseFile.__str__()WaveformExchangeFileWaveformExchangeFile.AnyWaveformExchangeFile.DesignWaveformExchangeFile.FileSetWaveformExchangeFile.FileTypeWaveformExchangeFile.PathWaveformExchangeFile.ProjectWaveformExchangeFile.ResolvedPathWaveformExchangeFile.Validate()WaveformExchangeFile.__delitem__()WaveformExchangeFile.__getitem__()WaveformExchangeFile.__init__()WaveformExchangeFile.__len__()WaveformExchangeFile.__setitem__()WaveformExchangeFile.__str__()FileSetFileSet.__init__()FileSet.NameFileSet.TopLevelFileSet.ProjectFileSet.DesignFileSet.DirectoryFileSet.ResolvedPathFileSet.ParentFileSet.FileSetsFileSet.Files()FileSet.AddFileSet()FileSet.AddFileSets()FileSet.FileSetCountFileSet.TotalFileSetCountFileSet.AddFile()FileSet.AddFiles()FileSet.FileCountFileSet.TotalFileCountFileSet.Validate()FileSet.VHDLLibraryFileSet.VHDLVersionFileSet.VerilogVersionFileSet.SVVersionFileSet.__len__()FileSet.__getitem__()FileSet.__setitem__()FileSet.__delitem__()FileSet.__str__()VHDLLibrary
+DesignDesign.__init__()Design.NameDesign.TopLevelDesign.ProjectDesign.DirectoryDesign.ResolvedPathDesign.DefaultFileSetDesign.FileSetsDesign.Files()Design.Validate()Design.FileSetCountDesign.TotalFileSetCountDesign.__len__()Design.__getitem__()Design.__setitem__()Design.__delitem__()Design.__str__()Project
+Introduction
+ +Main Documentation
+ +References
+ +Appendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.Altera.Quartus¶Classes
+QuartusProjectFile:
+A Quartus project file (*.qpf).
SDCConstraintFile:
+A Quartus constraint file (Synopsys Design Constraints; *.sdc).
A Quartus project file (*.qpf).
Inheritance
+ +alias of QuartusProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Quartus constraint file (Synopsys Design Constraints; *.sdc).
Inheritance
+ +alias of SDCConstraintFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.Altera.QuartusQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()pyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.Altera¶Submodules
+pyEDAA.ProjectModel.Altera.QuartusQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.Altera
+pyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModelpyEDAA.ProjectModel.Altera.QuartusIntroduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.Attributes
+pyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.Altera.QuartuspyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.GHDL¶Classes
+GHDLWaveformFile:
+GHDL’s waveform file (*.ghw) supporting VHDL and Verilog simulation results.
GHDL’s waveform file (*.ghw) supporting VHDL and Verilog simulation results.
Inheritance
+ +alias of GHDLWaveformFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLGHDLWaveformFileGHDLWaveformFile.AnyGHDLWaveformFile.DesignGHDLWaveformFile.FileSetGHDLWaveformFile.FileTypeGHDLWaveformFile.PathGHDLWaveformFile.ProjectGHDLWaveformFile.ResolvedPathGHDLWaveformFile.Validate()GHDLWaveformFile.__delitem__()GHDLWaveformFile.__getitem__()GHDLWaveformFile.__init__()GHDLWaveformFile.__len__()GHDLWaveformFile.__setitem__()GHDLWaveformFile.__str__()pyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.Intel.QuartusPrime¶Classes
+QuartusProjectFile:
+A Quartus project file (*.qpf).
SDCConstraintFile:
+A Quartus constraint file (Synopsys Design Constraints; *.sdc).
A Quartus project file (*.qpf).
Inheritance
+ +alias of QuartusProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Quartus constraint file (Synopsys Design Constraints; *.sdc).
Inheritance
+ +alias of SDCConstraintFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.Intel.QuartusPrimeQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()pyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.Intel¶Submodules
+pyEDAA.ProjectModel.Intel.QuartusPrimeQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.Intel
+pyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.Intel.QuartusPrimepyEDAA.ProjectModel.MentorGraphics.ModelSim¶Classes
+ModelSimProjectFile:
+Base-class of all tool-specific project files.
ModelSimINIFile:
+Base-class of all tool-specific setting files.
WaveDoFile:
+Base-class of all tool-specific waveform configuration files.
Inheritance
+ +alias of ModelSimProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of ModelSimINIFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of WaveDoFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.MentorGraphics.ModelSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.MentorGraphics.QuestaSimpyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModel.MentorGraphics.QuestaSim¶Classes
+ModelSimProjectFile:
+Base-class of all tool-specific project files.
ModelSimINIFile:
+Base-class of all tool-specific setting files.
WaveDoFile:
+Base-class of all tool-specific waveform configuration files.
Inheritance
+ +alias of ModelSimProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of ModelSimINIFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of WaveDoFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.MentorGraphics.ModelSimpyEDAA.ProjectModel.MentorGraphics.QuestaSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.MentorGraphics.ModelSimpyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.MentorGraphics¶Submodules
+pyEDAA.ProjectModel.MentorGraphics.ModelSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.MentorGraphics.QuestaSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphics
+pyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.Intel.QuartusPrimepyEDAA.ProjectModel.MentorGraphics.ModelSimpyEDAA.ProjectModel.OSVVM¶Classes
+OSVVMProjectFile:
+An OSVVM project file (*.pro).
An OSVVM project file (*.pro).
Inheritance
+ +alias of OSVVMProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMOSVVMProjectFileOSVVMProjectFile.__init__()OSVVMProjectFile.AnyOSVVMProjectFile.DesignOSVVMProjectFile.FileSetOSVVMProjectFile.FileTypeOSVVMProjectFile.PathOSVVMProjectFile.ProjectOSVVMProjectFile.ResolvedPathOSVVMProjectFile.Validate()OSVVMProjectFile.__delitem__()OSVVMProjectFile.__getitem__()OSVVMProjectFile.__len__()OSVVMProjectFile.__setitem__()OSVVMProjectFile.__str__()pyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.MentorGraphics.QuestaSimpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VHDL¶Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.Verilog¶Classes
+ValueChangeDumpFile:
+Verilog’s waveform file (*.vcd) for exchanging value changes as defined by IEEE Std. 1364.
Verilog’s waveform file (*.vcd) for exchanging value changes as defined by IEEE Std. 1364.
Inheritance
+ +alias of ValueChangeDumpFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogValueChangeDumpFileValueChangeDumpFile.AnyValueChangeDumpFile.DesignValueChangeDumpFile.FileSetValueChangeDumpFile.FileTypeValueChangeDumpFile.PathValueChangeDumpFile.ProjectValueChangeDumpFile.ResolvedPathValueChangeDumpFile.Validate()ValueChangeDumpFile.__delitem__()ValueChangeDumpFile.__getitem__()ValueChangeDumpFile.__init__()ValueChangeDumpFile.__len__()ValueChangeDumpFile.__setitem__()ValueChangeDumpFile.__str__()pyEDAA.ProjectModel.XilinxAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.ISE¶Classes
+ISEProjectFile:
+Base-class of all tool-specific project files.
UCFConstraintFile:
+Base-class of all constraint files.
Inheritance
+ +alias of ISEProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of UCFConstraintFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.ISEISEProjectFileISEProjectFile.AnyISEProjectFile.DesignISEProjectFile.FileSetISEProjectFile.FileTypeISEProjectFile.PathISEProjectFile.ProjectISEProjectFile.ResolvedPathISEProjectFile.Validate()ISEProjectFile.__delitem__()ISEProjectFile.__getitem__()ISEProjectFile.__init__()ISEProjectFile.__len__()ISEProjectFile.__setitem__()ISEProjectFile.__str__()UCFConstraintFileUCFConstraintFile.AnyUCFConstraintFile.DesignUCFConstraintFile.FileSetUCFConstraintFile.FileTypeUCFConstraintFile.PathUCFConstraintFile.ProjectUCFConstraintFile.ResolvedPathUCFConstraintFile.Validate()UCFConstraintFile.__delitem__()UCFConstraintFile.__getitem__()UCFConstraintFile.__init__()UCFConstraintFile.__len__()UCFConstraintFile.__setitem__()UCFConstraintFile.__str__()pyEDAA.ProjectModel.Xilinx.VivadoAttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.VivadopyEDAA.ProjectModel.Xilinx.Vivado¶Classes
+UsedInAttribute:
+Undocumented.
File:
+A File represents a file in a design. This base-class is used
ConstraintFile:
+Base-class of all constraint files.
VerilogSourceFile:
+A Verilog source file (of any language version).
VHDLSourceFile:
+A VHDL source file (of any language version).
VivadoProjectFile:
+A Vivado project file (*.xpr).
XDCConstraintFile:
+A Vivado constraint file (Xilinx Design Constraints; *.xdc).
IPCoreDescriptionFile:
+An XML file (*.xml).
IPCoreInstantiationFile:
+A Vivado IP core instantiation file (Xilinx IPCore Instance; *.xci).
Inheritance
+ +Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Returns number of attributes set on this file.
+The number if attributes set on this file.
+Inheritance
+ +alias of ConstraintFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of VerilogSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Property setting or returning the Verilog version this Verilog source file is used in.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +path (Path)
vhdlLibrary (str | VHDLLibrary)
vhdlVersion (VHDLVersion | None)
project (Project | None)
design (Design | None)
fileSet (FileSet | None)
alias of VHDLSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Property setting or returning the VHDL library this VHDL source file is used in.
+Property setting or returning the VHDL version this VHDL source file is used in.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +path (Path)
vhdlLibrary (str | VHDLLibrary)
vhdlVersion (VHDLVersion | None)
project (Project | None)
design (Design | None)
fileSet (FileSet | None)
Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Vivado project file (*.xpr).
Inheritance
+ +alias of VivadoProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Vivado constraint file (Xilinx Design Constraints; *.xdc).
Inheritance
+ +alias of XDCConstraintFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of IPCoreDescriptionFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Vivado IP core instantiation file (Xilinx IPCore Instance; *.xci).
Inheritance
+ +alias of IPCoreInstantiationFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.ISEpyEDAA.ProjectModel.Xilinx.VivadoUsedInAttributeFile
+ConstraintFileConstraintFile.AnyConstraintFile.DesignConstraintFile.FileSetConstraintFile.FileTypeConstraintFile.PathConstraintFile.ProjectConstraintFile.ResolvedPathConstraintFile.Validate()ConstraintFile.__delitem__()ConstraintFile.__getitem__()ConstraintFile.__init__()ConstraintFile.__len__()ConstraintFile.__setitem__()ConstraintFile.__str__()VerilogSourceFileVerilogSourceFile.AnyVerilogSourceFile.DesignVerilogSourceFile.FileSetVerilogSourceFile.FileTypeVerilogSourceFile.PathVerilogSourceFile.ProjectVerilogSourceFile.ResolvedPathVerilogSourceFile.Validate()VerilogSourceFile.VerilogVersionVerilogSourceFile.__delitem__()VerilogSourceFile.__getitem__()VerilogSourceFile.__init__()VerilogSourceFile.__len__()VerilogSourceFile.__setitem__()VerilogSourceFile.__str__()VHDLSourceFileVHDLSourceFile.AnyVHDLSourceFile.DesignVHDLSourceFile.FileSetVHDLSourceFile.FileTypeVHDLSourceFile.PathVHDLSourceFile.ProjectVHDLSourceFile.ResolvedPathVHDLSourceFile.VHDLLibraryVHDLSourceFile.VHDLVersionVHDLSourceFile.Validate()VHDLSourceFile.__delitem__()VHDLSourceFile.__getitem__()VHDLSourceFile.__init__()VHDLSourceFile.__len__()VHDLSourceFile.__repr__()VHDLSourceFile.__setitem__()VHDLSourceFile.__str__()VivadoProjectFileVivadoProjectFile.__init__()VivadoProjectFile.AnyVivadoProjectFile.DesignVivadoProjectFile.FileSetVivadoProjectFile.FileTypeVivadoProjectFile.PathVivadoProjectFile.ProjectVivadoProjectFile.ResolvedPathVivadoProjectFile.Validate()VivadoProjectFile.__delitem__()VivadoProjectFile.__getitem__()VivadoProjectFile.__len__()VivadoProjectFile.__setitem__()VivadoProjectFile.__str__()XDCConstraintFileXDCConstraintFile.AnyXDCConstraintFile.DesignXDCConstraintFile.FileSetXDCConstraintFile.FileTypeXDCConstraintFile.PathXDCConstraintFile.ProjectXDCConstraintFile.ResolvedPathXDCConstraintFile.Validate()XDCConstraintFile.__delitem__()XDCConstraintFile.__getitem__()XDCConstraintFile.__init__()XDCConstraintFile.__len__()XDCConstraintFile.__setitem__()XDCConstraintFile.__str__()IPCoreDescriptionFileIPCoreDescriptionFile.AnyIPCoreDescriptionFile.DesignIPCoreDescriptionFile.FileSetIPCoreDescriptionFile.FileTypeIPCoreDescriptionFile.PathIPCoreDescriptionFile.ProjectIPCoreDescriptionFile.ResolvedPathIPCoreDescriptionFile.Validate()IPCoreDescriptionFile.__delitem__()IPCoreDescriptionFile.__getitem__()IPCoreDescriptionFile.__init__()IPCoreDescriptionFile.__len__()IPCoreDescriptionFile.__setitem__()IPCoreDescriptionFile.__str__()IPCoreInstantiationFileIPCoreInstantiationFile.AnyIPCoreInstantiationFile.DesignIPCoreInstantiationFile.FileSetIPCoreInstantiationFile.FileTypeIPCoreInstantiationFile.PathIPCoreInstantiationFile.ProjectIPCoreInstantiationFile.ResolvedPathIPCoreInstantiationFile.Validate()IPCoreInstantiationFile.__delitem__()IPCoreInstantiationFile.__getitem__()IPCoreInstantiationFile.__init__()IPCoreInstantiationFile.__len__()IPCoreInstantiationFile.__setitem__()IPCoreInstantiationFile.__str__()AttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.ISEpyEDAA.ProjectModel.Xilinx¶Submodules
+pyEDAA.ProjectModel.Xilinx.ISEISEProjectFileISEProjectFile.AnyISEProjectFile.DesignISEProjectFile.FileSetISEProjectFile.FileTypeISEProjectFile.PathISEProjectFile.ProjectISEProjectFile.ResolvedPathISEProjectFile.Validate()ISEProjectFile.__delitem__()ISEProjectFile.__getitem__()ISEProjectFile.__init__()ISEProjectFile.__len__()ISEProjectFile.__setitem__()ISEProjectFile.__str__()UCFConstraintFileUCFConstraintFile.AnyUCFConstraintFile.DesignUCFConstraintFile.FileSetUCFConstraintFile.FileTypeUCFConstraintFile.PathUCFConstraintFile.ProjectUCFConstraintFile.ResolvedPathUCFConstraintFile.Validate()UCFConstraintFile.__delitem__()UCFConstraintFile.__getitem__()UCFConstraintFile.__init__()UCFConstraintFile.__len__()UCFConstraintFile.__setitem__()UCFConstraintFile.__str__()pyEDAA.ProjectModel.Xilinx.VivadoUsedInAttributeFile
+ConstraintFileConstraintFile.AnyConstraintFile.DesignConstraintFile.FileSetConstraintFile.FileTypeConstraintFile.PathConstraintFile.ProjectConstraintFile.ResolvedPathConstraintFile.Validate()ConstraintFile.__delitem__()ConstraintFile.__getitem__()ConstraintFile.__init__()ConstraintFile.__len__()ConstraintFile.__setitem__()ConstraintFile.__str__()VerilogSourceFileVerilogSourceFile.AnyVerilogSourceFile.DesignVerilogSourceFile.FileSetVerilogSourceFile.FileTypeVerilogSourceFile.PathVerilogSourceFile.ProjectVerilogSourceFile.ResolvedPathVerilogSourceFile.Validate()VerilogSourceFile.VerilogVersionVerilogSourceFile.__delitem__()VerilogSourceFile.__getitem__()VerilogSourceFile.__init__()VerilogSourceFile.__len__()VerilogSourceFile.__setitem__()VerilogSourceFile.__str__()VHDLSourceFileVHDLSourceFile.AnyVHDLSourceFile.DesignVHDLSourceFile.FileSetVHDLSourceFile.FileTypeVHDLSourceFile.PathVHDLSourceFile.ProjectVHDLSourceFile.ResolvedPathVHDLSourceFile.VHDLLibraryVHDLSourceFile.VHDLVersionVHDLSourceFile.Validate()VHDLSourceFile.__delitem__()VHDLSourceFile.__getitem__()VHDLSourceFile.__init__()VHDLSourceFile.__len__()VHDLSourceFile.__repr__()VHDLSourceFile.__setitem__()VHDLSourceFile.__str__()VivadoProjectFileVivadoProjectFile.__init__()VivadoProjectFile.AnyVivadoProjectFile.DesignVivadoProjectFile.FileSetVivadoProjectFile.FileTypeVivadoProjectFile.PathVivadoProjectFile.ProjectVivadoProjectFile.ResolvedPathVivadoProjectFile.Validate()VivadoProjectFile.__delitem__()VivadoProjectFile.__getitem__()VivadoProjectFile.__len__()VivadoProjectFile.__setitem__()VivadoProjectFile.__str__()XDCConstraintFileXDCConstraintFile.AnyXDCConstraintFile.DesignXDCConstraintFile.FileSetXDCConstraintFile.FileTypeXDCConstraintFile.PathXDCConstraintFile.ProjectXDCConstraintFile.ResolvedPathXDCConstraintFile.Validate()XDCConstraintFile.__delitem__()XDCConstraintFile.__getitem__()XDCConstraintFile.__init__()XDCConstraintFile.__len__()XDCConstraintFile.__setitem__()XDCConstraintFile.__str__()IPCoreDescriptionFileIPCoreDescriptionFile.AnyIPCoreDescriptionFile.DesignIPCoreDescriptionFile.FileSetIPCoreDescriptionFile.FileTypeIPCoreDescriptionFile.PathIPCoreDescriptionFile.ProjectIPCoreDescriptionFile.ResolvedPathIPCoreDescriptionFile.Validate()IPCoreDescriptionFile.__delitem__()IPCoreDescriptionFile.__getitem__()IPCoreDescriptionFile.__init__()IPCoreDescriptionFile.__len__()IPCoreDescriptionFile.__setitem__()IPCoreDescriptionFile.__str__()IPCoreInstantiationFileIPCoreInstantiationFile.AnyIPCoreInstantiationFile.DesignIPCoreInstantiationFile.FileSetIPCoreInstantiationFile.FileTypeIPCoreInstantiationFile.PathIPCoreInstantiationFile.ProjectIPCoreInstantiationFile.ResolvedPathIPCoreInstantiationFile.Validate()IPCoreInstantiationFile.__delitem__()IPCoreInstantiationFile.__getitem__()IPCoreInstantiationFile.__init__()IPCoreInstantiationFile.__len__()IPCoreInstantiationFile.__setitem__()IPCoreInstantiationFile.__str__()Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.Xilinx
+AttributeFileTypeFileHumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFileLogFileXMLFileSourceFileHDLSourceFileRDLSourceFileNetlistFileEDIFNetlistFileTCLSourceFileVHDLSourceFileVerilogBaseFileVerilogSourceFileVerilogHeaderFileSystemVerilogBaseFileSystemVerilogSourceFileSystemVerilogHeaderFileSystemRDLSourceFilePythonSourceFileCocotbPythonFileConstraintFileProjectFileCSourceFileCppSourceFileSettingFileSimulationAnalysisFileSimulationElaborationFileSimulationStartFileSimulationRunFileWaveformConfigFileWaveformDatabaseFileWaveformExchangeFileFileSetVHDLLibraryDesignProjectAppendix
+pyEDAA.ProjectModelpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.Xilinx.ISEpyEDAA.ProjectModel¶Submodules
+pyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.Altera.QuartusQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()pyEDAA.ProjectModel.Attributes
+pyEDAA.ProjectModel.GHDLGHDLWaveformFileGHDLWaveformFile.AnyGHDLWaveformFile.DesignGHDLWaveformFile.FileSetGHDLWaveformFile.FileTypeGHDLWaveformFile.PathGHDLWaveformFile.ProjectGHDLWaveformFile.ResolvedPathGHDLWaveformFile.Validate()GHDLWaveformFile.__delitem__()GHDLWaveformFile.__getitem__()GHDLWaveformFile.__init__()GHDLWaveformFile.__len__()GHDLWaveformFile.__setitem__()GHDLWaveformFile.__str__()pyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.Intel.QuartusPrimeQuartusProjectFileQuartusProjectFile.AnyQuartusProjectFile.DesignQuartusProjectFile.FileSetQuartusProjectFile.FileTypeQuartusProjectFile.PathQuartusProjectFile.ProjectQuartusProjectFile.ResolvedPathQuartusProjectFile.Validate()QuartusProjectFile.__delitem__()QuartusProjectFile.__getitem__()QuartusProjectFile.__init__()QuartusProjectFile.__len__()QuartusProjectFile.__setitem__()QuartusProjectFile.__str__()SDCConstraintFileSDCConstraintFile.AnySDCConstraintFile.DesignSDCConstraintFile.FileSetSDCConstraintFile.FileTypeSDCConstraintFile.PathSDCConstraintFile.ProjectSDCConstraintFile.ResolvedPathSDCConstraintFile.Validate()SDCConstraintFile.__delitem__()SDCConstraintFile.__getitem__()SDCConstraintFile.__init__()SDCConstraintFile.__len__()SDCConstraintFile.__setitem__()SDCConstraintFile.__str__()pyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.MentorGraphics.ModelSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.MentorGraphics.QuestaSimModelSimProjectFileModelSimProjectFile.AnyModelSimProjectFile.DesignModelSimProjectFile.FileSetModelSimProjectFile.FileTypeModelSimProjectFile.PathModelSimProjectFile.ProjectModelSimProjectFile.ResolvedPathModelSimProjectFile.Validate()ModelSimProjectFile.__delitem__()ModelSimProjectFile.__getitem__()ModelSimProjectFile.__init__()ModelSimProjectFile.__len__()ModelSimProjectFile.__setitem__()ModelSimProjectFile.__str__()ModelSimINIFileModelSimINIFile.AnyModelSimINIFile.DesignModelSimINIFile.FileSetModelSimINIFile.FileTypeModelSimINIFile.PathModelSimINIFile.ProjectModelSimINIFile.ResolvedPathModelSimINIFile.Validate()ModelSimINIFile.__delitem__()ModelSimINIFile.__getitem__()ModelSimINIFile.__init__()ModelSimINIFile.__len__()ModelSimINIFile.__setitem__()ModelSimINIFile.__str__()WaveDoFileWaveDoFile.AnyWaveDoFile.DesignWaveDoFile.FileSetWaveDoFile.FileTypeWaveDoFile.PathWaveDoFile.ProjectWaveDoFile.ResolvedPathWaveDoFile.Validate()WaveDoFile.__delitem__()WaveDoFile.__getitem__()WaveDoFile.__init__()WaveDoFile.__len__()WaveDoFile.__setitem__()WaveDoFile.__str__()pyEDAA.ProjectModel.OSVVMOSVVMProjectFileOSVVMProjectFile.__init__()OSVVMProjectFile.AnyOSVVMProjectFile.DesignOSVVMProjectFile.FileSetOSVVMProjectFile.FileTypeOSVVMProjectFile.PathOSVVMProjectFile.ProjectOSVVMProjectFile.ResolvedPathOSVVMProjectFile.Validate()OSVVMProjectFile.__delitem__()OSVVMProjectFile.__getitem__()OSVVMProjectFile.__len__()OSVVMProjectFile.__setitem__()OSVVMProjectFile.__str__()pyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogValueChangeDumpFileValueChangeDumpFile.AnyValueChangeDumpFile.DesignValueChangeDumpFile.FileSetValueChangeDumpFile.FileTypeValueChangeDumpFile.PathValueChangeDumpFile.ProjectValueChangeDumpFile.ResolvedPathValueChangeDumpFile.Validate()ValueChangeDumpFile.__delitem__()ValueChangeDumpFile.__getitem__()ValueChangeDumpFile.__init__()ValueChangeDumpFile.__len__()ValueChangeDumpFile.__setitem__()ValueChangeDumpFile.__str__()pyEDAA.ProjectModel.XilinxpyEDAA.ProjectModel.Xilinx.ISEISEProjectFileISEProjectFile.AnyISEProjectFile.DesignISEProjectFile.FileSetISEProjectFile.FileTypeISEProjectFile.PathISEProjectFile.ProjectISEProjectFile.ResolvedPathISEProjectFile.Validate()ISEProjectFile.__delitem__()ISEProjectFile.__getitem__()ISEProjectFile.__init__()ISEProjectFile.__len__()ISEProjectFile.__setitem__()ISEProjectFile.__str__()UCFConstraintFileUCFConstraintFile.AnyUCFConstraintFile.DesignUCFConstraintFile.FileSetUCFConstraintFile.FileTypeUCFConstraintFile.PathUCFConstraintFile.ProjectUCFConstraintFile.ResolvedPathUCFConstraintFile.Validate()UCFConstraintFile.__delitem__()UCFConstraintFile.__getitem__()UCFConstraintFile.__init__()UCFConstraintFile.__len__()UCFConstraintFile.__setitem__()UCFConstraintFile.__str__()pyEDAA.ProjectModel.Xilinx.VivadoUsedInAttributeFile
+ConstraintFileConstraintFile.AnyConstraintFile.DesignConstraintFile.FileSetConstraintFile.FileTypeConstraintFile.PathConstraintFile.ProjectConstraintFile.ResolvedPathConstraintFile.Validate()ConstraintFile.__delitem__()ConstraintFile.__getitem__()ConstraintFile.__init__()ConstraintFile.__len__()ConstraintFile.__setitem__()ConstraintFile.__str__()VerilogSourceFileVerilogSourceFile.AnyVerilogSourceFile.DesignVerilogSourceFile.FileSetVerilogSourceFile.FileTypeVerilogSourceFile.PathVerilogSourceFile.ProjectVerilogSourceFile.ResolvedPathVerilogSourceFile.Validate()VerilogSourceFile.VerilogVersionVerilogSourceFile.__delitem__()VerilogSourceFile.__getitem__()VerilogSourceFile.__init__()VerilogSourceFile.__len__()VerilogSourceFile.__setitem__()VerilogSourceFile.__str__()VHDLSourceFileVHDLSourceFile.AnyVHDLSourceFile.DesignVHDLSourceFile.FileSetVHDLSourceFile.FileTypeVHDLSourceFile.PathVHDLSourceFile.ProjectVHDLSourceFile.ResolvedPathVHDLSourceFile.VHDLLibraryVHDLSourceFile.VHDLVersionVHDLSourceFile.Validate()VHDLSourceFile.__delitem__()VHDLSourceFile.__getitem__()VHDLSourceFile.__init__()VHDLSourceFile.__len__()VHDLSourceFile.__repr__()VHDLSourceFile.__setitem__()VHDLSourceFile.__str__()VivadoProjectFileVivadoProjectFile.__init__()VivadoProjectFile.AnyVivadoProjectFile.DesignVivadoProjectFile.FileSetVivadoProjectFile.FileTypeVivadoProjectFile.PathVivadoProjectFile.ProjectVivadoProjectFile.ResolvedPathVivadoProjectFile.Validate()VivadoProjectFile.__delitem__()VivadoProjectFile.__getitem__()VivadoProjectFile.__len__()VivadoProjectFile.__setitem__()VivadoProjectFile.__str__()XDCConstraintFileXDCConstraintFile.AnyXDCConstraintFile.DesignXDCConstraintFile.FileSetXDCConstraintFile.FileTypeXDCConstraintFile.PathXDCConstraintFile.ProjectXDCConstraintFile.ResolvedPathXDCConstraintFile.Validate()XDCConstraintFile.__delitem__()XDCConstraintFile.__getitem__()XDCConstraintFile.__init__()XDCConstraintFile.__len__()XDCConstraintFile.__setitem__()XDCConstraintFile.__str__()IPCoreDescriptionFileIPCoreDescriptionFile.AnyIPCoreDescriptionFile.DesignIPCoreDescriptionFile.FileSetIPCoreDescriptionFile.FileTypeIPCoreDescriptionFile.PathIPCoreDescriptionFile.ProjectIPCoreDescriptionFile.ResolvedPathIPCoreDescriptionFile.Validate()IPCoreDescriptionFile.__delitem__()IPCoreDescriptionFile.__getitem__()IPCoreDescriptionFile.__init__()IPCoreDescriptionFile.__len__()IPCoreDescriptionFile.__setitem__()IPCoreDescriptionFile.__str__()IPCoreInstantiationFileIPCoreInstantiationFile.AnyIPCoreInstantiationFile.DesignIPCoreInstantiationFile.FileSetIPCoreInstantiationFile.FileTypeIPCoreInstantiationFile.PathIPCoreInstantiationFile.ProjectIPCoreInstantiationFile.ResolvedPathIPCoreInstantiationFile.Validate()IPCoreInstantiationFile.__delitem__()IPCoreInstantiationFile.__getitem__()IPCoreInstantiationFile.__init__()IPCoreInstantiationFile.__len__()IPCoreInstantiationFile.__setitem__()IPCoreInstantiationFile.__str__()Classes
+Attribute:
+Undocumented.
FileType:
+A meta-class to construct FileType classes.
File:
+A File represents a file in a design. This base-class is used
HumanReadableContent:
+A file type representing human-readable contents.
XMLContent:
+A file type representing XML contents.
YAMLContent:
+A file type representing YAML contents.
JSONContent:
+A file type representing JSON contents.
INIContent:
+A file type representing INI contents.
TOMLContent:
+A file type representing TOML contents.
TCLContent:
+A file type representing content in TCL code.
SDCContent:
+A file type representing contents as Synopsys Design Constraints (SDC).
PythonContent:
+A file type representing contents as Python source code.
TextFile:
+A text file (*.txt).
LogFile:
+A log file (*.log).
XMLFile:
+An XML file (*.xml).
SourceFile:
+Base-class of all source files.
HDLSourceFile:
+Base-class of all HDL source files.
RDLSourceFile:
+Base-class of all RDL source files.
NetlistFile:
+Base-class of all netlist source files.
EDIFNetlistFile:
+Netlist file in EDIF (Electronic Design Interchange Format).
TCLSourceFile:
+A TCL source file.
VHDLSourceFile:
+A VHDL source file (of any language version).
VerilogBaseFile:
+Base-class of all HDL source files.
VerilogSourceFile:
+A Verilog source file (of any language version).
VerilogHeaderFile:
+A Verilog header file (of any language version).
SystemVerilogBaseFile:
+Base-class of all HDL source files.
SystemVerilogSourceFile:
+A SystemVerilog source file (of any language version).
SystemVerilogHeaderFile:
+A SystemVerilog header file (of any language version).
SystemRDLSourceFile:
+A SystemRDL source file (of any language version).
PythonSourceFile:
+A Python source file.
CocotbPythonFile:
+A Python source file used by Cocotb.
ConstraintFile:
+Base-class of all constraint files.
ProjectFile:
+Base-class of all tool-specific project files.
CSourceFile:
+Base-class of all ANSI-C source files.
CppSourceFile:
+Base-class of all ANSI-C++ source files.
SettingFile:
+Base-class of all tool-specific setting files.
SimulationAnalysisFile:
+Base-class of all tool-specific analysis files.
SimulationElaborationFile:
+Base-class of all tool-specific elaboration files.
SimulationStartFile:
+Base-class of all tool-specific simulation start-up files.
SimulationRunFile:
+Base-class of all tool-specific simulation run (execution) files.
WaveformConfigFile:
+Base-class of all tool-specific waveform configuration files.
WaveformDatabaseFile:
+Base-class of all tool-specific waveform database files.
WaveformExchangeFile:
+Base-class of all tool-independent waveform exchange files.
FileSet:
+A FileSet represents a group of files. Filesets can have sub-filesets.
VHDLLibrary:
+A VHDLLibrary represents a group of VHDL source files compiled into the same VHDL library.
Design:
+A Design represents a group of filesets and the source files therein.
Project:
+A Project represents a group of designs and the source files therein.
A meta-class to construct FileType classes.
+Modifications done by this meta-class:
+* Register all classes of type FileType or derived variants in a class field FileType.FileTypes in this meta-class.
Inheritance
+ +classMembers (Dict)
+Dict[str, FileType] = {'CSourceFile': <class 'pyEDAA.ProjectModel.CSourceFile'>, 'CocotbPythonFile': <class 'pyEDAA.ProjectModel.CocotbPythonFile'>, 'ConstraintFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.ConstraintFile'>, 'CppSourceFile': <class 'pyEDAA.ProjectModel.CppSourceFile'>, 'EDIFNetlistFile': <class 'pyEDAA.ProjectModel.EDIFNetlistFile'>, 'File': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.File'>, 'GHDLWaveformFile': <class 'pyEDAA.ProjectModel.GHDL.GHDLWaveformFile'>, 'HDLSourceFile': <class 'pyEDAA.ProjectModel.HDLSourceFile'>, 'IPCoreDescriptionFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.IPCoreDescriptionFile'>, 'IPCoreInstantiationFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.IPCoreInstantiationFile'>, 'ISEProjectFile': <class 'pyEDAA.ProjectModel.Xilinx.ISE.ISEProjectFile'>, 'LogFile': <class 'pyEDAA.ProjectModel.LogFile'>, 'ModelSimINIFile': <class 'pyEDAA.ProjectModel.MentorGraphics.QuestaSim.ModelSimINIFile'>, 'ModelSimProjectFile': <class 'pyEDAA.ProjectModel.MentorGraphics.QuestaSim.ModelSimProjectFile'>, 'NetlistFile': <class 'pyEDAA.ProjectModel.NetlistFile'>, 'OSVVMProjectFile': <class 'pyEDAA.ProjectModel.OSVVM.OSVVMProjectFile'>, 'ProjectFile': <class 'pyEDAA.ProjectModel.ProjectFile'>, 'PythonSourceFile': <class 'pyEDAA.ProjectModel.PythonSourceFile'>, 'QuartusProjectFile': <class 'pyEDAA.ProjectModel.Intel.QuartusPrime.QuartusProjectFile'>, 'RDLSourceFile': <class 'pyEDAA.ProjectModel.RDLSourceFile'>, 'SDCConstraintFile': <class 'pyEDAA.ProjectModel.Intel.QuartusPrime.SDCConstraintFile'>, 'SettingFile': <class 'pyEDAA.ProjectModel.SettingFile'>, 'SimulationAnalysisFile': <class 'pyEDAA.ProjectModel.SimulationAnalysisFile'>, 'SimulationElaborationFile': <class 'pyEDAA.ProjectModel.SimulationElaborationFile'>, 'SimulationRunFile': <class 'pyEDAA.ProjectModel.SimulationRunFile'>, 'SimulationStartFile': <class 'pyEDAA.ProjectModel.SimulationStartFile'>, 'SourceFile': <class 'pyEDAA.ProjectModel.SourceFile'>, 'SystemRDLSourceFile': <class 'pyEDAA.ProjectModel.SystemRDLSourceFile'>, 'SystemVerilogBaseFile': <class 'pyEDAA.ProjectModel.SystemVerilogBaseFile'>, 'SystemVerilogHeaderFile': <class 'pyEDAA.ProjectModel.SystemVerilogHeaderFile'>, 'SystemVerilogSourceFile': <class 'pyEDAA.ProjectModel.SystemVerilogSourceFile'>, 'TCLSourceFile': <class 'pyEDAA.ProjectModel.TCLSourceFile'>, 'TextFile': <class 'pyEDAA.ProjectModel.TextFile'>, 'UCFConstraintFile': <class 'pyEDAA.ProjectModel.Xilinx.ISE.UCFConstraintFile'>, 'VHDLSourceFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.VHDLSourceFile'>, 'ValueChangeDumpFile': <class 'pyEDAA.ProjectModel.Verilog.ValueChangeDumpFile'>, 'VerilogBaseFile': <class 'pyEDAA.ProjectModel.VerilogBaseFile'>, 'VerilogHeaderFile': <class 'pyEDAA.ProjectModel.VerilogHeaderFile'>, 'VerilogSourceFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.VerilogSourceFile'>, 'VivadoProjectFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.VivadoProjectFile'>, 'WaveDoFile': <class 'pyEDAA.ProjectModel.MentorGraphics.QuestaSim.WaveDoFile'>, 'WaveformConfigFile': <class 'pyEDAA.ProjectModel.WaveformConfigFile'>, 'WaveformDatabaseFile': <class 'pyEDAA.ProjectModel.WaveformDatabaseFile'>, 'WaveformExchangeFile': <class 'pyEDAA.ProjectModel.WaveformExchangeFile'>, 'XDCConstraintFile': <class 'pyEDAA.ProjectModel.Xilinx.Vivado.XDCConstraintFile'>, 'XMLFile': <class 'pyEDAA.ProjectModel.XMLFile'>}¶Dictionary of all classes of type FileType or derived variants
Construct a new class using this meta-class.
+className – The name of the class to construct.
baseClasses – The tuple of base-classes the class is derived from.
members – The dictionary of members for the constructed class.
slots – If true, store object attributes in __slots__ instead of __dict__.
mixin – If true, make the class a Mixin-Class.
+If false, create slots if slots is true.
+If none, preserve behavior of primary base-class.
singleton – If true, make the class a Singleton.
classMembers (Dict)
The new class.
+AttributeError – If base-class has no ‘__slots__’ attribute.
AttributeError – If slot already exists in base-class.
Read-only property to check if the class has Attributes (__pyattr__).
True, if the class has Attributes.
Read-only property to check if the class has methods with Attributes (__methodsWithAttributes__).
True, if the class has any method with Attributes.
alias of ExtendedType
Call self as a function.
+Implement delattr(self, name).
+Specialized __dir__ implementation for types.
+Return getattr(self, name).
+Check if an object is an instance.
+Return self|value.
+Create the namespace for the class statement
+Return repr(self).
+Return value|self.
+Implement setattr(self, name, value).
+Return memory consumption of the type object.
+Check if a class is a subclass.
+Return a list of immediate subclasses.
+Check if the current class contains abstract methods and return a tuple of them.
+These abstract methods might be inherited from any base-class. If there are inherited abstract methods, check if +they are now implemented (overridden) by the current class that’s right now constructed.
+ +Return a generator to iterate all possible inheritance paths for a given list of base-classes.
+An inheritance path is expressed as a tuple of base-classes from current base-class (left-most item) to
+object (right-most item).
If the class has abstract methods, replace the _new__ method, so it raises an exception.
newClass – The newly constructed class for further modifications.
+True, if the class is abstract.
AbstractClassError – If the class is abstract and can’t be instantiated.
+If a class is a singleton, wrap the _new__ method, so it returns a cached object, if a first object was created.
Only the first object creation initializes the object.
+This implementation is threadsafe.
+ +Return a type’s method resolution order.
+A File represents a file in a design. This base-class is used +for all derived file classes.
+A file can be created standalone and later associated to a fileset, design and +project. Or a fileset, design and/or project can be associated immediately +while creating a file.
+Inheritance
+ + + + + +Read-only property returning the path of this file.
+Read-only property returning the resolved path of this file.
+Property setting or returning the project this file is used in.
+Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A file type representing human-readable contents.
+Inheritance
+ +A file type representing XML contents.
+Inheritance
+ +A file type representing YAML contents.
+Inheritance
+ +A file type representing JSON contents.
+Inheritance
+ +A file type representing INI contents.
+Inheritance
+ +A file type representing TOML contents.
+Inheritance
+ +A file type representing content in TCL code.
+Inheritance
+ +A file type representing contents as Synopsys Design Constraints (SDC).
+Inheritance
+ +A file type representing contents as Python source code.
+Inheritance
+ +A text file (*.txt).
Inheritance
+ +Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A log file (*.log).
Inheritance
+ +Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +An XML file (*.xml).
Inheritance
+ +Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all source files.
+Inheritance
+ +alias of SourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all HDL source files.
+Inheritance
+ +alias of HDLSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all RDL source files.
+Inheritance
+ +alias of RDLSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all netlist source files.
+Inheritance
+ +alias of NetlistFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Netlist file in EDIF (Electronic Design Interchange Format).
+Inheritance
+ +alias of EDIFNetlistFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A TCL source file.
+Inheritance
+ +alias of TCLSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A VHDL source file (of any language version).
+path (Path) – Relative or absolute path to the file.
vhdlLibrary (Union[str, VHDLLibrary]) – VHDLLibrary this VHDL source file is associated wih.
vhdlVersion (Optional[VHDLVersion]) – VHDLVersion this VHDL source file is associated wih.
project (Optional[Project]) – Project the file is associated with.
design (Optional[Design]) – Design the file is associated with.
fileSet (Optional[FileSet]) – Fileset the file is associated with.
path
vhdlLibrary
vhdlVersion
project
design
fileSet
Inheritance
+ +path (Path)
vhdlLibrary (str | VHDLLibrary)
vhdlVersion (VHDLVersion | None)
project (Project | None)
design (Design | None)
fileSet (FileSet | None)
Property setting or returning the VHDL library this VHDL source file is used in.
+Property setting or returning the VHDL version this VHDL source file is used in.
+alias of VHDLSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of VerilogBaseFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Verilog source file (of any language version).
+Inheritance
+ +alias of VerilogSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Property setting or returning the Verilog version this Verilog source file is used in.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Verilog header file (of any language version).
+Inheritance
+ +alias of VerilogHeaderFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Property setting or returning the Verilog version this Verilog source file is used in.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Inheritance
+ +alias of SystemVerilogBaseFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A SystemVerilog source file (of any language version).
+Inheritance
+ +alias of SystemVerilogSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Property setting or returning the SystemVerilog version this SystemVerilog source file is used in.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A SystemVerilog header file (of any language version).
+Inheritance
+ +alias of SystemVerilogHeaderFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Property setting or returning the SystemVerilog version this SystemVerilog source file is used in.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A SystemRDL source file (of any language version).
+Inheritance
+ +Property setting or returning the SystemRDL version this SystemRDL source file is used in.
+alias of SystemRDLSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Python source file.
+Inheritance
+ +alias of PythonSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A Python source file used by Cocotb.
+Inheritance
+ +alias of CocotbPythonFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all constraint files.
+Inheritance
+ +alias of ConstraintFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific project files.
+Inheritance
+ +alias of ProjectFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all ANSI-C source files.
+Inheritance
+ +alias of CSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all ANSI-C++ source files.
+Inheritance
+ +alias of CppSourceFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific setting files.
+Inheritance
+ +alias of SettingFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific analysis files.
+Inheritance
+ +alias of SimulationAnalysisFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific elaboration files.
+Inheritance
+ +alias of SimulationElaborationFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific simulation start-up files.
+Inheritance
+ +alias of SimulationStartFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific simulation run (execution) files.
+Inheritance
+ +alias of SimulationRunFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific waveform configuration files.
+Inheritance
+ +alias of WaveformConfigFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-specific waveform database files.
+Inheritance
+ +alias of WaveformDatabaseFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +Base-class of all tool-independent waveform exchange files.
+Inheritance
+ +alias of WaveformExchangeFile
Property setting or returning the design this file is used in.
+Property setting or returning the fileset this file is used in.
+Read-only property returning the path of this file.
+Property setting or returning the project this file is used in.
+Read-only property returning the resolved path of this file.
+Index access for deleting attributes on this file.
+ +Index access for returning attributes on this file.
+ +Returns number of attributes set on this file.
+The number if attributes set on this file.
+Index access for adding or setting attributes on this file.
+ +A FileSet represents a group of files. Filesets can have sub-filesets.
+The order of insertion is preserved. A fileset can be created standalone and +later associated to another fileset, design and/or project. Or a fileset, +design and/or project can be associated immediately while creating the +fileset.
+name (str) – Name of this fileset.
directory (Path) – Path of this fileset (absolute or relative to a parent fileset or design).
project (Optional[Project]) – Project the file is associated with.
design (Optional[Design]) – Design the file is associated with.
parent (Optional[FileSet]) – Parent fileset if this fileset is nested.
vhdlLibrary (Union[str, VHDLLibrary]) – Default VHDL library for files in this fileset, if not specified for the file itself.
vhdlVersion (Optional[VHDLVersion]) – Default VHDL version for files in this fileset, if not specified for the file itself.
verilogVersion (Optional[SystemVerilogVersion]) – Default Verilog version for files in this fileset, if not specified for the file itself.
svVersion (Optional[SystemVerilogVersion]) – Default SystemVerilog version for files in this fileset, if not specified for the file itself.
srdlVersion (Optional[SystemRDLVersion]) – Default SystemRDL version for files in this fileset, if not specified for the file itself.
name
topLevel
directory
project
design
parent
vhdlLibrary
vhdlVersion
verilogVersion
svVersion
srdlVersion
Inheritance
+ +name (str)
topLevel (str | None)
directory (Path)
project (Project | None)
design (Design | None)
parent (FileSet | None)
vhdlLibrary (str | VHDLLibrary)
vhdlVersion (VHDLVersion | None)
verilogVersion (SystemVerilogVersion | None)
svVersion (SystemVerilogVersion | None)
srdlVersion (SystemRDLVersion | None)
Property setting or returning the project this fileset is used in.
+Property setting or returning the design this fileset is used in.
+Property setting or returning the directory this fileset is located in.
+Read-only property returning the resolved path of this fileset.
+Property setting or returning the parent fileset this fileset is used in.
+Read-only property returning the dictionary of sub-filesets.
+Method returning the files of this fileset.
+ +Property setting or returning the VHDL library of this fileset.
+Property setting or returning the VHDL version of this fileset.
+Property setting or returning the Verilog version of this fileset.
+Property setting or returning the SystemVerilog version of this fileset.
+Returns number of attributes set on this fileset.
+The number if attributes set on this fileset.
+Index access for adding or setting attributes on this fileset.
+ +A VHDLLibrary represents a group of VHDL source files compiled into the same VHDL library.
+name (str) – The VHDL libraries’ name.
project (Optional[Project]) – Project the VHDL library is associated with.
design (Optional[Design]) – Design the VHDL library is associated with.
vhdlVersion (Optional[VHDLVersion]) – Default VHDL version for files in this VHDL library, if not specified for the file itself.
name
project
design
vhdlVersion
Inheritance
+ + + +Property setting or returning the project this VHDL library is used in.
+Property setting or returning the design this VHDL library is used in.
+Read-only property to return all files in this VHDL library.
+Property setting or returning the VHDL version of this VHDL library.
+Returns number of attributes set on this VHDL library.
+The number if attributes set on this VHDL library.
+Index access for adding or setting attributes on this VHDL library.
+ +A Design represents a group of filesets and the source files therein.
+Each design contains at least one fileset - the default fileset. For +designs with VHDL source files, a independent VHDLLibraries overlay structure +exists.
+name (str) – The design’s name.
directory (Path) – Path of this design (absolute or relative to the project).
project (Optional[Project]) – Project the design is associated with.
vhdlVersion (Optional[VHDLVersion]) – Default VHDL version for files in this design, if not specified for the file itself.
verilogVersion (Optional[SystemVerilogVersion]) – Default Verilog version for files in this design, if not specified for the file itself.
svVersion (Optional[SystemVerilogVersion]) – Default SystemVerilog version for files in this design, if not specified for the file itself.
srdlVersion (Optional[SystemRDLVersion]) – Default SystemRDL version for files in this fileset, if not specified for the file itself.
name
topLevel
directory
project
vhdlVersion
verilogVersion
svVersion
srdlVersion
Inheritance
+ +Property setting or returning the project this design is used in.
+Property setting or returning the directory this design is located in.
+Read-only property returning the resolved path of this fileset.
+Property setting or returning the default fileset of this design.
+Read-only property returning the dictionary of filesets.
+Method returning the files of this design.
+ +Returns number of attributes set on this design.
+The number if attributes set on this design.
+Index access for adding or setting attributes on this design.
+ +A Project represents a group of designs and the source files therein.
+name (str) – The project’s name.
rootDirectory (Path) – Base-path to the project.
vhdlVersion (Optional[VHDLVersion]) – Default VHDL version for files in this project, if not specified for the file itself.
verilogVersion (Optional[SystemVerilogVersion]) – Default Verilog version for files in this project, if not specified for the file itself.
svVersion (Optional[SystemVerilogVersion]) – Default SystemVerilog version for files in this project, if not specified for the file itself.
name
rootDirectory
vhdlVersion
verilogVersion
svVersion
Inheritance
+ +name (str)
rootDirectory (Path)
vhdlVersion (VHDLVersion | None)
verilogVersion (SystemVerilogVersion | None)
svVersion (SystemVerilogVersion | None)
Property setting or returning the root directory this project is located in.
+Read-only property returning the resolved path of this fileset.
+Returns number of attributes set on this project.
+The number if attributes set on this project.
+Index access for adding or setting attributes on this project.
+ +Introduction
+ +Main Documentation
+ +References
+pyEDAA.ProjectModelpyEDAA.ProjectModel.AlterapyEDAA.ProjectModel.AttributespyEDAA.ProjectModel.GHDLpyEDAA.ProjectModel.IntelpyEDAA.ProjectModel.MentorGraphicspyEDAA.ProjectModel.OSVVMpyEDAA.ProjectModel.VHDLpyEDAA.ProjectModel.VerilogpyEDAA.ProjectModel.XilinxAttributeFileTypeFileType.FileTypesFileType.__init__()FileType.__new__()FileType.HasClassAttributesFileType.HasMethodAttributesFileType.__base__FileType.__call__()FileType.__delattr__()FileType.__dir__()FileType.__getattribute__()FileType.__instancecheck__()FileType.__or__()FileType.__prepare__()FileType.__repr__()FileType.__ror__()FileType.__setattr__()FileType.__sizeof__()FileType.__subclasscheck__()FileType.__subclasses__()FileType._checkForAbstractMethods()FileType._iterateBaseClassPaths()FileType._wrapNewMethodIfAbstract()FileType._wrapNewMethodIfSingleton()FileType.mro()File
+HumanReadableContentXMLContentYAMLContentJSONContentINIContentTOMLContentTCLContentSDCContentPythonContentTextFile
+LogFile
+XMLFile
+SourceFileSourceFile.AnySourceFile.DesignSourceFile.FileSetSourceFile.FileTypeSourceFile.PathSourceFile.ProjectSourceFile.ResolvedPathSourceFile.Validate()SourceFile.__delitem__()SourceFile.__getitem__()SourceFile.__init__()SourceFile.__len__()SourceFile.__setitem__()SourceFile.__str__()HDLSourceFileHDLSourceFile.AnyHDLSourceFile.DesignHDLSourceFile.FileSetHDLSourceFile.FileTypeHDLSourceFile.PathHDLSourceFile.ProjectHDLSourceFile.ResolvedPathHDLSourceFile.Validate()HDLSourceFile.__delitem__()HDLSourceFile.__getitem__()HDLSourceFile.__init__()HDLSourceFile.__len__()HDLSourceFile.__setitem__()HDLSourceFile.__str__()RDLSourceFileRDLSourceFile.AnyRDLSourceFile.DesignRDLSourceFile.FileSetRDLSourceFile.FileTypeRDLSourceFile.PathRDLSourceFile.ProjectRDLSourceFile.ResolvedPathRDLSourceFile.Validate()RDLSourceFile.__delitem__()RDLSourceFile.__getitem__()RDLSourceFile.__init__()RDLSourceFile.__len__()RDLSourceFile.__setitem__()RDLSourceFile.__str__()NetlistFileNetlistFile.AnyNetlistFile.DesignNetlistFile.FileSetNetlistFile.FileTypeNetlistFile.PathNetlistFile.ProjectNetlistFile.ResolvedPathNetlistFile.Validate()NetlistFile.__delitem__()NetlistFile.__getitem__()NetlistFile.__init__()NetlistFile.__len__()NetlistFile.__setitem__()NetlistFile.__str__()EDIFNetlistFileEDIFNetlistFile.AnyEDIFNetlistFile.DesignEDIFNetlistFile.FileSetEDIFNetlistFile.FileTypeEDIFNetlistFile.PathEDIFNetlistFile.ProjectEDIFNetlistFile.ResolvedPathEDIFNetlistFile.Validate()EDIFNetlistFile.__delitem__()EDIFNetlistFile.__getitem__()EDIFNetlistFile.__init__()EDIFNetlistFile.__len__()EDIFNetlistFile.__setitem__()EDIFNetlistFile.__str__()TCLSourceFileTCLSourceFile.AnyTCLSourceFile.DesignTCLSourceFile.FileSetTCLSourceFile.FileTypeTCLSourceFile.PathTCLSourceFile.ProjectTCLSourceFile.ResolvedPathTCLSourceFile.Validate()TCLSourceFile.__delitem__()TCLSourceFile.__getitem__()TCLSourceFile.__init__()TCLSourceFile.__len__()TCLSourceFile.__setitem__()TCLSourceFile.__str__()VHDLSourceFileVHDLSourceFile.__init__()VHDLSourceFile.Validate()VHDLSourceFile.VHDLLibraryVHDLSourceFile.VHDLVersionVHDLSourceFile.__repr__()VHDLSourceFile.AnyVHDLSourceFile.DesignVHDLSourceFile.FileSetVHDLSourceFile.FileTypeVHDLSourceFile.PathVHDLSourceFile.ProjectVHDLSourceFile.ResolvedPathVHDLSourceFile.__delitem__()VHDLSourceFile.__getitem__()VHDLSourceFile.__len__()VHDLSourceFile.__setitem__()VHDLSourceFile.__str__()VerilogBaseFileVerilogBaseFile.__init__()VerilogBaseFile.AnyVerilogBaseFile.DesignVerilogBaseFile.FileSetVerilogBaseFile.FileTypeVerilogBaseFile.PathVerilogBaseFile.ProjectVerilogBaseFile.ResolvedPathVerilogBaseFile.Validate()VerilogBaseFile.__delitem__()VerilogBaseFile.__getitem__()VerilogBaseFile.__len__()VerilogBaseFile.__setitem__()VerilogBaseFile.__str__()VerilogSourceFileVerilogSourceFile.AnyVerilogSourceFile.DesignVerilogSourceFile.FileSetVerilogSourceFile.FileTypeVerilogSourceFile.PathVerilogSourceFile.ProjectVerilogSourceFile.ResolvedPathVerilogSourceFile.Validate()VerilogSourceFile.VerilogVersionVerilogSourceFile.__delitem__()VerilogSourceFile.__getitem__()VerilogSourceFile.__init__()VerilogSourceFile.__len__()VerilogSourceFile.__setitem__()VerilogSourceFile.__str__()VerilogHeaderFileVerilogHeaderFile.AnyVerilogHeaderFile.DesignVerilogHeaderFile.FileSetVerilogHeaderFile.FileTypeVerilogHeaderFile.PathVerilogHeaderFile.ProjectVerilogHeaderFile.ResolvedPathVerilogHeaderFile.Validate()VerilogHeaderFile.VerilogVersionVerilogHeaderFile.__delitem__()VerilogHeaderFile.__getitem__()VerilogHeaderFile.__init__()VerilogHeaderFile.__len__()VerilogHeaderFile.__setitem__()VerilogHeaderFile.__str__()SystemVerilogBaseFileSystemVerilogBaseFile.AnySystemVerilogBaseFile.DesignSystemVerilogBaseFile.FileSetSystemVerilogBaseFile.FileTypeSystemVerilogBaseFile.PathSystemVerilogBaseFile.ProjectSystemVerilogBaseFile.ResolvedPathSystemVerilogBaseFile.Validate()SystemVerilogBaseFile.__delitem__()SystemVerilogBaseFile.__getitem__()SystemVerilogBaseFile.__init__()SystemVerilogBaseFile.__len__()SystemVerilogBaseFile.__setitem__()SystemVerilogBaseFile.__str__()SystemVerilogSourceFileSystemVerilogSourceFile.AnySystemVerilogSourceFile.DesignSystemVerilogSourceFile.FileSetSystemVerilogSourceFile.FileTypeSystemVerilogSourceFile.PathSystemVerilogSourceFile.ProjectSystemVerilogSourceFile.ResolvedPathSystemVerilogSourceFile.SVVersionSystemVerilogSourceFile.Validate()SystemVerilogSourceFile.__delitem__()SystemVerilogSourceFile.__getitem__()SystemVerilogSourceFile.__init__()SystemVerilogSourceFile.__len__()SystemVerilogSourceFile.__setitem__()SystemVerilogSourceFile.__str__()SystemVerilogHeaderFileSystemVerilogHeaderFile.AnySystemVerilogHeaderFile.DesignSystemVerilogHeaderFile.FileSetSystemVerilogHeaderFile.FileTypeSystemVerilogHeaderFile.PathSystemVerilogHeaderFile.ProjectSystemVerilogHeaderFile.ResolvedPathSystemVerilogHeaderFile.SVVersionSystemVerilogHeaderFile.Validate()SystemVerilogHeaderFile.__delitem__()SystemVerilogHeaderFile.__getitem__()SystemVerilogHeaderFile.__init__()SystemVerilogHeaderFile.__len__()SystemVerilogHeaderFile.__setitem__()SystemVerilogHeaderFile.__str__()SystemRDLSourceFileSystemRDLSourceFile.__init__()SystemRDLSourceFile.SystemRDLVersionSystemRDLSourceFile.AnySystemRDLSourceFile.DesignSystemRDLSourceFile.FileSetSystemRDLSourceFile.FileTypeSystemRDLSourceFile.PathSystemRDLSourceFile.ProjectSystemRDLSourceFile.ResolvedPathSystemRDLSourceFile.Validate()SystemRDLSourceFile.__delitem__()SystemRDLSourceFile.__getitem__()SystemRDLSourceFile.__len__()SystemRDLSourceFile.__setitem__()SystemRDLSourceFile.__str__()PythonSourceFilePythonSourceFile.AnyPythonSourceFile.DesignPythonSourceFile.FileSetPythonSourceFile.FileTypePythonSourceFile.PathPythonSourceFile.ProjectPythonSourceFile.ResolvedPathPythonSourceFile.Validate()PythonSourceFile.__delitem__()PythonSourceFile.__getitem__()PythonSourceFile.__init__()PythonSourceFile.__len__()PythonSourceFile.__setitem__()PythonSourceFile.__str__()CocotbPythonFileCocotbPythonFile.AnyCocotbPythonFile.DesignCocotbPythonFile.FileSetCocotbPythonFile.FileTypeCocotbPythonFile.PathCocotbPythonFile.ProjectCocotbPythonFile.ResolvedPathCocotbPythonFile.Validate()CocotbPythonFile.__delitem__()CocotbPythonFile.__getitem__()CocotbPythonFile.__init__()CocotbPythonFile.__len__()CocotbPythonFile.__setitem__()CocotbPythonFile.__str__()ConstraintFileConstraintFile.AnyConstraintFile.DesignConstraintFile.FileSetConstraintFile.FileTypeConstraintFile.PathConstraintFile.ProjectConstraintFile.ResolvedPathConstraintFile.Validate()ConstraintFile.__delitem__()ConstraintFile.__getitem__()ConstraintFile.__init__()ConstraintFile.__len__()ConstraintFile.__setitem__()ConstraintFile.__str__()ProjectFileProjectFile.AnyProjectFile.DesignProjectFile.FileSetProjectFile.FileTypeProjectFile.PathProjectFile.ProjectProjectFile.ResolvedPathProjectFile.Validate()ProjectFile.__delitem__()ProjectFile.__getitem__()ProjectFile.__init__()ProjectFile.__len__()ProjectFile.__setitem__()ProjectFile.__str__()CSourceFileCSourceFile.AnyCSourceFile.DesignCSourceFile.FileSetCSourceFile.FileTypeCSourceFile.PathCSourceFile.ProjectCSourceFile.ResolvedPathCSourceFile.Validate()CSourceFile.__delitem__()CSourceFile.__getitem__()CSourceFile.__init__()CSourceFile.__len__()CSourceFile.__setitem__()CSourceFile.__str__()CppSourceFileCppSourceFile.AnyCppSourceFile.DesignCppSourceFile.FileSetCppSourceFile.FileTypeCppSourceFile.PathCppSourceFile.ProjectCppSourceFile.ResolvedPathCppSourceFile.Validate()CppSourceFile.__delitem__()CppSourceFile.__getitem__()CppSourceFile.__init__()CppSourceFile.__len__()CppSourceFile.__setitem__()CppSourceFile.__str__()SettingFileSettingFile.AnySettingFile.DesignSettingFile.FileSetSettingFile.FileTypeSettingFile.PathSettingFile.ProjectSettingFile.ResolvedPathSettingFile.Validate()SettingFile.__delitem__()SettingFile.__getitem__()SettingFile.__init__()SettingFile.__len__()SettingFile.__setitem__()SettingFile.__str__()SimulationAnalysisFileSimulationAnalysisFile.AnySimulationAnalysisFile.DesignSimulationAnalysisFile.FileSetSimulationAnalysisFile.FileTypeSimulationAnalysisFile.PathSimulationAnalysisFile.ProjectSimulationAnalysisFile.ResolvedPathSimulationAnalysisFile.Validate()SimulationAnalysisFile.__delitem__()SimulationAnalysisFile.__getitem__()SimulationAnalysisFile.__init__()SimulationAnalysisFile.__len__()SimulationAnalysisFile.__setitem__()SimulationAnalysisFile.__str__()SimulationElaborationFileSimulationElaborationFile.AnySimulationElaborationFile.DesignSimulationElaborationFile.FileSetSimulationElaborationFile.FileTypeSimulationElaborationFile.PathSimulationElaborationFile.ProjectSimulationElaborationFile.ResolvedPathSimulationElaborationFile.Validate()SimulationElaborationFile.__delitem__()SimulationElaborationFile.__getitem__()SimulationElaborationFile.__init__()SimulationElaborationFile.__len__()SimulationElaborationFile.__setitem__()SimulationElaborationFile.__str__()SimulationStartFileSimulationStartFile.AnySimulationStartFile.DesignSimulationStartFile.FileSetSimulationStartFile.FileTypeSimulationStartFile.PathSimulationStartFile.ProjectSimulationStartFile.ResolvedPathSimulationStartFile.Validate()SimulationStartFile.__delitem__()SimulationStartFile.__getitem__()SimulationStartFile.__init__()SimulationStartFile.__len__()SimulationStartFile.__setitem__()SimulationStartFile.__str__()SimulationRunFileSimulationRunFile.AnySimulationRunFile.DesignSimulationRunFile.FileSetSimulationRunFile.FileTypeSimulationRunFile.PathSimulationRunFile.ProjectSimulationRunFile.ResolvedPathSimulationRunFile.Validate()SimulationRunFile.__delitem__()SimulationRunFile.__getitem__()SimulationRunFile.__init__()SimulationRunFile.__len__()SimulationRunFile.__setitem__()SimulationRunFile.__str__()WaveformConfigFileWaveformConfigFile.AnyWaveformConfigFile.DesignWaveformConfigFile.FileSetWaveformConfigFile.FileTypeWaveformConfigFile.PathWaveformConfigFile.ProjectWaveformConfigFile.ResolvedPathWaveformConfigFile.Validate()WaveformConfigFile.__delitem__()WaveformConfigFile.__getitem__()WaveformConfigFile.__init__()WaveformConfigFile.__len__()WaveformConfigFile.__setitem__()WaveformConfigFile.__str__()WaveformDatabaseFileWaveformDatabaseFile.AnyWaveformDatabaseFile.DesignWaveformDatabaseFile.FileSetWaveformDatabaseFile.FileTypeWaveformDatabaseFile.PathWaveformDatabaseFile.ProjectWaveformDatabaseFile.ResolvedPathWaveformDatabaseFile.Validate()WaveformDatabaseFile.__delitem__()WaveformDatabaseFile.__getitem__()WaveformDatabaseFile.__init__()WaveformDatabaseFile.__len__()WaveformDatabaseFile.__setitem__()WaveformDatabaseFile.__str__()WaveformExchangeFileWaveformExchangeFile.AnyWaveformExchangeFile.DesignWaveformExchangeFile.FileSetWaveformExchangeFile.FileTypeWaveformExchangeFile.PathWaveformExchangeFile.ProjectWaveformExchangeFile.ResolvedPathWaveformExchangeFile.Validate()WaveformExchangeFile.__delitem__()WaveformExchangeFile.__getitem__()WaveformExchangeFile.__init__()WaveformExchangeFile.__len__()WaveformExchangeFile.__setitem__()WaveformExchangeFile.__str__()FileSetFileSet.__init__()FileSet.NameFileSet.TopLevelFileSet.ProjectFileSet.DesignFileSet.DirectoryFileSet.ResolvedPathFileSet.ParentFileSet.FileSetsFileSet.Files()FileSet.AddFileSet()FileSet.AddFileSets()FileSet.FileSetCountFileSet.TotalFileSetCountFileSet.AddFile()FileSet.AddFiles()FileSet.FileCountFileSet.TotalFileCountFileSet.Validate()FileSet.VHDLLibraryFileSet.VHDLVersionFileSet.VerilogVersionFileSet.SVVersionFileSet.__len__()FileSet.__getitem__()FileSet.__setitem__()FileSet.__delitem__()FileSet.__str__()VHDLLibrary
+DesignDesign.__init__()Design.NameDesign.TopLevelDesign.ProjectDesign.DirectoryDesign.ResolvedPathDesign.DefaultFileSetDesign.FileSetsDesign.Files()Design.Validate()Design.FileSetCountDesign.TotalFileSetCountDesign.__len__()Design.__getitem__()Design.__setitem__()Design.__delitem__()Design.__str__()Project
+Appendix
+pyEDAA.ProjectModel.Altera+ Searching for multiple words only shows matches that contain + all words. +
+ + + + + + + + +Introduction
+ +Main Documentation
+ +References
+ +Appendix
+pyEDAA.ProjectModel", "pyEDAA.ProjectModel.Altera", "pyEDAA.ProjectModel.Altera.Quartus", "pyEDAA.ProjectModel.Attributes", "pyEDAA.ProjectModel.GHDL", "pyEDAA.ProjectModel.Intel", "pyEDAA.ProjectModel.Intel.QuartusPrime", "pyEDAA.ProjectModel.MentorGraphics", "pyEDAA.ProjectModel.MentorGraphics.ModelSim", "pyEDAA.ProjectModel.MentorGraphics.QuestaSim", "pyEDAA.ProjectModel.OSVVM", "pyEDAA.ProjectModel.VHDL", "pyEDAA.ProjectModel.Verilog", "pyEDAA.ProjectModel.Xilinx", "pyEDAA.ProjectModel.Xilinx.ISE", "pyEDAA.ProjectModel.Xilinx.Vivado", "Static Type Checking Report"], "titleterms": {"0": [2, 6], "01": 0, "09": 0, "1": [2, 6], "2": [2, 6], "2021": [0, 15], "3": [2, 6], "4": [2, 6], "5": [2, 6], "6": [2, 6], "7": [2, 6], "8": [2, 6], "9": 6, "ISE": 32, "The": 15, "accept": 6, "addit": 6, "altera": [19, 20], "apach": 6, "attribut": [2, 21], "case": 15, "changelog": 0, "check": [1, 34], "ci": 1, "class": [7, 8, 9, 10, 11, 17], "common": 2, "condens": [7, 8, 9, 10, 11], "condit": 2, "content": 3, "contribut": 6, "contributor": 15, "copyright": 6, "coverag": [1, 13], "creativ": 2, "databas": 2, "definit": [2, 6, 7, 8, 9, 10, 11], "depend": 1, "design": 7, "directori": 5, "disclaim": [2, 6], "document": [1, 15], "extract": 15, "file": [3, 8, 15], "fileset": 9, "from": [5, 15], "generi": 2, "ghdl": 22, "glossari": 4, "goal": 15, "grant": 6, "hierarchi": 3, "index": [14, 16], "instal": 5, "intel": [23, 24], "intern": 2, "interpret": 2, "legaci": 5, "liabil": [2, 6], "librari": 11, "licens": [2, 6, 15], "limit": [2, 6], "local": 5, "main": 15, "mentorgraph": [25, 26, 27], "model": 12, "modelsim": 26, "modul": 16, "new": 15, "oct": 15, "onli": 1, "option": 1, "osvvm": 28, "other": 2, "overal": 3, "packag": 1, "patent": 6, "pip": 5, "pro": 15, "project": [10, 12], "projectmodel": [1, 15, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33], "public": 2, "publish": 1, "py": 5, "pyedaa": [1, 15, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33], "pyipcmi": 15, "pypi": 5, "python": 17, "quartu": 20, "quartusprim": 24, "questasim": 27, "read": 15, "redistribut": 6, "refer": 17, "releas": 0, "report": [13, 34], "right": 2, "scope": 2, "section": 2, "sep": 15, "server": 1, "setup": 5, "sphinx": 1, "static": 34, "submiss": 6, "sui": 2, "term": 2, "termin": 2, "test": 1, "todo": [7, 8, 9, 10, 11], "trademark": 6, "type": [1, 3, 34], "uninstal": 5, "unit": 1, "upcom": 0, "updat": 5, "us": [2, 5, 15], "verilog": 30, "vhdl": [11, 29], "vhdllibrari": 11, "vivado": 33, "warranti": [2, 6], "xilinx": [31, 32, 33], "xpr": 15}})
\ No newline at end of file
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+1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 + |
+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Altera Quartus.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, SDCContent, TCLContent + + +@export +class QuartusProjectFile(ProjectFile, TCLContent): + """A Quartus project file (``*.qpf``).""" + + +@export +class SDCConstraintFile(ConstraintFile, SDCContent): + """A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``).""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""A vendor specific package for Altera (now Intel FPGA).""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""A set of common attributes to store meta information on ProjectModel entities (project, design, fileset, file, ...).""" +from typing import Dict +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import Attribute + + +@export +class KeyValueAttribute(Attribute): + KEY = "ID" + + _keyValuePairs: Dict[str, str] + + def __init__(self) -> None: + super().__init__() + + self._keyValuePairs = {} + + def __getitem__(self, item: str) -> str: + return self._keyValuePairs[item] + + def __setitem__(self, key: str, value: str) -> None: + self._keyValuePairs[key] = value + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for `GHDL <https://github.com/ghdl>`__.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import WaveformExchangeFile + + +@export +class GHDLWaveformFile(WaveformExchangeFile): + """GHDL's waveform file (``*.ghw``) supporting VHDL and Verilog simulation results.""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Intel FPGA Quartus Prime.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, SDCContent, TCLContent + + +@export +class QuartusProjectFile(ProjectFile, TCLContent): + """A Quartus project file (``*.qpf``).""" + + +@export +class SDCConstraintFile(ConstraintFile, SDCContent): + """A Quartus constraint file (Synopsys Design Constraints; ``*.sdc``).""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""A vendor specific package for Intel FPGA (formerly Altera).""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Mentor Graphics ModelSim.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import ProjectFile, SettingFile, INIContent, WaveformConfigFile, TCLContent + + +@export +class ModelSimProjectFile(ProjectFile): + pass + + +@export +class ModelSimINIFile(SettingFile, INIContent): + pass + + +@export +class WaveDoFile(WaveformConfigFile, TCLContent): + pass + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Mentor Graphics QuestaSim.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import ProjectFile, SettingFile, INIContent, WaveformConfigFile, TCLContent + + +@export +class ModelSimProjectFile(ProjectFile): + pass + + +@export +class ModelSimINIFile(SettingFile, INIContent): + pass + + +@export +class WaveDoFile(WaveformConfigFile, TCLContent): + pass + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""A vendor specific package for Mentor Graphics (now Siemens EDA).""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for `OSVVM <https://github.com/OSVVM>`__.""" +from pathlib import Path + +from pyTooling.Decorators import export +from typing import Optional as Nullable, List + +from pyEDAA.ProjectModel import ProjectFile, TCLContent, Project, Design, FileSet, VHDLLibrary, VHDLSourceFile + + +@export +class OSVVMProjectFile(ProjectFile, TCLContent): + """An OSVVM project file (``*.pro``).""" + + _osvvmProject: Nullable[Project] + + def __init__( + self, + path: Path, + project: Nullable[Project] = None, + design: Nullable[Design] = None, + fileSet: Nullable[FileSet] = None + ): + super().__init__(path, project, design, fileSet) + + self._osvvmProject = None + + @property + def ProjectModel(self) -> Project: + return self._osvvmProject + + class Instruction: + _line: int + + def __init__(self, line: int): + self._line = line + + class Empty(Instruction): + def __init__(self, line: int): + super().__init__(line) + + class Comment(Instruction): + _commentText: str + + def __init__(self, line: int, commentText: str): + super().__init__(line) + self._commentText = commentText.rstrip() + + @property + def CommentText(self) -> str: + return self._commentText + + class Analyze(Instruction): + _vhdlSourceFile: VHDLSourceFile + + def __init__(self, line: int, parameterText: str): + super().__init__(line) + self._vhdlSourceFile = VHDLSourceFile(Path(parameterText.strip())) + + @property + def VHDLSourceFile(self) -> VHDLSourceFile: + return self._vhdlSourceFile + + class Library(Instruction): + _vhdlLibrary: VHDLLibrary + + def __init__(self, line: int, parameterText: str): + super().__init__(line) + self._vhdlLibrary = VHDLLibrary(parameterText.strip()) + + @property + def VHDLLibrary(self) -> VHDLLibrary: + return self._vhdlLibrary + + class Include(Instruction): + _osvvmProjectFile: 'OSVVMProjectFile' + _fileSet: FileSet + + def __init__(self, line: int, workingDirectory: Path, parameterText: str): + super().__init__(line) + + includeFile = Path(parameterText.strip()) + includePath = (workingDirectory / includeFile).resolve() + + self._fileSet = FileSet(includeFile.name, directory=includeFile.parent) + self._osvvmProjectFile = OSVVMProjectFile(includePath) + + @property + def OSVVMProjectFile(self) -> 'OSVVMProjectFile': + return self._osvvmProjectFile + + def Parse(self, fileSet: FileSet): + self._fileSet.Parent = fileSet + + for instruction in self._osvvmProjectFile._Parse(): + if isinstance(instruction, OSVVMProjectFile.Include): + instruction.Parse(self._fileSet) + elif isinstance(instruction, OSVVMProjectFile.Analyze): + self._fileSet.AddFile(instruction.VHDLSourceFile) + elif isinstance(instruction, OSVVMProjectFile.Library): + self._fileSet.Design.AddVHDLLibrary(instruction.VHDLLibrary) +# elif isinstance(instruction, OSVVMProjectFile.Build): + + elif not isinstance(instruction, (OSVVMProjectFile.Empty, OSVVMProjectFile.Comment)): + raise Exception(f"Unknown instruction '{instruction.__class__.__name__}' in OSVVM project file '{self._osvvmProjectFile.ResolvedPath}'") + + def Parse(self) -> None: + projectName = self._path.name + self._osvvmProject = Project(projectName, rootDirectory=self._path.parent) + + fileSet = self._osvvmProject.DefaultDesign.DefaultFileSet + + for instruction in self._Parse(): + if isinstance(instruction, OSVVMProjectFile.Include): + instruction.Parse(fileSet) + elif isinstance(instruction, OSVVMProjectFile.Analyze): + fileSet.AddFile(instruction.VHDLSourceFile) + elif not isinstance(instruction, (OSVVMProjectFile.Empty, OSVVMProjectFile.Comment)): + raise Exception(f"Unknown instruction '{instruction.__class__.__name__}' in OSVVM project file '{self.ResolvedPath}'") + + def _Parse(self) -> List: + path = self.ResolvedPath + if not path.exists(): + raise Exception(f"OSVVM project file '{path}' not found.") from FileNotFoundError(f"File '{path}' not found.") + + instructions: List = [] + print() + with path.open("r", encoding="utf-8") as file: + i = 1 + for line in file: + line = line.lstrip() + + if line.startswith("#"): + comment = OSVVMProjectFile.Comment(i, line[1:]) + instructions.append(comment) + + elif line.startswith("analyze"): + vhdlFile = OSVVMProjectFile.Analyze(i, line[8:]) + instructions.append(vhdlFile) + + elif line.startswith("library"): + vhdlLibrary = OSVVMProjectFile.Library(i, line[8:]) + instructions.append(vhdlLibrary) + + elif line.startswith("include"): + include = OSVVMProjectFile.Include(i, path.parent, line[8:]) + instructions.append(include) + + elif line.startswith("build"): + parameter = line[6:] + print(f"BUILD: {parameter}") + elif line.startswith("if"): + print(f"IF (line={i}): {line[3:].rstrip()}") + elif line.startswith("}"): + print(f"}} (line={i}): {line[2:].rstrip()}") + elif len(line) == 0: + instructions.append(OSVVMProjectFile.Empty(i)) + else: + print(f"UNKNOWN (line={i}): '{line.rstrip()}'") + + i += 1 + + return instructions + |
+
| + | + |
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Verilog.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import WaveformExchangeFile + + +@export +class ValueChangeDumpFile(WaveformExchangeFile): + """Verilog's waveform file (``*.vcd``) for exchanging value changes as defined by IEEE Std. 1364.""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Xilinx ISE.""" +from pyTooling.Decorators import export + +from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, HumanReadableContent + + +@export +class ISEProjectFile(ProjectFile): + pass + + +@export +class UCFConstraintFile(ConstraintFile, HumanReadableContent): + pass + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""Specific file types and attributes for Xilinx Vivado.""" +from pathlib import Path +from typing import Iterable, Optional as Nullable +from xml.dom import minidom, Node + +from pyTooling.Decorators import export +from pyTooling.MetaClasses import ExtendedType +from pyVHDLModel import VHDLVersion + +from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, Attribute, Design +from pyEDAA.ProjectModel import File as Model_File +from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile +from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile +from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile + + +@export +class UsedInAttribute(Attribute): + KEY = "UsedIn" + VALUE_TYPE = Iterable[str] + + +@export +class File(Model_File): + pass + + +class VivadoFileMixIn(metaclass=ExtendedType, mixin=True): + def _registerAttributes(self) -> None: + self._attributes[UsedInAttribute] = [] + + +@export +class ConstraintFile(Model_ConstraintFile, VivadoFileMixIn): + def _registerAttributes(self) -> None: + super()._registerAttributes() + VivadoFileMixIn._registerAttributes(self) + + +@export +class VerilogSourceFile(Model_VerilogSourceFile): + def _registerAttributes(self) -> None: + super()._registerAttributes() + VivadoFileMixIn._registerAttributes(self) + + +@export +class VHDLSourceFile(Model_VHDLSourceFile): + def _registerAttributes(self) -> None: + super()._registerAttributes() + VivadoFileMixIn._registerAttributes(self) + + +@export +class VivadoProjectFile(ProjectFile, XMLContent): + """A Vivado project file (``*.xpr``).""" + + _xprProject: Project + + def __init__( + self, + path: Path, + project: Nullable[Project] = None, + design: Nullable[Design] = None, + fileSet: Nullable[FileSet] = None + ) -> None: + super().__init__(path, project, design, fileSet) + + self._xprProject = None + + @property + def ProjectModel(self) -> Project: + return self._xprProject + + def Parse(self) -> None: + if not self._path.exists(): + raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.") + + try: + root = minidom.parse(str(self._path)).documentElement + except Exception as ex: + raise Exception(f"Couldn't open '{self._path!s}'.") from ex + + self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent) + self._ParseRootElement(root) + + def _ParseRootElement(self, root) -> None: + for rootNode in root.childNodes: + if rootNode.nodeName == "FileSets": + self._ParseFileSets(rootNode) + break + + def _ParseFileSets(self, filesetsNode) -> None: + for fileSetsNode in filesetsNode.childNodes: + if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet": + self._ParseFileSet(fileSetsNode) + + def _ParseFileSet(self, filesetNode) -> None: + filesetName = filesetNode.getAttribute("Name") + fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign) + + for fileNode in filesetNode.childNodes: + if fileNode.nodeType == Node.ELEMENT_NODE: + if fileNode.tagName == "File": + self._ParseFile(fileNode, fileset) + elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config": + self._ParseFileSetConfig(fileNode, fileset) + + def _ParseFile(self, fileNode, fileset) -> None: + croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "") + filePath = Path(croppedPath) + if filePath.suffix in (".vhd", ".vhdl"): + self._ParseVHDLFile(fileNode, filePath, fileset) + elif filePath.suffix == ".xdc": + self._ParseXDCFile(fileNode, filePath, fileset) + elif filePath.suffix == ".v": + self._ParseVerilogFile(fileNode, filePath, fileset) + elif filePath.suffix == ".xci": + self._ParseXCIFile(fileNode, filePath, fileset) + else: + self._ParseDefaultFile(fileNode, filePath, fileset) + + def _ParseVHDLFile(self, fileNode, path, fileset) -> None: + vhdlFile = VHDLSourceFile(path) + fileset.AddFile(vhdlFile) + usedInAttr = vhdlFile[UsedInAttribute] + + for childNode in fileNode.childNodes: + if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo": + if childNode.getAttribute("SFType") == "VHDL2008": + vhdlFile.VHDLVersion = VHDLVersion.VHDL2008 + else: + vhdlFile.VHDLVersion = VHDLVersion.VHDL93 + + for fileAttribute in childNode.childNodes: + if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr": + if fileAttribute.getAttribute("Name") == "Library": + libraryName = fileAttribute.getAttribute("Val") + vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName) + elif fileAttribute.getAttribute("Val") == "UsedIn": + usedInAttr.append(fileAttribute.getAttribute("Val")) + + def _ParseDefaultFile(self, _, path, fileset) -> None: + File(path, fileSet=fileset) + + def _ParseXDCFile(self, _, path, fileset) -> None: + XDCConstraintFile(path, fileSet=fileset) + + def _ParseVerilogFile(self, _, path, fileset) -> None: + VerilogSourceFile(path, fileSet=fileset) + + def _ParseXCIFile(self, _, path, fileset) -> None: + IPCoreInstantiationFile(path, fileSet=fileset) + + def _ParseFileSetConfig(self, fileNode, fileset) -> None: + for option in fileNode.childNodes: + if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option": + if option.getAttribute("Name") == "TopModule": + fileset.TopLevel = option.getAttribute("Val") + + +@export +class XDCConstraintFile(ConstraintFile, SDCContent): + """A Vivado constraint file (Xilinx Design Constraints; ``*.xdc``).""" + + +@export +class IPCoreDescriptionFile(XMLFile): + pass + + +@export +class IPCoreInstantiationFile(XMLFile): + """A Vivado IP core instantiation file (Xilinx IPCore Instance; ``*.xci``).""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""A vendor specific package for Xilinx.""" + |
+
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+# ==================================================================================================================== # +# _____ ____ _ _ ____ _ _ __ __ _ _ # +# _ __ _ _| ____| _ \ / \ / \ | _ \ _ __ ___ (_) ___ ___| |_| \/ | ___ __| | ___| | # +# | '_ \| | | | _| | | | |/ _ \ / _ \ | |_) | '__/ _ \| |/ _ \/ __| __| |\/| |/ _ \ / _` |/ _ \ | # +# | |_) | |_| | |___| |_| / ___ \ / ___ \ _| __/| | | (_) | | __/ (__| |_| | | | (_) | (_| | __/ | # +# | .__/ \__, |_____|____/_/ \_\/_/ \_(_)_| |_| \___// |\___|\___|\__|_| |_|\___/ \__,_|\___|_| # +# |_| |___/ |__/ # +# ==================================================================================================================== # +# Authors: # +# Patrick Lehmann # +# # +# License: # +# ==================================================================================================================== # +# Copyright 2017-2024 Patrick Lehmann - Boetzingen, Germany # +# Copyright 2014-2016 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture # +# # +# Licensed under the Apache License, Version 2.0 (the "License"); # +# you may not use this file except in compliance with the License. # +# You may obtain a copy of the License at # +# # +# http://www.apache.org/licenses/LICENSE-2.0 # +# # +# Unless required by applicable law or agreed to in writing, software # +# distributed under the License is distributed on an "AS IS" BASIS, # +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # +# See the License for the specific language governing permissions and # +# limitations under the License. # +# # +# SPDX-License-Identifier: Apache-2.0 # +# ==================================================================================================================== # +# +"""An abstract model of EDA tool projects.""" +__author__ = "Patrick Lehmann" +__email__ = "Paebbels@gmail.com" +__copyright__ = "2014-2024, Patrick Lehmann, Unai Martinez-Corral" +__license__ = "Apache License, Version 2.0" +__version__ = "0.5.0" +__keywords__ = ["eda project", "model", "abstract", "xilinx", "vivado", "osvvm", "file set", "file group", "test bench", "test harness"] + +from os.path import relpath as path_relpath +from pathlib import Path as pathlib_Path +from sys import version_info +from typing import Dict, Union, Optional as Nullable, List, Iterable, Generator, Tuple, Any as typing_Any, Type, Set, Any + +from pyTooling.Common import getFullyQualifiedName +from pyTooling.Decorators import export +from pyTooling.MetaClasses import ExtendedType +from pyTooling.Graph import Graph, Vertex +from pySVModel import SystemVerilogVersion +from pyVHDLModel import VHDLVersion +from pySystemRDLModel import SystemRDLVersion + + +@export +class Attribute(metaclass=ExtendedType): + KEY: str + VALUE_TYPE: typing_Any + + @staticmethod + def resolve(obj: typing_Any, key: Type['Attribute']): + if isinstance(obj, File): + return obj._fileSet[key] + elif isinstance(obj, FileSet): + return obj._design[key] + elif isinstance(obj, Design): + return obj._project[key] + else: + raise Exception("Resolution error") + + +@export +class FileType(ExtendedType): + """ + A :term:`meta-class` to construct *FileType* classes. + + Modifications done by this meta-class: + * Register all classes of type :class:`FileType` or derived variants in a class field :attr:`FileType.FileTypes` in this meta-class. + """ + + FileTypes: Dict[str, 'FileType'] = {} #: Dictionary of all classes of type :class:`FileType` or derived variants + Any: 'FileType' + + def __init__(cls, name: str, bases: Tuple[type, ...], dictionary: Dict[str, typing_Any], **kwargs): + super().__init__(name, bases, dictionary, **kwargs) + cls.Any = cls + + def __new__(cls, className, baseClasses, classMembers: Dict, *args, **kwargs): + fileType = super().__new__(cls, className, baseClasses, classMembers, *args, **kwargs) + cls.FileTypes[className] = fileType + return fileType + + def __getattr__(cls, item) -> 'FileType': + if item[:2] != "__" and item[-2:] != "__": + return cls.FileTypes[item] + else: + return super().__getattribute__(item) + + def __contains__(cls, item) -> bool: + return issubclass(item, cls) + + +@export +class File(metaclass=FileType, slots=True): + """ + A :term:`File` represents a file in a design. This :term:`base-class` is used + for all derived file classes. + + A file can be created standalone and later associated to a fileset, design and + project. Or a fileset, design and/or project can be associated immediately + while creating a file. + + :arg path: Relative or absolute path to the file. + :arg project: Project the file is associated with. + :arg design: Design the file is associated with. + :arg fileSet: Fileset the file is associated with. + """ + + _path: pathlib_Path + _fileType: 'FileType' + _project: Nullable['Project'] + _design: Nullable['Design'] + _fileSet: Nullable['FileSet'] + _attributes: Dict[Type[Attribute], typing_Any] + + def __init__( + self, + path: pathlib_Path, + project: Nullable["Project"] = None, + design: Nullable["Design"] = None, + fileSet: Nullable["FileSet"] = None + ): + self._fileType = getattr(FileTypes, self.__class__.__name__) + self._path = path + if project is not None: + self._project = project + self._design = design + if fileSet is not None: + self.FileSet = fileSet + elif design is not None: + self._project = design._project + self._design = design + self.FileSet = design.DefaultFileSet if fileSet is None else fileSet + elif fileSet is not None: + design = fileSet._design + if design is not None: + self._project = design._project + else: + self._project = None + self._design = design + self.FileSet = fileSet + else: + self._project = None + self._design = None + self._fileSet = None + + self._attributes = {} + self._registerAttributes() + + def _registerAttributes(self) -> None: + pass + + @property + def FileType(self) -> 'FileType': + """Read-only property to return the file type of this file.""" + return self._fileType + + @property + def Path(self) -> pathlib_Path: + """Read-only property returning the path of this file.""" + return self._path + + # TODO: setter? + + @property + def ResolvedPath(self) -> pathlib_Path: + """Read-only property returning the resolved path of this file.""" + if self._path.is_absolute(): + return self._path.resolve() + elif self._fileSet is not None: + path = (self._fileSet.ResolvedPath / self._path).resolve() + + if path.is_absolute(): + return path + else: + # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath + return pathlib_Path(path_relpath(path, pathlib_Path.cwd())) + else: + # TODO: message and exception type + raise Exception("") + + @property + def Project(self) -> Nullable['Project']: + """Property setting or returning the project this file is used in.""" + return self._project + + @Project.setter + def Project(self, value: 'Project') -> None: + self._project = value + + if self._fileSet is None: + self._project.DefaultDesign.DefaultFileSet.AddFile(self) + + @property + def Design(self) -> Nullable['Design']: + """Property setting or returning the design this file is used in.""" + return self._design + + @Design.setter + def Design(self, value: 'Design') -> None: + self._design = value + + if self._fileSet is None: + self._design.DefaultFileSet.AddFile(self) + + if self._project is None: + self._project = value._project + elif self._project is not value._project: + raise Exception("The design's project is not identical to the already assigned project.") + + @property + def FileSet(self) -> Nullable['FileSet']: + """Property setting or returning the fileset this file is used in.""" + return self._fileSet + + @FileSet.setter + def FileSet(self, value: 'FileSet') -> None: + self._fileSet = value + value._files.append(self) + + def Validate(self) -> None: + """Validate this file.""" + if self._path is None: + raise Exception("Validation: File has no path.") + try: + path = self.ResolvedPath + except Exception as ex: + raise Exception(f"Validation: File '{self._path}' could not compute resolved path.") from ex + if not path.exists(): + raise Exception(f"Validation: File '{self._path}' (={path}) does not exist.") + if not path.is_file(): + raise Exception(f"Validation: File '{self._path}' (={path}) is not a file.") + + if self._fileSet is None: + raise Exception(f"Validation: File '{self._path}' has no fileset.") + if self._design is None: + raise Exception(f"Validation: File '{self._path}' has no design.") + if self._project is None: + raise Exception(f"Validation: File '{self._path}' has no project.") + + def __len__(self) -> int: + """ + Returns number of attributes set on this file. + + :returns: The number if attributes set on this file. + """ + return len(self._attributes) + + def __getitem__(self, key: Type[Attribute]) -> Any: + """Index access for returning attributes on this file. + + :param key: The attribute type. + :returns: The attribute's value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + try: + return self._attributes[key] + except KeyError: + try: + return key.resolve(self, key) + except KeyError: + attribute = key() + self._attributes[key] = attribute + return attribute + + def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: + """ + Index access for adding or setting attributes on this file. + + :param key: The attribute type. + :param value: The attributes value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + self._attributes[key] = value + + def __delitem__(self, key: Type[Attribute]) -> None: + """ + Index access for deleting attributes on this file. + + :param key: The attribute type. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + del self._attributes[key] + + def __str__(self) -> str: + return f"{self._path}" + + +FileTypes = File + + +@export +class HumanReadableContent(metaclass=ExtendedType, mixin=True): + """A file type representing human-readable contents.""" + + +@export +class XMLContent(HumanReadableContent, mixin=True): + """A file type representing XML contents.""" + + +@export +class YAMLContent(HumanReadableContent, mixin=True): + """A file type representing YAML contents.""" + + +@export +class JSONContent(HumanReadableContent, mixin=True): + """A file type representing JSON contents.""" + + +@export +class INIContent(HumanReadableContent, mixin=True): + """A file type representing INI contents.""" + + +@export +class TOMLContent(HumanReadableContent, mixin=True): + """A file type representing TOML contents.""" + + +@export +class TCLContent(HumanReadableContent, mixin=True): + """A file type representing content in TCL code.""" + + +@export +class SDCContent(TCLContent, mixin=True): + """A file type representing contents as Synopsys Design Constraints (SDC).""" + + +@export +class PythonContent(HumanReadableContent, mixin=True): + """A file type representing contents as Python source code.""" + + +@export +class TextFile(File, HumanReadableContent): + """A text file (``*.txt``).""" + + +@export +class LogFile(File, HumanReadableContent): + """A log file (``*.log``).""" + + +@export +class XMLFile(File, XMLContent): + """An XML file (``*.xml``).""" + + +@export +class SourceFile(File): + """Base-class of all source files.""" + + +@export +class HDLSourceFile(SourceFile): + """Base-class of all HDL source files.""" + + +@export +class RDLSourceFile(SourceFile): + """Base-class of all RDL source files.""" + + +@export +class NetlistFile(SourceFile): + """Base-class of all netlist source files.""" + + +@export +class EDIFNetlistFile(NetlistFile): + """Netlist file in EDIF (Electronic Design Interchange Format).""" + + +@export +class TCLSourceFile(SourceFile, TCLContent): + """A TCL source file.""" + + +@export +class VHDLSourceFile(HDLSourceFile, HumanReadableContent): + """ + A VHDL source file (of any language version). + + :arg path: Relative or absolute path to the file. + :arg vhdlLibrary: VHDLLibrary this VHDL source file is associated wih. + :arg vhdlVersion: VHDLVersion this VHDL source file is associated wih. + :arg project: Project the file is associated with. + :arg design: Design the file is associated with. + :arg fileSet: Fileset the file is associated with. + """ + + _vhdlLibrary: Nullable['VHDLLibrary'] + _vhdlVersion: VHDLVersion + + def __init__(self, path: pathlib_Path, vhdlLibrary: Union[str, 'VHDLLibrary'] = None, vhdlVersion: Nullable[VHDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None): + super().__init__(path, project, design, fileSet) + + if isinstance(vhdlLibrary, str): + if design is not None: + try: + vhdlLibrary = design.VHDLLibraries[vhdlLibrary] + except KeyError as ex: + raise Exception(f"VHDL library '{vhdlLibrary}' not found in design '{design.Name}'.") from ex + elif project is not None: + try: + vhdlLibrary = project.DefaultDesign.VHDLLibraries[vhdlLibrary] + except KeyError as ex: + raise Exception(f"VHDL library '{vhdlLibrary}' not found in default design '{project.DefaultDesign.Name}'.") from ex + else: + raise Exception(f"Can't lookup VHDL library because neither 'project' nor 'design' is given as a parameter.") + elif isinstance(vhdlLibrary, VHDLLibrary): + self._vhdlLibrary = vhdlLibrary + vhdlLibrary.AddFile(self) + elif vhdlLibrary is None: + self._vhdlLibrary = None + else: + ex = TypeError(f"Parameter 'vhdlLibrary' is neither a 'str' nor 'VHDLibrary'.") + if version_info >= (3, 11): # pragma: no cover + ex.add_note(f"Got type '{getFullyQualifiedName(vhdlLibrary)}'.") + raise ex + + self._vhdlVersion = vhdlVersion + + def Validate(self) -> None: + """Validate this VHDL source file.""" + super().Validate() + + try: + _ = self.VHDLLibrary + except Exception as ex: + raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLLibrary assigned.") from ex + try: + _ = self.VHDLVersion + except Exception as ex: + raise Exception(f"Validation: VHDLSourceFile '{self._path}' (={self.ResolvedPath}) has no VHDLVersion assigned.") from ex + + @property + def VHDLLibrary(self) -> 'VHDLLibrary': + """Property setting or returning the VHDL library this VHDL source file is used in.""" + if self._vhdlLibrary is not None: + return self._vhdlLibrary + elif self._fileSet is not None: + return self._fileSet.VHDLLibrary + else: + raise Exception("VHDLLibrary was neither set locally nor globally.") + + @VHDLLibrary.setter + def VHDLLibrary(self, value: 'VHDLLibrary') -> None: + self._vhdlLibrary = value + value._files.append(self) + + @property + def VHDLVersion(self) -> VHDLVersion: + """Property setting or returning the VHDL version this VHDL source file is used in.""" + if self._vhdlVersion is not None: + return self._vhdlVersion + elif self._fileSet is not None: + return self._fileSet.VHDLVersion + else: + raise Exception("VHDLVersion was neither set locally nor globally.") + + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + self._vhdlVersion = value + + def __repr__(self) -> str: + return f"<VHDL file: '{self.ResolvedPath}'; lib: '{self.VHDLLibrary}'; version: {self.VHDLVersion}>" + + +class VerilogMixIn(metaclass=ExtendedType, mixin=True): + @property + def VerilogVersion(self) -> SystemVerilogVersion: + """Property setting or returning the Verilog version this Verilog source file is used in.""" + if self._version is not None: + return self._version + elif self._fileSet is not None: + return self._fileSet.VerilogVersion + else: + raise Exception("VerilogVersion was neither set locally nor globally.") + + @VerilogVersion.setter + def VerilogVersion(self, value: SystemVerilogVersion) -> None: + self._version = value + + +class SystemVerilogMixIn(metaclass=ExtendedType, mixin=True): + @property + def SVVersion(self) -> SystemVerilogVersion: + """Property setting or returning the SystemVerilog version this SystemVerilog source file is used in.""" + if self._version is not None: + return self._version + elif self._fileSet is not None: + return self._fileSet.SVVersion + else: + raise Exception("SVVersion was neither set locally nor globally.") + + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: + self._version = value + + +@export +class VerilogBaseFile(HDLSourceFile, HumanReadableContent): + _version: SystemVerilogVersion + + def __init__(self, path: pathlib_Path, version: Nullable[SystemVerilogVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None): + super().__init__(path, project, design, fileSet) + + self._version = version + + +@export +class VerilogSourceFile(VerilogBaseFile, VerilogMixIn): + """A Verilog source file (of any language version).""" + + +@export +class VerilogHeaderFile(VerilogBaseFile, VerilogMixIn): + """A Verilog header file (of any language version).""" + + +@export +class SystemVerilogBaseFile(VerilogBaseFile): + ... + + +@export +class SystemVerilogSourceFile(SystemVerilogBaseFile, SystemVerilogMixIn): + """A SystemVerilog source file (of any language version).""" + + +@export +class SystemVerilogHeaderFile(SystemVerilogBaseFile, SystemVerilogMixIn): + """A SystemVerilog header file (of any language version).""" + + +@export +class SystemRDLSourceFile(RDLSourceFile, HumanReadableContent): + """A SystemRDL source file (of any language version).""" + + _srdlVersion: SystemRDLVersion + + def __init__(self, path: pathlib_Path, srdlVersion: Nullable[SystemRDLVersion] = None, project: Nullable["Project"] = None, design: Nullable["Design"] = None, fileSet: Nullable["FileSet"] = None): + super().__init__(path, project, design, fileSet) + + self._srdlVersion = srdlVersion + + @property + def SystemRDLVersion(self) -> SystemRDLVersion: + """Property setting or returning the SystemRDL version this SystemRDL source file is used in.""" + if self._srdlVersion is not None: + return self._srdlVersion + elif self._fileSet is not None: + return self._fileSet.SRDLVersion + else: + raise Exception("SRDLVersion was neither set locally nor globally.") + + @SystemRDLVersion.setter + def SystemRDLVersion(self, value: SystemRDLVersion) -> None: + self._srdlVersion = value + + +@export +class PythonSourceFile(SourceFile, PythonContent): + """A Python source file.""" + + +# TODO: move to a Cocotb module +@export +class CocotbPythonFile(PythonSourceFile): + """A Python source file used by Cocotb.""" + + +@export +class ConstraintFile(File, HumanReadableContent): + """Base-class of all constraint files.""" + + +@export +class ProjectFile(File): + """Base-class of all tool-specific project files.""" + + +@export +class CSourceFile(SourceFile): + """Base-class of all ANSI-C source files.""" + + +@export +class CppSourceFile(SourceFile): + """Base-class of all ANSI-C++ source files.""" + + +@export +class SettingFile(File): + """Base-class of all tool-specific setting files.""" + + +@export +class SimulationAnalysisFile(File): + """Base-class of all tool-specific analysis files.""" + + +@export +class SimulationElaborationFile(File): + """Base-class of all tool-specific elaboration files.""" + + +@export +class SimulationStartFile(File): + """Base-class of all tool-specific simulation start-up files.""" + + +@export +class SimulationRunFile(File): + """Base-class of all tool-specific simulation run (execution) files.""" + + +@export +class WaveformConfigFile(File): + """Base-class of all tool-specific waveform configuration files.""" + + +@export +class WaveformDatabaseFile(File): + """Base-class of all tool-specific waveform database files.""" + + +@export +class WaveformExchangeFile(File): + """Base-class of all tool-independent waveform exchange files.""" + + +@export +class FileSet(metaclass=ExtendedType, slots=True): + """ + A :term:`FileSet` represents a group of files. Filesets can have sub-filesets. + + The order of insertion is preserved. A fileset can be created standalone and + later associated to another fileset, design and/or project. Or a fileset, + design and/or project can be associated immediately while creating the + fileset. + + :arg name: Name of this fileset. + :arg topLevel: Name of the fileset's toplevel. + :arg directory: Path of this fileset (absolute or relative to a parent fileset or design). + :arg project: Project the file is associated with. + :arg design: Design the file is associated with. + :arg parent: Parent fileset if this fileset is nested. + :arg vhdlLibrary: Default VHDL library for files in this fileset, if not specified for the file itself. + :arg vhdlVersion: Default VHDL version for files in this fileset, if not specified for the file itself. + :arg verilogVersion: Default Verilog version for files in this fileset, if not specified for the file itself. + :arg svVersion: Default SystemVerilog version for files in this fileset, if not specified for the file itself. + :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself. + """ + + _name: str + _topLevel: Nullable[str] + _project: Nullable['Project'] + _design: Nullable['Design'] + _directory: pathlib_Path + _parent: Nullable['FileSet'] + _fileSets: Dict[str, 'FileSet'] + _files: List[File] + _set: Set + _attributes: Dict[Type[Attribute], typing_Any] + _vhdlLibraries: Dict[str, 'VHDLLibrary'] + _vhdlLibrary: 'VHDLLibrary' + _vhdlVersion: VHDLVersion + _verilogVersion: SystemVerilogVersion + _svVersion: SystemVerilogVersion + _srdlVersion: SystemRDLVersion + + def __init__( + self, + name: str, + topLevel: Nullable[str] = None, + directory: pathlib_Path = pathlib_Path("."), + project: Nullable["Project"] = None, + design: Nullable["Design"] = None, + parent: Nullable['FileSet'] = None, + vhdlLibrary: Union[str, 'VHDLLibrary'] = None, + vhdlVersion: Nullable[VHDLVersion] = None, + verilogVersion: Nullable[SystemVerilogVersion] = None, + svVersion: Nullable[SystemVerilogVersion] = None, + srdlVersion: Nullable[SystemRDLVersion] = None + ): + self._name = name + self._topLevel = topLevel + if project is not None: + self._project = project + self._design = design if design is not None else project.DefaultDesign + + elif design is not None: + self._project = design._project + self._design = design + else: + self._project = None + self._design = None + self._directory = directory + self._parent = parent + self._fileSets = {} + self._files = [] + self._set = set() + + if design is not None: + design._fileSets[name] = self + + self._attributes = {} + self._vhdlLibraries = {} + + # TODO: handle if vhdlLibrary is a string + self._vhdlLibrary = vhdlLibrary + self._vhdlVersion = vhdlVersion + self._verilogVersion = verilogVersion + self._svVersion = svVersion + self._srdlVersion = srdlVersion + + @property + def Name(self) -> str: + """Property setting or returning the fileset's name.""" + return self._name + + @Name.setter + def Name(self, value: str) -> None: + self._name = value + + @property + def TopLevel(self) -> str: + """Property setting or returning the fileset's toplevel.""" + return self._topLevel + + @TopLevel.setter + def TopLevel(self, value: str) -> None: + self._topLevel = value + + @property + def Project(self) -> Nullable['Project']: + """Property setting or returning the project this fileset is used in.""" + return self._project + + @Project.setter + def Project(self, value: 'Project') -> None: + self._project = value + + @property + def Design(self) -> Nullable['Design']: + """Property setting or returning the design this fileset is used in.""" + if self._design is not None: + return self._design + elif self._parent is not None: + return self._parent.Design + else: + return None + # TODO: raise exception instead + # QUESTION: how to handle if design and parent is set? + + @Design.setter + def Design(self, value: 'Design') -> None: + self._design = value + if self._project is None: + self._project = value._project + elif self._project is not value._project: + raise Exception("The design's project is not identical to the already assigned project.") + + @property + def Directory(self) -> pathlib_Path: + """Property setting or returning the directory this fileset is located in.""" + return self._directory + + @Directory.setter + def Directory(self, value: pathlib_Path) -> None: + self._directory = value + + @property + def ResolvedPath(self) -> pathlib_Path: + """Read-only property returning the resolved path of this fileset.""" + if self._directory.is_absolute(): + return self._directory.resolve() + else: + if self._parent is not None: + directory = self._parent.ResolvedPath + elif self._design is not None: + directory = self._design.ResolvedPath + elif self._project is not None: + directory = self._project.ResolvedPath + else: + # TODO: message and exception type + raise Exception("") + + directory = (directory / self._directory).resolve() + if directory.is_absolute(): + return directory + else: + # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath + return pathlib_Path(path_relpath(directory, pathlib_Path.cwd())) + + @property + def Parent(self) -> Nullable['FileSet']: + """Property setting or returning the parent fileset this fileset is used in.""" + return self._parent + + @Parent.setter + def Parent(self, value: 'FileSet') -> None: + self._parent = value + value._fileSets[self._name] = self + # TODO: check it it already exists + # QUESTION: make an Add fileset method? + + @property + def FileSets(self) -> Dict[str, 'FileSet']: + """Read-only property returning the dictionary of sub-filesets.""" + return self._fileSets + + def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[bool, str, 'FileSet'] = None) -> Generator[File, None, None]: + """ + Method returning the files of this fileset. + + :arg fileType: A filter for file types. Default: ``Any``. + :arg fileSet: Specifies how to handle sub-filesets. + """ + if fileSet is False: + for file in self._files: + if file.FileType in fileType: + yield file + elif fileSet is None: + for fileSet in self._fileSets.values(): + for file in fileSet.Files(fileType): + yield file + for file in self._files: + if file.FileType in fileType: + yield file + else: + if isinstance(fileSet, str): + fileSetName = fileSet + try: + fileSet = self._fileSets[fileSetName] + except KeyError as ex: + raise Exception(f"Fileset {fileSetName} not bound to fileset {self.Name}.") from ex + elif not isinstance(fileSet, FileSet): + raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.") + + for file in fileSet.Files(fileType): + yield file + + def AddFileSet(self, fileSet: "FileSet") -> None: + """ + Method to add a single sub-fileset to this fileset. + + :arg fileSet: A fileset to add to this fileset as sub-fileset. + """ + if not isinstance(fileSet, FileSet): + raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.") + elif fileSet in self._fileSets: + raise Exception("Sub-fileset already contains this fileset.") + elif fileSet.Name in self._fileSets.keys(): + raise Exception(f"Fileset already contains a sub-fileset named '{fileSet.Name}'.") + + self._fileSets[fileSet.Name] = fileSet + fileSet._parent = self + + def AddFileSets(self, fileSets: Iterable["FileSet"]) -> None: + """ + Method to add a multiple sub-filesets to this fileset. + + :arg fileSets: An iterable of filesets to add each to the fileset. + """ + for fileSet in fileSets: + self.AddFileSet(fileSet) + + @property + def FileSetCount(self) -> int: + """Returns number of file sets excl. sub-filesets.""" + return len(self._fileSets) + + @property + def TotalFileSetCount(self) -> int: + """Returns number of file sets incl. sub-filesets.""" + fileSetCount = len(self._fileSets) + for fileSet in self._fileSets.values(): + fileSetCount += fileSet.TotalFileSetCount + + return fileSetCount + + def AddFile(self, file: File) -> None: + """ + Method to add a single file to this fileset. + + :arg file: A file to add to this fileset. + """ + if not isinstance(file, File): + raise TypeError("Parameter 'file' is not of type ProjectModel.File.") + elif file._fileSet is not None: + ex = ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}'.") + if version_info >= (3, 11): # pragma: no cover + ex.add_note(f"A file can't be assigned to another fileset.") + raise ex + elif file in self._set: + ex = ValueError(f"File '{file.Path!s}' is already part of this fileset.") + if version_info >= (3, 11): # pragma: no cover + ex.add_note(f"A file can't be added twice to a fileset.") + raise ex + + self._files.append(file) + self._set.add(file) + file._fileSet = self + + def AddFiles(self, files: Iterable[File]) -> None: + """ + Method to add a multiple files to this fileset. + + :arg files: An iterable of files to add each to the fileset. + """ + for file in files: + self.AddFile(file) + + @property + def FileCount(self) -> int: + """Returns number of files excl. sub-filesets.""" + return len(self._files) + + @property + def TotalFileCount(self) -> int: + """Returns number of files incl. the files in sub-filesets.""" + fileCount = len(self._files) + for fileSet in self._fileSets.values(): + fileCount += fileSet.FileCount + + return fileCount + + def Validate(self) -> None: + """Validate this fileset.""" + if self._name is None or self._name == "": + raise Exception("Validation: FileSet has no name.") + + if self._directory is None: + raise Exception(f"Validation: FileSet '{self._name}' has no directory.") + try: + path = self.ResolvedPath + except Exception as ex: + raise Exception(f"Validation: FileSet '{self._name}' could not compute resolved path.") from ex + if not path.exists(): + raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' does not exist.") + if not path.is_dir(): + raise Exception(f"Validation: FileSet '{self._name}'s directory '{path}' is not a directory.") + + if self._design is None: + raise Exception(f"Validation: FileSet '{self._directory}' has no design.") + if self._project is None: + raise Exception(f"Validation: FileSet '{self._directory}' has no project.") + + for fileSet in self._fileSets.values(): + fileSet.Validate() + for file in self._files: + file.Validate() + + def GetOrCreateVHDLLibrary(self, name) -> 'VHDLLibrary': + if name in self._vhdlLibraries: + return self._vhdlLibraries[name] + elif name in self._design._vhdlLibraries: + library = self._design._vhdlLibraries[name] + self._vhdlLibraries[name] = library + return library + else: + library = VHDLLibrary(name, design=self._design, vhdlVersion=self._vhdlVersion) + self._vhdlLibraries[name] = library + return library + + @property + def VHDLLibrary(self) -> 'VHDLLibrary': + """Property setting or returning the VHDL library of this fileset.""" + if self._vhdlLibrary is not None: + return self._vhdlLibrary + elif self._parent is not None: + return self._parent.VHDLLibrary + elif self._design is not None: + return self._design.VHDLLibrary + else: + raise Exception("VHDLLibrary was neither set locally nor globally.") + + @VHDLLibrary.setter + def VHDLLibrary(self, value: 'VHDLLibrary') -> None: + self._vhdlLibrary = value + + @property + def VHDLVersion(self) -> VHDLVersion: + """Property setting or returning the VHDL version of this fileset.""" + if self._vhdlVersion is not None: + return self._vhdlVersion + elif self._parent is not None: + return self._parent.VHDLVersion + elif self._design is not None: + return self._design.VHDLVersion + else: + raise Exception("VHDLVersion was neither set locally nor globally.") + + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + self._vhdlVersion = value + + @property + def VerilogVersion(self) -> SystemVerilogVersion: + """Property setting or returning the Verilog version of this fileset.""" + if self._verilogVersion is not None: + return self._verilogVersion + elif self._parent is not None: + return self._parent.VerilogVersion + elif self._design is not None: + return self._design.VerilogVersion + else: + raise Exception("VerilogVersion was neither set locally nor globally.") + + @VerilogVersion.setter + def VerilogVersion(self, value: SystemVerilogVersion) -> None: + self._verilogVersion = value + + @property + def SVVersion(self) -> SystemVerilogVersion: + """Property setting or returning the SystemVerilog version of this fileset.""" + if self._svVersion is not None: + return self._svVersion + elif self._parent is not None: + return self._parent.SVVersion + elif self._design is not None: + return self._design.SVVersion + else: + raise Exception("SVVersion was neither set locally nor globally.") + + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: + self._svVersion = value + + @property + def SRDLVersion(self) -> SystemRDLVersion: + if self._srdlVersion is not None: + return self._srdlVersion + elif self._parent is not None: + return self._parent.SRDLVersion + elif self._design is not None: + return self._design.SRDLVersion + else: + raise Exception("SRDLVersion was neither set locally nor globally.") + + @SRDLVersion.setter + def SRDLVersion(self, value: SystemRDLVersion) -> None: + self._srdlVersion = value + + def __len__(self) -> int: + """ + Returns number of attributes set on this fileset. + + :returns: The number if attributes set on this fileset. + """ + return len(self._attributes) + + def __getitem__(self, key: Type[Attribute]) -> Any: + """Index access for returning attributes on this fileset. + + :param key: The attribute type. + :returns: The attribute's value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + try: + return self._attributes[key] + except KeyError: + return key.resolve(self, key) + + def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: + """ + Index access for adding or setting attributes on this fileset. + + :param key: The attribute type. + :param value: The attributes value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + self._attributes[key] = value + + def __delitem__(self, key: Type[Attribute]) -> None: + """ + Index access for deleting attributes on this fileset. + + :param key: The attribute type. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + del self._attributes[key] + + def __str__(self) -> str: + """Returns the fileset's name.""" + return self._name + + +@export +class VHDLLibrary(metaclass=ExtendedType, slots=True): + """ + A :term:`VHDLLibrary` represents a group of VHDL source files compiled into the same VHDL library. + + :arg name: The VHDL libraries' name. + :arg project: Project the VHDL library is associated with. + :arg design: Design the VHDL library is associated with. + :arg vhdlVersion: Default VHDL version for files in this VHDL library, if not specified for the file itself. + """ + + _name: str + _project: Nullable['Project'] + _design: Nullable['Design'] + _files: List[File] + _vhdlVersion: VHDLVersion + + _dependencyNode: Vertex + + def __init__( + self, + name: str, + project: Nullable["Project"] = None, + design: Nullable["Design"] = None, + vhdlVersion: Nullable[VHDLVersion] = None + ): + self._name = name + if project is not None: + self._project = project + self._design = project._defaultDesign if design is None else design + self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph) + + if name in self._design._vhdlLibraries: + raise Exception(f"Library '{name}' already in design '{self._design.Name}'.") + else: + self._design._vhdlLibraries[name] = self + + elif design is not None: + self._project = design._project + self._design = design + self._dependencyNode = Vertex(value=self, graph=design._vhdlLibraryDependencyGraph) + + if name in design._vhdlLibraries: + raise Exception(f"Library '{name}' already in design '{design.Name}'.") + else: + design._vhdlLibraries[name] = self + + else: + self._project = None + self._design = None + self._dependencyNode = None + + self._files = [] + self._vhdlVersion = vhdlVersion + + @property + def Name(self) -> str: + return self._name + + @property + def Project(self) -> Nullable['Project']: + """Property setting or returning the project this VHDL library is used in.""" + return self._project + + @Project.setter + def Project(self, value: 'Project') -> None: + if not isinstance(value, Project): + raise TypeError("Parameter 'value' is not of type 'Project'.") + + if value is None: + # TODO: unlink VHDLLibrary from project + self._project = None + else: + self._project = value + if self._design is None: + self._design = value._defaultDesign + + @property + def Design(self) -> Nullable['Design']: + """Property setting or returning the design this VHDL library is used in.""" + return self._design + + @Design.setter + def Design(self, value: 'Design') -> None: + if not isinstance(value, Design): + raise TypeError("Parameter 'value' is not of type 'Design'.") + + if value is None: + # TODO: unlink VHDLLibrary from design + self._design = None + else: + if self._design is None: + self._design = value + self._dependencyNode = Vertex(value=self, graph=self._design._vhdlLibraryDependencyGraph) + elif self._design is not value: + # TODO: move VHDLLibrary to other design + # TODO: create new vertex in dependency graph and remove vertex from old graph + self._design = value + else: + pass + + if self._project is None: + self._project = value._project + elif self._project is not value._project: + raise Exception("The design's project is not identical to the already assigned project.") + + @property + def Files(self) -> Generator[File, None, None]: + """Read-only property to return all files in this VHDL library.""" + for file in self._files: + yield file + + @property + def VHDLVersion(self) -> VHDLVersion: + """Property setting or returning the VHDL version of this VHDL library.""" + if self._vhdlVersion is not None: + return self._vhdlVersion + elif self._design is not None: + return self._design.VHDLVersion + else: + raise Exception("VHDLVersion is not set on VHDLLibrary nor parent object.") + + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + self._vhdlVersion = value + + def AddDependency(self, library: 'VHDLLibrary') -> None: + library.parent = self + + def AddFile(self, vhdlFile: VHDLSourceFile) -> None: + if not isinstance(vhdlFile, VHDLSourceFile): + ex = TypeError(f"Parameter 'vhdlFile' is not a 'VHDLSourceFile'.") + if version_info >= (3, 11): # pragma: no cover + ex.add_note(f"Got type '{getFullyQualifiedName(vhdlFile)}'.") + raise ex + + self._files.append(vhdlFile) + + def AddFiles(self, vhdlFiles: Iterable[VHDLSourceFile]) -> None: + for vhdlFile in vhdlFiles: + if not isinstance(vhdlFile, VHDLSourceFile): + raise TypeError(f"Item '{vhdlFile}' in parameter 'vhdlFiles' is not a 'VHDLSourceFile'.") + + self._files.append(vhdlFile) + + @property + def FileCount(self) -> int: + """Returns number of files.""" + return len(self._files) + + def __len__(self) -> int: + """ + Returns number of attributes set on this VHDL library. + + :returns: The number if attributes set on this VHDL library. + """ + return len(self._attributes) + + def __getitem__(self, key: Type[Attribute]) -> Any: + """Index access for returning attributes on this VHDL library. + + :param key: The attribute type. + :returns: The attribute's value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + try: + return self._attributes[key] + except KeyError: + return key.resolve(self, key) + + def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: + """ + Index access for adding or setting attributes on this VHDL library. + + :param key: The attribute type. + :param value: The attributes value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + self._attributes[key] = value + + def __delitem__(self, key: Type[Attribute]) -> None: + """ + Index access for deleting attributes on this VHDL library. + + :param key: The attribute type. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + del self._attributes[key] + + def __str__(self) -> str: + """Returns the VHDL library's name.""" + return self._name + + +@export +class Design(metaclass=ExtendedType, slots=True): + """ + A :term:`Design` represents a group of filesets and the source files therein. + + Each design contains at least one fileset - the :term:`default fileset`. For + designs with VHDL source files, a independent `VHDLLibraries` overlay structure + exists. + + :arg name: The design's name. + :arg topLevel: Name of the design's toplevel. + :arg directory: Path of this design (absolute or relative to the project). + :arg project: Project the design is associated with. + :arg vhdlVersion: Default VHDL version for files in this design, if not specified for the file itself. + :arg verilogVersion: Default Verilog version for files in this design, if not specified for the file itself. + :arg svVersion: Default SystemVerilog version for files in this design, if not specified for the file itself. + :arg srdlVersion: Default SystemRDL version for files in this fileset, if not specified for the file itself. + """ + + _name: str + _topLevel: Nullable[str] + _project: Nullable['Project'] + _directory: pathlib_Path + _fileSets: Dict[str, FileSet] + _defaultFileSet: Nullable[FileSet] + _attributes: Dict[Type[Attribute], typing_Any] + + _vhdlLibraries: Dict[str, VHDLLibrary] + _vhdlVersion: VHDLVersion + _verilogVersion: SystemVerilogVersion + _svVersion: SystemVerilogVersion + _srdlVersion: SystemRDLVersion + _externalVHDLLibraries: List + + _vhdlLibraryDependencyGraph: Graph + _fileDependencyGraph: Graph + + def __init__( + self, + name: str, + topLevel: Nullable[str] = None, + directory: pathlib_Path = pathlib_Path("."), + project: Nullable["Project"] = None, + vhdlVersion: Nullable[VHDLVersion] = None, + verilogVersion: Nullable[SystemVerilogVersion] = None, + svVersion: Nullable[SystemVerilogVersion] = None, + srdlVersion: Nullable[SystemRDLVersion] = None + ): + self._name = name + self._topLevel = topLevel + self._project = project + if project is not None: + project._designs[name] = self + self._directory = directory + self._fileSets = {} + self._defaultFileSet = FileSet("default", project=project, design=self) + self._attributes = {} + self._vhdlLibraries = {} + self._vhdlVersion = vhdlVersion + self._verilogVersion = verilogVersion + self._svVersion = svVersion + self._srdlVersion = srdlVersion + self._externalVHDLLibraries = [] + + self._vhdlLibraryDependencyGraph = Graph() + self._fileDependencyGraph = Graph() + + @property + def Name(self) -> str: + """Property setting or returning the design's name.""" + return self._name + + @Name.setter + def Name(self, value: str) -> None: + self._name = value + + @property + def TopLevel(self) -> str: + """Property setting or returning the fileset's toplevel.""" + return self._topLevel + + @TopLevel.setter + def TopLevel(self, value: str) -> None: + self._topLevel = value + + @property + def Project(self) -> Nullable['Project']: + """Property setting or returning the project this design is used in.""" + return self._project + + @Project.setter + def Project(self, value: 'Project') -> None: + self._project = value + + @property + def Directory(self) -> pathlib_Path: + """Property setting or returning the directory this design is located in.""" + return self._directory + + @Directory.setter + def Directory(self, value: pathlib_Path) -> None: + self._directory = value + + @property + def ResolvedPath(self) -> pathlib_Path: + """Read-only property returning the resolved path of this fileset.""" + if self._directory.is_absolute(): + return self._directory.resolve() + elif self._project is not None: + path = (self._project.ResolvedPath / self._directory).resolve() + + if path.is_absolute(): + return path + else: + # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath + return pathlib_Path(path_relpath(path, pathlib_Path.cwd())) + else: + # TODO: message and exception type + raise Exception("") + + @property + def DefaultFileSet(self) -> FileSet: + """Property setting or returning the default fileset of this design.""" + return self._defaultFileSet + + @DefaultFileSet.setter + def DefaultFileSet(self, value: Union[str, FileSet]) -> None: + if isinstance(value, str): + if value not in self._fileSets.keys(): + raise Exception(f"Fileset '{value}' is not in this design.") + + self._defaultFileSet = self._fileSets[value] + elif isinstance(value, FileSet): + if value not in self.FileSets: + raise Exception(f"Fileset '{value}' is not associated to this design.") + + self._defaultFileSet = value + else: + raise ValueError("Unsupported parameter type for 'value'.") + + # TODO: return generator with another method + @property + def FileSets(self) -> Dict[str, FileSet]: + """Read-only property returning the dictionary of filesets.""" + return self._fileSets + + def Files(self, fileType: FileType = FileTypes.Any, fileSet: Union[str, FileSet] = None) -> Generator[File, None, None]: + """ + Method returning the files of this design. + + :arg fileType: A filter for file types. Default: ``Any``. + :arg fileSet: Specifies if all files from all filesets (``fileSet=None``) are files from a single fileset are returned. + """ + if fileSet is None: + for fileSet in self._fileSets.values(): + for file in fileSet.Files(fileType): + yield file + else: + if isinstance(fileSet, str): + try: + fileSet = self._fileSets[fileSet] + except KeyError as ex: + raise Exception(f"Fileset {fileSet.Name} not bound to design {self.Name}.") from ex + elif not isinstance(fileSet, FileSet): + raise TypeError("Parameter 'fileSet' is not of type 'str' or 'FileSet' nor value 'None'.") + + for file in fileSet.Files(fileType): + yield file + + def Validate(self) -> None: + """Validate this design.""" + if self._name is None or self._name == "": + raise Exception("Validation: Design has no name.") + + if self._directory is None: + raise Exception(f"Validation: Design '{self._name}' has no directory.") + try: + path = self.ResolvedPath + except Exception as ex: + raise Exception(f"Validation: Design '{self._name}' could not compute resolved path.") from ex + if not path.exists(): + raise Exception(f"Validation: Design '{self._name}'s directory '{path}' does not exist.") + if not path.is_dir(): + raise Exception(f"Validation: Design '{self._name}'s directory '{path}' is not a directory.") + + if len(self._fileSets) == 0: + raise Exception(f"Validation: Design '{self._name}' has no fileset.") + try: + if self._defaultFileSet is not self._fileSets[self._defaultFileSet.Name]: + raise Exception(f"Validation: Design '{self._name}'s default fileset is the same as listed in filesets.") + except KeyError as ex: + raise Exception(f"Validation: Design '{self._name}'s default fileset is not in list of filesets.") from ex + if self._project is None: + raise Exception(f"Validation: Design '{self._path}' has no project.") + + for fileSet in self._fileSets.values(): + fileSet.Validate() + + @property + def VHDLLibraries(self) -> Dict[str, VHDLLibrary]: + return self._vhdlLibraries + + @property + def VHDLVersion(self) -> VHDLVersion: + if self._vhdlVersion is not None: + return self._vhdlVersion + elif self._project is not None: + return self._project.VHDLVersion + else: + raise Exception("VHDLVersion was neither set locally nor globally.") + + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + self._vhdlVersion = value + + @property + def VerilogVersion(self) -> SystemVerilogVersion: + if self._verilogVersion is not None: + return self._verilogVersion + elif self._project is not None: + return self._project.VerilogVersion + else: + raise Exception("VerilogVersion was neither set locally nor globally.") + + @VerilogVersion.setter + def VerilogVersion(self, value: SystemVerilogVersion) -> None: + self._verilogVersion = value + + @property + def SVVersion(self) -> SystemVerilogVersion: + if self._svVersion is not None: + return self._svVersion + elif self._project is not None: + return self._project.SVVersion + else: + raise Exception("SVVersion was neither set locally nor globally.") + + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: + self._svVersion = value + + @property + def SRDLVersion(self) -> SystemRDLVersion: + if self._srdlVersion is not None: + return self._srdlVersion + elif self._project is not None: + return self._project.SRDLVersion + else: + raise Exception("SRDLVersion was neither set locally nor globally.") + + @SRDLVersion.setter + def SRDLVersion(self, value: SystemRDLVersion) -> None: + self._srdlVersion = value + + @property + def ExternalVHDLLibraries(self) -> List: + return self._externalVHDLLibraries + + def AddFileSet(self, fileSet: FileSet) -> None: + if not isinstance(fileSet, FileSet): + raise ValueError("Parameter 'fileSet' is not of type ProjectModel.FileSet.") + elif fileSet in self._fileSets: + raise Exception("Design already contains this fileset.") + elif fileSet.Name in self._fileSets.keys(): + raise Exception(f"Design already contains a fileset named '{fileSet.Name}'.") + + self._fileSets[fileSet.Name] = fileSet + fileSet.Design = self + fileSet._parent = self + + def AddFileSets(self, fileSets: Iterable[FileSet]) -> None: + for fileSet in fileSets: + self.AddFileSet(fileSet) + + @property + def FileSetCount(self) -> int: + """Returns number of file sets excl. sub-filesets.""" + return len(self._fileSets) + + @property + def TotalFileSetCount(self) -> int: + """Returns number of file sets incl. sub-filesets.""" + fileSetCount = len(self._fileSets) + for fileSet in self._fileSets.values(): + fileSetCount += fileSet.TotalFileSetCount + + return fileSetCount + + def AddFile(self, file: File) -> None: + if file.FileSet is None: + self._defaultFileSet.AddFile(file) + else: + raise ValueError(f"File '{file.Path!s}' is already part of fileset '{file.FileSet.Name}' and can't be assigned via Design to a default fileset.") + + def AddFiles(self, files: Iterable[File]) -> None: + for file in files: + self.AddFile(file) + + def AddVHDLLibrary(self, vhdlLibrary: VHDLLibrary) -> None: + if vhdlLibrary.Name in self._vhdlLibraries: + if self._vhdlLibraries[vhdlLibrary.Name] is vhdlLibrary: + raise Exception(f"The VHDLLibrary '{vhdlLibrary.Name}' was already added to the design.") + else: + raise Exception(f"A VHDLLibrary with same name ('{vhdlLibrary.Name}') already exists for this design.") + + + def __len__(self) -> int: + """ + Returns number of attributes set on this design. + + :returns: The number if attributes set on this design. + """ + return len(self._attributes) + + def __getitem__(self, key: Type[Attribute]) -> Any: + """Index access for returning attributes on this design. + + :param key: The attribute type. + :returns: The attribute's value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + try: + return self._attributes[key] + except KeyError: + return key.resolve(self, key) + + def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: + """ + Index access for adding or setting attributes on this design. + + :param key: The attribute type. + :param value: The attributes value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + self._attributes[key] = value + + def __delitem__(self, key: Type[Attribute]) -> None: + """ + Index access for deleting attributes on this design. + + :param key: The attribute type. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + del self._attributes[key] + + def __str__(self) -> str: + return self._name + + +@export +class Project(metaclass=ExtendedType, slots=True): + """ + A :term:`Project` represents a group of designs and the source files therein. + + :arg name: The project's name. + :arg rootDirectory: Base-path to the project. + :arg vhdlVersion: Default VHDL version for files in this project, if not specified for the file itself. + :arg verilogVersion: Default Verilog version for files in this project, if not specified for the file itself. + :arg svVersion: Default SystemVerilog version for files in this project, if not specified for the file itself. + """ + + _name: str + _rootDirectory: pathlib_Path + _designs: Dict[str, Design] + _defaultDesign: Design + _attributes: Dict[Type[Attribute], typing_Any] + + _vhdlVersion: VHDLVersion + _verilogVersion: SystemVerilogVersion + _svVersion: SystemVerilogVersion + _srdlVersion: SystemRDLVersion + + def __init__( + self, + name: str, + rootDirectory: pathlib_Path = pathlib_Path("."), + vhdlVersion: Nullable[VHDLVersion] = None, + verilogVersion: Nullable[SystemVerilogVersion] = None, + svVersion: Nullable[SystemVerilogVersion] = None + ): + self._name = name + self._rootDirectory = rootDirectory + self._designs = {} + self._defaultDesign = Design("default", project=self) + self._attributes = {} + self._vhdlVersion = vhdlVersion + self._verilogVersion = verilogVersion + self._svVersion = svVersion + + @property + def Name(self) -> str: + """Property setting or returning the project's name.""" + return self._name + + @property + def RootDirectory(self) -> pathlib_Path: + """Property setting or returning the root directory this project is located in.""" + return self._rootDirectory + + @RootDirectory.setter + def RootDirectory(self, value: pathlib_Path) -> None: + self._rootDirectory = value + + @property + def ResolvedPath(self) -> pathlib_Path: + """Read-only property returning the resolved path of this fileset.""" + path = self._rootDirectory.resolve() + if self._rootDirectory.is_absolute(): + return path + else: + # WORKAROUND: https://stackoverflow.com/questions/67452690/pathlib-path-relative-to-vs-os-path-relpath + return pathlib_Path(path_relpath(path, pathlib_Path.cwd())) + + # TODO: return generator with another method + @property + def Designs(self) -> Dict[str, Design]: + return self._designs + + @property + def DefaultDesign(self) -> Design: + return self._defaultDesign + + def Validate(self) -> None: + """Validate this project.""" + if self._name is None or self._name == "": + raise Exception("Validation: Project has no name.") + + if self._rootDirectory is None: + raise Exception(f"Validation: Project '{self._name}' has no root directory.") + try: + path = self.ResolvedPath + except Exception as ex: + raise Exception(f"Validation: Project '{self._name}' could not compute resolved path.") from ex + if not path.exists(): + raise Exception(f"Validation: Project '{self._name}'s directory '{path}' does not exist.") + if not path.is_dir(): + raise Exception(f"Validation: Project '{self._name}'s directory '{path}' is not a directory.") + + if len(self._designs) == 0: + raise Exception(f"Validation: Project '{self._name}' has no design.") + try: + if self._defaultDesign is not self._designs[self._defaultDesign.Name]: + raise Exception(f"Validation: Project '{self._name}'s default design is the same as listed in designs.") + except KeyError as ex: + raise Exception(f"Validation: Project '{self._name}'s default design is not in list of designs.") from ex + + for design in self._designs.values(): + design.Validate() + + @property + def DesignCount(self) -> int: + """Returns number of designs.""" + return len(self._designs) + + @property + def VHDLVersion(self) -> VHDLVersion: + # TODO: check for None and return exception + return self._vhdlVersion + + @VHDLVersion.setter + def VHDLVersion(self, value: VHDLVersion) -> None: + self._vhdlVersion = value + + @property + def VerilogVersion(self) -> SystemVerilogVersion: + # TODO: check for None and return exception + return self._verilogVersion + + @VerilogVersion.setter + def VerilogVersion(self, value: SystemVerilogVersion) -> None: + self._verilogVersion = value + + @property + def SVVersion(self) -> SystemVerilogVersion: + # TODO: check for None and return exception + return self._svVersion + + @SVVersion.setter + def SVVersion(self, value: SystemVerilogVersion) -> None: + self._svVersion = value + + @property + def SRDLVersion(self) -> SystemRDLVersion: + # TODO: check for None and return exception + return self._srdlVersion + + @SRDLVersion.setter + def SRDLVersion(self, value: SystemRDLVersion) -> None: + self._srdlVersion = value + + def __len__(self) -> int: + """ + Returns number of attributes set on this project. + + :returns: The number if attributes set on this project. + """ + return len(self._attributes) + + def __getitem__(self, key: Type[Attribute]) -> Any: + """Index access for returning attributes on this project. + + :param key: The attribute type. + :returns: The attribute's value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + try: + return self._attributes[key] + except KeyError: + return key.resolve(self, key) + + def __setitem__(self, key: Type[Attribute], value: typing_Any) -> None: + """ + Index access for adding or setting attributes on this project. + + :param key: The attribute type. + :param value: The attributes value. + :raises TypeError: When parameter 'key' is not a subclass of Attribute. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + self._attributes[key] = value + + def __delitem__(self, key: Type[Attribute]) -> None: + """ + Index access for deleting attributes on this project. + + :param key: The attribute type. + """ + if not issubclass(key, Attribute): + raise TypeError("Parameter 'key' is not an 'Attribute'.") + + del self._attributes[key] + + def __str__(self) -> str: + return self._name + |
+
| File | +Imprecision | +Lines | +
|---|---|---|
| Total | +9.89% imprecise | +2749 LOC | +
| pyEDAA.ProjectModel | +10.44% imprecise | +1868 LOC | +
| pyEDAA.ProjectModel.Altera | +0.00% imprecise | +31 LOC | +
| pyEDAA.ProjectModel.Altera.Quartus | +0.00% imprecise | +44 LOC | +
| pyEDAA.ProjectModel.Attributes | +0.00% imprecise | +53 LOC | +
| pyEDAA.ProjectModel.GHDL | +0.00% imprecise | +39 LOC | +
| pyEDAA.ProjectModel.Intel | +0.00% imprecise | +31 LOC | +
| pyEDAA.ProjectModel.Intel.QuartusPrime | +0.00% imprecise | +44 LOC | +
| pyEDAA.ProjectModel.MentorGraphics | +0.00% imprecise | +31 LOC | +
| pyEDAA.ProjectModel.MentorGraphics.ModelSim | +0.00% imprecise | +49 LOC | +
| pyEDAA.ProjectModel.MentorGraphics.QuestaSim | +0.00% imprecise | +49 LOC | +
| pyEDAA.ProjectModel.OSVVM | +11.98% imprecise | +192 LOC | +
| pyEDAA.ProjectModel.VHDL | +0.00% imprecise | +0 LOC | +
| pyEDAA.ProjectModel.Verilog | +0.00% imprecise | +39 LOC | +
| pyEDAA.ProjectModel.Xilinx | +0.00% imprecise | +31 LOC | +
| pyEDAA.ProjectModel.Xilinx.ISE | +0.00% imprecise | +44 LOC | +
| pyEDAA.ProjectModel.Xilinx.Vivado | +26.47% imprecise | +204 LOC | +