diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
index 39fc55f1..e14a3e86 100644
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
@@ -85,7 +85,7 @@
   gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
   gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
   gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
-  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA)
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
   gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
   gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
 
@@ -93,6 +93,7 @@
   # USB/DP Combo PHY support flags and default values
   #
   gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
   gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
   gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
 
@@ -125,3 +126,9 @@
 
   # Splash screen logo
   $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+
+  # Hack to enable use of PCA9555 during PCIe initialization.
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
+  }
diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
index 6471b68a..8c130adc 100644
--- a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
@@ -373,6 +373,9 @@ PciePeReset (
   BOOLEAN Enable
   )
 {
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
   switch (Segment) {
   case PCIE_SEGMENT_PCIE30X4:
     GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1
@@ -383,6 +386,16 @@ PciePeReset (
   case PCIE_SEGMENT_PCIE20L1:
     break;
   case PCIE_SEGMENT_PCIE20L2:
+    Status = GetPca9555Protocol(&Pca95xxProtocol);
+    if (EFI_ERROR(Status)) {
+      DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status));
+    } else {
+      Pca95xxProtocol->GpioProtocol.Set(
+        &Pca95xxProtocol->GpioProtocol,
+        14, /* PCA_IO1_6 */
+        Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1
+      );
+    }
     break;
   }
 }
diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
new file mode 100644
index 00000000..6c686c31
--- /dev/null
+++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+
+# Hack to enable use of PCA9555 during PCIe initialization.
+[Depex]
+  gPca95xxProtocolGuid