diff --git a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl index 4c6e57df7..f442f735e 100644 --- a/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf index 5ac5e196a..b7df6737e 100644 --- a/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl index 60f61eb95..c0a9486c6 100644 --- a/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl @@ -19,6 +19,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl index ebd74ec02..3791e45ff 100644 --- a/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl index 7acff974c..9b5f85a70 100755 --- a/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl @@ -21,6 +21,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl index ba2376e52..41dd82fc5 100644 --- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl @@ -19,6 +19,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588S", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl index 9487e7be1..8eef9a0f7 100755 --- a/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl @@ -19,6 +19,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl index c6b57a891..0436e497d 100755 --- a/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl index 0ee6ea63a..0717f350c 100644 --- a/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl index d6d8c9446..eea386553 100644 --- a/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl @@ -19,6 +19,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl index 5883e91f8..a637e45ce 100644 --- a/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl index 8d4a6aef2..cd38ab4c2 100644 --- a/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl @@ -19,6 +19,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl index 366aca3c4..5df37a535 100755 --- a/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") // include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl index a691a731b..3ea82157f 100644 --- a/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl index 346a8deed..e797ab8f0 100755 --- a/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf index e262848a2..1cfeaf165 100644 --- a/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf +++ b/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf @@ -32,14 +32,6 @@ $(RK_COMMON_ACPI_DIR)/Mcfg.aslc $(RK_COMMON_ACPI_DIR)/Dbg2.aslc $(RK_COMMON_ACPI_DIR)/Pptt.aslc - $(RK_COMMON_ACPI_DIR)/Pcie3x4.asl - $(RK_COMMON_ACPI_DIR)/Pcie3x2.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l0.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l1.asl - $(RK_COMMON_ACPI_DIR)/Pcie2x1l2.asl - $(RK_COMMON_ACPI_DIR)/Sata0.asl - $(RK_COMMON_ACPI_DIR)/Sata1.asl - $(RK_COMMON_ACPI_DIR)/Sata2.asl [Packages] ArmPkg/ArmPkg.dec diff --git a/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl index 76550c6f3..340c3c8fc 100755 --- a/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl +++ b/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) { include ("Cpu.asl") + include ("Pcie.asl") + include ("Sata.asl") include ("Emmc.asl") include ("Sdhc.asl") include ("Dma.asl") diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc index 930ba829d..ce8449081 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc @@ -3,7 +3,7 @@ * PCI Express Memory-mapped Configuration Space base address description table (MCFG) * * Copyright (c) 2021, Jared McNeill - * Copyright (c) 2023, Mario Bălănică + * Copyright (c) 2024, Mario Bălănică * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -12,7 +12,7 @@ #include "AcpiTables.h" // -// MCFG may get patched by AcpiPlatformDxe. +// MCFG is patched by AcpiPlatformDxe. // RK3588_MCFG_TABLE Mcfg = { @@ -23,42 +23,79 @@ RK3588_MCFG_TABLE Mcfg = { EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION ), }, - { + { // Main config space { - 0x0000000900000000 + 0x8000, + PCIE_CFG_BASE (0), 0, // PciSegmentNumber 1, // PciBusMin 1, // PciBusMax 0 // Reserved }, { - 0x0000000940000000 + 0x8000, + PCIE_CFG_BASE (1), 1, // PciSegmentNumber 1, // PciBusMin 1, // PciBusMax 0 // Reserved }, { - 0x0000000980000000 + 0x8000, + PCIE_CFG_BASE (2), 2, // PciSegmentNumber 1, // PciBusMin 1, // PciBusMax 0 // Reserved }, { - 0x00000009C0000000 + 0x8000, + PCIE_CFG_BASE (3), 3, // PciSegmentNumber 1, // PciBusMin 1, // PciBusMax 0 // Reserved }, { - 0x0000000A00000000 + 0x8000, + PCIE_CFG_BASE (4), 4, // PciSegmentNumber 1, // PciBusMin 1, // PciBusMax 0 // Reserved } + }, + { // Root Port DBI config space (for Windows) + { + PCIE_DBI_BASE (0), + 0, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (1), + 1, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (2), + 2, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (3), + 3, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (4), + 4, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + } } }; diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl new file mode 100644 index 000000000..f54ec458c --- /dev/null +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl @@ -0,0 +1,125 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define PCIE_ROOT_COMPLEX(Segment, LegacyIrq) \ + Device (PCI ## Segment) { \ + Name (_HID, "PNP0A08") \ + Name (_CID, "PNP0A03") \ + Name (_CCA, 0) \ + Name (_UID, Segment) \ + Name (_SEG, Segment) \ + Method (_BBN) { \ + Return (PBMI) \ + } \ + Name (_STA, 0xF) \ + \ + Name (_PRT, Package() { \ + Package (4) { 0x0FFFF, 0, 0, LegacyIrq }, \ + Package (4) { 0x0FFFF, 1, 0, LegacyIrq }, \ + Package (4) { 0x0FFFF, 2, 0, LegacyIrq }, \ + Package (4) { 0x0FFFF, 3, 0, LegacyIrq } \ + }) \ + \ + Method (_CRS, 0, Serialized) { \ + Name (RBUF, ResourceTemplate () { \ + WORDBUSNUMBER_BUF (00, ResourceProducer) \ + DWORDMEMORY_BUF (01, ResourceProducer) \ + QWORDMEMORY_BUF (02, ResourceProducer) \ + QWORDIO_BUF (03, ResourceProducer) \ + }) \ + WORD_SET (00, PBMI, PBMA - PBMI + 1, 0) \ + DWORD_SET (01, PCIE_MEM_BASE (Segment), PCIE_MEM_SIZE, 0) \ + QWORD_SET (02, PCIE_MEM64_BASE (Segment), PCIE_MEM64_SIZE, 0) \ + QWORD_SET (03, PCIE_IO_BASE, PCIE_IO_SIZE, PCIE_IO_XLATE (Segment)) \ + Return (RBUF) \ + } \ + \ + Device (RES0) { \ + Name (_HID, "AMZN0001") \ + Name (_CID, "PNP0C02") \ + Name (_UID, Segment) \ + Method (_CRS, 0, Serialized) { \ + Name (RBUF, ResourceTemplate () { \ + QWORDMEMORY_BUF (00, ResourceProducer) \ + }) \ + QWORD_SET (00, PCIE_DBI_BASE (Segment), PCIE_DBI_SIZE, 0) \ + Return (RBUF) \ + } \ + } \ + \ + Device (RES1) { \ + Name (_HID, "PNP0C02") \ + Name (_UID, Segment + 1) \ + Method (_CRS, 0, Serialized) { \ + Name (RBUF, ResourceTemplate () { \ + QWORDMEMORY_BUF (00, ResourceProducer) \ + }) \ + QWORD_SET (00, PCIE_CFG_BASE (Segment), SIZE_256MB, 0) \ + Return (RBUF) \ + } \ + } \ + \ + Name (SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name (CTRL, Zero) /* PCI _OSC Control Field value */ \ + \ + Method (_OSC, 4) { \ + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField (Arg3, 0, CDW1) \ + CreateDWordField (Arg3, 4, CDW2) \ + CreateDWordField (Arg3, 8, CDW3) \ + \ + /* Save Capabilities DWord2 & 3 */ \ + SUPP = CDW2 \ + CTRL = CDW3 \ + \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If ((SUPP & 0x16) != 0x16) { \ + Ctrl &= 0x3E /* Mask bit 0 (and undefined bits) */ \ + } \ + \ + /* Always allow native PME, AER and Capability Structure control */ \ + /* Never allow SHPC and LTR control */ \ + Ctrl &= 0x1D \ + \ + /* Unknown revision */ \ + If (Arg1 != 1) { \ + Cdw1 |= 0x08 \ + } \ + \ + /* Capabilities bits were masked */ \ + If (CDW3 != CTRL) { \ + CDW1 |= 0x10 \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + CDW3 = CTRL \ + Return (Arg3) \ + } Else { \ + /* Unrecognized UUID */ \ + CDW1 |= 4 \ + Return (Arg3) \ + } \ + } \ + } + +Scope (\_SB_) { + Name (PBMI, 0xABCD) // PCI Bus Minimum + Name (PBMA, 0xABCD) // PCI Bus Maximum + + PCIE_ROOT_COMPLEX (0, 292) + PCIE_ROOT_COMPLEX (1, 287) + PCIE_ROOT_COMPLEX (2, 272) + PCIE_ROOT_COMPLEX (3, 277) + PCIE_ROOT_COMPLEX (4, 282) +} diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l0.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l0.asl deleted file mode 100644 index 2d4a111dd..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l0.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - * - * Copyright (c) 2022-2023, Jared McNeill - * Copyright (c) 2023, Mario Bălănică - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ - -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "PCIE21L0", 2) -{ - Scope (\_SB_) - { - Device (PCI2) { - Name (_HID, "PNP0A08") - Name (_CID, "PNP0A03") - Name (_CCA, Zero) - Name (_UID, 2) - Name (_SEG, 2) - Name (_BBN, One) - - Name (_PRT, Package() { - Package (4) { 0x0FFFF, 0, Zero, 272 }, - Package (4) { 0x0FFFF, 1, Zero, 272 }, - Package (4) { 0x0FFFF, 2, Zero, 272 }, - Package (4) { 0x0FFFF, 3, Zero, 272 } - }) - - Method (_CRS, 0, Serialized) { - Name (RBUF, ResourceTemplate () { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // Granularity - 1, // Range Minimum - 1, // Range Maximum - 0, // Translation Offset - 1, // Length - ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0xF2000000, // Range Minimum - 0xF2FFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x01000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000990000000, // Range Minimum - 0x00000009BFFEFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x000000002FFF0000, // Length - ) - QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0, // Granularity - 0x0000, // Range Minimum - 0xFFFF, // Range Maximum - 0x00000009BFFF0000, // Translation Offset - 0x10000, // Length - ) - }) - return (RBUF) - } - - Device (RES0) { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate () { - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000980000000, // Range Minimum - 0x000000098FFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A40800000, // Range Minimum - 0x0000000A40BFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000000400000, // Length - ) - }) - } - - // OS Control Handoff - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - // See [1] 6.2.10, [2] 4.5 - Method(_OSC,4) { - // Note, This code is very similar to the code in the PCIe firmware - // specification which can be used as a reference - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - // Mask out Native HotPlug - And(CTRL,0x1E,CTRL) - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC - } // PCI2 - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l1.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l1.asl deleted file mode 100644 index 88334d0fd..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l1.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - * - * Copyright (c) 2022-2023, Jared McNeill - * Copyright (c) 2023, Mario Bălănică - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ - -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "PCIE21L1", 2) -{ - Scope (\_SB_) - { - Device (PCI3) { - Name (_HID, "PNP0A08") - Name (_CID, "PNP0A03") - Name (_CCA, Zero) - Name (_UID, 3) - Name (_SEG, 3) - Name (_BBN, One) - - Name (_PRT, Package() { - Package (4) { 0x0FFFF, 0, Zero, 277 }, - Package (4) { 0x0FFFF, 1, Zero, 277 }, - Package (4) { 0x0FFFF, 2, Zero, 277 }, - Package (4) { 0x0FFFF, 3, Zero, 277 } - }) - - Method (_CRS, 0, Serialized) { - Name (RBUF, ResourceTemplate () { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // Granularity - 1, // Range Minimum - 1, // Range Maximum - 0, // Translation Offset - 1, // Length - ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0xF3000000, // Range Minimum - 0xF3FFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x01000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x00000009D0000000, // Range Minimum - 0x00000009FFFEFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x000000002FFF0000, // Length - ) - QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0, // Granularity - 0x0000, // Range Minimum - 0xFFFF, // Range Maximum - 0x00000009FFFF0000, // Translation Offset - 0x10000, // Length - ) - }) - return (RBUF) - } - - Device (RES0) { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate () { - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x00000009C0000000, // Range Minimum - 0x00000009CFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A40C00000, // Range Minimum - 0x0000000A40FFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000000400000, // Length - ) - }) - } - - // OS Control Handoff - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - // See [1] 6.2.10, [2] 4.5 - Method(_OSC,4) { - // Note, This code is very similar to the code in the PCIe firmware - // specification which can be used as a reference - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - // Mask out Native HotPlug - And(CTRL,0x1E,CTRL) - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC - } // PCI3 - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l2.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l2.asl deleted file mode 100644 index 114f1b636..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie2x1l2.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - * - * Copyright (c) 2022-2023, Jared McNeill - * Copyright (c) 2023, Mario Bălănică - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ - -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "PCIE21L2", 2) -{ - Scope (\_SB_) - { - Device (PCI4) { - Name (_HID, "PNP0A08") - Name (_CID, "PNP0A03") - Name (_CCA, Zero) - Name (_UID, 4) - Name (_SEG, 4) - Name (_BBN, One) - - Name (_PRT, Package() { - Package (4) { 0x0FFFF, 0, Zero, 282 }, - Package (4) { 0x0FFFF, 1, Zero, 282 }, - Package (4) { 0x0FFFF, 2, Zero, 282 }, - Package (4) { 0x0FFFF, 3, Zero, 282 } - }) - - Method (_CRS, 0, Serialized) { - Name (RBUF, ResourceTemplate () { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // Granularity - 1, // Range Minimum - 1, // Range Maximum - 0, // Translation Offset - 1, // Length - ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0xF4000000, // Range Minimum - 0xF4FFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x01000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A10000000, // Range Minimum - 0x0000000A3FFEFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x000000002FFF0000, // Length - ) - QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0, // Granularity - 0x0000, // Range Minimum - 0xFFFF, // Range Maximum - 0x0000000A3FFF0000, // Translation Offset - 0x10000, // Length - ) - }) - return (RBUF) - } - - Device (RES0) { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate () { - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A00000000, // Range Minimum - 0x0000000A0FFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A41000000, // Range Minimum - 0x0000000A413FFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000000400000, // Length - ) - }) - } - - // OS Control Handoff - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - // See [1] 6.2.10, [2] 4.5 - Method(_OSC,4) { - // Note, This code is very similar to the code in the PCIe firmware - // specification which can be used as a reference - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - // Mask out Native HotPlug - And(CTRL,0x1E,CTRL) - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC - } // PCI4 - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie3x2.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie3x2.asl deleted file mode 100644 index df4a43db2..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie3x2.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - * - * Copyright (c) 2022-2023, Jared McNeill - * Copyright (c) 2023, Mario Bălănică - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ - -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "PCIE32L0", 2) -{ - Scope (\_SB_) - { - Device (PCI1) { - Name (_HID, "PNP0A08") - Name (_CID, "PNP0A03") - Name (_CCA, Zero) - Name (_UID, 1) - Name (_SEG, 1) - Name (_BBN, One) - - Name (_PRT, Package() { - Package (4) { 0x0FFFF, 0, Zero, 287 }, - Package (4) { 0x0FFFF, 1, Zero, 287 }, - Package (4) { 0x0FFFF, 2, Zero, 287 }, - Package (4) { 0x0FFFF, 3, Zero, 287 } - }) - - Method (_CRS, 0, Serialized) { - Name (RBUF, ResourceTemplate () { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // Granularity - 1, // Range Minimum - 1, // Range Maximum - 0, // Translation Offset - 1, // Length - ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0xF1000000, // Range Minimum - 0xF1FFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x01000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000950000000, // Range Minimum - 0x000000097FFEFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x000000002FFF0000, // Length - ) - QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0, // Granularity - 0x0000, // Range Minimum - 0xFFFF, // Range Maximum - 0x000000097FFF0000, // Translation Offset - 0x10000, // Length - ) - }) - return (RBUF) - } - - Device (RES0) { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate () { - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000940000000, // Range Minimum - 0x000000094FFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A40400000, // Range Minimum - 0x0000000A407FFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000000400000, // Length - ) - }) - } - - // OS Control Handoff - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - // See [1] 6.2.10, [2] 4.5 - Method(_OSC,4) { - // Note, This code is very similar to the code in the PCIe firmware - // specification which can be used as a reference - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - // Mask out Native HotPlug - And(CTRL,0x1E,CTRL) - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC - } // PCI1 - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie3x4.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie3x4.asl deleted file mode 100644 index 6246555d4..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie3x4.asl +++ /dev/null @@ -1,125 +0,0 @@ -/** @file - * - * Copyright (c) 2022-2023, Jared McNeill - * Copyright (c) 2023, Mario Bălănică - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ - -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "PCIE34L0", 2) -{ - Scope (\_SB_) - { - Device (PCI0) { - Name (_HID, "PNP0A08") - Name (_CID, "PNP0A03") - Name (_CCA, Zero) - Name (_UID, 0) - Name (_SEG, 0) - Name (_BBN, One) - - Name (_PRT, Package() { - Package (4) { 0x0FFFF, 0, Zero, 292 }, - Package (4) { 0x0FFFF, 1, Zero, 292 }, - Package (4) { 0x0FFFF, 2, Zero, 292 }, - Package (4) { 0x0FFFF, 3, Zero, 292 } - }) - - Method (_CRS, 0, Serialized) { - Name (RBUF, ResourceTemplate () { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0, // Granularity - 1, // Range Minimum - 1, // Range Maximum - 0, // Translation Offset - 1, // Length - ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0xF0000000, // Range Minimum - 0xF0FFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x01000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000910000000, // Range Minimum - 0x000000093FFEFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x000000002FFF0000, // Length - ) - QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0, // Granularity - 0x0000, // Range Minimum - 0xFFFF, // Range Maximum - 0x000000093FFF0000, // Translation Offset - 0x10000, // Length - ) - }) - return (RBUF) - } - - Device (RES0) { - Name (_HID, "PNP0C02") - Name (_CRS, ResourceTemplate () { - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000900000000, // Range Minimum - 0x000000090FFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000010000000, // Length - ) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000000A40000000, // Range Minimum - 0x0000000A403FFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000000000400000, // Length - ) - }) - } - - // OS Control Handoff - Name(SUPP, Zero) // PCI _OSC Support Field value - Name(CTRL, Zero) // PCI _OSC Control Field value - - // See [1] 6.2.10, [2] 4.5 - Method(_OSC,4) { - // Note, This code is very similar to the code in the PCIe firmware - // specification which can be used as a reference - // Check for proper UUID - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWord-adressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - // Save Capabilities DWord2 & 3 - Store(CDW2,SUPP) - Store(CDW3,CTRL) - // Mask out Native HotPlug - And(CTRL,0x1E,CTRL) - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL,0x1D,CTRL) - - If(LNotEqual(Arg1,One)) { // Unknown revision - Or(CDW1,0x08,CDW1) - } - - If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked - Or(CDW1,0x10,CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL,CDW3) - Return(Arg3) - } Else { - Or(CDW1,4,CDW1) // Unrecognized UUID - Return(Arg3) - } - } // End _OSC - } // PCI0 - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata.asl new file mode 100644 index 000000000..d094c5452 --- /dev/null +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata.asl @@ -0,0 +1,77 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +Scope (\_SB_) { + Device (ATA0) { + Name (_HID, "RKCP0161") + Name (_UID, 0) + Name (_CLS, Package() { 0x01, 0x06, 0x01 }) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe210000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 305 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk-ahci" }, + } + }) + } + + Device (ATA1) { + Name (_HID, "RKCP0161") + Name (_UID, 1) + Name (_CLS, Package() { 0x01, 0x06, 0x01 }) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe220000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 306 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk-ahci" }, + } + }) + } + + Device (ATA2) { + Name (_HID, "RKCP0161") + Name (_UID, 2) + Name (_CLS, Package() { 0x01, 0x06, 0x01 }) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe230000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 307 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk-ahci" }, + } + }) + } +} diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata0.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata0.asl deleted file mode 100644 index 7895f52ff..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata0.asl +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - * - * Copyright (c) 2021, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "AHCSATA0", 2) -{ - Scope (\_SB_) - { - Device (ATA0) { - Name (_HID, "RKCP0161") - Name (_UID, 0) - Name (_CLS, Package() { 0x01, 0x06, 0x01 }) - Name (_CCA, 0) - - Method (_CRS, 0x0, Serialized) { - Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xfe210000, 0x1000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 305 } - }) - Return (RBUF) - } - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "compatible", "rockchip,rk-ahci" }, - } - }) - } - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata1.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata1.asl deleted file mode 100644 index 47e218eb6..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata1.asl +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - * - * Copyright (c) 2021, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "AHCSATA1", 2) -{ - Scope (\_SB_) - { - Device (ATA1) { - Name (_HID, "RKCP0161") - Name (_UID, 1) - Name (_CLS, Package() { 0x01, 0x06, 0x01 }) - Name (_CCA, 0) - - Method (_CRS, 0x0, Serialized) { - Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xfe220000, 0x1000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 306 } - }) - Return (RBUF) - } - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "compatible", "rockchip,rk-ahci" }, - } - }) - } - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata2.asl b/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata2.asl deleted file mode 100644 index 8b678bee0..000000000 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata2.asl +++ /dev/null @@ -1,35 +0,0 @@ -/** @file - * - * Copyright (c) 2021, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * - **/ -#include "AcpiTables.h" - -DefinitionBlock (__FILE__, "SSDT", 5, "RKCP ", "AHCSATA2", 2) -{ - Scope (\_SB_) - { - Device (ATA2) { - Name (_HID, "RKCP0161") - Name (_UID, 2) - Name (_CLS, Package() { 0x01, 0x06, 0x01 }) - Name (_CCA, 0) - - Method (_CRS, 0x0, Serialized) { - Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xfe230000, 0x1000) - Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 307 } - }) - Return (RBUF) - } - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package (2) { "compatible", "rockchip,rk-ahci" }, - } - }) - } - } // Scope (\_SB_) -} // DefinitionBlock diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c index e18609059..ebf26d6eb 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c @@ -26,7 +26,8 @@ STATIC CONST EFI_GUID mAcpiTableFile = { STATIC EFI_EXIT_BOOT_SERVICES mOriginalExitBootServices; -STATIC EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; +STATIC EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; +STATIC EFI_ACPI_DESCRIPTION_HEADER *mDsdtTable; typedef enum { AcpiOsUnknown = 0, @@ -98,81 +99,41 @@ AcpiUpdateSdtNameInteger ( } STATIC -BOOLEAN -AcpiVerifyUpdateTable ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - BOOLEAN Result; - - Result = TRUE; - - switch (AcpiHeader->OemTableId) { - case SIGNATURE_64 ('P', 'C', 'I', 'E', '3', '4', 'L', '0'): - Result = FixedPcdGetBool (PcdPcie30Supported) - && PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED; - break; - case SIGNATURE_64 ('P', 'C', 'I', 'E', '3', '2', 'L', '0'): - Result = FALSE; // not supported yet - break; - case SIGNATURE_64 ('P', 'C', 'I', 'E', '2', '1', 'L', '0'): - Result = PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_PCIE; - break; - case SIGNATURE_64 ('P', 'C', 'I', 'E', '2', '1', 'L', '1'): - Result = PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_PCIE; - break; - case SIGNATURE_64 ('P', 'C', 'I', 'E', '2', '1', 'L', '2'): - Result = PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_PCIE; - break; - case SIGNATURE_64 ('A', 'H', 'C', 'S', 'A', 'T', 'A', '0'): - Result = PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_SATA; - break; - case SIGNATURE_64 ('A', 'H', 'C', 'S', 'A', 'T', 'A', '1'): - Result = PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_SATA; - break; - case SIGNATURE_64 ('A', 'H', 'C', 'S', 'A', 'T', 'A', '2'): - Result = PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_SATA; - break; - } - - return Result; -} - -STATIC -BOOLEAN -AcpiFixupMcfg ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader +VOID +EFIAPI +AcpiDsdtFixupStatus ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol, + IN EFI_ACPI_HANDLE TableHandle ) { - RK3588_MCFG_TABLE *Table; - UINT32 Seg; - - Table = (RK3588_MCFG_TABLE *) AcpiHeader; - - for (Seg = 0; Seg < ARRAY_SIZE (Table->Entry); Seg++) { - if ((PcdGet32 (PcdPcieEcamCompliantSegmentsMask) & (1 << Seg)) != 0) { - Table->Entry[Seg].BaseAddress -= 0x8000; + EFI_STATUS Status; + UINTN Index; + + struct { + CHAR8 *ObjectPath; + BOOLEAN Enabled; + } DevStatus[] = { + { "\\_SB.PCI0._STA", FixedPcdGetBool (PcdPcie30Supported) && + PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED }, + { "\\_SB.PCI1._STA", FALSE }, // not supported yet + { "\\_SB.PCI2._STA", PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_PCIE }, + { "\\_SB.PCI3._STA", PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_PCIE }, + { "\\_SB.PCI4._STA", PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_PCIE }, + { "\\_SB.ATA0._STA", PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_SATA }, + { "\\_SB.ATA1._STA", PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_SATA }, + { "\\_SB.ATA2._STA", PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_SATA }, + }; + + for (Index = 0; Index < ARRAY_SIZE (DevStatus); Index++) { + if (DevStatus[Index].Enabled == FALSE) { + Status = AcpiAmlObjectUpdateInteger (AcpiSdtProtocol, TableHandle, + DevStatus[Index].ObjectPath, 0x0); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Failed to patch %a. Status=%r\n", + DevStatus[Index].ObjectPath, Status)); + } } } - - return TRUE; -} - -STATIC -BOOLEAN -AcpiHandleDynamicNamespace ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - switch (AcpiHeader->Signature) { - case SIGNATURE_32 ('D', 'S', 'D', 'T'): - case SIGNATURE_32 ('S', 'S', 'D', 'T'): - return AcpiVerifyUpdateTable (AcpiHeader); - case SIGNATURE_32 ('M', 'C', 'F', 'G'): - return AcpiFixupMcfg (AcpiHeader); - } - - return TRUE; } STATIC @@ -183,7 +144,10 @@ NotifyEndOfDxeEvent ( IN VOID *Context ) { - EFI_STATUS Status; + EFI_STATUS Status; + UINTN TableKey; + UINTN TableIndex; + EFI_ACPI_HANDLE TableHandle; Status = gBS->LocateProtocol ( &gEfiAcpiSdtProtocolGuid, @@ -194,39 +158,154 @@ NotifyEndOfDxeEvent ( return; } - Status = LocateAndInstallAcpiFromFvConditional (&mAcpiTableFile, &AcpiHandleDynamicNamespace); + Status = LocateAndInstallAcpiFromFvConditional (&mAcpiTableFile, NULL); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_WARN, "AcpiPlatform: Failed to install firmware ACPI as config table. Status=%r\n", Status)); } + + TableIndex = 0; + Status = AcpiLocateTableBySignature ( + mAcpiSdtProtocol, + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + &TableIndex, + &mDsdtTable, + &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate ACPI DSDT table!\n", __func__)); + return; + } + + Status = mAcpiSdtProtocol->OpenSdt (TableKey, &TableHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't open ACPI DSDT table!\n", __func__)); + mAcpiSdtProtocol->Close (TableHandle); + return; + } + + AcpiDsdtFixupStatus (mAcpiSdtProtocol, TableHandle); + + mAcpiSdtProtocol->Close (TableHandle); } STATIC -VOID +EFI_STATUS EFIAPI -AcpiPlatformOsBootHandler ( +AcpiFixupPcieEcam ( IN ACPI_OS_BOOT_TYPE OsType ) { EFI_STATUS Status; - EFI_ACPI_DESCRIPTION_HEADER *Table; + UINTN Index; + RK3588_MCFG_TABLE *McfgTable; + EFI_ACPI_DESCRIPTION_HEADER *FadtTable; UINTN TableKey; - UINTN TableIndex; - - if (mAcpiSdtProtocol == NULL) { - return; - } - - TableIndex = 0; + UINT32 PcieEcamMode; + UINT8 PcieBusMin; + UINT8 PcieBusMax; + UINT8 McfgMainBusMin; + BOOLEAN McfgSplitRootPort; + BOOLEAN McfgSingleDevQuirk; + + Index = 0; Status = AcpiLocateTableBySignature ( mAcpiSdtProtocol, - EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, - &TableIndex, - &Table, + EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + &Index, + (EFI_ACPI_DESCRIPTION_HEADER **)&McfgTable, &TableKey); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "%a: Couldn't locate ACPI DSDT table! Status=%r\n", - __func__, Status)); + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate ACPI MCFG table! Status=%r\n", + Status)); + return Status; + } + + PcieEcamMode = PcdGet32 (PcdAcpiPcieEcamCompatMode); + + if (PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV || + PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON) { + if (OsType == AcpiOsWindows) { + PcieEcamMode = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6; + } else { + PcieEcamMode &= ~ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6; + } + } + + switch (PcieEcamMode) { + case ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6: + PcieBusMin = 0; + PcieBusMax = PCIE_BUS_LIMIT; + McfgMainBusMin = 1; + McfgSplitRootPort = TRUE; + McfgSingleDevQuirk = FALSE; + + Index = 0; + Status = AcpiLocateTableBySignature ( + mAcpiSdtProtocol, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + &Index, + &FadtTable, + &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate ACPI FADT table! Status=%r\n", + Status)); + return Status; + } + + CopyMem (FadtTable->OemId, "NXPMX6", sizeof (FadtTable->OemId)); + AcpiUpdateChecksum ((UINT8 *)FadtTable, FadtTable->Length); + break; + + case ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON: + PcieBusMin = 0; + PcieBusMax = PCIE_BUS_LIMIT; + McfgMainBusMin = 0; + McfgSplitRootPort = FALSE; + McfgSingleDevQuirk = FALSE; + + CopyMem (McfgTable->Header.Header.OemId, "AMAZON", sizeof (McfgTable->Header.Header.OemId)); + McfgTable->Header.Header.OemTableId = SIGNATURE_64 ('G','R','A','V','I','T','O','N'); + break; + + default: // ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV + PcieBusMin = 1; + PcieBusMax = 1; + McfgMainBusMin = 1; + McfgSplitRootPort = FALSE; + McfgSingleDevQuirk = TRUE; + break; + } + + for (Index = 0; Index < ARRAY_SIZE (McfgTable->MainEntries); Index++) { + if (McfgSingleDevQuirk) { + if ((PcdGet32 (PcdPcieEcamCompliantSegmentsMask) & (1 << Index)) == 0) { + McfgTable->MainEntries[Index].BaseAddress += 0x8000; + } + } + McfgTable->MainEntries[Index].StartBusNumber = McfgMainBusMin; + McfgTable->MainEntries[Index].EndBusNumber = PcieBusMax; + } + + if (McfgSplitRootPort == FALSE) { + McfgTable->Header.Header.Length -= sizeof (McfgTable->RootPortEntries); + } + + AcpiUpdateChecksum ((UINT8 *)McfgTable, McfgTable->Header.Header.Length); + + AcpiUpdateSdtNameInteger (mDsdtTable, "PBMI", PcieBusMin); + AcpiUpdateSdtNameInteger (mDsdtTable, "PBMA", PcieBusMax); + + return EFI_SUCCESS; +} + +STATIC +VOID +EFIAPI +AcpiPlatformOsBootHandler ( + IN ACPI_OS_BOOT_TYPE OsType + ) +{ + if (mAcpiSdtProtocol == NULL || mDsdtTable == NULL) { return; } @@ -236,10 +315,12 @@ AcpiPlatformOsBootHandler ( // the system. // if (OsType == AcpiOsWindows) { - AcpiUpdateSdtNameInteger (Table, "EHID", 0); + AcpiUpdateSdtNameInteger (mDsdtTable, "EHID", 0); } - AcpiUpdateChecksum ((UINT8 *)Table, Table->Length); + AcpiFixupPcieEcam (OsType); + + AcpiUpdateChecksum ((UINT8 *)mDsdtTable, mDsdtTable->Length); } STATIC diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 6416de46f..c7aa4646c 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -43,6 +43,7 @@ [Pcd] gRK3588TokenSpaceGuid.PcdConfigTableMode + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode gRK3588TokenSpaceGuid.PcdComboPhy0Mode gRK3588TokenSpaceGuid.PcdComboPhy1Mode gRK3588TokenSpaceGuid.PcdComboPhy2Mode diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c index 0a08b29f1..97dff9526 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c @@ -43,6 +43,15 @@ SetupConfigTableVariables ( ASSERT_EFI_ERROR (Status); } + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"AcpiPcieEcamCompatMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdAcpiPcieEcamCompatMode, FixedPcdGet32 (PcdAcpiPcieEcamCompatModeDefault)); + ASSERT_EFI_ERROR (Status); + } + Size = sizeof (UINT8); Status = gRT->GetVariable (L"FdtSupportOverrides", &gRK3588DxeFormSetGuid, diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf index 9942afce5..797dc0aec 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf @@ -93,6 +93,8 @@ gRK3588TokenSpaceGuid.PcdPcie30State gRK3588TokenSpaceGuid.PcdConfigTableMode + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode gRK3588TokenSpaceGuid.PcdFdtSupportOverrides gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni index 37f801c70..57be07894 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni @@ -136,6 +136,18 @@ #string STR_CONFIG_TABLE_ACPI_SUBTITLE #language en-US "ACPI Configuration" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_PROMPT #language en-US "PCIe ECAM Compatibility Mode" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_HELP #language en-US "Choose how to expose the non-standard PCIe configuration space to the OS.\n\n" + "Single Device - compatible with all OSes. Allows usage of a single or multi-function device. Switches are not supported.\n\n" + "NXPMX6 - compatible with Windows. Exposes the full bus topology and supports switches.\n\n" + "AMAZON GRAVITON - compatible with Linux. Exposes the full bus topology and supports switches.\n\n" + "The Auto modes select NXPMX6 for Windows and fall back to the second option when booting other OSes." +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV #language en-US "Auto (NXPMX6 + Single Device)" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON #language en-US "Auto (NXPMX6 + AMAZON GRAVITON)" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV #language en-US "Single Device" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6 #language en-US "NXPMX6" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON #language en-US "AMAZON GRAVITON" + #string STR_CONFIG_TABLE_FDT_SUBTITLE #language en-US "Device Tree Configuration" #string STR_FDT_SUPPORT_OVERRIDES_PROMPT #language en-US "Support DTB override & overlays" #string STR_FDT_SUPPORT_OVERRIDES_HELP #language en-US "Enable or disable support for overriding the firmware-provided DTB and installing overlays.\n\nCheck firmware documentation for more details." diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr index bf22bf35a..01daba1c2 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr @@ -127,6 +127,11 @@ formset name = ConfigTableMode, guid = RK3588DXE_FORMSET_GUID; + efivarstore ACPI_PCIE_ECAM_COMPAT_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = AcpiPcieEcamCompatMode, + guid = RK3588DXE_FORMSET_GUID; + efivarstore FDT_SUPPORT_OVERRIDES_VARSTORE_DATA, attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, name = FdtSupportOverrides, @@ -474,12 +479,22 @@ formset option text = STRING_TOKEN(STR_CONFIG_TABLE_MODE_ACPI_FDT), value = CONFIG_TABLE_MODE_ACPI_FDT, flags = 0; endoneof; -#if 0 suppressif (get(ConfigTableMode.Mode) & CONFIG_TABLE_MODE_ACPI) == 0; subtitle text = STRING_TOKEN(STR_NULL_STRING); subtitle text = STRING_TOKEN(STR_CONFIG_TABLE_ACPI_SUBTITLE); + + oneof varid = AcpiPcieEcamCompatMode.Mode, + prompt = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_PROMPT), + help = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdAcpiPcieEcamCompatModeDefault), + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV), value = ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON), value = ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON, flags = 0; + endoneof; endif; -#endif suppressif (get(ConfigTableMode.Mode) & CONFIG_TABLE_MODE_FDT) == 0; subtitle text = STRING_TOKEN(STR_NULL_STRING); diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h index 31a6fbf43..b525f89f3 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h @@ -2,6 +2,7 @@ * * RK3588 defines for constructing ACPI tables * + * Copyright (c) 2024, Mario Bălănică * Copyright (c) 2020, Pete Batard * Copyright (c) 2019, ARM Ltd. All rights reserved. * Copyright (c) 2018, Andrei Warkentin @@ -17,6 +18,7 @@ #include #include #include +#include #define EFI_ACPI_OEM_ID {'R','K','C','P',' ',' '} @@ -60,10 +62,64 @@ 0 \ } +// +// Device resource helpers +// +#define QWORDMEMORY_BUF(Index, ResourceType) \ + QWordMemory (ResourceType,, \ + MinFixed, MaxFixed, NonCacheable, ReadWrite, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define QWORDIO_BUF(Index, ResourceType) \ + QWordIO (ResourceType, \ + MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define DWORDMEMORY_BUF(Index, ResourceType) \ + DWordMemory (ResourceType,, \ + MinFixed, MaxFixed, NonCacheable, ReadWrite, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define WORDBUSNUMBER_BUF(Index, ResourceType) \ + WordBusNumber (ResourceType, \ + MinFixed, MaxFixed, PosDecode, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define QWORD_SET(Index, Minimum, Length, Translation) \ + CreateQWordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateQWordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateQWordField (RBUF, RB ## Index._TRA, TR ## Index) \ + CreateQWordField (RBUF, RB ## Index._LEN, LE ## Index) \ + LE ## Index = Length \ + MI ## Index = Minimum \ + TR ## Index = Translation \ + MA ## Index = MI ## Index + LE ## Index - 1 + +#define DWORD_SET(Index, Minimum, Length, Translation) \ + CreateDWordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateDWordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateDWordField (RBUF, RB ## Index._TRA, TR ## Index) \ + CreateDWordField (RBUF, RB ## Index._LEN, LE ## Index) \ + LE ## Index = Length \ + MI ## Index = Minimum \ + TR ## Index = Translation \ + MA ## Index = MI ## Index + LE ## Index - 1 + +#define WORD_SET(Index, Minimum, Length, Translation) \ + CreateWordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateWordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateWordField (RBUF, RB ## Index._TRA, TR ## Index) \ + CreateWordField (RBUF, RB ## Index._LEN, LE ## Index) \ + LE ## Index = Length \ + MI ## Index = Minimum \ + TR ## Index = Translation \ + MA ## Index = MI ## Index + LE ## Index - 1 + #pragma pack(push, 1) typedef struct { EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; - EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Entry[5]; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE MainEntries[NUM_PCIE_CONTROLLER]; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE RootPortEntries[NUM_PCIE_CONTROLLER]; } RK3588_MCFG_TABLE; #pragma pack(pop) diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h index a26092e5e..a1fff317b 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h @@ -58,4 +58,6 @@ PciePinmuxInit( #define PCIE_MEM64_SIZE (PCIE_CFG_SIZE - PCIE_IO_SIZE - PCIE_MEM64_OFFSET) +#define PCIE_BUS_LIMIT 252 // limited by CFG1 iATU window size + #endif diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h index dc280701b..83804eccf 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h @@ -52,6 +52,15 @@ typedef struct { UINT32 Mode; } CONFIG_TABLE_MODE_VARSTORE_DATA; +#define ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV 0x00000001 +#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6 0x00000002 +#define ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON 0x00000004 +#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV 0x00000003 +#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON 0x00000006 +typedef struct { + UINT32 Mode; +} ACPI_PCIE_ECAM_COMPAT_MODE_VARSTORE_DATA; + typedef struct { UINT8 State; } FDT_SUPPORT_OVERRIDES_VARSTORE_DATA; diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c index b077c231f..2a257130f 100755 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c @@ -70,6 +70,8 @@ #define PL_MISC_CONTROL_1_OFF 0x08BC #define DBI_RO_WR_EN BIT0 +#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 + /* ATU Registers */ #define ATU_CAP_BASE 0x300000 #define IATU_REGION_CTRL_OUTBOUND(n) (ATU_CAP_BASE + ((n) << 9)) @@ -287,6 +289,10 @@ PciSetupBars ( ) { MmioWrite16 (DbiBase + PCI_DEVICE_CLASS, (PCI_CLASS_BRIDGE << 8) | PCI_CLASS_BRIDGE_P2P); + + // Disable BAR0 + BAR1 of root port as they're invalid. + MmioWrite32 (DbiBase + PCIE_TYPE0_HDR_DBI2_OFFSET + PCI_BAR0, 0x0); + MmioWrite32 (DbiBase + PCIE_TYPE0_HDR_DBI2_OFFSET + PCI_BAR1, 0x0); } STATIC diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c index e31bb676b..fa0cba5ef 100755 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c @@ -192,7 +192,7 @@ PciHostBridgeGetRootBridges ( EFI_PCI_HOST_BRIDGE_MEM64_DECODE; mPciRootBridges[Loop].Bus.Base = 0; - mPciRootBridges[Loop].Bus.Limit = 252; // limited by CFG1 iATU window size + mPciRootBridges[Loop].Bus.Limit = PCIE_BUS_LIMIT; mPciRootBridges[Loop].Io.Base = PCIE_IO_BASE; mPciRootBridges[Loop].Io.Limit = mPciRootBridges[Loop].Io.Base + PCIE_IO_SIZE - 1; diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c index addf4cef8..95d566ae2 100755 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c @@ -108,12 +108,6 @@ PciSegmentLibReadWorker ( case PciCfgWidthUint16: return MmioRead16 (Base + (UINT32)Address); case PciCfgWidthUint32: - if (GET_BUS_NUM (Address) == 0) { - if (GET_REG_NUM (Address) == 0x10 || GET_REG_NUM (Address) == 0x14) { - // Hide BAR0 + BAR1 of root port - return 0; - } - } return MmioRead32 (Base + (UINT32)Address); default: ASSERT (FALSE); diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec index 27ee5eb93..b5314b4e8 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec @@ -43,6 +43,8 @@ gRK3588TokenSpaceGuid.PcdPcie30Supported|FALSE|BOOLEAN|0x00010201 + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault|0|UINT32|0x00010301 + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|FALSE|BOOLEAN|0x10401 gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|FALSE|BOOLEAN|0x00010501 @@ -81,6 +83,7 @@ gRK3588TokenSpaceGuid.PcdPcie30State|0|UINT32|0x00000201 gRK3588TokenSpaceGuid.PcdConfigTableMode|0|UINT32|0x00000300 + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode|0|UINT32|0x00000301 gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|0|UINT8|0x00000351 gRK3588TokenSpaceGuid.PcdCoolingFanState|0|UINT32|0x00000401 diff --git a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc index 8c235ff79..2ac2b89a3 100644 --- a/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc +++ b/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc @@ -45,6 +45,12 @@ DEFINE CONFIG_TABLE_MODE_FDT = 0x00000002 DEFINE CONFIG_TABLE_MODE_ACPI_FDT = 0x00000003 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV = 0x00000001 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6 = 0x00000002 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON = 0x00000004 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV = 0x00000003 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON = 0x00000006 + # # Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.h # @@ -252,6 +258,7 @@ # # ACPI support flags and default values # + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault|$(ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV) [PcdsPatchableInModule] gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000 @@ -298,6 +305,7 @@ # ACPI / Device Tree # gRK3588TokenSpaceGuid.PcdConfigTableMode|L"ConfigTableMode"|gRK3588DxeFormSetGuid|0x0|$(CONFIG_TABLE_MODE_ACPI) + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode|L"AcpiPcieEcamCompatMode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|L"FdtSupportOverrides"|gRK3588DxeFormSetGuid|0x0|FALSE # diff --git a/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc b/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc index 291449c9a..e3eaa00ce 100644 --- a/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc +++ b/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc @@ -52,6 +52,20 @@ DEFINE DEBUG_PRINT_ERROR_LEVEL_NO_INFO = $(DEBUG_PRINT_ERROR_LEVEL) & ~0x00000040 + # + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 + # +!if $(TARGET) == RELEASE + DEFINE DEBUG_PROPERTY_MASK = 0x00 +!else + DEFINE DEBUG_PROPERTY_MASK = 0x0f +!endif + ################################################################################ # # Library Class section - list of all common Library Classes needed by Rockchip platforms. @@ -395,17 +409,7 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 - # DEBUG_ASSERT_ENABLED 0x01 - # DEBUG_PRINT_ENABLED 0x02 - # DEBUG_CODE_ENABLED 0x04 - # CLEAR_MEMORY_ENABLED 0x08 - # ASSERT_BREAKPOINT_ENABLED 0x10 - # ASSERT_DEADLOOP_ENABLED 0x20 -!if $(TARGET) == RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x00 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f -!endif + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|$(DEBUG_PROPERTY_MASK) gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL) @@ -571,7 +575,10 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf # # ACPI Support # - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|$(DEBUG_PROPERTY_MASK) & ~0x04 + } MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf #