diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 43f6c29c6..b456b6ba7 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -30,6 +30,7 @@ jobs: - indiedroid-nova - roc-rk3588s-pc - itx-3588j + - aio-3588q - station-m3 - r58x - r58-mini diff --git a/README.md b/README.md index 0a1955a05..d18707b83 100644 --- a/README.md +++ b/README.md @@ -7,6 +7,8 @@ This repository contains an UEFI firmware implementation based on EDK2 for vario - [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html) - [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html) - [ameriDroid Indiedroid Nova](https://indiedroid.us) +- [Firefly AIO-3588Q](https://en.t-firefly.com/product/industry/aio3588q) +- [Firefly ITX-3588J](https://en.t-firefly.com/product/industry/itx3588j) - [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc) - [StationPC Station M3](https://www.stationpc.com/product/stationm3) - [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html) @@ -141,6 +143,8 @@ The paths above are relative to the root of the file system. That is, the `dtb` | Name | Platform | | --------------------------------------- | ----------------------------- | | `rk3588s-9tripod-linux` | Indiedroid Nova | +| `aio-3588q` | Firefly AIO-3588Q | +| `itx-3588j` | Firefly ITX-3588J | | `roc-rk3588s-pc` | ROC-RK3588S-PC / Station M3 | | `rk3588-nanopc-t6` | NanoPC T6 | | `rk3588s-nanopi-r6c` | NanoPi R6C | diff --git a/configs/aio-3588q.conf b/configs/aio-3588q.conf new file mode 100644 index 000000000..f394772ae --- /dev/null +++ b/configs/aio-3588q.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc +PLATFORM_NAME=AIO-3588Q +SOC=RK3588 diff --git a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md index 33eb353b9..ceacef3db 100644 --- a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md +++ b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md @@ -7,6 +7,8 @@ * itx-3588j: (note: in the dtb given here, the builtin bootargs in the source above were commented out before building. Not sure if that was a necessary step - SS) - + +* rk3588-firefly-aio-3588q: + ## License SPDX-License-Identifier: GPL-2.0-only diff --git a/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb new file mode 100644 index 000000000..f02d0427c Binary files /dev/null and b/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb differ diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc new file mode 100644 index 000000000..656ef890f --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc new file mode 100644 index 000000000..a09f125ff --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = AIO-3588Q + PLATFORM_VENDOR = Firefly + PLATFORM_GUID = 400f8259-7664-47df-b375-8ba262e4867e + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + # + # Platform based on AIO-3588Q board + # +!include Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc new file mode 100644 index 000000000..e14a3e862 --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc @@ -0,0 +1,134 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # PCA9555 GPIO extender support + # I2C location configured by PCDs below. + # + DEFINE RK_PCA9555_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"AIO-3588Q" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly" + gRockchipTokenSpaceGuid.PcdFamilyName|"AIO" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/core/icore3588q" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"aio-3588q" + + # I2C + # i2c0: pc9202@3c, rk8602@42, rk8603@43 + # i2c1: rk8602@42 (npu) + # i2c3: es8388@11, XC7160b@1b, gc2053b@37, gc2093b@7e + # i2c6: pca9555@20, pca9555@21, fusb302@22, hym8563@51 + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x42, 0x11, 0x51, 0x20, 0x21, 0x22 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x3, 0x6, 0x6, 0x6, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + gRockchipTokenSpaceGuid.PcdPca9555Address|0x21 + gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x47 + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x4f + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf + + # Hack to enable use of PCA9555 during PCIe initialization. + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf + } diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000..1cfeaf165 --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf @@ -0,0 +1,55 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl new file mode 100644 index 000000000..cf2c5d840 --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C3" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac0.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C3) { + include ("Es8388.asl") + } + } +} diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 000000000..8c130adc3 --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,460 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +EFI_STATUS +EFIAPI +GetPca9555Protocol ( + IN OUT PCA95XX_PROTOCOL **Pca95xxProtocl + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN HandleCount; + + /* Locate Handles of all PCA95XX_PROTOCOL producers */ + Status = gBS->LocateHandleBuffer (ByProtocol, + &gPca95xxProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__)); + return Status; + } + + DEBUG ((DEBUG_INFO, + "%a: got %d PCA95XX_PROTOCOLs\n", + __FUNCTION__, + HandleCount)); + + /* + * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute + * the consumer is not obliged to call CloseProtocol. + */ + Status = gBS->OpenProtocol (HandleBuffer[0], + &gPca95xxProtocolGuid, + (VOID **)Pca95xxProtocl, + HandleBuffer[0], + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + + return Status; +} + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + /* gmac0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_RXD2, GMAC0_RXD3 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; // GMAC0_RXCLK, GMAC0_TXD2, GMAC0_TXD3, GMAC0_TXCLK + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_TXD0, GMAC0_TXD1 + BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; // GMAC0_TXEN, GMAC0_RXD0, GMAC0_RXD1 + BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; // GMAC0_RXDV_CRS, GMAC0_MCLKINOUT + BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; // GMAC0_MDC, GMAC0_MDIO + + /* phy0 reset */ + GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT); + break; + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */ + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */ + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */ + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 0: + /* phy0 reset */ + GpioPinWrite (3, GPIO_PIN_PC7, !Enable); + break; + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + /* On Firefly AIO-3588Q this is controlled via the PCA9555. */ + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status)); + } else { + /* USB-C */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 12, /* vbus5v0_typec_pwr_en */ + GPIO_MODE_OUTPUT_0 + ); + + gBS->Stall(1200000); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 12, /* vbus5v0_typec_pwr_en */ + GPIO_MODE_OUTPUT_1 + ); + + /* other USB stuff */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 5, /* vcc5v0_host */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 4, /* vcc_hub_reset */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 6, /* vcc_hub3_reset */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 7, /* vcc5v0_host3 */ + GPIO_MODE_OUTPUT_1 + ); + } +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1 + GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30 + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30 + break; + case PCIE_SEGMENT_PCIE20L0: + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1 + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PB4, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status)); + } else { + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 14, /* PCA_IO1_6 */ + Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1 + ); + } + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER3, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 50000, + .DutyNs = 50000, + .Polarity = FALSE, +}; // PWM15 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (1, GPIO_PIN_PC6, 0xB); // PWM15_IR_M2 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + GpioPinWrite (3, GPIO_PIN_PB2, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PB2, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); // headphone enable + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // headphone detect +} diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 000000000..8becb63ff --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,38 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Protocols] + gPca95xxProtocolGuid + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf new file mode 100644 index 000000000..6c686c31c --- /dev/null +++ b/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf @@ -0,0 +1,42 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Protocols] + gPca95xxProtocolGuid + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c + +# Hack to enable use of PCA9555 during PCIe initialization. +[Depex] + gPca95xxProtocolGuid