diff --git a/EF_I2S.yaml b/EF_I2S.yaml
index 73708f5..d1c4272 100644
--- a/EF_I2S.yaml
+++ b/EF_I2S.yaml
@@ -5,8 +5,8 @@ info:
repo: github.com/efabless/EF_I2S
owner: Efabless Corp.
license: APACHE 2.0
- author: Mohamed Shalan
- email: mshalan@efabless.com
+ author: Efabless Corp.
+ email: ip_admin@efabless.com
version: v1.1.14
date: 17-09-2024
category: digital
@@ -161,6 +161,7 @@ external_interface:
clock:
name: clk
+ gated: 'yes'
reset:
name: rst_n
diff --git a/README.md b/README.md
index 29c3dca..192fe32 100644
--- a/README.md
+++ b/README.md
@@ -1,41 +1,36 @@
# EF_I2S
Two-wire I2S synchronous serial interface, compatible with I2S specification.
-- Receiver only
-- 32x32 Receive FIFO
-- Sample Size selection
-- Left channel, Right channel only or Stereo
-- Programmable prescaler
-- Supports both the classical I2S and the Left-aligned formats
-- Programmable sample size
-- Zero/Sign extension for the samples
-
-
## The wrapped IP
+ APB, AHBL, and Wishbone wrappers are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
+#### Wrapped IP System Integration
- APB, AHBL, and Wishbone wrappers, generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility, are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
-
-
-### Wrapped IP System Integration
-
-
-Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the APB wrapper:
+Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the wishbone wrapper:
```verilog
-EF_I2S_APB INST (
- `TB_APB_SLAVE_CONN,
- .ws(ws),
- .sck(sck),
- .sdi(sdi)
+EF_I2S_WB INST (
+ .clk_i(clk_i),
+ .rst_i(rst_i),
+ .adr_i(adr_i),
+ .dat_i(dat_i),
+ .dat_o(dat_o),
+ .sel_i(sel_i),
+ .cyc_i(cyc_i),
+ .stb_i(stb_i),
+ .ack_o(ack_o),
+ .we_i(we_i),
+ .IRQ(irq),
+ .ws(ws),
+ .sck(sck),
+ .sdi(sdi)
);
```
-> **_NOTE:_** `TB_APB_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
-
-
-## Implementation example
+#### Wrappers with DFT support
+Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to enable the clock gate whenever the scan chain testmode is enabled.
+## Implementation example
The following table is the result for implementing the EF_I2S IP with different wrappers using Sky130 PDK and [OpenLane2](https://github.com/efabless/openlane2) flow.
|Module | Number of cells | Max. freq |
@@ -47,8 +42,6 @@ The following table is the result for implementing the EF_I2S IP with different
## The Programmer's Interface
-
-
### Registers
|Name|Offset|Reset Value|Access Mode|Description|
@@ -66,31 +59,28 @@ The following table is the result for implementing the EF_I2S IP with different
|RIS|ff08|0x00000000|w|Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details|
|MIS|ff04|0x00000000|w|Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details|
|IC|ff0c|0x00000000|w|Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details|
+|GCLK|ff10|0x00000000|w|Gated clock enable; 1: enable clock, 0: disable clock|
### RXDATA Register [Offset: 0x0, mode: r]
The received sample
-
### PR Register [Offset: 0x4, mode: w]
The Prescaler register; used to determine the sck signal frequency . $Prescaler = clk_freq/(2 x sck_freq) - 1$.
-
### AVGT Register [Offset: 0x8, mode: w]
The Average threshold
-
### ZCRT Register [Offset: 0xc, mode: w]
The ZCR threshold
-
### CTRL Register [Offset: 0x10, mode: w]
Control Register; 0:Enable, 1:FIFO Enable.
@@ -103,7 +93,6 @@ Control Register; 0:Enable, 1:FIFO Enable.
|2|avg_en|1|Averaging enable|
|3|zcr_en|1|ZCR enable|
-
### CFG Register [Offset: 0x14, mode: w]
Configuration Register, 0-1: Channels to read, '01': right, '10': left, '11': Both (stereo) 2: Sign Extend 3: Left Justify 4-8: Sample Size (0-31)
@@ -118,7 +107,6 @@ Configuration Register, 0-1: Channels to read, '01': right, '10': left, '11': Bo
|10|AVGSEL|1|Select the number of samples to average|
|11|ZCRSEL|1|Select the number of samples to calculate the ZCR|
-
### RX_FIFO_LEVEL Register [Offset: 0xfe00, mode: r]
RX_FIFO Level Register
@@ -128,7 +116,6 @@ RX_FIFO Level Register
|---|---|---|---|
|0|level|4|FIFO data level|
-
### RX_FIFO_THRESHOLD Register [Offset: 0xfe04, mode: w]
RX_FIFO Level Threshold Register
@@ -138,7 +125,6 @@ RX_FIFO Level Threshold Register
|---|---|---|---|
|0|threshold|4|FIFO level threshold value|
-
### RX_FIFO_FLUSH Register [Offset: 0xfe08, mode: w]
RX_FIFO Flush Register
@@ -148,19 +134,28 @@ RX_FIFO Flush Register
|---|---|---|---|
|0|flush|1|FIFO flush|
+### GCLK Register [Offset: 0xff10, mode: w]
+
+ Gated clock enable register
+
+
+|bit|field name|width|description|
+|---|---|---|---|
+|0|gclk_enable|1|Gated clock enable; 1: enable clock, 0: disable clock|
+
### Interrupt Flags
-The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility.
+The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types.
Each register has a group of bits for the interrupt sources/flags.
-- `IM`: is used to enable/disable interrupt sources.
+- `IM` [offset: 0xff00]: is used to enable/disable interrupt sources.
-- `RIS`: has the current interrupt status (interrupt flags) whether they are enabled or disabled.
+- `RIS` [offset: 0xff08]: has the current interrupt status (interrupt flags) whether they are enabled or disabled.
-- `MIS`: is the result of masking (ANDing) RIS by IM.
+- `MIS` [offset: 0xff04]: is the result of masking (ANDing) RIS by IM.
-- `IC`: is used to clear an interrupt flag.
+- `IC` [offset: 0xff0c]: is used to clear an interrupt flag.
The following are the bit definitions for the interrupt registers:
@@ -173,9 +168,17 @@ The following are the bit definitions for the interrupt registers:
|3|AVGF|1|The avg is above the threshold.|
|4|ZCRF|1|The ZCR is above the threshold.|
|5|VADF|1|The Voice Activity Detector flag; active when both ZCR & AVG flags are active.|
+### Clock Gating
+The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_util_gating_cell``, which is part of the the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the cell operates with a behavioral implementation, but when the ``CLKG_SKY130_HD`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used.
+**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to add the clock gating feature, you need to add ``SKY130`` macro to the ``VERILOG_DEFINES`` configuration variable. Update the YAML configuration file as follows:
+```
+VERILOG_DEFINES:
+- SKY130
+```
### The Interface
+
#### Module Parameters
@@ -215,54 +218,14 @@ The following are the bit definitions for the interrupt registers:
|vad_flag|output|1|The VAD flag|
|channels|input|2|Channels used (left, right, or stereo)|
|en|input|1|Enable signal|
-
-
-
-
-## F/W Usage Guidelines:
-1. Set the prescaler value in the ``PR`` register where sck_freq = (clk_freq / (prescaler+1))/2. Note that for the controller to function correctly, the prescaler needs to be greater than 1.
-2. Check the I2S device data sheet to know the sample size sent and configure the ``sample_size`` field in the ``CFG`` reg accordingly.
-3. Check the I2S device data sheet to know if the samples sent are in left justified or i2s mode and configure the ``left_justified`` field in the ``CFG`` reg.
-4. Configure the ``channels`` field in ``CFG`` by specifying which channel you want to capture or both channels (stereo)
-5. If you want the sample to be sign extended by the controller, enable ``sign_extended`` field in ``CFG`` register
-6. After configuring the controller, enable it along with the FIFO to capture the samples by setting ``en`` and ``fifo_en`` fields in the ``CTRL`` register.
-7. If you want to use the averaging feature in the controller, you can set the ``avg_en`` field and set the average threshold ``AVGT`` register. The average flag ``AVGF`` will be fired when the average of the samples sent are above this threshold. Note that the averaging mode works only when the sign extension mode is on.
-
-
+## Firmware Drivers:
+Firmware drivers for EF_I2S can be found in the [fw](https://github.com/efabless/EF_I2S/tree/main/fw) directory. EF_I2S driver documentation is available [here](https://github.com/efabless/EF_I2S/blob/main/fw/README.md).
+You can also find an example C application using the EF_I2S drivers [here]().
## Installation:
You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager
* To clone repo:
```git clone https://github.com/efabless/EF_I2S```
+> **Note:** If you choose this method, you need to clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, as it includes required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v)
* To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run
```ipm install EF_I2S```
-### Run cocotb UVM Testbench:
-In IP directory run:
- ```shell
- cd verify/uvm-python/
- ```
- ##### To run testbench for design with APB
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=APB
- ```
- To run a certain test:
- ```shell
- make run_ BUS_TYPE=APB
- ```
- To run all tests with a tag:
- ```shell
- make run_all_tests TAG= BUS_TYPE=APB
- ```
- ##### To run testbench for design with APB
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=AHB
- ```
- To run a certain test:
- ```shell
- make run_ BUS_TYPE=AHB
- ```
- To run all tests with a tag:
- ```shell
- make run_all_tests TAG= BUS_TYPE=AHB
-```
+> **Note:** This method is recommended as it automatically installs [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) as a dependency.
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.dev.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.dev.v
new file mode 100644
index 0000000..4cbe636
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.dev.v
@@ -0,0 +1,254 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns/1ps
+`default_nettype none
+
+`define AHBL_AW 16
+
+`include "ahbl_wrapper.vh"
+
+module EF_I2S_AHBL #(
+ parameter
+ DW = 32,
+ AW = 4
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ `AHBL_SLAVE_PORTS,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = `AHBL_AW'h0000;
+ localparam PR_REG_OFFSET = `AHBL_AW'h0004;
+ localparam AVGT_REG_OFFSET = `AHBL_AW'h0008;
+ localparam ZCRT_REG_OFFSET = `AHBL_AW'h000C;
+ localparam CTRL_REG_OFFSET = `AHBL_AW'h0010;
+ localparam CFG_REG_OFFSET = `AHBL_AW'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
+ localparam IM_REG_OFFSET = `AHBL_AW'hFF00;
+ localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
+ localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
+ localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell(
+ `ifdef USE_POWER_PINS
+ .vpwr(VPWR),
+ .vgnd(VGND),
+ `endif // USE_POWER_PINS
+ .clk(HCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = HRESETn;
+
+
+ `AHBL_CTRL_SIGNALS
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ `AHBL_REG(PR_REG, 0, 8)
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ `AHBL_REG(AVGT_REG, 0, 32)
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ `AHBL_REG(ZCRT_REG, 0, 32)
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ `AHBL_REG(CTRL_REG, 'h0, 4)
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ `AHBL_REG(CFG_REG, 'h201, 12)
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+ `AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ `AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+ localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
+ `AHBL_REG(GCLK_REG, 0, 1)
+
+ reg [5:0] IM_REG;
+ reg [5:0] IC_REG;
+ reg [5:0] RIS_REG;
+
+ `AHBL_MIS_REG(6)
+ `AHBL_REG(IM_REG, 0, 6)
+ `AHBL_IC_REG(6)
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ `AHBL_BLOCK(RIS_REG, 0) else begin
+ for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always@(posedge HCLK or negedge HRESETn)
+ if(HRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end
+ else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign HRDATA =
+ (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (last_HADDR[`AHBL_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (last_HADDR[`AHBL_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (last_HADDR[`AHBL_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ 32'hDEADBEEF;
+
+ assign HREADYOUT = 1'b1;
+
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v
deleted file mode 100644
index 2d996df..0000000
--- a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- Copyright 2024 Efabless Corp.
-
- Author: Mohamed Shalan (mshalan@efabless.com)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-
-*/
-
-/* THIS FILE IS GENERATED, DO NOT EDIT */
-
-`timescale 1ns/1ps
-`default_nettype none
-
-
-
-/*
- Copyright 2020 AUCOHL
-
- Author: Mohamed Shalan (mshalan@aucegypt.edu)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at:
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
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-module EF_I2S_AHBL #(
- parameter
- DW = 32,
- AW = 4
-) (
-
-
-
-
- input wire HCLK,
- input wire HRESETn,
- input wire HWRITE,
- input wire [31:0] HWDATA,
- input wire [31:0] HADDR,
- input wire [1:0] HTRANS,
- input wire HSEL,
- input wire HREADY,
- output wire HREADYOUT,
- output wire [31:0] HRDATA,
- output wire IRQ
-,
- output wire [1-1:0] ws,
- output wire [1-1:0] sck,
- input wire [1-1:0] sdi
-);
-
- localparam RXDATA_REG_OFFSET = 16'h0000;
- localparam PR_REG_OFFSET = 16'h0004;
- localparam AVGT_REG_OFFSET = 16'h0008;
- localparam ZCRT_REG_OFFSET = 16'h000C;
- localparam CTRL_REG_OFFSET = 16'h0010;
- localparam CFG_REG_OFFSET = 16'h0014;
- localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
- localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
- localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
- localparam IM_REG_OFFSET = 16'hFF00;
- localparam MIS_REG_OFFSET = 16'hFF04;
- localparam RIS_REG_OFFSET = 16'hFF08;
- localparam IC_REG_OFFSET = 16'hFF0C;
-
- reg [0:0] GCLK_REG;
- wire clk_g;
- wire clk_gated_en = GCLK_REG[0];
- ef_gating_cell clk_gate_cell(
-
-
-
- // USE_POWER_PINS
- .clk(HCLK),
- .clk_en(clk_gated_en),
- .clk_o(clk_g)
- );
-
- wire clk = clk_g;
- wire rst_n = HRESETn;
-
-
- reg last_HSEL, last_HWRITE; reg [31:0] last_HADDR; reg [1:0] last_HTRANS;
- always@ (posedge HCLK or negedge HRESETn) begin
- if(~HRESETn) begin
- last_HSEL <= 1'b0;
- last_HADDR <= 1'b0;
- last_HWRITE <= 1'b0;
- last_HTRANS <= 1'b0;
- end else if(HREADY) begin
- last_HSEL <= HSEL;
- last_HADDR <= HADDR;
- last_HWRITE <= HWRITE;
- last_HTRANS <= HTRANS;
- end
- end
- wire ahbl_valid = last_HSEL & last_HTRANS[1];
- wire ahbl_we = last_HWRITE & ahbl_valid;
- wire ahbl_re = ~last_HWRITE & ahbl_valid;
-
- wire [1-1:0] fifo_en;
- wire [1-1:0] fifo_rd;
- wire [AW-1:0] fifo_level_threshold;
- wire [1-1:0] fifo_flush;
- wire [1-1:0] fifo_full;
- wire [1-1:0] fifo_empty;
- wire [AW-1:0] fifo_level;
- wire [1-1:0] fifo_level_above;
- wire [32-1:0] fifo_rdata;
- wire [1-1:0] sign_extend;
- wire [1-1:0] left_justified;
- wire [6-1:0] sample_size;
- wire [8-1:0] sck_prescaler;
- wire [32-1:0] avg_threshold;
- wire [1-1:0] avg_flag;
- wire [1-1:0] avg_en;
- wire [1-1:0] avg_sel;
- wire [32-1:0] zcr_threshold;
- wire [1-1:0] zcr_flag;
- wire [1-1:0] zcr_en;
- wire [1-1:0] zcr_sel;
- wire [1-1:0] vad_flag;
- wire [2-1:0] channels;
- wire [1-1:0] en;
-
- // Register Definitions
- wire [32-1:0] RXDATA_WIRE;
-
- reg [7:0] PR_REG;
- assign sck_prescaler = PR_REG;
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) PR_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==PR_REG_OFFSET))
- PR_REG <= HWDATA[8-1:0];
-
- reg [31:0] AVGT_REG;
- assign avg_threshold = AVGT_REG;
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) AVGT_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==AVGT_REG_OFFSET))
- AVGT_REG <= HWDATA[32-1:0];
-
- reg [31:0] ZCRT_REG;
- assign zcr_threshold = ZCRT_REG;
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) ZCRT_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==ZCRT_REG_OFFSET))
- ZCRT_REG <= HWDATA[32-1:0];
-
- reg [3:0] CTRL_REG;
- assign en = CTRL_REG[0 : 0];
- assign fifo_en = CTRL_REG[1 : 1];
- assign avg_en = CTRL_REG[2 : 2];
- assign zcr_en = CTRL_REG[3 : 3];
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CTRL_REG <= 'h0;
- else if(ahbl_we & (last_HADDR[16-1:0]==CTRL_REG_OFFSET))
- CTRL_REG <= HWDATA[4-1:0];
-
- reg [11:0] CFG_REG;
- assign channels = CFG_REG[1 : 0];
- assign sign_extend = CFG_REG[2 : 2];
- assign left_justified = CFG_REG[3 : 3];
- assign sample_size = CFG_REG[9 : 4];
- assign avg_sel = CFG_REG[10 : 10];
- assign zcr_sel = CFG_REG[11 : 11];
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CFG_REG <= 'h201;
- else if(ahbl_we & (last_HADDR[16-1:0]==CFG_REG_OFFSET))
- CFG_REG <= HWDATA[12-1:0];
-
- wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
- assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
-
- reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
- assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
- RX_FIFO_THRESHOLD_REG <= HWDATA[AW-1:0];
-
- reg [0:0] RX_FIFO_FLUSH_REG;
- assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_FLUSH_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET))
- RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
- else
- RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
-
- localparam GCLK_REG_OFFSET = 16'hFF10;
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
- GCLK_REG <= HWDATA[1-1:0];
-
- reg [5:0] IM_REG;
- reg [5:0] IC_REG;
- reg [5:0] RIS_REG;
-
- wire[6-1:0] MIS_REG = RIS_REG & IM_REG;
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IM_REG <= 0;
- else if(ahbl_we & (last_HADDR[16-1:0]==IM_REG_OFFSET))
- IM_REG <= HWDATA[6-1:0];
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IC_REG <= 6'b0;
- else if(ahbl_we & (last_HADDR[16-1:0]==IC_REG_OFFSET))
- IC_REG <= HWDATA[6-1:0];
- else IC_REG <= 6'd0;
-
- wire [0:0] FIFOE = fifo_empty;
- wire [0:0] FIFOA = fifo_level_above;
- wire [0:0] FIFOF = fifo_full;
- wire [0:0] AVGF = avg_flag;
- wire [0:0] ZCRF = zcr_flag;
- wire [0:0] VADF = vad_flag;
-
-
- integer _i_;
- always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RIS_REG <= 0; else begin
- for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- end
-
- assign IRQ = |MIS_REG;
-
- reg [0:0] _sdi_reg_[1:0];
- wire _sdi_w_ = _sdi_reg_[1];
- always@(posedge HCLK or negedge HRESETn)
- if(HRESETn == 0) begin
- _sdi_reg_[0] <= 'b0;
- _sdi_reg_[1] <= 'b0;
- end
- else begin
- _sdi_reg_[0] <= sdi;
- _sdi_reg_[1] <= _sdi_reg_[0];
- end
- EF_I2S #(
- .DW(DW),
- .AW(AW)
- ) instance_to_wrap (
- .clk(clk),
- .rst_n(rst_n),
- .fifo_en(fifo_en),
- .fifo_rd(fifo_rd),
- .fifo_level_threshold(fifo_level_threshold),
- .fifo_flush(fifo_flush),
- .fifo_full(fifo_full),
- .fifo_empty(fifo_empty),
- .fifo_level(fifo_level),
- .fifo_level_above(fifo_level_above),
- .fifo_rdata(fifo_rdata),
- .sign_extend(sign_extend),
- .left_justified(left_justified),
- .sample_size(sample_size),
- .sck_prescaler(sck_prescaler),
- .avg_threshold(avg_threshold),
- .avg_flag(avg_flag),
- .avg_en(avg_en),
- .avg_sel(avg_sel),
- .zcr_threshold(zcr_threshold),
- .zcr_flag(zcr_flag),
- .zcr_en(zcr_en),
- .zcr_sel(zcr_sel),
- .vad_flag(vad_flag),
- .channels(channels),
- .en(en),
- .ws(ws),
- .sck(sck),
- .sdi(_sdi_w_)
- );
-
- assign HRDATA =
- (last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
- (last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
- (last_HADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
- (last_HADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
- (last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
- (last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
- (last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
- (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
- (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
- (last_HADDR[16-1:0] == IM_REG_OFFSET) ? IM_REG :
- (last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
- (last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
- (last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG :
- (last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
- 32'hDEADBEEF;
-
- assign HREADYOUT = 1'b1;
-
- assign RXDATA_WIRE = fifo_rdata;
- assign fifo_rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
-endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v
index f3ba023..4da4583 100644
--- a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v
+++ b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v
@@ -1,7 +1,7 @@
/*
Copyright 2024 Efabless Corp.
- Author: Mohamed Shalan (mshalan@efabless.com)
+ Author: Efabless Corp. (ip_admin@efabless.com)
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,236 +19,367 @@
/* THIS FILE IS GENERATED, DO NOT EDIT */
-`timescale 1ns/1ps
-`default_nettype none
+`timescale 1ns / 1ps `default_nettype none
-`define AHBL_AW 16
-`include "ahbl_wrapper.vh"
-module EF_I2S_AHBL #(
- parameter
- DW = 32,
- AW = 4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// PRINT_LICENSE
+
+
+
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+
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+
+
+
+
+module EF_I2S_AHBL #(
+ parameter DW = 32,
+ AW = 4
) (
-`ifdef USE_POWER_PINS
- inout VPWR,
- inout VGND,
-`endif
- `AHBL_SLAVE_PORTS,
- output wire [1-1:0] ws,
- output wire [1-1:0] sck,
- input wire [1-1:0] sdi
+
+
+
+
+ input wire HCLK,
+ input wire HRESETn,
+ input wire HWRITE,
+ input wire [ 31:0] HWDATA,
+ input wire [ 31:0] HADDR,
+ input wire [ 1:0] HTRANS,
+ input wire HSEL,
+ input wire HREADY,
+ output wire HREADYOUT,
+ output wire [ 31:0] HRDATA,
+ output wire IRQ,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
);
- localparam RXDATA_REG_OFFSET = `AHBL_AW'h0000;
- localparam PR_REG_OFFSET = `AHBL_AW'h0004;
- localparam AVGT_REG_OFFSET = `AHBL_AW'h0008;
- localparam ZCRT_REG_OFFSET = `AHBL_AW'h000C;
- localparam CTRL_REG_OFFSET = `AHBL_AW'h0010;
- localparam CFG_REG_OFFSET = `AHBL_AW'h0014;
- localparam RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
- localparam RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
- localparam RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
- localparam IM_REG_OFFSET = `AHBL_AW'hFF00;
- localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
- localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
- localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
-
- reg [0:0] GCLK_REG;
- wire clk_g;
- wire clk_gated_en = GCLK_REG[0];
- ef_gating_cell clk_gate_cell(
- `ifdef USE_POWER_PINS
- .vpwr(VPWR),
- .vgnd(VGND),
- `endif // USE_POWER_PINS
- .clk(HCLK),
- .clk_en(clk_gated_en),
- .clk_o(clk_g)
- );
-
- wire clk = clk_g;
- wire rst_n = HRESETn;
-
-
- `AHBL_CTRL_SIGNALS
-
- wire [1-1:0] fifo_en;
- wire [1-1:0] fifo_rd;
- wire [AW-1:0] fifo_level_threshold;
- wire [1-1:0] fifo_flush;
- wire [1-1:0] fifo_full;
- wire [1-1:0] fifo_empty;
- wire [AW-1:0] fifo_level;
- wire [1-1:0] fifo_level_above;
- wire [32-1:0] fifo_rdata;
- wire [1-1:0] sign_extend;
- wire [1-1:0] left_justified;
- wire [6-1:0] sample_size;
- wire [8-1:0] sck_prescaler;
- wire [32-1:0] avg_threshold;
- wire [1-1:0] avg_flag;
- wire [1-1:0] avg_en;
- wire [1-1:0] avg_sel;
- wire [32-1:0] zcr_threshold;
- wire [1-1:0] zcr_flag;
- wire [1-1:0] zcr_en;
- wire [1-1:0] zcr_sel;
- wire [1-1:0] vad_flag;
- wire [2-1:0] channels;
- wire [1-1:0] en;
-
- // Register Definitions
- wire [32-1:0] RXDATA_WIRE;
-
- reg [7:0] PR_REG;
- assign sck_prescaler = PR_REG;
- `AHBL_REG(PR_REG, 0, 8)
-
- reg [31:0] AVGT_REG;
- assign avg_threshold = AVGT_REG;
- `AHBL_REG(AVGT_REG, 0, 32)
-
- reg [31:0] ZCRT_REG;
- assign zcr_threshold = ZCRT_REG;
- `AHBL_REG(ZCRT_REG, 0, 32)
-
- reg [3:0] CTRL_REG;
- assign en = CTRL_REG[0 : 0];
- assign fifo_en = CTRL_REG[1 : 1];
- assign avg_en = CTRL_REG[2 : 2];
- assign zcr_en = CTRL_REG[3 : 3];
- `AHBL_REG(CTRL_REG, 'h0, 4)
-
- reg [11:0] CFG_REG;
- assign channels = CFG_REG[1 : 0];
- assign sign_extend = CFG_REG[2 : 2];
- assign left_justified = CFG_REG[3 : 3];
- assign sample_size = CFG_REG[9 : 4];
- assign avg_sel = CFG_REG[10 : 10];
- assign zcr_sel = CFG_REG[11 : 11];
- `AHBL_REG(CFG_REG, 'h201, 12)
-
- wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
- assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
-
- reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
- assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
- `AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
-
- reg [0:0] RX_FIFO_FLUSH_REG;
- assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
- `AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
- localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
- `AHBL_REG(GCLK_REG, 0, 1)
-
- reg [5:0] IM_REG;
- reg [5:0] IC_REG;
- reg [5:0] RIS_REG;
-
- `AHBL_MIS_REG(6)
- `AHBL_REG(IM_REG, 0, 6)
- `AHBL_IC_REG(6)
-
- wire [0:0] FIFOE = fifo_empty;
- wire [0:0] FIFOA = fifo_level_above;
- wire [0:0] FIFOF = fifo_full;
- wire [0:0] AVGF = avg_flag;
- wire [0:0] ZCRF = zcr_flag;
- wire [0:0] VADF = vad_flag;
-
-
- integer _i_;
- `AHBL_BLOCK(RIS_REG, 0) else begin
- for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- end
-
- assign IRQ = |MIS_REG;
-
- reg [0:0] _sdi_reg_[1:0];
- wire _sdi_w_ = _sdi_reg_[1];
- always@(posedge HCLK or negedge HRESETn)
- if(HRESETn == 0) begin
- _sdi_reg_[0] <= 'b0;
- _sdi_reg_[1] <= 'b0;
- end
- else begin
- _sdi_reg_[0] <= sdi;
- _sdi_reg_[1] <= _sdi_reg_[0];
- end
- EF_I2S #(
- .DW(DW),
- .AW(AW)
- ) instance_to_wrap (
- .clk(clk),
- .rst_n(rst_n),
- .fifo_en(fifo_en),
- .fifo_rd(fifo_rd),
- .fifo_level_threshold(fifo_level_threshold),
- .fifo_flush(fifo_flush),
- .fifo_full(fifo_full),
- .fifo_empty(fifo_empty),
- .fifo_level(fifo_level),
- .fifo_level_above(fifo_level_above),
- .fifo_rdata(fifo_rdata),
- .sign_extend(sign_extend),
- .left_justified(left_justified),
- .sample_size(sample_size),
- .sck_prescaler(sck_prescaler),
- .avg_threshold(avg_threshold),
- .avg_flag(avg_flag),
- .avg_en(avg_en),
- .avg_sel(avg_sel),
- .zcr_threshold(zcr_threshold),
- .zcr_flag(zcr_flag),
- .zcr_en(zcr_en),
- .zcr_sel(zcr_sel),
- .vad_flag(vad_flag),
- .channels(channels),
- .en(en),
- .ws(ws),
- .sck(sck),
- .sdi(_sdi_w_)
- );
-
- assign HRDATA =
- (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
- (last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
- (last_HADDR[`AHBL_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
- (last_HADDR[`AHBL_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
- (last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
- (last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
- (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
- (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
- (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
- (last_HADDR[`AHBL_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
- (last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
- (last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
- (last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
- (last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ localparam RXDATA_REG_OFFSET = 16'h0000;
+ localparam PR_REG_OFFSET = 16'h0004;
+ localparam AVGT_REG_OFFSET = 16'h0008;
+ localparam ZCRT_REG_OFFSET = 16'h000C;
+ localparam CTRL_REG_OFFSET = 16'h0010;
+ localparam CFG_REG_OFFSET = 16'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+ localparam IM_REG_OFFSET = 16'hFF00;
+ localparam MIS_REG_OFFSET = 16'hFF04;
+ localparam RIS_REG_OFFSET = 16'hFF08;
+ localparam IC_REG_OFFSET = 16'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell (
+
+
+
+ // USE_POWER_PINS
+ .clk(HCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = HRESETn;
+
+
+ reg last_HSEL, last_HWRITE;
+ reg [31:0] last_HADDR;
+ reg [ 1:0] last_HTRANS;
+ always @(posedge HCLK or negedge HRESETn) begin
+ if (~HRESETn) begin
+ last_HSEL <= 1'b0;
+ last_HADDR <= 1'b0;
+ last_HWRITE <= 1'b0;
+ last_HTRANS <= 1'b0;
+ end else if (HREADY) begin
+ last_HSEL <= HSEL;
+ last_HADDR <= HADDR;
+ last_HWRITE <= HWRITE;
+ last_HTRANS <= HTRANS;
+ end
+ end
+ wire ahbl_valid = last_HSEL & last_HTRANS[1];
+ wire ahbl_we = last_HWRITE & ahbl_valid;
+ wire ahbl_re = ~last_HWRITE & ahbl_valid;
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) PR_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= HWDATA[8-1:0];
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) AVGT_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == AVGT_REG_OFFSET)) AVGT_REG <= HWDATA[32-1:0];
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) ZCRT_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == ZCRT_REG_OFFSET)) ZCRT_REG <= HWDATA[32-1:0];
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) CTRL_REG <= 'h0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= HWDATA[4-1:0];
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) CFG_REG <= 'h201;
+ else if (ahbl_we & (last_HADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= HWDATA[12-1:0];
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW-1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW-1) : 0];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+ RX_FIFO_THRESHOLD_REG <= HWDATA[AW-1:0];
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) RX_FIFO_FLUSH_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+ RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+ else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+ localparam GCLK_REG_OFFSET = 16'hFF10;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) GCLK_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= HWDATA[1-1:0];
+
+ reg [ 5:0] IM_REG;
+ reg [ 5:0] IC_REG;
+ reg [ 5:0] RIS_REG;
+
+ wire [6-1:0] MIS_REG = RIS_REG & IM_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) IM_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= HWDATA[6-1:0];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) IC_REG <= 6'b0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= HWDATA[6-1:0];
+ else IC_REG <= 6'd0;
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) RIS_REG <= 0;
+ else begin
+ for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOA[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOF[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (AVGF[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (ZCRF[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (VADF[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always @(posedge HCLK or negedge HRESETn)
+ if (HRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign HRDATA =
+ (last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (last_HADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (last_HADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (last_HADDR[16-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;
- assign HREADYOUT = 1'b1;
+ assign HREADYOUT = 1'b1;
- assign RXDATA_WIRE = fifo_rdata;
- assign fifo_rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.dev.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.dev.v
new file mode 100644
index 0000000..5b5d278
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/EF_I2S_APB.dev.v
@@ -0,0 +1,254 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns/1ps
+`default_nettype none
+
+`define APB_AW 16
+
+`include "apb_wrapper.vh"
+
+module EF_I2S_APB #(
+ parameter
+ DW = 32,
+ AW = 4
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ `APB_SLAVE_PORTS,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = `APB_AW'h0000;
+ localparam PR_REG_OFFSET = `APB_AW'h0004;
+ localparam AVGT_REG_OFFSET = `APB_AW'h0008;
+ localparam ZCRT_REG_OFFSET = `APB_AW'h000C;
+ localparam CTRL_REG_OFFSET = `APB_AW'h0010;
+ localparam CFG_REG_OFFSET = `APB_AW'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE08;
+ localparam IM_REG_OFFSET = `APB_AW'hFF00;
+ localparam MIS_REG_OFFSET = `APB_AW'hFF04;
+ localparam RIS_REG_OFFSET = `APB_AW'hFF08;
+ localparam IC_REG_OFFSET = `APB_AW'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell(
+ `ifdef USE_POWER_PINS
+ .vpwr(VPWR),
+ .vgnd(VGND),
+ `endif // USE_POWER_PINS
+ .clk(PCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = PRESETn;
+
+
+ `APB_CTRL_SIGNALS
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ `APB_REG(PR_REG, 0, 8)
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ `APB_REG(AVGT_REG, 0, 32)
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ `APB_REG(ZCRT_REG, 0, 32)
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ `APB_REG(CTRL_REG, 'h0, 4)
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ `APB_REG(CFG_REG, 'h201, 12)
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+ `APB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ `APB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+ localparam GCLK_REG_OFFSET = `APB_AW'hFF10;
+ `APB_REG(GCLK_REG, 0, 1)
+
+ reg [5:0] IM_REG;
+ reg [5:0] IC_REG;
+ reg [5:0] RIS_REG;
+
+ `APB_MIS_REG(6)
+ `APB_REG(IM_REG, 0, 6)
+ `APB_IC_REG(6)
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ `APB_BLOCK(RIS_REG, 0) else begin
+ for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always@(posedge PCLK or negedge PRESETn)
+ if(PRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end
+ else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign PRDATA =
+ (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (PADDR[`APB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (PADDR[`APB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (PADDR[`APB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (PADDR[`APB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (PADDR[`APB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (PADDR[`APB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (PADDR[`APB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (PADDR[`APB_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (PADDR[`APB_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (PADDR[`APB_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ 32'hDEADBEEF;
+
+ assign PREADY = 1'b1;
+
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v
deleted file mode 100644
index 51a19de..0000000
--- a/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- Copyright 2024 Efabless Corp.
-
- Author: Mohamed Shalan (mshalan@efabless.com)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-
-*/
-
-/* THIS FILE IS GENERATED, DO NOT EDIT */
-
-`timescale 1ns/1ps
-`default_nettype none
-
-
-
-/*
- Copyright 2020 AUCOHL
-
- Author: Mohamed Shalan (mshalan@aucegypt.edu)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at:
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-
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-
-
-module EF_I2S_APB #(
- parameter
- DW = 32,
- AW = 4
-) (
-
-
-
-
- input wire PCLK,
- input wire PRESETn,
- input wire PWRITE,
- input wire [31:0] PWDATA,
- input wire [31:0] PADDR,
- input wire PENABLE,
- input wire PSEL,
- output wire PREADY,
- output wire [31:0] PRDATA,
- output wire IRQ
-,
- output wire [1-1:0] ws,
- output wire [1-1:0] sck,
- input wire [1-1:0] sdi
-);
-
- localparam RXDATA_REG_OFFSET = 16'h0000;
- localparam PR_REG_OFFSET = 16'h0004;
- localparam AVGT_REG_OFFSET = 16'h0008;
- localparam ZCRT_REG_OFFSET = 16'h000C;
- localparam CTRL_REG_OFFSET = 16'h0010;
- localparam CFG_REG_OFFSET = 16'h0014;
- localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
- localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
- localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
- localparam IM_REG_OFFSET = 16'hFF00;
- localparam MIS_REG_OFFSET = 16'hFF04;
- localparam RIS_REG_OFFSET = 16'hFF08;
- localparam IC_REG_OFFSET = 16'hFF0C;
-
- reg [0:0] GCLK_REG;
- wire clk_g;
- wire clk_gated_en = GCLK_REG[0];
- ef_gating_cell clk_gate_cell(
-
-
-
- // USE_POWER_PINS
- .clk(PCLK),
- .clk_en(clk_gated_en),
- .clk_o(clk_g)
- );
-
- wire clk = clk_g;
- wire rst_n = PRESETn;
-
-
- wire apb_valid = PSEL & PENABLE;
- wire apb_we = PWRITE & apb_valid;
- wire apb_re = ~PWRITE & apb_valid;
-
- wire [1-1:0] fifo_en;
- wire [1-1:0] fifo_rd;
- wire [AW-1:0] fifo_level_threshold;
- wire [1-1:0] fifo_flush;
- wire [1-1:0] fifo_full;
- wire [1-1:0] fifo_empty;
- wire [AW-1:0] fifo_level;
- wire [1-1:0] fifo_level_above;
- wire [32-1:0] fifo_rdata;
- wire [1-1:0] sign_extend;
- wire [1-1:0] left_justified;
- wire [6-1:0] sample_size;
- wire [8-1:0] sck_prescaler;
- wire [32-1:0] avg_threshold;
- wire [1-1:0] avg_flag;
- wire [1-1:0] avg_en;
- wire [1-1:0] avg_sel;
- wire [32-1:0] zcr_threshold;
- wire [1-1:0] zcr_flag;
- wire [1-1:0] zcr_en;
- wire [1-1:0] zcr_sel;
- wire [1-1:0] vad_flag;
- wire [2-1:0] channels;
- wire [1-1:0] en;
-
- // Register Definitions
- wire [32-1:0] RXDATA_WIRE;
-
- reg [7:0] PR_REG;
- assign sck_prescaler = PR_REG;
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) PR_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==PR_REG_OFFSET))
- PR_REG <= PWDATA[8-1:0];
-
- reg [31:0] AVGT_REG;
- assign avg_threshold = AVGT_REG;
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) AVGT_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==AVGT_REG_OFFSET))
- AVGT_REG <= PWDATA[32-1:0];
-
- reg [31:0] ZCRT_REG;
- assign zcr_threshold = ZCRT_REG;
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) ZCRT_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==ZCRT_REG_OFFSET))
- ZCRT_REG <= PWDATA[32-1:0];
-
- reg [3:0] CTRL_REG;
- assign en = CTRL_REG[0 : 0];
- assign fifo_en = CTRL_REG[1 : 1];
- assign avg_en = CTRL_REG[2 : 2];
- assign zcr_en = CTRL_REG[3 : 3];
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) CTRL_REG <= 'h0;
- else if(apb_we & (PADDR[16-1:0]==CTRL_REG_OFFSET))
- CTRL_REG <= PWDATA[4-1:0];
-
- reg [11:0] CFG_REG;
- assign channels = CFG_REG[1 : 0];
- assign sign_extend = CFG_REG[2 : 2];
- assign left_justified = CFG_REG[3 : 3];
- assign sample_size = CFG_REG[9 : 4];
- assign avg_sel = CFG_REG[10 : 10];
- assign zcr_sel = CFG_REG[11 : 11];
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) CFG_REG <= 'h201;
- else if(apb_we & (PADDR[16-1:0]==CFG_REG_OFFSET))
- CFG_REG <= PWDATA[12-1:0];
-
- wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
- assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
-
- reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
- assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
- RX_FIFO_THRESHOLD_REG <= PWDATA[AW-1:0];
-
- reg [0:0] RX_FIFO_FLUSH_REG;
- assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RX_FIFO_FLUSH_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET))
- RX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
- else
- RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
-
- localparam GCLK_REG_OFFSET = 16'hFF10;
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==GCLK_REG_OFFSET))
- GCLK_REG <= PWDATA[1-1:0];
-
- reg [5:0] IM_REG;
- reg [5:0] IC_REG;
- reg [5:0] RIS_REG;
-
- wire[6-1:0] MIS_REG = RIS_REG & IM_REG;
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) IM_REG <= 0;
- else if(apb_we & (PADDR[16-1:0]==IM_REG_OFFSET))
- IM_REG <= PWDATA[6-1:0];
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) IC_REG <= 6'b0;
- else if(apb_we & (PADDR[16-1:0]==IC_REG_OFFSET))
- IC_REG <= PWDATA[6-1:0];
- else
- IC_REG <= 6'd0;
-
- wire [0:0] FIFOE = fifo_empty;
- wire [0:0] FIFOA = fifo_level_above;
- wire [0:0] FIFOF = fifo_full;
- wire [0:0] AVGF = avg_flag;
- wire [0:0] ZCRF = zcr_flag;
- wire [0:0] VADF = vad_flag;
-
-
- integer _i_;
- always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RIS_REG <= 0; else begin
- for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- end
-
- assign IRQ = |MIS_REG;
-
- reg [0:0] _sdi_reg_[1:0];
- wire _sdi_w_ = _sdi_reg_[1];
- always@(posedge PCLK or negedge PRESETn)
- if(PRESETn == 0) begin
- _sdi_reg_[0] <= 'b0;
- _sdi_reg_[1] <= 'b0;
- end
- else begin
- _sdi_reg_[0] <= sdi;
- _sdi_reg_[1] <= _sdi_reg_[0];
- end
- EF_I2S #(
- .DW(DW),
- .AW(AW)
- ) instance_to_wrap (
- .clk(clk),
- .rst_n(rst_n),
- .fifo_en(fifo_en),
- .fifo_rd(fifo_rd),
- .fifo_level_threshold(fifo_level_threshold),
- .fifo_flush(fifo_flush),
- .fifo_full(fifo_full),
- .fifo_empty(fifo_empty),
- .fifo_level(fifo_level),
- .fifo_level_above(fifo_level_above),
- .fifo_rdata(fifo_rdata),
- .sign_extend(sign_extend),
- .left_justified(left_justified),
- .sample_size(sample_size),
- .sck_prescaler(sck_prescaler),
- .avg_threshold(avg_threshold),
- .avg_flag(avg_flag),
- .avg_en(avg_en),
- .avg_sel(avg_sel),
- .zcr_threshold(zcr_threshold),
- .zcr_flag(zcr_flag),
- .zcr_en(zcr_en),
- .zcr_sel(zcr_sel),
- .vad_flag(vad_flag),
- .channels(channels),
- .en(en),
- .ws(ws),
- .sck(sck),
- .sdi(_sdi_w_)
- );
-
- assign PRDATA =
- (PADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
- (PADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
- (PADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
- (PADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
- (PADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
- (PADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
- (PADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
- (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
- (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
- (PADDR[16-1:0] == IM_REG_OFFSET) ? IM_REG :
- (PADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
- (PADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
- (PADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG :
- (PADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
- 32'hDEADBEEF;
-
- assign PREADY = 1'b1;
-
- assign RXDATA_WIRE = fifo_rdata;
- assign fifo_rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
-endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.v
index c9c1c08..7670ccd 100644
--- a/hdl/rtl/bus_wrappers/EF_I2S_APB.v
+++ b/hdl/rtl/bus_wrappers/EF_I2S_APB.v
@@ -1,7 +1,7 @@
/*
Copyright 2024 Efabless Corp.
- Author: Mohamed Shalan (mshalan@efabless.com)
+ Author: Efabless Corp. (ip_admin@efabless.com)
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,236 +19,349 @@
/* THIS FILE IS GENERATED, DO NOT EDIT */
-`timescale 1ns/1ps
-`default_nettype none
+`timescale 1ns / 1ps `default_nettype none
-`define APB_AW 16
-`include "apb_wrapper.vh"
-module EF_I2S_APB #(
- parameter
- DW = 32,
- AW = 4
+
+
+
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+// PRINT_LICENSE
+
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+
+
+
+module EF_I2S_APB #(
+ parameter DW = 32,
+ AW = 4
) (
-`ifdef USE_POWER_PINS
- inout VPWR,
- inout VGND,
-`endif
- `APB_SLAVE_PORTS,
- output wire [1-1:0] ws,
- output wire [1-1:0] sck,
- input wire [1-1:0] sdi
+
+
+
+
+ input wire PCLK,
+ input wire PRESETn,
+ input wire PWRITE,
+ input wire [ 31:0] PWDATA,
+ input wire [ 31:0] PADDR,
+ input wire PENABLE,
+ input wire PSEL,
+ output wire PREADY,
+ output wire [ 31:0] PRDATA,
+ output wire IRQ,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
);
- localparam RXDATA_REG_OFFSET = `APB_AW'h0000;
- localparam PR_REG_OFFSET = `APB_AW'h0004;
- localparam AVGT_REG_OFFSET = `APB_AW'h0008;
- localparam ZCRT_REG_OFFSET = `APB_AW'h000C;
- localparam CTRL_REG_OFFSET = `APB_AW'h0010;
- localparam CFG_REG_OFFSET = `APB_AW'h0014;
- localparam RX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE00;
- localparam RX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE04;
- localparam RX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE08;
- localparam IM_REG_OFFSET = `APB_AW'hFF00;
- localparam MIS_REG_OFFSET = `APB_AW'hFF04;
- localparam RIS_REG_OFFSET = `APB_AW'hFF08;
- localparam IC_REG_OFFSET = `APB_AW'hFF0C;
-
- reg [0:0] GCLK_REG;
- wire clk_g;
- wire clk_gated_en = GCLK_REG[0];
- ef_gating_cell clk_gate_cell(
- `ifdef USE_POWER_PINS
- .vpwr(VPWR),
- .vgnd(VGND),
- `endif // USE_POWER_PINS
- .clk(PCLK),
- .clk_en(clk_gated_en),
- .clk_o(clk_g)
- );
-
- wire clk = clk_g;
- wire rst_n = PRESETn;
-
-
- `APB_CTRL_SIGNALS
-
- wire [1-1:0] fifo_en;
- wire [1-1:0] fifo_rd;
- wire [AW-1:0] fifo_level_threshold;
- wire [1-1:0] fifo_flush;
- wire [1-1:0] fifo_full;
- wire [1-1:0] fifo_empty;
- wire [AW-1:0] fifo_level;
- wire [1-1:0] fifo_level_above;
- wire [32-1:0] fifo_rdata;
- wire [1-1:0] sign_extend;
- wire [1-1:0] left_justified;
- wire [6-1:0] sample_size;
- wire [8-1:0] sck_prescaler;
- wire [32-1:0] avg_threshold;
- wire [1-1:0] avg_flag;
- wire [1-1:0] avg_en;
- wire [1-1:0] avg_sel;
- wire [32-1:0] zcr_threshold;
- wire [1-1:0] zcr_flag;
- wire [1-1:0] zcr_en;
- wire [1-1:0] zcr_sel;
- wire [1-1:0] vad_flag;
- wire [2-1:0] channels;
- wire [1-1:0] en;
-
- // Register Definitions
- wire [32-1:0] RXDATA_WIRE;
-
- reg [7:0] PR_REG;
- assign sck_prescaler = PR_REG;
- `APB_REG(PR_REG, 0, 8)
-
- reg [31:0] AVGT_REG;
- assign avg_threshold = AVGT_REG;
- `APB_REG(AVGT_REG, 0, 32)
-
- reg [31:0] ZCRT_REG;
- assign zcr_threshold = ZCRT_REG;
- `APB_REG(ZCRT_REG, 0, 32)
-
- reg [3:0] CTRL_REG;
- assign en = CTRL_REG[0 : 0];
- assign fifo_en = CTRL_REG[1 : 1];
- assign avg_en = CTRL_REG[2 : 2];
- assign zcr_en = CTRL_REG[3 : 3];
- `APB_REG(CTRL_REG, 'h0, 4)
-
- reg [11:0] CFG_REG;
- assign channels = CFG_REG[1 : 0];
- assign sign_extend = CFG_REG[2 : 2];
- assign left_justified = CFG_REG[3 : 3];
- assign sample_size = CFG_REG[9 : 4];
- assign avg_sel = CFG_REG[10 : 10];
- assign zcr_sel = CFG_REG[11 : 11];
- `APB_REG(CFG_REG, 'h201, 12)
-
- wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
- assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
-
- reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
- assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
- `APB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
-
- reg [0:0] RX_FIFO_FLUSH_REG;
- assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
- `APB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
- localparam GCLK_REG_OFFSET = `APB_AW'hFF10;
- `APB_REG(GCLK_REG, 0, 1)
-
- reg [5:0] IM_REG;
- reg [5:0] IC_REG;
- reg [5:0] RIS_REG;
-
- `APB_MIS_REG(6)
- `APB_REG(IM_REG, 0, 6)
- `APB_IC_REG(6)
-
- wire [0:0] FIFOE = fifo_empty;
- wire [0:0] FIFOA = fifo_level_above;
- wire [0:0] FIFOF = fifo_full;
- wire [0:0] AVGF = avg_flag;
- wire [0:0] ZCRF = zcr_flag;
- wire [0:0] VADF = vad_flag;
-
-
- integer _i_;
- `APB_BLOCK(RIS_REG, 0) else begin
- for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- end
-
- assign IRQ = |MIS_REG;
-
- reg [0:0] _sdi_reg_[1:0];
- wire _sdi_w_ = _sdi_reg_[1];
- always@(posedge PCLK or negedge PRESETn)
- if(PRESETn == 0) begin
- _sdi_reg_[0] <= 'b0;
- _sdi_reg_[1] <= 'b0;
- end
- else begin
- _sdi_reg_[0] <= sdi;
- _sdi_reg_[1] <= _sdi_reg_[0];
- end
- EF_I2S #(
- .DW(DW),
- .AW(AW)
- ) instance_to_wrap (
- .clk(clk),
- .rst_n(rst_n),
- .fifo_en(fifo_en),
- .fifo_rd(fifo_rd),
- .fifo_level_threshold(fifo_level_threshold),
- .fifo_flush(fifo_flush),
- .fifo_full(fifo_full),
- .fifo_empty(fifo_empty),
- .fifo_level(fifo_level),
- .fifo_level_above(fifo_level_above),
- .fifo_rdata(fifo_rdata),
- .sign_extend(sign_extend),
- .left_justified(left_justified),
- .sample_size(sample_size),
- .sck_prescaler(sck_prescaler),
- .avg_threshold(avg_threshold),
- .avg_flag(avg_flag),
- .avg_en(avg_en),
- .avg_sel(avg_sel),
- .zcr_threshold(zcr_threshold),
- .zcr_flag(zcr_flag),
- .zcr_en(zcr_en),
- .zcr_sel(zcr_sel),
- .vad_flag(vad_flag),
- .channels(channels),
- .en(en),
- .ws(ws),
- .sck(sck),
- .sdi(_sdi_w_)
- );
-
- assign PRDATA =
- (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
- (PADDR[`APB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
- (PADDR[`APB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
- (PADDR[`APB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
- (PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
- (PADDR[`APB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
- (PADDR[`APB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
- (PADDR[`APB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
- (PADDR[`APB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
- (PADDR[`APB_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
- (PADDR[`APB_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
- (PADDR[`APB_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
- (PADDR[`APB_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
- (PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ localparam RXDATA_REG_OFFSET = 16'h0000;
+ localparam PR_REG_OFFSET = 16'h0004;
+ localparam AVGT_REG_OFFSET = 16'h0008;
+ localparam ZCRT_REG_OFFSET = 16'h000C;
+ localparam CTRL_REG_OFFSET = 16'h0010;
+ localparam CFG_REG_OFFSET = 16'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+ localparam IM_REG_OFFSET = 16'hFF00;
+ localparam MIS_REG_OFFSET = 16'hFF04;
+ localparam RIS_REG_OFFSET = 16'hFF08;
+ localparam IC_REG_OFFSET = 16'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell (
+
+
+
+ // USE_POWER_PINS
+ .clk(PCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = PRESETn;
+
+
+ wire apb_valid = PSEL & PENABLE;
+ wire apb_we = PWRITE & apb_valid;
+ wire apb_re = ~PWRITE & apb_valid;
+
+ wire [ 1-1:0] fifo_en;
+ wire [ 1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [ 1-1:0] fifo_flush;
+ wire [ 1-1:0] fifo_full;
+ wire [ 1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [ 1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [ 1-1:0] sign_extend;
+ wire [ 1-1:0] left_justified;
+ wire [ 6-1:0] sample_size;
+ wire [ 8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [ 1-1:0] avg_flag;
+ wire [ 1-1:0] avg_en;
+ wire [ 1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [ 1-1:0] zcr_flag;
+ wire [ 1-1:0] zcr_en;
+ wire [ 1-1:0] zcr_sel;
+ wire [ 1-1:0] vad_flag;
+ wire [ 2-1:0] channels;
+ wire [ 1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [ 7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) PR_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= PWDATA[8-1:0];
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) AVGT_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == AVGT_REG_OFFSET)) AVGT_REG <= PWDATA[32-1:0];
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) ZCRT_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == ZCRT_REG_OFFSET)) ZCRT_REG <= PWDATA[32-1:0];
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) CTRL_REG <= 'h0;
+ else if (apb_we & (PADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= PWDATA[4-1:0];
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) CFG_REG <= 'h201;
+ else if (apb_we & (PADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= PWDATA[12-1:0];
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW-1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW-1) : 0];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+ RX_FIFO_THRESHOLD_REG <= PWDATA[AW-1:0];
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) RX_FIFO_FLUSH_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+ RX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
+ else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+ localparam GCLK_REG_OFFSET = 16'hFF10;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) GCLK_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= PWDATA[1-1:0];
+
+ reg [ 5:0] IM_REG;
+ reg [ 5:0] IC_REG;
+ reg [ 5:0] RIS_REG;
+
+ wire [6-1:0] MIS_REG = RIS_REG & IM_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) IM_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= PWDATA[6-1:0];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) IC_REG <= 6'b0;
+ else if (apb_we & (PADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= PWDATA[6-1:0];
+ else IC_REG <= 6'd0;
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) RIS_REG <= 0;
+ else begin
+ for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOA[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOF[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (AVGF[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (ZCRF[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (VADF[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always @(posedge PCLK or negedge PRESETn)
+ if (PRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign PRDATA =
+ (PADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (PADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (PADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (PADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (PADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (PADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (PADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (PADDR[16-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (PADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (PADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (PADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;
- assign PREADY = 1'b1;
+ assign PREADY = 1'b1;
- assign RXDATA_WIRE = fifo_rdata;
- assign fifo_rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.dev.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.dev.v
new file mode 100644
index 0000000..85b4c5e
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/EF_I2S_WB.dev.v
@@ -0,0 +1,259 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns/1ps
+`default_nettype none
+
+`define WB_AW 16
+
+`include "wb_wrapper.vh"
+
+module EF_I2S_WB #(
+ parameter
+ DW = 32,
+ AW = 4
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ `WB_SLAVE_PORTS,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = `WB_AW'h0000;
+ localparam PR_REG_OFFSET = `WB_AW'h0004;
+ localparam AVGT_REG_OFFSET = `WB_AW'h0008;
+ localparam ZCRT_REG_OFFSET = `WB_AW'h000C;
+ localparam CTRL_REG_OFFSET = `WB_AW'h0010;
+ localparam CFG_REG_OFFSET = `WB_AW'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08;
+ localparam IM_REG_OFFSET = `WB_AW'hFF00;
+ localparam MIS_REG_OFFSET = `WB_AW'hFF04;
+ localparam RIS_REG_OFFSET = `WB_AW'hFF08;
+ localparam IC_REG_OFFSET = `WB_AW'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell(
+ `ifdef USE_POWER_PINS
+ .vpwr(VPWR),
+ .vgnd(VGND),
+ `endif // USE_POWER_PINS
+ .clk(clk_i),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = (~rst_i);
+
+
+ `WB_CTRL_SIGNALS
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ `WB_REG(PR_REG, 0, 8)
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ `WB_REG(AVGT_REG, 0, 32)
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ `WB_REG(ZCRT_REG, 0, 32)
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ `WB_REG(CTRL_REG, 'h0, 4)
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ `WB_REG(CFG_REG, 'h201, 12)
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+ `WB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ `WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+ localparam GCLK_REG_OFFSET = `WB_AW'hFF10;
+ `WB_REG(GCLK_REG, 0, 1)
+
+ reg [5:0] IM_REG;
+ reg [5:0] IC_REG;
+ reg [5:0] RIS_REG;
+
+ `WB_MIS_REG(6)
+ `WB_REG(IM_REG, 0, 6)
+ `WB_IC_REG(6)
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ `WB_BLOCK(RIS_REG, 0) else begin
+ for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always@(posedge clk_i or posedge rst_i)
+ if(rst_i == 1) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end
+ else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign dat_o =
+ (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (adr_i[`WB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (adr_i[`WB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (adr_i[`WB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (adr_i[`WB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (adr_i[`WB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (adr_i[`WB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (adr_i[`WB_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (adr_i[`WB_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (adr_i[`WB_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (adr_i[`WB_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
+ 32'hDEADBEEF;
+
+ always @ (posedge clk_i or posedge rst_i)
+ if(rst_i)
+ ack_o <= 1'b0;
+ else if(wb_valid & ~ack_o)
+ ack_o <= 1'b1;
+ else
+ ack_o <= 1'b0;
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v
deleted file mode 100644
index 3465c5e..0000000
--- a/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- Copyright 2024 Efabless Corp.
-
- Author: Mohamed Shalan (mshalan@efabless.com)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-
-*/
-
-/* THIS FILE IS GENERATED, DO NOT EDIT */
-
-`timescale 1ns/1ps
-`default_nettype none
-
-
-
-/*
- Copyright 2020 AUCOHL
-
- Author: Mohamed Shalan (mshalan@aucegypt.edu)
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at:
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-module EF_I2S_WB #(
- parameter
- DW = 32,
- AW = 4
-) (
-
-
-
-
- input wire ext_clk,
- input wire clk_i,
- input wire rst_i,
- input wire [31:0] adr_i,
- input wire [31:0] dat_i,
- output wire [31:0] dat_o,
- input wire [3:0] sel_i,
- input wire cyc_i,
- input wire stb_i,
- output reg ack_o,
- input wire we_i,
- output wire IRQ,
- output wire [1-1:0] ws,
- output wire [1-1:0] sck,
- input wire [1-1:0] sdi
-);
-
- localparam RXDATA_REG_OFFSET = 16'h0000;
- localparam PR_REG_OFFSET = 16'h0004;
- localparam AVGT_REG_OFFSET = 16'h0008;
- localparam ZCRT_REG_OFFSET = 16'h000C;
- localparam CTRL_REG_OFFSET = 16'h0010;
- localparam CFG_REG_OFFSET = 16'h0014;
- localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
- localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
- localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
- localparam IM_REG_OFFSET = 16'hFF00;
- localparam MIS_REG_OFFSET = 16'hFF04;
- localparam RIS_REG_OFFSET = 16'hFF08;
- localparam IC_REG_OFFSET = 16'hFF0C;
-
- reg [0:0] GCLK_REG;
- wire clk_g;
- wire clk_gated_en = GCLK_REG[0];
- ef_gating_cell clk_gate_cell(
-
-
-
- // USE_POWER_PINS
- .clk(clk_i),
- .clk_en(clk_gated_en),
- .clk_o(clk_g)
- );
-
- wire clk = clk_g;
- wire rst_n = (~rst_i);
-
-
- wire wb_valid = cyc_i & stb_i;
- wire wb_we = we_i & wb_valid;
- wire wb_re = ~we_i & wb_valid;
- wire[3:0] wb_byte_sel = sel_i & {4{wb_we}};
-
- wire [1-1:0] fifo_en;
- wire [1-1:0] fifo_rd;
- wire [AW-1:0] fifo_level_threshold;
- wire [1-1:0] fifo_flush;
- wire [1-1:0] fifo_full;
- wire [1-1:0] fifo_empty;
- wire [AW-1:0] fifo_level;
- wire [1-1:0] fifo_level_above;
- wire [32-1:0] fifo_rdata;
- wire [1-1:0] sign_extend;
- wire [1-1:0] left_justified;
- wire [6-1:0] sample_size;
- wire [8-1:0] sck_prescaler;
- wire [32-1:0] avg_threshold;
- wire [1-1:0] avg_flag;
- wire [1-1:0] avg_en;
- wire [1-1:0] avg_sel;
- wire [32-1:0] zcr_threshold;
- wire [1-1:0] zcr_flag;
- wire [1-1:0] zcr_en;
- wire [1-1:0] zcr_sel;
- wire [1-1:0] vad_flag;
- wire [2-1:0] channels;
- wire [1-1:0] en;
-
- // Register Definitions
- wire [32-1:0] RXDATA_WIRE;
-
- reg [7:0] PR_REG;
- assign sck_prescaler = PR_REG;
- always @(posedge clk_i or posedge rst_i) if(rst_i) PR_REG <= 0; else if(wb_we & (adr_i[16-1:0]==PR_REG_OFFSET)) PR_REG <= dat_i[8-1:0];
-
- reg [31:0] AVGT_REG;
- assign avg_threshold = AVGT_REG;
- always @(posedge clk_i or posedge rst_i) if(rst_i) AVGT_REG <= 0; else if(wb_we & (adr_i[16-1:0]==AVGT_REG_OFFSET)) AVGT_REG <= dat_i[32-1:0];
-
- reg [31:0] ZCRT_REG;
- assign zcr_threshold = ZCRT_REG;
- always @(posedge clk_i or posedge rst_i) if(rst_i) ZCRT_REG <= 0; else if(wb_we & (adr_i[16-1:0]==ZCRT_REG_OFFSET)) ZCRT_REG <= dat_i[32-1:0];
-
- reg [3:0] CTRL_REG;
- assign en = CTRL_REG[0 : 0];
- assign fifo_en = CTRL_REG[1 : 1];
- assign avg_en = CTRL_REG[2 : 2];
- assign zcr_en = CTRL_REG[3 : 3];
- always @(posedge clk_i or posedge rst_i) if(rst_i) CTRL_REG <= 'h0; else if(wb_we & (adr_i[16-1:0]==CTRL_REG_OFFSET)) CTRL_REG <= dat_i[4-1:0];
-
- reg [11:0] CFG_REG;
- assign channels = CFG_REG[1 : 0];
- assign sign_extend = CFG_REG[2 : 2];
- assign left_justified = CFG_REG[3 : 3];
- assign sample_size = CFG_REG[9 : 4];
- assign avg_sel = CFG_REG[10 : 10];
- assign zcr_sel = CFG_REG[11 : 11];
- always @(posedge clk_i or posedge rst_i) if(rst_i) CFG_REG <= 'h201; else if(wb_we & (adr_i[16-1:0]==CFG_REG_OFFSET)) CFG_REG <= dat_i[12-1:0];
-
- wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
- assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
-
- reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
- assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
- always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET)) RX_FIFO_THRESHOLD_REG <= dat_i[AW-1:0];
-
- reg [0:0] RX_FIFO_FLUSH_REG;
- assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
- always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
-
- localparam GCLK_REG_OFFSET = 16'hFF10;
- always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
-
- reg [5:0] IM_REG;
- reg [5:0] IC_REG;
- reg [5:0] RIS_REG;
-
- wire[6-1:0] MIS_REG = RIS_REG & IM_REG;
- always @(posedge clk_i or posedge rst_i) if(rst_i) IM_REG <= 0; else if(wb_we & (adr_i[16-1:0]==IM_REG_OFFSET)) IM_REG <= dat_i[6-1:0];
- always @(posedge clk_i or posedge rst_i) if(rst_i) IC_REG <= 6'b0;
- else if(wb_we & (adr_i[16-1:0]==IC_REG_OFFSET))
- IC_REG <= dat_i[6-1:0];
- else
- IC_REG <= 6'd0;
-
- wire [0:0] FIFOE = fifo_empty;
- wire [0:0] FIFOA = fifo_level_above;
- wire [0:0] FIFOF = fifo_full;
- wire [0:0] AVGF = avg_flag;
- wire [0:0] ZCRF = zcr_flag;
- wire [0:0] VADF = vad_flag;
-
-
- integer _i_;
- always @(posedge clk_i or posedge rst_i) if(rst_i) RIS_REG <= 0; else begin
- for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- end
-
- assign IRQ = |MIS_REG;
-
- reg [0:0] _sdi_reg_[1:0];
- wire _sdi_w_ = _sdi_reg_[1];
- always@(posedge clk_i or posedge rst_i)
- if(rst_i == 1) begin
- _sdi_reg_[0] <= 'b0;
- _sdi_reg_[1] <= 'b0;
- end
- else begin
- _sdi_reg_[0] <= sdi;
- _sdi_reg_[1] <= _sdi_reg_[0];
- end
- EF_I2S #(
- .DW(DW),
- .AW(AW)
- ) instance_to_wrap (
- .clk(clk),
- .rst_n(rst_n),
- .fifo_en(fifo_en),
- .fifo_rd(fifo_rd),
- .fifo_level_threshold(fifo_level_threshold),
- .fifo_flush(fifo_flush),
- .fifo_full(fifo_full),
- .fifo_empty(fifo_empty),
- .fifo_level(fifo_level),
- .fifo_level_above(fifo_level_above),
- .fifo_rdata(fifo_rdata),
- .sign_extend(sign_extend),
- .left_justified(left_justified),
- .sample_size(sample_size),
- .sck_prescaler(sck_prescaler),
- .avg_threshold(avg_threshold),
- .avg_flag(avg_flag),
- .avg_en(avg_en),
- .avg_sel(avg_sel),
- .zcr_threshold(zcr_threshold),
- .zcr_flag(zcr_flag),
- .zcr_en(zcr_en),
- .zcr_sel(zcr_sel),
- .vad_flag(vad_flag),
- .channels(channels),
- .en(en),
- .ws(ws),
- .sck(sck),
- .sdi(_sdi_w_)
- );
-
- assign dat_o =
- (adr_i[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
- (adr_i[16-1:0] == PR_REG_OFFSET) ? PR_REG :
- (adr_i[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
- (adr_i[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
- (adr_i[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
- (adr_i[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
- (adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
- (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
- (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
- (adr_i[16-1:0] == IM_REG_OFFSET) ? IM_REG :
- (adr_i[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
- (adr_i[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
- (adr_i[16-1:0] == IC_REG_OFFSET) ? IC_REG :
- 32'hDEADBEEF;
-
- always @ (posedge clk_i or posedge rst_i)
- if(rst_i)
- ack_o <= 1'b0;
- else if(wb_valid & ~ack_o)
- ack_o <= 1'b1;
- else
- ack_o <= 1'b0;
- assign RXDATA_WIRE = fifo_rdata;
- assign fifo_rd = ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
-endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.v
index bdcc08d..7776137 100644
--- a/hdl/rtl/bus_wrappers/EF_I2S_WB.v
+++ b/hdl/rtl/bus_wrappers/EF_I2S_WB.v
@@ -1,7 +1,7 @@
/*
Copyright 2024 Efabless Corp.
- Author: Mohamed Shalan (mshalan@efabless.com)
+ Author: Efabless Corp. (ip_admin@efabless.com)
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -19,240 +19,330 @@
/* THIS FILE IS GENERATED, DO NOT EDIT */
-`timescale 1ns/1ps
-`default_nettype none
+`timescale 1ns / 1ps `default_nettype none
-`define WB_AW 16
-`include "wb_wrapper.vh"
-module EF_I2S_WB #(
- parameter
- DW = 32,
- AW = 4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// PRINT_LICENSE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module EF_I2S_WB #(
+ parameter DW = 32,
+ AW = 4
) (
-`ifdef USE_POWER_PINS
- inout VPWR,
- inout VGND,
-`endif
- `WB_SLAVE_PORTS,
- output wire [1-1:0] ws,
- output wire [1-1:0] sck,
- input wire [1-1:0] sdi
+
+
+
+
+ input wire clk_i,
+ input wire rst_i,
+ input wire [ 31:0] adr_i,
+ input wire [ 31:0] dat_i,
+ output wire [ 31:0] dat_o,
+ input wire [ 3:0] sel_i,
+ input wire cyc_i,
+ input wire stb_i,
+ output reg ack_o,
+ input wire we_i,
+ output wire IRQ,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
);
- localparam RXDATA_REG_OFFSET = `WB_AW'h0000;
- localparam PR_REG_OFFSET = `WB_AW'h0004;
- localparam AVGT_REG_OFFSET = `WB_AW'h0008;
- localparam ZCRT_REG_OFFSET = `WB_AW'h000C;
- localparam CTRL_REG_OFFSET = `WB_AW'h0010;
- localparam CFG_REG_OFFSET = `WB_AW'h0014;
- localparam RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00;
- localparam RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04;
- localparam RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08;
- localparam IM_REG_OFFSET = `WB_AW'hFF00;
- localparam MIS_REG_OFFSET = `WB_AW'hFF04;
- localparam RIS_REG_OFFSET = `WB_AW'hFF08;
- localparam IC_REG_OFFSET = `WB_AW'hFF0C;
-
- reg [0:0] GCLK_REG;
- wire clk_g;
- wire clk_gated_en = GCLK_REG[0];
- ef_gating_cell clk_gate_cell(
- `ifdef USE_POWER_PINS
- .vpwr(VPWR),
- .vgnd(VGND),
- `endif // USE_POWER_PINS
- .clk(clk_i),
- .clk_en(clk_gated_en),
- .clk_o(clk_g)
- );
-
- wire clk = clk_g;
- wire rst_n = (~rst_i);
-
-
- `WB_CTRL_SIGNALS
-
- wire [1-1:0] fifo_en;
- wire [1-1:0] fifo_rd;
- wire [AW-1:0] fifo_level_threshold;
- wire [1-1:0] fifo_flush;
- wire [1-1:0] fifo_full;
- wire [1-1:0] fifo_empty;
- wire [AW-1:0] fifo_level;
- wire [1-1:0] fifo_level_above;
- wire [32-1:0] fifo_rdata;
- wire [1-1:0] sign_extend;
- wire [1-1:0] left_justified;
- wire [6-1:0] sample_size;
- wire [8-1:0] sck_prescaler;
- wire [32-1:0] avg_threshold;
- wire [1-1:0] avg_flag;
- wire [1-1:0] avg_en;
- wire [1-1:0] avg_sel;
- wire [32-1:0] zcr_threshold;
- wire [1-1:0] zcr_flag;
- wire [1-1:0] zcr_en;
- wire [1-1:0] zcr_sel;
- wire [1-1:0] vad_flag;
- wire [2-1:0] channels;
- wire [1-1:0] en;
-
- // Register Definitions
- wire [32-1:0] RXDATA_WIRE;
-
- reg [7:0] PR_REG;
- assign sck_prescaler = PR_REG;
- `WB_REG(PR_REG, 0, 8)
-
- reg [31:0] AVGT_REG;
- assign avg_threshold = AVGT_REG;
- `WB_REG(AVGT_REG, 0, 32)
-
- reg [31:0] ZCRT_REG;
- assign zcr_threshold = ZCRT_REG;
- `WB_REG(ZCRT_REG, 0, 32)
-
- reg [3:0] CTRL_REG;
- assign en = CTRL_REG[0 : 0];
- assign fifo_en = CTRL_REG[1 : 1];
- assign avg_en = CTRL_REG[2 : 2];
- assign zcr_en = CTRL_REG[3 : 3];
- `WB_REG(CTRL_REG, 'h0, 4)
-
- reg [11:0] CFG_REG;
- assign channels = CFG_REG[1 : 0];
- assign sign_extend = CFG_REG[2 : 2];
- assign left_justified = CFG_REG[3 : 3];
- assign sample_size = CFG_REG[9 : 4];
- assign avg_sel = CFG_REG[10 : 10];
- assign zcr_sel = CFG_REG[11 : 11];
- `WB_REG(CFG_REG, 'h201, 12)
-
- wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
- assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
-
- reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
- assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
- `WB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
-
- reg [0:0] RX_FIFO_FLUSH_REG;
- assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
- `WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
-
- localparam GCLK_REG_OFFSET = `WB_AW'hFF10;
- `WB_REG(GCLK_REG, 0, 1)
-
- reg [5:0] IM_REG;
- reg [5:0] IC_REG;
- reg [5:0] RIS_REG;
-
- `WB_MIS_REG(6)
- `WB_REG(IM_REG, 0, 6)
- `WB_IC_REG(6)
-
- wire [0:0] FIFOE = fifo_empty;
- wire [0:0] FIFOA = fifo_level_above;
- wire [0:0] FIFOF = fifo_full;
- wire [0:0] AVGF = avg_flag;
- wire [0:0] ZCRF = zcr_flag;
- wire [0:0] VADF = vad_flag;
-
-
- integer _i_;
- `WB_BLOCK(RIS_REG, 0) else begin
- for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
- if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
- end
- end
-
- assign IRQ = |MIS_REG;
-
- reg [0:0] _sdi_reg_[1:0];
- wire _sdi_w_ = _sdi_reg_[1];
- always@(posedge clk_i or posedge rst_i)
- if(rst_i == 1) begin
- _sdi_reg_[0] <= 'b0;
- _sdi_reg_[1] <= 'b0;
- end
- else begin
- _sdi_reg_[0] <= sdi;
- _sdi_reg_[1] <= _sdi_reg_[0];
- end
- EF_I2S #(
- .DW(DW),
- .AW(AW)
- ) instance_to_wrap (
- .clk(clk),
- .rst_n(rst_n),
- .fifo_en(fifo_en),
- .fifo_rd(fifo_rd),
- .fifo_level_threshold(fifo_level_threshold),
- .fifo_flush(fifo_flush),
- .fifo_full(fifo_full),
- .fifo_empty(fifo_empty),
- .fifo_level(fifo_level),
- .fifo_level_above(fifo_level_above),
- .fifo_rdata(fifo_rdata),
- .sign_extend(sign_extend),
- .left_justified(left_justified),
- .sample_size(sample_size),
- .sck_prescaler(sck_prescaler),
- .avg_threshold(avg_threshold),
- .avg_flag(avg_flag),
- .avg_en(avg_en),
- .avg_sel(avg_sel),
- .zcr_threshold(zcr_threshold),
- .zcr_flag(zcr_flag),
- .zcr_en(zcr_en),
- .zcr_sel(zcr_sel),
- .vad_flag(vad_flag),
- .channels(channels),
- .en(en),
- .ws(ws),
- .sck(sck),
- .sdi(_sdi_w_)
- );
-
- assign dat_o =
- (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
- (adr_i[`WB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
- (adr_i[`WB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
- (adr_i[`WB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
- (adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
- (adr_i[`WB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
- (adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
- (adr_i[`WB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
- (adr_i[`WB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
- (adr_i[`WB_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
- (adr_i[`WB_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
- (adr_i[`WB_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
- (adr_i[`WB_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
+ localparam RXDATA_REG_OFFSET = 16'h0000;
+ localparam PR_REG_OFFSET = 16'h0004;
+ localparam AVGT_REG_OFFSET = 16'h0008;
+ localparam ZCRT_REG_OFFSET = 16'h000C;
+ localparam CTRL_REG_OFFSET = 16'h0010;
+ localparam CFG_REG_OFFSET = 16'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+ localparam IM_REG_OFFSET = 16'hFF00;
+ localparam MIS_REG_OFFSET = 16'hFF04;
+ localparam RIS_REG_OFFSET = 16'hFF08;
+ localparam IC_REG_OFFSET = 16'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell (
+
+
+
+ // USE_POWER_PINS
+ .clk(clk_i),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = (~rst_i);
+
+
+ wire wb_valid = cyc_i & stb_i;
+ wire wb_we = we_i & wb_valid;
+ wire wb_re = ~we_i & wb_valid;
+ wire [ 3:0] wb_byte_sel = sel_i & {4{wb_we}};
+
+ wire [ 1-1:0] fifo_en;
+ wire [ 1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [ 1-1:0] fifo_flush;
+ wire [ 1-1:0] fifo_full;
+ wire [ 1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [ 1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [ 1-1:0] sign_extend;
+ wire [ 1-1:0] left_justified;
+ wire [ 6-1:0] sample_size;
+ wire [ 8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [ 1-1:0] avg_flag;
+ wire [ 1-1:0] avg_en;
+ wire [ 1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [ 1-1:0] zcr_flag;
+ wire [ 1-1:0] zcr_en;
+ wire [ 1-1:0] zcr_sel;
+ wire [ 1-1:0] vad_flag;
+ wire [ 2-1:0] channels;
+ wire [ 1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [ 7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) PR_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == PR_REG_OFFSET)) PR_REG <= dat_i[8-1:0];
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) AVGT_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == AVGT_REG_OFFSET)) AVGT_REG <= dat_i[32-1:0];
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) ZCRT_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == ZCRT_REG_OFFSET)) ZCRT_REG <= dat_i[32-1:0];
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) CTRL_REG <= 'h0;
+ else if (wb_we & (adr_i[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= dat_i[4-1:0];
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) CFG_REG <= 'h201;
+ else if (wb_we & (adr_i[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= dat_i[12-1:0];
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW-1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW-1) : 0];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) RX_FIFO_THRESHOLD_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+ RX_FIFO_THRESHOLD_REG <= dat_i[AW-1:0];
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) RX_FIFO_FLUSH_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0];
+ else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+ localparam GCLK_REG_OFFSET = 16'hFF10;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) GCLK_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
+
+ reg [ 5:0] IM_REG;
+ reg [ 5:0] IC_REG;
+ reg [ 5:0] RIS_REG;
+
+ wire [6-1:0] MIS_REG = RIS_REG & IM_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) IM_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == IM_REG_OFFSET)) IM_REG <= dat_i[6-1:0];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) IC_REG <= 6'b0;
+ else if (wb_we & (adr_i[16-1:0] == IC_REG_OFFSET)) IC_REG <= dat_i[6-1:0];
+ else IC_REG <= 6'd0;
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) RIS_REG <= 0;
+ else begin
+ for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOA[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOF[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (AVGF[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (ZCRF[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (VADF[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i == 1) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign dat_o =
+ (adr_i[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (adr_i[16-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (adr_i[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (adr_i[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (adr_i[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (adr_i[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (adr_i[16-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (adr_i[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (adr_i[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (adr_i[16-1:0] == IC_REG_OFFSET) ? IC_REG :
32'hDEADBEEF;
- always @ (posedge clk_i or posedge rst_i)
- if(rst_i)
- ack_o <= 1'b0;
- else if(wb_valid & ~ack_o)
- ack_o <= 1'b1;
- else
- ack_o <= 1'b0;
- assign RXDATA_WIRE = fifo_rdata;
- assign fifo_rd = ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) ack_o <= 1'b0;
+ else if (wb_valid & ~ack_o) ack_o <= 1'b1;
+ else ack_o <= 1'b0;
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_I2S_AHBL_DFT.dev.v b/hdl/rtl/bus_wrappers/dft/EF_I2S_AHBL_DFT.dev.v
new file mode 100644
index 0000000..d87c7db
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_I2S_AHBL_DFT.dev.v
@@ -0,0 +1,255 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns/1ps
+`default_nettype none
+
+`define AHBL_AW 16
+
+`include "ahbl_wrapper.vh"
+
+module EF_I2S_AHBL #(
+ parameter
+ DW = 32,
+ AW = 4
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ input wire sc_testmode,
+ `AHBL_SLAVE_PORTS,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = `AHBL_AW'h0000;
+ localparam PR_REG_OFFSET = `AHBL_AW'h0004;
+ localparam AVGT_REG_OFFSET = `AHBL_AW'h0008;
+ localparam ZCRT_REG_OFFSET = `AHBL_AW'h000C;
+ localparam CTRL_REG_OFFSET = `AHBL_AW'h0010;
+ localparam CFG_REG_OFFSET = `AHBL_AW'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08;
+ localparam IM_REG_OFFSET = `AHBL_AW'hFF00;
+ localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
+ localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
+ localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell(
+ `ifdef USE_POWER_PINS
+ .vpwr(VPWR),
+ .vgnd(VGND),
+ `endif // USE_POWER_PINS
+ .clk(HCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = HRESETn;
+
+
+ `AHBL_CTRL_SIGNALS
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ `AHBL_REG(PR_REG, 0, 8)
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ `AHBL_REG(AVGT_REG, 0, 32)
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ `AHBL_REG(ZCRT_REG, 0, 32)
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ `AHBL_REG(CTRL_REG, 'h0, 4)
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ `AHBL_REG(CFG_REG, 'h201, 12)
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+ `AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ `AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+ localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
+ `AHBL_REG(GCLK_REG, 0, 1)
+
+ reg [5:0] IM_REG;
+ reg [5:0] IC_REG;
+ reg [5:0] RIS_REG;
+
+ `AHBL_MIS_REG(6)
+ `AHBL_REG(IM_REG, 0, 6)
+ `AHBL_IC_REG(6)
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ `AHBL_BLOCK(RIS_REG, 0) else begin
+ for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always@(posedge HCLK or negedge HRESETn)
+ if(HRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end
+ else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign HRDATA =
+ (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (last_HADDR[`AHBL_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (last_HADDR[`AHBL_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (last_HADDR[`AHBL_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ 32'hDEADBEEF;
+
+ assign HREADYOUT = 1'b1;
+
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_I2S_AHBL_DFT.v b/hdl/rtl/bus_wrappers/dft/EF_I2S_AHBL_DFT.v
new file mode 100644
index 0000000..4b0ba4e
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_I2S_AHBL_DFT.v
@@ -0,0 +1,386 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns / 1ps `default_nettype none
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// PRINT_LICENSE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module EF_I2S_AHBL #(
+ parameter DW = 32,
+ AW = 4
+) (
+
+
+
+
+ input wire sc_testmode,
+ input wire HCLK,
+ input wire HRESETn,
+ input wire HWRITE,
+ input wire [ 31:0] HWDATA,
+ input wire [ 31:0] HADDR,
+ input wire [ 1:0] HTRANS,
+ input wire HSEL,
+ input wire HREADY,
+ output wire HREADYOUT,
+ output wire [ 31:0] HRDATA,
+ output wire IRQ,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = 16'h0000;
+ localparam PR_REG_OFFSET = 16'h0004;
+ localparam AVGT_REG_OFFSET = 16'h0008;
+ localparam ZCRT_REG_OFFSET = 16'h000C;
+ localparam CTRL_REG_OFFSET = 16'h0010;
+ localparam CFG_REG_OFFSET = 16'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+ localparam IM_REG_OFFSET = 16'hFF00;
+ localparam MIS_REG_OFFSET = 16'hFF04;
+ localparam RIS_REG_OFFSET = 16'hFF08;
+ localparam IC_REG_OFFSET = 16'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell (
+
+
+
+ // USE_POWER_PINS
+ .clk(HCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = HRESETn;
+
+
+ reg last_HSEL, last_HWRITE;
+ reg [31:0] last_HADDR;
+ reg [ 1:0] last_HTRANS;
+ always @(posedge HCLK or negedge HRESETn) begin
+ if (~HRESETn) begin
+ last_HSEL <= 1'b0;
+ last_HADDR <= 1'b0;
+ last_HWRITE <= 1'b0;
+ last_HTRANS <= 1'b0;
+ end else if (HREADY) begin
+ last_HSEL <= HSEL;
+ last_HADDR <= HADDR;
+ last_HWRITE <= HWRITE;
+ last_HTRANS <= HTRANS;
+ end
+ end
+ wire ahbl_valid = last_HSEL & last_HTRANS[1];
+ wire ahbl_we = last_HWRITE & ahbl_valid;
+ wire ahbl_re = ~last_HWRITE & ahbl_valid;
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) PR_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= HWDATA[8-1:0];
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) AVGT_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == AVGT_REG_OFFSET)) AVGT_REG <= HWDATA[32-1:0];
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) ZCRT_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == ZCRT_REG_OFFSET)) ZCRT_REG <= HWDATA[32-1:0];
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) CTRL_REG <= 'h0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= HWDATA[4-1:0];
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) CFG_REG <= 'h201;
+ else if (ahbl_we & (last_HADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= HWDATA[12-1:0];
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW-1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW-1) : 0];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+ RX_FIFO_THRESHOLD_REG <= HWDATA[AW-1:0];
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) RX_FIFO_FLUSH_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+ RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+ else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+ localparam GCLK_REG_OFFSET = 16'hFF10;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) GCLK_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= HWDATA[1-1:0];
+
+ reg [ 5:0] IM_REG;
+ reg [ 5:0] IC_REG;
+ reg [ 5:0] RIS_REG;
+
+ wire [6-1:0] MIS_REG = RIS_REG & IM_REG;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) IM_REG <= 0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= HWDATA[6-1:0];
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) IC_REG <= 6'b0;
+ else if (ahbl_we & (last_HADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= HWDATA[6-1:0];
+ else IC_REG <= 6'd0;
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ always @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) RIS_REG <= 0;
+ else begin
+ for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOA[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOF[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (AVGF[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (ZCRF[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (VADF[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always @(posedge HCLK or negedge HRESETn)
+ if (HRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign HRDATA =
+ (last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (last_HADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (last_HADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (last_HADDR[16-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ 32'hDEADBEEF;
+
+ assign HREADYOUT = 1'b1;
+
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_I2S_APB_DFT.dev.v b/hdl/rtl/bus_wrappers/dft/EF_I2S_APB_DFT.dev.v
new file mode 100644
index 0000000..9a8fccd
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_I2S_APB_DFT.dev.v
@@ -0,0 +1,255 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns/1ps
+`default_nettype none
+
+`define APB_AW 16
+
+`include "apb_wrapper.vh"
+
+module EF_I2S_APB #(
+ parameter
+ DW = 32,
+ AW = 4
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ input wire sc_testmode,
+ `APB_SLAVE_PORTS,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = `APB_AW'h0000;
+ localparam PR_REG_OFFSET = `APB_AW'h0004;
+ localparam AVGT_REG_OFFSET = `APB_AW'h0008;
+ localparam ZCRT_REG_OFFSET = `APB_AW'h000C;
+ localparam CTRL_REG_OFFSET = `APB_AW'h0010;
+ localparam CFG_REG_OFFSET = `APB_AW'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = `APB_AW'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = `APB_AW'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = `APB_AW'hFE08;
+ localparam IM_REG_OFFSET = `APB_AW'hFF00;
+ localparam MIS_REG_OFFSET = `APB_AW'hFF04;
+ localparam RIS_REG_OFFSET = `APB_AW'hFF08;
+ localparam IC_REG_OFFSET = `APB_AW'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell(
+ `ifdef USE_POWER_PINS
+ .vpwr(VPWR),
+ .vgnd(VGND),
+ `endif // USE_POWER_PINS
+ .clk(PCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = PRESETn;
+
+
+ `APB_CTRL_SIGNALS
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ `APB_REG(PR_REG, 0, 8)
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ `APB_REG(AVGT_REG, 0, 32)
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ `APB_REG(ZCRT_REG, 0, 32)
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ `APB_REG(CTRL_REG, 'h0, 4)
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ `APB_REG(CFG_REG, 'h201, 12)
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+ `APB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ `APB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+ localparam GCLK_REG_OFFSET = `APB_AW'hFF10;
+ `APB_REG(GCLK_REG, 0, 1)
+
+ reg [5:0] IM_REG;
+ reg [5:0] IC_REG;
+ reg [5:0] RIS_REG;
+
+ `APB_MIS_REG(6)
+ `APB_REG(IM_REG, 0, 6)
+ `APB_IC_REG(6)
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ `APB_BLOCK(RIS_REG, 0) else begin
+ for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always@(posedge PCLK or negedge PRESETn)
+ if(PRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end
+ else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign PRDATA =
+ (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (PADDR[`APB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (PADDR[`APB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (PADDR[`APB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (PADDR[`APB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (PADDR[`APB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (PADDR[`APB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (PADDR[`APB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (PADDR[`APB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (PADDR[`APB_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (PADDR[`APB_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (PADDR[`APB_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ 32'hDEADBEEF;
+
+ assign PREADY = 1'b1;
+
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_I2S_APB_DFT.v b/hdl/rtl/bus_wrappers/dft/EF_I2S_APB_DFT.v
new file mode 100644
index 0000000..1bca4fd
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_I2S_APB_DFT.v
@@ -0,0 +1,368 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns / 1ps `default_nettype none
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// PRINT_LICENSE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module EF_I2S_APB #(
+ parameter DW = 32,
+ AW = 4
+) (
+
+
+
+
+ input wire sc_testmode,
+ input wire PCLK,
+ input wire PRESETn,
+ input wire PWRITE,
+ input wire [ 31:0] PWDATA,
+ input wire [ 31:0] PADDR,
+ input wire PENABLE,
+ input wire PSEL,
+ output wire PREADY,
+ output wire [ 31:0] PRDATA,
+ output wire IRQ,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = 16'h0000;
+ localparam PR_REG_OFFSET = 16'h0004;
+ localparam AVGT_REG_OFFSET = 16'h0008;
+ localparam ZCRT_REG_OFFSET = 16'h000C;
+ localparam CTRL_REG_OFFSET = 16'h0010;
+ localparam CFG_REG_OFFSET = 16'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+ localparam IM_REG_OFFSET = 16'hFF00;
+ localparam MIS_REG_OFFSET = 16'hFF04;
+ localparam RIS_REG_OFFSET = 16'hFF08;
+ localparam IC_REG_OFFSET = 16'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell (
+
+
+
+ // USE_POWER_PINS
+ .clk(PCLK),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = PRESETn;
+
+
+ wire apb_valid = PSEL & PENABLE;
+ wire apb_we = PWRITE & apb_valid;
+ wire apb_re = ~PWRITE & apb_valid;
+
+ wire [ 1-1:0] fifo_en;
+ wire [ 1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [ 1-1:0] fifo_flush;
+ wire [ 1-1:0] fifo_full;
+ wire [ 1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [ 1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [ 1-1:0] sign_extend;
+ wire [ 1-1:0] left_justified;
+ wire [ 6-1:0] sample_size;
+ wire [ 8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [ 1-1:0] avg_flag;
+ wire [ 1-1:0] avg_en;
+ wire [ 1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [ 1-1:0] zcr_flag;
+ wire [ 1-1:0] zcr_en;
+ wire [ 1-1:0] zcr_sel;
+ wire [ 1-1:0] vad_flag;
+ wire [ 2-1:0] channels;
+ wire [ 1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [ 7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) PR_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == PR_REG_OFFSET)) PR_REG <= PWDATA[8-1:0];
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) AVGT_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == AVGT_REG_OFFSET)) AVGT_REG <= PWDATA[32-1:0];
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) ZCRT_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == ZCRT_REG_OFFSET)) ZCRT_REG <= PWDATA[32-1:0];
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) CTRL_REG <= 'h0;
+ else if (apb_we & (PADDR[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= PWDATA[4-1:0];
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) CFG_REG <= 'h201;
+ else if (apb_we & (PADDR[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= PWDATA[12-1:0];
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW-1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW-1) : 0];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+ RX_FIFO_THRESHOLD_REG <= PWDATA[AW-1:0];
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) RX_FIFO_FLUSH_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET))
+ RX_FIFO_FLUSH_REG <= PWDATA[1-1:0];
+ else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+ localparam GCLK_REG_OFFSET = 16'hFF10;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) GCLK_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= PWDATA[1-1:0];
+
+ reg [ 5:0] IM_REG;
+ reg [ 5:0] IC_REG;
+ reg [ 5:0] RIS_REG;
+
+ wire [6-1:0] MIS_REG = RIS_REG & IM_REG;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) IM_REG <= 0;
+ else if (apb_we & (PADDR[16-1:0] == IM_REG_OFFSET)) IM_REG <= PWDATA[6-1:0];
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) IC_REG <= 6'b0;
+ else if (apb_we & (PADDR[16-1:0] == IC_REG_OFFSET)) IC_REG <= PWDATA[6-1:0];
+ else IC_REG <= 6'd0;
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ always @(posedge PCLK or negedge PRESETn)
+ if (~PRESETn) RIS_REG <= 0;
+ else begin
+ for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOA[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOF[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (AVGF[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (ZCRF[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (VADF[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always @(posedge PCLK or negedge PRESETn)
+ if (PRESETn == 0) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign PRDATA =
+ (PADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (PADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (PADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (PADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (PADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (PADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (PADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (PADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (PADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (PADDR[16-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (PADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (PADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (PADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
+ 32'hDEADBEEF;
+
+ assign PREADY = 1'b1;
+
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_I2S_WB_DFT.dev.v b/hdl/rtl/bus_wrappers/dft/EF_I2S_WB_DFT.dev.v
new file mode 100644
index 0000000..f84aa0f
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_I2S_WB_DFT.dev.v
@@ -0,0 +1,260 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns/1ps
+`default_nettype none
+
+`define WB_AW 16
+
+`include "wb_wrapper.vh"
+
+module EF_I2S_WB #(
+ parameter
+ DW = 32,
+ AW = 4
+) (
+`ifdef USE_POWER_PINS
+ inout VPWR,
+ inout VGND,
+`endif
+ input wire sc_testmode,
+ `WB_SLAVE_PORTS,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = `WB_AW'h0000;
+ localparam PR_REG_OFFSET = `WB_AW'h0004;
+ localparam AVGT_REG_OFFSET = `WB_AW'h0008;
+ localparam ZCRT_REG_OFFSET = `WB_AW'h000C;
+ localparam CTRL_REG_OFFSET = `WB_AW'h0010;
+ localparam CFG_REG_OFFSET = `WB_AW'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08;
+ localparam IM_REG_OFFSET = `WB_AW'hFF00;
+ localparam MIS_REG_OFFSET = `WB_AW'hFF04;
+ localparam RIS_REG_OFFSET = `WB_AW'hFF08;
+ localparam IC_REG_OFFSET = `WB_AW'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell(
+ `ifdef USE_POWER_PINS
+ .vpwr(VPWR),
+ .vgnd(VGND),
+ `endif // USE_POWER_PINS
+ .clk(clk_i),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = (~rst_i);
+
+
+ `WB_CTRL_SIGNALS
+
+ wire [1-1:0] fifo_en;
+ wire [1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [1-1:0] fifo_flush;
+ wire [1-1:0] fifo_full;
+ wire [1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [1-1:0] sign_extend;
+ wire [1-1:0] left_justified;
+ wire [6-1:0] sample_size;
+ wire [8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [1-1:0] avg_flag;
+ wire [1-1:0] avg_en;
+ wire [1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [1-1:0] zcr_flag;
+ wire [1-1:0] zcr_en;
+ wire [1-1:0] zcr_sel;
+ wire [1-1:0] vad_flag;
+ wire [2-1:0] channels;
+ wire [1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ `WB_REG(PR_REG, 0, 8)
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ `WB_REG(AVGT_REG, 0, 32)
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ `WB_REG(ZCRT_REG, 0, 32)
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ `WB_REG(CTRL_REG, 'h0, 4)
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ `WB_REG(CFG_REG, 'h201, 12)
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+ `WB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ `WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0)
+
+ localparam GCLK_REG_OFFSET = `WB_AW'hFF10;
+ `WB_REG(GCLK_REG, 0, 1)
+
+ reg [5:0] IM_REG;
+ reg [5:0] IC_REG;
+ reg [5:0] RIS_REG;
+
+ `WB_MIS_REG(6)
+ `WB_REG(IM_REG, 0, 6)
+ `WB_IC_REG(6)
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ `WB_BLOCK(RIS_REG, 0) else begin
+ for(_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOE[_i_ - 0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOA[_i_ - 1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(FIFOF[_i_ - 2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always@(posedge clk_i or posedge rst_i)
+ if(rst_i == 1) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end
+ else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign dat_o =
+ (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (adr_i[`WB_AW-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (adr_i[`WB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (adr_i[`WB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (adr_i[`WB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (adr_i[`WB_AW-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (adr_i[`WB_AW-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (adr_i[`WB_AW-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (adr_i[`WB_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (adr_i[`WB_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (adr_i[`WB_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
+ 32'hDEADBEEF;
+
+ always @ (posedge clk_i or posedge rst_i)
+ if(rst_i)
+ ack_o <= 1'b0;
+ else if(wb_valid & ~ack_o)
+ ack_o <= 1'b1;
+ else
+ ack_o <= 1'b0;
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/hdl/rtl/bus_wrappers/dft/EF_I2S_WB_DFT.v b/hdl/rtl/bus_wrappers/dft/EF_I2S_WB_DFT.v
new file mode 100644
index 0000000..1735ad5
--- /dev/null
+++ b/hdl/rtl/bus_wrappers/dft/EF_I2S_WB_DFT.v
@@ -0,0 +1,349 @@
+/*
+ Copyright 2024 Efabless Corp.
+
+ Author: Efabless Corp. (ip_admin@efabless.com)
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+*/
+
+/* THIS FILE IS GENERATED, DO NOT EDIT */
+
+`timescale 1ns / 1ps `default_nettype none
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// PRINT_LICENSE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+module EF_I2S_WB #(
+ parameter DW = 32,
+ AW = 4
+) (
+
+
+
+
+ input wire sc_testmode,
+ input wire clk_i,
+ input wire rst_i,
+ input wire [ 31:0] adr_i,
+ input wire [ 31:0] dat_i,
+ output wire [ 31:0] dat_o,
+ input wire [ 3:0] sel_i,
+ input wire cyc_i,
+ input wire stb_i,
+ output reg ack_o,
+ input wire we_i,
+ output wire IRQ,
+ output wire [1-1:0] ws,
+ output wire [1-1:0] sck,
+ input wire [1-1:0] sdi
+);
+
+ localparam RXDATA_REG_OFFSET = 16'h0000;
+ localparam PR_REG_OFFSET = 16'h0004;
+ localparam AVGT_REG_OFFSET = 16'h0008;
+ localparam ZCRT_REG_OFFSET = 16'h000C;
+ localparam CTRL_REG_OFFSET = 16'h0010;
+ localparam CFG_REG_OFFSET = 16'h0014;
+ localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+ localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+ localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+ localparam IM_REG_OFFSET = 16'hFF00;
+ localparam MIS_REG_OFFSET = 16'hFF04;
+ localparam RIS_REG_OFFSET = 16'hFF08;
+ localparam IC_REG_OFFSET = 16'hFF0C;
+
+ reg [0:0] GCLK_REG;
+ wire clk_g;
+
+ wire clk_gated_en = sc_testmode ? 1'b1 : GCLK_REG[0];
+ ef_util_gating_cell clk_gate_cell (
+
+
+
+ // USE_POWER_PINS
+ .clk(clk_i),
+ .clk_en(clk_gated_en),
+ .clk_o(clk_g)
+ );
+
+ wire clk = clk_g;
+ wire rst_n = (~rst_i);
+
+
+ wire wb_valid = cyc_i & stb_i;
+ wire wb_we = we_i & wb_valid;
+ wire wb_re = ~we_i & wb_valid;
+ wire [ 3:0] wb_byte_sel = sel_i & {4{wb_we}};
+
+ wire [ 1-1:0] fifo_en;
+ wire [ 1-1:0] fifo_rd;
+ wire [AW-1:0] fifo_level_threshold;
+ wire [ 1-1:0] fifo_flush;
+ wire [ 1-1:0] fifo_full;
+ wire [ 1-1:0] fifo_empty;
+ wire [AW-1:0] fifo_level;
+ wire [ 1-1:0] fifo_level_above;
+ wire [32-1:0] fifo_rdata;
+ wire [ 1-1:0] sign_extend;
+ wire [ 1-1:0] left_justified;
+ wire [ 6-1:0] sample_size;
+ wire [ 8-1:0] sck_prescaler;
+ wire [32-1:0] avg_threshold;
+ wire [ 1-1:0] avg_flag;
+ wire [ 1-1:0] avg_en;
+ wire [ 1-1:0] avg_sel;
+ wire [32-1:0] zcr_threshold;
+ wire [ 1-1:0] zcr_flag;
+ wire [ 1-1:0] zcr_en;
+ wire [ 1-1:0] zcr_sel;
+ wire [ 1-1:0] vad_flag;
+ wire [ 2-1:0] channels;
+ wire [ 1-1:0] en;
+
+ // Register Definitions
+ wire [32-1:0] RXDATA_WIRE;
+
+ reg [ 7:0] PR_REG;
+ assign sck_prescaler = PR_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) PR_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == PR_REG_OFFSET)) PR_REG <= dat_i[8-1:0];
+
+ reg [31:0] AVGT_REG;
+ assign avg_threshold = AVGT_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) AVGT_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == AVGT_REG_OFFSET)) AVGT_REG <= dat_i[32-1:0];
+
+ reg [31:0] ZCRT_REG;
+ assign zcr_threshold = ZCRT_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) ZCRT_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == ZCRT_REG_OFFSET)) ZCRT_REG <= dat_i[32-1:0];
+
+ reg [3:0] CTRL_REG;
+ assign en = CTRL_REG[0 : 0];
+ assign fifo_en = CTRL_REG[1 : 1];
+ assign avg_en = CTRL_REG[2 : 2];
+ assign zcr_en = CTRL_REG[3 : 3];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) CTRL_REG <= 'h0;
+ else if (wb_we & (adr_i[16-1:0] == CTRL_REG_OFFSET)) CTRL_REG <= dat_i[4-1:0];
+
+ reg [11:0] CFG_REG;
+ assign channels = CFG_REG[1 : 0];
+ assign sign_extend = CFG_REG[2 : 2];
+ assign left_justified = CFG_REG[3 : 3];
+ assign sample_size = CFG_REG[9 : 4];
+ assign avg_sel = CFG_REG[10 : 10];
+ assign zcr_sel = CFG_REG[11 : 11];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) CFG_REG <= 'h201;
+ else if (wb_we & (adr_i[16-1:0] == CFG_REG_OFFSET)) CFG_REG <= dat_i[12-1:0];
+
+ wire [AW-1:0] RX_FIFO_LEVEL_WIRE;
+ assign RX_FIFO_LEVEL_WIRE[(AW-1) : 0] = fifo_level;
+
+ reg [AW-1:0] RX_FIFO_THRESHOLD_REG;
+ assign fifo_level_threshold = RX_FIFO_THRESHOLD_REG[(AW-1) : 0];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) RX_FIFO_THRESHOLD_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET))
+ RX_FIFO_THRESHOLD_REG <= dat_i[AW-1:0];
+
+ reg [0:0] RX_FIFO_FLUSH_REG;
+ assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) RX_FIFO_FLUSH_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0];
+ else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+ localparam GCLK_REG_OFFSET = 16'hFF10;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) GCLK_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];
+
+ reg [ 5:0] IM_REG;
+ reg [ 5:0] IC_REG;
+ reg [ 5:0] RIS_REG;
+
+ wire [6-1:0] MIS_REG = RIS_REG & IM_REG;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) IM_REG <= 0;
+ else if (wb_we & (adr_i[16-1:0] == IM_REG_OFFSET)) IM_REG <= dat_i[6-1:0];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) IC_REG <= 6'b0;
+ else if (wb_we & (adr_i[16-1:0] == IC_REG_OFFSET)) IC_REG <= dat_i[6-1:0];
+ else IC_REG <= 6'd0;
+
+ wire [0:0] FIFOE = fifo_empty;
+ wire [0:0] FIFOA = fifo_level_above;
+ wire [0:0] FIFOF = fifo_full;
+ wire [0:0] AVGF = avg_flag;
+ wire [0:0] ZCRF = zcr_flag;
+ wire [0:0] VADF = vad_flag;
+
+
+ integer _i_;
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) RIS_REG <= 0;
+ else begin
+ for (_i_ = 0; _i_ < 1; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOE[_i_-0] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 1; _i_ < 2; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOA[_i_-1] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 2; _i_ < 3; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (FIFOF[_i_-2] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (AVGF[_i_-3] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (ZCRF[_i_-4] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ for (_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin
+ if (IC_REG[_i_]) RIS_REG[_i_] <= 1'b0;
+ else if (VADF[_i_-5] == 1'b1) RIS_REG[_i_] <= 1'b1;
+ end
+ end
+
+ assign IRQ = |MIS_REG;
+
+ reg [0:0] _sdi_reg_[1:0];
+ wire _sdi_w_ = _sdi_reg_[1];
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i == 1) begin
+ _sdi_reg_[0] <= 'b0;
+ _sdi_reg_[1] <= 'b0;
+ end else begin
+ _sdi_reg_[0] <= sdi;
+ _sdi_reg_[1] <= _sdi_reg_[0];
+ end
+ EF_I2S #(
+ .DW(DW),
+ .AW(AW)
+ ) instance_to_wrap (
+ .clk(clk),
+ .rst_n(rst_n),
+ .fifo_en(fifo_en),
+ .fifo_rd(fifo_rd),
+ .fifo_level_threshold(fifo_level_threshold),
+ .fifo_flush(fifo_flush),
+ .fifo_full(fifo_full),
+ .fifo_empty(fifo_empty),
+ .fifo_level(fifo_level),
+ .fifo_level_above(fifo_level_above),
+ .fifo_rdata(fifo_rdata),
+ .sign_extend(sign_extend),
+ .left_justified(left_justified),
+ .sample_size(sample_size),
+ .sck_prescaler(sck_prescaler),
+ .avg_threshold(avg_threshold),
+ .avg_flag(avg_flag),
+ .avg_en(avg_en),
+ .avg_sel(avg_sel),
+ .zcr_threshold(zcr_threshold),
+ .zcr_flag(zcr_flag),
+ .zcr_en(zcr_en),
+ .zcr_sel(zcr_sel),
+ .vad_flag(vad_flag),
+ .channels(channels),
+ .en(en),
+ .ws(ws),
+ .sck(sck),
+ .sdi(_sdi_w_)
+ );
+
+ assign dat_o =
+ (adr_i[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE :
+ (adr_i[16-1:0] == PR_REG_OFFSET) ? PR_REG :
+ (adr_i[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG :
+ (adr_i[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG :
+ (adr_i[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG :
+ (adr_i[16-1:0] == CFG_REG_OFFSET) ? CFG_REG :
+ (adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE :
+ (adr_i[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET) ? RX_FIFO_THRESHOLD_REG :
+ (adr_i[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET) ? RX_FIFO_FLUSH_REG :
+ (adr_i[16-1:0] == IM_REG_OFFSET) ? IM_REG :
+ (adr_i[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
+ (adr_i[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
+ (adr_i[16-1:0] == IC_REG_OFFSET) ? IC_REG :
+ 32'hDEADBEEF;
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i) ack_o <= 1'b0;
+ else if (wb_valid & ~ack_o) ack_o <= 1'b1;
+ else ack_o <= 1'b0;
+ assign RXDATA_WIRE = fifo_rdata;
+ assign fifo_rd = ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
+endmodule
diff --git a/ip/dependencies.json b/ip/dependencies.json
index bc86f84..2474569 100644
--- a/ip/dependencies.json
+++ b/ip/dependencies.json
@@ -1,7 +1,7 @@
{
"IP": [
{
- "IP_Utilities": "v1.0.0"
+ "EF_IP_UTIL": "v1.0.0"
}
]
}
\ No newline at end of file
diff --git a/ipm_package.bash b/ipm_package.bash
new file mode 100644
index 0000000..57333e2
--- /dev/null
+++ b/ipm_package.bash
@@ -0,0 +1,55 @@
+#!/bin/bash
+# More safety, by turning some bugs into errors.
+set -o errexit -o pipefail -o nounset
+
+# now enjoy the options in order and nicely split until we see --
+# option --output/-o requires 1 argument
+LONGOPTS=version:
+OPTIONS=
+
+# -temporarily store output to be able to check for errors
+# -activate quoting/enhanced mode (e.g. by writing out "--options")
+# -pass arguments only via -- "$@" to separate them correctly
+# -if getopt fails, it complains itself to stdout
+PARSED=$(getopt --options=$OPTIONS --longoptions=$LONGOPTS --name "$0" -- "$@") || exit 2
+# read getopt's output this way to handle the quoting right:
+eval set -- "$PARSED"
+unset PARSED
+
+
+while true; do
+ case "$1" in
+ --version)
+ version="$2"
+ shift 2
+ ;;
+ --)
+ shift
+ break
+ ;;
+ *)
+ echo "Programming error"
+ exit 3
+ ;;
+ esac
+done
+
+echo "+ version=$version"
+
+# zip needed files
+tar czf v$version.tar.gz hdl/ef_util_lib.v fw
+# get checksum
+shasum -a 256 v$version.tar.gz > v$version.tar.gz.sha256
+
+# create tag
+git tag -a EF_IP_UTIL-v$version -m "Release version $version"
+git push origin EF_IP_UTIL-v$version
+
+# create release
+set -x
+if gh release view EF_IP_UTIL-v$version > /dev/null 2>&1; then
+ echo "Release EF_IP_UTIL-v$version already exists. Skipping..."
+else
+ echo "Creating release EF_IP_UTIL-v$version..."
+ gh release create EF_IP_UTIL-v$version v$version.tar.gz -t "EF_IP_UTIL-v$version" --notes "sha256: $(cat v$version.tar.gz.sha256)"
+fi
\ No newline at end of file
diff --git a/verify/README.md b/verify/README.md
new file mode 100644
index 0000000..79a7572
--- /dev/null
+++ b/verify/README.md
@@ -0,0 +1,31 @@
+## Run cocotb UVM Testbench:
+In IP directory run:
+ ```shell
+ cd verify/uvm-python/
+ ```
+ ##### To run testbench for design with APB
+ To run all tests:
+ ```shell
+ make run_all_tests BUS_TYPE=APB
+ ```
+ To run a certain test:
+ ```shell
+ make run_ BUS_TYPE=APB
+ ```
+ To run all tests with a tag:
+ ```shell
+ make run_all_tests TAG= BUS_TYPE=APB
+ ```
+ ##### To run testbench for design with APB
+ To run all tests:
+ ```shell
+ make run_all_tests BUS_TYPE=AHB
+ ```
+ To run a certain test:
+ ```shell
+ make run_ BUS_TYPE=AHB
+ ```
+ To run all tests with a tag:
+ ```shell
+ make run_all_tests TAG= BUS_TYPE=AHB
+```