From b2af4de7e936366178e85cf83c7f7b4901a7c1eb Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 7 Oct 2024 10:13:09 +0300 Subject: [PATCH] regenerate the wrappers with the new updates of the buswrap script --- hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v | 85 ++++++++++++++++++++++----- hdl/rtl/bus_wrappers/EF_I2S_AHBL.v | 77 ++++++++++++++++++++---- hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v | 43 ++++++-------- hdl/rtl/bus_wrappers/EF_I2S_APB.v | 35 +++++------ hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v | 80 ++++++++++++++++++++----- hdl/rtl/bus_wrappers/EF_I2S_WB.v | 76 ++++++++++++++++++++---- verify/uvm-python/Makefile | 2 +- verify/uvm-python/top.v | 4 -- 8 files changed, 295 insertions(+), 107 deletions(-) diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v index 53e39b3..2d996df 100644 --- a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v +++ b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v @@ -104,6 +104,10 @@ module EF_I2S_AHBL #( DW = 32, AW = 4 ) ( + + + + input wire HCLK, input wire HRESETn, input wire HWRITE, @@ -124,8 +128,9 @@ module EF_I2S_AHBL #( localparam RXDATA_REG_OFFSET = 16'h0000; localparam PR_REG_OFFSET = 16'h0004; localparam AVGT_REG_OFFSET = 16'h0008; - localparam CTRL_REG_OFFSET = 16'h000C; - localparam CFG_REG_OFFSET = 16'h0010; + localparam ZCRT_REG_OFFSET = 16'h000C; + localparam CTRL_REG_OFFSET = 16'h0010; + localparam CFG_REG_OFFSET = 16'h0014; localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00; localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04; localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08; @@ -133,7 +138,21 @@ module EF_I2S_AHBL #( localparam MIS_REG_OFFSET = 16'hFF04; localparam RIS_REG_OFFSET = 16'hFF08; localparam IC_REG_OFFSET = 16'hFF0C; - wire clk = HCLK; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + + + + // USE_POWER_PINS + .clk(HCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = HRESETn; @@ -171,6 +190,12 @@ module EF_I2S_AHBL #( wire [32-1:0] avg_threshold; wire [1-1:0] avg_flag; wire [1-1:0] avg_en; + wire [1-1:0] avg_sel; + wire [32-1:0] zcr_threshold; + wire [1-1:0] zcr_flag; + wire [1-1:0] zcr_en; + wire [1-1:0] zcr_sel; + wire [1-1:0] vad_flag; wire [2-1:0] channels; wire [1-1:0] en; @@ -189,22 +214,31 @@ module EF_I2S_AHBL #( else if(ahbl_we & (last_HADDR[16-1:0]==AVGT_REG_OFFSET)) AVGT_REG <= HWDATA[32-1:0]; - reg [2:0] CTRL_REG; + reg [31:0] ZCRT_REG; + assign zcr_threshold = ZCRT_REG; + always @(posedge HCLK or negedge HRESETn) if(~HRESETn) ZCRT_REG <= 0; + else if(ahbl_we & (last_HADDR[16-1:0]==ZCRT_REG_OFFSET)) + ZCRT_REG <= HWDATA[32-1:0]; + + reg [3:0] CTRL_REG; assign en = CTRL_REG[0 : 0]; assign fifo_en = CTRL_REG[1 : 1]; assign avg_en = CTRL_REG[2 : 2]; + assign zcr_en = CTRL_REG[3 : 3]; always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CTRL_REG <= 'h0; else if(ahbl_we & (last_HADDR[16-1:0]==CTRL_REG_OFFSET)) - CTRL_REG <= HWDATA[3-1:0]; + CTRL_REG <= HWDATA[4-1:0]; - reg [9:0] CFG_REG; + reg [11:0] CFG_REG; assign channels = CFG_REG[1 : 0]; assign sign_extend = CFG_REG[2 : 2]; assign left_justified = CFG_REG[3 : 3]; assign sample_size = CFG_REG[9 : 4]; + assign avg_sel = CFG_REG[10 : 10]; + assign zcr_sel = CFG_REG[11 : 11]; always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CFG_REG <= 'h201; else if(ahbl_we & (last_HADDR[16-1:0]==CFG_REG_OFFSET)) - CFG_REG <= HWDATA[10-1:0]; + CFG_REG <= HWDATA[12-1:0]; wire [AW-1:0] RX_FIFO_LEVEL_WIRE; assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level; @@ -223,23 +257,30 @@ module EF_I2S_AHBL #( else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG; - reg [3:0] IM_REG; - reg [3:0] IC_REG; - reg [3:0] RIS_REG; + localparam GCLK_REG_OFFSET = 16'hFF10; + always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0; + else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET)) + GCLK_REG <= HWDATA[1-1:0]; - wire[4-1:0] MIS_REG = RIS_REG & IM_REG; + reg [5:0] IM_REG; + reg [5:0] IC_REG; + reg [5:0] RIS_REG; + + wire[6-1:0] MIS_REG = RIS_REG & IM_REG; always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IM_REG <= 0; else if(ahbl_we & (last_HADDR[16-1:0]==IM_REG_OFFSET)) - IM_REG <= HWDATA[4-1:0]; - always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IC_REG <= 4'b0; + IM_REG <= HWDATA[6-1:0]; + always @(posedge HCLK or negedge HRESETn) if(~HRESETn) IC_REG <= 6'b0; else if(ahbl_we & (last_HADDR[16-1:0]==IC_REG_OFFSET)) - IC_REG <= HWDATA[4-1:0]; - else IC_REG <= 4'd0; + IC_REG <= HWDATA[6-1:0]; + else IC_REG <= 6'd0; wire [0:0] FIFOE = fifo_empty; wire [0:0] FIFOA = fifo_level_above; wire [0:0] FIFOF = fifo_full; wire [0:0] AVGF = avg_flag; + wire [0:0] ZCRF = zcr_flag; + wire [0:0] VADF = vad_flag; integer _i_; @@ -256,6 +297,12 @@ module EF_I2S_AHBL #( for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1; end + for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1; + end + for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1; + end end assign IRQ = |MIS_REG; @@ -293,6 +340,12 @@ module EF_I2S_AHBL #( .avg_threshold(avg_threshold), .avg_flag(avg_flag), .avg_en(avg_en), + .avg_sel(avg_sel), + .zcr_threshold(zcr_threshold), + .zcr_flag(zcr_flag), + .zcr_en(zcr_en), + .zcr_sel(zcr_sel), + .vad_flag(vad_flag), .channels(channels), .en(en), .ws(ws), @@ -304,6 +357,7 @@ module EF_I2S_AHBL #( (last_HADDR[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE : (last_HADDR[16-1:0] == PR_REG_OFFSET) ? PR_REG : (last_HADDR[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG : + (last_HADDR[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG : (last_HADDR[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG : (last_HADDR[16-1:0] == CFG_REG_OFFSET) ? CFG_REG : (last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE : @@ -313,6 +367,7 @@ module EF_I2S_AHBL #( (last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG : (last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG : (last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG : + (last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG : 32'hDEADBEEF; assign HREADYOUT = 1'b1; diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v index 6a2f637..f3ba023 100644 --- a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v +++ b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v @@ -31,6 +31,10 @@ module EF_I2S_AHBL #( DW = 32, AW = 4 ) ( +`ifdef USE_POWER_PINS + inout VPWR, + inout VGND, +`endif `AHBL_SLAVE_PORTS, output wire [1-1:0] ws, output wire [1-1:0] sck, @@ -40,8 +44,9 @@ module EF_I2S_AHBL #( localparam RXDATA_REG_OFFSET = `AHBL_AW'h0000; localparam PR_REG_OFFSET = `AHBL_AW'h0004; localparam AVGT_REG_OFFSET = `AHBL_AW'h0008; - localparam CTRL_REG_OFFSET = `AHBL_AW'h000C; - localparam CFG_REG_OFFSET = `AHBL_AW'h0010; + localparam ZCRT_REG_OFFSET = `AHBL_AW'h000C; + localparam CTRL_REG_OFFSET = `AHBL_AW'h0010; + localparam CFG_REG_OFFSET = `AHBL_AW'h0014; localparam RX_FIFO_LEVEL_REG_OFFSET = `AHBL_AW'hFE00; localparam RX_FIFO_THRESHOLD_REG_OFFSET = `AHBL_AW'hFE04; localparam RX_FIFO_FLUSH_REG_OFFSET = `AHBL_AW'hFE08; @@ -49,7 +54,21 @@ module EF_I2S_AHBL #( localparam MIS_REG_OFFSET = `AHBL_AW'hFF04; localparam RIS_REG_OFFSET = `AHBL_AW'hFF08; localparam IC_REG_OFFSET = `AHBL_AW'hFF0C; - wire clk = HCLK; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + `ifdef USE_POWER_PINS + .vpwr(VPWR), + .vgnd(VGND), + `endif // USE_POWER_PINS + .clk(HCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = HRESETn; @@ -71,6 +90,12 @@ module EF_I2S_AHBL #( wire [32-1:0] avg_threshold; wire [1-1:0] avg_flag; wire [1-1:0] avg_en; + wire [1-1:0] avg_sel; + wire [32-1:0] zcr_threshold; + wire [1-1:0] zcr_flag; + wire [1-1:0] zcr_en; + wire [1-1:0] zcr_sel; + wire [1-1:0] vad_flag; wire [2-1:0] channels; wire [1-1:0] en; @@ -85,18 +110,25 @@ module EF_I2S_AHBL #( assign avg_threshold = AVGT_REG; `AHBL_REG(AVGT_REG, 0, 32) - reg [2:0] CTRL_REG; + reg [31:0] ZCRT_REG; + assign zcr_threshold = ZCRT_REG; + `AHBL_REG(ZCRT_REG, 0, 32) + + reg [3:0] CTRL_REG; assign en = CTRL_REG[0 : 0]; assign fifo_en = CTRL_REG[1 : 1]; assign avg_en = CTRL_REG[2 : 2]; - `AHBL_REG(CTRL_REG, 'h0, 3) + assign zcr_en = CTRL_REG[3 : 3]; + `AHBL_REG(CTRL_REG, 'h0, 4) - reg [9:0] CFG_REG; + reg [11:0] CFG_REG; assign channels = CFG_REG[1 : 0]; assign sign_extend = CFG_REG[2 : 2]; assign left_justified = CFG_REG[3 : 3]; assign sample_size = CFG_REG[9 : 4]; - `AHBL_REG(CFG_REG, 'h201, 10) + assign avg_sel = CFG_REG[10 : 10]; + assign zcr_sel = CFG_REG[11 : 11]; + `AHBL_REG(CFG_REG, 'h201, 12) wire [AW-1:0] RX_FIFO_LEVEL_WIRE; assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level; @@ -109,18 +141,23 @@ module EF_I2S_AHBL #( assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0]; `AHBL_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0) - reg [3:0] IM_REG; - reg [3:0] IC_REG; - reg [3:0] RIS_REG; + localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10; + `AHBL_REG(GCLK_REG, 0, 1) + + reg [5:0] IM_REG; + reg [5:0] IC_REG; + reg [5:0] RIS_REG; - `AHBL_MIS_REG(4) - `AHBL_REG(IM_REG, 0, 4) - `AHBL_IC_REG(4) + `AHBL_MIS_REG(6) + `AHBL_REG(IM_REG, 0, 6) + `AHBL_IC_REG(6) wire [0:0] FIFOE = fifo_empty; wire [0:0] FIFOA = fifo_level_above; wire [0:0] FIFOF = fifo_full; wire [0:0] AVGF = avg_flag; + wire [0:0] ZCRF = zcr_flag; + wire [0:0] VADF = vad_flag; integer _i_; @@ -137,6 +174,12 @@ module EF_I2S_AHBL #( for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1; end + for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1; + end + for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1; + end end assign IRQ = |MIS_REG; @@ -174,6 +217,12 @@ module EF_I2S_AHBL #( .avg_threshold(avg_threshold), .avg_flag(avg_flag), .avg_en(avg_en), + .avg_sel(avg_sel), + .zcr_threshold(zcr_threshold), + .zcr_flag(zcr_flag), + .zcr_en(zcr_en), + .zcr_sel(zcr_sel), + .vad_flag(vad_flag), .channels(channels), .en(en), .ws(ws), @@ -185,6 +234,7 @@ module EF_I2S_AHBL #( (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE : (last_HADDR[`AHBL_AW-1:0] == PR_REG_OFFSET) ? PR_REG : (last_HADDR[`AHBL_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG : + (last_HADDR[`AHBL_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG : (last_HADDR[`AHBL_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG : (last_HADDR[`AHBL_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG : (last_HADDR[`AHBL_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE : @@ -194,6 +244,7 @@ module EF_I2S_AHBL #( (last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG : (last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG : (last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG : + (last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG : 32'hDEADBEEF; assign HREADYOUT = 1'b1; diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v index 71f8ec1..51a19de 100644 --- a/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v @@ -102,10 +102,10 @@ module EF_I2S_APB #( DW = 32, AW = 4 ) ( -`ifdef USE_POWER_PINS - input VPWR, - input VGND, -`endif + + + + input wire PCLK, input wire PRESETn, input wire PWRITE, @@ -136,27 +136,20 @@ module EF_I2S_APB #( localparam RIS_REG_OFFSET = 16'hFF08; localparam IC_REG_OFFSET = 16'hFF0C; - reg [0:0] GCLK_REG; - wire clk_g; - wire clk_gated_en = GCLK_REG[0]; - - `ifdef FPGA - wire clk = PCLK; - `else - (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - `endif - .GCLK(clk_g), - .GATE(clk_gated_en), - .CLK(PCLK) - ); - - wire clk = clk_g; - `endif + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + + + + // USE_POWER_PINS + .clk(PCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = PRESETn; diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.v index 16ccdaa..c9c1c08 100644 --- a/hdl/rtl/bus_wrappers/EF_I2S_APB.v +++ b/hdl/rtl/bus_wrappers/EF_I2S_APB.v @@ -55,27 +55,20 @@ module EF_I2S_APB #( localparam RIS_REG_OFFSET = `APB_AW'hFF08; localparam IC_REG_OFFSET = `APB_AW'hFF0C; - reg [0:0] GCLK_REG; - wire clk_g; - wire clk_gated_en = GCLK_REG[0]; - - `ifdef FPGA - wire clk = PCLK; - `else - (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - `endif - .GCLK(clk_g), - .GATE(clk_gated_en), - .CLK(PCLK) - ); - - wire clk = clk_g; - `endif + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + `ifdef USE_POWER_PINS + .vpwr(VPWR), + .vgnd(VGND), + `endif // USE_POWER_PINS + .clk(PCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = PRESETn; diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v index fa093de..3465c5e 100644 --- a/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v @@ -81,6 +81,10 @@ module EF_I2S_WB #( DW = 32, AW = 4 ) ( + + + + input wire ext_clk, input wire clk_i, input wire rst_i, @@ -101,8 +105,9 @@ module EF_I2S_WB #( localparam RXDATA_REG_OFFSET = 16'h0000; localparam PR_REG_OFFSET = 16'h0004; localparam AVGT_REG_OFFSET = 16'h0008; - localparam CTRL_REG_OFFSET = 16'h000C; - localparam CFG_REG_OFFSET = 16'h0010; + localparam ZCRT_REG_OFFSET = 16'h000C; + localparam CTRL_REG_OFFSET = 16'h0010; + localparam CFG_REG_OFFSET = 16'h0014; localparam RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00; localparam RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04; localparam RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08; @@ -110,7 +115,21 @@ module EF_I2S_WB #( localparam MIS_REG_OFFSET = 16'hFF04; localparam RIS_REG_OFFSET = 16'hFF08; localparam IC_REG_OFFSET = 16'hFF0C; - wire clk = clk_i; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + + + + // USE_POWER_PINS + .clk(clk_i), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = (~rst_i); @@ -135,6 +154,12 @@ module EF_I2S_WB #( wire [32-1:0] avg_threshold; wire [1-1:0] avg_flag; wire [1-1:0] avg_en; + wire [1-1:0] avg_sel; + wire [32-1:0] zcr_threshold; + wire [1-1:0] zcr_flag; + wire [1-1:0] zcr_en; + wire [1-1:0] zcr_sel; + wire [1-1:0] vad_flag; wire [2-1:0] channels; wire [1-1:0] en; @@ -149,18 +174,25 @@ module EF_I2S_WB #( assign avg_threshold = AVGT_REG; always @(posedge clk_i or posedge rst_i) if(rst_i) AVGT_REG <= 0; else if(wb_we & (adr_i[16-1:0]==AVGT_REG_OFFSET)) AVGT_REG <= dat_i[32-1:0]; - reg [2:0] CTRL_REG; + reg [31:0] ZCRT_REG; + assign zcr_threshold = ZCRT_REG; + always @(posedge clk_i or posedge rst_i) if(rst_i) ZCRT_REG <= 0; else if(wb_we & (adr_i[16-1:0]==ZCRT_REG_OFFSET)) ZCRT_REG <= dat_i[32-1:0]; + + reg [3:0] CTRL_REG; assign en = CTRL_REG[0 : 0]; assign fifo_en = CTRL_REG[1 : 1]; assign avg_en = CTRL_REG[2 : 2]; - always @(posedge clk_i or posedge rst_i) if(rst_i) CTRL_REG <= 'h0; else if(wb_we & (adr_i[16-1:0]==CTRL_REG_OFFSET)) CTRL_REG <= dat_i[3-1:0]; + assign zcr_en = CTRL_REG[3 : 3]; + always @(posedge clk_i or posedge rst_i) if(rst_i) CTRL_REG <= 'h0; else if(wb_we & (adr_i[16-1:0]==CTRL_REG_OFFSET)) CTRL_REG <= dat_i[4-1:0]; - reg [9:0] CFG_REG; + reg [11:0] CFG_REG; assign channels = CFG_REG[1 : 0]; assign sign_extend = CFG_REG[2 : 2]; assign left_justified = CFG_REG[3 : 3]; assign sample_size = CFG_REG[9 : 4]; - always @(posedge clk_i or posedge rst_i) if(rst_i) CFG_REG <= 'h201; else if(wb_we & (adr_i[16-1:0]==CFG_REG_OFFSET)) CFG_REG <= dat_i[10-1:0]; + assign avg_sel = CFG_REG[10 : 10]; + assign zcr_sel = CFG_REG[11 : 11]; + always @(posedge clk_i or posedge rst_i) if(rst_i) CFG_REG <= 'h201; else if(wb_we & (adr_i[16-1:0]==CFG_REG_OFFSET)) CFG_REG <= dat_i[12-1:0]; wire [AW-1:0] RX_FIFO_LEVEL_WIRE; assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level; @@ -173,22 +205,27 @@ module EF_I2S_WB #( assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0]; always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET)) RX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG; - reg [3:0] IM_REG; - reg [3:0] IC_REG; - reg [3:0] RIS_REG; + localparam GCLK_REG_OFFSET = 16'hFF10; + always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0]; + + reg [5:0] IM_REG; + reg [5:0] IC_REG; + reg [5:0] RIS_REG; - wire[4-1:0] MIS_REG = RIS_REG & IM_REG; - always @(posedge clk_i or posedge rst_i) if(rst_i) IM_REG <= 0; else if(wb_we & (adr_i[16-1:0]==IM_REG_OFFSET)) IM_REG <= dat_i[4-1:0]; - always @(posedge clk_i or posedge rst_i) if(rst_i) IC_REG <= 4'b0; + wire[6-1:0] MIS_REG = RIS_REG & IM_REG; + always @(posedge clk_i or posedge rst_i) if(rst_i) IM_REG <= 0; else if(wb_we & (adr_i[16-1:0]==IM_REG_OFFSET)) IM_REG <= dat_i[6-1:0]; + always @(posedge clk_i or posedge rst_i) if(rst_i) IC_REG <= 6'b0; else if(wb_we & (adr_i[16-1:0]==IC_REG_OFFSET)) - IC_REG <= dat_i[4-1:0]; + IC_REG <= dat_i[6-1:0]; else - IC_REG <= 4'd0; + IC_REG <= 6'd0; wire [0:0] FIFOE = fifo_empty; wire [0:0] FIFOA = fifo_level_above; wire [0:0] FIFOF = fifo_full; wire [0:0] AVGF = avg_flag; + wire [0:0] ZCRF = zcr_flag; + wire [0:0] VADF = vad_flag; integer _i_; @@ -205,6 +242,12 @@ module EF_I2S_WB #( for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1; end + for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1; + end + for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1; + end end assign IRQ = |MIS_REG; @@ -242,6 +285,12 @@ module EF_I2S_WB #( .avg_threshold(avg_threshold), .avg_flag(avg_flag), .avg_en(avg_en), + .avg_sel(avg_sel), + .zcr_threshold(zcr_threshold), + .zcr_flag(zcr_flag), + .zcr_en(zcr_en), + .zcr_sel(zcr_sel), + .vad_flag(vad_flag), .channels(channels), .en(en), .ws(ws), @@ -253,6 +302,7 @@ module EF_I2S_WB #( (adr_i[16-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE : (adr_i[16-1:0] == PR_REG_OFFSET) ? PR_REG : (adr_i[16-1:0] == AVGT_REG_OFFSET) ? AVGT_REG : + (adr_i[16-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG : (adr_i[16-1:0] == CTRL_REG_OFFSET) ? CTRL_REG : (adr_i[16-1:0] == CFG_REG_OFFSET) ? CFG_REG : (adr_i[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE : diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.v index 665b100..bdcc08d 100644 --- a/hdl/rtl/bus_wrappers/EF_I2S_WB.v +++ b/hdl/rtl/bus_wrappers/EF_I2S_WB.v @@ -31,6 +31,10 @@ module EF_I2S_WB #( DW = 32, AW = 4 ) ( +`ifdef USE_POWER_PINS + inout VPWR, + inout VGND, +`endif `WB_SLAVE_PORTS, output wire [1-1:0] ws, output wire [1-1:0] sck, @@ -40,8 +44,9 @@ module EF_I2S_WB #( localparam RXDATA_REG_OFFSET = `WB_AW'h0000; localparam PR_REG_OFFSET = `WB_AW'h0004; localparam AVGT_REG_OFFSET = `WB_AW'h0008; - localparam CTRL_REG_OFFSET = `WB_AW'h000C; - localparam CFG_REG_OFFSET = `WB_AW'h0010; + localparam ZCRT_REG_OFFSET = `WB_AW'h000C; + localparam CTRL_REG_OFFSET = `WB_AW'h0010; + localparam CFG_REG_OFFSET = `WB_AW'h0014; localparam RX_FIFO_LEVEL_REG_OFFSET = `WB_AW'hFE00; localparam RX_FIFO_THRESHOLD_REG_OFFSET = `WB_AW'hFE04; localparam RX_FIFO_FLUSH_REG_OFFSET = `WB_AW'hFE08; @@ -49,7 +54,21 @@ module EF_I2S_WB #( localparam MIS_REG_OFFSET = `WB_AW'hFF04; localparam RIS_REG_OFFSET = `WB_AW'hFF08; localparam IC_REG_OFFSET = `WB_AW'hFF0C; - wire clk = clk_i; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + `ifdef USE_POWER_PINS + .vpwr(VPWR), + .vgnd(VGND), + `endif // USE_POWER_PINS + .clk(clk_i), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = (~rst_i); @@ -71,6 +90,12 @@ module EF_I2S_WB #( wire [32-1:0] avg_threshold; wire [1-1:0] avg_flag; wire [1-1:0] avg_en; + wire [1-1:0] avg_sel; + wire [32-1:0] zcr_threshold; + wire [1-1:0] zcr_flag; + wire [1-1:0] zcr_en; + wire [1-1:0] zcr_sel; + wire [1-1:0] vad_flag; wire [2-1:0] channels; wire [1-1:0] en; @@ -85,18 +110,25 @@ module EF_I2S_WB #( assign avg_threshold = AVGT_REG; `WB_REG(AVGT_REG, 0, 32) - reg [2:0] CTRL_REG; + reg [31:0] ZCRT_REG; + assign zcr_threshold = ZCRT_REG; + `WB_REG(ZCRT_REG, 0, 32) + + reg [3:0] CTRL_REG; assign en = CTRL_REG[0 : 0]; assign fifo_en = CTRL_REG[1 : 1]; assign avg_en = CTRL_REG[2 : 2]; - `WB_REG(CTRL_REG, 'h0, 3) + assign zcr_en = CTRL_REG[3 : 3]; + `WB_REG(CTRL_REG, 'h0, 4) - reg [9:0] CFG_REG; + reg [11:0] CFG_REG; assign channels = CFG_REG[1 : 0]; assign sign_extend = CFG_REG[2 : 2]; assign left_justified = CFG_REG[3 : 3]; assign sample_size = CFG_REG[9 : 4]; - `WB_REG(CFG_REG, 'h201, 10) + assign avg_sel = CFG_REG[10 : 10]; + assign zcr_sel = CFG_REG[11 : 11]; + `WB_REG(CFG_REG, 'h201, 12) wire [AW-1:0] RX_FIFO_LEVEL_WIRE; assign RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level; @@ -109,18 +141,23 @@ module EF_I2S_WB #( assign fifo_flush = RX_FIFO_FLUSH_REG[0 : 0]; `WB_REG_AC(RX_FIFO_FLUSH_REG, 0, 1, 1'h0) - reg [3:0] IM_REG; - reg [3:0] IC_REG; - reg [3:0] RIS_REG; + localparam GCLK_REG_OFFSET = `WB_AW'hFF10; + `WB_REG(GCLK_REG, 0, 1) + + reg [5:0] IM_REG; + reg [5:0] IC_REG; + reg [5:0] RIS_REG; - `WB_MIS_REG(4) - `WB_REG(IM_REG, 0, 4) - `WB_IC_REG(4) + `WB_MIS_REG(6) + `WB_REG(IM_REG, 0, 6) + `WB_IC_REG(6) wire [0:0] FIFOE = fifo_empty; wire [0:0] FIFOA = fifo_level_above; wire [0:0] FIFOF = fifo_full; wire [0:0] AVGF = avg_flag; + wire [0:0] ZCRF = zcr_flag; + wire [0:0] VADF = vad_flag; integer _i_; @@ -137,6 +174,12 @@ module EF_I2S_WB #( for(_i_ = 3; _i_ < 4; _i_ = _i_ + 1) begin if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(AVGF[_i_ - 3] == 1'b1) RIS_REG[_i_] <= 1'b1; end + for(_i_ = 4; _i_ < 5; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(ZCRF[_i_ - 4] == 1'b1) RIS_REG[_i_] <= 1'b1; + end + for(_i_ = 5; _i_ < 6; _i_ = _i_ + 1) begin + if(IC_REG[_i_]) RIS_REG[_i_] <= 1'b0; else if(VADF[_i_ - 5] == 1'b1) RIS_REG[_i_] <= 1'b1; + end end assign IRQ = |MIS_REG; @@ -174,6 +217,12 @@ module EF_I2S_WB #( .avg_threshold(avg_threshold), .avg_flag(avg_flag), .avg_en(avg_en), + .avg_sel(avg_sel), + .zcr_threshold(zcr_threshold), + .zcr_flag(zcr_flag), + .zcr_en(zcr_en), + .zcr_sel(zcr_sel), + .vad_flag(vad_flag), .channels(channels), .en(en), .ws(ws), @@ -185,6 +234,7 @@ module EF_I2S_WB #( (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET) ? RXDATA_WIRE : (adr_i[`WB_AW-1:0] == PR_REG_OFFSET) ? PR_REG : (adr_i[`WB_AW-1:0] == AVGT_REG_OFFSET) ? AVGT_REG : + (adr_i[`WB_AW-1:0] == ZCRT_REG_OFFSET) ? ZCRT_REG : (adr_i[`WB_AW-1:0] == CTRL_REG_OFFSET) ? CTRL_REG : (adr_i[`WB_AW-1:0] == CFG_REG_OFFSET) ? CFG_REG : (adr_i[`WB_AW-1:0] == RX_FIFO_LEVEL_REG_OFFSET) ? RX_FIFO_LEVEL_WIRE : diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile index df49b6b..f3caf86 100644 --- a/verify/uvm-python/Makefile +++ b/verify/uvm-python/Makefile @@ -1,7 +1,7 @@ PLUSARGS += "+UVM_VERBOSITY=UVM_MEDUIM" TOPLEVEL := top MODULE ?= top_module -PDK_FILES ?= /home/nouran/PDK_cheetah_v3/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v /home/nouran/PDK_cheetah_v3/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v +PDK_FILES ?= $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v AHB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v APB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v diff --git a/verify/uvm-python/top.v b/verify/uvm-python/top.v index af7cbaa..58d2f52 100644 --- a/verify/uvm-python/top.v +++ b/verify/uvm-python/top.v @@ -17,10 +17,6 @@ module top(); wire [31:0] PRDATA; wire PREADY; EF_I2S_APB uut( - `ifdef USE_POWER_PINS - .VPWR(1'b1), - .VGND(1'b0), - `endif .ws(ws), .sck(sck), .sdi(sdi),