EF_PSRAM_CTRL.yaml

---
info:
  name: EF_PSRAM_CTRL
  description: |
    A Controller for Quad I/O SPI PSRAM
      Pseudostatic RAM (PSRAM) is DRAM combined with a self-refresh circuit. 
      It appears externally as slower SRAM, albeit with a density/cost advantage 
      over true SRAM, and without the access complexity of DRAM.
      The controller was designed after:
    - https://www.issi.com/WW/pdf/66-67WVS4M8ALL-BLL.pdf and
    - https://www.microchip.com/en-us/parametric-search/514

    utilizing SPI, QSPI and QPI modes.

    The controller was verified against the Verilog model of Microchip M23LC1024 for SPI and QPI modes only.

    ##### Features:
    - Small in size (800 cells)
    - Supports PSRAM or serial SRAM memories up to 8MBytes.
    - Programmable to configure: read/write commands, number of wait states, enter and exist quad i/o commands.
  repo: github.com/efabless/EF_PSRAM_CTRL
  owner: Efabless Corp.
  license: Apache 2.0
  author: Efabless Corp.
  email: ip_admin@efabless.com
  version: v1.0.8
  date: 27-11-2024
  category: digital
  tags:
    - memory
    - psram
  bus:
    - AHBL
  type: soft
  status: verified
  cell_count:
    - IP: TBD
    - AHBL: TBD
  width: "0.0"
  height: "0.0"
  technology: n/a
  clock_freq_mhz:
    - IP: TBD
    - AHBL: TBD
  digital_supply_voltage: n/a
  analog_supply_voltage: n/a

external_interface:
- name: sck
  port: sck
  width: 1
  direction: output
  description: SPI master output clock 
- name: ce_n
  port: ce_n
  width: 1
  direction: output 
  description: SPI Master slave select.
- name: din
  port: din
  width: 4
  direction: input
  description: SPI Master data in , slave out 
- name: dout
  port: dout
  width: 4
  direction: output 
  description: SPI Master data out , slave in  
- name: douten
  port: douten
  width: 4
  direction: output 
  description: SPI Master data out enable 

registers:
  - name: rd_cmd
    size: 8
    mode: w
    fifo: no
    offset: 0x0080_0100
    bit_access: no
    init: "'h3"
    write_port: ""
    description: RD Command Register
  - name: wr_cmd
    size: 8
    mode: w
    fifo: no
    offset: 0x0080_0200
    bit_access: no
    init: "'h2"
    write_port: ""
    description: WR Command Register
  - name: eqpi_cmd
    size: 8
    mode: w
    fifo: no
    offset: 0x0080_0400
    bit_access: no
    init: "'h35"
    write_port: ""
    description: Enter QPI Command Register
  - name: xqpi_cmd
    size: 8
    mode: w
    fifo: no
    offset: 0x0080_0800
    bit_access: no
    init: "'hFE"
    write_port: ""
    description: Exit QPI Command Register
  - name: wait_states
    size: 4
    mode: w
    fifo: no
    offset: 0x0080_1000
    bit_access: no
    init: "'h0"
    write_port: ""
    description: Wait States Register
  - name: mode
    size: 2
    mode: w
    fifo: no
    offset: 0x0080_2000
    bit_access: no
    init: "'h0"
    write_port: ""
    description: I/O Mode Register, {qpi, qspi}
  - name: enter_qpi
    size: 1
    mode: w
    fifo: no
    offset: 0x0080_4000
    bit_access: no
    init: "'h0"
    write_port: ""
    description: Initiate Enter QPI (EQPI) Mode process Register
  - name: exit_qpi
    size: 1
    mode: w
    fifo: no
    offset: 0x0080_8000
    bit_access: no
    init: "'h0"
    write_port: ""
    description: Initiate Exit QPI (XQPI) Mode process Register
clock: 
  name: HCLK
  gated: "no"
reset:
  name: HRESETn
  pol: "0"