From 230415630deb8ff266f8e066104476af2eb76636 Mon Sep 17 00:00:00 2001 From: NouranAbdelaziz Date: Mon, 8 Jul 2024 14:26:53 +0300 Subject: [PATCH] change power ports direction to inout --- EF_UART.yaml | 2 +- hdl/rtl/bus_wrappers/EF_UART_APB.pp.v | 4 ++-- hdl/rtl/bus_wrappers/EF_UART_APB.v | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/EF_UART.yaml b/EF_UART.yaml index 5d6cd4b..16f675c 100644 --- a/EF_UART.yaml +++ b/EF_UART.yaml @@ -7,7 +7,7 @@ info: license: APACHE 2.0 author: Mohamed Shalan email: mshalan@efabless.com - version: v1.1.4 + version: v1.1.5 date: 08-07-2024 category: digital tags: diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v index 907f7c0..fdf8d70 100644 --- a/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_UART_APB.pp.v @@ -30,8 +30,8 @@ module EF_UART_APB #( FAW = 4 ) ( `ifdef USE_POWER_PINS - input wire VPWR, - input wire VGND, + inout VPWR, + inout VGND, `endif input wire PCLK, input wire PRESETn, diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.v b/hdl/rtl/bus_wrappers/EF_UART_APB.v index 6c17d10..f0a65fb 100644 --- a/hdl/rtl/bus_wrappers/EF_UART_APB.v +++ b/hdl/rtl/bus_wrappers/EF_UART_APB.v @@ -34,8 +34,8 @@ module EF_UART_APB #( FAW = 4 ) ( `ifdef USE_POWER_PINS - input wire VPWR, - input wire VGND, + inout VPWR, + inout VGND, `endif `APB_SLAVE_PORTS, input wire [1-1:0] rx,