diff --git a/verilog/dv/make/sim.makefile b/verilog/dv/make/sim.makefile
index 76ea174..8c433e3 100644
--- a/verilog/dv/make/sim.makefile
+++ b/verilog/dv/make/sim.makefile
@@ -63,45 +63,85 @@ hex:  ${BLOCKS:=.hex}
 
 ## RTL
 ifeq ($(SIM),RTL)
-    ifeq ($(CONFIG),caravel_user_project)
+ifeq ($(CONFIG),caravel_user_project)
 		iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
-    else
+		-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+		-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+else
+ifeq ($(CONFIG),caravel_user_project_analog)
+		iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f$(VERILOG_PATH)/includes/includes.rtl.caravan \
+		-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+else
+ifeq ($(CONFIG),caravel)
 		iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
 		-f $(VERILOG_PATH)/includes/includes.rtl.$(CONFIG) \
 		-o $@ $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $<
-    endif
+else
+		iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f $(VERILOG_PATH)/includes/includes.rtl.$(CONFIG) \
+		-o $@ $(CARAVEL_PATH)/rtl/__user_analog_project_wrapper.v $<
+endif
+endif
+endif
 endif 
 
-## GL
+# GL
 ifeq ($(SIM),GL)
-    ifeq ($(CONFIG),caravel_user_project)
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
-        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
-    else
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f$(VERILOG_PATH)/includes/includes.gl.caravel \
+		-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+else
+ifeq ($(CONFIG),caravel_user_project_analog)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f$(VERILOG_PATH)/includes/includes.gl.caravan \
+		-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+else
+ifeq ($(CONFIG),caravel)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
 		-o $@ $(CARAVEL_PATH)/gl/__user_project_wrapper.v $<
-    endif
+else
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+		-o $@ $(CARAVEL_PATH)/gl/__user_analog_project_wrapper.v $<
+endif
+endif
+endif
 endif 
 
 ## GL+SDF
 ifeq ($(SIM),GL_SDF)
-    ifeq ($(CONFIG),caravel_user_project)
-		cvc64  +interp \
-		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
-		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
-		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
-		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
-	else
-		cvc64  +interp \
-		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
-		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
-		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
-		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
-    endif
+ifeq ($(CONFIG),caravel_user_project)
+ 		cvc64  +interp \
+ 		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ 		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+ 		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+ 		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+else
+ifeq ($(CONFIG),caravel_user_project)
+ 		cvc64  +interp \
+ 		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ 		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+ 		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravan \
+ 		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+else
+ifeq ($(CONFIG),caravel)
+ 		cvc64  +interp \
+ 		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ 		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+ 		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+ 		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+else
+ 		cvc64  +interp \
+ 		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+ 		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+ 		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+ 		-f $CARAVEL_PATH/gl/__user_analog_project_wrapper.v $<
+endif
+endif
+endif
 endif
 
 %.vcd: %.vvp
diff --git a/verilog/dv/tests-caravel/caravan_pud/Makefile b/verilog/dv/tests-caravel/caravan_pud/Makefile
new file mode 100755
index 0000000..074c7fa
--- /dev/null
+++ b/verilog/dv/tests-caravel/caravan_pud/Makefile
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravan
+
+include ../../make/env.makefile
+include ../../make/var.makefile
+include ../../make/cpu.makefile
+include ../../make/sim.makefile
+
+
diff --git a/verilog/dv/tests-caravel/caravan_pud/caravan_pud.c b/verilog/dv/tests-caravel/caravan_pud/caravan_pud.c
new file mode 100755
index 0000000..e337447
--- /dev/null
+++ b/verilog/dv/tests-caravel/caravan_pud/caravan_pud.c
@@ -0,0 +1,202 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <defs.h>
+
+// --------------------------------------------------------
+
+/*
+ * GPIO Pin test pull-up and pull-down modes on caravan.
+ * This is a modification of the "pullupdown" testbench,
+ * which checks that the pins that have the GPIOs
+ * removed on caravan are always in an unknown state.
+ */
+
+void main()
+{
+    int j;
+
+    /* Configure top 6 GPIO for signaling the testbench. */
+    /* The signal GPIOs will be swapped later so the	 */
+    /* top GPIOs can be tested.				 */
+
+    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* Turn off the remaining I/O */
+
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_15 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_14 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_13 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_12 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_11 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_10 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_9 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_8 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_7 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_6 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_5 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_4 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_3 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_2 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_1 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_0 = GPIO_MODE_MGMT_STD_ANALOG;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_mprj_datah = 0x20;	/* Flag end of CSB test */
+
+    /* Turn off the SPI because we will test the	*/
+    /* GPIO pins connected to the SPI lines.		*/
+
+    reg_hkspi_disable = 1;
+
+    /* Flag the start of the full GPIO test */
+    reg_mprj_datah = 0x30;
+
+    for (j = 0; j < 32; j++) {
+	/* Set output j to weak pull-down */
+	(*(volatile uint32_t*)(0x26000024 + 4 * j)) = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Flag the pulldown test */
+	reg_mprj_datah = 0x31;
+
+	/* During this time, GPIO j is tested for the pull-down state */
+
+	/* Set output j to weak pull-up */
+	(*(volatile uint32_t*)(0x26000024 + 4 * j)) = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Flag the pullup test */
+	reg_mprj_datah = 0x32;
+
+	/* During this time, GPIO j is tested for the pull-up state */
+
+	/* Set output j to disabled state */
+	(*(volatile uint32_t*)(0x26000024 + 4 * j)) = GPIO_MODE_MGMT_STD_ANALOG;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Flag the disabled state test */
+	reg_mprj_datah = 0x33;
+
+	/* During this time, GPIO j is tested for the disabled state */
+    }    
+
+    /* Flag the change of GPIOs */
+    reg_mprj_datah = 0x34;
+
+    reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    reg_mprj_datal = 0x35;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_mprj_io_37 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_36 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_35 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_34 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_33 = GPIO_MODE_MGMT_STD_ANALOG;
+    reg_mprj_io_32 = GPIO_MODE_MGMT_STD_ANALOG;
+
+    /* Apply configuration */
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    /* Flag start of testing upper GPIOs */
+    reg_mprj_datal = 0x36;
+
+    for (j = 32; j < 38; j++) {
+	/* Set output j to weak pull-down */
+	(*(volatile uint32_t*)(0x26000024 + 4 * j)) = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Flag the pulldown test */
+	reg_mprj_datal = 0x37;
+
+	/* During this time, GPIO j is tested for the pull-down state */
+
+	/* Set output j to weak pull-up */
+	(*(volatile uint32_t*)(0x26000024 + 4 * j)) = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Flag the pullup test */
+	reg_mprj_datal = 0x38;
+
+	/* During this time, GPIO j is tested for the pull-up state */
+
+	/* Set output j to disabled state */
+	(*(volatile uint32_t*)(0x26000024 + 4 * j)) = GPIO_MODE_MGMT_STD_ANALOG;
+
+	/* Apply configuration */
+	reg_mprj_xfer = 1;
+	while (reg_mprj_xfer == 1);
+
+	/* Flag the disabled state test */
+	reg_mprj_datal = 0x39;
+
+	/* During this time, GPIO j is tested for the disabled state */
+    }    
+
+    /* Flag the end of the test */
+    reg_mprj_datal = 0x3a;
+}
+
diff --git a/verilog/dv/tests-caravel/caravan_pud/caravan_pud_tb.v b/verilog/dv/tests-caravel/caravan_pud/caravan_pud_tb.v
new file mode 100755
index 0000000..8390ebe
--- /dev/null
+++ b/verilog/dv/tests-caravel/caravan_pud/caravan_pud_tb.v
@@ -0,0 +1,335 @@
+/*
+ *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
+ *
+ *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Tim Edwards <tim@efabless.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ *  SPDX-License-Identifier: ISC
+ */
+`timescale 1 ns / 1 ps
+
+module caravan_pud_tb;
+
+	reg clock;
+	reg power1;
+	reg power2;
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock <= 0;
+	end
+
+	initial begin
+		$dumpfile("caravan_pud.vcd");
+		$dumpvars(3, caravan_pud_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (500) begin
+			repeat (1000) @(posedge clock);
+			$display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Pullupdown (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Pullupdown (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	wire [37:0] mprj_io;
+	wire [5:0] checkbits_lo;
+	wire [5:0] checkbits_hi;
+
+	assign checkbits_hi = mprj_io[37:32];
+	assign checkbits_lo = mprj_io[5:0];
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+	wire gpio;
+
+	reg RSTB;
+
+	integer i;
+	reg [37:0] mprj_apply = 38'bz;
+
+        assign mprj_io = mprj_apply;
+
+	// Monitor
+	initial begin
+		#4000;
+		if (mprj_io[3] !== 1'b1) begin
+		    $display("Monitor: CSB value %b should be 1.", mprj_io[3]);
+		    $display("Monitor: Test CSB check-pullup failed.");
+		    $finish;
+		end
+		// Should be able to force the pin low against the pull-up
+		mprj_apply[3] = 1'b0;
+		#10;
+		if (mprj_io[3] !== 1'b0) begin
+		    $display("Monitor: CSB value %b should be 0.", mprj_io[3]);
+		    $display("Monitor: Test CSB force-low failed.");
+		    $finish;
+		end
+		mprj_apply[3] = 1'bz;
+		wait(checkbits_hi == 6'h20);
+		$display("Monitor: CSB default pull-up state check passed");
+
+		wait(checkbits_hi == 6'h30);
+		for (i = 0; i < 14; i++) begin
+	   	   $display("Monitor: Testing channel %d", i);
+		   wait(checkbits_hi == 6'h31);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pulldown failed.");
+			$finish;
+		   end
+		   // Should be able to force the pin high against the pull-down
+		   mprj_apply[i] = 1'b1;
+		   #10;
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud force-high failed.");
+			$finish;
+		   end
+		   mprj_apply[i] = 1'bz;
+		   wait(checkbits_hi == 6'h32);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pullup failed.");
+			$finish;
+		   end
+		   // Should be able to force the pin low against the pull-up
+		   mprj_apply[i] = 1'b0;
+		   #10;
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud force-low failed.");
+			$finish;
+		   end
+		   mprj_apply[i] = 1'bz;
+		   wait(checkbits_hi == 6'h33);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-disabled failed.");
+			$finish;
+		   end
+		end
+		for (i = 14; i < 25; i++) begin
+	   	   $display("Monitor: Testing channel %d", i);
+		   wait(checkbits_hi == 6'h31);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pulldown failed.");
+			$finish;
+		   end
+		   wait(checkbits_hi == 6'h32);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pulldown failed.");
+			$finish;
+		   end
+		   wait(checkbits_hi == 6'h33);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pulldown failed.");
+			$finish;
+		   end
+		end
+		for (i = 25; i < 32; i++) begin
+	   	   $display("Monitor: Testing channel %d", i);
+		   wait(checkbits_hi == 6'h31);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pulldown failed.");
+			$finish;
+		   end
+		   // Should be able to force the pin high against the pull-down
+		   mprj_apply[i] = 1'b1;
+		   #10;
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud force-high failed.");
+			$finish;
+		   end
+		   mprj_apply[i] = 1'bz;
+		   wait(checkbits_hi == 6'h32);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pullup failed.");
+			$finish;
+		   end
+		   // Should be able to force the pin low against the pull-up
+		   mprj_apply[i] = 1'b0;
+		   #10;
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud force-low failed.");
+			$finish;
+		   end
+		   mprj_apply[i] = 1'bz;
+		   wait(checkbits_hi == 6'h33);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-disabled failed.");
+			$finish;
+		   end
+		end
+		wait(checkbits_hi == 6'h34);
+		$display("Monitor: Switch from low to high GPIOs");
+		wait(checkbits_lo == 6'h35);
+		$display("Monitor: GPIO 0-31 pull-up/down check passed");
+		wait(checkbits_lo == 6'h36);
+		$display("Monitor: Start test of high GPIOs");
+		for (i = 32; i < 38; i++) begin
+	   	   $display("Monitor: Testing channel %d", i);
+		   wait(checkbits_lo == 6'h37);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pulldown failed.");
+			$finish;
+		   end
+		   // Should be able to force the pin high against the pull-down
+		   mprj_apply[i] = 1'b1;
+		   #10;
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud force-high failed.");
+			$finish;
+		   end
+		   mprj_apply[i] = 1'bz;
+		   wait(checkbits_lo == 6'h38);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-pullup failed.");
+			$finish;
+		   end
+		   // Should be able to force the pin low against the pull-up
+		   mprj_apply[i] = 1'b0;
+		   #10;
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud force-low failed.");
+			$finish;
+		   end
+		   mprj_apply[i] = 1'bz;
+		   wait(checkbits_lo == 6'h39);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
+			$display("Monitor: Test caravan_pud check-disabled failed.");
+			$finish;
+		   end
+		end
+		wait(checkbits_lo == 6'h3a);
+		$display("Monitor: GPIO 37-32 pull-up/down check passed");
+		`ifdef GL
+			$display("Monitor: Test Pullupdown (GL) Passed");
+		`else
+			$display("Monitor: Test Pullupdown (RTL) Passed");
+		`endif
+		#2000;
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	initial begin			// Power-up
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+		
+
+	always @(mprj_io) begin
+		#1 $display("Mgmt GPIO state = %b (%d - %d)", mprj_io,
+				checkbits_hi, checkbits_lo);
+	end
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	// These are the mappings of mprj_io GPIO pads that are set to
+	// specific functions on startup:
+	//
+	// JTAG      = mgmt_gpio_io[0]              (inout)
+	// SDO       = mgmt_gpio_io[1]              (output)
+	// SDI       = mgmt_gpio_io[2]              (input)
+	// CSB       = mgmt_gpio_io[3]              (input)
+	// SCK       = mgmt_gpio_io[4]              (input)
+	// ser_rx    = mgmt_gpio_io[5]              (input)
+	// ser_tx    = mgmt_gpio_io[6]              (output)
+	// irq       = mgmt_gpio_io[7]              (input)
+
+ 	caravan uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),		
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("caravan_pud.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
diff --git a/verilog/dv/tests-caravel/pullupdown/pullupdown.c b/verilog/dv/tests-caravel/pullupdown/pullupdown.c
index 9fd688a..fee765a 100755
--- a/verilog/dv/tests-caravel/pullupdown/pullupdown.c
+++ b/verilog/dv/tests-caravel/pullupdown/pullupdown.c
@@ -77,7 +77,7 @@ void main()
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
-    reg_mprj_datah = 0x20;	/* Flag start of CSB test */
+    reg_mprj_datah = 0x20;	/* Flag end of CSB test */
 
     /* Turn off the SPI because we will test the	*/
     /* GPIO pins connected to the SPI lines.		*/
diff --git a/verilog/dv/tests-caravel/pullupdown/pullupdown_tb.v b/verilog/dv/tests-caravel/pullupdown/pullupdown_tb.v
index f276127..dadacb8 100755
--- a/verilog/dv/tests-caravel/pullupdown/pullupdown_tb.v
+++ b/verilog/dv/tests-caravel/pullupdown/pullupdown_tb.v
@@ -69,72 +69,65 @@ module pullupdown_tb;
 	reg RSTB;
 
 	integer i;
-	reg w;
 	reg [37:0] mprj_apply = 38'bz;
 
         assign mprj_io = mprj_apply;
 
 	// Monitor
 	initial begin
-		wait(checkbits_hi == 6'h20);
-		w = mprj_io[3];
-		if (w != 1'b1) begin
-		    $display("Monitor: CSB value %b should be 1.", w);
+		#4000;
+		if (mprj_io[3] !== 1'b1) begin
+		    $display("Monitor: CSB value %b should be 1.", mprj_io[3]);
 		    $display("Monitor: Test CSB check-pullup failed.");
 		    $finish;
 		end
 		// Should be able to force the pin low against the pull-up
 		mprj_apply[3] = 1'b0;
 		#10;
-		w = mprj_io[3];
-		if (w != 1'b0) begin
-		    $display("Monitor: CSB value %b should be 0.", w);
+		if (mprj_io[3] !== 1'b0) begin
+		    $display("Monitor: CSB value %b should be 0.", mprj_io[3]);
 		    $display("Monitor: Test CSB force-low failed.");
 		    $finish;
 		end
 		mprj_apply[3] = 1'bz;
+		wait(checkbits_hi == 6'h20);
 		$display("Monitor: CSB default pull-up state check passed");
 
 		wait(checkbits_hi == 6'h30);
 		for (i = 0; i < 32; i++) begin
 		   wait(checkbits_hi == 6'h31);
-		   w = mprj_io[i];
-		   if (w != 1'b0) begin
-			$display("Monitor: wire value %b should be 0.", w);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
 			$display("Monitor: Test pullupdown check-pulldown failed.");
 			$finish;
 		   end
 		   // Should be able to force the pin high against the pull-down
 		   mprj_apply[i] = 1'b1;
 		   #10;
-		   w = mprj_io[i];
-		   if (w != 1'b1) begin
-			$display("Monitor: wire value %b should be 1.", w);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
 			$display("Monitor: Test pullupdown force-high failed.");
 			$finish;
 		   end
 		   mprj_apply[i] = 1'bz;
 		   wait(checkbits_hi == 6'h32);
-		   w = mprj_io[i];
-		   if (w != 1'b1) begin
-			$display("Monitor: wire value %b should be 1.", w);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
 			$display("Monitor: Test pullupdown check-pullup failed.");
 			$finish;
 		   end
 		   // Should be able to force the pin low against the pull-up
 		   mprj_apply[i] = 1'b0;
 		   #10;
-		   w = mprj_io[i];
-		   if (w != 1'b0) begin
-			$display("Monitor: wire value %b should be 0.", w);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
 			$display("Monitor: Test pullupdown force-low failed.");
 			$finish;
 		   end
 		   mprj_apply[i] = 1'bz;
 		   wait(checkbits_hi == 6'h33);
-		   w = mprj_io[i];
-		   if (w != 1'bz) begin
-			$display("Monitor: wire value %b should be z.", w);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
 			$display("Monitor: Test pullupdown check-disabled failed.");
 			$finish;
 		   end
@@ -147,43 +140,38 @@ module pullupdown_tb;
 		$display("Monitor: Start test of high GPIOs");
 		for (i = 32; i < 38; i++) begin
 		   wait(checkbits_lo == 6'h37);
-		   w = mprj_io[i];
-		   if (w != 1'b0) begin
-			$display("Monitor: wire value %b should be 0.", w);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
 			$display("Monitor: Test pullupdown check-pulldown failed.");
 			$finish;
 		   end
 		   // Should be able to force the pin high against the pull-down
 		   mprj_apply[i] = 1'b1;
 		   #10;
-		   w = mprj_io[i];
-		   if (w != 1'b1) begin
-			$display("Monitor: wire value %b should be 1.", w);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
 			$display("Monitor: Test pullupdown force-high failed.");
 			$finish;
 		   end
 		   mprj_apply[i] = 1'bz;
 		   wait(checkbits_lo == 6'h38);
-		   w = mprj_io[i];
-		   if (w != 1'b1) begin
-			$display("Monitor: wire value %b should be 1.", w);
+		   if (mprj_io[i] !== 1'b1) begin
+			$display("Monitor: wire value %b should be 1.", mprj_io[i]);
 			$display("Monitor: Test pullupdown check-pullup failed.");
 			$finish;
 		   end
 		   // Should be able to force the pin low against the pull-up
 		   mprj_apply[i] = 1'b0;
 		   #10;
-		   w = mprj_io[i];
-		   if (w != 1'b0) begin
-			$display("Monitor: wire value %b should be 0.", w);
+		   if (mprj_io[i] !== 1'b0) begin
+			$display("Monitor: wire value %b should be 0.", mprj_io[i]);
 			$display("Monitor: Test pullupdown force-low failed.");
 			$finish;
 		   end
 		   mprj_apply[i] = 1'bz;
 		   wait(checkbits_lo == 6'h39);
-		   w = mprj_io[i];
-		   if (w != 1'bz) begin
-			$display("Monitor: wire value %b should be z.", w);
+		   if (mprj_io[i] !== 1'bz) begin
+			$display("Monitor: wire value %b should be z.", mprj_io[i]);
 			$display("Monitor: Test pullupdown check-disabled failed.");
 			$finish;
 		   end
diff --git a/verilog/includes/includes.rtl.caravan b/verilog/includes/includes.rtl.caravan
new file mode 100644
index 0000000..1fbf9db
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravan
@@ -0,0 +1,79 @@
+## VIP
+-v $(VERILOG_PATH)/dv/vip/tbuart.v
+-v $(VERILOG_PATH)/dv/vip/spiflash.v
+-v $(VERILOG_PATH)/dv/vip/wb_rw_test.v
+
+## DFFRAM Behavioral Model
+-v $(VERILOG_PATH)/dv/vip/RAM256.v
+-v $(VERILOG_PATH)/dv/vip/RAM128.v
+
+## DFFRAM Full RTL
+#-v $(VERILOG_PATH)/rtl/DFFRAM.v
+#-v $(VERILOG_PATH)/rtl/DFFRAMBB.v
+
+# Mgmt Core Wrapper
+-v $(VERILOG_PATH)/rtl/defines.v
+-v $(VERILOG_PATH)/rtl/mgmt_core.v
+-v $(VERILOG_PATH)/rtl/mgmt_core_wrapper.v
+-v $(VERILOG_PATH)/rtl/VexRiscv_MinDebugCache.v
+
+# Caravel
+
+## These blocks need to stay in RTL
+-v $(CARAVEL_PATH)/rtl/pads.v			
+-v $(CARAVEL_PATH)/rtl/defines.v 		     		
+-v $(CARAVEL_PATH)/rtl/user_defines.v		     
+-v $(CARAVEL_PATH)/rtl/mprj_io.v
+-v $(CARAVEL_PATH)/rtl/simple_por.v		     
+
+## These blocks only needed for RTL sims							     
+-v $(CARAVEL_PATH)/rtl/digital_pll_controller.v 
+-v $(CARAVEL_PATH)/rtl/ring_osc2x13.v		
+-v $(CARAVEL_PATH)/rtl/clock_div.v
+-v $(CARAVEL_PATH)/rtl/housekeeping_spi.v
+					     
+-v $(CARAVEL_PATH)/rtl/chip_io_alt.v
+-v $(CARAVEL_PATH)/rtl/mprj_logic_high.v 	     
+-v $(CARAVEL_PATH)/rtl/mprj2_logic_high.v	     
+-v $(CARAVEL_PATH)/rtl/mgmt_protect.v		     
+-v $(CARAVEL_PATH)/rtl/mgmt_protect_hv.v 	     
+-v $(CARAVEL_PATH)/rtl/gpio_control_block.v	     
+-v $(CARAVEL_PATH)/rtl/gpio_defaults_block.v	     
+-v $(CARAVEL_PATH)/rtl/gpio_logic_high.v 	     
+-v $(CARAVEL_PATH)/rtl/constant_block.v 	     
+-v $(CARAVEL_PATH)/rtl/xres_buf.v		     
+-v $(CARAVEL_PATH)/rtl/spare_logic_block.v	     
+-v $(CARAVEL_PATH)/rtl/housekeeping.v		     
+-v $(CARAVEL_PATH)/rtl/caravel_clocking.v	     
+-v $(CARAVEL_PATH)/rtl/digital_pll.v		     
+#-v $(CARAVEL_PATH)/rtl/__user_analog_project_wrapper.v	     
+-v $(CARAVEL_PATH)/rtl/debug_regs.v
+-v $(CARAVEL_PATH)/rtl/user_id_programming.v
+-v $(CARAVEL_PATH)/rtl/buff_flash_clkrst.v		     
+-v $(CARAVEL_PATH)/rtl/gpio_signal_buffering_alt.v
+-v $(CARAVEL_PATH)/rtl/caravan.v 		     
+
+## These blocks are manually designed 		
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0403.v     
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_1803.v     
+-v $(CARAVEL_PATH)/gl/gpio_defaults_block_0801.v
+
+# STD CELLS - they need to be below the defines.v files 
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+ -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+#-v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v
+
+
+## STD CELLS - they need to be below the defines.v files 
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_ef_io.v
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_io.v
+#-v $(VERILOG_PATH)/cvc-pdk/primitives_hd.v
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_sc_hd.v
+#-v $(VERILOG_PATH)/cvc-pdk/primitives_hvl.v
+#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_sc_hvl.v
+ -v $(VERILOG_PATH)/cvc-pdk/sky130_sram_2kbyte_1rw1r_32x512_8.v
+