diff --git a/manifest b/manifest
index 798bc8b9..b8e72733 100644
--- a/manifest
+++ b/manifest
@@ -1,47 +1,47 @@
-d328f88dd48e015bbaa95e0d7c88954343cc5632  verilog/rtl/DFFRAM.v
-dab57f3c5464ce3354219840dae589a3fcd27135  verilog/rtl/DFFRAMBB.v
+e80d15d008cf6a03a44bba3be5002e32a6effc16  verilog/rtl/DFFRAM.v
+5c35006cfe9fe7c583f5bb6809afdeb2ef527e2d  verilog/rtl/DFFRAMBB.v
 535d0592c0b1349489b6b86fd5449f9d1d81482e  verilog/rtl/__uprj_analog_netlists.v
 87735eb5981740ca4d4b48e6b0321c8bb0023800  verilog/rtl/__uprj_netlists.v
-ef9cf827273c2a245f807725f33bb3bc6e51ba54  verilog/rtl/__user_analog_project_wrapper.v
-c3616f10b8d437432a30dc0dbf2235d50c4f5847  verilog/rtl/__user_project_wrapper.v
-6229bc5cbbe404575340153b4274033ca8d66c38  verilog/rtl/caravan.v
+144fd2bcd269472374fa3ae6162a57f7835871a9  verilog/rtl/__user_analog_project_wrapper.v
+1f83da79ede7775e3b0d3b1c078123a22dc1b94c  verilog/rtl/__user_project_wrapper.v
+3ee8c61791ee73810263d93631e9ee0736012964  verilog/rtl/caravan.v
 31775f9c43c80b137a1cbbc9dd78e4e96708a8e9  verilog/rtl/caravan_netlists.v
-6ff514c11754375cd9c86229d4466c071617e8c2  verilog/rtl/caravel.v
-b2feeb2a098894d5d731a5b011858a471e855d73  verilog/rtl/caravel_clocking.v
-7c4b2a8c1a70bbf13291f25973a4f776c804909e  verilog/rtl/chip_io.v
-a6f9dbe63659a716d85f646b14421b9ad0425186  verilog/rtl/chip_io_alt.v
-d772308bd2a72121d7ed9dcdd40c8e6cbbe4b43c  verilog/rtl/clock_div.v
-f937b52e53d45bdbe41bcbd07c65b41104c21756  verilog/rtl/convert_gpio_sigs.v
-21204dc96bdb3c1295dd06375293ee3d811d2f7e  verilog/rtl/counter_timer_high.v
-6b9b2ab85a85f73d6ce686c67fc85e59d9623ee6  verilog/rtl/counter_timer_low.v
-fff2d08e49701312c2ebd6714b7425baf83f3d35  verilog/rtl/digital_pll.v
-ce49f9af199b5f16d2c39c417d58e5890bc7bab2  verilog/rtl/digital_pll_controller.v
-89dee515f5819e4f5d572f9542ca19798f4b6c4e  verilog/rtl/gpio_control_block.v
-57554b3586f306944b31718a8c52526fa9a8a574  verilog/rtl/gpio_wb.v
-baf3aba29655ca7021398ddc3f68be81eff0fa0c  verilog/rtl/housekeeping_spi.v
-6c11ee92e0b2995982041d8a599b5d46b7dde838  verilog/rtl/la_wb.v
-ff3e65a783f3807340e25efac9207787d39fb6cd  verilog/rtl/mem_wb.v
-0894819fdfdcc1cb7a0fcacca3ac133f9884cc5a  verilog/rtl/mgmt_core.v
-65934e08f3ad2d5fbacd8fc68eae0bb485c25309  verilog/rtl/mgmt_protect.v
-3b1ff20593bc386d13f5e2cf1571f08121889957  verilog/rtl/mgmt_protect_hv.v
-85bc308843b6aad96ac9e75f49c942db8e1c0afe  verilog/rtl/mgmt_soc.v
+fc02a1dd5fddef63591e5aa34bb46c6277c5950b  verilog/rtl/caravel.v
+d8995a9f8cc795b3e8c677166a93c5fd8914d4ab  verilog/rtl/caravel_clocking.v
+a6c35338687c0249898a290c2cc606da3cf4e165  verilog/rtl/chip_io.v
+75d65f67819956159f6cc112a6eb026030269878  verilog/rtl/chip_io_alt.v
+980608198b184e9eab4787c7418626225be1ce91  verilog/rtl/clock_div.v
+bcf4a2476054e72aa4bea78a9d5032849e9568d0  verilog/rtl/convert_gpio_sigs.v
+044c59316aac36d11da8be2c9243b239bb097b02  verilog/rtl/counter_timer_high.v
+6c9e2c65cebd65c77a5ddf2b81fd17781e5ab744  verilog/rtl/counter_timer_low.v
+fa8bd588477f9ad8b63c27eb81cb7623ba449ca4  verilog/rtl/digital_pll.v
+284d191f252dcfbdb03431f2cf0196fb4b969173  verilog/rtl/digital_pll_controller.v
+df03577698eeca10cb4e14dc8ef052d3df9f7378  verilog/rtl/gpio_control_block.v
+325dd37baeab4c05ada86573a894d5d8a4e5da82  verilog/rtl/gpio_wb.v
+1f7ff151c206c41fe5c39d13138b4303aa8dd0a8  verilog/rtl/housekeeping_spi.v
+c6fe30f47b6948c7d13e8e9bced245ed64a17179  verilog/rtl/la_wb.v
+de8921ac6a86f18ad14feb017cfbbc23657f2870  verilog/rtl/mem_wb.v
+ad03a871a8271dfd00564a6acba0ae0b37c325ef  verilog/rtl/mgmt_core.v
+fdf6bbb948ca3386bc81369fc94aff7745fa3637  verilog/rtl/mgmt_protect.v
+93903f794edd129825fe6bbde271bd06baae2ade  verilog/rtl/mgmt_protect_hv.v
+aa21d0aed7f9ef1ac39e56f8f34f336fbee10d4b  verilog/rtl/mgmt_soc.v
 9816acedf3dc3edd193861cc217ec46180ac1cdd  verilog/rtl/mprj2_logic_high.v
-b4395fbd17108e58e33a620159464ae944a15878  verilog/rtl/mprj_ctrl.v
-a61f5566f5d369d879c47d6b65f99cf297debe8f  verilog/rtl/mprj_io.v
+8e2fe315a8d3ab4148782478932c2f7491fef20d  verilog/rtl/mprj_ctrl.v
+86f2596c83b7df0b054d80dce1b33751f9d9ff50  verilog/rtl/mprj_io.v
 b928ab6205a267f6ac83c603965c6f34a486724e  verilog/rtl/mprj_logic_high.v
-eac1e6d413cdfbc2f802e229ae5058828e01be1e  verilog/rtl/pads.v
-b5aff2fda5078cfda377b98337fcc91040815fc2  verilog/rtl/picorv32.v
-669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
-6864cc10dacfd3edb4c66825b7a301ab097cea0d  verilog/rtl/simple_por.v
-917aa6e1bb869f973c79fb2c7894eab882ead74c  verilog/rtl/simple_spi_master.v
-d43221ffa0f2d760991d8b911b4a5292911203f5  verilog/rtl/simpleuart.v
+de677b27ae74fdf2674ceb70df062f90582d4fe6  verilog/rtl/pads.v
+f297c3b729e92baae4f9cf90177278a93cb1f44e  verilog/rtl/picorv32.v
+2668c372527e6879920da9e930d6a1cd44f68fe6  verilog/rtl/ring_osc2x13.v
+b4ee56a9c1999b97a6ad58f0ad98d0e751c85e20  verilog/rtl/simple_por.v
+f46abcc049b7d4a16b331854deee3768483292d0  verilog/rtl/simple_spi_master.v
+fea2533928785182e2ae9ea9d5d47a84b0f25843  verilog/rtl/simpleuart.v
 46bca62460c4dbfac30233318b24c3d526a40058  verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
-eb0c856ab69e8c364c04bdc149db9d82ae67b39d  verilog/rtl/spimemio.v
-3b4c3de623f8af0f0780f1e5b0f2217ef6406a2f  verilog/rtl/sram_1rw1r_32_256_8_sky130.v
-da42d868bfe847b83ed0a3e6e8307216a6f3fa21  verilog/rtl/storage.v
-7e8d789570ed224df49cf61f69593cc738790a5d  verilog/rtl/storage_bridge_wb.v
-5e314e94a13d7291117123395ae088e1d17cf487  verilog/rtl/sysctrl.v
-e6246df6bbf0860a331b3547d64f7d235b0eca9a  verilog/rtl/wb_intercon.v
+3d945b85b5c2d8f1d2eff8d9a189cd1d3a5584f3  verilog/rtl/spimemio.v
+6b55019e80874ccbd43ec3d559499c328eb385d7  verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+4557c05867ca42c3de4f4cd35c1c3195d6b3886f  verilog/rtl/storage.v
+42e604a40a787d25e839664c117c0b7317dd73d5  verilog/rtl/storage_bridge_wb.v
+db70a9a4a296376ae79c3e46bd26985ca6c54f18  verilog/rtl/sysctrl.v
+db9739e72cc1a5c1cd624f0ba3a54b6348ad2a00  verilog/rtl/wb_intercon.v
 9d06bd68e8ec6918cd3ef5467cb8cee44e7e3a26  scripts/set_user_id.py
 be50a23e39bf13eed5090ac819b785afdba587b0  scripts/generate_fill.py
 e3793327393803e44a90a702c5413facbb4b46e8  scripts/compositor.py
diff --git a/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
index 1b32be20..6362479d 100644
--- a/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -211,4 +210,3 @@ module caravan_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index a6bd94df..3a5ff65c 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -193,4 +192,3 @@ module gpio_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index e7af16e4..53a8c226 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
 	StriVe housekeeping SPI testbench.
 */
@@ -428,4 +427,3 @@ module hkspi_tb;
 	);
 		
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index 4aa244a3..a2ef3bc4 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -200,4 +199,3 @@ module mem_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index 6ddfca37..12f98afc 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -173,4 +172,3 @@ module mprj_ctrl_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index dea8dba0..5aa45b66 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*	
  *	StriVe housekeeping pass-thru mode SPI testbench.
  */
@@ -347,4 +346,3 @@ module pass_thru_tb;
 	);
 		
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 25798ec2..85b29281 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -156,4 +155,3 @@ module perf_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index 5c037b06..18057912 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -155,4 +154,3 @@ module pll_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
index d8683b99..ad925d68 100644
--- a/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -202,4 +201,3 @@ module qspi_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index 0adee87b..d380ee3f 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -187,4 +186,3 @@ module storage_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index a39e689f..c1ba5d4c 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
@@ -217,4 +216,3 @@ module sysctrl_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 3865bf33..0e3365c4 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -198,4 +197,3 @@ module timer_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index a53e216d..94ce8a56 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -226,4 +225,3 @@ module timer2_tb;
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index d8bbd35e..dad0a9f8 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017  Clifford Wolf, 2018  Tim Edwards
  *
@@ -147,4 +146,3 @@ module uart_tb;
 	);
 		
 endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
index 6aa29baa..7af4ec19 100644
--- a/verilog/dv/caravel/spiflash.v
+++ b/verilog/dv/caravel/spiflash.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *
diff --git a/verilog/dv/caravel/tbuart.v b/verilog/dv/caravel/tbuart.v
index bac9480e..b0e87a27 100644
--- a/verilog/dv/caravel/tbuart.v
+++ b/verilog/dv/caravel/tbuart.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2017 Clifford Wolf
  *
diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
index be068fc5..876e8f85 100644
--- a/verilog/dv/dummy_slave.v
+++ b/verilog/dv/dummy_slave.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module dummy_slave(
     input wb_clk_i,
     input wb_rst_i,
diff --git a/verilog/dv/wb_utests/chip_io/chip_io_tb.v b/verilog/dv/wb_utests/chip_io/chip_io_tb.v
index 4a004cda..01fdeacb 100644
--- a/verilog/dv/wb_utests/chip_io/chip_io_tb.v
+++ b/verilog/dv/wb_utests/chip_io/chip_io_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
index ea6c7726..5821c6fe 100644
--- a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
index 4f6fd387..35324a8f 100644
--- a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
+++ b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
index a1c10abf..9e3087ea 100644
--- a/verilog/dv/wb_utests/la_wb/la_wb_tb.v
+++ b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `timescale 1 ns / 1 ps
 
 `include "la_wb.v"
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index cfc82aac..9fcec4a5 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
index b90afa8c..9a4ac5d7 100644
--- a/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
+++ b/verilog/dv/wb_utests/mgmt_protect/mgmt_protect_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
index fd9e5a24..24246451 100644
--- a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
index 99cb0081..86cc9b4c 100644
--- a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
index c474fd06..cac66be0 100644
--- a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
+++ b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
index c9aa7682..2377de5c 100644
--- a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // `define DBG
 
 `define STORAGE_BASE_ADR  32'h0100_0000
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index 77140c75..c9fb757c 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
index da481512..9ee7878e 100644
--- a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
+++ b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/gl/__user_project_wrapper.v b/verilog/gl/__user_project_wrapper.v
index eed6cd75..f7a753a0 100644
--- a/verilog/gl/__user_project_wrapper.v
+++ b/verilog/gl/__user_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
index 2488ba23..c550e25a 100644
--- a/verilog/gl/gpio_control_block.v
+++ b/verilog/gl/gpio_control_block.v
@@ -1,4 +1,3 @@
-`default_nettype wire
 module gpio_control_block (mgmt_gpio_in,
     mgmt_gpio_oeb,
     mgmt_gpio_out,
diff --git a/verilog/gl/storage.v b/verilog/gl/storage.v
index f212dc2a..6e71a98b 100644
--- a/verilog/gl/storage.v
+++ b/verilog/gl/storage.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
 
 module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);
diff --git a/verilog/rtl/DFFRAM.v b/verilog/rtl/DFFRAM.v
index b80677f2..494cac9a 100644
--- a/verilog/rtl/DFFRAM.v
+++ b/verilog/rtl/DFFRAM.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `ifndef USE_CUSTOM_DFFRAM
 
 module DFFRAM(
diff --git a/verilog/rtl/DFFRAMBB.v b/verilog/rtl/DFFRAMBB.v
index 22ab55eb..00f977a9 100644
--- a/verilog/rtl/DFFRAMBB.v
+++ b/verilog/rtl/DFFRAMBB.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
     Building blocks for DFF based RAM compiler for SKY130A 
     BYTE        :   8 memory cells used as a building block for WORD module
diff --git a/verilog/rtl/__user_analog_project_wrapper.v b/verilog/rtl/__user_analog_project_wrapper.v
index 5fd2096e..621c7e1c 100644
--- a/verilog/rtl/__user_analog_project_wrapper.v
+++ b/verilog/rtl/__user_analog_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v
index a6d8911b..684c16e7 100644
--- a/verilog/rtl/__user_project_wrapper.v
+++ b/verilog/rtl/__user_project_wrapper.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*
  *-------------------------------------------------------------
  *
diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index da9d245e..4e5b3be6 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -1,4 +1,3 @@
-// `default_nettype none
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -864,4 +863,3 @@ module caravan (
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 1cbc6053..8edba2b8 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,4 +1,3 @@
-// `default_nettype none
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -801,4 +800,3 @@ module caravel (
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index cc0af252..18db9e28 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // This routine synchronizes the 
 
 module caravel_clocking(
@@ -108,4 +107,3 @@ module caravel_clocking(
     assign resetb_sync = ~(reset_delay[0] | ext_reset);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 39529c50..82b1be62 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 module chip_io(
 	// Package Pins
 	inout  vddio,		// Common padframe/ESD supply
@@ -362,4 +361,3 @@ module chip_io(
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v
index 799403df..b47bda6f 100644
--- a/verilog/rtl/chip_io_alt.v
+++ b/verilog/rtl/chip_io_alt.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 
 /* Alternative padframe that removes the GPIO from the top row,	*/
 /* replacing them with un-overlaid power pads which have a	*/
@@ -446,4 +445,3 @@ module chip_io_alt #(
 	);
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 49ff44bf..8bf21c79 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -14,7 +14,6 @@
 // SPDX-License-Identifier: Apache-2.0
 
 /* Integer-N clock divider */
-`default_nettype none
  
 module clock_div #(
     parameter SIZE = 3		// Number of bits for the divider value
@@ -210,4 +209,3 @@ module even #(
     end
  
 endmodule //even
-`default_nettype wire
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index e9e83510..2c9735e1 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Convert the standard set of GPIO signals: input, output, output_enb,
  * pullup, and pulldown into the set needed by the s8 GPIO pads:
  * input, output, output_enb, input_enb, mode.  Note that dm[2] on
@@ -48,4 +47,3 @@ module convert_gpio_sigs (
     assign gpio_mode0_pad = gpio_outenb;
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index e13172eb..80fc33b7 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Simple 32-bit counter-timer for Caravel. */
 
 /* Counter acts as high 32 bits of a 64-bit counter
@@ -95,36 +94,31 @@ module counter_timer_high_wb # (
 endmodule
 
 module counter_timer_high (
-    input resetn,
-    input clkin,
+    input  wire resetn,
+    input  wire clkin,
 
-    input  [3:0]  reg_val_we,
-    input  [31:0] reg_val_di,
-    output [31:0] reg_val_do,
+    input  wire [3:0]  reg_val_we,
+    input  wire [31:0] reg_val_di,
+    output wire [31:0] reg_val_do,
 
-    input 	  reg_cfg_we,
-    input  [31:0] reg_cfg_di,
-    output [31:0] reg_cfg_do,
+    input  wire 	  reg_cfg_we,
+    input  wire [31:0] reg_cfg_di,
+    output wire [31:0] reg_cfg_do,
 
     input  [3:0]  reg_dat_we,
     input  [31:0] reg_dat_di,
     output [31:0] reg_dat_do,
-    input	  stop_in,
-    input	  enable_in,
-    input	  is_offset,
-    input	  strobe,
-    output	  stop_out,
-    output	  enable_out,
-    output	  irq_out
+    input  wire  	stop_in,
+    input  wire 	enable_in, 	// Enable from chained counter
+    input  wire	  	is_offset,
+    input  wire  	strobe,		// Count strobe from low word counter
+    output reg	  	stop_out,	// Stop signal to low word counter
+    output wire	  	enable_out, // Enable to chained counter (sync)
+    output reg  	irq_out
 );
 
 reg [31:0] value_cur;
 reg [31:0] value_reset;
-reg	   irq_out;
-wire	   enable_in;		// Enable from chained counter
-wire	   strobe;		// Count strobe from low word counter
-wire	   enable_out;		// Enable to chained counter (sync)
-reg	   stop_out;		// Stop signal to low word counter
 
 wire [31:0] value_cur_plus;	// Next value, on up-count
 wire [31:0] value_cur_minus;	// Next value, on down-count
@@ -292,4 +286,3 @@ always @(posedge clkin or negedge resetn) begin
 end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index 06ed5d18..3e2d9343 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* Simple 32-bit counter-timer for Caravel. */
 
 /* Counter acts as low 32 bits of a 64-bit counter
@@ -96,42 +95,37 @@ module counter_timer_low_wb # (
 endmodule
 
 module counter_timer_low (
-    input resetn,
-    input clkin,
-
-    input  [3:0]  reg_val_we,
-    input  [31:0] reg_val_di,
-    output [31:0] reg_val_do,
-
-    input 	  reg_cfg_we,
-    input  [31:0] reg_cfg_di,
-    output [31:0] reg_cfg_do,
-
-    input  [3:0]  reg_dat_we,
-    input  [31:0] reg_dat_di,
-    output [31:0] reg_dat_do,
-
-    input	  stop_in,
-    input	  enable_in,
-    output	  strobe,
-    output	  enable_out,
-    output	  stop_out,
-    output	  is_offset,
-    output	  irq_out
+    input  wire 	resetn,
+    input  wire 	clkin,
+
+    input  wire 	[3:0]  reg_val_we,
+    input  wire 	[31:0] reg_val_di,
+    output wire 	[31:0] reg_val_do,
+
+    input  wire  		   reg_cfg_we,
+    input  wire 	[31:0] reg_cfg_di,
+    output wire 	[31:0] reg_cfg_do,
+
+    input  wire		[3:0]  reg_dat_we,
+    input  wire		[31:0] reg_dat_di,
+    output wire		[31:0] reg_dat_do,
+
+    input	wire  	stop_in, // High 32 bits counter has stopped
+    input	wire 	enable_in,
+    output	reg  	strobe, // Strobe to high 32 bits counter; occurs
+							// one cycle before actual timeout and
+							// irq signal.
+    output	wire  	enable_out,
+    output	reg  	stop_out, // Stop condition flag
+    output	wire  	is_offset,
+    output	reg  	irq_out
 );
 
 reg [31:0] value_cur;
-reg [31:0] value_reset;
-reg	   irq_out;
-wire	   stop_in;		// High 32 bits counter has stopped
-reg	   strobe;		// Strobe to high 32 bits counter; occurs
-				// one cycle before actual timeout and
-				// irq signal.
-reg	   stop_out;		// Stop condition flag
+reg [31:0] value_reset;			
 
 wire [31:0] value_cur_plus;	// Next value, on up-count
 wire [31:0] value_cur_minus;	// Next value, on down-count
-wire	    is_offset;
 wire	    loc_enable;
 
 reg enable;	// Enable (start) the counter/timer
@@ -324,4 +318,3 @@ always @(posedge clkin or negedge resetn) begin
 end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 7fefe52d..a59f3643 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 
 `ifndef __GLOBAL_DEFINE_H
 // Global parameters
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index b8dd69e9..9e5092ac 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // Digital PLL (ring oscillator + controller)
 // Technically this is a frequency locked loop, not a phase locked loop.
 
@@ -68,4 +67,3 @@ module digital_pll(
     );
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index ae13d9d1..68e8c435 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // (True) digital PLL
 //
 // Output goes to a trimmable ring oscillator (see documentation).
@@ -133,4 +132,3 @@ module digital_pll_controller(reset, clock, osc, div, trim);
     end
 
 endmodule	// digital_pll_controller
-`default_nettype wire
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 7d5924bf..665ee69a 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /* 
  *---------------------------------------------------------------------
  * See gpio_control_block for description.  This module is like
@@ -67,42 +66,42 @@ module gpio_control_block #(
     `endif
 
     // Management Soc-facing signals
-    input  	     resetn,		// Global reset, locally propagated
-    output       resetn_out,
-    input  	     serial_clock,		// Global clock, locally propatated
-    output  	 serial_clock_out,
+    input  	 wire resetn,		// Global reset, locally propagated
+    output   wire resetn_out,
+    input  	 wire serial_clock,		// Global clock, locally propatated
+    output   wire serial_clock_out,
 
-    output       mgmt_gpio_in,		// Management from pad (input only)
-    input        mgmt_gpio_out,		// Management to pad (output only)
-    input        mgmt_gpio_oeb,		// Management to pad (output only)
+    output   wire mgmt_gpio_in,		// Management from pad (input only)
+    input    wire mgmt_gpio_out,    // Management to pad (output only)
+    input    wire mgmt_gpio_oeb,	// Management to pad (output only)
 
     // Serial data chain for pad configuration
-    input  	 serial_data_in,
-    output 	 serial_data_out,
+    input  	 wire serial_data_in,
+    output 	 wire serial_data_out,
 
     // User-facing signals
-    input        user_gpio_out,		// User space to pad
-    input        user_gpio_oeb,		// Output enable (user)
-    output	 user_gpio_in,		// Pad to user space
+    input    wire user_gpio_out,		// User space to pad
+    input    wire user_gpio_oeb,		// Output enable (user)
+    output	 wire user_gpio_in,		// Pad to user space
 
     // Pad-facing signals (Pad GPIOv2)
-    output	 pad_gpio_holdover,
-    output	 pad_gpio_slow_sel,
-    output	 pad_gpio_vtrip_sel,
-    output       pad_gpio_inenb,
-    output       pad_gpio_ib_mode_sel,
-    output	 pad_gpio_ana_en,
-    output	 pad_gpio_ana_sel,
-    output	 pad_gpio_ana_pol,
-    output [2:0] pad_gpio_dm,
-    output       pad_gpio_outenb,
-    output	 pad_gpio_out,
-    input	 pad_gpio_in,
+    output	 wire pad_gpio_holdover,
+    output	 wire pad_gpio_slow_sel,
+    output	 wire pad_gpio_vtrip_sel,
+    output   wire pad_gpio_inenb,
+    output   wire pad_gpio_ib_mode_sel,
+    output	 wire pad_gpio_ana_en,
+    output	 wire pad_gpio_ana_sel,
+    output	 wire pad_gpio_ana_pol,
+    output   wire [2:0] pad_gpio_dm,
+    output   wire pad_gpio_outenb,
+    output	 wire pad_gpio_out,
+    input	 wire pad_gpio_in,
 
     // to provide a way to automatically disable/enable output
     // from the outside with needing a conb cell
-    output	 one,
-    output	 zero
+    output	 wire one,
+    output	 wire zero
 );
 
     /* Parameters defining the bit offset of each function in the chain */
@@ -131,23 +130,6 @@ module gpio_control_block #(
     reg	 	gpio_ana_sel;
     reg	 	gpio_ana_pol;
 
-    /* Derived output values */
-    wire	pad_gpio_holdover;
-    wire	pad_gpio_slow_sel;
-    wire	pad_gpio_vtrip_sel;
-    wire      	pad_gpio_inenb;
-    wire       	pad_gpio_ib_mode_sel;
-    wire	pad_gpio_ana_en;
-    wire	pad_gpio_ana_sel;
-    wire	pad_gpio_ana_pol;
-    wire [2:0]  pad_gpio_dm;
-    wire        pad_gpio_outenb;
-    wire	pad_gpio_out;
-    wire	pad_gpio_in;
-    wire	one;
-    wire	zero;
-
-    wire user_gpio_in;
     wire gpio_in_unbuf;
     wire gpio_logic1;
 
@@ -278,4 +260,3 @@ module gpio_control_block #(
     );
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 9941fc96..ffab49a3 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module gpio_wb # (
     parameter BASE_ADR  = 32'h 2100_0000,
     parameter GPIO_DATA = 8'h 00,
@@ -98,17 +97,12 @@ module gpio #(
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    output gpio,
-    output gpio_oeb,
-    output gpio_pu,
-    output gpio_pd
+    output reg  gpio,       // GPIO output data
+    output reg  gpio_oeb,   // GPIO pull-up enable
+    output reg  gpio_pu,    // GPIO pull-down enable
+    output reg  gpio_pd     // GPIO output enable (sense negative)
 );
-
-    reg gpio;		// GPIO output data
-    reg gpio_pu;		// GPIO pull-up enable
-    reg gpio_pd;		// GPIO pull-down enable
-    reg gpio_oeb;    // GPIO output enable (sense negative)
-    
+ 
     wire gpio_sel;
     wire gpio_oeb_sel;
     wire gpio_pu_sel;  
@@ -153,4 +147,3 @@ module gpio #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 37c27c86..1540806b 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 //-------------------------------------
 // SPI controller for Caravel (PicoSoC)
 //-------------------------------------
@@ -491,4 +490,3 @@ module housekeeping_spi_slave(reset, SCK, SDI, CSB, SDO,
     end			// always @ SCK
 
 endmodule // housekeeping_spi_slave
-`default_nettype wire
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index fbbc77cf..eaa058f9 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module la_wb # (
     parameter BASE_ADR  = 32'h 2200_0000,
     parameter LA_DATA_0 = 8'h00,
@@ -302,4 +301,3 @@ module la #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 01bd2e1a..61d85124 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -13,24 +13,23 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module mem_wb (
 `ifdef USE_POWER_PINS
     input VPWR,
     input VGND,
 `endif
-    input wb_clk_i,
-    input wb_rst_i,
-
-    input [31:0] wb_adr_i,
-    input [31:0] wb_dat_i,
-    input [3:0] wb_sel_i,
-    input wb_we_i,
-    input wb_cyc_i,
-    input wb_stb_i,
-
-    output wb_ack_o,
-    output [31:0] wb_dat_o
+    input  wire wb_clk_i,
+    input  wire wb_rst_i,
+
+    input  wire [31:0]  wb_adr_i,
+    input  wire [31:0]  wb_dat_i,
+    input  wire [3:0]   wb_sel_i,
+    input  wire         wb_we_i,
+    input  wire         wb_cyc_i,
+    input  wire         wb_stb_i,
+
+    output reg          wb_ack_o,
+    output wire [31:0]  wb_dat_o
     
 );
 
@@ -52,7 +51,6 @@ module mem_wb (
     */ 
 
     reg wb_ack_read;
-    reg wb_ack_o;
 
     always @(posedge wb_clk_i) begin
         if (wb_rst_i == 1'b 1) begin
@@ -138,4 +136,3 @@ module soc_mem
 `endif
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index c7eff11a..814b0809 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -13,113 +13,111 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module mgmt_core (
 `ifdef USE_POWER_PINS
 	inout VPWR,	   
 	inout VGND,
 `endif
 	// GPIO (dedicated pad)
-	output gpio_out_pad,		// Connect to out on gpio pad
-	input  gpio_in_pad,		// Connect to in on gpio pad
-	output gpio_mode0_pad,		// Connect to dm[0] on gpio pad
-	output gpio_mode1_pad,		// Connect to dm[2] on gpio pad
-	output gpio_outenb_pad,		// Connect to oe_n on gpio pad
-	output gpio_inenb_pad,		// Connect to inp_dis on gpio pad
+	output wire gpio_out_pad,		// Connect to out on gpio pad
+	input  wire gpio_in_pad,		// Connect to in on gpio pad
+	output wire gpio_mode0_pad,		// Connect to dm[0] on gpio pad
+	output wire gpio_mode1_pad,		// Connect to dm[2] on gpio pad
+	output wire gpio_outenb_pad,		// Connect to oe_n on gpio pad
+	output wire gpio_inenb_pad,		// Connect to inp_dis on gpio pad
 	// Flash memory control (SPI master)
-	output flash_csb,
-	output flash_clk,
-	output flash_csb_oeb,
-	output flash_clk_oeb,
-	output flash_io0_oeb,
-	output flash_io1_oeb,
-	output flash_io2_oeb,	// through GPIO 36
-	output flash_io3_oeb,	// through GPIO 37
-	output flash_csb_ieb,
-	output flash_clk_ieb,
-	output flash_io0_ieb,
-	output flash_io1_ieb,
-	output flash_io0_do,
-	output flash_io1_do,
-	output flash_io2_do,	// through GPIO 36
-	output flash_io3_do,	// through GPIO 37
-	input flash_io0_di,
-	input flash_io1_di,
+	output wire flash_csb,
+	output wire flash_clk,
+	output wire flash_csb_oeb,
+	output wire flash_clk_oeb,
+	output wire flash_io0_oeb,
+	output wire flash_io1_oeb,
+	output wire flash_io2_oeb,	// through GPIO 36
+	output wire flash_io3_oeb,	// through GPIO 37
+	output wire flash_csb_ieb,
+	output wire flash_clk_ieb,
+	output wire flash_io0_ieb,
+	output wire flash_io1_ieb,
+	output wire flash_io0_do,
+	output wire flash_io1_do,
+	output wire flash_io2_do,	// through GPIO 36
+	output wire flash_io3_do,	// through GPIO 37
+	input  wire flash_io0_di,
+	input  wire flash_io1_di,
 	// Master reset
-	input resetb,
-	input porb,
+	input  wire resetb,
+	input  wire porb,
 	// Clocking
-	input clock,
+	input  wire clock,
 	// LA signals
-    	input  [127:0] la_input,           	// From User Project to cpu
-    	output [127:0] la_output,          	// From CPU to User Project
-    	output [127:0] la_oenb,                 // LA output enable  
-    	output [127:0] la_iena,                 // LA input enable  
+	input  wire [127:0] la_input,           	// From User Project to cpu
+	output wire [127:0] la_output,          	// From CPU to User Project
+	output wire [127:0] la_oenb,                 // LA output enable  
+	output wire [127:0] la_iena,                 // LA input enable  
 	// Housekeeping SPI
-	output sdo_out,
-	output sdo_outenb,
+	output wire sdo_out,
+	output wire sdo_outenb,
 	// JTAG
-	output jtag_out,
-	output jtag_outenb,
+	output wire jtag_out,
+	output wire jtag_outenb,
 	// User Project Control Signals
-	input [`MPRJ_IO_PADS-1:0] mgmt_in_data,
-	output [`MPRJ_IO_PADS-1:0] mgmt_out_data,
-	output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
-	input mprj_vcc_pwrgood,
-	input mprj2_vcc_pwrgood,
-	input mprj_vdd_pwrgood,
-	input mprj2_vdd_pwrgood,
-	output mprj_io_loader_resetn,
-	output mprj_io_loader_clock,
-	output mprj_io_loader_data_1,
-	output mprj_io_loader_data_2,
+	input  wire [`MPRJ_IO_PADS-1:0] mgmt_in_data,
+	output wire [`MPRJ_IO_PADS-1:0] mgmt_out_data,
+	output wire [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
+	input  wire mprj_vcc_pwrgood,
+	input  wire mprj2_vcc_pwrgood,
+	input  wire mprj_vdd_pwrgood,
+	input  wire mprj2_vdd_pwrgood,
+	output wire mprj_io_loader_resetn,
+	output wire mprj_io_loader_clock,
+	output wire mprj_io_loader_data_1,
+	output wire mprj_io_loader_data_2,
 	// WB MI A (User project)
-    	input mprj_ack_i,
-	input [31:0] mprj_dat_i,
-    	output mprj_cyc_o,
-	output mprj_stb_o,
-	output mprj_we_o,
-	output [3:0] mprj_sel_o,
-	output [31:0] mprj_adr_o,
-	output [31:0] mprj_dat_o,
+	input  wire mprj_ack_i,
+	input  wire [31:0] mprj_dat_i,
+	output wire mprj_cyc_o,
+	output wire mprj_stb_o,
+	output wire mprj_we_o,
+	output wire [3:0] mprj_sel_o,
+	output wire [31:0] mprj_adr_o,
+	output wire [31:0] mprj_dat_o,
 	
-    	output core_clk,
-    	output user_clk,
-    	output core_rstn,
-	input [2:0] user_irq,
-	output [2:0] user_irq_ena,
+    output wire core_clk,
+    output wire user_clk,
+    output wire core_rstn,
+	input  wire [2:0] user_irq,
+	output wire [2:0] user_irq_ena,
 
 	// Metal programmed user ID / mask revision vector
-	input [31:0] mask_rev,
+	input  wire [31:0] mask_rev,
 	
     // MGMT area R/W interface for mgmt RAM
-    output [`RAM_BLOCKS-1:0] mgmt_ena, 
-    output [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
-    output [`RAM_BLOCKS-1:0] mgmt_wen,
-    output [7:0] mgmt_addr,
-    output [31:0] mgmt_wdata,
-    input  [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
+    output wire [`RAM_BLOCKS-1:0] mgmt_ena, 
+    output wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
+    output wire [`RAM_BLOCKS-1:0] mgmt_wen,
+    output wire [7:0] mgmt_addr,
+    output wire [31:0] mgmt_wdata,
+    input  wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
 
     // MGMT area RO interface for user RAM 
-    output mgmt_ena_ro,
-    output [7:0] mgmt_addr_ro,
-    input  [31:0] mgmt_rdata_ro
+    output wire mgmt_ena_ro,
+    output wire [7:0] mgmt_addr_ro,
+    input  wire [31:0] mgmt_rdata_ro
 );
-    	wire ext_clk_sel;
-    	wire pll_clk, pll_clk90;
-    	wire ext_reset;
+
+	wire ext_clk_sel;
+    wire pll_clk, pll_clk90;
+    wire ext_reset;
 	wire hk_connect;
 	wire trap;
 	wire irq_spi;
 
 	// JTAG (to be implemented)
-	wire jtag_out;
 	wire jtag_out_pre = 1'b0;
-	wire jtag_outenb = 1'b1;
+	//wire jtag_outenb = 1'b1;
 	wire jtag_oenb_state;
 
 	// SDO
-	wire sdo_out;
 	wire sdo_out_pre;
 	wire sdo_oenb_state;
 
@@ -154,10 +152,8 @@ module mgmt_core (
 
 	// These wires are defined in the SoC but are not being used because
 	// the SoC flash is reduced to a 2-pin I/O
-	wire flash_io2_oeb, flash_io3_oeb;
 	wire flash_io2_ieb, flash_io3_ieb;
 	wire flash_io2_di, flash_io3_di;
-	wire flash_io2_do, flash_io3_do;
 
 	wire pass_thru_mgmt_sdo, pass_thru_mgmt_csb;
 	wire pass_thru_mgmt_sck, pass_thru_mgmt_sdi;
@@ -334,4 +330,3 @@ module mgmt_core (
 	);
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 4d5fd113..cfc401b7 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*----------------------------------------------------------------------*/
 /* Buffers protecting the management region from the user region.	*/
 /* This mainly consists of tristate buffers that are enabled by a	*/
@@ -79,10 +78,10 @@ module mgmt_protect (
     output [31:0] mprj_adr_o_user,
     output [31:0] mprj_dat_o_user,
     output [2:0]  user_irq,
-    output	  user1_vcc_powergood,
-    output	  user2_vcc_powergood,
-    output	  user1_vdd_powergood,
-    output	  user2_vdd_powergood
+    output wire user1_vcc_powergood,
+    output wire	user2_vcc_powergood,
+    output wire user1_vdd_powergood,
+    output wire user2_vdd_powergood
 );
 
 	wire [461:0] mprj_logic1;
@@ -93,11 +92,6 @@ module mgmt_protect (
 	wire mprj_vdd_logic1;
 	wire mprj2_vdd_logic1;
 
-	wire user1_vcc_powergood;
-	wire user2_vcc_powergood;
-	wire user1_vdd_powergood;
-	wire user2_vdd_powergood;
-
 	wire [127:0] la_data_in_mprj_bar;
 	wire [2:0] user_irq_bar;
 
@@ -422,4 +416,3 @@ module mgmt_protect (
                 .X(user2_vdd_powergood)
 	);
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
index 23d9cf60..f6cff356 100644
--- a/verilog/rtl/mgmt_protect_hv.v
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 /*----------------------------------------------------------------------*/
 /* mgmt_protect_hv:							*/
 /*									*/
@@ -45,8 +44,11 @@ module mgmt_protect_hv (
 `ifdef USE_POWER_PINS
     // This is to emulate the substrate shorting grounds together for LVS
     // purposes
-    assign vssa2 = vssa1;
-    assign vssa1 = vssd;
+    `ifndef SIM
+        assign vssa2 = vssa1;
+        assign vssa1 = vssd;
+    `endif
+    
 `endif
 
     // Logic high in the VDDA (3.3V) domains
@@ -100,4 +102,3 @@ module mgmt_protect_hv (
     );
 endmodule
 
-`default_nettype wire
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index d8ae5487..8f405625 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoSoC - A simple example SoC using PicoRV32
@@ -500,6 +499,12 @@ module mgmt_soc (
         .ser_rx(mgmt_in_data[5])
     );
 
+    // WB Slave User Project Control
+    wire mprj_ctrl_stb_i;
+    wire mprj_ctrl_ack_o;
+    wire [31:0] mprj_ctrl_dat_o;
+    wire [`MPRJ_IO_PADS-1:0] mgmt_out_pre;
+
     // Wishbone SPI master
     wire spi_master_stb_i;
     wire spi_master_ack_o;
@@ -716,12 +721,6 @@ module mgmt_soc (
     assign mprj_adr_o = cpu_adr_o;
     assign mprj_dat_o = cpu_dat_o;
 
-    // WB Slave User Project Control
-    wire mprj_ctrl_stb_i;
-    wire mprj_ctrl_ack_o;
-    wire [31:0] mprj_ctrl_dat_o;
-    wire [`MPRJ_IO_PADS-1:0] mgmt_out_pre;
-
     // Bits assigned to specific functions as outputs prevent the
     // mprj GPIO-as-output from applying data when that function
     // is active
@@ -887,4 +886,3 @@ module mgmt_soc_regs (
     assign rdata1 = regs[raddr1[4:0]];
     assign rdata2 = regs[raddr2[4:0]];
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 679c7f13..03f76264 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module mprj_ctrl_wb #(
     parameter BASE_ADR  = 32'h 2300_0000,
     parameter XFER      = 8'h 00,
@@ -125,20 +124,22 @@ module mprj_ctrl #(
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    output serial_clock,
-    output serial_resetn,
-    output serial_data_out_1,
-    output serial_data_out_2,
-    output sdo_oenb_state,
-    output jtag_oenb_state,
-    output flash_io2_oenb_state,
-    output flash_io3_oenb_state,
-    input  [`MPRJ_IO_PADS-1:0] mgmt_gpio_in,
-    output [`MPRJ_IO_PADS-1:0] mgmt_gpio_out,
-    output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
-    output [2:0] user_irq_ena
+    output reg  serial_clock,
+    output reg  serial_resetn,
+    output wire serial_data_out_1,
+    output wire serial_data_out_2,
+    output wire sdo_oenb_state,
+    output wire jtag_oenb_state,
+    output wire flash_io2_oenb_state,
+    output wire flash_io3_oenb_state,
+    input  wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_in,
+    output wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out,  // I/O write data output when input disabled
+    output reg  [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,  // Power write data, 1 bit per power pad    
+    output reg  [2:0] user_irq_ena                  // Enable user to raise IRQs
 );
 
+
+
 `define IDLE	2'b00
 `define START	2'b01
 `define XBYTE	2'b10
@@ -153,9 +154,6 @@ module mprj_ctrl #(
 
     reg  [IO_CTRL_BITS-1:0] io_ctrl[`MPRJ_IO_PADS-1:0];  // I/O control, 1 word per gpio pad
     reg  [`MPRJ_IO_PADS-1:0] mgmt_gpio_outr; 	 // I/O write data, 1 bit per gpio pad
-    wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out;	 // I/O write data output when input disabled
-    reg  [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out;	 // Power write data, 1 bit per power pad
-    reg  [2:0] user_irq_ena;		 // Enable user to raise IRQs
     reg xfer_ctrl;			 // Transfer control (1 bit)
 
     wire [IO_WORDS-1:0] io_data_sel;	// wishbone selects
@@ -167,10 +165,7 @@ module mprj_ctrl #(
     wire [`MPRJ_IO_PADS-1:0] io_ctrl_sel;
     reg [31:0] iomem_rdata_pre;
 
-    wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_in;
 
-    wire sdo_oenb_state, jtag_oenb_state;
-    wire flash_io2_oenb_state, flash_io3_oenb_state;
 
     // JTAG and housekeeping SDO are normally controlled by their respective
     // modules with OEB set to the default 1 value.  If configured for an
@@ -340,14 +335,10 @@ module mprj_ctrl #(
     reg [4:0]  pad_count_1;
     reg [5:0]  pad_count_2;
     reg [1:0]  xfer_state;
-    reg	       serial_clock;
-    reg	       serial_resetn;
 
     reg [IO_CTRL_BITS-1:0] serial_data_staging_1;
     reg [IO_CTRL_BITS-1:0] serial_data_staging_2;
 
-    wire       serial_data_out_1;
-    wire       serial_data_out_2;
 
     assign serial_data_out_1 = serial_data_staging_1[IO_CTRL_BITS-1];
     assign serial_data_out_2 = serial_data_staging_2[IO_CTRL_BITS-1];
@@ -432,4 +423,3 @@ module mprj_ctrl #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 3a94da0e..f7958bd8 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 
 /* Define the array of GPIO pads.  Note that the analog project support
  * version of caravel (caravan) defines fewer GPIO and replaces them
@@ -135,4 +134,3 @@ module mprj_io #(
     );
 
 endmodule
-// `default_nettype wire
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index f89ba908..306e8ba9 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-// `default_nettype none
 `ifndef TOP_ROUTING 
 	`define USER1_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
@@ -169,4 +168,3 @@
 		.TIE_HI_ESD(), \
 		.TIE_LO_ESD(loop_``X) )
 
-// `default_nettype wire
diff --git a/verilog/rtl/picorv32.v b/verilog/rtl/picorv32.v
index 13162736..1249ad53 100644
--- a/verilog/rtl/picorv32.v
+++ b/verilog/rtl/picorv32.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
@@ -3045,4 +3044,3 @@ module picorv32_wb #(
 		end
 	end
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index f20110e9..21870707 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // Tunable ring oscillator---synthesizable (physical) version.
 //
 // NOTE:  This netlist cannot be simulated correctly due to lack
@@ -247,4 +246,3 @@ module ring_osc2x13(reset, trim, clockp);
 `endif // !FUNCTIONAL
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index 8168c0bb..d5d6b55f 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 `timescale 1 ns / 1 ps
 
 module simple_por(
@@ -22,12 +21,12 @@ module simple_por(
     inout vdd1v8,
     inout vss,
 `endif
-    output porb_h,
-    output porb_l,
-    output por_l
+    output wire porb_h,
+    output wire porb_l,
+    output wire por_l
 );
 
-    wire mid, porb_h;
+    wire mid;
     reg inode;
 
     // This is a behavioral model!  Actual circuit is a resitor dumping
@@ -89,4 +88,3 @@ module simple_por(
     // replaced by a proper inverter
     assign por_l = ~porb_l;
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index c319de82..bda80a68 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -1,4 +1,3 @@
-`default_nettype none
 // SPDX-FileCopyrightText: 2019 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
@@ -148,26 +147,26 @@ module simple_spi_master_wb #(
 endmodule
 
 module simple_spi_master (
-    input        resetn,
-    input        clk,	 // master clock (assume 100MHz)
+    input   wire        resetn,
+    input   wire        clk,	 // master clock (assume 100MHz)
 
-    input  [1:0]  reg_cfg_we,
-    input  [31:0] reg_cfg_di,
-    output [31:0] reg_cfg_do,
+    input   wire  [1:0]  reg_cfg_we,
+    input   wire  [31:0] reg_cfg_di,
+    output  wire  [31:0] reg_cfg_do,
 
-    input  	  reg_dat_we,
-    input  	  reg_dat_re,
-    input  [31:0] reg_dat_di,
-    output [31:0] reg_dat_do,
-    output	  reg_dat_wait,
-    output	  irq_out,
-    output	  err_out,
+    input  	wire  reg_dat_we,
+    input  	wire  reg_dat_re,
+    input   wire  [31:0] reg_dat_di,
+    output  wire  [31:0] reg_dat_do,
+    output	wire  reg_dat_wait,
+    output	wire  irq_out,
+    output	reg   err_out,
 
-    output	 hk_connect,	// Connect to housekeeping SPI
-    input 	 sdi,	 // SPI input
-    output 	 csb,	 // SPI chip select
-    output 	 sck,	 // SPI clock
-    output 	 sdo	 // SPI output
+    output	 wire hk_connect,	// Connect to housekeeping SPI
+    input 	 wire sdi,	 // SPI input
+    output 	 wire csb,	 // SPI chip select
+    output 	 wire sck,	 // SPI clock
+    output 	 wire sdo	 // SPI output
 );
 
     parameter IDLE   = 2'b00;	    
@@ -179,8 +178,7 @@ module simple_spi_master (
     reg 	  isdo, hsck, icsb;
     reg [1:0] state;
     reg 	  isck;
-    reg	  err_out;
- 
+
     reg [7:0]  treg, rreg, d_latched;
     reg [2:0]  nbit;
 
@@ -195,12 +193,7 @@ module simple_spi_master (
     reg	   enable;
     reg	   hkconn;
  
-    wire	  csb;
-    wire	  irq_out;
-    wire	  sck;
-    wire	  sdo;
     wire	  sdoenb;
-    wire	  hk_connect;
 
     // Define behavior for inverted SCK and inverted CSB
     assign    	  csb = (enable == 1'b0) ? 1'bz : (invcsb) ? ~icsb : icsb;
@@ -403,4 +396,3 @@ module simple_spi_master (
     end // always
  
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 12be1671..24ba06e8 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoSoC - A simple example SoC using PicoRV32
@@ -97,7 +96,7 @@ module simpleuart (
     input clk,
     input resetn,
 
-    output enabled,
+    output reg enabled,
     output ser_tx,
     input  ser_rx,
 
@@ -116,7 +115,6 @@ module simpleuart (
     output        reg_dat_wait
 );
     reg [31:0] cfg_divider;
-    reg        enabled;
 
     reg [3:0] recv_state;
     reg [31:0] recv_divcnt;
@@ -220,4 +218,3 @@ module simpleuart (
         end
     end
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index 0e3c95fe..ea602cbd 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  *  SPDX-FileCopyrightText: 2015 Clifford Wolf
  *  PicoSoC - A simple example SoC using PicoRV32
@@ -39,7 +38,7 @@ module spimemio_wb (
     output [31:0] wb_flash_dat_o,
     output [31:0] wb_cfg_dat_o,
 
-    output quad_mode,
+    output wire quad_mode,
     input  pass_thru,
     input  pass_thru_csb,
     input  pass_thru_sck,
@@ -84,7 +83,6 @@ module spimemio_wb (
     wire spimemio_cfgreg_sel;
     wire valid;
     wire resetn;
-    wire quad_mode;
 
     assign resetn = ~wb_rst_i;
     assign valid = wb_cyc_i && wb_flash_stb_i;    
@@ -190,13 +188,13 @@ module spimemio (
     input  [31:0] cfgreg_di,
     output [31:0] cfgreg_do,
 
-    output quad_mode,
+    output wire quad_mode,
 
-    input  pass_thru,
-    input  pass_thru_csb,
-    input  pass_thru_sck,
-    input  pass_thru_sdi,
-    output pass_thru_sdo
+    input  wire pass_thru,
+    input  wire pass_thru_csb,
+    input  wire pass_thru_sck,
+    input  wire pass_thru_sdi,
+    output wire pass_thru_sdo
 );
     reg        xfer_resetn;
     reg        din_valid;
@@ -211,7 +209,6 @@ module spimemio (
     wire       dout_valid;
     wire [7:0] dout_data;
     wire [3:0] dout_tag;
-    wire       quad_mode;
 
     reg [23:0] buffer;
 
@@ -307,11 +304,6 @@ module spimemio (
         xfer_io3_90 <= xfer_io3_do;
     end
 
-    wire pass_thru;
-    wire pass_thru_csb;
-    wire pass_thru_sck;
-    wire pass_thru_sdi;
-    wire pass_thru_sdo;
 
     assign quad_mode = config_qspi;
 
@@ -750,4 +742,3 @@ module spimemio_xfer (
     end
 endmodule
 
-`default_nettype wire
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index f6220797..5a23804e 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // OpenRAM SRAM model
 // Words: 256
 // Word size: 32
@@ -130,4 +129,3 @@ reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
   end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index 01dac0dc..8c6c5d46 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
  
 module storage (
     // MGMT_AREA R/W Interface 
@@ -62,4 +61,3 @@ module storage (
     );  
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index 0f243215..edd48c5a 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module storage_bridge_wb (
     // MGMT_AREA R/W WB Interface
     input wb_clk_i,
@@ -109,4 +108,3 @@ module storage_bridge_wb (
     assign wb_ro_dat_o = mgmt_rdata_ro;
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index c18979eb..71af2ab5 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module sysctrl_wb #(
     parameter BASE_ADR     = 32'h2F00_0000,
     parameter PWRGOOD	   = 8'h00,
@@ -94,38 +93,27 @@ module sysctrl #(
     parameter TRAP_OUT     = 8'h08,
     parameter IRQ_SRC      = 8'h0c
 ) (
-    input clk,
-    input resetn,
+    input  wire clk,
+    input  wire resetn,
     
-    input [31:0] iomem_addr,
-    input iomem_valid,
-    input [3:0] iomem_wstrb,
-    input [31:0] iomem_wdata,
-    output reg [31:0] iomem_rdata,
-    output reg iomem_ready,
-
-    input  usr1_vcc_pwrgood,
-    input  usr2_vcc_pwrgood,
-    input  usr1_vdd_pwrgood,
-    input  usr2_vdd_pwrgood,
-    output clk1_output_dest,
-    output clk2_output_dest,
-    output trap_output_dest,
-    output irq_7_inputsrc,
-    output irq_8_inputsrc
+    input  wire [31:0]  iomem_addr,
+    input  wire         iomem_valid,
+    input  wire [3:0]   iomem_wstrb,
+    input  wire [31:0]  iomem_wdata,
+    output reg  [31:0]  iomem_rdata,
+    output reg          iomem_ready,
+
+    input  wire usr1_vcc_pwrgood,
+    input  wire usr2_vcc_pwrgood,
+    input  wire usr1_vdd_pwrgood,
+    input  wire usr2_vdd_pwrgood,
+    output reg  clk1_output_dest,
+    output reg  clk2_output_dest,
+    output reg  trap_output_dest,
+    output reg  irq_7_inputsrc,
+    output reg  irq_8_inputsrc
 ); 
 
-    reg clk1_output_dest;
-    reg clk2_output_dest;
-    reg trap_output_dest;
-    reg irq_7_inputsrc;
-    reg irq_8_inputsrc;
-
-    wire usr1_vcc_pwrgood;
-    wire usr2_vcc_pwrgood;
-    wire usr1_vdd_pwrgood;
-    wire usr2_vdd_pwrgood;
-
     wire pwrgood_sel;
     wire clk_out_sel;
     wire trap_out_sel;
@@ -177,4 +165,3 @@ module sysctrl #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 873bbce2..98c5b942 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -13,7 +13,6 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 // This module represents an unprogrammed mask revision
 // block that is configured with via programming on the
 // chip top level.  This value is passed to the block as
@@ -26,9 +25,8 @@ module user_id_programming #(
     inout VPWR,
     inout VGND,
 `endif
-    output [31:0] mask_rev
+    output wire [31:0] mask_rev
 );
-    wire [31:0] mask_rev;
     wire [31:0] user_proj_id_high;
     wire [31:0] user_proj_id_low;
 
@@ -54,4 +52,3 @@ module user_id_programming #(
     endgenerate
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 7ebce83f..4262271c 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -13,24 +13,10 @@
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
 
-`default_nettype none
 module wb_intercon #(
     parameter DW = 32,          // Data Width
     parameter AW = 32,          // Address Width
-    parameter NS = 6           // Number of Slaves
-) (
-    // Master Interface
-    input [AW-1:0] wbm_adr_i,
-    input wbm_stb_i,
-
-    output reg [DW-1:0] wbm_dat_o,
-    output wbm_ack_o,
-
-    // Slave Interface
-    input [NS*DW-1:0] wbs_dat_i,
-    input [NS-1:0] wbs_ack_i,
-    output [NS-1:0] wbs_stb_o
-);
+    parameter NS = 6,           // Number of Slaves
     parameter [NS*AW-1:0] ADR_MASK = {      // Page & Sub-page bits
         {8'hFF, {24{1'b0}} },
         {8'hFF, {24{1'b0}} },
@@ -38,7 +24,7 @@ module wb_intercon #(
         {8'hFF, {24{1'b0}} },
         {8'hFF, {24{1'b0}} },
         {8'hFF, {24{1'b0}} }
-    };
+    },
     parameter [NS*AW-1:0] SLAVE_ADR = {
         { 32'h2800_0000 },    // Flash Configuration Register
         { 32'h2200_0000 },    // System Control
@@ -46,8 +32,21 @@ module wb_intercon #(
         { 32'h2000_0000 },    // UART 
         { 32'h1000_0000 },    // Flash 
         { 32'h0000_0000 }     // RAM
-    };
-    
+    }
+) (
+    // Master Interface
+    input [AW-1:0] wbm_adr_i,
+    input wbm_stb_i,
+
+    output reg [DW-1:0] wbm_dat_o,
+    output wbm_ack_o,
+
+    // Slave Interface
+    input [NS*DW-1:0] wbs_dat_i,
+    input [NS-1:0] wbs_ack_i,
+    output [NS-1:0] wbs_stb_o
+);
+   
     wire [NS-1: 0] slave_sel;
 
     // Address decoder
@@ -71,4 +70,3 @@ module wb_intercon #(
     end
  
 endmodule
-`default_nettype wire
diff --git a/verilog/stubs/sky130_fd_io__top_xres4v2.v b/verilog/stubs/sky130_fd_io__top_xres4v2.v
index 3fa6736a..693e6cd5 100644
--- a/verilog/stubs/sky130_fd_io__top_xres4v2.v
+++ b/verilog/stubs/sky130_fd_io__top_xres4v2.v
@@ -1,4 +1,3 @@
-`default_nettype none
 /*
  * SPDX-FileCopyrightText: 2020 The SkyWater PDK Authors
  *