From cc6e3e6891349fb35328aea0b77cf06037bed7e7 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 26 Nov 2023 04:17:46 -0800 Subject: [PATCH 1/4] Add cocotb tests for GF180 --- verilog/dv/cocotb/.gitignore | 4 + verilog/dv/cocotb/README.md | 43 +++++++++++ verilog/dv/cocotb/cocotb_tests.py | 7 ++ verilog/dv/cocotb/design_info.yaml | 9 +++ verilog/dv/cocotb/gpio_test/gpio_test.c | 30 ++++++++ verilog/dv/cocotb/gpio_test/gpio_test.py | 36 +++++++++ verilog/dv/cocotb/hello_world/hello_world.c | 19 +++++ verilog/dv/cocotb/hello_world/hello_world.py | 25 +++++++ .../dv/cocotb/hello_world/hello_world.yaml | 27 +++++++ .../hello_world_uart/hello_world_uart.c | 28 +++++++ .../hello_world_uart/hello_world_uart.py | 38 ++++++++++ .../hello_world_uart/hello_world_uart.yaml | 24 ++++++ verilog/dv/cocotb/user_proj_tests/README.md | 26 +++++++ .../user_proj_tests/counter_la/counter_la.c | 44 +++++++++++ .../user_proj_tests/counter_la/counter_la.py | 53 +++++++++++++ .../counter_la/counter_la.yaml | 21 ++++++ .../counter_la_clk/counter_la_clk.c | 75 +++++++++++++++++++ .../counter_la_clk/counter_la_clk.py | 47 ++++++++++++ .../counter_la_clk/counter_la_clk.yaml | 21 ++++++ .../counter_la_reset/counter_la_reset.c | 67 +++++++++++++++++ .../counter_la_reset/counter_la_reset.py | 58 ++++++++++++++ .../counter_la_reset/counter_la_reset.yaml | 21 ++++++ .../user_proj_tests/counter_wb/counter_wb.c | 39 ++++++++++ .../user_proj_tests/counter_wb/counter_wb.py | 63 ++++++++++++++++ .../counter_wb/counter_wb.yaml | 21 ++++++ .../user_proj_tests/user_proj_tests.yaml | 24 ++++++ .../user_proj_tests/user_proj_tests_gl.yaml | 8 ++ verilog/dv/setup-cocotb.py | 50 +++++++++++++ 28 files changed, 928 insertions(+) create mode 100644 verilog/dv/cocotb/.gitignore create mode 100644 verilog/dv/cocotb/README.md create mode 100644 verilog/dv/cocotb/cocotb_tests.py create mode 100644 verilog/dv/cocotb/design_info.yaml create mode 100644 verilog/dv/cocotb/gpio_test/gpio_test.c create mode 100644 verilog/dv/cocotb/gpio_test/gpio_test.py create mode 100644 verilog/dv/cocotb/hello_world/hello_world.c create mode 100644 verilog/dv/cocotb/hello_world/hello_world.py create mode 100644 verilog/dv/cocotb/hello_world/hello_world.yaml create mode 100644 verilog/dv/cocotb/hello_world_uart/hello_world_uart.c create mode 100644 verilog/dv/cocotb/hello_world_uart/hello_world_uart.py create mode 100644 verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml create mode 100644 verilog/dv/cocotb/user_proj_tests/README.md create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py create mode 100644 verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml create mode 100644 verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml create mode 100644 verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml create mode 100644 verilog/dv/setup-cocotb.py diff --git a/verilog/dv/cocotb/.gitignore b/verilog/dv/cocotb/.gitignore new file mode 100644 index 000000000..fe104e164 --- /dev/null +++ b/verilog/dv/cocotb/.gitignore @@ -0,0 +1,4 @@ +sim/ +*.log +*.vcd +*.pyc \ No newline at end of file diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md new file mode 100644 index 000000000..340e85d57 --- /dev/null +++ b/verilog/dv/cocotb/README.md @@ -0,0 +1,43 @@ +Overview +======== +This directory contain tests to verify the example user project 16 bit counter and 2 other simple tests as examples. + +directory hierarchy +===================== + +# counter_tests + +contain tests for 16 bit counter for more info refer to [counter_tests](counter_tests/README.md) + + # hello_world + + Example test with empty firmware that only power and reset caravel the print "Hello World" + + # hello_world_uart + + Example test That uses the firmware to send "Hello World" using UART TX + +# cocotb_tests.py + +Module that should import all the tests used to be seen for cocotb as a test + + +Run tests +=========== +# run hello_world_uart + ```bash + caravel_cocotb -t hello_world_uart -tag hello_world + ``` +# run all counter testlist + ```bash + caravel_cocotb -tl counter_tests/counter_tests.yaml -tag counter_tests + ``` +# run from different directory + ```bash + caravel_cocotb -t hello_world_uart -tag hello_world -design_info + ``` +# run with changing the results directory + ```bash + caravel_cocotb -t hello_world_uart -tag hello_world -sim + ``` + diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py new file mode 100644 index 000000000..bb220ecb6 --- /dev/null +++ b/verilog/dv/cocotb/cocotb_tests.py @@ -0,0 +1,7 @@ +from hello_world.hello_world import hello_world +from hello_world_uart.hello_world_uart import hello_world_uart +from user_proj_tests.counter_wb.counter_wb import counter_wb +from user_proj_tests.counter_la.counter_la import counter_la +from user_proj_tests.counter_la_reset.counter_la_reset import counter_la_reset +from user_proj_tests.counter_la_clk.counter_la_clk import counter_la_clk +from gpio_test.gpio_test import gpio_test diff --git a/verilog/dv/cocotb/design_info.yaml b/verilog/dv/cocotb/design_info.yaml new file mode 100644 index 000000000..aacfd903b --- /dev/null +++ b/verilog/dv/cocotb/design_info.yaml @@ -0,0 +1,9 @@ +CARAVEL_ROOT: /usr/caravel_user_project/caravel +MCW_ROOT: /usr/caravel_user_project/mgmt_core_wrapper +PDK: sky130A +PDK_ROOT: /usr/pdk +USER_PROJECT_ROOT: /usr/caravel_user_project +caravan: false +clk: 25 +emailto: +- null diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.c b/verilog/dv/cocotb/gpio_test/gpio_test.c new file mode 100644 index 000000000..530c45ee2 --- /dev/null +++ b/verilog/dv/cocotb/gpio_test/gpio_test.c @@ -0,0 +1,30 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include // include required APIs +void main(){ + // Enable managment gpio as output to use as indicator for finishing configuration + ManagmentGpio_outputEnable(); + ManagmentGpio_write(0); + enableHkSpi(0); // disable housekeeping spi + //GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUT); + GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_loadConfigs(); + GPIOs_writeLow(0x8F); + ManagmentGpio_write(1); // configuration finished + + + return; +} diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.py b/verilog/dv/cocotb/gpio_test/gpio_test.py new file mode 100644 index 000000000..17323fbe2 --- /dev/null +++ b/verilog/dv/cocotb/gpio_test/gpio_test.py @@ -0,0 +1,36 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +from caravel_cocotb.caravel_interfaces import * # import python APIs +import cocotb + +@cocotb.test() # cocotb test marker +@report_test # wrapper for configure test reporting files +async def gpio_test(dut): + caravelEnv = await test_configure(dut) #configure, start up and reset caravel + #await caravelEnv.release_csb() + await caravelEnv.wait_mgmt_gpio(1) + gpios_value_str = caravelEnv.monitor_gpio(37, 0).binstr + cocotb.log.info (f"All gpios '{gpios_value_str}'") + gpio_value_int = caravelEnv.monitor_gpio(37, 0).integer + #expected_gpio_value = 0xF8 + expected_gpio_value = 0x8F + if (gpio_value_int == expected_gpio_value): + cocotb.log.info (f"[TEST] Pass the gpio value is '{hex(gpio_value_int)}'") + else: + cocotb.log.error (f"[TEST] Fail the gpio value is :'{hex(gpio_value_int)}' expected {hex(expected_gpio_value)}") + + diff --git a/verilog/dv/cocotb/hello_world/hello_world.c b/verilog/dv/cocotb/hello_world/hello_world.c new file mode 100644 index 000000000..f5825dd2f --- /dev/null +++ b/verilog/dv/cocotb/hello_world/hello_world.c @@ -0,0 +1,19 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +void main(){ + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world/hello_world.py b/verilog/dv/cocotb/hello_world/hello_world.py new file mode 100644 index 000000000..6ea67c75d --- /dev/null +++ b/verilog/dv/cocotb/hello_world/hello_world.py @@ -0,0 +1,25 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb + +@cocotb.test() +@report_test +async def hello_world(dut): + caravelEnv = await test_configure(dut,timeout_cycles=9373) + cocotb.log.info("Hello World") \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world/hello_world.yaml b/verilog/dv/cocotb/hello_world/hello_world.yaml new file mode 100644 index 000000000..f3a98149d --- /dev/null +++ b/verilog/dv/cocotb/hello_world/hello_world.yaml @@ -0,0 +1,27 @@ +--- +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +# Yalm file contain general design information that would mostly need to be updated in the first run only +# example +## tests: [debug,clock_redirect] +## sim: [RTL,RTL] +Tests: + - {name: hello_world, sim: RTL} + + + + diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c new file mode 100644 index 000000000..6acd8a742 --- /dev/null +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c @@ -0,0 +1,28 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include + +void main(){ + ManagmentGpio_write(0); + ManagmentGpio_outputEnable(); + GPIOs_configure(6,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_loadConfigs(); + UART_enableTX(1); + ManagmentGpio_write(1); // configuration finished + + print("Hello World\n"); + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py new file mode 100644 index 000000000..4ab26621f --- /dev/null +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py @@ -0,0 +1,38 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb +from caravel_cocotb.caravel_interfaces import UART + +@cocotb.test() +@report_test +async def hello_world_uart(dut): + caravelEnv = await test_configure(dut,timeout_cycles=3346140) + + cocotb.log.info(f"[TEST] Start uart test") + expected_msg = "Hello World" + uart = UART(caravelEnv) + # wait for start of sending + await caravelEnv.wait_mgmt_gpio(1) + # read the msg sent + msg = await uart.get_line() + if msg in expected_msg : + cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{msg}'") + else: + cocotb.log.error (f"[TEST] recieved wrong msg from uart msg recieved:'{msg}' expected '{expected_msg}'") \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml new file mode 100644 index 000000000..b231d9b40 --- /dev/null +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml @@ -0,0 +1,24 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + + +# Yalm file contain general design information that would mostly need to be updated in the first run only + +Tests: + - {name: hello_world_uart, sim: RTL} + + diff --git a/verilog/dv/cocotb/user_proj_tests/README.md b/verilog/dv/cocotb/user_proj_tests/README.md new file mode 100644 index 000000000..94f7006cd --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/README.md @@ -0,0 +1,26 @@ + +Tests hierarchy +===================== + +# counter_wb + +Test that overwrite the counter value using wishbone interface + + # counter_la + +Test that overwrite the counter value using logic analyzer interface + + # counter_la_clk + +Counter can work by 2 different clocks wishbone clock or clock provided through logic analyzers. +By default the wishbone clock is the used one. This test uses the logic analyzers clock + + + # counter_la_reset + +Counter reset also provided through wishbone or logic analyzers. this test uses the logic analyzers reset + +# counter_tests.yaml + +Testlist contain all counter tests + diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c new file mode 100644 index 000000000..36bcd4cb7 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c @@ -0,0 +1,44 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include + +void main(){ + // Enable managment gpio as output to use as indicator for finishing configuration + ManagmentGpio_outputEnable(); + ManagmentGpio_write(0); + enableHkSpi(0); // disable housekeeping spi + // configure all gpios as user out then chenge gpios from 32 to 37 before loading this configurations + GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(32,GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(33,GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(34,GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(35,GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(36,GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(37,GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_loadConfigs(); // load the configuration + ManagmentGpio_write(1); // configuration finished + // configure la [63:32] as output from cpu + #ifdef GF + LogicAnalyzer_write(1,7<<14); + LogicAnalyzer_outputEnable(1,0xC0000000); + #else + LogicAnalyzer_write(1,7<<16); + LogicAnalyzer_outputEnable(1,0); + #endif // GF + ManagmentGpio_write(0); // configuration finished + LogicAnalyzer_outputEnable(1,0xFFFFFFFF); + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py new file mode 100644 index 000000000..b4424ae9f --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py @@ -0,0 +1,53 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb + +@cocotb.test() +@report_test +async def counter_la(dut): + caravelEnv = await test_configure(dut, timeout_cycles=59844) + + cocotb.log.info(f"[TEST] Start counter_la test") + # wait for start of sending + await caravelEnv.release_csb() + await caravelEnv.wait_mgmt_gpio(1) + cocotb.log.info(f"[TEST] finish configuration") + overwrite_val = 7 # value will be written to the counter by la + # expect value bigger than 7 + await caravelEnv.wait_mgmt_gpio(0) # wait until writing 7 through la + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + counter = overwrite_val + + if received_val != counter : + cocotb.log.fatal(f"LA writing is incorrect: {overwrite_val} receieved: {received_val}") + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + + # wait until the LA writing is disabled + while (received_val == counter): + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + + counter = received_val + for i in range(100): + if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) : + cocotb.log.error(f"counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }") + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + counter +=1 + diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml new file mode 100644 index 000000000..c0f1fdeb8 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 +# Yalm file contain general design information that would mostly need to be updated in the first run only + +Tests: + - {name: counter_la, sim: RTL} + + diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c new file mode 100644 index 000000000..6f29809f1 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c @@ -0,0 +1,75 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include + +void main(){ + // Enable managment gpio as output to use as indicator for finishing configuration + ManagmentGpio_outputEnable(); + ManagmentGpio_write(0); + enableHkSpi(0); // disable housekeeping spi + // configure all gpios as user out then chenge gpios from 32 to 37 before loading this configurations + GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(32,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(33,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(34,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(35,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(36,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(37,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_loadConfigs(); // load the configuration + // configure la 64 (clk enable by la) as output from cpu + // writing 1 in bit 64(first bit in reg 2) to reset + #ifdef GF + LogicAnalyzer_write(1,0); + LogicAnalyzer_outputEnable(1, 0x3FFFFFFF); + // reset counter + // reset 1 + LogicAnalyzer_write(1,0xC0000000); // clk pose edge + LogicAnalyzer_write(1,0x80000000);// clk neg edge + // reset 0 + LogicAnalyzer_write(1,0x40000000); // clk pose edge + LogicAnalyzer_write(1,0x00000000);// clk neg edge + + ManagmentGpio_write(1); // configuration finished + + for (int i = 0; i < 7; i++){ + LogicAnalyzer_write(1,0x40000000); // clk pose edge + ManagmentGpio_write(0); + LogicAnalyzer_write(1,0x00000000);// clk neg edge + ManagmentGpio_write(1); + } + #else + LogicAnalyzer_write(2,0); + // LogicAnalyzer_inputEnable(2,0x1); + LogicAnalyzer_outputEnable(2,0xFFFFFFFC); + // reset counter + // reset 1 + LogicAnalyzer_write(2,3); // clk pose edge + LogicAnalyzer_write(2,2);// clk pose edge + // reset 0 + LogicAnalyzer_write(2,1); // clk pose edge + LogicAnalyzer_write(2,0);// clk pose edge + + ManagmentGpio_write(1); // configuration finished + + for (int i = 0; i < 7; i++){ + LogicAnalyzer_write(2,1); // clk pose edge + ManagmentGpio_write(0); + LogicAnalyzer_write(2,0);// clk pose edge + ManagmentGpio_write(1); + } + #endif // GF + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py new file mode 100644 index 000000000..93f70df61 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py @@ -0,0 +1,47 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb + +@cocotb.test() +@report_test +async def counter_la_clk(dut): + caravelEnv = await test_configure(dut,timeout_cycles=61011) + + cocotb.log.info(f"[TEST] Start counter_wb test") + # wait for start of sending + await caravelEnv.release_csb() + await caravelEnv.wait_mgmt_gpio(1) + cocotb.log.info(f"[TEST] finish configuration") + overwrite_val = 0 # because of the reset + # expect value bigger than 7 + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + counter = received_val + + for i in range(5): + if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) : + cocotb.log.error(f"counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }") + await wait_la_clock_cycle(caravelEnv) + counter +=1 + + +async def wait_la_clock_cycle(caravelEnv): + # clock is synced with mgmt_gpio + await caravelEnv.wait_mgmt_gpio(0) + await caravelEnv.wait_mgmt_gpio(1) \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml new file mode 100644 index 000000000..758e34690 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +# Yalm file contain general design information that would mostly need to be updated in the first run only +Tests: + - {name: counter_la_clk, sim: RTL} + + diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c new file mode 100644 index 000000000..6b9b3bf8f --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c @@ -0,0 +1,67 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include + +void main(){ + // Enable managment gpio as output to use as indicator for finishing configuration + ManagmentGpio_outputEnable(); + ManagmentGpio_write(0); + enableHkSpi(0); // disable housekeeping spi + // configure all gpios as user out then chenge gpios from 32 to 37 before loading this configurations + GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED); + GPIOs_configure(32,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(33,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(34,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(35,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(36,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_configure(37,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_loadConfigs(); // load the configuration + // reset counter + #ifdef GF + LogicAnalyzer_outputEnable(1,0x3FFFFFFF); + LogicAnalyzer_write(1,0x80000000); + LogicAnalyzer_write(1,0); + #else + LogicAnalyzer_outputEnable(2,0xFFFFFFFD); + LogicAnalyzer_write(2,2); + LogicAnalyzer_write(2,0); + #endif // GF + + ManagmentGpio_write(1); // configuration finished + // configure la 65 (reset enable by la) as output from cpu + // writing 1 in bit 65(second bit in reg 2) to reset + // asset reset + #ifdef GF + LogicAnalyzer_write(1,0x80000000); + LogicAnalyzer_inputEnable(1,0xC0000000); + LogicAnalyzer_outputEnable(1,0x3FFFFFFF); + #else + LogicAnalyzer_write(2,2); + LogicAnalyzer_inputEnable(2,0x2); + LogicAnalyzer_outputEnable(2,0xFFFFFFFD); + #endif // GF + + // deassert reset + #ifdef GF + LogicAnalyzer_inputEnable(1,0); + LogicAnalyzer_outputEnable(1,0xFFFFFFFF); + #else + LogicAnalyzer_inputEnable(2,0); + LogicAnalyzer_outputEnable(2,0xFFFFFFFF); + #endif // GF + + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py new file mode 100644 index 000000000..cfe8a5838 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py @@ -0,0 +1,58 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb + +@cocotb.test() +@report_test +async def counter_la_reset(dut): + caravelEnv = await test_configure(dut,timeout_cycles=1346140) + + cocotb.log.info(f"[TEST] Start counter_wb test") + # wait for start of sending + await caravelEnv.release_csb() + await caravelEnv.wait_mgmt_gpio(1) + cocotb.log.info(f"[TEST] finish configuration") + overwrite_val = 0 # because of the reset + # expect value bigger than 7 + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + counter = received_val + if received_val <= overwrite_val : + cocotb.log.error(f"counter started late and value captured after configuration is smaller than overwrite value: {overwrite_val} receieved: {received_val}") + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + + while True: # wait until reset asserted + if await get_reset_val(caravelEnv) == 1: + cocotb.log.info(f"[TEST] Reset asserted by la") + break + while True: # wait until reset deasserted + if await get_reset_val(caravelEnv) == 0: + cocotb.log.info(f"[TEST] Reset deasserted by la") + break + counter =0 + + for i in range(100): + if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) : + cocotb.log.error(f"counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }") + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + counter +=1 + +async def get_reset_val(caravelEnv): + """ get the counter reset value""" + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + return caravelEnv.user_hdl.mprj.counter.reset.value diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml new file mode 100644 index 000000000..38110352b --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +# Yalm file contain general design information that would mostly need to be updated in the first run only +Tests: + - {name: counter_la_reset, sim: RTL} + + diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c new file mode 100644 index 000000000..c9f021c6b --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c @@ -0,0 +1,39 @@ +// SPDX-FileCopyrightText: 2023 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include + +void main(){ + // Enable managment gpio as output to use as indicator for finishing configuration + ManagmentGpio_outputEnable(); + ManagmentGpio_write(0); + enableHkSpi(0); // disable housekeeping spi + // configure all gpios as user out then chenge gpios from 32 to 37 before loading this configurations + GPIOs_configureAll(GPIO_MODE_USER_STD_OUT_MONITORED); + + GPIOs_loadConfigs(); // load the configuration + User_enableIF(); // this necessary when reading or writing between wishbone and user project if interface isn't enabled no ack would be recieve and the command will be stuck + // user la reset and wb clk + LogicAnalyzer_outputEnable(2,1); + // reset counter + LogicAnalyzer_write(2,2); + LogicAnalyzer_write(2,0); + ManagmentGpio_write(1); // configuration finished + // writing to any address inside user project address space would reload the counter value + USER_writeWord(0x7,0x88); + ManagmentGpio_write(0); // start counting from 0 + + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py new file mode 100644 index 000000000..f4539fe2c --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py @@ -0,0 +1,63 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb + +@cocotb.test() +@report_test +async def counter_wb(dut): + caravelEnv = await test_configure(dut,timeout_cycles=22620) + + cocotb.log.info(f"[TEST] Start counter_wb test") + # wait for start of sending + await caravelEnv.release_csb() + await caravelEnv.wait_mgmt_gpio(1) + cocotb.log.info(f"[TEST] finish configuration") + overwrite_val = 7 # value will be written to the counter by wishbone + # expect value bigger than 7 + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + counter = received_val + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + + while True: # wait until the value 1 start counting after the initial + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + if counter == 0xFFFF: # rollover + counter = 0 + else: + counter +=1 + if received_val != counter: + if received_val == overwrite_val: + counter = received_val +1 + cocotb.log.info(f"Counter value has been overwritten by wishbone to be {received_val}") + while True: #wait until the wishbone writing finished and the counter start running again + received_val = int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) + if counter == received_val: + break + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + cocotb.log.info(f"Counter value has been overwritten by wishbone to be {received_val}") + break + else: + cocotb.log.error(f"Counter has wrong value before overwrite happened expected: {counter} received: {received_val}") + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + + for i in range(100): + if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) : + cocotb.log.error(f"Counter have wrong value expected = {counter} recieved = {int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) }") + await cocotb.triggers.ClockCycles(caravelEnv.clk,1) + counter +=1 \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml new file mode 100644 index 000000000..8436c3218 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +# Yalm file contain general design information that would mostly need to be updated in the first run only +Tests: + - {name: counter_wb, sim: RTL} + + diff --git a/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml new file mode 100644 index 000000000..0d3a7fd5c --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml @@ -0,0 +1,24 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + +# yaml file contain general design information that would mostly need to be updated in the first run only +includes: + - counter_la/counter_la.yaml + - counter_wb/counter_wb.yaml + - counter_la_reset/counter_la_reset.yaml + - counter_la_clk/counter_la_clk.yaml + + diff --git a/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml new file mode 100644 index 000000000..4019756d0 --- /dev/null +++ b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml @@ -0,0 +1,8 @@ +--- +# yaml file contain general design information that would mostly need to be updated in the first run only +Tests: + - {name: counter_wb, sim: GL} + - {name: counter_la, sim: GL} + - {name: counter_la_reset, sim: GL} + - {name: counter_la_clk, sim: GL} + diff --git a/verilog/dv/setup-cocotb.py b/verilog/dv/setup-cocotb.py new file mode 100644 index 000000000..4471ee640 --- /dev/null +++ b/verilog/dv/setup-cocotb.py @@ -0,0 +1,50 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 +import click +import yaml + + +@click.command() +@click.argument('caravel_root', type=click.Path(exists=True)) +@click.argument('mcw_root', type=click.Path(exists=True)) +@click.argument('pdk_root', type=click.Path(exists=True)) +@click.argument('pdk') +@click.argument('user_project_root', type=click.Path(exists=True)) +def update_design_info(caravel_root, mcw_root, pdk_root, pdk, user_project_root): + data = { + 'CARAVEL_ROOT': caravel_root, + 'MCW_ROOT': mcw_root, + 'USER_PROJECT_ROOT': user_project_root, + 'PDK_ROOT': pdk_root, + 'PDK': pdk, + 'clk': 25, + 'caravan': False, + 'emailto': [None] + } + + with open(f'{user_project_root}/verilog/dv/cocotb/design_info.yaml', 'w') as file: + yaml.dump(data, file) + + +if __name__ == "__main__": + update_design_info() + +# paths = EnvironmentPaths("/home/rady/caravel/caravel_orginal/caravel/", +# "/home/rady/caravel/caravel_orginal/caravel_mgmt_soc_litex/", +# "/home/rady/caravel/files4vcs/pdk","sky130A", +# "/home/rady/caravel/swift/caravel_user_project/") + +# WriteDesignInfo("/home/Marwan/caravel/swift/caravel-dynamic-sims/cocotb/",paths,Emailto=["mostafa.rady@efabless.com"]) From f16a6c6bce690befdc3af97aadcccebb251b59c8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 26 Nov 2023 04:39:06 -0800 Subject: [PATCH 2/4] change macro GF to GF180 --- .../cocotb/user_proj_tests/counter_la/counter_la.c | 4 ++-- .../user_proj_tests/counter_la_clk/counter_la_clk.c | 4 ++-- .../counter_la_reset/counter_la_reset.c | 12 ++++++------ 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c index 36bcd4cb7..9293b6b76 100644 --- a/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c +++ b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c @@ -31,13 +31,13 @@ void main(){ GPIOs_loadConfigs(); // load the configuration ManagmentGpio_write(1); // configuration finished // configure la [63:32] as output from cpu - #ifdef GF + #ifdef GF180 LogicAnalyzer_write(1,7<<14); LogicAnalyzer_outputEnable(1,0xC0000000); #else LogicAnalyzer_write(1,7<<16); LogicAnalyzer_outputEnable(1,0); - #endif // GF + #endif // GF180 ManagmentGpio_write(0); // configuration finished LogicAnalyzer_outputEnable(1,0xFFFFFFFF); return; diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c index 6f29809f1..a89a49b4a 100644 --- a/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c @@ -31,7 +31,7 @@ void main(){ GPIOs_loadConfigs(); // load the configuration // configure la 64 (clk enable by la) as output from cpu // writing 1 in bit 64(first bit in reg 2) to reset - #ifdef GF + #ifdef GF180 LogicAnalyzer_write(1,0); LogicAnalyzer_outputEnable(1, 0x3FFFFFFF); // reset counter @@ -70,6 +70,6 @@ void main(){ LogicAnalyzer_write(2,0);// clk pose edge ManagmentGpio_write(1); } - #endif // GF + #endif // GF180 return; } \ No newline at end of file diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c index 6b9b3bf8f..abf7b241a 100644 --- a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c @@ -30,7 +30,7 @@ void main(){ GPIOs_configure(37,GPIO_MODE_MGMT_STD_OUTPUT); GPIOs_loadConfigs(); // load the configuration // reset counter - #ifdef GF + #ifdef GF180 LogicAnalyzer_outputEnable(1,0x3FFFFFFF); LogicAnalyzer_write(1,0x80000000); LogicAnalyzer_write(1,0); @@ -38,13 +38,13 @@ void main(){ LogicAnalyzer_outputEnable(2,0xFFFFFFFD); LogicAnalyzer_write(2,2); LogicAnalyzer_write(2,0); - #endif // GF + #endif // GF180 ManagmentGpio_write(1); // configuration finished // configure la 65 (reset enable by la) as output from cpu // writing 1 in bit 65(second bit in reg 2) to reset // asset reset - #ifdef GF + #ifdef GF180 LogicAnalyzer_write(1,0x80000000); LogicAnalyzer_inputEnable(1,0xC0000000); LogicAnalyzer_outputEnable(1,0x3FFFFFFF); @@ -52,16 +52,16 @@ void main(){ LogicAnalyzer_write(2,2); LogicAnalyzer_inputEnable(2,0x2); LogicAnalyzer_outputEnable(2,0xFFFFFFFD); - #endif // GF + #endif // GF180 // deassert reset - #ifdef GF + #ifdef GF180 LogicAnalyzer_inputEnable(1,0); LogicAnalyzer_outputEnable(1,0xFFFFFFFF); #else LogicAnalyzer_inputEnable(2,0); LogicAnalyzer_outputEnable(2,0xFFFFFFFF); - #endif // GF + #endif // GF180 return; } \ No newline at end of file From 55225ac1010450dda64ea18aeb173ad89cda58f1 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 26 Nov 2023 06:07:44 -0800 Subject: [PATCH 3/4] fix counter_wb and counter_la_reset tests for iverilog --- .../counter_la_reset/counter_la_reset.c | 2 +- .../counter_la_reset/counter_la_reset.py | 2 +- .../dv/cocotb/user_proj_tests/counter_wb/counter_wb.c | 11 +++++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c index abf7b241a..ce8e275ad 100644 --- a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c @@ -31,7 +31,7 @@ void main(){ GPIOs_loadConfigs(); // load the configuration // reset counter #ifdef GF180 - LogicAnalyzer_outputEnable(1,0x3FFFFFFF); + LogicAnalyzer_outputEnable(1,0x7FFFFFFF); LogicAnalyzer_write(1,0x80000000); LogicAnalyzer_write(1,0); #else diff --git a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py index cfe8a5838..98322d4c1 100644 --- a/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py @@ -44,7 +44,7 @@ async def counter_la_reset(dut): if await get_reset_val(caravelEnv) == 0: cocotb.log.info(f"[TEST] Reset deasserted by la") break - counter =0 + counter =int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) for i in range(100): if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) : diff --git a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c index c9f021c6b..2eeefaa67 100644 --- a/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c +++ b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c @@ -25,11 +25,18 @@ void main(){ GPIOs_loadConfigs(); // load the configuration User_enableIF(); // this necessary when reading or writing between wishbone and user project if interface isn't enabled no ack would be recieve and the command will be stuck - // user la reset and wb clk - LogicAnalyzer_outputEnable(2,1); + // user la reset and wb // reset counter + #ifdef GF180 + LogicAnalyzer_outputEnable(1, 0x7FFFFFFF); + LogicAnalyzer_write(1,0x80000000); + LogicAnalyzer_write(1,0x0); + #else + LogicAnalyzer_outputEnable(2,1); LogicAnalyzer_write(2,2); LogicAnalyzer_write(2,0); + #endif // GF180 + ManagmentGpio_write(1); // configuration finished // writing to any address inside user project address space would reload the counter value USER_writeWord(0x7,0x88); From 1d0469ba9daa2da8b4cfa51e2920ea6f9b642c67 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 26 Nov 2023 06:29:46 -0800 Subject: [PATCH 4/4] remove reset tests from GL --- verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml index 4019756d0..b41405977 100644 --- a/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml +++ b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml @@ -3,6 +3,6 @@ Tests: - {name: counter_wb, sim: GL} - {name: counter_la, sim: GL} - - {name: counter_la_reset, sim: GL} + # - {name: counter_la_reset, sim: GL} - {name: counter_la_clk, sim: GL}