From 141dcaed6cc930d83a4f95cb51ebc22f51fcc32c Mon Sep 17 00:00:00 2001 From: Dhaval Sharma Date: Mon, 29 Jan 2024 09:31:16 +0530 Subject: [PATCH] UefiCpuPkg: Add cache operations support for Arch proto With CMO operations available for RISC-V, utilize them in CPU Architecture protocol. Signed-off-by: Dhaval Sharma Cc: Gerd Hoffmann Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Ray Ni Cc: Sunil VL Cc: Andrei Warkentin Reviewed-by: Sunil V L --- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + 2 files changed, 15 insertions(+) diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c index 2af3b6223450..c6bae100a9e4 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -90,6 +90,20 @@ CpuFlushCpuDataCache ( IN EFI_CPU_FLUSH_TYPE FlushType ) { + switch (FlushType) { + case EfiCpuFlushTypeWriteBack: + WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + case EfiCpuFlushTypeInvalidate: + InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + case EfiCpuFlushTypeWriteBackInvalidate: + WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + default: + return EFI_INVALID_PARAMETER; + } + return EFI_SUCCESS; } diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h index 68e6d038b66e..d4d67778eb1c 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include