Gate

A (logical) gate is an electronic component comprising multiple in- and outputs that implements one or more Boolean fucntion(s). It is connected to a number of nets via its pins and can thus be used in larger circuits to implement complex logic operations. Such a circuit on gate-level is usually referred to as a netlist.

Gate Information and Management

Similar to all other netlist components in HAL, a gate comprises basic information such as an ID, a name, and a gate type that can be read and sometimes written using dedicated commands such as get_id, get_name, set_name, and get_type. A gate can be created by using create_gate on the netlist while specifying its gate type and name. Furthermore, a gate can return the module and the grouping is is assigned to using get_module and get_grouping.

gt = GateType("example_type")                 # create an empty gate type
g = netlist.create_gate(gt, "example_gate")   # create a new gate
id = g.get_id()                               # get the gate's ID
name = g.get_name()                           # get the gate's name
grouping = g.get_grouping()                   # get the gate's grouping

Additionally, a gate can be retrieved from the netlist by ID using get_gate_by_id and may be deleted using delete_gate. Deleting a gate may result in dangling wires.

g = netlist.get_gate_by_id(3)   # get the gate with ID 3 from the netlist
netlist.delete_gate(g)          # delete the gate

Gate Connections

Each gate offers functions has multiple input and output pins that are potentially connected to a variety of nets. The user can retrieve the names of the in- and output pins by using get_input_pins or get_output_pins respectively. Furthermore, the net connected to such a pin can be retrieved using get_fan_in_net and get_fan_out_net. If required, even the whole endpoint of a pin is accessible via get_fan_in_endpoint and get_fan_out_endpoint. A list of all connected nets or endpoints is also available via get_fan_in_nets', 'get_fan_out_nets, get_fan_in_endpoints and get_fan_out_endpoints.

out_pins = g.get_output_pins()                 # get all output pins
out_net = g.get_fan_out_net(out_pins[0])       # get net connected to first output pin
out_ep = g.get_fan_out_endpoint(out_pins[0])   # get endpoint of first output pin
in_eps = g.get_fan_in_endpoints()              # get all endpoints at input pins

Easy access to the predecessors and successors of a gate is provided by the functions get_predecessors, get_unique_predecessors, get_successors, and get_unique_successors. The functions retrieving unique predecessors or successors return a list of gates while all remaining function return a list of endpoints of the predecessor or successor gate.

pred = g.get_predecessors()               # get all predecessor endpoints
unique_succ = g.get_unique_successors()   # get all unique successor gates

Boolean Functions

The function(s) implemented by a gate are defined by their Boolean function(s). Usually, these Boolean functions are specified by the gate type and not the gate itself. However, for FPGA netlists containing LUTs it is not sufficient to store the Boolean function solely with the gate type since different gates of the same LUT gate type may implement different functions. Therefore, the functions get_boolean_function, get_boolean_functions and 'add_boolean_function` may be used to add and retrieve Boolean functions associated with a gate and its gate type. Hence we recommend always retrieving Boolean functions from individual gates and not gate types. For the LUT gate type, Boolean functions are automatically automatically created from their initialization string and cached until this string changes.

func = gate.get_boolean_function("O")      # get Boolean function with name "O"
all_funcs = gate.get_boolean_functions()   # get all Boolean functions associated with gate and its type

Special Gates

Each gate library is required to provide dedicated gate types for Vcc and GND. Instances of these gate type are connected to constant 1 or 0 signals and need to be marked as such by using mark_vcc_gate and mark_gnd_gate. This process can be reversed using unmark_vcc_gate and unmark_gnd_gate. Whether a gate is a Vcc or GND gate can be determined using is_vcc_gate and is_gnd_gate. Marking gates as Vcc or GND gates is usually taken care of by the netlist parser and should not be done by the user.

gate.mark_vcc_gate()        # mark a gate as a Vcc gate
print(gate.is_vcc_gate())   # prints True
gate.unmark_vcc_gate()      # unmark the Vcc gate

By providing the gate as input, all these functions can also be executed on the netlist itself. In addition, calling get_vcc_gates or get_gnd_gates on the netlist returns a list of all Vcc or GND gates respectively.

gate = netlist.get_gate_by_id(3)   # get gate with ID 3
netlist.mark_vcc_gate(gate)        # mark gate as Vcc gate
netlist.is_vcc_gate(gate)          # returns True
netlist.unmark_vcc_gate(gate)      # unmark gate
netlist.get_gnd_gates()            # return all GND gates