diff --git a/esp32s2/src/copy_dma.rs b/esp32s2/src/copy_dma.rs new file mode 100644 index 000000000..281a2e13c --- /dev/null +++ b/esp32s2/src/copy_dma.rs @@ -0,0 +1,180 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + out_link: OUT_LINK, + in_link: IN_LINK, + out_eof_des_addr: OUT_EOF_DES_ADDR, + in_eof_des_addr: IN_EOF_DES_ADDR, + out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR, + inlink_dscr: INLINK_DSCR, + inlink_dscr_bf0: INLINK_DSCR_BF0, + _reserved11: [u8; 0x04], + outlink_dscr: OUTLINK_DSCR, + outlink_dscr_bf0: OUTLINK_DSCR_BF0, + _reserved13: [u8; 0x04], + conf: CONF, + in_st: IN_ST, + out_st: OUT_ST, + _reserved16: [u8; 0xb4], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x04 - Masked interrupt status"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x08 - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x0c - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x10 - Link descriptor address and control"] + #[inline(always)] + pub const fn out_link(&self) -> &OUT_LINK { + &self.out_link + } + #[doc = "0x14 - Link descriptor address and control"] + #[inline(always)] + pub const fn in_link(&self) -> &IN_LINK { + &self.in_link + } + #[doc = "0x18 - Transmit descriptor address when EOF occurs"] + #[inline(always)] + pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR { + &self.out_eof_des_addr + } + #[doc = "0x1c - Receive descriptor address when EOF occurs"] + #[inline(always)] + pub const fn in_eof_des_addr(&self) -> &IN_EOF_DES_ADDR { + &self.in_eof_des_addr + } + #[doc = "0x20 - Transmit descriptor address before the last transmit descriptor"] + #[inline(always)] + pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR { + &self.out_eof_bfr_des_addr + } + #[doc = "0x24 - Address of current receive descriptor"] + #[inline(always)] + pub const fn inlink_dscr(&self) -> &INLINK_DSCR { + &self.inlink_dscr + } + #[doc = "0x28 - Address of last receive descriptor"] + #[inline(always)] + pub const fn inlink_dscr_bf0(&self) -> &INLINK_DSCR_BF0 { + &self.inlink_dscr_bf0 + } + #[doc = "0x30 - Address of current transmit descriptor"] + #[inline(always)] + pub const fn outlink_dscr(&self) -> &OUTLINK_DSCR { + &self.outlink_dscr + } + #[doc = "0x34 - Address of last transmit descriptor"] + #[inline(always)] + pub const fn outlink_dscr_bf0(&self) -> &OUTLINK_DSCR_BF0 { + &self.outlink_dscr_bf0 + } + #[doc = "0x3c - Copy DMA configuration register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x40 - Status register of receiving data"] + #[inline(always)] + pub const fn in_st(&self) -> &IN_ST { + &self.in_st + } + #[doc = "0x44 - Status register of transmitting data"] + #[inline(always)] + pub const fn out_st(&self) -> &OUT_ST { + &self.out_st + } + #[doc = "0xfc - Copy DMA version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Masked interrupt status"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "OUT_LINK (rw) register accessor: Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link`] module"] +pub type OUT_LINK = crate::Reg; +#[doc = "Link descriptor address and control"] +pub mod out_link; +#[doc = "IN_LINK (rw) register accessor: Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link`] module"] +pub type IN_LINK = crate::Reg; +#[doc = "Link descriptor address and control"] +pub mod in_link; +#[doc = "CONF (r) register accessor: Copy DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "Copy DMA configuration register"] +pub mod conf; +#[doc = "OUT_EOF_DES_ADDR (r) register accessor: Transmit descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr`] module"] +pub type OUT_EOF_DES_ADDR = crate::Reg; +#[doc = "Transmit descriptor address when EOF occurs"] +pub mod out_eof_des_addr; +#[doc = "IN_EOF_DES_ADDR (r) register accessor: Receive descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`in_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_eof_des_addr`] module"] +pub type IN_EOF_DES_ADDR = crate::Reg; +#[doc = "Receive descriptor address when EOF occurs"] +pub mod in_eof_des_addr; +#[doc = "OUT_EOF_BFR_DES_ADDR (r) register accessor: Transmit descriptor address before the last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr`] module"] +pub type OUT_EOF_BFR_DES_ADDR = crate::Reg; +#[doc = "Transmit descriptor address before the last transmit descriptor"] +pub mod out_eof_bfr_des_addr; +#[doc = "INLINK_DSCR (r) register accessor: Address of current receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`inlink_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inlink_dscr`] module"] +pub type INLINK_DSCR = crate::Reg; +#[doc = "Address of current receive descriptor"] +pub mod inlink_dscr; +#[doc = "INLINK_DSCR_BF0 (r) register accessor: Address of last receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`inlink_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inlink_dscr_bf0`] module"] +pub type INLINK_DSCR_BF0 = crate::Reg; +#[doc = "Address of last receive descriptor"] +pub mod inlink_dscr_bf0; +#[doc = "OUTLINK_DSCR (r) register accessor: Address of current transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`outlink_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outlink_dscr`] module"] +pub type OUTLINK_DSCR = crate::Reg; +#[doc = "Address of current transmit descriptor"] +pub mod outlink_dscr; +#[doc = "OUTLINK_DSCR_BF0 (r) register accessor: Address of last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`outlink_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outlink_dscr_bf0`] module"] +pub type OUTLINK_DSCR_BF0 = crate::Reg; +#[doc = "Address of last transmit descriptor"] +pub mod outlink_dscr_bf0; +#[doc = "IN_ST (r) register accessor: Status register of receiving data\n\nYou can [`read`](crate::Reg::read) this register and get [`in_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_st`] module"] +pub type IN_ST = crate::Reg; +#[doc = "Status register of receiving data"] +pub mod in_st; +#[doc = "OUT_ST (r) register accessor: Status register of transmitting data\n\nYou can [`read`](crate::Reg::read) this register and get [`out_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_st`] module"] +pub type OUT_ST = crate::Reg; +#[doc = "Status register of transmitting data"] +pub mod out_st; +#[doc = "DATE (rw) register accessor: Copy DMA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Copy DMA version control register"] +pub mod date; diff --git a/esp32s2/src/copy_dma/conf.rs b/esp32s2/src/copy_dma/conf.rs new file mode 100644 index 000000000..e899b73a0 --- /dev/null +++ b/esp32s2/src/copy_dma/conf.rs @@ -0,0 +1,129 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Field `IN_RST` reader - Set this bit to reset in DMA FSM."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` reader - Set this bit to reset out DMA FSM."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `CMDFIFO_RST` reader - Set this bit to reset in_cmd FIFO and out_cmd FIFO."] +pub type CMDFIFO_RST_R = crate::BitReader; +#[doc = "Field `FIFO_RST` reader - Set this bit to reset data in RX FIFO."] +pub type FIFO_RST_R = crate::BitReader; +#[doc = "Field `OUT_OWNER` reader - This is used to configure the owner bit in transmit descriptor. This is effective only when you set OUT_AUTO_WRBACK."] +pub type OUT_OWNER_R = crate::BitReader; +#[doc = "Field `IN_OWNER` reader - This is used to configure the owner bit in receive descriptor."] +pub type IN_OWNER_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` reader - This bit is used to write back out descriptor when hardware has already used this descriptor."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `CHECK_OWNER` reader - Set this bit to enable owner bit check in descriptor."] +pub type CHECK_OWNER_R = crate::BitReader; +#[doc = "1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CLK_EN { + #[doc = "0: Support clock only when application writes registers"] + OnWrite = 0, + #[doc = "1: Force clock on for register"] + Force = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLK_EN) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK_EN` reader - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +impl CLK_EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CLK_EN { + match self.bits { + false => CLK_EN::OnWrite, + true => CLK_EN::Force, + } + } + #[doc = "Support clock only when application writes registers"] + #[inline(always)] + pub fn is_on_write(&self) -> bool { + *self == CLK_EN::OnWrite + } + #[doc = "Force clock on for register"] + #[inline(always)] + pub fn is_force(&self) -> bool { + *self == CLK_EN::Force + } +} +impl R { + #[doc = "Bit 0 - Set this bit to reset in DMA FSM."] + #[inline(always)] + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to reset out DMA FSM."] + #[inline(always)] + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to reset in_cmd FIFO and out_cmd FIFO."] + #[inline(always)] + pub fn cmdfifo_rst(&self) -> CMDFIFO_RST_R { + CMDFIFO_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to reset data in RX FIFO."] + #[inline(always)] + pub fn fifo_rst(&self) -> FIFO_RST_R { + FIFO_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is used to configure the owner bit in transmit descriptor. This is effective only when you set OUT_AUTO_WRBACK."] + #[inline(always)] + pub fn out_owner(&self) -> OUT_OWNER_R { + OUT_OWNER_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is used to configure the owner bit in receive descriptor."] + #[inline(always)] + pub fn in_owner(&self) -> IN_OWNER_R { + IN_OWNER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This bit is used to write back out descriptor when hardware has already used this descriptor."] + #[inline(always)] + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable owner bit check in descriptor."] + #[inline(always)] + pub fn check_owner(&self) -> CHECK_OWNER_R { + CHECK_OWNER_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 31 - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("in_rst", &self.in_rst()) + .field("out_rst", &self.out_rst()) + .field("cmdfifo_rst", &self.cmdfifo_rst()) + .field("fifo_rst", &self.fifo_rst()) + .field("out_owner", &self.out_owner()) + .field("in_owner", &self.in_owner()) + .field("out_auto_wrback", &self.out_auto_wrback()) + .field("check_owner", &self.check_owner()) + .field("clk_en", &self.clk_en()) + .finish() + } +} +#[doc = "Copy DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`reset()` method sets CONF to value 0"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/date.rs b/esp32s2/src/copy_dma/date.rs new file mode 100644 index 000000000..1d670f725 --- /dev/null +++ b/esp32s2/src/copy_dma/date.rs @@ -0,0 +1,47 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_DATE` reader - This is the version control register."] +pub type DMA_DATE_R = crate::FieldReader; +#[doc = "Field `DMA_DATE` writer - This is the version control register."] +pub type DMA_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is the version control register."] + #[inline(always)] + pub fn dma_date(&self) -> DMA_DATE_R { + DMA_DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("dma_date", &self.dma_date()) + .finish() + } +} +impl W { + #[doc = "Bits 0:31 - This is the version control register."] + #[inline(always)] + pub fn dma_date(&mut self) -> DMA_DATE_W { + DMA_DATE_W::new(self, 0) + } +} +#[doc = "Copy DMA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATE to value 0x1808_2000"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: u32 = 0x1808_2000; +} diff --git a/esp32s2/src/copy_dma/in_eof_des_addr.rs b/esp32s2/src/copy_dma/in_eof_des_addr.rs new file mode 100644 index 000000000..5314ef92d --- /dev/null +++ b/esp32s2/src/copy_dma/in_eof_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `IN_EOF_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the receive descriptor when received successful EOF."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the receive descriptor when received successful EOF."] + #[inline(always)] + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_EOF_DES_ADDR") + .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr()) + .finish() + } +} +#[doc = "Receive descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`in_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_EOF_DES_ADDR_SPEC; +impl crate::RegisterSpec for IN_EOF_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_eof_des_addr::R`](R) reader structure"] +impl crate::Readable for IN_EOF_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets IN_EOF_DES_ADDR to value 0"] +impl crate::Resettable for IN_EOF_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/in_link.rs b/esp32s2/src/copy_dma/in_link.rs new file mode 100644 index 000000000..c2f3ed4d6 --- /dev/null +++ b/esp32s2/src/copy_dma/in_link.rs @@ -0,0 +1,157 @@ +#[doc = "Register `IN_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR` reader - This register is used to specify the least significant 20 bits of the first receive descriptor’s address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register is used to specify the least significant 20 bits of the first receive descriptor’s address."] +pub type INLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] +pub type INLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START` reader - Set this bit to enable DMA to read receive descriptor."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to enable DMA to read receive descriptor."] +pub type INLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to restart new receive descriptors."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to restart new receive descriptors."] +pub type INLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INLINK_PARK { + #[doc = "0: The receive descriptor’s FSM is working."] + Working = 0, + #[doc = "1: The receive descriptor’s FSM is in idle state"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INLINK_PARK) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INLINK_PARK` reader - 1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; +impl INLINK_PARK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> INLINK_PARK { + match self.bits { + false => INLINK_PARK::Working, + true => INLINK_PARK::Idle, + } + } + #[doc = "The receive descriptor’s FSM is working."] + #[inline(always)] + pub fn is_working(&self) -> bool { + *self == INLINK_PARK::Working + } + #[doc = "The receive descriptor’s FSM is in idle state"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == INLINK_PARK::Idle + } +} +#[doc = "Field `INLINK_PARK` writer - 1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working."] +pub type INLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG, INLINK_PARK>; +impl<'a, REG> INLINK_PARK_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The receive descriptor’s FSM is working."] + #[inline(always)] + pub fn working(self) -> &'a mut crate::W { + self.variant(INLINK_PARK::Working) + } + #[doc = "The receive descriptor’s FSM is in idle state"] + #[inline(always)] + pub fn idle(self) -> &'a mut crate::W { + self.variant(INLINK_PARK::Idle) + } +} +impl R { + #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first receive descriptor’s address."] + #[inline(always)] + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to enable DMA to read receive descriptor."] + #[inline(always)] + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to restart new receive descriptors."] + #[inline(always)] + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working."] + #[inline(always)] + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK") + .field("inlink_addr", &self.inlink_addr()) + .field("inlink_stop", &self.inlink_stop()) + .field("inlink_start", &self.inlink_start()) + .field("inlink_restart", &self.inlink_restart()) + .field("inlink_park", &self.inlink_park()) + .finish() + } +} +impl W { + #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first receive descriptor’s address."] + #[inline(always)] + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W { + INLINK_ADDR_W::new(self, 0) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn inlink_stop(&mut self) -> INLINK_STOP_W { + INLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to enable DMA to read receive descriptor."] + #[inline(always)] + pub fn inlink_start(&mut self) -> INLINK_START_W { + INLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to restart new receive descriptors."] + #[inline(always)] + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W { + INLINK_RESTART_W::new(self, 30) + } + #[doc = "Bit 31 - 1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working."] + #[inline(always)] + pub fn inlink_park(&mut self) -> INLINK_PARK_W { + INLINK_PARK_W::new(self, 31) + } +} +#[doc = "Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_SPEC; +impl crate::RegisterSpec for IN_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link::R`](R) reader structure"] +impl crate::Readable for IN_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link::W`](W) writer structure"] +impl crate::Writable for IN_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IN_LINK to value 0"] +impl crate::Resettable for IN_LINK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/in_st.rs b/esp32s2/src/copy_dma/in_st.rs new file mode 100644 index 000000000..2f9040d99 --- /dev/null +++ b/esp32s2/src/copy_dma/in_st.rs @@ -0,0 +1,54 @@ +#[doc = "Register `IN_ST` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current receive descriptor’s address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - Reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - Reserved"] +pub type IN_STATE_R = crate::FieldReader; +#[doc = "Field `FIFO_EMPTY` reader - Copy DMA FIFO empty signal."] +pub type FIFO_EMPTY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current receive descriptor’s address."] + #[inline(always)] + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - Reserved"] + #[inline(always)] + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - Reserved"] + #[inline(always)] + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - Copy DMA FIFO empty signal."] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ST") + .field("inlink_dscr_addr", &self.inlink_dscr_addr()) + .field("in_dscr_state", &self.in_dscr_state()) + .field("in_state", &self.in_state()) + .field("fifo_empty", &self.fifo_empty()) + .finish() + } +} +#[doc = "Status register of receiving data\n\nYou can [`read`](crate::Reg::read) this register and get [`in_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ST_SPEC; +impl crate::RegisterSpec for IN_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_st::R`](R) reader structure"] +impl crate::Readable for IN_ST_SPEC {} +#[doc = "`reset()` method sets IN_ST to value 0"] +impl crate::Resettable for IN_ST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/inlink_dscr.rs b/esp32s2/src/copy_dma/inlink_dscr.rs new file mode 100644 index 000000000..8977e5ae5 --- /dev/null +++ b/esp32s2/src/copy_dma/inlink_dscr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `INLINK_DSCR` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR` reader - The address of the current receive descriptor x."] +pub type INLINK_DSCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the current receive descriptor x."] + #[inline(always)] + pub fn inlink_dscr(&self) -> INLINK_DSCR_R { + INLINK_DSCR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INLINK_DSCR") + .field("inlink_dscr", &self.inlink_dscr()) + .finish() + } +} +#[doc = "Address of current receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`inlink_dscr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INLINK_DSCR_SPEC; +impl crate::RegisterSpec for INLINK_DSCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inlink_dscr::R`](R) reader structure"] +impl crate::Readable for INLINK_DSCR_SPEC {} +#[doc = "`reset()` method sets INLINK_DSCR to value 0"] +impl crate::Resettable for INLINK_DSCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/inlink_dscr_bf0.rs b/esp32s2/src/copy_dma/inlink_dscr_bf0.rs new file mode 100644 index 000000000..275250d7a --- /dev/null +++ b/esp32s2/src/copy_dma/inlink_dscr_bf0.rs @@ -0,0 +1,30 @@ +#[doc = "Register `INLINK_DSCR_BF0` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last receive descriptor x-1."] +pub type INLINK_DSCR_BF0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last receive descriptor x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R { + INLINK_DSCR_BF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INLINK_DSCR_BF0") + .field("inlink_dscr_bf0", &self.inlink_dscr_bf0()) + .finish() + } +} +#[doc = "Address of last receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`inlink_dscr_bf0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INLINK_DSCR_BF0_SPEC; +impl crate::RegisterSpec for INLINK_DSCR_BF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inlink_dscr_bf0::R`](R) reader structure"] +impl crate::Readable for INLINK_DSCR_BF0_SPEC {} +#[doc = "`reset()` method sets INLINK_DSCR_BF0 to value 0"] +impl crate::Resettable for INLINK_DSCR_BF0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/int_clr.rs b/esp32s2/src/copy_dma/int_clr.rs new file mode 100644 index 000000000..479f7c27b --- /dev/null +++ b/esp32s2/src/copy_dma/int_clr.rs @@ -0,0 +1,81 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE` writer - Set this bit to clear IN_DONE interrupt."] +pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_DONE` writer - Set this bit to clear OUT_DONE interrupt."] +pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear OUT_EOF interrupt."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&mut self) -> IN_DONE_W { + IN_DONE_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W { + IN_SUC_EOF_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&mut self) -> OUT_DONE_W { + OUT_DONE_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W { + IN_DSCR_ERR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W { + OUT_DSCR_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W { + IN_DSCR_EMPTY_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W { + OUT_TOTAL_EOF_W::new(self, 7) + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/int_ena.rs b/esp32s2/src/copy_dma/int_ena.rs new file mode 100644 index 000000000..63bf45c27 --- /dev/null +++ b/esp32s2/src/copy_dma/int_ena.rs @@ -0,0 +1,152 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE` reader - This is the interrupt enable bit for IN_DONE interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - This is the interrupt enable bit for IN_DONE interrupt."] +pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF` reader - This is the interrupt enable bit for IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - This is the interrupt enable bit for IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DONE` reader - This is the interrupt enable bit for OUT_DONE interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - This is the interrupt enable bit for OUT_DONE interrupt."] +pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF` reader - This is the interrupt enable bit for OUT_EOF interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - This is the interrupt enable bit for OUT_EOF interrupt."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR` reader - This is the interrupt enable bit for IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - This is the interrupt enable bit for IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR` reader - This is the interrupt enable bit for OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - This is the interrupt enable bit for OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY` reader - This is the interrupt enable bit for IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - This is the interrupt enable bit for IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF` reader - This is the interrupt enable bit for OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - This is the interrupt enable bit for OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This is the interrupt enable bit for IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This is the interrupt enable bit for IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This is the interrupt enable bit for OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This is the interrupt enable bit for OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the interrupt enable bit for IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is the interrupt enable bit for OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the interrupt enable bit for IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This is the interrupt enable bit for OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("in_done", &self.in_done()) + .field("in_suc_eof", &self.in_suc_eof()) + .field("out_done", &self.out_done()) + .field("out_eof", &self.out_eof()) + .field("in_dscr_err", &self.in_dscr_err()) + .field("out_dscr_err", &self.out_dscr_err()) + .field("in_dscr_empty", &self.in_dscr_empty()) + .field("out_total_eof", &self.out_total_eof()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - This is the interrupt enable bit for IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&mut self) -> IN_DONE_W { + IN_DONE_W::new(self, 0) + } + #[doc = "Bit 1 - This is the interrupt enable bit for IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W { + IN_SUC_EOF_W::new(self, 1) + } + #[doc = "Bit 2 - This is the interrupt enable bit for OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&mut self) -> OUT_DONE_W { + OUT_DONE_W::new(self, 2) + } + #[doc = "Bit 3 - This is the interrupt enable bit for OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 3) + } + #[doc = "Bit 4 - This is the interrupt enable bit for IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W { + IN_DSCR_ERR_W::new(self, 4) + } + #[doc = "Bit 5 - This is the interrupt enable bit for OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W { + OUT_DSCR_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - This is the interrupt enable bit for IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W { + IN_DSCR_EMPTY_W::new(self, 6) + } + #[doc = "Bit 7 - This is the interrupt enable bit for OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W { + OUT_TOTAL_EOF_W::new(self, 7) + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/int_raw.rs b/esp32s2/src/copy_dma/int_raw.rs new file mode 100644 index 000000000..bc6f7a03e --- /dev/null +++ b/esp32s2/src/copy_dma/int_raw.rs @@ -0,0 +1,86 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE` reader - Triggered when the last data of frame is received or the receive buffer is full indicated by receive descriptor."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - Triggered when the last data of one frame is received."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - Triggered when all data indicated by one transmit descriptor has been pushed into TX FIFO."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - Triggered when the last data with EOF flag has been pushed into TX FIFO."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - Triggered when detecting receive descriptor error, including owner error, the second and third word error of receive descriptor."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - Triggered when detecting transmit descriptor error, including owner error, the second and third word error of transmit descriptor."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - Triggered when receiving data is completed and no more receive descriptor."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - Triggered when data corresponding to all transmit descriptors and the last descriptor with valid EOF is transmitted out."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Triggered when the last data of frame is received or the receive buffer is full indicated by receive descriptor."] + #[inline(always)] + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Triggered when the last data of one frame is received."] + #[inline(always)] + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Triggered when all data indicated by one transmit descriptor has been pushed into TX FIFO."] + #[inline(always)] + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Triggered when the last data with EOF flag has been pushed into TX FIFO."] + #[inline(always)] + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Triggered when detecting receive descriptor error, including owner error, the second and third word error of receive descriptor."] + #[inline(always)] + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Triggered when detecting transmit descriptor error, including owner error, the second and third word error of transmit descriptor."] + #[inline(always)] + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Triggered when receiving data is completed and no more receive descriptor."] + #[inline(always)] + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Triggered when data corresponding to all transmit descriptors and the last descriptor with valid EOF is transmitted out."] + #[inline(always)] + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field("in_done", &self.in_done()) + .field("in_suc_eof", &self.in_suc_eof()) + .field("out_done", &self.out_done()) + .field("out_eof", &self.out_eof()) + .field("in_dscr_err", &self.in_dscr_err()) + .field("out_dscr_err", &self.out_dscr_err()) + .field("in_dscr_empty", &self.in_dscr_empty()) + .field("out_total_eof", &self.out_total_eof()) + .finish() + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/int_st.rs b/esp32s2/src/copy_dma/int_st.rs new file mode 100644 index 000000000..ad7b44c12 --- /dev/null +++ b/esp32s2/src/copy_dma/int_st.rs @@ -0,0 +1,86 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE` reader - This is the masked interrupt bit for IN_DONE interrupt when IN_DONE is enabled."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - This is the masked interrupt bit for IN_SUC_EOF interrupt when IN_SUC_EOF is enabled."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - This is the masked interrupt bit for OUT_DONE interrupt when OUT_DONE is enabled."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - This is the masked interrupt bit for OUT_EOF interrupt when OUT_EOF is enabled."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - This is the masked interrupt bit for IN_DSCR_ERR interrupt when IN_DSCR_ERR is enabled."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - This is the masked interrupt bit for OUT_DSCR_ERR interrupt when OUT_DSCR_ERR is enabled."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - This is the masked interrupt bit for IN_DSCR_EMPTY interrupt when IN_DSCR_EMPTY is enabled."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - This is the masked interrupt bit for OUT_TOTAL_EOF interrupt when OUT_TOTAL_EOF is enabled."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This is the masked interrupt bit for IN_DONE interrupt when IN_DONE is enabled."] + #[inline(always)] + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This is the masked interrupt bit for IN_SUC_EOF interrupt when IN_SUC_EOF is enabled."] + #[inline(always)] + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This is the masked interrupt bit for OUT_DONE interrupt when OUT_DONE is enabled."] + #[inline(always)] + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This is the masked interrupt bit for OUT_EOF interrupt when OUT_EOF is enabled."] + #[inline(always)] + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the masked interrupt bit for IN_DSCR_ERR interrupt when IN_DSCR_ERR is enabled."] + #[inline(always)] + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is the masked interrupt bit for OUT_DSCR_ERR interrupt when OUT_DSCR_ERR is enabled."] + #[inline(always)] + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the masked interrupt bit for IN_DSCR_EMPTY interrupt when IN_DSCR_EMPTY is enabled."] + #[inline(always)] + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This is the masked interrupt bit for OUT_TOTAL_EOF interrupt when OUT_TOTAL_EOF is enabled."] + #[inline(always)] + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field("in_done", &self.in_done()) + .field("in_suc_eof", &self.in_suc_eof()) + .field("out_done", &self.out_done()) + .field("out_eof", &self.out_eof()) + .field("in_dscr_err", &self.in_dscr_err()) + .field("out_dscr_err", &self.out_dscr_err()) + .field("in_dscr_empty", &self.in_dscr_empty()) + .field("out_total_eof", &self.out_total_eof()) + .finish() + } +} +#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/out_eof_bfr_des_addr.rs b/esp32s2/src/copy_dma/out_eof_bfr_des_addr.rs new file mode 100644 index 000000000..91c2b9a5c --- /dev/null +++ b/esp32s2/src/copy_dma/out_eof_bfr_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `OUT_EOF_BFR_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the transmit descriptor before the last transmit descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the transmit descriptor before the last transmit descriptor."] + #[inline(always)] + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_BFR_DES_ADDR") + .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr()) + .finish() + } +} +#[doc = "Transmit descriptor address before the last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_BFR_DES_ADDR_SPEC; +impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_bfr_des_addr::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_BFR_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_BFR_DES_ADDR to value 0"] +impl crate::Resettable for OUT_EOF_BFR_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/out_eof_des_addr.rs b/esp32s2/src/copy_dma/out_eof_des_addr.rs new file mode 100644 index 000000000..70701391e --- /dev/null +++ b/esp32s2/src/copy_dma/out_eof_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `OUT_EOF_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR") + .field("out_eof_des_addr", &self.out_eof_des_addr()) + .finish() + } +} +#[doc = "Transmit descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/out_link.rs b/esp32s2/src/copy_dma/out_link.rs new file mode 100644 index 000000000..8a0d7ac5b --- /dev/null +++ b/esp32s2/src/copy_dma/out_link.rs @@ -0,0 +1,157 @@ +#[doc = "Register `OUT_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR` reader - This register is used to specify the least significant 20 bits of the first transmit descriptor’s address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register is used to specify the least significant 20 bits of the first transmit descriptor’s address."] +pub type OUTLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] +pub type OUTLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to start a new transmit descriptor."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to start a new transmit descriptor."] +pub type OUTLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart the transmit descriptor from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart the transmit descriptor from the last address."] +pub type OUTLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OUTLINK_PARK { + #[doc = "0: The transmit descriptor’s FSM is working."] + Working = 0, + #[doc = "1: The transmit descriptor’s FSM is in idle state"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OUTLINK_PARK) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OUTLINK_PARK` reader - 1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; +impl OUTLINK_PARK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUTLINK_PARK { + match self.bits { + false => OUTLINK_PARK::Working, + true => OUTLINK_PARK::Idle, + } + } + #[doc = "The transmit descriptor’s FSM is working."] + #[inline(always)] + pub fn is_working(&self) -> bool { + *self == OUTLINK_PARK::Working + } + #[doc = "The transmit descriptor’s FSM is in idle state"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == OUTLINK_PARK::Idle + } +} +#[doc = "Field `OUTLINK_PARK` writer - 1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working."] +pub type OUTLINK_PARK_W<'a, REG> = crate::BitWriter<'a, REG, OUTLINK_PARK>; +impl<'a, REG> OUTLINK_PARK_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The transmit descriptor’s FSM is working."] + #[inline(always)] + pub fn working(self) -> &'a mut crate::W { + self.variant(OUTLINK_PARK::Working) + } + #[doc = "The transmit descriptor’s FSM is in idle state"] + #[inline(always)] + pub fn idle(self) -> &'a mut crate::W { + self.variant(OUTLINK_PARK::Idle) + } +} +impl R { + #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first transmit descriptor’s address."] + #[inline(always)] + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to start a new transmit descriptor."] + #[inline(always)] + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to restart the transmit descriptor from the last address."] + #[inline(always)] + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working."] + #[inline(always)] + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK") + .field("outlink_addr", &self.outlink_addr()) + .field("outlink_stop", &self.outlink_stop()) + .field("outlink_start", &self.outlink_start()) + .field("outlink_restart", &self.outlink_restart()) + .field("outlink_park", &self.outlink_park()) + .finish() + } +} +impl W { + #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first transmit descriptor’s address."] + #[inline(always)] + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W { + OUTLINK_ADDR_W::new(self, 0) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W { + OUTLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to start a new transmit descriptor."] + #[inline(always)] + pub fn outlink_start(&mut self) -> OUTLINK_START_W { + OUTLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to restart the transmit descriptor from the last address."] + #[inline(always)] + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W { + OUTLINK_RESTART_W::new(self, 30) + } + #[doc = "Bit 31 - 1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working."] + #[inline(always)] + pub fn outlink_park(&mut self) -> OUTLINK_PARK_W { + OUTLINK_PARK_W::new(self, 31) + } +} +#[doc = "Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_SPEC; +impl crate::RegisterSpec for OUT_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OUT_LINK to value 0"] +impl crate::Resettable for OUT_LINK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/out_st.rs b/esp32s2/src/copy_dma/out_st.rs new file mode 100644 index 000000000..a4afe4fa0 --- /dev/null +++ b/esp32s2/src/copy_dma/out_st.rs @@ -0,0 +1,54 @@ +#[doc = "Register `OUT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current transmit descriptor’s address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - Reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - Reserved"] +pub type OUT_STATE_R = crate::FieldReader; +#[doc = "Field `FIFO_FULL` reader - Copy DMA FIFO full signal."] +pub type FIFO_FULL_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current transmit descriptor’s address."] + #[inline(always)] + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - Reserved"] + #[inline(always)] + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - Reserved"] + #[inline(always)] + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - Copy DMA FIFO full signal."] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ST") + .field("outlink_dscr_addr", &self.outlink_dscr_addr()) + .field("out_dscr_state", &self.out_dscr_state()) + .field("out_state", &self.out_state()) + .field("fifo_full", &self.fifo_full()) + .finish() + } +} +#[doc = "Status register of transmitting data\n\nYou can [`read`](crate::Reg::read) this register and get [`out_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ST_SPEC; +impl crate::RegisterSpec for OUT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_st::R`](R) reader structure"] +impl crate::Readable for OUT_ST_SPEC {} +#[doc = "`reset()` method sets OUT_ST to value 0"] +impl crate::Resettable for OUT_ST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/outlink_dscr.rs b/esp32s2/src/copy_dma/outlink_dscr.rs new file mode 100644 index 000000000..3da303531 --- /dev/null +++ b/esp32s2/src/copy_dma/outlink_dscr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `OUTLINK_DSCR` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR` reader - The address of the current transmit descriptor y."] +pub type OUTLINK_DSCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the current transmit descriptor y."] + #[inline(always)] + pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R { + OUTLINK_DSCR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTLINK_DSCR") + .field("outlink_dscr", &self.outlink_dscr()) + .finish() + } +} +#[doc = "Address of current transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`outlink_dscr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTLINK_DSCR_SPEC; +impl crate::RegisterSpec for OUTLINK_DSCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outlink_dscr::R`](R) reader structure"] +impl crate::Readable for OUTLINK_DSCR_SPEC {} +#[doc = "`reset()` method sets OUTLINK_DSCR to value 0"] +impl crate::Resettable for OUTLINK_DSCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/copy_dma/outlink_dscr_bf0.rs b/esp32s2/src/copy_dma/outlink_dscr_bf0.rs new file mode 100644 index 000000000..6f08ebc75 --- /dev/null +++ b/esp32s2/src/copy_dma/outlink_dscr_bf0.rs @@ -0,0 +1,30 @@ +#[doc = "Register `OUTLINK_DSCR_BF0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last transmit descriptor y-1."] +pub type OUTLINK_DSCR_BF0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last transmit descriptor y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R { + OUTLINK_DSCR_BF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTLINK_DSCR_BF0") + .field("outlink_dscr_bf0", &self.outlink_dscr_bf0()) + .finish() + } +} +#[doc = "Address of last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`outlink_dscr_bf0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTLINK_DSCR_BF0_SPEC; +impl crate::RegisterSpec for OUTLINK_DSCR_BF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outlink_dscr_bf0::R`](R) reader structure"] +impl crate::Readable for OUTLINK_DSCR_BF0_SPEC {} +#[doc = "`reset()` method sets OUTLINK_DSCR_BF0 to value 0"] +impl crate::Resettable for OUTLINK_DSCR_BF0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma.rs b/esp32s2/src/crypto_dma.rs new file mode 100644 index 000000000..8b8528587 --- /dev/null +++ b/esp32s2/src/crypto_dma.rs @@ -0,0 +1,252 @@ +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +#[doc = "Register block"] +pub struct RegisterBlock { + conf: CONF, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + out_status: OUT_STATUS, + _reserved6: [u8; 0x04], + in_status: IN_STATUS, + _reserved7: [u8; 0x04], + out_link: OUT_LINK, + in_link: IN_LINK, + conf1: CONF1, + state0: STATE0, + state1: STATE1, + out_eof_des_addr: OUT_EOF_DES_ADDR, + in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR, + in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR, + out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR, + ahb_test: AHB_TEST, + dma_in_dscr: DMA_IN_DSCR, + dma_in_dscr_bf0: DMA_IN_DSCR_BF0, + _reserved19: [u8; 0x04], + dma_out_dscr: DMA_OUT_DSCR, + dma_out_dscr_bf0: DMA_OUT_DSCR_BF0, + _reserved21: [u8; 0x04], + aes_sha_select: AES_SHA_SELECT, + pd_conf: PD_CONF, + _reserved23: [u8; 0x90], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - DMA configuration register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x04 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x08 - Masked interrupt status"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x0c - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x10 - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x14 - TX FIFO status register"] + #[inline(always)] + pub const fn out_status(&self) -> &OUT_STATUS { + &self.out_status + } + #[doc = "0x1c - RX FIFO status register"] + #[inline(always)] + pub const fn in_status(&self) -> &IN_STATUS { + &self.in_status + } + #[doc = "0x24 - Link descriptor address and control"] + #[inline(always)] + pub const fn out_link(&self) -> &OUT_LINK { + &self.out_link + } + #[doc = "0x28 - Link descriptor address and control"] + #[inline(always)] + pub const fn in_link(&self) -> &IN_LINK { + &self.in_link + } + #[doc = "0x2c - DMA configuration register"] + #[inline(always)] + pub const fn conf1(&self) -> &CONF1 { + &self.conf1 + } + #[doc = "0x30 - Status register of receiving data"] + #[inline(always)] + pub const fn state0(&self) -> &STATE0 { + &self.state0 + } + #[doc = "0x34 - Status register of transmitting data"] + #[inline(always)] + pub const fn state1(&self) -> &STATE1 { + &self.state1 + } + #[doc = "0x38 - Transmit descriptor address when EOF occurs"] + #[inline(always)] + pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR { + &self.out_eof_des_addr + } + #[doc = "0x3c - Receive descriptor address when EOF occurs"] + #[inline(always)] + pub const fn in_suc_eof_des_addr(&self) -> &IN_SUC_EOF_DES_ADDR { + &self.in_suc_eof_des_addr + } + #[doc = "0x40 - Receive descriptor address when errors occur"] + #[inline(always)] + pub const fn in_err_eof_des_addr(&self) -> &IN_ERR_EOF_DES_ADDR { + &self.in_err_eof_des_addr + } + #[doc = "0x44 - Transmit descriptor address before the last transmit descriptor"] + #[inline(always)] + pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR { + &self.out_eof_bfr_des_addr + } + #[doc = "0x48 - AHB test register"] + #[inline(always)] + pub const fn ahb_test(&self) -> &AHB_TEST { + &self.ahb_test + } + #[doc = "0x4c - Address of current receive descriptor"] + #[inline(always)] + pub const fn dma_in_dscr(&self) -> &DMA_IN_DSCR { + &self.dma_in_dscr + } + #[doc = "0x50 - Address of last receive descriptor"] + #[inline(always)] + pub const fn dma_in_dscr_bf0(&self) -> &DMA_IN_DSCR_BF0 { + &self.dma_in_dscr_bf0 + } + #[doc = "0x58 - Address of current transmit descriptor"] + #[inline(always)] + pub const fn dma_out_dscr(&self) -> &DMA_OUT_DSCR { + &self.dma_out_dscr + } + #[doc = "0x5c - Address of last transmit descriptor"] + #[inline(always)] + pub const fn dma_out_dscr_bf0(&self) -> &DMA_OUT_DSCR_BF0 { + &self.dma_out_dscr_bf0 + } + #[doc = "0x64 - AES/SHA select register"] + #[inline(always)] + pub const fn aes_sha_select(&self) -> &AES_SHA_SELECT { + &self.aes_sha_select + } + #[doc = "0x68 - Power control register"] + #[inline(always)] + pub const fn pd_conf(&self) -> &PD_CONF { + &self.pd_conf + } + #[doc = "0xfc - Crypto DMA version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CONF (rw) register accessor: DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "DMA configuration register"] +pub mod conf; +#[doc = "OUT_LINK (rw) register accessor: Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link`] module"] +pub type OUT_LINK = crate::Reg; +#[doc = "Link descriptor address and control"] +pub mod out_link; +#[doc = "IN_LINK (rw) register accessor: Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link`] module"] +pub type IN_LINK = crate::Reg; +#[doc = "Link descriptor address and control"] +pub mod in_link; +#[doc = "CONF1 (rw) register accessor: DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"] +pub type CONF1 = crate::Reg; +#[doc = "DMA configuration register"] +pub mod conf1; +#[doc = "AHB_TEST (rw) register accessor: AHB test register\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_test::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_test::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_test`] module"] +pub type AHB_TEST = crate::Reg; +#[doc = "AHB test register"] +pub mod ahb_test; +#[doc = "AES_SHA_SELECT (rw) register accessor: AES/SHA select register\n\nYou can [`read`](crate::Reg::read) this register and get [`aes_sha_select::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aes_sha_select::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aes_sha_select`] module"] +pub type AES_SHA_SELECT = crate::Reg; +#[doc = "AES/SHA select register"] +pub mod aes_sha_select; +#[doc = "PD_CONF (rw) register accessor: Power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_conf`] module"] +pub type PD_CONF = crate::Reg; +#[doc = "Power control register"] +pub mod pd_conf; +#[doc = "DATE (rw) register accessor: Crypto DMA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Crypto DMA version control register"] +pub mod date; +#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Masked interrupt status"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "OUT_STATUS (r) register accessor: TX FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`out_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_status`] module"] +pub type OUT_STATUS = crate::Reg; +#[doc = "TX FIFO status register"] +pub mod out_status; +#[doc = "IN_STATUS (r) register accessor: RX FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`in_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_status`] module"] +pub type IN_STATUS = crate::Reg; +#[doc = "RX FIFO status register"] +pub mod in_status; +#[doc = "STATE0 (r) register accessor: Status register of receiving data\n\nYou can [`read`](crate::Reg::read) this register and get [`state0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state0`] module"] +pub type STATE0 = crate::Reg; +#[doc = "Status register of receiving data"] +pub mod state0; +#[doc = "STATE1 (r) register accessor: Status register of transmitting data\n\nYou can [`read`](crate::Reg::read) this register and get [`state1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state1`] module"] +pub type STATE1 = crate::Reg; +#[doc = "Status register of transmitting data"] +pub mod state1; +#[doc = "OUT_EOF_DES_ADDR (r) register accessor: Transmit descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr`] module"] +pub type OUT_EOF_DES_ADDR = crate::Reg; +#[doc = "Transmit descriptor address when EOF occurs"] +pub mod out_eof_des_addr; +#[doc = "IN_SUC_EOF_DES_ADDR (r) register accessor: Receive descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`in_suc_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr`] module"] +pub type IN_SUC_EOF_DES_ADDR = crate::Reg; +#[doc = "Receive descriptor address when EOF occurs"] +pub mod in_suc_eof_des_addr; +#[doc = "IN_ERR_EOF_DES_ADDR (r) register accessor: Receive descriptor address when errors occur\n\nYou can [`read`](crate::Reg::read) this register and get [`in_err_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr`] module"] +pub type IN_ERR_EOF_DES_ADDR = crate::Reg; +#[doc = "Receive descriptor address when errors occur"] +pub mod in_err_eof_des_addr; +#[doc = "OUT_EOF_BFR_DES_ADDR (r) register accessor: Transmit descriptor address before the last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr`] module"] +pub type OUT_EOF_BFR_DES_ADDR = crate::Reg; +#[doc = "Transmit descriptor address before the last transmit descriptor"] +pub mod out_eof_bfr_des_addr; +#[doc = "DMA_IN_DSCR (r) register accessor: Address of current receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_in_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_in_dscr`] module"] +pub type DMA_IN_DSCR = crate::Reg; +#[doc = "Address of current receive descriptor"] +pub mod dma_in_dscr; +#[doc = "DMA_IN_DSCR_BF0 (r) register accessor: Address of last receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_in_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_in_dscr_bf0`] module"] +pub type DMA_IN_DSCR_BF0 = crate::Reg; +#[doc = "Address of last receive descriptor"] +pub mod dma_in_dscr_bf0; +#[doc = "DMA_OUT_DSCR (r) register accessor: Address of current transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_out_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_out_dscr`] module"] +pub type DMA_OUT_DSCR = crate::Reg; +#[doc = "Address of current transmit descriptor"] +pub mod dma_out_dscr; +#[doc = "DMA_OUT_DSCR_BF0 (r) register accessor: Address of last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_out_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_out_dscr_bf0`] module"] +pub type DMA_OUT_DSCR_BF0 = crate::Reg; +#[doc = "Address of last transmit descriptor"] +pub mod dma_out_dscr_bf0; diff --git a/esp32s2/src/crypto_dma/aes_sha_select.rs b/esp32s2/src/crypto_dma/aes_sha_select.rs new file mode 100644 index 000000000..00c7e135c --- /dev/null +++ b/esp32s2/src/crypto_dma/aes_sha_select.rs @@ -0,0 +1,97 @@ +#[doc = "Register `AES_SHA_SELECT` reader"] +pub type R = crate::R; +#[doc = "Register `AES_SHA_SELECT` writer"] +pub type W = crate::W; +#[doc = "Select one between AES and SHA to use DMA. 0: AES. 1: SHA.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SELECT { + #[doc = "0: The AES peripheral uses the Crypto DMA"] + Aes = 0, + #[doc = "1: The SHA peripheral uses the Crypto DMA"] + Sha = 1, +} +impl From; +impl SELECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SELECT { + match self.bits { + false => SELECT::Aes, + true => SELECT::Sha, + } + } + #[doc = "The AES peripheral uses the Crypto DMA"] + #[inline(always)] + pub fn is_aes(&self) -> bool { + *self == SELECT::Aes + } + #[doc = "The SHA peripheral uses the Crypto DMA"] + #[inline(always)] + pub fn is_sha(&self) -> bool { + *self == SELECT::Sha + } +} +#[doc = "Field `SELECT` writer - Select one between AES and SHA to use DMA. 0: AES. 1: SHA."] +pub type SELECT_W<'a, REG> = crate::BitWriter<'a, REG, SELECT>; +impl<'a, REG> SELECT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The AES peripheral uses the Crypto DMA"] + #[inline(always)] + pub fn aes(self) -> &'a mut crate::W { + self.variant(SELECT::Aes) + } + #[doc = "The SHA peripheral uses the Crypto DMA"] + #[inline(always)] + pub fn sha(self) -> &'a mut crate::W { + self.variant(SELECT::Sha) + } +} +impl R { + #[doc = "Bit 0 - Select one between AES and SHA to use DMA. 0: AES. 1: SHA."] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AES_SHA_SELECT") + .field("select", &self.select()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - Select one between AES and SHA to use DMA. 0: AES. 1: SHA."] + #[inline(always)] + pub fn select(&mut self) -> SELECT_W { + SELECT_W::new(self, 0) + } +} +#[doc = "AES/SHA select register\n\nYou can [`read`](crate::Reg::read) this register and get [`aes_sha_select::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aes_sha_select::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AES_SHA_SELECT_SPEC; +impl crate::RegisterSpec for AES_SHA_SELECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`aes_sha_select::R`](R) reader structure"] +impl crate::Readable for AES_SHA_SELECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aes_sha_select::W`](W) writer structure"] +impl crate::Writable for AES_SHA_SELECT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets AES_SHA_SELECT to value 0"] +impl crate::Resettable for AES_SHA_SELECT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/ahb_test.rs b/esp32s2/src/crypto_dma/ahb_test.rs new file mode 100644 index 000000000..34ea9f7e8 --- /dev/null +++ b/esp32s2/src/crypto_dma/ahb_test.rs @@ -0,0 +1,62 @@ +#[doc = "Register `AHB_TEST` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_TEST` writer"] +pub type W = crate::W; +#[doc = "Field `AHB_TESTMODE` reader - Reserved"] +pub type AHB_TESTMODE_R = crate::FieldReader; +#[doc = "Field `AHB_TESTMODE` writer - Reserved"] +pub type AHB_TESTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `AHB_TESTADDR` reader - Reserved"] +pub type AHB_TESTADDR_R = crate::FieldReader; +#[doc = "Field `AHB_TESTADDR` writer - Reserved"] +pub type AHB_TESTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:2 - Reserved"] + #[inline(always)] + pub fn ahb_testmode(&self) -> AHB_TESTMODE_R { + AHB_TESTMODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:5 - Reserved"] + #[inline(always)] + pub fn ahb_testaddr(&self) -> AHB_TESTADDR_R { + AHB_TESTADDR_R::new(((self.bits >> 4) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_TEST") + .field("ahb_testmode", &self.ahb_testmode()) + .field("ahb_testaddr", &self.ahb_testaddr()) + .finish() + } +} +impl W { + #[doc = "Bits 0:2 - Reserved"] + #[inline(always)] + pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W { + AHB_TESTMODE_W::new(self, 0) + } + #[doc = "Bits 4:5 - Reserved"] + #[inline(always)] + pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W { + AHB_TESTADDR_W::new(self, 4) + } +} +#[doc = "AHB test register\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_test::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_test::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_TEST_SPEC; +impl crate::RegisterSpec for AHB_TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_test::R`](R) reader structure"] +impl crate::Readable for AHB_TEST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_test::W`](W) writer structure"] +impl crate::Writable for AHB_TEST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets AHB_TEST to value 0"] +impl crate::Resettable for AHB_TEST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/conf.rs b/esp32s2/src/crypto_dma/conf.rs new file mode 100644 index 000000000..32a871790 --- /dev/null +++ b/esp32s2/src/crypto_dma/conf.rs @@ -0,0 +1,277 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `IN_RST` reader - This bit is used to reset crypto DMA in FSM and RX FIFO pointer."] +pub type IN_RST_R = crate::BitReader; +#[doc = "Field `IN_RST` writer - This bit is used to reset crypto DMA in FSM and RX FIFO pointer."] +pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RST` reader - This bit is used to reset crypto DMA out FSM and TX FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset crypto DMA out FSM and TX FIFO pointer."] +pub type OUT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AHBM_FIFO_RST` reader - This bit is used to reset crypto DMA AHB master FIFO pointer."] +pub type AHBM_FIFO_RST_R = crate::BitReader; +#[doc = "Field `AHBM_FIFO_RST` writer - This bit is used to reset crypto DMA AHB master FIFO pointer."] +pub type AHBM_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AHBM_RST` reader - Reset crypto DMA AHB master."] +pub type AHBM_RST_R = crate::BitReader; +#[doc = "Field `AHBM_RST` writer - Reset crypto DMA AHB master."] +pub type AHBM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_LOOP_TEST` reader - Reserved"] +pub type IN_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST` writer - Reserved"] +pub type IN_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_LOOP_TEST` reader - Reserved"] +pub type OUT_LOOP_TEST_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST` writer - Reserved"] +pub type OUT_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in TX Buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in TX Buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_NO_RESTART_CLR` reader - Reserved"] +pub type OUT_NO_RESTART_CLR_R = crate::BitReader; +#[doc = "Field `OUT_NO_RESTART_CLR` writer - Reserved"] +pub type OUT_NO_RESTART_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Out EOF flag generation mode of TX FIFO. 1: EOF flag of TX is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA; 0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA.\n\nValue on reset: 1"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OUT_EOF_MODE { + #[doc = "0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA"] + OnPush = 0, + #[doc = "1: EOF flag is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA"] + OnPop = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OUT_EOF_MODE) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OUT_EOF_MODE` reader - Out EOF flag generation mode of TX FIFO. 1: EOF flag of TX is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA; 0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA."] +pub type OUT_EOF_MODE_R = crate::BitReader; +impl OUT_EOF_MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUT_EOF_MODE { + match self.bits { + false => OUT_EOF_MODE::OnPush, + true => OUT_EOF_MODE::OnPop, + } + } + #[doc = "EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA"] + #[inline(always)] + pub fn is_on_push(&self) -> bool { + *self == OUT_EOF_MODE::OnPush + } + #[doc = "EOF flag is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA"] + #[inline(always)] + pub fn is_on_pop(&self) -> bool { + *self == OUT_EOF_MODE::OnPop + } +} +#[doc = "Field `OUT_EOF_MODE` writer - Out EOF flag generation mode of TX FIFO. 1: EOF flag of TX is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA; 0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA."] +pub type OUT_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG, OUT_EOF_MODE>; +impl<'a, REG> OUT_EOF_MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA"] + #[inline(always)] + pub fn on_push(self) -> &'a mut crate::W { + self.variant(OUT_EOF_MODE::OnPush) + } + #[doc = "EOF flag is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA"] + #[inline(always)] + pub fn on_pop(self) -> &'a mut crate::W { + self.variant(OUT_EOF_MODE::OnPop) + } +} +#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to enable INCR burst transfer when TX FIFO reads descriptor from internal RAM."] +pub type OUTDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to enable INCR burst transfer when TX FIFO reads descriptor from internal RAM."] +pub type OUTDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to enable INCR burst transfer when RX FIFO reads descriptor from internal RAM."] +pub type INDSCR_BURST_EN_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to enable INCR burst transfer when RX FIFO reads descriptor from internal RAM."] +pub type INDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to enable INCR burst transfer when TX FIFO reads data from internal RAM."] +pub type OUT_DATA_BURST_EN_R = crate::BitReader; +#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to enable INCR burst transfer when TX FIFO reads data from internal RAM."] +pub type OUT_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_TRANS_EN` reader - Set this bit to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN` writer - Set this bit to enable automatic transmitting data from memory to memory via DMA."] +pub type MEM_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset crypto DMA in FSM and RX FIFO pointer."] + #[inline(always)] + pub fn in_rst(&self) -> IN_RST_R { + IN_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This bit is used to reset crypto DMA out FSM and TX FIFO pointer."] + #[inline(always)] + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit is used to reset crypto DMA AHB master FIFO pointer."] + #[inline(always)] + pub fn ahbm_fifo_rst(&self) -> AHBM_FIFO_RST_R { + AHBM_FIFO_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reset crypto DMA AHB master."] + #[inline(always)] + pub fn ahbm_rst(&self) -> AHBM_RST_R { + AHBM_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn in_loop_test(&self) -> IN_LOOP_TEST_R { + IN_LOOP_TEST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R { + OUT_LOOP_TEST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to enable automatic outlink-writeback when all the data in TX Buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R { + OUT_AUTO_WRBACK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn out_no_restart_clr(&self) -> OUT_NO_RESTART_CLR_R { + OUT_NO_RESTART_CLR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Out EOF flag generation mode of TX FIFO. 1: EOF flag of TX is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA; 0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA."] + #[inline(always)] + pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R { + OUT_EOF_MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Set this bit to enable INCR burst transfer when TX FIFO reads descriptor from internal RAM."] + #[inline(always)] + pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R { + OUTDSCR_BURST_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to enable INCR burst transfer when RX FIFO reads descriptor from internal RAM."] + #[inline(always)] + pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R { + INDSCR_BURST_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Set this bit to enable INCR burst transfer when TX FIFO reads data from internal RAM."] + #[inline(always)] + pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R { + OUT_DATA_BURST_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Set this bit to enable automatic transmitting data from memory to memory via DMA."] + #[inline(always)] + pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R { + MEM_TRANS_EN_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("in_rst", &self.in_rst()) + .field("out_rst", &self.out_rst()) + .field("ahbm_fifo_rst", &self.ahbm_fifo_rst()) + .field("ahbm_rst", &self.ahbm_rst()) + .field("in_loop_test", &self.in_loop_test()) + .field("out_loop_test", &self.out_loop_test()) + .field("out_auto_wrback", &self.out_auto_wrback()) + .field("out_no_restart_clr", &self.out_no_restart_clr()) + .field("out_eof_mode", &self.out_eof_mode()) + .field("outdscr_burst_en", &self.outdscr_burst_en()) + .field("indscr_burst_en", &self.indscr_burst_en()) + .field("out_data_burst_en", &self.out_data_burst_en()) + .field("mem_trans_en", &self.mem_trans_en()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset crypto DMA in FSM and RX FIFO pointer."] + #[inline(always)] + pub fn in_rst(&mut self) -> IN_RST_W { + IN_RST_W::new(self, 0) + } + #[doc = "Bit 1 - This bit is used to reset crypto DMA out FSM and TX FIFO pointer."] + #[inline(always)] + pub fn out_rst(&mut self) -> OUT_RST_W { + OUT_RST_W::new(self, 1) + } + #[doc = "Bit 2 - This bit is used to reset crypto DMA AHB master FIFO pointer."] + #[inline(always)] + pub fn ahbm_fifo_rst(&mut self) -> AHBM_FIFO_RST_W { + AHBM_FIFO_RST_W::new(self, 2) + } + #[doc = "Bit 3 - Reset crypto DMA AHB master."] + #[inline(always)] + pub fn ahbm_rst(&mut self) -> AHBM_RST_W { + AHBM_RST_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W { + IN_LOOP_TEST_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W { + OUT_LOOP_TEST_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to enable automatic outlink-writeback when all the data in TX Buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W { + OUT_AUTO_WRBACK_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn out_no_restart_clr(&mut self) -> OUT_NO_RESTART_CLR_W { + OUT_NO_RESTART_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Out EOF flag generation mode of TX FIFO. 1: EOF flag of TX is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA; 0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA."] + #[inline(always)] + pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W { + OUT_EOF_MODE_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to enable INCR burst transfer when TX FIFO reads descriptor from internal RAM."] + #[inline(always)] + pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W { + OUTDSCR_BURST_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to enable INCR burst transfer when RX FIFO reads descriptor from internal RAM."] + #[inline(always)] + pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W { + INDSCR_BURST_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to enable INCR burst transfer when TX FIFO reads data from internal RAM."] + #[inline(always)] + pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W { + OUT_DATA_BURST_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to enable automatic transmitting data from memory to memory via DMA."] + #[inline(always)] + pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W { + MEM_TRANS_EN_W::new(self, 12) + } +} +#[doc = "DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONF to value 0x0100"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: u32 = 0x0100; +} diff --git a/esp32s2/src/crypto_dma/conf1.rs b/esp32s2/src/crypto_dma/conf1.rs new file mode 100644 index 000000000..7c3ba64ce --- /dev/null +++ b/esp32s2/src/crypto_dma/conf1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_FULL_THRS` reader - This register is used to generate the CRYPTO_DMA_INFIFO_FULL_WM_INT interrupt when the byte number is up to the value of the register."] +pub type INFIFO_FULL_THRS_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_THRS` writer - This register is used to generate the CRYPTO_DMA_INFIFO_FULL_WM_INT interrupt when the byte number is up to the value of the register."] +pub type INFIFO_FULL_THRS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type CHECK_OWNER_R = crate::BitReader; +#[doc = "Field `CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type CHECK_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "DMA access external memory block size. 0: 16 bytes; 1: 32 bytes; 2: 64 bytes; 3:Reserved.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EXT_MEM_BK_SIZE { + #[doc = "0: DMA access external memory block size is 16 bytes"] + Size16 = 0, + #[doc = "1: DMA access external memory block size is 32 bytes"] + Size32 = 1, + #[doc = "2: DMA access external memory block size is 64 bytes"] + Size64 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EXT_MEM_BK_SIZE) -> Self { + variant as _ + } +} +impl crate::FieldSpec for EXT_MEM_BK_SIZE { + type Ux = u8; +} +impl crate::IsEnum for EXT_MEM_BK_SIZE {} +#[doc = "Field `EXT_MEM_BK_SIZE` reader - DMA access external memory block size. 0: 16 bytes; 1: 32 bytes; 2: 64 bytes; 3:Reserved."] +pub type EXT_MEM_BK_SIZE_R = crate::FieldReader; +impl EXT_MEM_BK_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(EXT_MEM_BK_SIZE::Size16), + 1 => Some(EXT_MEM_BK_SIZE::Size32), + 2 => Some(EXT_MEM_BK_SIZE::Size64), + _ => None, + } + } + #[doc = "DMA access external memory block size is 16 bytes"] + #[inline(always)] + pub fn is_size_16(&self) -> bool { + *self == EXT_MEM_BK_SIZE::Size16 + } + #[doc = "DMA access external memory block size is 32 bytes"] + #[inline(always)] + pub fn is_size_32(&self) -> bool { + *self == EXT_MEM_BK_SIZE::Size32 + } + #[doc = "DMA access external memory block size is 64 bytes"] + #[inline(always)] + pub fn is_size_64(&self) -> bool { + *self == EXT_MEM_BK_SIZE::Size64 + } +} +#[doc = "Field `EXT_MEM_BK_SIZE` writer - DMA access external memory block size. 0: 16 bytes; 1: 32 bytes; 2: 64 bytes; 3:Reserved."] +pub type EXT_MEM_BK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EXT_MEM_BK_SIZE>; +impl<'a, REG> EXT_MEM_BK_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "DMA access external memory block size is 16 bytes"] + #[inline(always)] + pub fn size_16(self) -> &'a mut crate::W { + self.variant(EXT_MEM_BK_SIZE::Size16) + } + #[doc = "DMA access external memory block size is 32 bytes"] + #[inline(always)] + pub fn size_32(self) -> &'a mut crate::W { + self.variant(EXT_MEM_BK_SIZE::Size32) + } + #[doc = "DMA access external memory block size is 64 bytes"] + #[inline(always)] + pub fn size_64(self) -> &'a mut crate::W { + self.variant(EXT_MEM_BK_SIZE::Size64) + } +} +impl R { + #[doc = "Bits 0:11 - This register is used to generate the CRYPTO_DMA_INFIFO_FULL_WM_INT interrupt when the byte number is up to the value of the register."] + #[inline(always)] + pub fn infifo_full_thrs(&self) -> INFIFO_FULL_THRS_R { + INFIFO_FULL_THRS_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn check_owner(&self) -> CHECK_OWNER_R { + CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:14 - DMA access external memory block size. 0: 16 bytes; 1: 32 bytes; 2: 64 bytes; 3:Reserved."] + #[inline(always)] + pub fn ext_mem_bk_size(&self) -> EXT_MEM_BK_SIZE_R { + EXT_MEM_BK_SIZE_R::new(((self.bits >> 13) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF1") + .field("infifo_full_thrs", &self.infifo_full_thrs()) + .field("check_owner", &self.check_owner()) + .field("ext_mem_bk_size", &self.ext_mem_bk_size()) + .finish() + } +} +impl W { + #[doc = "Bits 0:11 - This register is used to generate the CRYPTO_DMA_INFIFO_FULL_WM_INT interrupt when the byte number is up to the value of the register."] + #[inline(always)] + pub fn infifo_full_thrs(&mut self) -> INFIFO_FULL_THRS_W { + INFIFO_FULL_THRS_W::new(self, 0) + } + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn check_owner(&mut self) -> CHECK_OWNER_W { + CHECK_OWNER_W::new(self, 12) + } + #[doc = "Bits 13:14 - DMA access external memory block size. 0: 16 bytes; 1: 32 bytes; 2: 64 bytes; 3:Reserved."] + #[inline(always)] + pub fn ext_mem_bk_size(&mut self) -> EXT_MEM_BK_SIZE_W { + EXT_MEM_BK_SIZE_W::new(self, 13) + } +} +#[doc = "DMA configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF1_SPEC; +impl crate::RegisterSpec for CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf1::R`](R) reader structure"] +impl crate::Readable for CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"] +impl crate::Writable for CONF1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONF1 to value 0"] +impl crate::Resettable for CONF1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/date.rs b/esp32s2/src/crypto_dma/date.rs new file mode 100644 index 000000000..313252ebf --- /dev/null +++ b/esp32s2/src/crypto_dma/date.rs @@ -0,0 +1,45 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - This is the version control register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - This is the version control register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is the version control register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE").field("date", &self.date()).finish() + } +} +impl W { + #[doc = "Bits 0:31 - This is the version control register."] + #[inline(always)] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } +} +#[doc = "Crypto DMA version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATE to value 0x1905_0700"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: u32 = 0x1905_0700; +} diff --git a/esp32s2/src/crypto_dma/dma_in_dscr.rs b/esp32s2/src/crypto_dma/dma_in_dscr.rs new file mode 100644 index 000000000..a876cb176 --- /dev/null +++ b/esp32s2/src/crypto_dma/dma_in_dscr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `DMA_IN_DSCR` reader"] +pub type R = crate::R; +#[doc = "Field `DMA_IN_DSCR` reader - Address of the current receive descriptor x."] +pub type DMA_IN_DSCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Address of the current receive descriptor x."] + #[inline(always)] + pub fn dma_in_dscr(&self) -> DMA_IN_DSCR_R { + DMA_IN_DSCR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_IN_DSCR") + .field("dma_in_dscr", &self.dma_in_dscr()) + .finish() + } +} +#[doc = "Address of current receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_in_dscr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_IN_DSCR_SPEC; +impl crate::RegisterSpec for DMA_IN_DSCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_in_dscr::R`](R) reader structure"] +impl crate::Readable for DMA_IN_DSCR_SPEC {} +#[doc = "`reset()` method sets DMA_IN_DSCR to value 0"] +impl crate::Resettable for DMA_IN_DSCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/dma_in_dscr_bf0.rs b/esp32s2/src/crypto_dma/dma_in_dscr_bf0.rs new file mode 100644 index 000000000..77d3beead --- /dev/null +++ b/esp32s2/src/crypto_dma/dma_in_dscr_bf0.rs @@ -0,0 +1,30 @@ +#[doc = "Register `DMA_IN_DSCR_BF0` reader"] +pub type R = crate::R; +#[doc = "Field `DMA_IN_DSCR_BF0` reader - Address of the last receive descriptor x-1."] +pub type DMA_IN_DSCR_BF0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Address of the last receive descriptor x-1."] + #[inline(always)] + pub fn dma_in_dscr_bf0(&self) -> DMA_IN_DSCR_BF0_R { + DMA_IN_DSCR_BF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_IN_DSCR_BF0") + .field("dma_in_dscr_bf0", &self.dma_in_dscr_bf0()) + .finish() + } +} +#[doc = "Address of last receive descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_in_dscr_bf0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_IN_DSCR_BF0_SPEC; +impl crate::RegisterSpec for DMA_IN_DSCR_BF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_in_dscr_bf0::R`](R) reader structure"] +impl crate::Readable for DMA_IN_DSCR_BF0_SPEC {} +#[doc = "`reset()` method sets DMA_IN_DSCR_BF0 to value 0"] +impl crate::Resettable for DMA_IN_DSCR_BF0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/dma_out_dscr.rs b/esp32s2/src/crypto_dma/dma_out_dscr.rs new file mode 100644 index 000000000..1fa9289d9 --- /dev/null +++ b/esp32s2/src/crypto_dma/dma_out_dscr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `DMA_OUT_DSCR` reader"] +pub type R = crate::R; +#[doc = "Field `DMA_OUT_DSCR` reader - Address of the current transmit descriptor y."] +pub type DMA_OUT_DSCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Address of the current transmit descriptor y."] + #[inline(always)] + pub fn dma_out_dscr(&self) -> DMA_OUT_DSCR_R { + DMA_OUT_DSCR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_OUT_DSCR") + .field("dma_out_dscr", &self.dma_out_dscr()) + .finish() + } +} +#[doc = "Address of current transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_out_dscr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_OUT_DSCR_SPEC; +impl crate::RegisterSpec for DMA_OUT_DSCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_out_dscr::R`](R) reader structure"] +impl crate::Readable for DMA_OUT_DSCR_SPEC {} +#[doc = "`reset()` method sets DMA_OUT_DSCR to value 0"] +impl crate::Resettable for DMA_OUT_DSCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/dma_out_dscr_bf0.rs b/esp32s2/src/crypto_dma/dma_out_dscr_bf0.rs new file mode 100644 index 000000000..cc649574e --- /dev/null +++ b/esp32s2/src/crypto_dma/dma_out_dscr_bf0.rs @@ -0,0 +1,30 @@ +#[doc = "Register `DMA_OUT_DSCR_BF0` reader"] +pub type R = crate::R; +#[doc = "Field `DMA_OUT_DSCR_BF0` reader - Address of the last transmit descriptor y-1."] +pub type DMA_OUT_DSCR_BF0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Address of the last transmit descriptor y-1."] + #[inline(always)] + pub fn dma_out_dscr_bf0(&self) -> DMA_OUT_DSCR_BF0_R { + DMA_OUT_DSCR_BF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_OUT_DSCR_BF0") + .field("dma_out_dscr_bf0", &self.dma_out_dscr_bf0()) + .finish() + } +} +#[doc = "Address of last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_out_dscr_bf0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_OUT_DSCR_BF0_SPEC; +impl crate::RegisterSpec for DMA_OUT_DSCR_BF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_out_dscr_bf0::R`](R) reader structure"] +impl crate::Readable for DMA_OUT_DSCR_BF0_SPEC {} +#[doc = "`reset()` method sets DMA_OUT_DSCR_BF0 to value 0"] +impl crate::Resettable for DMA_OUT_DSCR_BF0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/in_err_eof_des_addr.rs b/esp32s2/src/crypto_dma/in_err_eof_des_addr.rs new file mode 100644 index 000000000..4864dd456 --- /dev/null +++ b/esp32s2/src/crypto_dma/in_err_eof_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the receive descriptor when there are some errors in this descriptor."] +pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the receive descriptor when there are some errors in this descriptor."] + #[inline(always)] + pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R { + IN_ERR_EOF_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR") + .field("in_err_eof_des_addr", &self.in_err_eof_des_addr()) + .finish() + } +} +#[doc = "Receive descriptor address when errors occur\n\nYou can [`read`](crate::Reg::read) this register and get [`in_err_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/in_link.rs b/esp32s2/src/crypto_dma/in_link.rs new file mode 100644 index 000000000..5b953839c --- /dev/null +++ b/esp32s2/src/crypto_dma/in_link.rs @@ -0,0 +1,150 @@ +#[doc = "Register `IN_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first receive descriptor’s address."] +pub type INLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first receive descriptor’s address."] +pub type INLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `INLINK_AUTO_RET` reader - Reserved"] +pub type INLINK_AUTO_RET_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET` writer - Reserved"] +pub type INLINK_AUTO_RET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP` reader - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] +pub type INLINK_STOP_R = crate::BitReader; +#[doc = "Field `INLINK_STOP` writer - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] +pub type INLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START` reader - Set this bit to enable DMA to read receive descriptors."] +pub type INLINK_START_R = crate::BitReader; +#[doc = "Field `INLINK_START` writer - Set this bit to enable DMA to read receive descriptors."] +pub type INLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new receive descriptor."] +pub type INLINK_RESTART_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new receive descriptor."] +pub type INLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum INLINK_PARK { + #[doc = "0: The receive descriptor’s FSM is working"] + Working = 0, + #[doc = "1: The receive descriptor’s FSM is in idle state"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: INLINK_PARK) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INLINK_PARK` reader - 1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working."] +pub type INLINK_PARK_R = crate::BitReader; +impl INLINK_PARK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> INLINK_PARK { + match self.bits { + false => INLINK_PARK::Working, + true => INLINK_PARK::Idle, + } + } + #[doc = "The receive descriptor’s FSM is working"] + #[inline(always)] + pub fn is_working(&self) -> bool { + *self == INLINK_PARK::Working + } + #[doc = "The receive descriptor’s FSM is in idle state"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == INLINK_PARK::Idle + } +} +impl R { + #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first receive descriptor’s address."] + #[inline(always)] + pub fn inlink_addr(&self) -> INLINK_ADDR_R { + INLINK_ADDR_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R { + INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn inlink_stop(&self) -> INLINK_STOP_R { + INLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to enable DMA to read receive descriptors."] + #[inline(always)] + pub fn inlink_start(&self) -> INLINK_START_R { + INLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to mount a new receive descriptor."] + #[inline(always)] + pub fn inlink_restart(&self) -> INLINK_RESTART_R { + INLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working."] + #[inline(always)] + pub fn inlink_park(&self) -> INLINK_PARK_R { + INLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK") + .field("inlink_addr", &self.inlink_addr()) + .field("inlink_auto_ret", &self.inlink_auto_ret()) + .field("inlink_stop", &self.inlink_stop()) + .field("inlink_start", &self.inlink_start()) + .field("inlink_restart", &self.inlink_restart()) + .field("inlink_park", &self.inlink_park()) + .finish() + } +} +impl W { + #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first receive descriptor’s address."] + #[inline(always)] + pub fn inlink_addr(&mut self) -> INLINK_ADDR_W { + INLINK_ADDR_W::new(self, 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W { + INLINK_AUTO_RET_W::new(self, 20) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn inlink_stop(&mut self) -> INLINK_STOP_W { + INLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to enable DMA to read receive descriptors."] + #[inline(always)] + pub fn inlink_start(&mut self) -> INLINK_START_W { + INLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to mount a new receive descriptor."] + #[inline(always)] + pub fn inlink_restart(&mut self) -> INLINK_RESTART_W { + INLINK_RESTART_W::new(self, 30) + } +} +#[doc = "Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_SPEC; +impl crate::RegisterSpec for IN_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link::R`](R) reader structure"] +impl crate::Readable for IN_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link::W`](W) writer structure"] +impl crate::Writable for IN_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IN_LINK to value 0x0010_0000"] +impl crate::Resettable for IN_LINK_SPEC { + const RESET_VALUE: u32 = 0x0010_0000; +} diff --git a/esp32s2/src/crypto_dma/in_status.rs b/esp32s2/src/crypto_dma/in_status.rs new file mode 100644 index 000000000..dd7778d23 --- /dev/null +++ b/esp32s2/src/crypto_dma/in_status.rs @@ -0,0 +1,38 @@ +#[doc = "Register `IN_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `IN_FULL` reader - DMA RX FIFO is full."] +pub type IN_FULL_R = crate::BitReader; +#[doc = "Field `IN_EMPTY` reader - DMA RX FIFO is empty."] +pub type IN_EMPTY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA RX FIFO is full."] + #[inline(always)] + pub fn in_full(&self) -> IN_FULL_R { + IN_FULL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA RX FIFO is empty."] + #[inline(always)] + pub fn in_empty(&self) -> IN_EMPTY_R { + IN_EMPTY_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATUS") + .field("in_full", &self.in_full()) + .field("in_empty", &self.in_empty()) + .finish() + } +} +#[doc = "RX FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`in_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATUS_SPEC; +impl crate::RegisterSpec for IN_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_status::R`](R) reader structure"] +impl crate::Readable for IN_STATUS_SPEC {} +#[doc = "`reset()` method sets IN_STATUS to value 0x02"] +impl crate::Resettable for IN_STATUS_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/esp32s2/src/crypto_dma/in_suc_eof_des_addr.rs b/esp32s2/src/crypto_dma/in_suc_eof_des_addr.rs new file mode 100644 index 000000000..cbd422e5c --- /dev/null +++ b/esp32s2/src/crypto_dma/in_suc_eof_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the receive descriptor when received successful EOF."] +pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the receive descriptor when received successful EOF."] + #[inline(always)] + pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R { + IN_SUC_EOF_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR") + .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr()) + .finish() + } +} +#[doc = "Receive descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/int_clr.rs b/esp32s2/src/crypto_dma/int_clr.rs new file mode 100644 index 000000000..441000186 --- /dev/null +++ b/esp32s2/src/crypto_dma/int_clr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE interrupt."] +pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF interrupt."] +pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE interrupt."] +pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF interrupt."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `INFIFO_FULL_WM` writer - Set this bit to clear the INFIFO_FULL_WM interrupt."] +pub type INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&mut self) -> IN_DONE_W { + IN_DONE_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W { + IN_SUC_EOF_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF interrupt."] + #[inline(always)] + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W { + IN_ERR_EOF_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&mut self) -> OUT_DONE_W { + OUT_DONE_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W { + IN_DSCR_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W { + OUT_DSCR_ERR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W { + IN_DSCR_EMPTY_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W { + OUT_TOTAL_EOF_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the INFIFO_FULL_WM interrupt."] + #[inline(always)] + pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W { + INFIFO_FULL_WM_W::new(self, 9) + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03ff; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/int_ena.rs b/esp32s2/src/crypto_dma/int_ena.rs new file mode 100644 index 000000000..741f6b59d --- /dev/null +++ b/esp32s2/src/crypto_dma/int_ena.rs @@ -0,0 +1,182 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE interrupt."] +pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF interrupt."] +pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE interrupt."] +pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF interrupt."] +pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_FULL_WM` reader - The interrupt enable bit for the INFIFO_FULL_WM interrupt."] +pub type INFIFO_FULL_WM_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_WM` writer - The interrupt enable bit for the INFIFO_FULL_WM interrupt."] +pub type INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF interrupt."] + #[inline(always)] + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_FULL_WM interrupt."] + #[inline(always)] + pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R { + INFIFO_FULL_WM_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("in_done", &self.in_done()) + .field("in_suc_eof", &self.in_suc_eof()) + .field("in_err_eof", &self.in_err_eof()) + .field("out_done", &self.out_done()) + .field("out_eof", &self.out_eof()) + .field("in_dscr_err", &self.in_dscr_err()) + .field("out_dscr_err", &self.out_dscr_err()) + .field("in_dscr_empty", &self.in_dscr_empty()) + .field("out_total_eof", &self.out_total_eof()) + .field("infifo_full_wm", &self.infifo_full_wm()) + .finish() + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&mut self) -> IN_DONE_W { + IN_DONE_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W { + IN_SUC_EOF_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF interrupt."] + #[inline(always)] + pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W { + IN_ERR_EOF_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&mut self) -> OUT_DONE_W { + OUT_DONE_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&mut self) -> OUT_EOF_W { + OUT_EOF_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W { + IN_DSCR_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W { + OUT_DSCR_ERR_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W { + IN_DSCR_EMPTY_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W { + OUT_TOTAL_EOF_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_FULL_WM interrupt."] + #[inline(always)] + pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W { + INFIFO_FULL_WM_W::new(self, 9) + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/int_raw.rs b/esp32s2/src/crypto_dma/int_raw.rs new file mode 100644 index 000000000..5c48984f4 --- /dev/null +++ b/esp32s2/src/crypto_dma/int_raw.rs @@ -0,0 +1,102 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE` reader - Set when the last data of one frame is received or the receive buffer is full indicated by receive descriptor."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - Set when the last data of one frame is received by Crypto DMA RX FIFO."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - Reserved"] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - Set when all data indicated by one transmit descriptor has been pushed into TX FIFO."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - Set when Out EOF flag is generated."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - Set when detecting receive descriptor error, including owner error, the second and third word error of receive descriptor."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - Set when detecting transmit descriptor error, including owner error, the second and third word error of transmit descriptor."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - Set when receiving data is completed and no more receive descriptor."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - Set when data corresponding to all transmit descriptor and the last descriptor with valid EOF is transmitted out."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_WM` reader - Set when received data byte number is up to threshold configured by CRYPTO_DMA_INFIFO_FULL_THRS in RX FIFO."] +pub type INFIFO_FULL_WM_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set when the last data of one frame is received or the receive buffer is full indicated by receive descriptor."] + #[inline(always)] + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set when the last data of one frame is received by Crypto DMA RX FIFO."] + #[inline(always)] + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set when all data indicated by one transmit descriptor has been pushed into TX FIFO."] + #[inline(always)] + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set when Out EOF flag is generated."] + #[inline(always)] + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set when detecting receive descriptor error, including owner error, the second and third word error of receive descriptor."] + #[inline(always)] + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set when detecting transmit descriptor error, including owner error, the second and third word error of transmit descriptor."] + #[inline(always)] + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set when receiving data is completed and no more receive descriptor."] + #[inline(always)] + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set when data corresponding to all transmit descriptor and the last descriptor with valid EOF is transmitted out."] + #[inline(always)] + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Set when received data byte number is up to threshold configured by CRYPTO_DMA_INFIFO_FULL_THRS in RX FIFO."] + #[inline(always)] + pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R { + INFIFO_FULL_WM_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field("in_done", &self.in_done()) + .field("in_suc_eof", &self.in_suc_eof()) + .field("in_err_eof", &self.in_err_eof()) + .field("out_done", &self.out_done()) + .field("out_eof", &self.out_eof()) + .field("in_dscr_err", &self.in_dscr_err()) + .field("out_dscr_err", &self.out_dscr_err()) + .field("in_dscr_empty", &self.in_dscr_empty()) + .field("out_total_eof", &self.out_total_eof()) + .field("infifo_full_wm", &self.infifo_full_wm()) + .finish() + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/int_st.rs b/esp32s2/src/crypto_dma/int_st.rs new file mode 100644 index 000000000..58a56e111 --- /dev/null +++ b/esp32s2/src/crypto_dma/int_st.rs @@ -0,0 +1,102 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE` reader - The masked interrupt status bit for the IN_DONE interrupt."] +pub type IN_DONE_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF` reader - The masked interrupt status bit for the IN_SUC_EOF interrupt."] +pub type IN_SUC_EOF_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF` reader - The masked interrupt status bit for the IN_ERR_EOF interrupt."] +pub type IN_ERR_EOF_R = crate::BitReader; +#[doc = "Field `OUT_DONE` reader - The masked interrupt status bit for the OUT_DONE interrupt."] +pub type OUT_DONE_R = crate::BitReader; +#[doc = "Field `OUT_EOF` reader - The masked interrupt status bit for the OUT_EOF interrupt."] +pub type OUT_EOF_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR` reader - The masked interrupt status bit for the IN_DSCR_ERR interrupt."] +pub type IN_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR` reader - The masked interrupt status bit for the OUT_DSCR_ERR interrupt."] +pub type OUT_DSCR_ERR_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY` reader - The masked interrupt status bit for the IN_DSCR_EMPTY interrupt."] +pub type IN_DSCR_EMPTY_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF` reader - The masked interrupt status bit for the OUT_TOTAL_EOF interrupt."] +pub type OUT_TOTAL_EOF_R = crate::BitReader; +#[doc = "Field `INFIFO_FULL_WM` reader - The masked interrupt status bit for the INFIFO_FULL_WM interrupt."] +pub type INFIFO_FULL_WM_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the IN_DONE interrupt."] + #[inline(always)] + pub fn in_done(&self) -> IN_DONE_R { + IN_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the IN_SUC_EOF interrupt."] + #[inline(always)] + pub fn in_suc_eof(&self) -> IN_SUC_EOF_R { + IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for the IN_ERR_EOF interrupt."] + #[inline(always)] + pub fn in_err_eof(&self) -> IN_ERR_EOF_R { + IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status bit for the OUT_DONE interrupt."] + #[inline(always)] + pub fn out_done(&self) -> OUT_DONE_R { + OUT_DONE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status bit for the OUT_EOF interrupt."] + #[inline(always)] + pub fn out_eof(&self) -> OUT_EOF_R { + OUT_EOF_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status bit for the IN_DSCR_ERR interrupt."] + #[inline(always)] + pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R { + IN_DSCR_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status bit for the OUT_DSCR_ERR interrupt."] + #[inline(always)] + pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R { + OUT_DSCR_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status bit for the IN_DSCR_EMPTY interrupt."] + #[inline(always)] + pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R { + IN_DSCR_EMPTY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status bit for the OUT_TOTAL_EOF interrupt."] + #[inline(always)] + pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R { + OUT_TOTAL_EOF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status bit for the INFIFO_FULL_WM interrupt."] + #[inline(always)] + pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R { + INFIFO_FULL_WM_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field("in_done", &self.in_done()) + .field("in_suc_eof", &self.in_suc_eof()) + .field("in_err_eof", &self.in_err_eof()) + .field("out_done", &self.out_done()) + .field("out_eof", &self.out_eof()) + .field("in_dscr_err", &self.in_dscr_err()) + .field("out_dscr_err", &self.out_dscr_err()) + .field("in_dscr_empty", &self.in_dscr_empty()) + .field("out_total_eof", &self.out_total_eof()) + .field("infifo_full_wm", &self.infifo_full_wm()) + .finish() + } +} +#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/out_eof_bfr_des_addr.rs b/esp32s2/src/crypto_dma/out_eof_bfr_des_addr.rs new file mode 100644 index 000000000..91c2b9a5c --- /dev/null +++ b/esp32s2/src/crypto_dma/out_eof_bfr_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `OUT_EOF_BFR_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the transmit descriptor before the last transmit descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the transmit descriptor before the last transmit descriptor."] + #[inline(always)] + pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R { + OUT_EOF_BFR_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_BFR_DES_ADDR") + .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr()) + .finish() + } +} +#[doc = "Transmit descriptor address before the last transmit descriptor\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_BFR_DES_ADDR_SPEC; +impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_bfr_des_addr::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_BFR_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_BFR_DES_ADDR to value 0"] +impl crate::Resettable for OUT_EOF_BFR_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/out_eof_des_addr.rs b/esp32s2/src/crypto_dma/out_eof_des_addr.rs new file mode 100644 index 000000000..70701391e --- /dev/null +++ b/esp32s2/src/crypto_dma/out_eof_des_addr.rs @@ -0,0 +1,30 @@ +#[doc = "Register `OUT_EOF_DES_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R { + OUT_EOF_DES_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR") + .field("out_eof_des_addr", &self.out_eof_des_addr()) + .finish() + } +} +#[doc = "Transmit descriptor address when EOF occurs\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/out_link.rs b/esp32s2/src/crypto_dma/out_link.rs new file mode 100644 index 000000000..14df08dc5 --- /dev/null +++ b/esp32s2/src/crypto_dma/out_link.rs @@ -0,0 +1,135 @@ +#[doc = "Register `OUT_LINK` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first transmit descriptor’s address."] +pub type OUTLINK_ADDR_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first transmit descriptor’s address."] +pub type OUTLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] +pub type OUTLINK_STOP_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] +pub type OUTLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START` reader - Set this bit to enable DMA to read transmit descriptors."] +pub type OUTLINK_START_R = crate::BitReader; +#[doc = "Field `OUTLINK_START` writer - Set this bit to enable DMA to read transmit descriptors."] +pub type OUTLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working.\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum OUTLINK_PARK { + #[doc = "0: The transmit descriptor’s FSM is working"] + Working = 0, + #[doc = "1: The transmit descriptor’s FSM is in idle state"] + Idle = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: OUTLINK_PARK) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OUTLINK_PARK` reader - 1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working."] +pub type OUTLINK_PARK_R = crate::BitReader; +impl OUTLINK_PARK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUTLINK_PARK { + match self.bits { + false => OUTLINK_PARK::Working, + true => OUTLINK_PARK::Idle, + } + } + #[doc = "The transmit descriptor’s FSM is working"] + #[inline(always)] + pub fn is_working(&self) -> bool { + *self == OUTLINK_PARK::Working + } + #[doc = "The transmit descriptor’s FSM is in idle state"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == OUTLINK_PARK::Idle + } +} +impl R { + #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first transmit descriptor’s address."] + #[inline(always)] + pub fn outlink_addr(&self) -> OUTLINK_ADDR_R { + OUTLINK_ADDR_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn outlink_stop(&self) -> OUTLINK_STOP_R { + OUTLINK_STOP_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to enable DMA to read transmit descriptors."] + #[inline(always)] + pub fn outlink_start(&self) -> OUTLINK_START_R { + OUTLINK_START_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart(&self) -> OUTLINK_RESTART_R { + OUTLINK_RESTART_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working."] + #[inline(always)] + pub fn outlink_park(&self) -> OUTLINK_PARK_R { + OUTLINK_PARK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK") + .field("outlink_addr", &self.outlink_addr()) + .field("outlink_stop", &self.outlink_stop()) + .field("outlink_start", &self.outlink_start()) + .field("outlink_restart", &self.outlink_restart()) + .field("outlink_park", &self.outlink_park()) + .finish() + } +} +impl W { + #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first transmit descriptor’s address."] + #[inline(always)] + pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W { + OUTLINK_ADDR_W::new(self, 0) + } + #[doc = "Bit 28 - Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction."] + #[inline(always)] + pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W { + OUTLINK_STOP_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to enable DMA to read transmit descriptors."] + #[inline(always)] + pub fn outlink_start(&mut self) -> OUTLINK_START_W { + OUTLINK_START_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W { + OUTLINK_RESTART_W::new(self, 30) + } +} +#[doc = "Link descriptor address and control\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_SPEC; +impl crate::RegisterSpec for OUT_LINK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OUT_LINK to value 0"] +impl crate::Resettable for OUT_LINK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/out_status.rs b/esp32s2/src/crypto_dma/out_status.rs new file mode 100644 index 000000000..7fff7f316 --- /dev/null +++ b/esp32s2/src/crypto_dma/out_status.rs @@ -0,0 +1,38 @@ +#[doc = "Register `OUT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_FULL` reader - DMA TX FIFO is full."] +pub type OUT_FULL_R = crate::BitReader; +#[doc = "Field `OUT_EMPTY` reader - DMA TX FIFO is empty."] +pub type OUT_EMPTY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA TX FIFO is full."] + #[inline(always)] + pub fn out_full(&self) -> OUT_FULL_R { + OUT_FULL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA TX FIFO is empty."] + #[inline(always)] + pub fn out_empty(&self) -> OUT_EMPTY_R { + OUT_EMPTY_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATUS") + .field("out_full", &self.out_full()) + .field("out_empty", &self.out_empty()) + .finish() + } +} +#[doc = "TX FIFO status register\n\nYou can [`read`](crate::Reg::read) this register and get [`out_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATUS_SPEC; +impl crate::RegisterSpec for OUT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_status::R`](R) reader structure"] +impl crate::Readable for OUT_STATUS_SPEC {} +#[doc = "`reset()` method sets OUT_STATUS to value 0x02"] +impl crate::Resettable for OUT_STATUS_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/esp32s2/src/crypto_dma/pd_conf.rs b/esp32s2/src/crypto_dma/pd_conf.rs new file mode 100644 index 000000000..f7382698e --- /dev/null +++ b/esp32s2/src/crypto_dma/pd_conf.rs @@ -0,0 +1,77 @@ +#[doc = "Register `PD_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `PD_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RAM_FORCE_PD` reader - Force power down signal to RAM. 0: force RAM power up; 1: only when CRYPTO_DMA_RAM_FORCE_PU is 0, power down RAM."] +pub type RAM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `RAM_FORCE_PD` writer - Force power down signal to RAM. 0: force RAM power up; 1: only when CRYPTO_DMA_RAM_FORCE_PU is 0, power down RAM."] +pub type RAM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM_FORCE_PU` reader - Force power up signal to RAM. 0: only when CRYPTO_DMA_RAM_FORCE_PD is 1, power down RAM; 1: force RAM power up."] +pub type RAM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `RAM_FORCE_PU` writer - Force power up signal to RAM. 0: only when CRYPTO_DMA_RAM_FORCE_PD is 1, power down RAM; 1: force RAM power up."] +pub type RAM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM_CLK_FO` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] +pub type RAM_CLK_FO_R = crate::BitReader; +#[doc = "Field `RAM_CLK_FO` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] +pub type RAM_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 4 - Force power down signal to RAM. 0: force RAM power up; 1: only when CRYPTO_DMA_RAM_FORCE_PU is 0, power down RAM."] + #[inline(always)] + pub fn ram_force_pd(&self) -> RAM_FORCE_PD_R { + RAM_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Force power up signal to RAM. 0: only when CRYPTO_DMA_RAM_FORCE_PD is 1, power down RAM; 1: force RAM power up."] + #[inline(always)] + pub fn ram_force_pu(&self) -> RAM_FORCE_PU_R { + RAM_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] + #[inline(always)] + pub fn ram_clk_fo(&self) -> RAM_CLK_FO_R { + RAM_CLK_FO_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PD_CONF") + .field("ram_force_pd", &self.ram_force_pd()) + .field("ram_force_pu", &self.ram_force_pu()) + .field("ram_clk_fo", &self.ram_clk_fo()) + .finish() + } +} +impl W { + #[doc = "Bit 4 - Force power down signal to RAM. 0: force RAM power up; 1: only when CRYPTO_DMA_RAM_FORCE_PU is 0, power down RAM."] + #[inline(always)] + pub fn ram_force_pd(&mut self) -> RAM_FORCE_PD_W { + RAM_FORCE_PD_W::new(self, 4) + } + #[doc = "Bit 5 - Force power up signal to RAM. 0: only when CRYPTO_DMA_RAM_FORCE_PD is 1, power down RAM; 1: force RAM power up."] + #[inline(always)] + pub fn ram_force_pu(&mut self) -> RAM_FORCE_PU_W { + RAM_FORCE_PU_W::new(self, 5) + } + #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] + #[inline(always)] + pub fn ram_clk_fo(&mut self) -> RAM_CLK_FO_W { + RAM_CLK_FO_W::new(self, 6) + } +} +#[doc = "Power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PD_CONF_SPEC; +impl crate::RegisterSpec for PD_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pd_conf::R`](R) reader structure"] +impl crate::Readable for PD_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pd_conf::W`](W) writer structure"] +impl crate::Writable for PD_CONF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PD_CONF to value 0x20"] +impl crate::Resettable for PD_CONF_SPEC { + const RESET_VALUE: u32 = 0x20; +} diff --git a/esp32s2/src/crypto_dma/state0.rs b/esp32s2/src/crypto_dma/state0.rs new file mode 100644 index 000000000..0ef569f14 --- /dev/null +++ b/esp32s2/src/crypto_dma/state0.rs @@ -0,0 +1,54 @@ +#[doc = "Register `STATE0` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current receive descriptor’s address."] +pub type INLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE` reader - Reserved"] +pub type IN_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `IN_STATE` reader - Reserved"] +pub type IN_STATE_R = crate::FieldReader; +#[doc = "Field `INFIFO_CNT_DEBUG` reader - This register stores the byte number of the data in the receive descriptor’s FIFO."] +pub type INFIFO_CNT_DEBUG_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current receive descriptor’s address."] + #[inline(always)] + pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R { + INLINK_DSCR_ADDR_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - Reserved"] + #[inline(always)] + pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R { + IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - Reserved"] + #[inline(always)] + pub fn in_state(&self) -> IN_STATE_R { + IN_STATE_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 23:26 - This register stores the byte number of the data in the receive descriptor’s FIFO."] + #[inline(always)] + pub fn infifo_cnt_debug(&self) -> INFIFO_CNT_DEBUG_R { + INFIFO_CNT_DEBUG_R::new(((self.bits >> 23) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE0") + .field("inlink_dscr_addr", &self.inlink_dscr_addr()) + .field("in_dscr_state", &self.in_dscr_state()) + .field("in_state", &self.in_state()) + .field("infifo_cnt_debug", &self.infifo_cnt_debug()) + .finish() + } +} +#[doc = "Status register of receiving data\n\nYou can [`read`](crate::Reg::read) this register and get [`state0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE0_SPEC; +impl crate::RegisterSpec for STATE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state0::R`](R) reader structure"] +impl crate::Readable for STATE0_SPEC {} +#[doc = "`reset()` method sets STATE0 to value 0"] +impl crate::Resettable for STATE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/crypto_dma/state1.rs b/esp32s2/src/crypto_dma/state1.rs new file mode 100644 index 000000000..6d2621bd2 --- /dev/null +++ b/esp32s2/src/crypto_dma/state1.rs @@ -0,0 +1,54 @@ +#[doc = "Register `STATE1` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current transmit descriptor’s address."] +pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE` reader - Reserved"] +pub type OUT_DSCR_STATE_R = crate::FieldReader; +#[doc = "Field `OUT_STATE` reader - Reserved"] +pub type OUT_STATE_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_CNT_DEBUG` reader - This register stores the byte number of the data in the transmit descriptor’s FIFO."] +pub type OUTFIFO_CNT_DEBUG_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current transmit descriptor’s address."] + #[inline(always)] + pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R { + OUTLINK_DSCR_ADDR_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - Reserved"] + #[inline(always)] + pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R { + OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - Reserved"] + #[inline(always)] + pub fn out_state(&self) -> OUT_STATE_R { + OUT_STATE_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 23:27 - This register stores the byte number of the data in the transmit descriptor’s FIFO."] + #[inline(always)] + pub fn outfifo_cnt_debug(&self) -> OUTFIFO_CNT_DEBUG_R { + OUTFIFO_CNT_DEBUG_R::new(((self.bits >> 23) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE1") + .field("outlink_dscr_addr", &self.outlink_dscr_addr()) + .field("out_dscr_state", &self.out_dscr_state()) + .field("out_state", &self.out_state()) + .field("outfifo_cnt_debug", &self.outfifo_cnt_debug()) + .finish() + } +} +#[doc = "Status register of transmitting data\n\nYou can [`read`](crate::Reg::read) this register and get [`state1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE1_SPEC; +impl crate::RegisterSpec for STATE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state1::R`](R) reader structure"] +impl crate::Readable for STATE1_SPEC {} +#[doc = "`reset()` method sets STATE1 to value 0"] +impl crate::Resettable for STATE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/esp32s2/src/lib.rs b/esp32s2/src/lib.rs index 90237c1fe..2195e05cd 100644 --- a/esp32s2/src/lib.rs +++ b/esp32s2/src/lib.rs @@ -2557,6 +2557,98 @@ impl core::fmt::Debug for XTS_AES { } #[doc = "XTS-AES-128 Flash Encryption"] pub mod xts_aes; +#[doc = "Copy DMA Controller"] +pub struct COPY_DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for COPY_DMA {} +impl COPY_DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const copy_dma::RegisterBlock = 0x3f4c_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const copy_dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for COPY_DMA { + type Target = copy_dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for COPY_DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COPY_DMA").finish() + } +} +#[doc = "Copy DMA Controller"] +pub mod copy_dma; +#[doc = "Crypto DMA Controller"] +pub struct CRYPTO_DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CRYPTO_DMA {} +impl CRYPTO_DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const crypto_dma::RegisterBlock = 0x6003_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const crypto_dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CRYPTO_DMA { + type Target = crypto_dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CRYPTO_DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CRYPTO_DMA").finish() + } +} +#[doc = "Crypto DMA Controller"] +pub mod crypto_dma; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -2648,6 +2740,10 @@ pub struct Peripherals { pub USB_WRAP: USB_WRAP, #[doc = "XTS_AES"] pub XTS_AES: XTS_AES, + #[doc = "COPY_DMA"] + pub COPY_DMA: COPY_DMA, + #[doc = "CRYPTO_DMA"] + pub CRYPTO_DMA: CRYPTO_DMA, } impl Peripherals { #[doc = r" Returns all the peripherals *once*."] @@ -2713,6 +2809,8 @@ impl Peripherals { USB0: USB0::steal(), USB_WRAP: USB_WRAP::steal(), XTS_AES: XTS_AES::steal(), + COPY_DMA: COPY_DMA::steal(), + CRYPTO_DMA: CRYPTO_DMA::steal(), } } } diff --git a/esp32s2/svd/patches/esp32s2.yaml b/esp32s2/svd/patches/esp32s2.yaml index 048901027..f034fbdcc 100644 --- a/esp32s2/svd/patches/esp32s2.yaml +++ b/esp32s2/svd/patches/esp32s2.yaml @@ -1,5 +1,1055 @@ _svd: ../esp32s2.base.svd +_add: + COPY_DMA: + description: Copy DMA Controller + baseAddress: 0x3F4C3000 + addressBlock: + - offset: 0x0 + size: 0x100 + usage: "Registers" + registers: + INT_RAW: + description: "Raw interrupt status" + addressOffset: 0x0 + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_DONE: + description: "Triggered when the last data of frame is received or the receive buffer is full indicated by receive descriptor." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "Triggered when the last data of one frame is received." + bitOffset: 1 + bitWidth: 1 + OUT_DONE: + description: "Triggered when all data indicated by one transmit descriptor has been pushed into TX FIFO." + bitOffset: 2 + bitWidth: 1 + OUT_EOF: + description: "Triggered when the last data with EOF flag has been pushed into TX FIFO." + bitOffset: 3 + bitWidth: 1 + IN_DSCR_ERR: + description: "Triggered when detecting receive descriptor error, including owner error, the second and third word error of receive descriptor." + bitOffset: 4 + bitWidth: 1 + OUT_DSCR_ERR: + description: "Triggered when detecting transmit descriptor error, including owner error, the second and third word error of transmit descriptor." + bitOffset: 5 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "Triggered when receiving data is completed and no more receive descriptor." + bitOffset: 6 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "Triggered when data corresponding to all transmit descriptors and the last descriptor with valid EOF is transmitted out." + bitOffset: 7 + bitWidth: 1 + + INT_ST: + description: "Masked interrupt status" + addressOffset: 0x4 + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_DONE: + description: "This is the masked interrupt bit for IN_DONE interrupt when IN_DONE is enabled." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "This is the masked interrupt bit for IN_SUC_EOF interrupt when IN_SUC_EOF is enabled." + bitOffset: 1 + bitWidth: 1 + OUT_DONE: + description: "This is the masked interrupt bit for OUT_DONE interrupt when OUT_DONE is enabled." + bitOffset: 2 + bitWidth: 1 + OUT_EOF: + description: "This is the masked interrupt bit for OUT_EOF interrupt when OUT_EOF is enabled." + bitOffset: 3 + bitWidth: 1 + IN_DSCR_ERR: + description: "This is the masked interrupt bit for IN_DSCR_ERR interrupt when IN_DSCR_ERR is enabled." + bitOffset: 4 + bitWidth: 1 + OUT_DSCR_ERR: + description: "This is the masked interrupt bit for OUT_DSCR_ERR interrupt when OUT_DSCR_ERR is enabled." + bitOffset: 5 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "This is the masked interrupt bit for IN_DSCR_EMPTY interrupt when IN_DSCR_EMPTY is enabled." + bitOffset: 6 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "This is the masked interrupt bit for OUT_TOTAL_EOF interrupt when OUT_TOTAL_EOF is enabled." + bitOffset: 7 + bitWidth: 1 + + INT_ENA: + description: "Interrupt enable bits" + addressOffset: 0x8 + size: 32 + access: read-write + resetValue: 0x0 + fields: + IN_DONE: + description: "This is the interrupt enable bit for IN_DONE interrupt." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "This is the interrupt enable bit for IN_SUC_EOF interrupt." + bitOffset: 1 + bitWidth: 1 + OUT_DONE: + description: "This is the interrupt enable bit for OUT_DONE interrupt." + bitOffset: 2 + bitWidth: 1 + OUT_EOF: + description: "This is the interrupt enable bit for OUT_EOF interrupt." + bitOffset: 3 + bitWidth: 1 + IN_DSCR_ERR: + description: "This is the interrupt enable bit for IN_DSCR_ERR interrupt." + bitOffset: 4 + bitWidth: 1 + OUT_DSCR_ERR: + description: "This is the interrupt enable bit for OUT_DSCR_ERR interrupt." + bitOffset: 5 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "This is the interrupt enable bit for IN_DSCR_EMPTY interrupt." + bitOffset: 6 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "This is the interrupt enable bit for OUT_TOTAL_EOF interrupt." + bitOffset: 7 + bitWidth: 1 + + INT_CLR: + description: "Interrupt clear bits" + addressOffset: 0xC + size: 32 + access: write-only + resetValue: 0x0 + fields: + IN_DONE: + description: "Set this bit to clear IN_DONE interrupt." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "Set this bit to clear IN_SUC_EOF interrupt." + bitOffset: 1 + bitWidth: 1 + OUT_DONE: + description: "Set this bit to clear OUT_DONE interrupt." + bitOffset: 2 + bitWidth: 1 + OUT_EOF: + description: "Set this bit to clear OUT_EOF interrupt." + bitOffset: 3 + bitWidth: 1 + IN_DSCR_ERR: + description: "Set this bit to clear IN_DSCR_ERR interrupt." + bitOffset: 4 + bitWidth: 1 + OUT_DSCR_ERR: + description: "Set this bit to clear OUT_DSCR_ERR interrupt." + bitOffset: 5 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "Set this bit to clear IN_DSCR_EMPTY interrupt." + bitOffset: 6 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "Set this bit to clear OUT_TOTAL_EOF interrupt." + bitOffset: 7 + bitWidth: 1 + + OUT_LINK: + description: "Link descriptor address and control" + addressOffset: 0x10 + size: 32 + access: read-write + resetValue: 0x0 + fields: + OUTLINK_ADDR: + description: "This register is used to specify the least significant 20 bits of the first transmit descriptor’s address." + bitOffset: 0 + bitWidth: 20 + OUTLINK_STOP: + description: "Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction." + bitOffset: 28 + bitWidth: 1 + OUTLINK_START: + description: "Set this bit to start a new transmit descriptor." + bitOffset: 29 + bitWidth: 1 + OUTLINK_RESTART: + description: "Set this bit to restart the transmit descriptor from the last address." + bitOffset: 30 + bitWidth: 1 + OUTLINK_PARK: + description: "1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working." + bitOffset: 31 + bitWidth: 1 + enumerateValues: + IDLE: [1, "The transmit descriptor’s FSM is in idle state"] + WORKING: [0, "The transmit descriptor’s FSM is working."] + + IN_LINK: + description: "Link descriptor address and control" + addressOffset: 0x14 + size: 32 + access: read-write + resetValue: 0x0 + fields: + INLINK_ADDR: + description: "This register is used to specify the least significant 20 bits of the first receive descriptor’s address." + bitOffset: 0 + bitWidth: 20 + INLINK_STOP: + description: "Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction." + bitOffset: 28 + bitWidth: 1 + INLINK_START: + description: "Set this bit to enable DMA to read receive descriptor." + bitOffset: 29 + bitWidth: 1 + INLINK_RESTART: + description: "Set this bit to restart new receive descriptors." + bitOffset: 30 + bitWidth: 1 + INLINK_PARK: + description: "1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working." + bitOffset: 31 + bitWidth: 1 + + CONF: + description: "Copy DMA configuration register" + addressOffset: 0x3C + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_RST: + description: "Set this bit to reset in DMA FSM." + bitOffset: 0 + bitWidth: 1 + OUT_RST: + description: "Set this bit to reset out DMA FSM." + bitOffset: 1 + bitWidth: 1 + CMDFIFO_RST: + description: "Set this bit to reset in_cmd FIFO and out_cmd FIFO." + bitOffset: 2 + bitWidth: 1 + FIFO_RST: + description: "Set this bit to reset data in RX FIFO." + bitOffset: 3 + bitWidth: 1 + OUT_OWNER: + description: "This is used to configure the owner bit in transmit descriptor. This is effective only when you set OUT_AUTO_WRBACK." + bitOffset: 4 + bitWidth: 1 + IN_OWNER: + description: "This is used to configure the owner bit in receive descriptor." + bitOffset: 5 + bitWidth: 1 + OUT_AUTO_WRBACK: + description: "This bit is used to write back out descriptor when hardware has already used this descriptor." + bitOffset: 6 + bitWidth: 1 + CHECK_OWNER: + description: "Set this bit to enable owner bit check in descriptor." + bitOffset: 7 + bitWidth: 1 + CLK_EN: + description: "1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers." + bitOffset: 31 + bitWidth: 1 + + OUT_EOF_DES_ADDR: + description: "Transmit descriptor address when EOF occurs" + addressOffset: 0x18 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUT_EOF_DES_ADDR: + description: "This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1." + bitOffset: 0 + bitWidth: 32 + + IN_EOF_DES_ADDR: + description: "Receive descriptor address when EOF occurs" + addressOffset: 0x1C + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_SUC_EOF_DES_ADDR: + description: "This register stores the address of the receive descriptor when received successful EOF." + bitOffset: 0 + bitWidth: 32 + + OUT_EOF_BFR_DES_ADDR: + description: "Transmit descriptor address before the last transmit descriptor" + addressOffset: 0x20 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUT_EOF_BFR_DES_ADDR: + description: "This register stores the address of the transmit descriptor before the last transmit descriptor." + bitOffset: 0 + bitWidth: 32 + + INLINK_DSCR: + description: "Address of current receive descriptor" + addressOffset: 0x24 + size: 32 + access: read-only + resetValue: 0x0 + fields: + INLINK_DSCR: + description: "The address of the current receive descriptor x." + bitOffset: 0 + bitWidth: 32 + + INLINK_DSCR_BF0: + description: "Address of last receive descriptor" + addressOffset: 0x28 + size: 32 + access: read-only + resetValue: 0x0 + fields: + INLINK_DSCR_BF0: + description: "The address of the last receive descriptor x-1." + bitOffset: 0 + bitWidth: 32 + + OUTLINK_DSCR: + description: "Address of current transmit descriptor" + addressOffset: 0x30 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUTLINK_DSCR: + description: "The address of the current transmit descriptor y." + bitOffset: 0 + bitWidth: 32 + + OUTLINK_DSCR_BF0: + description: "Address of last transmit descriptor" + addressOffset: 0x34 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUTLINK_DSCR_BF0: + description: "The address of the last transmit descriptor y-1." + bitOffset: 0 + bitWidth: 32 + + IN_ST: + description: "Status register of receiving data" + addressOffset: 0x40 + size: 32 + access: read-only + resetValue: 0x0 + fields: + INLINK_DSCR_ADDR: + description: "This register stores the current receive descriptor’s address." + bitOffset: 0 + bitWidth: 18 + IN_DSCR_STATE: + description: "Reserved" + bitOffset: 18 + bitWidth: 2 + IN_STATE: + description: "Reserved" + bitOffset: 20 + bitWidth: 3 + FIFO_EMPTY: + description: "Copy DMA FIFO empty signal." + bitOffset: 23 + bitWidth: 1 + + OUT_ST: + description: "Status register of transmitting data" + addressOffset: 0x44 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUTLINK_DSCR_ADDR: + description: "This register stores the current transmit descriptor’s address." + bitOffset: 0 + bitWidth: 18 + OUT_DSCR_STATE: + description: "Reserved" + bitOffset: 18 + bitWidth: 2 + OUT_STATE: + description: "Reserved" + bitOffset: 20 + bitWidth: 3 + FIFO_FULL: + description: "Copy DMA FIFO full signal." + bitOffset: 23 + bitWidth: 1 + + DATE: + description: "Copy DMA version control register" + addressOffset: 0xFC + size: 32 + access: read-write + resetValue: 0x18082000 + fields: + DMA_DATE: + description: "This is the version control register." + bitOffset: 0 + bitWidth: 32 + + CRYPTO_DMA: + description: Crypto DMA Controller + baseAddress: 0x6003f000 + addressBlock: + - offset: 0x0 + size: 0x60 + usage: "Registers" + registers: + CONF: + description: "DMA configuration register" + addressOffset: 0x0 + size: 32 + access: read-write + resetValue: 0x0100 + fields: + IN_RST: + description: "This bit is used to reset crypto DMA in FSM and RX FIFO pointer." + bitOffset: 0 + bitWidth: 1 + OUT_RST: + description: "This bit is used to reset crypto DMA out FSM and TX FIFO pointer." + bitOffset: 1 + bitWidth: 1 + AHBM_FIFO_RST: + description: "This bit is used to reset crypto DMA AHB master FIFO pointer." + bitOffset: 2 + bitWidth: 1 + AHBM_RST: + description: "Reset crypto DMA AHB master." + bitOffset: 3 + bitWidth: 1 + IN_LOOP_TEST: + description: "Reserved" + bitOffset: 4 + bitWidth: 1 + OUT_LOOP_TEST: + description: "Reserved" + bitOffset: 5 + bitWidth: 1 + OUT_AUTO_WRBACK: + description: "Set this bit to enable automatic outlink-writeback when all the data in TX Buffer has been transmitted." + bitOffset: 6 + bitWidth: 1 + OUT_NO_RESTART_CLR: + description: "Reserved" + bitOffset: 7 + bitWidth: 1 + OUT_EOF_MODE: + description: "Out EOF flag generation mode of TX FIFO. 1: EOF flag of TX is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA; 0: EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA." + bitOffset: 8 + bitWidth: 1 + OUTDSCR_BURST_EN: + description: "Set this bit to enable INCR burst transfer when TX FIFO reads descriptor from internal RAM." + bitOffset: 9 + bitWidth: 1 + INDSCR_BURST_EN: + description: "Set this bit to enable INCR burst transfer when RX FIFO reads descriptor from internal RAM." + bitOffset: 10 + bitWidth: 1 + OUT_DATA_BURST_EN: + description: "Set this bit to enable INCR burst transfer when TX FIFO reads data from internal RAM." + bitOffset: 11 + bitWidth: 1 + MEM_TRANS_EN: + description: "Set this bit to enable automatic transmitting data from memory to memory via DMA." + bitOffset: 12 + bitWidth: 1 + + OUT_LINK: + description: "Link descriptor address and control" + addressOffset: 0x24 + size: 32 + access: read-write + resetValue: 0x0 + fields: + OUTLINK_ADDR: + description: "This register stores the 20 least significant bits of the first transmit descriptor’s address." + bitOffset: 0 + bitWidth: 20 + OUTLINK_STOP: + description: "Set this bit to stop DMA from reading transmit descriptors after finishing the current data transaction." + bitOffset: 28 + bitWidth: 1 + OUTLINK_START: + description: "Set this bit to enable DMA to read transmit descriptors." + bitOffset: 29 + bitWidth: 1 + OUTLINK_RESTART: + description: "Set this bit to restart a new outlink from the last address." + bitOffset: 30 + bitWidth: 1 + OUTLINK_PARK: + description: "1: the transmit descriptor’s FSM is in idle state. 0: the transmit descriptor’s FSM is working." + bitOffset: 31 + bitWidth: 1 + access: read-only + + IN_LINK: + description: "Link descriptor address and control" + addressOffset: 0x28 + size: 32 + access: read-write + resetValue: 0x100000 + fields: + INLINK_ADDR: + description: "This register stores the 20 least significant bits of the first receive descriptor’s address." + bitOffset: 0 + bitWidth: 20 + INLINK_AUTO_RET: + description: "Reserved" + bitOffset: 20 + bitWidth: 1 + INLINK_STOP: + description: "Set this bit to stop DMA from reading receive descriptors after finishing the current data transaction." + bitOffset: 28 + bitWidth: 1 + INLINK_START: + description: "Set this bit to enable DMA to read receive descriptors." + bitOffset: 29 + bitWidth: 1 + INLINK_RESTART: + description: "Set this bit to mount a new receive descriptor." + bitOffset: 30 + bitWidth: 1 + INLINK_PARK: + description: "1: the receive descriptor’s FSM is in idle state. 0: the receive descriptor’s FSM is working." + bitOffset: 31 + bitWidth: 1 + access: read-only + + CONF1: + description: "DMA configuration register" + addressOffset: 0x2C + size: 32 + access: read-write + resetValue: 0x0 + fields: + INFIFO_FULL_THRS: + description: "This register is used to generate the CRYPTO_DMA_INFIFO_FULL_WM_INT interrupt when the byte number is up to the value of the register." + bitOffset: 0 + bitWidth: 12 + CHECK_OWNER: + description: "Set this bit to enable checking the owner attribute of the link descriptor." + bitOffset: 12 + bitWidth: 1 + EXT_MEM_BK_SIZE: + description: "DMA access external memory block size. 0: 16 bytes; 1: 32 bytes; 2: 64 bytes; 3:Reserved." + bitOffset: 13 + bitWidth: 2 + + AHB_TEST: + description: "AHB test register" + addressOffset: 0x48 + size: 32 + access: read-write + resetValue: 0x0 + fields: + AHB_TESTMODE: + description: "Reserved" + bitOffset: 0 + bitWidth: 3 + AHB_TESTADDR: + description: "Reserved" + bitOffset: 4 + bitWidth: 2 + + AES_SHA_SELECT: + description: "AES/SHA select register" + addressOffset: 0x64 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SELECT: + description: "Select one between AES and SHA to use DMA. 0: AES. 1: SHA." + bitOffset: 0 + bitWidth: 1 + + PD_CONF: + description: "Power control register" + addressOffset: 0x68 + size: 32 + access: read-write + resetValue: 0x20 + fields: + RAM_FORCE_PD: + description: "Force power down signal to RAM. 0: force RAM power up; 1: only when CRYPTO_DMA_RAM_FORCE_PU is 0, power down RAM." + bitOffset: 4 + bitWidth: 1 + RAM_FORCE_PU: + description: "Force power up signal to RAM. 0: only when CRYPTO_DMA_RAM_FORCE_PD is 1, power down RAM; 1: force RAM power up." + bitOffset: 5 + bitWidth: 1 + RAM_CLK_FO: + description: "1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA." + bitOffset: 6 + bitWidth: 1 + + DATE: + description: "Crypto DMA version control register" + addressOffset: 0xFC + size: 32 + access: read-write + resetValue: 0x19050700 + fields: + DATE: + description: "This is the version control register." + bitOffset: 0 + bitWidth: 32 + + INT_RAW: + description: "Raw interrupt status" + addressOffset: 0x04 + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_DONE: + description: "Set when the last data of one frame is received or the receive buffer is full indicated by receive descriptor." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: " Set when the last data of one frame is received by Crypto DMA RX FIFO." + bitOffset: 1 + bitWidth: 1 + IN_ERR_EOF: + description: "Reserved" + bitOffset: 2 + bitWidth: 1 + OUT_DONE: + description: "Set when all data indicated by one transmit descriptor has been pushed into TX FIFO." + bitOffset: 3 + bitWidth: 1 + OUT_EOF: + description: "Set when Out EOF flag is generated." + bitOffset: 4 + bitWidth: 1 + IN_DSCR_ERR: + description: "Set when detecting receive descriptor error, including owner error, the second and third word error of receive descriptor." + bitOffset: 5 + bitWidth: 1 + OUT_DSCR_ERR: + description: "Set when detecting transmit descriptor error, including owner error, the second and third word error of transmit descriptor." + bitOffset: 6 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "Set when receiving data is completed and no more receive descriptor." + bitOffset: 7 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "Set when data corresponding to all transmit descriptor and the last descriptor with valid EOF is transmitted out." + bitOffset: 8 + bitWidth: 1 + INFIFO_FULL_WM: + description: "Set when received data byte number is up to threshold configured by CRYPTO_DMA_INFIFO_FULL_THRS in RX FIFO." + bitOffset: 9 + bitWidth: 1 + + INT_ST: + description: "Masked interrupt status" + addressOffset: 0x08 + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_DONE: + description: "The masked interrupt status bit for the IN_DONE interrupt." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "The masked interrupt status bit for the IN_SUC_EOF interrupt." + bitOffset: 1 + bitWidth: 1 + IN_ERR_EOF: + description: "The masked interrupt status bit for the IN_ERR_EOF interrupt." + bitOffset: 2 + bitWidth: 1 + OUT_DONE: + description: "The masked interrupt status bit for the OUT_DONE interrupt." + bitOffset: 3 + bitWidth: 1 + OUT_EOF: + description: "The masked interrupt status bit for the OUT_EOF interrupt." + bitOffset: 4 + bitWidth: 1 + IN_DSCR_ERR: + description: "The masked interrupt status bit for the IN_DSCR_ERR interrupt." + bitOffset: 5 + bitWidth: 1 + OUT_DSCR_ERR: + description: "The masked interrupt status bit for the OUT_DSCR_ERR interrupt." + bitOffset: 6 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "The masked interrupt status bit for the IN_DSCR_EMPTY interrupt." + bitOffset: 7 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "The masked interrupt status bit for the OUT_TOTAL_EOF interrupt." + bitOffset: 8 + bitWidth: 1 + INFIFO_FULL_WM: + description: "The masked interrupt status bit for the INFIFO_FULL_WM interrupt." + bitOffset: 9 + bitWidth: 1 + + INT_ENA: + description: "Interrupt enable bits" + addressOffset: 0x0C + size: 32 + access: read-write + resetValue: 0x0 + fields: + IN_DONE: + description: "The interrupt enable bit for the IN_DONE interrupt." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "The interrupt enable bit for the IN_SUC_EOF interrupt." + bitOffset: 1 + bitWidth: 1 + IN_ERR_EOF: + description: "The interrupt enable bit for the IN_ERR_EOF interrupt." + bitOffset: 2 + bitWidth: 1 + OUT_DONE: + description: "The interrupt enable bit for the OUT_DONE interrupt." + bitOffset: 3 + bitWidth: 1 + OUT_EOF: + description: "The interrupt enable bit for the OUT_EOF interrupt." + bitOffset: 4 + bitWidth: 1 + IN_DSCR_ERR: + description: "The interrupt enable bit for the IN_DSCR_ERR interrupt." + bitOffset: 5 + bitWidth: 1 + OUT_DSCR_ERR: + description: "The interrupt enable bit for the OUT_DSCR_ERR interrupt." + bitOffset: 6 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "The interrupt enable bit for the IN_DSCR_EMPTY interrupt." + bitOffset: 7 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "The interrupt enable bit for the OUT_TOTAL_EOF interrupt." + bitOffset: 8 + bitWidth: 1 + INFIFO_FULL_WM: + description: "The interrupt enable bit for the INFIFO_FULL_WM interrupt." + bitOffset: 9 + bitWidth: 1 + + INT_CLR: + description: "Interrupt clear bits" + addressOffset: 0x10 + size: 32 + access: write-only + resetValue: 0x0 + fields: + IN_DONE: + description: "Set this bit to clear the IN_DONE interrupt." + bitOffset: 0 + bitWidth: 1 + IN_SUC_EOF: + description: "Set this bit to clear the IN_SUC_EOF interrupt." + bitOffset: 1 + bitWidth: 1 + IN_ERR_EOF: + description: "Set this bit to clear the IN_ERR_EOF interrupt." + bitOffset: 2 + bitWidth: 1 + OUT_DONE: + description: "Set this bit to clear the OUT_DONE interrupt." + bitOffset: 3 + bitWidth: 1 + OUT_EOF: + description: "Set this bit to clear the OUT_EOF interrupt." + bitOffset: 4 + bitWidth: 1 + IN_DSCR_ERR: + description: "Set this bit to clear the IN_DSCR_ERR interrupt." + bitOffset: 5 + bitWidth: 1 + OUT_DSCR_ERR: + description: "Set this bit to clear the OUT_DSCR_ERR interrupt." + bitOffset: 6 + bitWidth: 1 + IN_DSCR_EMPTY: + description: "Set this bit to clear the IN_DSCR_EMPTY interrupt." + bitOffset: 7 + bitWidth: 1 + OUT_TOTAL_EOF: + description: "Set this bit to clear the OUT_TOTAL_EOF interrupt." + bitOffset: 8 + bitWidth: 1 + INFIFO_FULL_WM: + description: "Set this bit to clear the INFIFO_FULL_WM interrupt." + bitOffset: 9 + bitWidth: 1 + + OUT_STATUS: + description: "TX FIFO status register" + addressOffset: 0x14 + size: 32 + access: read-only + resetValue: 0x02 + fields: + OUT_FULL: + description: "DMA TX FIFO is full." + bitOffset: 0 + bitWidth: 1 + OUT_EMPTY: + description: "DMA TX FIFO is empty." + bitOffset: 1 + bitWidth: 1 + + IN_STATUS: + description: "RX FIFO status register" + addressOffset: 0x1C + size: 32 + access: read-only + resetValue: 0x02 + fields: + IN_FULL: + description: "DMA RX FIFO is full." + bitOffset: 0 + bitWidth: 1 + IN_EMPTY: + description: "DMA RX FIFO is empty." + bitOffset: 1 + bitWidth: 1 + + STATE0: + description: "Status register of receiving data" + addressOffset: 0x30 + size: 32 + access: read-only + resetValue: 0x0 + fields: + INLINK_DSCR_ADDR: + description: "This register stores the current receive descriptor’s address." + bitOffset: 0 + bitWidth: 18 + IN_DSCR_STATE: + description: "Reserved" + bitOffset: 18 + bitWidth: 2 + IN_STATE: + description: "Reserved" + bitOffset: 20 + bitWidth: 3 + INFIFO_CNT_DEBUG: + description: "This register stores the byte number of the data in the receive descriptor’s FIFO." + bitOffset: 23 + bitWidth: 4 + + STATE1: + description: "Status register of transmitting data" + addressOffset: 0x34 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUTLINK_DSCR_ADDR: + description: "This register stores the current transmit descriptor’s address." + bitOffset: 0 + bitWidth: 18 + OUT_DSCR_STATE: + description: "Reserved" + bitOffset: 18 + bitWidth: 2 + OUT_STATE: + description: "Reserved" + bitOffset: 20 + bitWidth: 3 + OUTFIFO_CNT_DEBUG: + description: "This register stores the byte number of the data in the transmit descriptor’s FIFO." + bitOffset: 23 + bitWidth: 5 + + OUT_EOF_DES_ADDR: + description: "Transmit descriptor address when EOF occurs" + addressOffset: 0x38 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUT_EOF_DES_ADDR: + description: "This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1." + bitOffset: 0 + bitWidth: 32 + access: read-only + + IN_SUC_EOF_DES_ADDR: + description: "Receive descriptor address when EOF occurs" + addressOffset: 0x3C + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_SUC_EOF_DES_ADDR: + description: "This register stores the address of the receive descriptor when received successful EOF." + bitOffset: 0 + bitWidth: 32 + access: read-only + + IN_ERR_EOF_DES_ADDR: + description: "Receive descriptor address when errors occur" + addressOffset: 0x40 + size: 32 + access: read-only + resetValue: 0x0 + fields: + IN_ERR_EOF_DES_ADDR: + description: "This register stores the address of the receive descriptor when there are some errors in this descriptor." + bitOffset: 0 + bitWidth: 32 + access: read-only + + OUT_EOF_BFR_DES_ADDR: + description: "Transmit descriptor address before the last transmit descriptor" + addressOffset: 0x44 + size: 32 + access: read-only + resetValue: 0x0 + fields: + OUT_EOF_BFR_DES_ADDR: + description: "This register stores the address of the transmit descriptor before the last transmit descriptor." + bitOffset: 0 + bitWidth: 32 + access: read-only + + DMA_IN_DSCR: + description: "Address of current receive descriptor" + addressOffset: 0x4C + size: 32 + access: read-only + resetValue: 0x0 + fields: + DMA_IN_DSCR: + description: "Address of the current receive descriptor x." + bitOffset: 0 + bitWidth: 32 + access: read-only + + DMA_IN_DSCR_BF0: + description: "Address of last receive descriptor" + addressOffset: 0x50 + size: 32 + access: read-only + resetValue: 0x0 + fields: + DMA_IN_DSCR_BF0: + description: "Address of the last receive descriptor x-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + + DMA_OUT_DSCR: + description: "Address of current transmit descriptor" + addressOffset: 0x58 + size: 32 + access: read-only + resetValue: 0x0 + fields: + DMA_OUT_DSCR: + description: "Address of the current transmit descriptor y." + bitOffset: 0 + bitWidth: 32 + access: read-only + + + DMA_OUT_DSCR_BF0: + description: "Address of last transmit descriptor" + addressOffset: 0x5C + size: 32 + access: read-only + resetValue: 0x0 + fields: + DMA_OUT_DSCR_BF0: + description: "Address of the last transmit descriptor y-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + +# We need to define enumeratedValues separately, becase svdtools has awesome UX. +COPY_DMA: + OUT_LINK: + OUTLINK_PARK: + IDLE: [1, "The transmit descriptor’s FSM is in idle state"] + WORKING: [0, "The transmit descriptor’s FSM is working."] + IN_LINK: + INLINK_PARK: + IDLE: [1, "The receive descriptor’s FSM is in idle state"] + WORKING: [0, "The receive descriptor’s FSM is working."] + CONF: + CLK_EN: + FORCE: [1, "Force clock on for register"] + ON_WRITE: [0, "Support clock only when application writes registers"] + INT_CLR: + _modify: + "*": + modifiedWriteValues: oneToClear + +# We need to define enumeratedValues separately. +CRYPTO_DMA: + CONF: + OUT_EOF_MODE: + ON_PUSH: [0, "EOF flag is generated when the last data with EOF would be transmitted has been pushed into FIFO of Crypto DMA"] + ON_POP: [1, "EOF flag is generated when the last data with EOF would be transmitted has been popped from FIFO of Crypto DMA"] + OUT_LINK: + OUTLINK_PARK: + IDLE: [1, "The transmit descriptor’s FSM is in idle state"] + WORKING: [0, "The transmit descriptor’s FSM is working"] + IN_LINK: + INLINK_PARK: + IDLE: [1, "The receive descriptor’s FSM is in idle state"] + WORKING: [0, "The receive descriptor’s FSM is working"] + CONF1: + EXT_MEM_BK_SIZE: + SIZE_16: [0, "DMA access external memory block size is 16 bytes"] + SIZE_32: [1, "DMA access external memory block size is 32 bytes"] + SIZE_64: [2, "DMA access external memory block size is 64 bytes"] + AES_SHA_SELECT: + SELECT: + AES: [0, "The AES peripheral uses the Crypto DMA"] + SHA: [1, "The SHA peripheral uses the Crypto DMA"] + INT_CLR: + _modify: + "*": + modifiedWriteValues: oneToClear + AES: _modify: IV_%s: