diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 0bd57503d10103..884c4d2d21eb32 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -183,6 +183,17 @@ def FeatureHIFI3            : SubtargetFeature<"hifi3", "HasHIFI3", "true",
 def HasHIFI3                : Predicate<"Subtarget->hasHIFI3()">,
                                          AssemblerPredicate<(all_of FeatureHIFI3)>;
 
+// Assume that lock-free native-width atomics are available, even if the target
+// and operating system combination would not usually provide them. The user
+// is responsible for providing any necessary __sync implementations. Code
+// built with this feature is not ABI-compatible with code built without this
+// feature, if atomic variables are exposed across the ABI boundary.
+def FeatureForcedAtomics    : SubtargetFeature<"forced-atomics", "HasForcedAtomics", "true",
+                                              "Assume that lock-free native-width atomics are available">;
+def HasForcedAtomics        : Predicate<"Subtarget->hasForcedAtomics()">,
+                                         AssemblerPredicate<(all_of FeatureForcedAtomics)>;
+def HasAtomicLdSt           : Predicate<"Subtarget->hasS32C1I() || Subtarget->hasForcedAtomics()">;
+
 //===----------------------------------------------------------------------===//
 // Xtensa supported processors.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 1a865b988f3386..e6c1a6b2fe6f0f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -440,6 +440,8 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
   if (Subtarget.hasS32C1I()) {
     setMaxAtomicSizeInBitsSupported(32);
     setMinCmpXchgSizeInBits(32);
+  } else if (Subtarget.hasForcedAtomics()) {
+    setMaxAtomicSizeInBitsSupported(32);
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index cb0986fac161ab..4e149fb8fc0c85 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1841,13 +1841,18 @@ def SIMCALL : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
 // Atomic patterns
 //===----------------------------------------------------------------------===//
 
-def : Pat<(i32 (atomic_load_8  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
-def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
-def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>;
-
-def : Pat<(atomic_store_8  AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>;
-def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>;
-def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>;
+// Atomic load/store are available under both +s32c1i and +force-atomics.
+// Fences will be inserted for atomic load/stores according to the logic in
+// XtensaTargetLowering.
+let Predicates = [HasAtomicLdSt] in {
+  def : Pat<(i32 (atomic_load_8  addr_ish1:$addr)), (L8UI addr_ish1:$addr)>;
+  def : Pat<(i32 (atomic_load_16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>;
+  def : Pat<(i32 (atomic_load_32 addr_ish4:$addr)), (L32I addr_ish4:$addr)>;
+
+  def : Pat<(atomic_store_8  AR:$t, addr_ish1:$addr), (S8I AR:$t, addr_ish1:$addr)>;
+  def : Pat<(atomic_store_16 AR:$t, addr_ish2:$addr), (S16I AR:$t, addr_ish2:$addr)>;
+  def : Pat<(atomic_store_32 AR:$t, addr_ish4:$addr), (S32I AR:$t, addr_ish4:$addr)>;
+}
 
 let usesCustomInserter = 1, Predicates = [HasS32C1I] in {
   def ATOMIC_CMP_SWAP_8_P : Pseudo<(outs AR:$dst), (ins AR:$ptr, AR:$cmp, AR:$swap),
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
index e5639ce706c864..6dcee8b5cbcf8f 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -78,6 +78,8 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   HasESP32S2Ops = false;
   HasESP32S3Ops = false;
   HasHIFI3 = false;
+  HasForcedAtomics = false;
+  HasAtomicLdSt = false;
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, CPUName, FS);
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index e794edec3f5c5a..a4672f1e2b7878 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -137,6 +137,13 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
   // Enable Xtensa HIFI3 Extension
   bool HasHIFI3;
 
+  // Enable 'forced-atomics' feature
+  bool HasForcedAtomics;
+
+  // Enable atomic load and stores ops
+  bool HasAtomicLdSt;
+
+
   XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
 public:
@@ -222,6 +229,10 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
 
   bool hasHIFI3() const { return HasHIFI3; }
 
+  bool hasForcedAtomics() const { return HasForcedAtomics; }
+
+  bool hasAtomicLdSt() const { return HasAtomicLdSt; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 };
diff --git a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll
index 8047fd2914d219..948f3a65501948 100644
--- a/llvm/test/CodeGen/Xtensa/atomic-load-store.ll
+++ b/llvm/test/CodeGen/Xtensa/atomic-load-store.ll
@@ -1,107 +1,450 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA,XTENSA_OPT
-; RUN: llc -mtriple=xtensa -O0 < %s | FileCheck %s --check-prefixes=XTENSA,XTENSA_OPT_NONE
+; RUN: llc -mtriple=xtensa -mcpu=esp32s2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA
+; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC
 
-define void @store32(ptr %ptr, i32 %val1) {
-; XTENSA-LABEL: store32:
+define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i8_unordered:
 ; XTENSA:         entry a1, 32
-; XTENSA-NEXT:    memw
-; XTENSA-NEXT:    s32i.n a3, a2, 0
-; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI0_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
 ; XTENSA-NEXT:    retw.n
-  store atomic i32 %val1, ptr %ptr seq_cst, align 4
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i8_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l8ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i8, ptr %a unordered, align 1
+  ret i8 %1
+}
+
+define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI1_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l8ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i8, ptr %a monotonic, align 1
+  ret i8 %1
+}
+
+define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 2
+; XTENSA-NEXT:    l32r a8, .LCPI2_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l8ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i8, ptr %a acquire, align 1
+  ret i8 %1
+}
+
+define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 5
+; XTENSA-NEXT:    l32r a8, .LCPI3_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l8ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i8, ptr %a seq_cst, align 1
+  ret i8 %1
+}
+
+define i16 @atomic_load_i16_unordered(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i16_unordered:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI4_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i16_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l16ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i16, ptr %a unordered, align 2
+  ret i16 %1
+}
+
+define i16 @atomic_load_i16_monotonic(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI5_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l16ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i16, ptr %a monotonic, align 2
+  ret i16 %1
+}
+
+define i16 @atomic_load_i16_acquire(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 2
+; XTENSA-NEXT:    l32r a8, .LCPI6_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l16ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i16, ptr %a acquire, align 2
+  ret i16 %1
+}
+
+define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 5
+; XTENSA-NEXT:    l32r a8, .LCPI7_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l16ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i16, ptr %a seq_cst, align 2
+  ret i16 %1
+}
+
+define i32 @atomic_load_i32_unordered(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i32_unordered:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI8_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i32_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i32, ptr %a unordered, align 4
+  ret i32 %1
+}
+
+define i32 @atomic_load_i32_monotonic(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI9_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i32, ptr %a monotonic, align 4
+  ret i32 %1
+}
+
+define i32 @atomic_load_i32_acquire(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 2
+; XTENSA-NEXT:    l32r a8, .LCPI10_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i32, ptr %a acquire, align 4
+  ret i32 %1
+}
+
+define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind {
+; XTENSA-LABEL: atomic_load_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 5
+; XTENSA-NEXT:    l32r a8, .LCPI11_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_load_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = load atomic i32, ptr %a seq_cst, align 4
+  ret i32 %1
+}
+
+define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i8_unordered:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI12_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i8_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    s8i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i8 %b, ptr %a unordered, align 1
+  ret void
+}
+
+define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI13_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    s8i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i8 %b, ptr %a monotonic, align 1
+  ret void
+}
+
+define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI14_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    s8i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i8 %b, ptr %a release, align 1
   ret void
 }
 
-define i32 @load32(ptr %ptr) {
-; XTENSA-LABEL: load32:
+define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i8_seq_cst:
 ; XTENSA:         entry a1, 32
-; XTENSA-NEXT:    l32i.n a2, a2, 0
-; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI15_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
 ; XTENSA-NEXT:    retw.n
-  %val = load atomic i32, ptr %ptr seq_cst, align 4
-  ret i32 %val
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    s8i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i8 %b, ptr %a seq_cst, align 1
+  ret void
+}
+
+define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i16_unordered:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI16_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i16_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    s16i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i16 %b, ptr %a unordered, align 2
+  ret void
+}
+
+define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI17_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    s16i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i16 %b, ptr %a monotonic, align 2
+  ret void
 }
 
-define i8 @load8(ptr %p) {
-; XTENSA-LABEL: load8:
+define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i16_release:
 ; XTENSA:         entry a1, 32
-; XTENSA-NEXT:    l8ui a2, a2, 0
-; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI18_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
 ; XTENSA-NEXT:    retw.n
-  %v = load atomic i8, ptr %p seq_cst, align 1
-  ret i8 %v
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    s16i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i16 %b, ptr %a release, align 2
+  ret void
 }
 
-define void @store8(ptr %p, i8 %val1) {
-; XTENSA_OPT-LABEL: store8:
-; XTENSA_OPT:         entry a1, 32
-; XTENSA_OPT-NEXT:    memw
-; XTENSA_OPT-NEXT:    s8i a3, a2, 0
-; XTENSA_OPT-NEXT:    memw
-; XTENSA_OPT-NEXT:    retw.n
+define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI19_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
 ;
-; XTENSA_OPT_NONE-LABEL: store8:
-; XTENSA_OPT_NONE:         entry a1, 32
-; XTENSA_OPT_NONE-NEXT:    # kill: def $a8 killed $a3
-; XTENSA_OPT_NONE-NEXT:    memw
-; XTENSA_OPT_NONE-NEXT:    s8i a3, a2, 0
-; XTENSA_OPT_NONE-NEXT:    memw
-; XTENSA_OPT_NONE-NEXT:    retw.n
-  store atomic i8 %val1, ptr %p seq_cst, align 1
+; XTENSA-ATOMIC-LABEL: atomic_store_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    s16i a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i16 %b, ptr %a seq_cst, align 2
   ret void
 }
 
-define i16 @load16(ptr %p) {
-; XTENSA-LABEL: load16:
+define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i32_unordered:
 ; XTENSA:         entry a1, 32
-; XTENSA-NEXT:    l16ui a2, a2, 0
-; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI20_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
 ; XTENSA-NEXT:    retw.n
-  %v = load atomic i16, ptr %p seq_cst, align 2
-  ret i16 %v
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i32_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    s32i.n a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 %b, ptr %a unordered, align 4
+  ret void
 }
 
-define void @store16(ptr %p, i16 %val1) {
-; XTENSA_OPT-LABEL: store16:
-; XTENSA_OPT:         entry a1, 32
-; XTENSA_OPT-NEXT:    memw
-; XTENSA_OPT-NEXT:    s16i a3, a2, 0
-; XTENSA_OPT-NEXT:    memw
-; XTENSA_OPT-NEXT:    retw.n
+define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI21_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
 ;
-; XTENSA_OPT_NONE-LABEL: store16:
-; XTENSA_OPT_NONE:         entry a1, 32
-; XTENSA_OPT_NONE-NEXT:    # kill: def $a8 killed $a3
-; XTENSA_OPT_NONE-NEXT:    memw
-; XTENSA_OPT_NONE-NEXT:    s16i a3, a2, 0
-; XTENSA_OPT_NONE-NEXT:    memw
-; XTENSA_OPT_NONE-NEXT:    retw.n
-  store atomic i16 %val1, ptr %p seq_cst, align 2
+; XTENSA-ATOMIC-LABEL: atomic_store_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    s32i.n a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 %b, ptr %a monotonic, align 4
   ret void
 }
 
-define void @test1(ptr %ptr1, ptr %ptr2) {
-; XTENSA-LABEL: test1:
+define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i32_release:
 ; XTENSA:         entry a1, 32
-; XTENSA-NEXT:    l8ui a8, a2, 0
-; XTENSA-NEXT:    s8i a8, a3, 0
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI22_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
 ; XTENSA-NEXT:    retw.n
-  %val = load atomic i8, ptr %ptr1 unordered, align 1
-  store atomic i8 %val, ptr %ptr2 unordered, align 1
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    s32i.n a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 %b, ptr %a release, align 4
   ret void
 }
 
-define void @test2(ptr %ptr1, ptr %ptr2) {
-; XTENSA-LABEL: test2:
+define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomic_store_i32_seq_cst:
 ; XTENSA:         entry a1, 32
-; XTENSA-NEXT:    l8ui a8, a2, 0
-; XTENSA-NEXT:    memw
-; XTENSA-NEXT:    memw
-; XTENSA-NEXT:    s8i a8, a3, 0
-; XTENSA-NEXT:    memw
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI23_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
 ; XTENSA-NEXT:    retw.n
-  %val = load atomic i8, ptr %ptr1 seq_cst, align 1
-  store atomic i8 %val, ptr %ptr2 seq_cst, align 1
+;
+; XTENSA-ATOMIC-LABEL: atomic_store_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    s32i.n a3, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 %b, ptr %a seq_cst, align 4
   ret void
 }
diff --git a/llvm/test/CodeGen/Xtensa/atomic-rmw.ll b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll
new file mode 100644
index 00000000000000..af3b568b5b619f
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/atomic-rmw.ll
@@ -0,0 +1,4388 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=xtensa -mcpu=esp32s2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA
+; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC
+
+define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI0_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a10, 255
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB0_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB0_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB0_2: # Parent Loop BB0_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB0_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB0_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB0_2
+; XTENSA-ATOMIC-NEXT:  .LBB0_4: # in Loop: Header=BB0_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB0_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 7
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI1_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a10, 255
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB1_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB1_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB1_2: # Parent Loop BB1_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB1_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB1_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB1_2
+; XTENSA-ATOMIC-NEXT:  .LBB1_4: # in Loop: Header=BB1_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB1_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 7
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI2_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a10, 255
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB2_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB2_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB2_2: # Parent Loop BB2_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB2_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB2_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB2_2
+; XTENSA-ATOMIC-NEXT:  .LBB2_4: # in Loop: Header=BB2_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB2_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 7
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI3_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a10, 255
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB3_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB3_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB3_2: # Parent Loop BB3_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB3_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB3_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB3_2
+; XTENSA-ATOMIC-NEXT:  .LBB3_4: # in Loop: Header=BB3_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB3_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 7
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI4_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a10, 255
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB4_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB4_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB4_2: # Parent Loop BB4_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB4_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB4_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB4_2
+; XTENSA-ATOMIC-NEXT:  .LBB4_4: # in Loop: Header=BB4_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB4_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 7
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI5_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB5_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI6_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB6_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI7_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB7_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI8_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB8_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI9_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB9_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI10_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB10_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI11_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB11_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI12_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB12_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI13_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB13_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI14_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB14_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI15_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a9, 255
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB15_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI16_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a9, 255
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB16_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB16_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI17_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a9, 255
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB17_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB17_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI18_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a9, 255
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB18_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB18_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI19_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a9, 255
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB19_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB19_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI20_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB20_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI21_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB21_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI22_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB22_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI23_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB23_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI24_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a10, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a9, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    ssl a9
+; XTENSA-ATOMIC-NEXT:    sll a11, a8
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a10, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB24_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a9
+; XTENSA-ATOMIC-NEXT:    srl a9, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a9, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI25_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB25_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB25_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI26_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB26_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI27_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB27_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB27_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI28_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB28_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB28_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI29_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB29_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB29_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i8_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI30_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB30_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB30_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i8 %b monotonic
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i8_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI31_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB31_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB31_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i8 %b acquire
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i8_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI32_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB32_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB32_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i8 %b release
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i8_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI33_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB33_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB33_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i8 %b acq_rel
+  ret i8 %1
+}
+
+define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i8_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI34_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i8_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi a8, 255
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB34_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB34_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i8 %b seq_cst
+  ret i8 %1
+}
+
+;define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i8 %b monotonic
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i8 %b acquire
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i8 %b release
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i8 %b acq_rel
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i8 %b seq_cst
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i8 %b monotonic
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i8 %b acquire
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i8 %b release
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i8 %b acq_rel
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i8 %b seq_cst
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i8 %b monotonic
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i8 %b acquire
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i8 %b release
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i8 %b acq_rel
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i8 %b seq_cst
+;  ret i8 %1
+;}
+
+;define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i8 %b monotonic
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i8 %b acquire
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i8 %b release
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i8 %b acq_rel
+;  ret i8 %1
+;}
+;
+;define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i8 %b seq_cst
+;  ret i8 %1
+;}
+
+define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI35_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB35_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB35_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB35_2: # Parent Loop BB35_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB35_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB35_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB35_2
+; XTENSA-ATOMIC-NEXT:  .LBB35_4: # in Loop: Header=BB35_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB35_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 15
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI36_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB36_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB36_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB36_2: # Parent Loop BB36_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB36_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB36_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB36_2
+; XTENSA-ATOMIC-NEXT:  .LBB36_4: # in Loop: Header=BB36_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB36_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 15
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI37_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB37_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB37_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB37_2: # Parent Loop BB37_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB37_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB37_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB37_2
+; XTENSA-ATOMIC-NEXT:  .LBB37_4: # in Loop: Header=BB37_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB37_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 15
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI38_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB38_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB38_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB38_2: # Parent Loop BB38_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB38_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB38_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB38_2
+; XTENSA-ATOMIC-NEXT:  .LBB38_4: # in Loop: Header=BB38_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB38_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 15
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI39_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    xor a11, a10, a11
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a14, a13, a10
+; XTENSA-ATOMIC-NEXT:  .LBB39_1: # =>This Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    # Child Loop BB39_2 Depth 2
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a14
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:  .LBB39_2: # Parent Loop BB39_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    # => This Inner Loop Header: Depth=2
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a7
+; XTENSA-ATOMIC-NEXT:    or a14, a12, a15
+; XTENSA-ATOMIC-NEXT:    or a7, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a7, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    beq a7, a14, .LBB39_4
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # in Loop: Header=BB39_2 Depth=2
+; XTENSA-ATOMIC-NEXT:    and a7, a14, a11
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB39_2
+; XTENSA-ATOMIC-NEXT:  .LBB39_4: # in Loop: Header=BB39_1 Depth=1
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a10
+; XTENSA-ATOMIC-NEXT:    bne a14, a13, .LBB39_1
+; XTENSA-ATOMIC-NEXT:  # %bb.5:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    sext a2, a8, 15
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI40_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB40_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI41_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB41_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI42_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB42_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI43_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB43_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI44_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    add.n a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB44_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI45_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB45_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB45_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI46_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB46_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB46_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI47_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB47_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB47_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI48_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB48_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB48_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI49_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    movi.n a12, -1
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    xor a12, a11, a12
+; XTENSA-ATOMIC-NEXT:    l32i.n a14, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a13, a3
+; XTENSA-ATOMIC-NEXT:  .LBB49_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a15, a14
+; XTENSA-ATOMIC-NEXT:    and a14, a15, a11
+; XTENSA-ATOMIC-NEXT:    sub a14, a14, a13
+; XTENSA-ATOMIC-NEXT:    and a14, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a7, a15, a12
+; XTENSA-ATOMIC-NEXT:    or a7, a14, a7
+; XTENSA-ATOMIC-NEXT:    wsr a15, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a7, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a7
+; XTENSA-ATOMIC-NEXT:    bne a7, a15, .LBB49_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a14
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI50_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a9, .LCPI50_0
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB50_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB50_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI51_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a9, .LCPI51_0
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB51_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB51_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI52_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a9, .LCPI52_0
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB52_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB52_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI53_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a9, .LCPI53_0
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB53_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB53_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI54_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a9, .LCPI54_0
+; XTENSA-ATOMIC-NEXT:    and a10, a3, a9
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a11
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a10, a10
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    xor a9, a9, a11
+; XTENSA-ATOMIC-NEXT:    or a9, a9, a10
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB54_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    and a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB54_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI55_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB55_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB55_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI56_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB56_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB56_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI57_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB57_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB57_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI58_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB58_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB58_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_nand_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI59_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_nand_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 3
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a2
+; XTENSA-ATOMIC-NEXT:    sub a9, a2, a8
+; XTENSA-ATOMIC-NEXT:    slli a8, a8, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 1
+; XTENSA-ATOMIC-NEXT:    slli a10, a10, 16
+; XTENSA-ATOMIC-NEXT:    addi.n a10, a10, -1
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a11, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a13, a9, 0
+; XTENSA-ATOMIC-NEXT:    sll a12, a3
+; XTENSA-ATOMIC-NEXT:  .LBB59_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a14, a13
+; XTENSA-ATOMIC-NEXT:    and a13, a14, a11
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a12
+; XTENSA-ATOMIC-NEXT:    and a13, a13, a11
+; XTENSA-ATOMIC-NEXT:    xor a15, a14, a11
+; XTENSA-ATOMIC-NEXT:    or a15, a13, a15
+; XTENSA-ATOMIC-NEXT:    wsr a14, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a15, a9, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a15
+; XTENSA-ATOMIC-NEXT:    bne a15, a14, .LBB59_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a8, a13
+; XTENSA-ATOMIC-NEXT:    and a2, a8, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw nand ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI60_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI60_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB60_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB60_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI61_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI61_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB61_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB61_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI62_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI62_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB62_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB62_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI63_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI63_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB63_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB63_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI64_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI64_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB64_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    or a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB64_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i16_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI65_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI65_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB65_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB65_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i16 %b monotonic
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i16_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI66_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI66_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB66_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB66_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i16 %b acquire
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i16_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI67_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI67_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB67_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB67_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i16 %b release
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i16_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI68_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI68_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB68_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB68_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i16 %b acq_rel
+  ret i16 %1
+}
+
+define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i16_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI69_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i16_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI69_0
+; XTENSA-ATOMIC-NEXT:    and a9, a3, a8
+; XTENSA-ATOMIC-NEXT:    _slli a8, a2, 3
+; XTENSA-ATOMIC-NEXT:    movi.n a10, 24
+; XTENSA-ATOMIC-NEXT:    and a8, a8, a10
+; XTENSA-ATOMIC-NEXT:    ssl a8
+; XTENSA-ATOMIC-NEXT:    sll a9, a9
+; XTENSA-ATOMIC-NEXT:    movi.n a10, -4
+; XTENSA-ATOMIC-NEXT:    and a10, a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a12, a10, 0
+; XTENSA-ATOMIC-NEXT:  .LBB69_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a13, a12
+; XTENSA-ATOMIC-NEXT:    xor a11, a13, a9
+; XTENSA-ATOMIC-NEXT:    wsr a13, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a11, a10, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a11
+; XTENSA-ATOMIC-NEXT:    bne a13, a11, .LBB69_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a11
+; XTENSA-ATOMIC-NEXT:    ssr a8
+; XTENSA-ATOMIC-NEXT:    srl a2, a9
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i16 %b seq_cst
+  ret i16 %1
+}
+
+;define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i16 %b monotonic
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i16 %b acquire
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i16 %b release
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i16 %b acq_rel
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i16 %b seq_cst
+;  ret i16 %1
+;}
+
+;define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i16 %b monotonic
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i16 %b acquire
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i16 %b release
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i16 %b acq_rel
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i16 %b seq_cst
+;  ret i16 %1
+;}
+
+;define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i16 %b monotonic
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i16 %b acquire
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i16 %b release
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i16 %b acq_rel
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i16 %b seq_cst
+;  ret i16 %1
+;}
+
+;define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i16 %b monotonic
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i16 %b acquire
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i16 %b release
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i16 %b acq_rel
+;  ret i16 %1
+;}
+;
+;define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i16 %b seq_cst
+;  ret i16 %1
+;}
+
+define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI70_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB70_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a9
+; XTENSA-ATOMIC-NEXT:    wsr a8, scompare1
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a3
+; XTENSA-ATOMIC-NEXT:    s32c1i a9, a2, 0
+; XTENSA-ATOMIC-NEXT:    bne a9, a8, .LBB70_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i32 %b monotonic
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI71_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB71_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a9
+; XTENSA-ATOMIC-NEXT:    wsr a8, scompare1
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a3
+; XTENSA-ATOMIC-NEXT:    s32c1i a9, a2, 0
+; XTENSA-ATOMIC-NEXT:    bne a9, a8, .LBB71_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i32 %b acquire
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI72_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB72_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a9
+; XTENSA-ATOMIC-NEXT:    wsr a8, scompare1
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a3
+; XTENSA-ATOMIC-NEXT:    s32c1i a9, a2, 0
+; XTENSA-ATOMIC-NEXT:    bne a9, a8, .LBB72_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i32 %b release
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i32_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI73_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB73_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a9
+; XTENSA-ATOMIC-NEXT:    wsr a8, scompare1
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a3
+; XTENSA-ATOMIC-NEXT:    s32c1i a9, a2, 0
+; XTENSA-ATOMIC-NEXT:    bne a9, a8, .LBB73_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i32 %b acq_rel
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xchg_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI74_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xchg_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB74_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a9
+; XTENSA-ATOMIC-NEXT:    wsr a8, scompare1
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a3
+; XTENSA-ATOMIC-NEXT:    s32c1i a9, a2, 0
+; XTENSA-ATOMIC-NEXT:    bne a9, a8, .LBB74_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xchg ptr %a, i32 %b seq_cst
+  ret i32 %1
+}
+
+define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI75_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB75_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    add.n a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB75_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i32 %b monotonic
+  ret i32 %1
+}
+
+define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI76_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB76_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    add.n a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB76_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i32 %b acquire
+  ret i32 %1
+}
+
+define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI77_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB77_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    add.n a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB77_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i32 %b release
+  ret i32 %1
+}
+
+define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i32_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI78_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB78_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    add.n a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB78_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i32 %b acq_rel
+  ret i32 %1
+}
+
+define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_add_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI79_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_add_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB79_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    add.n a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB79_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw add ptr %a, i32 %b seq_cst
+  ret i32 %1
+}
+
+define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI80_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB80_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    sub a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB80_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i32 %b monotonic
+  ret i32 %1
+}
+
+define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI81_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB81_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    sub a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB81_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i32 %b acquire
+  ret i32 %1
+}
+
+define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI82_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB82_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    sub a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB82_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i32 %b release
+  ret i32 %1
+}
+
+define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i32_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI83_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB83_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    sub a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB83_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i32 %b acq_rel
+  ret i32 %1
+}
+
+define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_sub_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI84_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_sub_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB84_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    sub a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB84_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw sub ptr %a, i32 %b seq_cst
+  ret i32 %1
+}
+
+define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI85_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB85_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    and a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB85_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i32 %b monotonic
+  ret i32 %1
+}
+
+define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI86_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB86_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    and a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB86_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i32 %b acquire
+  ret i32 %1
+}
+
+define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI87_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB87_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    and a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB87_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i32 %b release
+  ret i32 %1
+}
+
+define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i32_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI88_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB88_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    and a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB88_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i32 %b acq_rel
+  ret i32 %1
+}
+
+define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_and_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI89_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_and_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB89_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    and a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB89_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw and ptr %a, i32 %b seq_cst
+  ret i32 %1
+}
+
+;define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw nand ptr %a, i32 %b monotonic
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw nand ptr %a, i32 %b acquire
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw nand ptr %a, i32 %b release
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw nand ptr %a, i32 %b acq_rel
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw nand ptr %a, i32 %b seq_cst
+;  ret i32 %1
+;}
+
+define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI90_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB90_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    or a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB90_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i32 %b monotonic
+  ret i32 %1
+}
+
+define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI91_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB91_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    or a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB91_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i32 %b acquire
+  ret i32 %1
+}
+
+define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI92_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB92_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    or a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB92_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i32 %b release
+  ret i32 %1
+}
+
+define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i32_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI93_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB93_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    or a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB93_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i32 %b acq_rel
+  ret i32 %1
+}
+
+define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_or_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI94_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_or_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB94_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    or a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB94_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw or ptr %a, i32 %b seq_cst
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI95_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB95_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    xor a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB95_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i32 %b monotonic
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 2
+; XTENSA-NEXT:    l32r a8, .LCPI96_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB96_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    xor a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB96_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i32 %b acquire
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI97_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB97_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    xor a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB97_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i32 %b release
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i32_acq_rel:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 4
+; XTENSA-NEXT:    l32r a8, .LCPI98_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_acq_rel:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB98_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    xor a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB98_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i32 %b acq_rel
+  ret i32 %1
+}
+
+define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind {
+; XTENSA-LABEL: atomicrmw_xor_i32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI99_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a11, a3
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: atomicrmw_xor_i32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a9, a2, 0
+; XTENSA-ATOMIC-NEXT:  .LBB99_1: # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a9
+; XTENSA-ATOMIC-NEXT:    xor a8, a10, a3
+; XTENSA-ATOMIC-NEXT:    wsr a10, scompare1
+; XTENSA-ATOMIC-NEXT:    s32c1i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    mov.n a9, a8
+; XTENSA-ATOMIC-NEXT:    bne a10, a8, .LBB99_1
+; XTENSA-ATOMIC-NEXT:  # %bb.2:
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a8
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %1 = atomicrmw xor ptr %a, i32 %b seq_cst
+  ret i32 %1
+}
+
+;define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i32 %b monotonic
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i32 %b acquire
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i32 %b release
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i32 %b acq_rel
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw max ptr %a, i32 %b seq_cst
+;  ret i32 %1
+;}
+
+;define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i32 %b monotonic
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i32 %b acquire
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i32 %b release
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i32 %b acq_rel
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw min ptr %a, i32 %b seq_cst
+;  ret i32 %1
+;}
+
+;define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i32 %b monotonic
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i32 %b acquire
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i32 %b release
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i32 %b acq_rel
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umax ptr %a, i32 %b seq_cst
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i32 %b monotonic
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i32 %b acquire
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i32 %b release
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i32 %b acq_rel
+;  ret i32 %1
+;}
+;
+;define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
+;  %1 = atomicrmw umin ptr %a, i32 %b seq_cst
+;  ret i32 %1
+;}
diff --git a/llvm/test/CodeGen/Xtensa/atomicrmw.ll b/llvm/test/CodeGen/Xtensa/atomicrmw.ll
deleted file mode 100644
index f2b7526e33e84c..00000000000000
--- a/llvm/test/CodeGen/Xtensa/atomicrmw.ll
+++ /dev/null
@@ -1,103 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=CHECK-XTENSA %s
-
-define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
-; CHECK-XTENSA-LABEL: atomicrmw_xchg_i8_seq_cst:
-; CHECK-XTENSA:       # %bb.0:
-; CHECK-XTENSA-NEXT:    entry	a1, 32
-; CHECK-XTENSA-NEXT:    memw
-; CHECK-XTENSA-NEXT:    movi.n	a8, 3
-; CHECK-XTENSA-NEXT:    and	a8, a8, a2
-; CHECK-XTENSA-NEXT:    sub	a9, a2, a8
-; CHECK-XTENSA-NEXT:    slli	a8, a8, 3
-; CHECK-XTENSA-NEXT:    movi	a10, 255
-; CHECK-XTENSA-NEXT:    ssl	a8
-; CHECK-XTENSA-NEXT:    movi.n	a11, -1
-; CHECK-XTENSA-NEXT:    sll	a10, a10
-; CHECK-XTENSA-NEXT:    xor	a11, a10, a11
-; CHECK-XTENSA-NEXT:    l32i.n	a12, a9, 0
-; CHECK-XTENSA-NEXT:    sll	a12, a3
-; CHECK-XTENSA-NEXT:    l32i.n	a13, a9, 0
-; CHECK-XTENSA-NEXT:    and	a14, a13, a10
-; CHECK-XTENSA-NEXT:  .LBB0_1: # =>This Loop Header: Depth=1
-; CHECK-XTENSA-NEXT:    #     Child Loop BB0_2 Depth 2
-; CHECK-XTENSA-NEXT:    mov.n	a13, a14
-; CHECK-XTENSA-NEXT:    memw
-; CHECK-XTENSA-NEXT:    l32i.n	a14, a9, 0
-; CHECK-XTENSA-NEXT:    and	a7, a14, a11
-; CHECK-XTENSA-NEXT:  .LBB0_2: #   Parent Loop BB0_1 Depth=1
-; CHECK-XTENSA-NEXT:  # =>  This Inner Loop Header: Depth=2
-; CHECK-XTENSA-NEXT:    mov.n	a15, a7
-; CHECK-XTENSA-NEXT:    or	a14, a12, a15
-; CHECK-XTENSA-NEXT:    or	a7, a13, a15
-; CHECK-XTENSA-NEXT:    wsr	a7, scompare1
-; CHECK-XTENSA-NEXT:    s32c1i	a14, a9, 0
-; CHECK-XTENSA-NEXT:    beq	a7, a14, .LBB0_4
-; CHECK-XTENSA-NEXT:  # %bb.3: #   in Loop: Header=BB0_2 Depth=2
-; CHECK-XTENSA-NEXT:    and	a7, a14, a11
-; CHECK-XTENSA-NEXT:    bne	a7, a15, .LBB0_2
-; CHECK-XTENSA-NEXT:  .LBB0_4: #   in Loop: Header=BB0_1 Depth=1
-; CHECK-XTENSA-NEXT:    and	a14, a14, a10
-; CHECK-XTENSA-NEXT:    bne	a14, a13, .LBB0_1
-; CHECK-XTENSA-NEXT:  # %bb.5:
-; CHECK-XTENSA-NEXT:    ssr	a8
-; CHECK-XTENSA-NEXT:    srl	a8, a14
-; CHECK-XTENSA-NEXT:    sext	a2, a8, 7
-; CHECK-XTENSA-NEXT:    memw
-; CHECK-XTENSA-NEXT:    retw.n
-
-  %1 = atomicrmw xchg i8* %a, i8 %b seq_cst
-  ret i8 %1
-}
-
-define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind {
-; CHECK-XTENSA-LABEL: atomicrmw_xchg_i16_seq_cst:
-; CHECK-XTENSA:       # %bb.0:
-; CHECK-XTENSA-NEXT:    entry	a1, 32
-; CHECK-XTENSA-NEXT:    memw
-; CHECK-XTENSA-NEXT:    movi.n	a8, 3
-; CHECK-XTENSA-NEXT:    and	a8, a8, a2
-; CHECK-XTENSA-NEXT:    sub	a9, a2, a8
-; CHECK-XTENSA-NEXT:    slli	a8, a8, 3
-; CHECK-XTENSA-NEXT:    movi.n	a10, 1
-; CHECK-XTENSA-NEXT:    slli	a10, a10, 16
-; CHECK-XTENSA-NEXT:    addi.n	a10, a10, -1
-; CHECK-XTENSA-NEXT:    ssl	a8
-; CHECK-XTENSA-NEXT:    movi.n	a11, -1
-; CHECK-XTENSA-NEXT:    sll	a10, a10
-; CHECK-XTENSA-NEXT:    xor	a11, a10, a11
-; CHECK-XTENSA-NEXT:    l32i.n	a12, a9, 0
-; CHECK-XTENSA-NEXT:    sll	a12, a3
-; CHECK-XTENSA-NEXT:    l32i.n	a13, a9, 0
-; CHECK-XTENSA-NEXT:    and	a14, a13, a10
-; CHECK-XTENSA-NEXT:  .LBB1_1: # =>This Loop Header: Depth=1
-; CHECK-XTENSA-NEXT:    #     Child Loop BB1_2 Depth 2
-; CHECK-XTENSA-NEXT:    mov.n	a13, a14
-; CHECK-XTENSA-NEXT:    memw
-; CHECK-XTENSA-NEXT:    l32i.n	a14, a9, 0
-; CHECK-XTENSA-NEXT:    and	a7, a14, a11
-; CHECK-XTENSA-NEXT:  .LBB1_2: #   Parent Loop BB1_1 Depth=1
-; CHECK-XTENSA-NEXT:    # =>  This Inner Loop Header: Depth=2
-; CHECK-XTENSA-NEXT:    mov.n	a15, a7
-; CHECK-XTENSA-NEXT:    or	a14, a12, a15
-; CHECK-XTENSA-NEXT:    or	a7, a13, a15
-; CHECK-XTENSA-NEXT:    wsr	a7, scompare1
-; CHECK-XTENSA-NEXT:    s32c1i	a14, a9, 0
-; CHECK-XTENSA-NEXT:    beq	a7, a14, .LBB1_4
-; CHECK-XTENSA-NEXT:  # %bb.3: #   in Loop: Header=BB1_2 Depth=2
-; CHECK-XTENSA-NEXT:    and	a7, a14, a11
-; CHECK-XTENSA-NEXT:    bne	a7, a15, .LBB1_2
-; CHECK-XTENSA-NEXT:  .LBB1_4: #   in Loop: Header=BB1_1 Depth=1
-; CHECK-XTENSA-NEXT:    and	a14, a14, a10
-; CHECK-XTENSA-NEXT:    bne	a14, a13, .LBB1_1
-; CHECK-XTENSA-NEXT:  # %bb.5:
-; CHECK-XTENSA-NEXT:    ssr	a8
-; CHECK-XTENSA-NEXT:    srl	a8, a14
-; CHECK-XTENSA-NEXT:    sext	a2, a8, 15
-; CHECK-XTENSA-NEXT:    memw
-; CHECK-XTENSA-NEXT:    retw.n
-
-  %1 = atomicrmw xchg i16* %a, i16 %b seq_cst
-  ret i16 %1
-}
diff --git a/llvm/test/CodeGen/Xtensa/forced-atomics.ll b/llvm/test/CodeGen/Xtensa/forced-atomics.ll
new file mode 100644
index 00000000000000..e11ae5329b091d
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/forced-atomics.ll
@@ -0,0 +1,1005 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=xtensa -mcpu=esp32s2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA
+; RUN: llc -mtriple=xtensa -mcpu=esp32s2 -mattr=+forced-atomics -verify-machineinstrs < %s | FileCheck %s --check-prefixes=XTENSA-ATOMIC
+
+define i8 @load8(ptr %p) nounwind {
+; XTENSA-LABEL: load8:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 5
+; XTENSA-NEXT:    l32r a8, .LCPI0_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: load8:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l8ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = load atomic i8, ptr %p seq_cst, align 1
+  ret i8 %v
+}
+
+define void @store8(ptr %p) nounwind {
+; XTENSA-LABEL: store8:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI1_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: store8:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s8i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i8 0, ptr %p seq_cst, align 1
+  ret void
+}
+
+define i8 @rmw8(ptr %p) nounwind {
+; XTENSA-LABEL: rmw8:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI2_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw8:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI2_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw add ptr %p, i8 1 seq_cst, align 1
+  ret i8 %v
+}
+
+define i8 @cmpxchg8(ptr %p) nounwind {
+; XTENSA-LABEL: cmpxchg8:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    movi.n a8, 0
+; XTENSA-NEXT:    s8i a8, a1, 3
+; XTENSA-NEXT:    addi a11, a1, 3
+; XTENSA-NEXT:    movi.n a12, 1
+; XTENSA-NEXT:    movi.n a13, 5
+; XTENSA-NEXT:    l32r a8, .LCPI3_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a14, a13
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    l8ui a2, a1, 3
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: cmpxchg8:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a12, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI3_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %res = cmpxchg ptr %p, i8 0, i8 1 seq_cst seq_cst
+  %res.0 = extractvalue { i8, i1 } %res, 0
+  ret i8 %res.0
+}
+
+define i16 @load16(ptr %p) nounwind {
+; XTENSA-LABEL: load16:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 5
+; XTENSA-NEXT:    l32r a8, .LCPI4_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: load16:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l16ui a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = load atomic i16, ptr %p seq_cst, align 2
+  ret i16 %v
+}
+
+define void @store16(ptr %p) nounwind {
+; XTENSA-LABEL: store16:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI5_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: store16:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s16i a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i16 0, ptr %p seq_cst, align 2
+  ret void
+}
+
+define i16 @rmw16(ptr %p) nounwind {
+; XTENSA-LABEL: rmw16:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI6_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw16:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI6_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw add ptr %p, i16 1 seq_cst, align 2
+  ret i16 %v
+}
+
+define i16 @cmpxchg16(ptr %p) nounwind {
+; XTENSA-LABEL: cmpxchg16:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    movi.n a8, 0
+; XTENSA-NEXT:    s16i a8, a1, 2
+; XTENSA-NEXT:    addi a11, a1, 2
+; XTENSA-NEXT:    movi.n a12, 1
+; XTENSA-NEXT:    movi.n a13, 5
+; XTENSA-NEXT:    l32r a8, .LCPI7_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a14, a13
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    l16ui a2, a1, 2
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: cmpxchg16:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a12, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI7_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %res = cmpxchg ptr %p, i16 0, i16 1 seq_cst seq_cst
+  %res.0 = extractvalue { i16, i1 } %res, 0
+  ret i16 %res.0
+}
+
+define i32 @load32_unordered(ptr %p) nounwind {
+; XTENSA-LABEL: load32_unordered:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI8_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: load32_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = load atomic i32, ptr %p unordered, align 4
+  ret i32 %v
+}
+
+define i32 @load32_monotonic(ptr %p) nounwind {
+; XTENSA-LABEL: load32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI9_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: load32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = load atomic i32, ptr %p monotonic, align 4
+  ret i32 %v
+}
+
+define i32 @load32_acquire(ptr %p) nounwind {
+; XTENSA-LABEL: load32_acquire:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 2
+; XTENSA-NEXT:    l32r a8, .LCPI10_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: load32_acquire:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = load atomic i32, ptr %p acquire, align 4
+  ret i32 %v
+}
+
+define i32 @load32_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: load32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 5
+; XTENSA-NEXT:    l32r a8, .LCPI11_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: load32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    l32i.n a2, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = load atomic i32, ptr %p seq_cst, align 4
+  ret i32 %v
+}
+
+define void @store32_unordered(ptr %p) nounwind {
+; XTENSA-LABEL: store32_unordered:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI12_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a12, a11
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: store32_unordered:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 0, ptr %p unordered, align 4
+  ret void
+}
+
+define void @store32_monotonic(ptr %p) nounwind {
+; XTENSA-LABEL: store32_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    l32r a8, .LCPI13_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a12, a11
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: store32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 0, ptr %p monotonic, align 4
+  ret void
+}
+
+define void @store32_release(ptr %p) nounwind {
+; XTENSA-LABEL: store32_release:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    movi.n a12, 3
+; XTENSA-NEXT:    l32r a8, .LCPI14_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: store32_release:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 0, ptr %p release, align 4
+  ret void
+}
+
+define void @store32_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: store32_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI15_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: store32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a2, 0
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  store atomic i32 0, ptr %p seq_cst, align 4
+  ret void
+}
+
+define i32 @rmw32_add_monotonic(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_add_monotonic:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 0
+; XTENSA-NEXT:    l32r a8, .LCPI16_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_add_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI16_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw add ptr %p, i32 1 monotonic, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_add_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_add_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI17_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_add_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI17_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw add ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_sub_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_sub_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI18_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_sub_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, -1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI18_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw sub ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_and_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_and_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI19_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_and_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI19_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw and ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_nand_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_nand_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI20_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_nand_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI20_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw nand ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_or_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_or_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI21_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_or_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI21_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw or ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_xor_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_xor_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI22_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_xor_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI22_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw xor ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_max_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_max_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    mov.n a6, a2
+; XTENSA-NEXT:    l32i.n a2, a6, 0
+; XTENSA-NEXT:    movi.n a5, 1
+; XTENSA-NEXT:    movi.n a7, 5
+; XTENSA-NEXT:    l32r a4, .LCPI23_0
+; XTENSA-NEXT:  .LBB23_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a2, a1, 0
+; XTENSA-NEXT:    max a12, a2, a5
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a6
+; XTENSA-NEXT:    mov.n a13, a7
+; XTENSA-NEXT:    mov.n a14, a7
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    l32i.n a2, a1, 0
+; XTENSA-NEXT:    beqz a10, .LBB23_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_max_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI23_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw max ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_min_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    mov.n a6, a2
+; XTENSA-NEXT:    l32i.n a2, a6, 0
+; XTENSA-NEXT:    movi.n a5, 1
+; XTENSA-NEXT:    movi.n a7, 5
+; XTENSA-NEXT:    l32r a4, .LCPI24_0
+; XTENSA-NEXT:  .LBB24_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a2, a1, 0
+; XTENSA-NEXT:    min a12, a2, a5
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a6
+; XTENSA-NEXT:    mov.n a13, a7
+; XTENSA-NEXT:    mov.n a14, a7
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    l32i.n a2, a1, 0
+; XTENSA-NEXT:    beqz a10, .LBB24_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_min_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI24_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw min ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_umax_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_umax_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    mov.n a6, a2
+; XTENSA-NEXT:    l32i.n a2, a6, 0
+; XTENSA-NEXT:    movi.n a5, 1
+; XTENSA-NEXT:    movi.n a7, 5
+; XTENSA-NEXT:    l32r a4, .LCPI25_0
+; XTENSA-NEXT:  .LBB25_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a2, a1, 0
+; XTENSA-NEXT:    maxu a12, a2, a5
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a6
+; XTENSA-NEXT:    mov.n a13, a7
+; XTENSA-NEXT:    mov.n a14, a7
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    l32i.n a2, a1, 0
+; XTENSA-NEXT:    beqz a10, .LBB25_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_umax_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI25_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw umax ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_umin_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    mov.n a6, a2
+; XTENSA-NEXT:    l32i.n a2, a6, 0
+; XTENSA-NEXT:    movi.n a5, 1
+; XTENSA-NEXT:    movi.n a7, 5
+; XTENSA-NEXT:    l32r a4, .LCPI26_0
+; XTENSA-NEXT:  .LBB26_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a2, a1, 0
+; XTENSA-NEXT:    minu a12, a2, a5
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a6
+; XTENSA-NEXT:    mov.n a13, a7
+; XTENSA-NEXT:    mov.n a14, a7
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    l32i.n a2, a1, 0
+; XTENSA-NEXT:    beqz a10, .LBB26_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_umin_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI26_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw umin ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define i32 @rmw32_xchg_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_xchg_seq_cst:
+; XTENSA:         entry a1, 32
+; XTENSA-NEXT:    movi.n a11, 1
+; XTENSA-NEXT:    movi.n a12, 5
+; XTENSA-NEXT:    l32r a8, .LCPI27_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_xchg_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI27_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw xchg ptr %p, i32 1 seq_cst, align 4
+  ret i32 %v
+}
+
+define float @rmw32_fadd_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_fadd_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    l32i.n a10, a2, 0
+; XTENSA-NEXT:    l32r a7, .LCPI28_0
+; XTENSA-NEXT:    l32r a5, .LCPI28_1
+; XTENSA-NEXT:    movi.n a6, 5
+; XTENSA-NEXT:    l32r a4, .LCPI28_2
+; XTENSA-NEXT:  .LBB28_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a10, a1, 0
+; XTENSA-NEXT:    mov.n a11, a7
+; XTENSA-NEXT:    callx8 a5
+; XTENSA-NEXT:    mov.n a12, a10
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a13, a6
+; XTENSA-NEXT:    mov.n a14, a6
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    mov.n a8, a10
+; XTENSA-NEXT:    l32i.n a10, a1, 0
+; XTENSA-NEXT:    beqz a8, .LBB28_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_fadd_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 48
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a6, a2, 0
+; XTENSA-ATOMIC-NEXT:    l32r a7, .LCPI28_0
+; XTENSA-ATOMIC-NEXT:    l32r a5, .LCPI28_1
+; XTENSA-ATOMIC-NEXT:    l32r a4, .LCPI28_2
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a3, 1
+; XTENSA-ATOMIC-NEXT:    j .LBB28_2
+; XTENSA-ATOMIC-NEXT:  .LBB28_1: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB28_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a6, a10
+; XTENSA-ATOMIC-NEXT:    beqi a8, 1, .LBB28_4
+; XTENSA-ATOMIC-NEXT:  .LBB28_2: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a6
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a7
+; XTENSA-ATOMIC-NEXT:    callx8 a5
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a10
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a6
+; XTENSA-ATOMIC-NEXT:    callx8 a4
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a3
+; XTENSA-ATOMIC-NEXT:    beq a10, a6, .LBB28_1
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB28_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    l32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    j .LBB28_1
+; XTENSA-ATOMIC-NEXT:  .LBB28_4: # %atomicrmw.end
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw fadd ptr %p, float 1.0 seq_cst, align 4
+  ret float %v
+}
+
+define float @rmw32_fsub_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_fsub_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    l32i.n a10, a2, 0
+; XTENSA-NEXT:    l32r a7, .LCPI29_0
+; XTENSA-NEXT:    l32r a5, .LCPI29_1
+; XTENSA-NEXT:    movi.n a6, 5
+; XTENSA-NEXT:    l32r a4, .LCPI29_2
+; XTENSA-NEXT:  .LBB29_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a10, a1, 0
+; XTENSA-NEXT:    mov.n a11, a7
+; XTENSA-NEXT:    callx8 a5
+; XTENSA-NEXT:    mov.n a12, a10
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a13, a6
+; XTENSA-NEXT:    mov.n a14, a6
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    mov.n a8, a10
+; XTENSA-NEXT:    l32i.n a10, a1, 0
+; XTENSA-NEXT:    beqz a8, .LBB29_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_fsub_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 48
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a6, a2, 0
+; XTENSA-ATOMIC-NEXT:    l32r a7, .LCPI29_0
+; XTENSA-ATOMIC-NEXT:    l32r a5, .LCPI29_1
+; XTENSA-ATOMIC-NEXT:    l32r a4, .LCPI29_2
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a3, 1
+; XTENSA-ATOMIC-NEXT:    j .LBB29_2
+; XTENSA-ATOMIC-NEXT:  .LBB29_1: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB29_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a6, a10
+; XTENSA-ATOMIC-NEXT:    beqi a8, 1, .LBB29_4
+; XTENSA-ATOMIC-NEXT:  .LBB29_2: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a6
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a7
+; XTENSA-ATOMIC-NEXT:    callx8 a5
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a10
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a6
+; XTENSA-ATOMIC-NEXT:    callx8 a4
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a3
+; XTENSA-ATOMIC-NEXT:    beq a10, a6, .LBB29_1
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB29_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    l32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    j .LBB29_1
+; XTENSA-ATOMIC-NEXT:  .LBB29_4: # %atomicrmw.end
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw fsub ptr %p, float 1.0 seq_cst, align 4
+  ret float %v
+}
+
+define float @rmw32_fmin_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_fmin_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    l32i.n a10, a2, 0
+; XTENSA-NEXT:    l32r a7, .LCPI30_0
+; XTENSA-NEXT:    l32r a5, .LCPI30_1
+; XTENSA-NEXT:    movi.n a6, 5
+; XTENSA-NEXT:    l32r a4, .LCPI30_2
+; XTENSA-NEXT:  .LBB30_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a10, a1, 0
+; XTENSA-NEXT:    mov.n a11, a7
+; XTENSA-NEXT:    callx8 a5
+; XTENSA-NEXT:    mov.n a12, a10
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a13, a6
+; XTENSA-NEXT:    mov.n a14, a6
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    mov.n a8, a10
+; XTENSA-NEXT:    l32i.n a10, a1, 0
+; XTENSA-NEXT:    beqz a8, .LBB30_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_fmin_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 48
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a6, a2, 0
+; XTENSA-ATOMIC-NEXT:    l32r a7, .LCPI30_0
+; XTENSA-ATOMIC-NEXT:    l32r a5, .LCPI30_1
+; XTENSA-ATOMIC-NEXT:    l32r a4, .LCPI30_2
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a3, 1
+; XTENSA-ATOMIC-NEXT:    j .LBB30_2
+; XTENSA-ATOMIC-NEXT:  .LBB30_1: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB30_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a6, a10
+; XTENSA-ATOMIC-NEXT:    beqi a8, 1, .LBB30_4
+; XTENSA-ATOMIC-NEXT:  .LBB30_2: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a6
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a7
+; XTENSA-ATOMIC-NEXT:    callx8 a5
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a10
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a6
+; XTENSA-ATOMIC-NEXT:    callx8 a4
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a3
+; XTENSA-ATOMIC-NEXT:    beq a10, a6, .LBB30_1
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB30_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    l32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    j .LBB30_1
+; XTENSA-ATOMIC-NEXT:  .LBB30_4: # %atomicrmw.end
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw fmin ptr %p, float 1.0 seq_cst, align 4
+  ret float %v
+}
+
+define float @rmw32_fmax_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: rmw32_fmax_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    l32i.n a10, a2, 0
+; XTENSA-NEXT:    l32r a7, .LCPI31_0
+; XTENSA-NEXT:    l32r a5, .LCPI31_1
+; XTENSA-NEXT:    movi.n a6, 5
+; XTENSA-NEXT:    l32r a4, .LCPI31_2
+; XTENSA-NEXT:  .LBB31_1: # %atomicrmw.start
+; XTENSA-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-NEXT:    s32i.n a10, a1, 0
+; XTENSA-NEXT:    mov.n a11, a7
+; XTENSA-NEXT:    callx8 a5
+; XTENSA-NEXT:    mov.n a12, a10
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a13, a6
+; XTENSA-NEXT:    mov.n a14, a6
+; XTENSA-NEXT:    callx8 a4
+; XTENSA-NEXT:    mov.n a8, a10
+; XTENSA-NEXT:    l32i.n a10, a1, 0
+; XTENSA-NEXT:    beqz a8, .LBB31_1
+; XTENSA-NEXT:  # %bb.2: # %atomicrmw.end
+; XTENSA-NEXT:    mov.n a2, a10
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: rmw32_fmax_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 48
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    l32i.n a6, a2, 0
+; XTENSA-ATOMIC-NEXT:    l32r a7, .LCPI31_0
+; XTENSA-ATOMIC-NEXT:    l32r a5, .LCPI31_1
+; XTENSA-ATOMIC-NEXT:    l32r a4, .LCPI31_2
+; XTENSA-ATOMIC-NEXT:    movi.n a8, 0
+; XTENSA-ATOMIC-NEXT:    s32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a3, 1
+; XTENSA-ATOMIC-NEXT:    j .LBB31_2
+; XTENSA-ATOMIC-NEXT:  .LBB31_1: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB31_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a6, a10
+; XTENSA-ATOMIC-NEXT:    beqi a8, 1, .LBB31_4
+; XTENSA-ATOMIC-NEXT:  .LBB31_2: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a6
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a7
+; XTENSA-ATOMIC-NEXT:    callx8 a5
+; XTENSA-ATOMIC-NEXT:    mov.n a12, a10
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    mov.n a11, a6
+; XTENSA-ATOMIC-NEXT:    callx8 a4
+; XTENSA-ATOMIC-NEXT:    mov.n a8, a3
+; XTENSA-ATOMIC-NEXT:    beq a10, a6, .LBB31_1
+; XTENSA-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
+; XTENSA-ATOMIC-NEXT:    # in Loop: Header=BB31_2 Depth=1
+; XTENSA-ATOMIC-NEXT:    l32i.n a8, a1, 0
+; XTENSA-ATOMIC-NEXT:    j .LBB31_1
+; XTENSA-ATOMIC-NEXT:  .LBB31_4: # %atomicrmw.end
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %v = atomicrmw fmax ptr %p, float 1.0 seq_cst, align 4
+  ret float %v
+}
+
+define i32 @cmpxchg32_monotonic(ptr %p) nounwind {
+; XTENSA-LABEL: cmpxchg32_monotonic:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    movi.n a13, 0
+; XTENSA-NEXT:    s32i.n a13, a1, 0
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    movi.n a12, 1
+; XTENSA-NEXT:    l32r a8, .LCPI32_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a14, a13
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    l32i.n a2, a1, 0
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: cmpxchg32_monotonic:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a12, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI32_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %res = cmpxchg ptr %p, i32 0, i32 1 monotonic monotonic
+  %res.0 = extractvalue { i32, i1 } %res, 0
+  ret i32 %res.0
+}
+
+define i32 @cmpxchg32_seq_cst(ptr %p) nounwind {
+; XTENSA-LABEL: cmpxchg32_seq_cst:
+; XTENSA:         entry a1, 48
+; XTENSA-NEXT:    movi.n a8, 0
+; XTENSA-NEXT:    s32i.n a8, a1, 0
+; XTENSA-NEXT:    addi a11, a1, 0
+; XTENSA-NEXT:    movi.n a12, 1
+; XTENSA-NEXT:    movi.n a13, 5
+; XTENSA-NEXT:    l32r a8, .LCPI33_0
+; XTENSA-NEXT:    mov.n a10, a2
+; XTENSA-NEXT:    mov.n a14, a13
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    l32i.n a2, a1, 0
+; XTENSA-NEXT:    retw.n
+;
+; XTENSA-ATOMIC-LABEL: cmpxchg32_seq_cst:
+; XTENSA-ATOMIC:         entry a1, 32
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    movi.n a11, 0
+; XTENSA-ATOMIC-NEXT:    movi.n a12, 1
+; XTENSA-ATOMIC-NEXT:    l32r a8, .LCPI33_0
+; XTENSA-ATOMIC-NEXT:    mov.n a10, a2
+; XTENSA-ATOMIC-NEXT:    callx8 a8
+; XTENSA-ATOMIC-NEXT:    mov.n a2, a10
+; XTENSA-ATOMIC-NEXT:    memw
+; XTENSA-ATOMIC-NEXT:    retw.n
+  %res = cmpxchg ptr %p, i32 0, i32 1 seq_cst seq_cst
+  %res.0 = extractvalue { i32, i1 } %res, 0
+  ret i32 %res.0
+}