How to generate RocketChip BD cell with multiple AXI4 interfaces for DDR channels?

[xiongyw]

I noticed that board VCU1525 folder contains two subfolders m2 and m4, probably corresponding to 2 and 4 ddr channels respectively. And in the BD creation tcl scripts (in m4, e.g.), the RocketChip has 4 AXI4 interfaces for connecting to DDR: MEM_AXI4_0~3. So it seems that the created RocketChip cell should also contains all those interfaces, but I don't know how such a RocketChip cell is created. By using make CONFIG=rocket64b2 BOARD=vcu1525 ..., it seems that the resulting project only contains one DDR4 channel, and RocketChip module contains a single DDR interface named MEM_AXI4.

I tried CONFIG=rocket64b2m4, it reports errors.

Btw, my goal is to port to another vu13p-based board using 4 DDR channels, using vcu1525 as a reference point.

Thanks!

[eugene-tarassov]

Look for WithNMemoryChannels in src/main/scala/rocket.scala. 64b4m4 config has 4 memory channels, you can add more configs like this.