diff --git a/.github/workflows/full-clang.yml b/.github/workflows/full-clang.yml index 6526b9f6a..ed56119f5 100644 --- a/.github/workflows/full-clang.yml +++ b/.github/workflows/full-clang.yml @@ -111,3 +111,18 @@ jobs: CI_STORAGE_URL: ${{secrets.CI_STORAGE_URL}} CI_STORAGE_USER: ${{secrets.CI_STORAGE_USER}} CI_STORAGE_TOKEN: ${{secrets.CI_STORAGE_TOKEN}} + + success: + if: ${{always()}} + needs: [grs, grs-vhdl, examples] + runs-on: [self-hosted] + steps: + - name: Check GCC Regression Simple status + if: ${{ needs.grs.result != 'success' }} + run: exit 1 + - name: Check GCC Regression Simple VHDL status + if: ${{ needs.grs-vhdl.result != 'success' }} + run: exit 1 + - name: Check Examples status + if: ${{ needs.examples.result != 'success' }} + run: exit 1 diff --git a/.github/workflows/full-gcc.yml b/.github/workflows/full-gcc.yml index b00d7bdb3..e90c1ce40 100644 --- a/.github/workflows/full-gcc.yml +++ b/.github/workflows/full-gcc.yml @@ -112,3 +112,18 @@ jobs: CI_STORAGE_URL: ${{secrets.CI_STORAGE_URL}} CI_STORAGE_USER: ${{secrets.CI_STORAGE_USER}} CI_STORAGE_TOKEN: ${{secrets.CI_STORAGE_TOKEN}} + + success: + if: ${{always()}} + needs: [grs, grs-vhdl, examples] + runs-on: [self-hosted] + steps: + - name: Check GCC Regression Simple status + if: ${{ needs.grs.result != 'success' }} + run: exit 1 + - name: Check GCC Regression Simple VHDL status + if: ${{ needs.grs-vhdl.result != 'success' }} + run: exit 1 + - name: Check Examples status + if: ${{ needs.examples.result != 'success' }} + run: exit 1 diff --git a/ChangeLog b/ChangeLog index bb01f61c8..a1e1c4db4 100644 --- a/ChangeLog +++ b/ChangeLog @@ -3,7 +3,9 @@ Ninth public release of PandA framework. New features introduced: - Added an LLVM based tree height reduction step. -- Updated support to NanoXplore NXmap +- Updated support to NanoXplore NXmap: NXmap3 support, NG-ULTRA nx2h540tsc device family support +- Added support for AXI Master interface. +- Improved regression test, benchmarking, and integration flow through GitHub Actions workflows =========== PANDA 0.9.7 =========== Sun 20 March 2022, PandA release 0.9.7 diff --git a/etc/clang_plugin/plugin_ASTAnalyzer.cpp b/etc/clang_plugin/plugin_ASTAnalyzer.cpp index 6f053bfe8..1dad90ac2 100644 --- a/etc/clang_plugin/plugin_ASTAnalyzer.cpp +++ b/etc/clang_plugin/plugin_ASTAnalyzer.cpp @@ -663,15 +663,17 @@ namespace clang { file_loc_arg_attr[filename][loc][pname]["attribute2"] = tmp; } - else if(tmp == "bundle") + + PP.Lex(Tok); + if(Tok.is(tok::identifier) && PP.getSpelling(Tok) == "bundle") { bundle_parse(); + end_parse(); } - else + else if(Tok.isNot(tok::eod)) { print_error("axi malformed"); } - end_parse(); }; const std::map> interface_parser = { {"none", end_parse}, {"none_registered", end_parse}, diff --git a/etc/lib/technology/dynamic_generators/ReadWrite_m_axi.cpp b/etc/lib/technology/dynamic_generators/ReadWrite_m_axi.cpp index 6b8ba687f..85a99b05e 100644 --- a/etc/lib/technology/dynamic_generators/ReadWrite_m_axi.cpp +++ b/etc/lib/technology/dynamic_generators/ReadWrite_m_axi.cpp @@ -31,145 +31,406 @@ * */ /** - * @file ReadWrite_array.cpp - * @brief Snippet for the ReadWrite_array dynamic generator. + * @file ReadWrite_m_axi.cpp + * @brief Snippet for the ReadWrite_m_axi dynamic generator. * - * @author Fabrizio Ferrandi + * @author Ankur Limaye + * @author Michele Fiorito * */ -bool isAlignedPowerOfTwo = _ports_out[1].alignment == RUPNP2(_ports_out[1].alignment); -std::cout << "//" << (isAlignedPowerOfTwo ? "T" : "F") << "\n"; -std::cout << "integer ii=0;\n"; -std::cout << "reg [" << _ports_out[1].type_size << "-1:0] " << _ports_out[1].name << ";\n"; -if(_np_out == 5) - std::cout << "reg [" << _ports_out[4].type_size << "-1:0] " << _ports_out[4].name << ";\n"; -if(_np_in == 8) - std::cout << "reg [(PORTSIZE_" << _ports_out[0].name << "*BITSIZE_" << _ports_out[0].name << ")+(-1):0] " - << _ports_out[0].name << ";\n"; +enum in_port +{ + clock = 0, + reset, + start_port, + in1, + in2, + in3, + in4, + AWREADY, + WREADY, + BID, + BRESP, + BUSER, + BVALID, + ARREADY, + RID, + RDATA, + RRESP, + RLAST, + RUSER, + RVALID, + _n_ptr, +}; -unsigned int log2nbyte = - _ports_out[1].alignment == 1 ? 0 : (32u - static_cast(__builtin_clz(_ports_out[1].alignment - 1))); +enum out_port +{ + done_port = 0, + out1, + AWID, + AWADDR, + AWLEN, + AWSIZE, + AWBURST, + AWLOCK, + AWCACHE, + AWPROT, + AWQOS, + AWREGION, + AWUSER, + AWVALID, + WID, + WDATA, + WSTRB, + WLAST, + WUSER, + WVALID, + BREADY, + ARID, + ARADDR, + ARLEN, + ARSIZE, + ARBURST, + ARLOCK, + ARCACHE, + ARPROT, + ARQOS, + ARREGION, + ARUSER, + ARVALID, + RREADY +}; -unsigned addressMaxValue = _ports_out[1].alignment * static_cast(atoi(_specializing_string.data())) - 1; -unsigned int nbitAddress = addressMaxValue == 1 ? 1 : (32u - static_cast(__builtin_clz(addressMaxValue))); +std::cout << R"( +`ifndef _SIM_HAVE_CLOG2 + `define CLOG2(x) \ + (x <= 2) ? 1 : \ + (x <= 4) ? 2 : \ + (x <= 8) ? 3 : \ + (x <= 16) ? 4 : \ + (x <= 32) ? 5 : \ + (x <= 64) ? 6 : \ + (x <= 128) ? 7 : \ + -1 +`endif -if(log2nbyte > 0) -{ - std::cout << "reg [(PORTSIZE_" << _ports_in[3].name << "*" << log2nbyte << ")+(-1):0] " << _ports_in[6].name - << "_0;\n"; - std::cout << "always @(*)\n"; - std::cout << "begin\n"; - std::cout << " for(ii=0; ii 0 && _np_in == 8) -{ - std::cout << "reg [(PORTSIZE_" << _ports_in[3].name << "*" << log2nbyte << ")+(-1):0] " << _ports_in[6].name - << "_reg;\n"; - std::cout << "always @(posedge clock 1RESET_EDGE)\n"; - std::cout << " if (1RESET_VALUE)\n"; - std::cout << " " << _ports_in[6].name << "_reg <= 0;\n"; - std::cout << " else\n"; - std::cout << " for(ii=0; ii 0) - std::cout << " " << _ports_out[0].name << "[(BITSIZE_" << _ports_out[0].name << ")*ii+:BITSIZE_" - << _ports_out[0].name << "] = " << _ports_in[7].name << " >> {" << _ports_in[6].name << "_reg[" - << log2nbyte << "*ii+:" << log2nbyte << "],3'b0};" << std::endl; - else - std::cout << " " << _ports_out[0].name << "[(BITSIZE_" << _ports_out[0].name << ")*ii+:BITSIZE_" - << _ports_out[0].name << "] = " << _ports_in[7].name << ";" << std::endl; - - std::cout << "end\n"; -} - -if(_np_out == 5) - std::cout << "assign " << _ports_out[3].name << " = (|" << _ports_in[2].name << ") & (|" << _ports_in[3].name - << ");\n"; - -if(_np_out == 5) -{ - std::cout << "always @(*)\n"; - std::cout << "begin\n"; - std::cout << " " << _ports_out[4].name << " = 0;\n"; - std::cout << " for(ii=0; ii 0) - std::cout << " " << _ports_out[4].name << " = (" << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name - << ")*ii+:BITSIZE_" << _ports_in[4].name << "]>=" << _ports_out[4].type_size << ")?" - << _ports_in[5].name << "[(BITSIZE_" << _ports_in[5].name << ")*ii+:BITSIZE_" << _ports_in[5].name - << "]:(" << _ports_out[4].name << "^((((BITSIZE_" << _ports_in[5].name << ">" << _ports_out[4].type_size - << "?" << _ports_in[5].name << "[(BITSIZE_" << _ports_in[5].name << ")*ii+:BITSIZE_" - << _ports_in[5].name << "]:{{(" << _ports_out[4].type_size << "< BITSIZE_" << _ports_in[5].name - << " ? 1 : " << _ports_out[4].type_size << "-BITSIZE_" << _ports_in[5].name << "){1'b0}}," - << _ports_in[5].name << "[(BITSIZE_" << _ports_in[5].name << ")*ii+:BITSIZE_" << _ports_in[5].name - << "]})<<{" << _ports_in[6].name << "_0[" << log2nbyte << "*ii+:" << log2nbyte << "],3'b0})^" - << _ports_out[4].name << ") & (((" << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name - << ")*ii+:BITSIZE_" << _ports_in[4].name << "]+{" << _ports_in[6].name << "_0[" << log2nbyte - << "*ii+:" << log2nbyte << "],3'b0})>" << _ports_out[4].type_size << ") ? ((({(" - << _ports_out[4].type_size << "){1'b1}})>>({" << _ports_in[6].name << "_0[" << log2nbyte - << "*ii+:" << log2nbyte << "],3'b0}))<<({" << _ports_in[6].name << "_0[" << log2nbyte - << "*ii+:" << log2nbyte << "],3'b0})) : ((((({(" << _ports_out[4].type_size << "){1'b1}})>>({" - << _ports_in[6].name << "_0[" << log2nbyte << "*ii+:" << log2nbyte << "],3'b0}))<<({" - << _ports_in[6].name << "_0[" << log2nbyte << "*ii+:" << log2nbyte << "],3'b0}))<<(" - << _ports_out[4].type_size << "-" << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name - << ")*ii+:BITSIZE_" << _ports_in[4].name << "]-{" << _ports_in[6].name << "_0[" << log2nbyte - << "*ii+:" << log2nbyte << "],3'b0}))>>(" << _ports_out[4].type_size << "-" << _ports_in[4].name - << "[(BITSIZE_" << _ports_in[4].name << ")*ii+:BITSIZE_" << _ports_in[4].name << "]-{" - << _ports_in[6].name << "_0[" << log2nbyte << "*ii+:" << log2nbyte << "],3'b0})))));\n"; - else - std::cout << " " << _ports_out[4].name << " = (" << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name - << ")*ii+:BITSIZE_" << _ports_in[4].name << "]>=" << _ports_out[4].type_size << ")?" - << _ports_in[5].name << "[(BITSIZE_" << _ports_in[5].name << ")*ii+:BITSIZE_" << _ports_in[5].name - << "]:(" << _ports_out[4].name << "^((((BITSIZE_" << _ports_in[5].name << ">" << _ports_out[4].type_size - << "?" << _ports_in[5].name << "[(BITSIZE_" << _ports_in[5].name << ")*ii+:BITSIZE_" - << _ports_in[5].name << "]:{{(" << _ports_out[4].type_size << "< BITSIZE_" << _ports_in[5].name - << " ? 1 : " << _ports_out[4].type_size << "-BITSIZE_" << _ports_in[5].name << "){1'b0}}," - << _ports_in[5].name << "[(BITSIZE_" << _ports_in[5].name << ")*ii+:BITSIZE_" << _ports_in[5].name - << "]}))^" << _ports_out[4].name << ") & (((" << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name - << ")*ii+:BITSIZE_" << _ports_in[4].name << "])>" << _ports_out[4].type_size << ") ? ((({(" - << _ports_out[4].type_size << "){1'b1}}))) : ((((({(" << _ports_out[4].type_size << "){1'b1}})))<<(" - << _ports_out[4].type_size << "-" << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name - << ")*ii+:BITSIZE_" << _ports_in[4].name << "]))>>(" << _ports_out[4].type_size << "-" - << _ports_in[4].name << "[(BITSIZE_" << _ports_in[4].name << ")*ii+:BITSIZE_" << _ports_in[4].name - << "])))));\n"; - std::cout << " end\n"; - std::cout << "end\n"; -} +)"; + +std::cout << "assign " << _ports_out[AWID].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[AWLOCK].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[AWCACHE].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[AWPROT].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[AWQOS].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[AWREGION].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[AWUSER].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[WID].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[WUSER].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARID].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARLOCK].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARCACHE].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARPROT].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARQOS].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARREGION].name << " = 'b0;\n"; +std::cout << "assign " << _ports_out[ARUSER].name << " = 'b0;\n"; + +std::cout << R"( +localparam [2:0] S_IDLE = 3'b000, + S_RD_BURST = 3'b001, + S_WR_BURST = 3'b101; +)"; + +std::cout << R"( +reg [2:0] _present_state, _next_state; +)"; +std::cout << "reg [BITSIZE_" + _ports_out[AWADDR].name + "+(-1):0] axi_awaddr, next_axi_awaddr;\n"; +std::cout << "reg [BITSIZE_" + _ports_out[ARADDR].name + "+(-1):0] axi_araddr, next_axi_araddr;\n"; +std::cout << "reg [BITSIZE_" + _ports_out[WDATA].name + "+(-1):0] axi_wdata, next_axi_wdata;\n"; +std::cout << "reg [2:0] AWSIZE, next_AWSIZE;\n"; +std::cout << "reg [(BITSIZE_" + _ports_out[WDATA].name + "/8)+(-1):0] WSTRB, next_WSTRB;\n"; +std::cout << "reg [1:0] AWBURST, next_AWBURST;\n"; +std::cout << "reg [7:0] AWLEN, next_AWLEN;\n"; +std::cout << "reg AWREADY, next_AWREADY;\n"; +std::cout << "reg [2:0] ARSIZE, next_ARSIZE;\n"; +std::cout << "reg [1:0] ARBURST, next_ARBURST;\n"; +std::cout << "reg [7:0] ARLEN, next_ARLEN;\n"; +/* This register will most likely be oversized. The actual size would be the logarithm of the size of WDATA in bytes, + * but I don't think that it's possible to use the log when declaring a reg */ +std::cout << "reg [(BITSIZE_" + _ports_out[WDATA].name + "/8)+(-1):0] misalignment;\n"; +std::cout << "reg [(BITSIZE_" + _ports_out[WDATA].name + ")+(-1):0] read_mask, next_read_mask;\n"; + +std::cout << R"( +reg axi_awvalid, next_axi_awvalid; +reg axi_wlast, next_axi_wlast; +reg axi_wvalid, next_axi_wvalid; +reg axi_bready, next_axi_bready; +reg axi_arvalid, next_axi_arvalid; +reg axi_rready, next_axi_rready; + +reg first_read, next_first_read; + +reg acc_done, next_acc_done; +)"; +std::cout << "reg [BITSIZE_" + _ports_in[RDATA].name + "+(-1):0] acc_rdata, next_acc_rdata;\n"; + +std::cout << "generate\n"; +std::cout << " assign " << _ports_out[AWLEN].name << " = AWLEN;\n"; +std::cout << " assign " << _ports_out[AWSIZE].name << " = AWSIZE;\n"; +std::cout << " assign " << _ports_out[AWBURST].name << " = AWBURST;\n"; +std::cout << " assign " << _ports_out[WSTRB].name << " = WSTRB;\n"; +std::cout << " assign " << _ports_out[ARLEN].name << " = ARLEN;\n"; +std::cout << " assign " << _ports_out[ARSIZE].name << " = ARSIZE;\n"; +std::cout << " assign " << _ports_out[ARBURST].name << " = ARBURST;\n"; +std::cout << "endgenerate\n"; + +// Assign reg values +std::cout << "assign " << _ports_out[AWADDR].name << " = axi_awaddr;\n"; +std::cout << "assign " << _ports_out[AWVALID].name << " = axi_awvalid;\n"; +std::cout << "assign " << _ports_out[WDATA].name << " = axi_wdata;\n"; +std::cout << "assign " << _ports_out[WLAST].name << " = axi_wlast;\n"; +std::cout << "assign " << _ports_out[WVALID].name << " = axi_wvalid;\n"; +std::cout << "assign " << _ports_out[BREADY].name << " = axi_bready;\n"; +std::cout << "assign " << _ports_out[ARADDR].name << " = axi_araddr;\n"; +std::cout << "assign " << _ports_out[ARVALID].name << " = axi_arvalid;\n"; +std::cout << "assign " << _ports_out[RREADY].name << " = axi_rready;\n"; +std::cout << R"( +assign done_port = acc_done; +assign out1 = acc_done ? acc_rdata : 'b0; + +initial begin + _present_state = S_IDLE; + axi_awaddr = 'b0; + axi_awvalid = 1'b0; + axi_wdata = 'b0; + axi_wlast = 1'b0; + axi_wvalid = 1'b0; + axi_bready = 1'b0; + axi_araddr = 'b0; + axi_arvalid = 1'b0; + axi_rready = 1'b0; + acc_done = 1'b0; + acc_rdata = 'b0; + AWLEN = 'b0; + AWBURST = 'b0; + ARLEN = 'b0; + ARBURST = 'b0; +end + +always @(*) begin + _next_state = S_IDLE; + next_axi_awaddr = axi_awaddr; + next_axi_awvalid = axi_awvalid; + next_axi_wdata = 'b0; + next_axi_wlast = 1'b0; + next_axi_wvalid = 1'b0; + next_axi_bready = 1'b0; + next_axi_araddr = axi_araddr; + next_axi_arvalid = 1'b0; + next_axi_rready = 1'b0; + next_acc_done = acc_done; + next_acc_rdata = acc_rdata; + next_AWSIZE = AWSIZE; + next_AWBURST = AWBURST; + next_AWLEN = AWLEN; + next_ARSIZE = ARSIZE; + next_ARBURST = ARBURST; + next_ARLEN = ARLEN; + misalignment = 0; + next_first_read = first_read; + next_read_mask = read_mask; + next_AWREADY = AWREADY; + next_WSTRB = WSTRB; + + case (_present_state) + S_IDLE: begin + next_axi_awaddr = 'b0; + next_axi_awvalid = 1'b0; + next_axi_wdata = 'b0; + next_axi_wvalid = 1'b0; + next_axi_bready = 1'b1; + next_axi_araddr = 'b0; + next_axi_arvalid = 1'd0; + next_axi_rready = 1'b1; + next_acc_done = 1'b0; + next_acc_rdata = 'b0; + next_AWSIZE = 'b0; + next_AWBURST = 'b0; + next_AWLEN = 'b0; + next_WSTRB = 'b0; + next_ARSIZE = 'b0; + next_ARBURST = 'b0; + next_ARLEN = 'b0; + next_first_read = 'b0; + next_read_mask = 'b0; + next_acc_rdata = 'b0; + next_AWREADY = 'b0; +)"; +std::cout << " if (" << _ports_in[start_port].name << " && !" << _ports_in[in1].name << ") begin\n"; +std::cout << R"( `ifdef _SIM_HAVE_CLOG2 + next_ARSIZE = $clog2(in2 / 8); + `else + next_ARSIZE = `CLOG2(in2 / 8); + `endif + next_axi_bready = 1'b0; + next_axi_rready = 1'b1; +)"; +std::cout << " next_first_read = 1'b1;\n"; +std::cout << " next_axi_araddr = " << _ports_in[in4].name << ";\n"; +std::cout << " misalignment = " << _ports_in[in4].name << " % (1 << next_ARSIZE);\n"; +std::cout << " if(misalignment > 'b0) begin\n"; +std::cout << " next_ARLEN = 'b1;\n"; +std::cout << " next_ARBURST = 'b1;\n"; +std::cout << " next_read_mask = -(1 << (misalignment * 8));\n"; +std::cout << " end else begin\n"; +std::cout << " next_ARLEN = 'b0;\n"; +std::cout << " next_ARBURST = 'b0;\n"; +std::cout << " end\n"; +std::cout << " next_axi_arvalid = 1'b1;\n"; +std::cout << " _next_state = S_RD_BURST;\n"; +std::cout << " end else if (" << _ports_in[start_port].name << " && " << _ports_in[in1].name << ") begin\n"; +std::cout << " next_axi_awaddr = " << _ports_in[in4].name << ";\n"; +std::cout << " next_axi_awvalid = 1'b1;\n"; +std::cout << " `ifdef _SIM_HAVE_CLOG2\n"; +std::cout << " next_AWSIZE = $clog2(in2 / 8);\n"; +std::cout << " `else\n"; +std::cout << " next_AWSIZE = `CLOG2(in2 / 8);\n"; +std::cout << " `endif\n"; +/* Compute the misalignment, assert all the bits to the left of the misaligned one */ +std::cout << " misalignment = " << _ports_in[in4].name << " % (1 << next_AWSIZE);\n"; +std::cout << " next_WSTRB = -(1 << misalignment);\n"; +std::cout << " next_axi_wdata = " << _ports_in[in3].name << ";\n"; +std::cout << R"( next_axi_wvalid = 1'b1; + next_axi_wlast = !(misalignment > 'b0); + if(next_axi_wlast) begin + next_AWBURST = 2'b00; + next_AWLEN = 8'b00000000; + end else begin + next_AWBURST = 2'b01; + next_AWLEN = 8'b00000001; + end + next_axi_rready = 1'b0; + _next_state = S_WR_BURST; + end else begin + _next_state = S_IDLE; + end + end + + S_RD_BURST: begin +)"; +std::cout << " if(" << _ports_in[ARREADY].name << ") begin\n"; +std::cout << R"( next_axi_arvalid = 1'b0; + next_ARSIZE = 'b0; + next_ARBURST = 'b0; + next_ARLEN = 'b0; + next_axi_araddr = 'b0; + next_axi_arvalid = 1'b0; + end + else begin + next_axi_arvalid = axi_arvalid; + next_axi_araddr = axi_araddr; + end + _next_state = S_RD_BURST; + next_axi_rready = 1'b1; + +)"; +std::cout << " if(" << _ports_in[RVALID].name << ") begin\n"; +std::cout << " if(" << _ports_in[RLAST].name << ") begin\n"; +std::cout << " next_acc_rdata = next_acc_rdata + (" << _ports_in[RDATA].name << " & (~read_mask));\n"; +std::cout << " next_axi_rready = 1'b0;\n"; +std::cout << " next_acc_done = 1'b1;\n"; +std::cout << " _next_state = S_IDLE;\n"; +std::cout << " end else if (first_read) begin\n"; +std::cout << " next_acc_rdata = " << _ports_in[RDATA].name << " & read_mask;\n"; +std::cout << R"( next_acc_done = 1'b0; + next_first_read = 1'b0; + _next_state = S_RD_BURST; + end + end else begin + _next_state = S_RD_BURST; + end + end + + S_WR_BURST : begin + _next_state = S_WR_BURST; +)"; +std::cout << " if(!" << _ports_in[WREADY].name << ") begin\n"; +std::cout << " next_axi_wvalid = axi_wvalid;\n"; +std::cout << " next_axi_wlast = axi_wlast;\n"; +std::cout << " next_axi_wdata = axi_wdata;\n"; +std::cout << " end\n"; +std::cout << " if(" << _ports_in[AWREADY].name << ") begin"; +std::cout << R"( + next_AWSIZE = 'b0; + next_AWBURST = 'b0; + next_AWLEN = 'b0; + next_axi_awvalid = 'b0; + next_axi_awaddr = 'b0; + next_AWREADY = 1'b1; + end +)"; + +std::cout << " if (next_AWREADY &&" << _ports_in[WREADY].name << " && !WSTRB[0]) begin"; +std::cout << R"( + /* If the last transfer was not aligned and the slave is ready, transfer the rest */ + next_WSTRB = ~WSTRB; + next_axi_wdata = axi_wdata; + next_axi_wvalid = 1'b1; + next_axi_wlast = 1'b1; + end + else if (next_AWREADY && !WSTRB[0]) begin + /* If it's an aligned transfer but the slave is not ready, just keep the signals */ + next_axi_wdata = axi_wdata; + next_axi_wvalid = axi_wvalid; + next_WSTRB = WSTRB; + next_axi_wlast = axi_wlast; + end + if(!next_AWREADY) begin + next_axi_awvalid = axi_awvalid; + next_axi_awaddr = axi_awaddr; + next_axi_wvalid = axi_wvalid; + next_axi_wdata = axi_wdata; + end + /* If the last transfer was complete, deassert the validity bits and check if you can go back to + IDLE */ +)"; +std::cout << " if (" << _ports_in[BVALID].name << ") begin"; +std::cout << R"( next_acc_done = 1'b1; + next_axi_wvalid = 1'b0; + next_axi_wdata = 'b0; + next_WSTRB = 'b0; + next_axi_wlast = 1'b0; + _next_state = S_IDLE; + end + end + endcase +end + +always @(posedge clock) begin + _present_state <= _next_state; + + axi_awaddr <= next_axi_awaddr; + axi_awvalid <= next_axi_awvalid; + axi_wdata <= next_axi_wdata; + axi_wlast <= next_axi_wlast; + axi_wvalid <= next_axi_wvalid; + axi_bready <= next_axi_bready; + axi_araddr <= next_axi_araddr; + axi_arvalid <= next_axi_arvalid; + axi_rready <= next_axi_rready; + acc_done <= next_acc_done; + acc_rdata <= next_acc_rdata; + AWSIZE <= next_AWSIZE; + AWBURST <= next_AWBURST; + AWLEN <= next_AWLEN; + WSTRB <= next_WSTRB; + ARSIZE <= next_ARSIZE; + ARBURST <= next_ARBURST; + ARLEN <= next_ARLEN; + first_read <= next_first_read; + read_mask <= next_read_mask; + AWREADY <= next_AWREADY; + + if (!reset) begin + _present_state <= S_IDLE; + end +end)"; diff --git a/etc/lib/technology/dynamic_generators/Read_axis.cpp b/etc/lib/technology/dynamic_generators/Read_axis.cpp index fa9c37a11..3ffe6c138 100644 --- a/etc/lib/technology/dynamic_generators/Read_axis.cpp +++ b/etc/lib/technology/dynamic_generators/Read_axis.cpp @@ -47,7 +47,7 @@ std::cout << "reg [PORTSIZE_" << _ports_out[1].name << "-1:0] " << _ports_out[0] std::cout << "always @(*)\n"; std::cout << " for(ii=0; ii + + + + + \ No newline at end of file diff --git a/panda_regressions/hls/bambu_specific_test4/simple4_axi_m.c b/panda_regressions/hls/bambu_specific_test4/simple4_axi_m.c new file mode 100644 index 000000000..17b105f9e --- /dev/null +++ b/panda_regressions/hls/bambu_specific_test4/simple4_axi_m.c @@ -0,0 +1,21 @@ +#pragma HLS_interface a m_axi direct +#pragma HLS_interface n_ptr m_axi direct +#pragma HLS_interface res m_axi direct + +void maxNumbers(int* a, unsigned int* n_ptr, int* res) + +{ + unsigned i; + int result; + unsigned int n = *n_ptr; + + if(n == 0) + { + *res = (int)(1 << 31); + return; + } + result = a[0]; + for(i = 1; i < n; ++i) + result = result < a[i] ? a[i] : result; + *res = result; +} \ No newline at end of file diff --git a/panda_regressions/hls/bambu_specific_test4/simple4_axi_tb.xml b/panda_regressions/hls/bambu_specific_test4/simple4_axi_tb.xml new file mode 100644 index 000000000..f254d9d30 --- /dev/null +++ b/panda_regressions/hls/bambu_specific_test4/simple4_axi_tb.xml @@ -0,0 +1,5 @@ + + + + + \ No newline at end of file diff --git a/panda_regressions/hls/bambu_specific_test4/simple_axi_m.c b/panda_regressions/hls/bambu_specific_test4/simple_axi_m.c new file mode 100644 index 000000000..87eae6758 --- /dev/null +++ b/panda_regressions/hls/bambu_specific_test4/simple_axi_m.c @@ -0,0 +1,13 @@ +#pragma HLS_interface a m_axi direct bundle=common +#pragma HLS_interface n_ptr m_axi direct bundle=common +short maxNumbers(short *a, unsigned short *n_ptr) +{ + unsigned i; + short res; + unsigned short n =*n_ptr; + if(n==0) return (short)(1u << 15); + res = a[0]; + for(i=1;iwrite(HDL_manager::convert_to_identifier(writer.get(), port_name) + ";\n"); + /* Add next_* to any input AXI signals */ + if(GetPointer(port_obj)->get_port_interface() >= port_o::port_interface::M_AXI_AWVALID && + GetPointer(port_obj)->get_port_interface() <= port_o::port_interface::M_AXI_BUSER) + { + std::string ptName = HDL_manager::convert_to_identifier(writer.get(), port_name); + writer->write(ptName + ", next_" + ptName + ";\n"); + } + else + { + writer->write(HDL_manager::convert_to_identifier(writer.get(), port_name) + ";\n"); + } if(port_obj->get_typeRef()->treenode > 0 && tree_helper::IsPointerType(TreeM->CGetTreeReindex(port_obj->get_typeRef()->treenode))) { diff --git a/src/HLS/simulation/testbench_generation_base_step.cpp b/src/HLS/simulation/testbench_generation_base_step.cpp index bcc792370..19694fba1 100644 --- a/src/HLS/simulation/testbench_generation_base_step.cpp +++ b/src/HLS/simulation/testbench_generation_base_step.cpp @@ -539,7 +539,8 @@ void TestbenchGenerationBaseStep::write_output_checks(const tree_managerConstRef auto InterfaceType = GetPointer(portInst)->get_port_interface(); if(InterfaceType == port_o::port_interface::PI_DOUT) { - const auto manage_pidout = [&](const std::string& portID) { + const auto manage_pidout = [&](const std::string& portID) + { auto port_name = portInst->get_id(); auto terminate = port_name.size() > 3 ? port_name.size() - std::string("_d" + portID).size() : 0; THROW_ASSERT(port_name.substr(terminate) == "_d" + portID, "inconsistent interface"); @@ -639,7 +640,8 @@ void TestbenchGenerationBaseStep::write_output_checks(const tree_managerConstRef auto InterfaceType = GetPointer(portInst)->get_port_interface(); if(InterfaceType == port_o::port_interface::PI_DIN) { - const auto manage_pidin = [&](const std::string& portID) { + const auto manage_pidin = [&](const std::string& portID) + { auto port_name = portInst->get_id(); auto terminate = port_name.size() > 3 ? port_name.size() - std::string("_q" + portID).size() : 0; THROW_ASSERT(port_name.substr(terminate) == "_q" + portID, "inconsistent interface"); @@ -2197,11 +2199,29 @@ void TestbenchGenerationBaseStep::write_auxiliary_signal_declaration() const writer->write("\n"); } } + + /* Check if AWADDR ports are present. If there are, declare a variable to store the last valid AWADDR for each bundle + */ + if(mod->get_out_port_size()) + { + for(unsigned int i = 0; i < mod->get_out_port_size(); i++) + { + const structural_objectRef& port = mod->get_out_port(i); + if(GetPointer(port)->get_port_interface() == port_o::port_interface::M_AXI_AWADDR) + { + unsigned int bitsize = + GetPointer(port)->get_typeRef()->size * GetPointer(port)->get_typeRef()->vector_size; + writer->write("reg [" + STR(bitsize - 1) + ":0] last_" + GetPointer(port)->get_id() + ";\n"); + } + } + } + writer->write("reg [7:0] _bambu_testbench_mem_ [0:MEMSIZE-1];\n\n"); writer->write("reg [7:0] _bambu_databyte_;\n\n"); writer->write("reg [3:0] __state, __next_state;\n"); writer->write("reg start_results_comparison;\n"); writer->write("reg next_start_port;\n"); + writer->write("integer currTime;\n"); } void TestbenchGenerationBaseStep::begin_initial_block() const @@ -2376,15 +2396,18 @@ void TestbenchGenerationBaseStep::testbench_controller_machine() const writer->write(" __next_state = 2;\n"); writer->write(" end\n"); writer->write(" 2:\n"); - writer->write(" begin\n"); - writer->write(" next_start_port = 1;\n"); - writer->write(" if (done_port == 1'b1)\n"); - writer->write(" begin\n"); - writer->write(" __next_state = 4;\n"); - writer->write(" end\n"); - writer->write(" else\n"); - writer->write(" __next_state = 3;\n"); - writer->write(" end\n"); + writer->write(" if(currTime > 100)\n"); + writer->write(" begin\n"); + writer->write(" next_start_port = 1;\n"); + writer->write(" if (done_port == 1'b1)\n"); + writer->write(" begin\n"); + writer->write(" __next_state = 4;\n"); + writer->write(" end\n"); + writer->write(" else\n"); + writer->write(" __next_state = 3;\n"); + writer->write(" end\n"); + writer->write(" else\n"); + writer->write(" __next_state = 2;\n"); writer->write(" 3:\n"); writer->write(" if (done_port == 1'b1)\n"); writer->write(" begin\n"); @@ -2424,6 +2447,100 @@ void TestbenchGenerationBaseStep::testbench_controller_machine() const writer->write(" __state <= __next_state;\n"); writer->write(" start_port <= next_start_port;\n"); writer->write(" end\n"); + + /* Look for AWADDR ports. For every port, write the AXI signals controller */ + std::string portPrefix; + if(mod->get_out_port_size()) + { + for(unsigned int i = 0; i < mod->get_out_port_size(); i++) + { + const structural_objectRef& port = mod->get_out_port(i); + if(GetPointer(port)->get_port_interface() == port_o::port_interface::M_AXI_AWADDR) + { + std::string portSpecializer = "AWADDR"; + std::string::size_type index = GetPointer(port)->get_id().find(portSpecializer); + if(index != std::string::npos) + { + portPrefix = GetPointer(port)->get_id(); + portPrefix.erase(index, portSpecializer.length()); + } + writer->write("always @(*) begin\n"); + writer->write(" next_" + portPrefix + "ARREADY = 1'b1;\n"); + writer->write(" next_" + portPrefix + "RDATA = 'b0;\n"); + writer->write(" next_" + portPrefix + "AWREADY = 1'b1;\n"); + writer->write(" next_" + portPrefix + "BVALID = 1'b0;\n"); + writer->write(" next_" + portPrefix + "RLAST = 1'b0;\n"); + writer->write(" next_" + portPrefix + "RVALID = 1'b0;\n"); + writer->write(" next_" + portPrefix + "WREADY = 1'b1;\n"); + writer->write(" if (" + portPrefix + "ARVALID == 1'b1) begin\n"); + { + /* Compute aggregate memory for RDATA */ + const structural_objectRef& portRDATA = mod->find_member(portPrefix + "RDATA", port_o_K, cir); + const unsigned int bitsizeRDATA = GetPointer(portRDATA)->get_typeRef()->size * + GetPointer(portRDATA)->get_typeRef()->vector_size; + + std::string mem_aggregated; + + mem_aggregated = "{"; + for(unsigned int bitsize_index = 0; bitsize_index < bitsizeRDATA; bitsize_index = bitsize_index + 8) + { + if(bitsize_index) + { + mem_aggregated += ", "; + } + mem_aggregated += "_bambu_testbench_mem_[" + portPrefix + "ARADDR + " + + STR((bitsizeRDATA - bitsize_index) / 8 - 1) + " - base_addr]"; + } + mem_aggregated += "}"; + + writer->write(" next_" + portPrefix + "RDATA = " + mem_aggregated + ";\n"); + writer->write(" next_" + portPrefix + "RLAST = 1'b1;\n"); + writer->write(" next_" + portPrefix + "RVALID = 1'b1;\n"); + } + writer->write(" end\n"); + + writer->write(" if (" + portPrefix + "AWVALID == 1'b1) begin\n"); + writer->write(" last_" + portPrefix + "AWADDR = " + portPrefix + "AWADDR;\n"); + writer->write(" end\n"); + writer->write(" if (" + portPrefix + "WVALID == 1'b1) begin\n"); + { + /* Compute aggregate memory for WDATA */ + const structural_objectRef& portWDATA = mod->find_member(portPrefix + "WDATA", port_o_K, cir); + const unsigned int bitsizeWDATA = GetPointer(portWDATA)->get_typeRef()->size * + GetPointer(portWDATA)->get_typeRef()->vector_size; + + std::string mem_aggregated = "{"; + for(unsigned int bitsize_index = 0; bitsize_index < bitsizeWDATA; bitsize_index = bitsize_index + 8) + { + if(bitsize_index) + { + mem_aggregated += ", "; + } + mem_aggregated += "_bambu_testbench_mem_[last_" + portPrefix + "AWADDR + " + + STR((bitsizeWDATA - bitsize_index) / 8 - 1) + " - base_addr]"; + } + mem_aggregated += "}"; + + writer->write(" " + mem_aggregated + " = " + portPrefix + "WDATA;\n"); + writer->write(" if (" + portPrefix + "WLAST == 1'b1) begin\n"); + writer->write(" next_" + portPrefix + "BVALID = 1'b1;\n"); + writer->write(" end\n"); + } + writer->write(" end\n"); + writer->write("end\n\n"); + + writer->write("always@(posedge " CLOCK_PORT_NAME ") begin\n"); + writer->write(" " + portPrefix + "ARREADY = next_" + portPrefix + "ARREADY;\n"); + writer->write(" " + portPrefix + "RDATA = next_" + portPrefix + "RDATA;\n"); + writer->write(" " + portPrefix + "AWREADY = next_" + portPrefix + "AWREADY;\n"); + writer->write(" " + portPrefix + "BVALID = next_" + portPrefix + "BVALID;\n"); + writer->write(" " + portPrefix + "RLAST = next_" + portPrefix + "RLAST;\n"); + writer->write(" " + portPrefix + "RVALID = next_" + portPrefix + "RVALID;\n"); + writer->write(" " + portPrefix + "WREADY = next_" + portPrefix + "WREADY;\n"); + writer->write("end\n"); + } + } + } } void TestbenchGenerationBaseStep::memory_initialization() const @@ -2441,6 +2558,7 @@ void TestbenchGenerationBaseStep::write_max_simulation_time_control() const writer->write("always @(posedge " CLOCK_PORT_NAME ")\n"); writer->write(STR(STD_OPENING_CHAR)); writer->write("begin\n"); + writer->write("currTime = $time;\n"); writer->write("if (($time - startTime)/`CLOCK_PERIOD > `SIMULATION_LENGTH)\n"); writer->write(STR(STD_OPENING_CHAR)); writer->write("begin\n"); diff --git a/src/design_flows/backend/ToC/source_code_writers/hls_c_writer.cpp b/src/design_flows/backend/ToC/source_code_writers/hls_c_writer.cpp index 4f18e233e..2dc6ef746 100644 --- a/src/design_flows/backend/ToC/source_code_writers/hls_c_writer.cpp +++ b/src/design_flows/backend/ToC/source_code_writers/hls_c_writer.cpp @@ -715,7 +715,10 @@ void HLSCWriter::WriteExpectedResults(const BehavioralHelperConstRef behavioral_ std::string fname; tree_helper::get_mangled_fname(fd, fname); auto& DesignInterfaceTypename = hls_c_backend_information->HLSMgr->design_interface_typename; + auto& DesignInterfaceSpecifier = hls_c_backend_information->HLSMgr->design_interface; bool hasInterface = DesignInterfaceTypename.find(fname) != DesignInterfaceTypename.end(); + bool hasSpecifier = DesignInterfaceSpecifier.find(fname) != DesignInterfaceSpecifier.end(); + bool is_fortran = (Param->isOption(OPT_input_format) && Param->getOption(OPT_input_format) == Parameters_FileFormat::FF_FORTRAN); @@ -863,7 +866,40 @@ void HLSCWriter::WriteExpectedResults(const BehavioralHelperConstRef behavioral_ } else { - if(splitted.size() == 1 && flag_cpp && reference_type_p) + std::string interfaceSpecifier = ""; + if(hasSpecifier) + { + interfaceSpecifier = DesignInterfaceSpecifier.at(fname).at(param); + } + /* m_axi interfaces require writing the full results in a row, not a single byte */ + if(interfaceSpecifier == "m_axi") + { + /// Retrieve the space to be reserved in memory + const auto pointedType_node = tree_helper::CGetPointedType(pt_node); + const auto reserved_mem_bytes = + hls_c_backend_information->HLSMgr->RSim->param_mem_size.at(v_idx).at(GET_INDEX_CONST_NODE(par)); + INDENT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, + "---Reserved memory " + STR(reserved_mem_bytes) + " bytes"); + const auto element_size = tree_helper::Size(pointedType_node) / 8; + THROW_ASSERT(reserved_mem_bytes % element_size == 0, + STR(reserved_mem_bytes) + "/" + STR(element_size)); + const auto num_elements = reserved_mem_bytes / element_size; + THROW_ASSERT(num_elements, STR(reserved_mem_bytes) + "/" + STR(element_size)); + indented_output_stream->Append("{\n"); + if(num_elements > 1 || !reference_type_p) + { + indented_output_stream->Append("for(unsigned int i0 = 0; i0 < " + STR(num_elements) + "; i0++)\n"); + indented_output_stream->Append("{\n"); + } + WriteParamInMemory(behavioral_helper, param + (reference_type_p ? "" : "[i0]"), + pointedType_node->index, 1, false); + if(num_elements > 1 || !reference_type_p) + { + indented_output_stream->Append("}\n"); + } + indented_output_stream->Append("}\n"); + } + else if(splitted.size() == 1 && flag_cpp && reference_type_p) { if(output_level > OUTPUT_LEVEL_MINIMUM) { @@ -1089,7 +1125,8 @@ void HLSCWriter::WriteSimulatorInitMemory(const unsigned int function_id) } /// Retrieve the space to be reserved in memory - const auto reserved_mem_bytes = [&]() -> size_t { + const auto reserved_mem_bytes = [&]() -> size_t + { if(is_memory) { const auto ret_value = tree_helper::Size(TM->CGetTreeReindex(l)) / 8; @@ -1113,7 +1150,8 @@ void HLSCWriter::WriteSimulatorInitMemory(const unsigned int function_id) std::string bits_offset = ""; std::vector splitted = SplitString(test_v, ","); INDENT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, "---Processing c++ init " + test_v); - const auto isAllZero = [&]() -> bool { + const auto isAllZero = [&]() -> bool + { if(splitted.size() == 0) { return false; diff --git a/src/frontend_analysis/IR_analysis/FunctionInterfaceInfer.cpp b/src/frontend_analysis/IR_analysis/FunctionInterfaceInfer.cpp index 2ffbd7727..c3d73c4d7 100644 --- a/src/frontend_analysis/IR_analysis/FunctionInterfaceInfer.cpp +++ b/src/frontend_analysis/IR_analysis/FunctionInterfaceInfer.cpp @@ -1149,250 +1149,258 @@ void FunctionInterfaceInfer::create_resource_m_axi(const std::set& unsigned n_resources, m_axi_type mat, unsigned rwBWsize) { const auto ResourceName = ENCODE_FDNAME(portNameSpecializer, "", ""); - auto HLSMgr = GetPointer(AppM); - auto HLS_T = HLSMgr->get_HLS_target(); - const auto device_type = HLS_T->get_target_device()->get_type(); - const auto set_op_time = [&](operation* op) { - op->time_m = time_model::create_model(device_type, parameters); - op->bounded = false; - op->time_m->set_execution_time(HLS_T->get_technology_manager()->CGetSetupHoldTime() + EPSILON, 0); - op->time_m->set_synthesis_dependent(true); - }; - auto TechMan = HLS_T->get_technology_manager(); + THROW_ASSERT(GetPointer(AppM), ""); + const auto HLSMgr = GetPointerS(AppM); + const auto HLS_T = HLSMgr->get_HLS_target(); + const auto TechMan = HLS_T->get_technology_manager(); if(!TechMan->is_library_manager(INTERFACE_LIBRARY) || !TechMan->get_library_manager(INTERFACE_LIBRARY)->is_fu(ResourceName)) { INDENT_DBG_MEX(DEBUG_LEVEL_PEDANTIC, debug_level, "-->Creating interface resource: " + INTERFACE_LIBRARY + ":" + ResourceName); - structural_managerRef CM = structural_managerRef(new structural_manager(parameters)); - structural_type_descriptorRef module_type = - structural_type_descriptorRef(new structural_type_descriptor(ResourceName)); + const structural_managerRef CM(new structural_manager(parameters)); + const structural_type_descriptorRef module_type(new structural_type_descriptor(ResourceName)); CM->set_top_info(ResourceName, module_type); - auto interface_top = CM->get_circ(); + const auto interface_top = CM->get_circ(); /// add description and license - GetPointer(interface_top)->set_description("Interface module for function: " + ResourceName); - GetPointer(interface_top)->set_copyright(GENERATED_COPYRIGHT); - GetPointer(interface_top)->set_authors("Component automatically generated by bambu"); - GetPointer(interface_top)->set_license(GENERATED_LICENSE); - GetPointer(interface_top)->set_multi_unit_multiplicity(n_resources); + GetPointerS(interface_top)->set_description("Interface module for function: " + ResourceName); + GetPointerS(interface_top)->set_copyright(GENERATED_COPYRIGHT); + GetPointerS(interface_top)->set_authors("Component automatically generated by bambu"); + GetPointerS(interface_top)->set_license(GENERATED_LICENSE); + GetPointerS(interface_top)->set_multi_unit_multiplicity(n_resources); - unsigned int address_bitsize = HLSMgr->get_address_bitsize(); - structural_type_descriptorRef address_interface_type = - structural_type_descriptorRef(new structural_type_descriptor("bool", address_bitsize)); - structural_type_descriptorRef Intype = - structural_type_descriptorRef(new structural_type_descriptor("bool", inputBitWidth)); - structural_type_descriptorRef size1 = structural_type_descriptorRef(new structural_type_descriptor("bool", 1)); - auto nbitDataSize = 32u - static_cast(__builtin_clz(rwBWsize)); - structural_type_descriptorRef rwsize = - structural_type_descriptorRef(new structural_type_descriptor("bool", nbitDataSize)); - structural_type_descriptorRef rwtype = - structural_type_descriptorRef(new structural_type_descriptor("bool", rwBWsize)); - structural_type_descriptorRef idType = structural_type_descriptorRef(new structural_type_descriptor("bool", 1)); - structural_type_descriptorRef lenType = structural_type_descriptorRef(new structural_type_descriptor("bool", 8)); - structural_type_descriptorRef sizeType = structural_type_descriptorRef(new structural_type_descriptor("bool", 3)); - structural_type_descriptorRef burstType = - structural_type_descriptorRef(new structural_type_descriptor("bool", 2)); - structural_type_descriptorRef lockType = structural_type_descriptorRef(new structural_type_descriptor("bool", 2)); - structural_type_descriptorRef cacheType = - structural_type_descriptorRef(new structural_type_descriptor("bool", 4)); - structural_type_descriptorRef protType = structural_type_descriptorRef(new structural_type_descriptor("bool", 3)); - structural_type_descriptorRef qosType = structural_type_descriptorRef(new structural_type_descriptor("bool", 4)); - structural_type_descriptorRef regionType = - structural_type_descriptorRef(new structural_type_descriptor("bool", 4)); - structural_type_descriptorRef userType = structural_type_descriptorRef(new structural_type_descriptor("bool", 1)); - structural_type_descriptorRef strbType = - structural_type_descriptorRef(new structural_type_descriptor("bool", inputBitWidth / 8)); - structural_type_descriptorRef respType = structural_type_descriptorRef(new structural_type_descriptor("bool", 2)); + const auto address_bitsize = HLSMgr->get_address_bitsize(); + const auto nbitDataSize = 32u - static_cast(__builtin_clz(rwBWsize)); + const structural_type_descriptorRef address_interface_type( + new structural_type_descriptor("bool", address_bitsize)); + const structural_type_descriptorRef Intype(new structural_type_descriptor("bool", inputBitWidth)); + const structural_type_descriptorRef size1(new structural_type_descriptor("bool", 1)); + const structural_type_descriptorRef rwsize(new structural_type_descriptor("bool", nbitDataSize)); + const structural_type_descriptorRef rwtype(new structural_type_descriptor("bool", rwBWsize)); + const structural_type_descriptorRef idType(new structural_type_descriptor("bool", 1)); + const structural_type_descriptorRef lenType(new structural_type_descriptor("bool", 8)); + const structural_type_descriptorRef sizeType(new structural_type_descriptor("bool", 3)); + const structural_type_descriptorRef burstType(new structural_type_descriptor("bool", 2)); + const structural_type_descriptorRef lockType(new structural_type_descriptor("bool", 1)); + const structural_type_descriptorRef cacheType(new structural_type_descriptor("bool", 4)); + const structural_type_descriptorRef protType(new structural_type_descriptor("bool", 3)); + const structural_type_descriptorRef qosType(new structural_type_descriptor("bool", 4)); + const structural_type_descriptorRef regionType(new structural_type_descriptor("bool", 4)); + const structural_type_descriptorRef userType(new structural_type_descriptor("bool", 1)); + const structural_type_descriptorRef strbType(new structural_type_descriptor("bool", inputBitWidth / 8)); + const structural_type_descriptorRef respType(new structural_type_descriptor("bool", 2)); + const structural_type_descriptorRef bool_type(new structural_type_descriptor("bool", 0)); + std::string param_ports; - structural_type_descriptorRef bool_type = - structural_type_descriptorRef(new structural_type_descriptor("bool", 0)); CM->add_port(CLOCK_PORT_NAME, port_o::IN, interface_top, bool_type); CM->add_port(RESET_PORT_NAME, port_o::IN, interface_top, bool_type); CM->add_port_vector(START_PORT_NAME, port_o::IN, n_resources, interface_top, bool_type); - CM->add_port_vector("in1", port_o::IN, n_resources, interface_top, - size1); // when 0 is a read otherwise is a write - CM->add_port_vector("in2", port_o::IN, n_resources, interface_top, - rwsize); // bit-width size of the written or read data - CM->add_port_vector("in3", port_o::IN, n_resources, interface_top, - rwtype); // value written when the first operand is 1, 0 otherwise - auto addrPort = - CM->add_port_vector("in4", port_o::IN, n_resources, interface_top, address_interface_type); // address + // when 0 is a read otherwise is a write + CM->add_port_vector("in1", port_o::IN, n_resources, interface_top, size1); + // bit-width size of the written or read data + CM->add_port_vector("in2", port_o::IN, n_resources, interface_top, rwsize); + // value written when the first operand is 1, 0 otherwise + CM->add_port_vector("in3", port_o::IN, n_resources, interface_top, rwtype); - GetPointer(addrPort)->set_is_addr_bus(true); - // GetPointer(addrPort)->set_is_var_args(true); /// required to activate the module generation + const auto addrPort = CM->add_port_vector("in4", port_o::IN, n_resources, interface_top, address_interface_type); + GetPointerS(addrPort)->set_is_addr_bus(true); + + const auto Port_awready = + CM->add_port("_m_axi_" + portNameSpecializer + "_AWREADY", port_o::IN, interface_top, bool_type); + GetPointerS(Port_awready)->set_port_interface(port_o::port_interface::M_AXI_AWREADY); + + const auto Port_wready = + CM->add_port("_m_axi_" + portNameSpecializer + "_WREADY", port_o::IN, interface_top, bool_type); + GetPointerS(Port_wready)->set_port_interface(port_o::port_interface::M_AXI_WREADY); + + const auto Port_bid = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_BID", port_o::IN, 1, interface_top, idType); + GetPointerS(Port_bid)->set_port_interface(port_o::port_interface::M_AXI_BID); + + const auto Port_bresp = + CM->add_port("_m_axi_" + portNameSpecializer + "_BRESP", port_o::IN, interface_top, respType); + GetPointerS(Port_bresp)->set_port_interface(port_o::port_interface::M_AXI_BRESP); + + const auto Port_buser = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_BUSER", port_o::IN, 1, interface_top, userType); + GetPointerS(Port_buser)->set_port_interface(port_o::port_interface::M_AXI_BUSER); + + const auto Port_bvalid = + CM->add_port("_m_axi_" + portNameSpecializer + "_BVALID", port_o::IN, interface_top, bool_type); + GetPointerS(Port_bvalid)->set_port_interface(port_o::port_interface::M_AXI_BVALID); + + const auto Port_arready = + CM->add_port("_m_axi_" + portNameSpecializer + "_ARREADY", port_o::IN, interface_top, bool_type); + GetPointerS(Port_arready)->set_port_interface(port_o::port_interface::M_AXI_ARREADY); + + const auto Port_rid = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_RID", port_o::IN, 1, interface_top, idType); + GetPointerS(Port_rid)->set_port_interface(port_o::port_interface::M_AXI_RID); + + const auto Port_rdata = + CM->add_port("_m_axi_" + portNameSpecializer + "_RDATA", port_o::IN, interface_top, Intype); + GetPointerS(Port_rdata)->set_port_interface(port_o::port_interface::M_AXI_RDATA); + param_ports += " _m_axi_" + portNameSpecializer + "_RDATA"; + + const auto Port_rresp = + CM->add_port("_m_axi_" + portNameSpecializer + "_RRESP", port_o::IN, interface_top, respType); + GetPointerS(Port_rresp)->set_port_interface(port_o::port_interface::M_AXI_RRESP); + + const auto Port_rlast = + CM->add_port("_m_axi_" + portNameSpecializer + "_RLAST", port_o::IN, interface_top, bool_type); + GetPointerS(Port_rlast)->set_port_interface(port_o::port_interface::M_AXI_RLAST); + + const auto Port_ruser = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_RUSER", port_o::IN, 1, interface_top, userType); + GetPointerS(Port_ruser)->set_port_interface(port_o::port_interface::M_AXI_RUSER); + + const auto Port_rvalid = + CM->add_port("_m_axi_" + portNameSpecializer + "_RVALID", port_o::IN, interface_top, bool_type); + GetPointerS(Port_rvalid)->set_port_interface(port_o::port_interface::M_AXI_RVALID); CM->add_port_vector(DONE_PORT_NAME, port_o::OUT, n_resources, interface_top, bool_type); CM->add_port_vector("out1", port_o::OUT, n_resources, interface_top, rwtype); - auto Port_awvalid = - CM->add_port("_m_axi_" + portNameSpecializer + "_AWVALID", port_o::OUT, interface_top, bool_type); - GetPointer(Port_awvalid)->set_port_interface(port_o::port_interface::M_AXI_AWVALID); - - auto Port_awready = - CM->add_port("_m_axi_" + portNameSpecializer + "_AWREADY", port_o::IN, interface_top, bool_type); - GetPointer(Port_awready)->set_port_interface(port_o::port_interface::M_AXI_AWREADY); + const auto Port_awid = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_AWID", port_o::OUT, 1, interface_top, idType); + GetPointerS(Port_awid)->set_port_interface(port_o::port_interface::M_AXI_AWID); - auto Port_awaddr = + const auto Port_awaddr = CM->add_port("_m_axi_" + portNameSpecializer + "_AWADDR", port_o::OUT, interface_top, address_interface_type); - GetPointer(Port_awaddr)->set_port_interface(port_o::port_interface::M_AXI_AWADDR); + GetPointerS(Port_awaddr)->set_port_interface(port_o::port_interface::M_AXI_AWADDR); + param_ports += " _m_axi_" + portNameSpecializer + "_AWADDR"; - auto Port_awid = CM->add_port("_m_axi_" + portNameSpecializer + "_AWID", port_o::OUT, interface_top, idType); - GetPointer(Port_awid)->set_port_interface(port_o::port_interface::M_AXI_AWID); + const auto Port_awlen = + CM->add_port("_m_axi_" + portNameSpecializer + "_AWLEN", port_o::OUT, interface_top, lenType); + GetPointerS(Port_awlen)->set_port_interface(port_o::port_interface::M_AXI_AWLEN); - auto Port_awlen = CM->add_port("_m_axi_" + portNameSpecializer + "_AWLEN", port_o::OUT, interface_top, lenType); - GetPointer(Port_awlen)->set_port_interface(port_o::port_interface::M_AXI_AWLEN); - - auto Port_awsize = + const auto Port_awsize = CM->add_port("_m_axi_" + portNameSpecializer + "_AWSIZE", port_o::OUT, interface_top, sizeType); - GetPointer(Port_awsize)->set_port_interface(port_o::port_interface::M_AXI_AWSIZE); + GetPointerS(Port_awsize)->set_port_interface(port_o::port_interface::M_AXI_AWSIZE); - auto Port_awburst = + const auto Port_awburst = CM->add_port("_m_axi_" + portNameSpecializer + "_AWBURST", port_o::OUT, interface_top, burstType); - GetPointer(Port_awburst)->set_port_interface(port_o::port_interface::M_AXI_AWBURST); + GetPointerS(Port_awburst)->set_port_interface(port_o::port_interface::M_AXI_AWBURST); - auto Port_awlock = - CM->add_port("_m_axi_" + portNameSpecializer + "_AWLOCK", port_o::OUT, interface_top, lockType); - GetPointer(Port_awlock)->set_port_interface(port_o::port_interface::M_AXI_AWLOCK); + const auto Port_awlock = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_AWLOCK", port_o::OUT, 1, interface_top, lockType); + GetPointerS(Port_awlock)->set_port_interface(port_o::port_interface::M_AXI_AWLOCK); - auto Port_awcache = + const auto Port_awcache = CM->add_port("_m_axi_" + portNameSpecializer + "_AWCACHE", port_o::OUT, interface_top, cacheType); - GetPointer(Port_awcache)->set_port_interface(port_o::port_interface::M_AXI_AWCACHE); + GetPointerS(Port_awcache)->set_port_interface(port_o::port_interface::M_AXI_AWCACHE); - auto Port_awprot = + const auto Port_awprot = CM->add_port("_m_axi_" + portNameSpecializer + "_AWPROT", port_o::OUT, interface_top, protType); - GetPointer(Port_awprot)->set_port_interface(port_o::port_interface::M_AXI_AWPROT); + GetPointerS(Port_awprot)->set_port_interface(port_o::port_interface::M_AXI_AWPROT); - auto Port_awqos = CM->add_port("_m_axi_" + portNameSpecializer + "_AWQOS", port_o::OUT, interface_top, qosType); - GetPointer(Port_awqos)->set_port_interface(port_o::port_interface::M_AXI_AWQOS); + const auto Port_awqos = + CM->add_port("_m_axi_" + portNameSpecializer + "_AWQOS", port_o::OUT, interface_top, qosType); + GetPointerS(Port_awqos)->set_port_interface(port_o::port_interface::M_AXI_AWQOS); - auto Port_awregion = + const auto Port_awregion = CM->add_port("_m_axi_" + portNameSpecializer + "_AWREGION", port_o::OUT, interface_top, regionType); - GetPointer(Port_awregion)->set_port_interface(port_o::port_interface::M_AXI_AWREGION); + GetPointerS(Port_awregion)->set_port_interface(port_o::port_interface::M_AXI_AWREGION); - auto Port_awuser = - CM->add_port("_m_axi_" + portNameSpecializer + "_AWUSER", port_o::OUT, interface_top, userType); - GetPointer(Port_awuser)->set_port_interface(port_o::port_interface::M_AXI_AWUSER); + const auto Port_awuser = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_AWUSER", port_o::OUT, 1, interface_top, userType); + GetPointerS(Port_awuser)->set_port_interface(port_o::port_interface::M_AXI_AWUSER); - auto Port_wvalid = - CM->add_port("_m_axi_" + portNameSpecializer + "_WVALID", port_o::OUT, interface_top, bool_type); - GetPointer(Port_wvalid)->set_port_interface(port_o::port_interface::M_AXI_WVALID); + const auto Port_awvalid = + CM->add_port("_m_axi_" + portNameSpecializer + "_AWVALID", port_o::OUT, interface_top, bool_type); + GetPointerS(Port_awvalid)->set_port_interface(port_o::port_interface::M_AXI_AWVALID); - auto Port_wready = - CM->add_port("_m_axi_" + portNameSpecializer + "_WREADY", port_o::IN, interface_top, bool_type); - GetPointer(Port_wready)->set_port_interface(port_o::port_interface::M_AXI_WREADY); + const auto Port_wid = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_WID", port_o::OUT, 1, interface_top, idType); + GetPointerS(Port_wid)->set_port_interface(port_o::port_interface::M_AXI_WID); - auto Port_wdata = CM->add_port("_m_axi_" + portNameSpecializer + "_WDATA", port_o::OUT, interface_top, Intype); - GetPointer(Port_wdata)->set_port_interface(port_o::port_interface::M_AXI_WDATA); + const auto Port_wdata = + CM->add_port("_m_axi_" + portNameSpecializer + "_WDATA", port_o::OUT, interface_top, Intype); + GetPointerS(Port_wdata)->set_port_interface(port_o::port_interface::M_AXI_WDATA); + param_ports += " _m_axi_" + portNameSpecializer + "_WDATA"; - auto Port_wstrb = CM->add_port("_m_axi_" + portNameSpecializer + "_WSTRB", port_o::OUT, interface_top, strbType); - GetPointer(Port_wstrb)->set_port_interface(port_o::port_interface::M_AXI_WSTRB); + const auto Port_wstrb = + CM->add_port("_m_axi_" + portNameSpecializer + "_WSTRB", port_o::OUT, interface_top, strbType); + GetPointerS(Port_wstrb)->set_port_interface(port_o::port_interface::M_AXI_WSTRB); - auto Port_wlast = CM->add_port("_m_axi_" + portNameSpecializer + "_WLAST", port_o::OUT, interface_top, bool_type); - GetPointer(Port_wlast)->set_port_interface(port_o::port_interface::M_AXI_WLAST); + const auto Port_wlast = + CM->add_port("_m_axi_" + portNameSpecializer + "_WLAST", port_o::OUT, interface_top, bool_type); + GetPointerS(Port_wlast)->set_port_interface(port_o::port_interface::M_AXI_WLAST); - auto Port_wid = CM->add_port("_m_axi_" + portNameSpecializer + "_WID", port_o::OUT, interface_top, idType); - GetPointer(Port_wid)->set_port_interface(port_o::port_interface::M_AXI_WID); + const auto Port_wuser = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_WUSER", port_o::OUT, 1, interface_top, userType); + GetPointerS(Port_wuser)->set_port_interface(port_o::port_interface::M_AXI_WUSER); - auto Port_wuser = CM->add_port("_m_axi_" + portNameSpecializer + "_WUSER", port_o::OUT, interface_top, userType); - GetPointer(Port_wuser)->set_port_interface(port_o::port_interface::M_AXI_WUSER); + const auto Port_wvalid = + CM->add_port("_m_axi_" + portNameSpecializer + "_WVALID", port_o::OUT, interface_top, bool_type); + GetPointerS(Port_wvalid)->set_port_interface(port_o::port_interface::M_AXI_WVALID); - auto Port_arvalid = - CM->add_port("_m_axi_" + portNameSpecializer + "_ARVALID", port_o::OUT, interface_top, bool_type); - GetPointer(Port_arvalid)->set_port_interface(port_o::port_interface::M_AXI_ARVALID); + const auto Port_bready = + CM->add_port("_m_axi_" + portNameSpecializer + "_BREADY", port_o::OUT, interface_top, bool_type); + GetPointerS(Port_bready)->set_port_interface(port_o::port_interface::M_AXI_BREADY); - auto Port_arready = - CM->add_port("_m_axi_" + portNameSpecializer + "_ARREADY", port_o::IN, interface_top, bool_type); - GetPointer(Port_arready)->set_port_interface(port_o::port_interface::M_AXI_ARREADY); + const auto Port_arid = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_ARID", port_o::OUT, 1, interface_top, idType); + GetPointerS(Port_arid)->set_port_interface(port_o::port_interface::M_AXI_ARID); - auto Port_araddr = + const auto Port_araddr = CM->add_port("_m_axi_" + portNameSpecializer + "_ARADDR", port_o::OUT, interface_top, address_interface_type); - GetPointer(Port_araddr)->set_port_interface(port_o::port_interface::M_AXI_ARADDR); - - auto Port_arid = CM->add_port("_m_axi_" + portNameSpecializer + "_ARID", port_o::OUT, interface_top, idType); - GetPointer(Port_arid)->set_port_interface(port_o::port_interface::M_AXI_ARID); + GetPointerS(Port_araddr)->set_port_interface(port_o::port_interface::M_AXI_ARADDR); + param_ports += " _m_axi_" + portNameSpecializer + "_ARADDR"; - auto Port_arlen = CM->add_port("_m_axi_" + portNameSpecializer + "_ARLEN", port_o::OUT, interface_top, lenType); - GetPointer(Port_arlen)->set_port_interface(port_o::port_interface::M_AXI_ARLEN); + const auto Port_arlen = + CM->add_port("_m_axi_" + portNameSpecializer + "_ARLEN", port_o::OUT, interface_top, lenType); + GetPointerS(Port_arlen)->set_port_interface(port_o::port_interface::M_AXI_ARLEN); - auto Port_arsize = + const auto Port_arsize = CM->add_port("_m_axi_" + portNameSpecializer + "_ARSIZE", port_o::OUT, interface_top, sizeType); - GetPointer(Port_arsize)->set_port_interface(port_o::port_interface::M_AXI_ARSIZE); + GetPointerS(Port_arsize)->set_port_interface(port_o::port_interface::M_AXI_ARSIZE); - auto Port_arburst = + const auto Port_arburst = CM->add_port("_m_axi_" + portNameSpecializer + "_ARBURST", port_o::OUT, interface_top, burstType); - GetPointer(Port_arburst)->set_port_interface(port_o::port_interface::M_AXI_ARBURST); + GetPointerS(Port_arburst)->set_port_interface(port_o::port_interface::M_AXI_ARBURST); - auto Port_arlock = - CM->add_port("_m_axi_" + portNameSpecializer + "_ARLOCK", port_o::OUT, interface_top, lockType); - GetPointer(Port_arlock)->set_port_interface(port_o::port_interface::M_AXI_ARLOCK); + const auto Port_arlock = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_ARLOCK", port_o::OUT, 1, interface_top, lockType); + GetPointerS(Port_arlock)->set_port_interface(port_o::port_interface::M_AXI_ARLOCK); - auto Port_arcache = + const auto Port_arcache = CM->add_port("_m_axi_" + portNameSpecializer + "_ARCACHE", port_o::OUT, interface_top, cacheType); - GetPointer(Port_arcache)->set_port_interface(port_o::port_interface::M_AXI_ARCACHE); + GetPointerS(Port_arcache)->set_port_interface(port_o::port_interface::M_AXI_ARCACHE); - auto Port_arprot = + const auto Port_arprot = CM->add_port("_m_axi_" + portNameSpecializer + "_ARPROT", port_o::OUT, interface_top, protType); - GetPointer(Port_arprot)->set_port_interface(port_o::port_interface::M_AXI_ARPROT); + GetPointerS(Port_arprot)->set_port_interface(port_o::port_interface::M_AXI_ARPROT); - auto Port_arqos = CM->add_port("_m_axi_" + portNameSpecializer + "_ARQOS", port_o::OUT, interface_top, qosType); - GetPointer(Port_arqos)->set_port_interface(port_o::port_interface::M_AXI_ARQOS); + const auto Port_arqos = + CM->add_port("_m_axi_" + portNameSpecializer + "_ARQOS", port_o::OUT, interface_top, qosType); + GetPointerS(Port_arqos)->set_port_interface(port_o::port_interface::M_AXI_ARQOS); - CM->add_port("_m_axi_" + portNameSpecializer + "_ARREGION", port_o::OUT, interface_top, regionType); - GetPointer(Port_awlock)->set_port_interface(port_o::port_interface::M_AXI_ARREGION); + const auto Port_arregion = + CM->add_port("_m_axi_" + portNameSpecializer + "_ARREGION", port_o::OUT, interface_top, regionType); + GetPointerS(Port_arregion)->set_port_interface(port_o::port_interface::M_AXI_ARREGION); - auto Port_aruser = - CM->add_port("_m_axi_" + portNameSpecializer + "_ARUSER", port_o::OUT, interface_top, userType); - GetPointer(Port_aruser)->set_port_interface(port_o::port_interface::M_AXI_ARUSER); + const auto Port_aruser = + CM->add_port_vector("_m_axi_" + portNameSpecializer + "_ARUSER", port_o::OUT, 1, interface_top, userType); + GetPointerS(Port_aruser)->set_port_interface(port_o::port_interface::M_AXI_ARUSER); - auto Port_rvalid = - CM->add_port("_m_axi_" + portNameSpecializer + "_RVALID", port_o::IN, interface_top, bool_type); - GetPointer(Port_rvalid)->set_port_interface(port_o::port_interface::M_AXI_RVALID); + const auto Port_arvalid = + CM->add_port("_m_axi_" + portNameSpecializer + "_ARVALID", port_o::OUT, interface_top, bool_type); + GetPointerS(Port_arvalid)->set_port_interface(port_o::port_interface::M_AXI_ARVALID); - auto Port_rready = + const auto Port_rready = CM->add_port("_m_axi_" + portNameSpecializer + "_RREADY", port_o::OUT, interface_top, bool_type); - GetPointer(Port_rready)->set_port_interface(port_o::port_interface::M_AXI_RREADY); - - auto Port_rdata = CM->add_port("_m_axi_" + portNameSpecializer + "_RDATA", port_o::IN, interface_top, Intype); - GetPointer(Port_rdata)->set_port_interface(port_o::port_interface::M_AXI_RDATA); - - auto Port_rlast = CM->add_port("_m_axi_" + portNameSpecializer + "_RLAST", port_o::IN, interface_top, bool_type); - GetPointer(Port_rlast)->set_port_interface(port_o::port_interface::M_AXI_RLAST); - - auto Port_rid = CM->add_port("_m_axi_" + portNameSpecializer + "_RID", port_o::IN, interface_top, idType); - GetPointer(Port_rid)->set_port_interface(port_o::port_interface::M_AXI_RID); - - auto Port_ruser = CM->add_port("_m_axi_" + portNameSpecializer + "_RUSER", port_o::IN, interface_top, userType); - GetPointer(Port_ruser)->set_port_interface(port_o::port_interface::M_AXI_RUSER); - - auto Port_rresp = CM->add_port("_m_axi_" + portNameSpecializer + "_RRESP", port_o::IN, interface_top, respType); - GetPointer(Port_rresp)->set_port_interface(port_o::port_interface::M_AXI_RRESP); - - auto Port_bvalid = - CM->add_port("_m_axi_" + portNameSpecializer + "_BVALID", port_o::IN, interface_top, bool_type); - GetPointer(Port_bvalid)->set_port_interface(port_o::port_interface::M_AXI_BVALID); - - auto Port_bready = - CM->add_port("_m_axi_" + portNameSpecializer + "_BREADY", port_o::OUT, interface_top, bool_type); - GetPointer(Port_bready)->set_port_interface(port_o::port_interface::M_AXI_BREADY); - - auto Port_bresp = CM->add_port("_m_axi_" + portNameSpecializer + "_BRESP", port_o::IN, interface_top, respType); - GetPointer(Port_bresp)->set_port_interface(port_o::port_interface::M_AXI_BRESP); - - auto Port_bid = CM->add_port("_m_axi_" + portNameSpecializer + "_BID", port_o::IN, interface_top, idType); - GetPointer(Port_bid)->set_port_interface(port_o::port_interface::M_AXI_BID); - - auto Port_buser = CM->add_port("_m_axi_" + portNameSpecializer + "_BUSER", port_o::OUT, interface_top, userType); - GetPointer(Port_buser)->set_port_interface(port_o::port_interface::M_AXI_BUSER); + GetPointerS(Port_rready)->set_port_interface(port_o::port_interface::M_AXI_RREADY); if(mat == m_axi_type::axi_slave) { - auto Port_LSawvalid = CM->add_port("_s_axi_AXILiteS_AWVALID", port_o::IN, interface_top, bool_type); - GetPointer(Port_LSawvalid)->set_port_interface(port_o::port_interface::S_AXIL_AWVALID); + const auto Port_LSawvalid = CM->add_port("_s_axi_AXILiteS_AWVALID", port_o::IN, interface_top, bool_type); + GetPointerS(Port_LSawvalid)->set_port_interface(port_o::port_interface::S_AXIL_AWVALID); CM->add_port("_s_axi_AXILiteS_AWREADY", port_o::OUT, interface_top, bool_type); - GetPointer(Port_LSawvalid)->set_port_interface(port_o::port_interface::S_AXIL_AWREADY); + GetPointerS(Port_LSawvalid)->set_port_interface(port_o::port_interface::S_AXIL_AWREADY); CM->add_port("_s_axi_AXILiteS_AWADDR", port_o::IN, interface_top, address_interface_type); - GetPointer(Port_LSawvalid)->set_port_interface(port_o::port_interface::S_AXIL_AWADDR); + GetPointerS(Port_LSawvalid)->set_port_interface(port_o::port_interface::S_AXIL_AWADDR); CM->add_port("_s_axi_AXILiteS_WVALID", port_o::IN, interface_top, bool_type); CM->add_port("_s_axi_AXILiteS_WREADY", port_o::OUT, interface_top, bool_type); CM->add_port("_s_axi_AXILiteS_WDATA", port_o::IN, interface_top, Intype); @@ -1409,81 +1417,59 @@ void FunctionInterfaceInfer::create_resource_m_axi(const std::set& CM->add_port("_s_axi_AXILiteS_BRESP", port_o::OUT, interface_top, respType); } - auto inPort_m_axi = CM->add_port("_" + argName_string, port_o::IN, interface_top, address_interface_type); - if(mat == m_axi_type::none || mat == m_axi_type::axi_slave) - { - GetPointer(inPort_m_axi)->set_port_interface(port_o::port_interface::PI_M_AXI_OFF); - } - else - { - GetPointer(inPort_m_axi)->set_port_interface(port_o::port_interface::PI_M_AXI_DIRECT); - } - - CM->add_NP_functionality(interface_top, NP_functionality::LIBRARY, "in1 in2 in3 out1"); + CM->add_NP_functionality(interface_top, NP_functionality::LIBRARY, "in1 in2 in3 in4 out1" + param_ports); CM->add_NP_functionality(interface_top, NP_functionality::VERILOG_GENERATOR, "ReadWrite_" + interfaceType + ".cpp"); TechMan->add_resource(INTERFACE_LIBRARY, ResourceName, CM); - for(const auto& fdName : operationsR) - { - TechMan->add_operation(INTERFACE_LIBRARY, ResourceName, fdName); - } - for(const auto& fdName : operationsW) - { - TechMan->add_operation(INTERFACE_LIBRARY, ResourceName, fdName); - } - auto fu = GetPointerS(TechMan->get_fu(ResourceName, INTERFACE_LIBRARY)); - fu->area_m = area_model::create_model(device_type, parameters); + + const auto fu = GetPointerS(TechMan->get_fu(ResourceName, INTERFACE_LIBRARY)); + const auto device = HLS_T->get_target_device(); + fu->area_m = area_model::create_model(device->get_type(), parameters); fu->area_m->set_area_value(0); - for(const auto& fdName : operationsR) - { - auto op = GetPointerS(fu->get_operation(fdName)); - set_op_time(op); - } - for(const auto& fdName : operationsW) - { - auto op = GetPointerS(fu->get_operation(fdName)); - set_op_time(op); - } /// add constraint on resource HLSMgr->design_interface_constraints[function_id][INTERFACE_LIBRARY][ResourceName] = n_resources; INDENT_DBG_MEX(DEBUG_LEVEL_PEDANTIC, debug_level, "<--Interface resource created: "); } - else + + for(const auto& fdName : operationsR) { - for(const auto& fdName : operationsR) - { - TechMan->add_operation(INTERFACE_LIBRARY, ResourceName, fdName); - } - for(const auto& fdName : operationsW) - { - TechMan->add_operation(INTERFACE_LIBRARY, ResourceName, fdName); - } - const auto fu = GetPointerS(TechMan->get_fu(ResourceName, INTERFACE_LIBRARY)); + TechMan->add_operation(INTERFACE_LIBRARY, ResourceName, fdName); + } + for(const auto& fdName : operationsW) + { + TechMan->add_operation(INTERFACE_LIBRARY, ResourceName, fdName); + } + const auto fu = GetPointerS(TechMan->get_fu(ResourceName, INTERFACE_LIBRARY)); + const auto device = HLS_T->get_target_device(); - for(const auto& fdName : operationsR) - { - auto op = GetPointerS(fu->get_operation(fdName)); - set_op_time(op); - } - for(const auto& fdName : operationsW) - { - auto op = GetPointerS(fu->get_operation(fdName)); - set_op_time(op); - } - const auto address_bitsize = HLSMgr->get_address_bitsize(); - structural_type_descriptorRef address_interface_type(new structural_type_descriptor("bool", address_bitsize)); - const auto interface_top = fu->CM->get_circ(); - const auto inPort_m_axi = - fu->CM->add_port("_" + argName_string, port_o::IN, interface_top, address_interface_type); - if(mat == m_axi_type::none || mat == m_axi_type::axi_slave) - { - GetPointerS(inPort_m_axi)->set_port_interface(port_o::port_interface::PI_M_AXI_OFF); - } - else - { - GetPointerS(inPort_m_axi)->set_port_interface(port_o::port_interface::PI_M_AXI_DIRECT); - } + for(const auto& fdName : operationsR) + { + const auto op = GetPointerS(fu->get_operation(fdName)); + op->time_m = time_model::create_model(device->get_type(), parameters); + op->bounded = false; + op->time_m->set_execution_time(HLS_T->get_technology_manager()->CGetSetupHoldTime() + EPSILON, 0); + op->time_m->set_synthesis_dependent(true); + } + for(const auto& fdName : operationsW) + { + const auto op = GetPointer(fu->get_operation(fdName)); + op->time_m = time_model::create_model(device->get_type(), parameters); + op->bounded = false; + op->time_m->set_execution_time(HLS_T->get_technology_manager()->CGetSetupHoldTime() + EPSILON, 0); + op->time_m->set_synthesis_dependent(true); + } + const auto address_bitsize = HLSMgr->get_address_bitsize(); + const structural_type_descriptorRef address_interface_type(new structural_type_descriptor("bool", address_bitsize)); + const auto interface_top = fu->CM->get_circ(); + const auto inPort_m_axi = fu->CM->add_port("_" + argName_string, port_o::IN, interface_top, address_interface_type); + if(mat == m_axi_type::none || mat == m_axi_type::axi_slave) + { + GetPointerS(inPort_m_axi)->set_port_interface(port_o::port_interface::PI_M_AXI_OFF); + } + else + { + GetPointerS(inPort_m_axi)->set_port_interface(port_o::port_interface::PI_M_AXI_DIRECT); } }