notes.txt

3/26
Add gchar to Verilog





3/20
zero out top bit after mod insn before or after, somewhere
positive mods look like they work, check neg
Signed mult looks like it works
Wrote a whole simulator...not sure why
if d is < 0 then q - ((-d) % q), this is how we should do negative mods, FOR SURE, 160 FTW
Profit?



1. Write assembly for ECC
2. Edit assembly to support signed multiplicaiton, and 255 bit split
- Change check to use R1 after adding mux
- note: change sub to use the same adder, just need to invert second input
3. Add mux to allow use of R2-R32 for single register instructions
4. Write assembler to compile code
5. Test Simulation
6. Write Loader for FPGA
7. Run on FPGA?



Things we talked about:
- To keep 255 bits in each register at the end of mult subroutine, keep MSB of RT in our single bit reg, unless we just issued an SDRH insn, then we should keep LSB of RS in our single bit reg. This one bit is then used by SDL and SDRL respectively











Will need to take into account the one cycle delay of reading from bram. Meaning when you select the place you want to read out of, it will take one extra cycle. This may cause issues when reading from memory and loading it into a register.


LC counts
  16 bit word size, not using BRAM
  -------
  Satya implementation using mem and vmem

  with everything: LCs          2530 / 7680
  without divider: LCs          2496 / 7680
  without mult: LCs          2145 / 7680
  without sub: LCs          2112 / 7680


LC and BRAM Counts:
  -----
    16 Bits with imem and dmem 16 bits and 1024 addresses
        LCs          1085 / 7680
        BRAMs        8 / 32
    16 Bits with imem and dmem 32 bits and 1024 addresses
        LCs          1418 / 7680
        BRAMs        8 / 32
    16 Bits with imem and dmem 64 bits and 1024 addresses
        LCs          1418 / 7680
        BRAMs        8 / 32

    NOTE: something looks horribly wrong


Single Cycle only
  16:
      LCs          1194 / 7680
  32:
      LCs          2016 / 7680
  64:
      LCs          3397 / 7680
  128:
      LCs          6322 / 7680
  256:
      LCs          11651 / 7680

System with 1024 imem and 32 dmem
  16:
    LCs          1179 / 7680
    BRAMs        5 / 32
  32:
    LCs          1973 / 7680
    BRAMs        5 / 32
  64:
    LCs          3227 / 7680
    BRAMs        5 / 32
  128:
    LCs          5846 / 7680
    BRAMs        5 / 32
  256:
    LCs          11015 / 7680
    BRAMs        5 / 32

Regfile should be 2-3 luts per bit
Keep 1 register, and 1 memory, so alu takes in 1 operand form reg and 1 operand from memory
Remove load/store instructions, treat just as reading out of register filea

add logic to repeat instruction N times

add shift register for multiply step