From 589cb4946467e5d8bb20556bdaa7a65ee95b2f15 Mon Sep 17 00:00:00 2001
From: Rodolfo Jordao <45004351+Rojods@users.noreply.github.com>
Date: Wed, 29 May 2024 14:00:00 +0200
Subject: [PATCH] Create 2024-05-29-fpga-support-and-more.md

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+# IDeSyDe and ForSyDe IO releases
+
+We are happy to annouce the newer releases of IDeSyDe and ForSyDe IO. These newest releases enables you to solve DSE scenarios where the applications are modelled as SDF graphs and the platform contains FPGA elements which can host actors synthetized as ASICs. Naturally, this happens at the system-level, which means that the IDeSyDe makes mapping judgments based on number estimates and not on actual synthesis results. On the other hand, this has the advantage that you can use the DSE approach of this latest release with estimates of performance, in earlier stages of your design process.