From 4eb4a45e9521a8f5e873cb9ce9b01d08f0e890f2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Vizi=20B=C3=A9la=20=C3=81kos?= <belaakos.vizi@gmail.com>
Date: Thu, 16 May 2024 19:47:05 +0200
Subject: [PATCH] benchmarks

---
 .../algorithm/cegar/BasicAbstractor.java      |   1 -
 subprojects/xta/xta-analysis/build.gradle.kts |   1 -
 .../ClockPred/SingleXtaTraceRefiner.java      |   1 -
 .../theta/xta/analysis/config/ConfigEnum.java |  29 ++
 .../config/XtaConfigBuilder_ClockPred.java    |  18 ++
 .../config/XtaConfigBuilder_Zone.java         |  18 ++
 .../theta/xta/analysis/Test_ClockPred.java    |  10 +-
 .../bme/mit/theta/xta/analysis/clockpred.log  |   0
 .../test/resources/model/ClockPredTest.xta    |   7 +-
 .../src/test/resources/model/dipterv/9.xta    | 226 ++++++++++++++
 .../resources/model/dipterv/ClockPredTest.xta |  26 ++
 .../model/dipterv/amba3b5y.aag_4L_200.xta     | 200 +++++++++++++
 .../model/dipterv/amba3b5y.aag_5L_290.xta     | 212 ++++++++++++++
 .../model/dipterv/amba3b5y.aag_7L_290.xta     | 236 +++++++++++++++
 .../model/dipterv/amba4c7y.aag_5L_200.xta     | 229 +++++++++++++++
 .../model/dipterv/amba4c7y.aag_7L_300.xta     | 253 ++++++++++++++++
 .../model/dipterv/amba4c7y.aag_9L_300.xta     | 277 ++++++++++++++++++
 .../model/dipterv/bs16y.aag_4L_100.xta        | 110 +++++++
 .../model/dipterv/bs16y.aag_4L_200.xta        | 111 +++++++
 .../model/dipterv/cnt5y.aag_4L_200.xta        |  85 ++++++
 .../model/dipterv/cnt5y.aag_4L_300.xta        |  85 ++++++
 ...tory_assembly_3x3_1_1errors.aag_4L_200.xta | 179 +++++++++++
 ...tory_assembly_3x3_1_1errors.aag_6L_300.xta | 203 +++++++++++++
 ...tory_assembly_3x3_1_1errors.aag_7L_500.xta | 215 ++++++++++++++
 .../dipterv/genbuf2b3unrealy.aag_4L_300.xta   | 159 ++++++++++
 .../dipterv/genbuf2b3unrealy.aag_5L_300.xta   | 171 +++++++++++
 .../model/dipterv/genbuf5f5n.aag_6L_290.xta   | 235 +++++++++++++++
 ...ving_obstacle_8x8_1glitches.aag_4L_150.xta | 179 +++++++++++
 .../java/hu/bme/mit/theta/xta/cli/XtaCli.java |  28 +-
 29 files changed, 3488 insertions(+), 16 deletions(-)
 create mode 100644 subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/ConfigEnum.java
 create mode 100644 subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/clockpred.log
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/9.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/ClockPredTest.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_4L_200.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_5L_290.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_7L_290.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_5L_200.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_7L_300.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_9L_300.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_100.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_200.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_200.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_300.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_4L_200.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_6L_300.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_7L_500.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_4L_300.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_5L_300.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf5f5n.aag_6L_290.xta
 create mode 100644 subprojects/xta/xta-analysis/src/test/resources/model/dipterv/moving_obstacle_8x8_1glitches.aag_4L_150.xta

diff --git a/subprojects/common/analysis/src/main/java/hu/bme/mit/theta/analysis/algorithm/cegar/BasicAbstractor.java b/subprojects/common/analysis/src/main/java/hu/bme/mit/theta/analysis/algorithm/cegar/BasicAbstractor.java
index e6a4206438..4c18611f18 100644
--- a/subprojects/common/analysis/src/main/java/hu/bme/mit/theta/analysis/algorithm/cegar/BasicAbstractor.java
+++ b/subprojects/common/analysis/src/main/java/hu/bme/mit/theta/analysis/algorithm/cegar/BasicAbstractor.java
@@ -86,7 +86,6 @@ public AbstractorResult check(final ARG<S, A> arg, final P prec) {
 
 		long startNodes = arg.getNodes().count();
 		long startIncompleteNodes = arg.getIncompleteNodes().count();
-
 		ArgCexCheckHandler.instance.setCurrentArg(new AbstractArg<S, A, P>(arg, prec));
 		logger.write(Level.INFO, "|  |  Starting ARG: %d nodes, %d incomplete, %d unsafe%n", arg.getNodes().count(),
 				arg.getIncompleteNodes().count(), arg.getUnsafeNodes().count());
diff --git a/subprojects/xta/xta-analysis/build.gradle.kts b/subprojects/xta/xta-analysis/build.gradle.kts
index 88df389b6f..3cd9dd7268 100644
--- a/subprojects/xta/xta-analysis/build.gradle.kts
+++ b/subprojects/xta/xta-analysis/build.gradle.kts
@@ -1,6 +1,5 @@
 plugins {
     id("java-common")
-    id("cli-tool")
 }
 
 dependencies {
diff --git a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/ClockPred/SingleXtaTraceRefiner.java b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/ClockPred/SingleXtaTraceRefiner.java
index db701ef7a9..189322a796 100644
--- a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/ClockPred/SingleXtaTraceRefiner.java
+++ b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/ClockPred/SingleXtaTraceRefiner.java
@@ -104,7 +104,6 @@ public RefinerResult<XtaState<Prod2State<S, ZoneState>>, XtaAction, XtaPrec<Prod
 
         assert cexZoneStatus.isFeasible() || cexZoneStatus.isInfeasible() : "Unknown CEX status";
         assert cexExprStatus.isFeasible() || cexExprStatus.isInfeasible() : "Unknown CEX status";
-
         if (cexZoneStatus.isFeasible() && cexExprStatus.isFeasible()) { // if any of traces are feasible than it is unsafe
             return RefinerResult.unsafe(traceToConcretize);
         } else {
diff --git a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/ConfigEnum.java b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/ConfigEnum.java
new file mode 100644
index 0000000000..c160807b1c
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/ConfigEnum.java
@@ -0,0 +1,29 @@
+package hu.bme.mit.theta.xta.analysis.config;
+
+import hu.bme.mit.theta.analysis.algorithm.ArgNodeComparators;
+
+public class ConfigEnum {
+    public enum Domain {
+        EXPL, PRED_BOOL, PRED_CART, PRED_SPLIT
+    }
+
+    public enum Refinement {
+        FW_BIN_ITP, BW_BIN_ITP, SEQ_ITP, MULTI_SEQ, UNSAT_CORE, UCB,
+        NWT_WP, NWT_SP, NWT_WP_LV, NWT_SP_LV, NWT_IT_WP, NWT_IT_SP, NWT_IT_WP_LV, NWT_IT_SP_LV
+    }
+    public enum InitPrec {
+        EMPTY, ALLVARS, ALLASSUMES
+    }
+    public enum Search {
+        BFS(ArgNodeComparators.combine(ArgNodeComparators.targetFirst(), ArgNodeComparators.bfs())),
+
+        DFS(ArgNodeComparators.combine(ArgNodeComparators.targetFirst(), ArgNodeComparators.dfs()));
+
+        public final ArgNodeComparators.ArgNodeComparator comparator;
+
+        private Search(final ArgNodeComparators.ArgNodeComparator comparator) {
+            this.comparator = comparator;
+        }
+
+    }
+}
diff --git a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_ClockPred.java b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_ClockPred.java
index 9f4ae1e9a8..ce7fb62890 100644
--- a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_ClockPred.java
+++ b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_ClockPred.java
@@ -146,15 +146,29 @@ public XtaConfigBuilder_ClockPred search(final Search search) {
         this.search = search;
         return this;
     }
+    public XtaConfigBuilder_ClockPred search(final String search) {
+        this.search = Search.valueOf(search);
+        return this;
+    }
     public XtaConfigBuilder_ClockPred predSplit(final PredSplit predSplit) {
         this.predSplit = predSplit;
         return this;
     }
+
+    public XtaConfigBuilder_ClockPred predSplit(final String predSplit) {
+        this.predSplit = PredSplit.valueOf(predSplit);
+        return this;
+    }
     public XtaConfigBuilder_ClockPred precGranularity(final PrecGranularity precGranularity) {
         this.precGranularity = precGranularity;
 
         return this;
     }
+    public XtaConfigBuilder_ClockPred precGranularity(final String precGranularity) {
+        this.precGranularity = PrecGranularity.valueOf(precGranularity);
+
+        return this;
+    }
     public XtaConfigBuilder_ClockPred maxEnum(final int maxEnum) {
         this.maxEnum = maxEnum;
         return this;
@@ -163,6 +177,10 @@ public XtaConfigBuilder_ClockPred initPrec(final InitPrec initPrec) {
         this.initPrec = initPrec;
         return this;
     }
+    public XtaConfigBuilder_ClockPred initPrec(final String initPrec) {
+        this.initPrec = InitPrec.valueOf(initPrec);
+        return this;
+    }
     public XtaConfigBuilder_ClockPred pruneStrategy(final PruneStrategy pruneStrategy) {
         this.pruneStrategy = pruneStrategy;
         return this;
diff --git a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_Zone.java b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_Zone.java
index 5774865330..a504d28d09 100644
--- a/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_Zone.java
+++ b/subprojects/xta/xta-analysis/src/main/java/hu/bme/mit/theta/xta/analysis/config/XtaConfigBuilder_Zone.java
@@ -140,15 +140,29 @@ public XtaConfigBuilder_Zone search(final Search search) {
         this.search = search;
         return this;
     }
+    public XtaConfigBuilder_Zone search(final String search) {
+        this.search = Search.valueOf(search);
+        return this;
+    }
     public XtaConfigBuilder_Zone predSplit(final PredSplit predSplit) {
         this.predSplit = predSplit;
         return this;
     }
+    public XtaConfigBuilder_Zone predSplit(final String predSplit) {
+        this.predSplit = PredSplit.valueOf(predSplit);
+        return this;
+    }
     public XtaConfigBuilder_Zone precGranularity(final PrecGranularity precGranularity) {
         this.precGranularity = precGranularity;
 
         return this;
     }
+
+    public XtaConfigBuilder_Zone precGranularity(final String precGranularity) {
+        this.precGranularity = PrecGranularity.valueOf(precGranularity);
+
+        return this;
+    }
     public XtaConfigBuilder_Zone maxEnum(final int maxEnum) {
         this.maxEnum = maxEnum;
         return this;
@@ -157,6 +171,10 @@ public XtaConfigBuilder_Zone initPrec(final InitPrec initPrec) {
         this.initPrec = initPrec;
         return this;
     }
+    public XtaConfigBuilder_Zone initPrec(final String initPrec) {
+        this.initPrec = InitPrec.valueOf(initPrec);
+        return this;
+    }
     public XtaConfigBuilder_Zone pruneStrategy(final PruneStrategy pruneStrategy) {
         this.pruneStrategy = pruneStrategy;
         return this;
diff --git a/subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/Test_ClockPred.java b/subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/Test_ClockPred.java
index 5083c915ad..7281c7dd98 100644
--- a/subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/Test_ClockPred.java
+++ b/subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/Test_ClockPred.java
@@ -3,6 +3,7 @@
 import hu.bme.mit.theta.analysis.algorithm.SafetyResult;
 import hu.bme.mit.theta.common.OsHelper;
 import hu.bme.mit.theta.common.logging.ConsoleLogger;
+import hu.bme.mit.theta.common.logging.FileLogger;
 import hu.bme.mit.theta.common.logging.Logger;
 import hu.bme.mit.theta.solver.SolverFactory;
 import hu.bme.mit.theta.solver.SolverManager;
@@ -42,7 +43,7 @@ public void check() throws Exception{
         refinement = XtaConfigBuilder_ClockPred.Refinement.SEQ_ITP;
         SolverManager.registerSolverManager(Z3SolverManager.create());
         if(OsHelper.getOs().equals(OsHelper.OperatingSystem.LINUX)) {
-            SolverManager.registerSolverManager(SmtLibSolverManager.create(SmtLibSolverManager.HOME, new ConsoleLogger(Logger.Level.DETAIL)));
+            SolverManager.registerSolverManager(SmtLibSolverManager.create(SmtLibSolverManager.HOME, new FileLogger(Logger.Level.DETAIL, "clockpred.log", false, false)));
         }
 
         final SolverFactory solverFactory;
@@ -51,15 +52,18 @@ public void check() throws Exception{
 
         XtaSystem system;
         try(InputStream inputStream =  new SequenceInputStream(new FileInputStream("src/test/resources/model/ClockPredTest.xta"), new FileInputStream("src/test/resources/property/ClockPredTest.prop"))){
-            system = XtaDslManager.createSystem(inputStream);
+            system = XtaDslManager.createSystem(new FileInputStream("src/test/resources/model/ClockPredTest.xta"));
         }
         XtaConfigBuilder_ClockPred builder =  new XtaConfigBuilder_ClockPred(domain, refinement, /*solverFactory*/ Z3SolverFactory.getInstance());
         builder.precGranularity(XtaConfigBuilder_ClockPred.PrecGranularity.GLOBAL);
         builder.initPrec(XtaConfigBuilder_ClockPred.InitPrec.EMPTY);
         builder.maxEnum(1);
-
+        builder.logger(new FileLogger(Logger.Level.DETAIL, "clockpred.txt", true, true));
         XtaConfig config = builder.build(system);
         SafetyResult result = config.check();
         System.out.println("Safe?: " + result.isSafe());
+        if(result.isUnsafe()){
+            System.out.println(result.asUnsafe().getTrace());
+        }
     }
 }
diff --git a/subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/clockpred.log b/subprojects/xta/xta-analysis/src/test/java/hu/bme/mit/theta/xta/analysis/clockpred.log
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/ClockPredTest.xta b/subprojects/xta/xta-analysis/src/test/resources/model/ClockPredTest.xta
index 2d34c8140e..a4474d02c8 100644
--- a/subprojects/xta/xta-analysis/src/test/resources/model/ClockPredTest.xta
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/ClockPredTest.xta
@@ -9,8 +9,6 @@ process P1(){
         A {y <= 1},
         B;
 
-    urgent
-        idle;
 
     init
         idle;
@@ -22,4 +20,7 @@ process P1(){
         A -> B {guard x >= 7   ;assign a = 3;};
 
 }
-system P1;
\ No newline at end of file
+system P1;
+prop{
+    E<> P1_B
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/9.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/9.xta
new file mode 100644
index 0000000000..d70a726605
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/9.xta
@@ -0,0 +1,226 @@
+ 
+chan go0,go1,go2; // Process i can start
+chan release0;
+chan release1; // Machine j can be freed
+int[0,2] running0 = 0; // Machine 1 is running process running1. 3 means none
+int[0,2] running1 = 0;
+
+int[0,2] round = 0;
+// Is process(i) waiting?
+// This is redundant information but don't know how to
+// simply access processes' locations
+bool w0 = 1;
+bool w1 = 1;
+bool w2 = 1;
+
+clock x0;
+// int[0,1] mode0;
+
+clock x1;
+// int[0,1] mode1;
+
+clock x2;
+// int[0,1] mode2;
+
+
+process Process0() {
+bool Istay;
+bool Icontrollable_reset;
+bool Ln7;
+bool Lcounter0_out;
+bool Lcounter1_out;
+bool Lcounter2_out;
+bool Lcounter3_out;
+
+state
+    on0 { x0 <= 1000 },
+    on1 { x0 <= 800 },
+    w,
+    dead,
+    up,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out,
+    UpdatedLcounter3_out;
+commit
+    up,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out,
+    UpdatedLcounter3_out;
+init
+    w;
+trans
+    w -> on0 { guard Lcounter0_out == 0; sync go0?; assign x0:=0, w0:=0; },
+    w -> dead { guard Lcounter0_out == 0 && x0 > 2000; },
+    on0 -> up { guard Lcounter0_out == 0 && x0 >= 500 && x0 <= 1000; assign x0:=0; },
+    w -> on1 { guard Lcounter0_out == 1; sync go0?; assign x0:=0, w0:=0; },
+    w -> dead { guard Lcounter0_out == 1 && x0 > 2200; },
+    on1 -> up { guard Lcounter0_out == 1 && x0 >= 400 && x0 <= 800; assign x0:=0; },
+    up -> JustSetIstay { assign Istay := 0; },
+    up -> JustSetIstay { assign Istay := 1; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 0; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { assign Ln7 := 1; },
+    UpdatedLn7 -> UpdatedLcounter0_out { assign Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { assign Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { assign Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter2_out -> UpdatedLcounter3_out { assign Lcounter3_out := (!(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && ((Lcounter2_out) && (Ln7))) && !(Istay)) && !((Lcounter3_out) && (Ln7))) && !((((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && ((Lcounter2_out) && (Ln7))) && !(Istay)) && !(!((Lcounter3_out) && (Ln7)) && !(Icontrollable_reset)))); },
+    UpdatedLcounter3_out -> w { guard running0 == 0; sync release0!; assign w0:=1; },
+    UpdatedLcounter3_out -> w { guard running1 == 0; sync release1!; assign w0:=1; };
+}
+
+process Process1() {
+bool Istay;
+bool Icontrollable_reset;
+bool Ln7;
+bool Lcounter0_out;
+bool Lcounter1_out;
+bool Lcounter2_out;
+bool Lcounter3_out;
+
+state
+    on0 { x1 <= 1000 },
+    on1 { x1 <= 800 },
+    w,
+    dead,
+    up,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out,
+    UpdatedLcounter3_out;
+commit
+    up,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out,
+    UpdatedLcounter3_out;
+init
+    w;
+trans
+    w -> on0 { guard Lcounter0_out == 0; sync go1?; assign x1:=0, w1:=0; },
+    w -> dead { guard Lcounter0_out == 0 && x1 > 2000; },
+    on0 -> up { guard Lcounter0_out == 0 && x1 >= 500 && x1 <= 1000; assign x1:=0; },
+    w -> on1 { guard Lcounter0_out == 1; sync go1?; assign x1:=0, w1:=0; },
+    w -> dead { guard Lcounter0_out == 1 && x1 > 2200; },
+    on1 -> up { guard Lcounter0_out == 1 && x1 >= 400 && x1 <= 800; assign x1:=0; },
+    up -> JustSetIstay { assign Istay := 0; },
+    up -> JustSetIstay { assign Istay := 1; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 0; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { assign Ln7 := 1; },
+    UpdatedLn7 -> UpdatedLcounter0_out { assign Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { assign Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { assign Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter2_out -> UpdatedLcounter3_out { assign Lcounter3_out := (!(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && ((Lcounter2_out) && (Ln7))) && !(Istay)) && !((Lcounter3_out) && (Ln7))) && !((((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && ((Lcounter2_out) && (Ln7))) && !(Istay)) && !(!((Lcounter3_out) && (Ln7)) && !(Icontrollable_reset)))); },
+    UpdatedLcounter3_out -> w { guard running0 == 1; sync release0!; assign w1:=1; },
+    UpdatedLcounter3_out -> w { guard running1 == 1; sync release1!; assign w1:=1; };
+}
+
+process Process2() {
+bool Istay;
+bool Icontrollable_reset;
+bool Ln7;
+bool Lcounter0_out;
+bool Lcounter1_out;
+bool Lcounter2_out;
+bool Lcounter3_out;
+
+state
+    on0 { x2 <= 1000 },
+    on1 { x2 <= 800 },
+    w,
+    dead,
+    up,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out,
+    UpdatedLcounter3_out;
+commit
+    up,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out,
+    UpdatedLcounter3_out;
+init
+    w;
+trans
+    w -> on0 { guard Lcounter0_out == 0; sync go2?; assign x2:=0, w2:=0; },
+    w -> dead { guard Lcounter0_out == 0 && x2 > 2000; },
+    on0 -> up { guard Lcounter0_out == 0 && x2 >= 500 && x2 <= 1000; assign x2:=0; },
+    w -> on1 { guard Lcounter0_out == 1; sync go2?; assign x2:=0, w2:=0; },
+    w -> dead { guard Lcounter0_out == 1 && x2 > 2200; },
+    on1 -> up { guard Lcounter0_out == 1 && x2 >= 400 && x2 <= 800; assign x2:=0; },
+    up -> JustSetIstay { assign Istay := 0; },
+    up -> JustSetIstay { assign Istay := 1; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 0; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { assign Ln7 := 1; },
+    UpdatedLn7 -> UpdatedLcounter0_out { assign Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { assign Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { assign Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter2_out -> UpdatedLcounter3_out { assign Lcounter3_out := (!(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && ((Lcounter2_out) && (Ln7))) && !(Istay)) && !((Lcounter3_out) && (Ln7))) && !((((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && ((Lcounter2_out) && (Ln7))) && !(Istay)) && !(!((Lcounter3_out) && (Ln7)) && !(Icontrollable_reset)))); },
+    UpdatedLcounter3_out -> w { guard running0 == 2; sync release0!; assign w2:=1; },
+    UpdatedLcounter3_out -> w { guard running1 == 2; sync release1!; assign w2:=1; };
+}
+
+process Machine0() {
+
+state
+    busy,
+    idle;
+commit
+    idle;
+init
+    idle;
+trans
+    busy -> idle { sync release0?; assign running0 := 2; },
+    idle -> busy { guard round == 0 && w0 == 1; sync go0!; assign round = 1,  running0 := 0; },
+    idle -> idle { guard round == 0 && w0 == 0; assign round = 1; },
+    idle -> busy { guard round == 1 && w1 == 1; sync go1!; assign round = 2,  running0 := 1; },
+    idle -> idle { guard round == 1 && w1 == 0; assign round = 2; },
+    idle -> busy { guard round == 2 && w2 == 1; sync go2!; assign round = 0,  running0 := 2; },
+    idle -> idle { guard round == 2 && w2 == 0; assign round = 0; };
+}
+
+process Machine1() {
+
+state
+    busy,
+    idle;
+commit
+    idle;
+init
+    idle;
+trans
+    busy -> idle { sync release1?; assign running1 := 2; },
+    idle -> busy { guard round == 0 && w0 == 1; sync go0!; assign round = 1,  running1 := 0; },
+    idle -> idle { guard round == 0 && w0 == 0; assign round = 1; },
+    idle -> busy { guard round == 1 && w1 == 1; sync go1!; assign round = 2,  running1 := 1; },
+    idle -> idle { guard round == 1 && w1 == 0; assign round = 2; },
+    idle -> busy { guard round == 2 && w2 == 1; sync go2!; assign round = 0,  running1 := 2; },
+    idle -> idle { guard round == 2 && w2 == 0; assign round = 0; };
+}
+
+system Process0, Process1, Process2, Machine0, Machine1;
+prop{
+    E<> Process0_dead || Process1_dead ||Process2_dead 
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/ClockPredTest.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/ClockPredTest.xta
new file mode 100644
index 0000000000..cbe46eec4a
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/ClockPredTest.xta
@@ -0,0 +1,26 @@
+clock x;
+clock y;
+
+int a = 0;
+process P1(){
+
+    state
+        idle ,
+        A {y <= 1},
+        B;
+
+
+    init
+        idle;
+
+
+
+    trans
+        idle -> A {guard x <= 5; assign y = 0;},
+        A -> B {guard x >= 6   ;assign a = 3;};
+
+}
+system P1;
+prop{
+    E<> P1_B
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_4L_200.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_4L_200.xta
new file mode 100644
index 0000000000..7b8dfdd365
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_4L_200.xta
@@ -0,0 +1,200 @@
+ clock x_40;
+clock x_42;
+clock x_44;
+clock x_46;
+clock T;
+bool Ii_hbusreq0;
+bool Ii_hbusreq1;
+bool Ii_hbusreq2;
+bool Ii_hburst1;
+bool Ii_hburst0;
+bool Ii_hlock0;
+bool Ii_hlock1;
+bool Ii_hlock2;
+bool Ii_hready;
+bool Icontrollable_hmastlock;
+bool Icontrollable_nstart;
+bool Icontrollable_hmaster1;
+bool Icontrollable_locked;
+bool Icontrollable_hmaster0;
+bool Icontrollable_hgrant1;
+bool Icontrollable_busreq;
+bool Icontrollable_hgrant2;
+bool Icontrollable_ndecide;
+bool Icontrollable_nhgrant0;
+bool Ln41;
+bool Lreg_controllable_hgrant2_out;
+bool Lreg_controllable_hmaster1_out;
+bool Lsys_fair0done_out;
+bool Lreg_stateG3_0_out;
+bool Lenv_fair1done_out;
+bool Lreg_controllable_locked_out;
+bool Lsys_fair3done_out;
+bool Lreg_stateG3_1_out;
+bool Lreg_controllable_ndecide_out;
+bool Lreg_stateG3_2_out;
+bool Lreg_i_hbusreq0_out;
+bool Lreg_controllable_busreq_out;
+bool Lreg_controllable_nstart_out;
+bool Lreg_i_hbusreq1_out;
+bool Lsys_fair1done_out;
+bool Lreg_stateG2_out;
+bool Lreg_stateG10_1_out;
+bool Lenv_fair0done_out;
+bool Lreg_controllable_nhgrant0_out;
+bool Lreg_i_hlock2_out;
+bool Lreg_stateG10_2_out;
+bool Lreg_stateA1_out;
+bool Lreg_controllable_hmastlock_out;
+bool Lsys_fair4done_out;
+bool Lreg_i_hbusreq2_out;
+bool Lreg_i_hlock1_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_hlock0_out;
+bool Lreg_i_hready_out;
+bool Lreg_controllable_hgrant1_out;
+bool Lsys_fair2done_out;
+bool Lreg_controllable_hmaster0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn41,
+    UpdatedLn41_becomes0 { x_40 <= 1000 },
+    UpdatedLn41_becomes1 { x_40 <= 1500 },
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hgrant2_out_becomes0 { x_42 <= 500 },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 { x_42 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hmaster1_out_becomes0 { x_44 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 { x_44 <= 3000 },
+    UpdatedLsys_fair0done_out,
+    UpdatedLsys_fair0done_out_becomes0 { x_46 <= 3000 },
+    UpdatedLsys_fair0done_out_becomes1 { x_46 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn41,
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLsys_fair0done_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 0; },
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 1; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 0; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 1; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 0; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 1; },
+    JustSetIi_hbusreq2 -> JustSetIi_hburst1 { assign Ii_hburst1 := 0; },
+    JustSetIi_hbusreq2 -> JustSetIi_hburst1 { assign Ii_hburst1 := 1; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 0; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 1; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 0; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 1; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 0; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 1; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 0; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 1; },
+    JustSetIi_hlock2 -> JustSetIi_hready { assign Ii_hready := 0; },
+    JustSetIi_hlock2 -> JustSetIi_hready { assign Ii_hready := 1; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 0; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 1; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 0; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 1; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 0; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 1; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 0; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 1; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 0; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 1; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 0; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 1; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 0; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 1; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 0; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 1; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 0; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 1; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 0; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 1 && Ln41 != 1 && x_40 >= 1000; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 0 && Ln41 != 1 && x_40 >= 1500; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41_becomes0 { guard Ln41 == 1 && Ln41 != 1 && x_40 < 1000; },
+    UpdatedLn41_becomes0 -> UpdatedLn41 { guard x_40 >= 1000; assign x_40:=0, Ln41 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41_becomes1 { guard Ln41 == 0 && Ln41 != 1 && x_40 < 1500; },
+    UpdatedLn41_becomes1 -> UpdatedLn41 { guard x_40 >= 1500; assign x_40:=0, Ln41 := 1; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == (Icontrollable_hgrant2); },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 >= 500; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 >= 2000; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out_becomes0 { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 < 500; },
+    UpdatedLreg_controllable_hgrant2_out_becomes0 -> UpdatedLreg_controllable_hgrant2_out { guard x_42 >= 500; assign x_42:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out_becomes1 { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 < 2000; },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 -> UpdatedLreg_controllable_hgrant2_out { guard x_42 >= 2000; assign x_42:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 >= 2000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 >= 3000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes0 { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 < 2000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes0 -> UpdatedLreg_controllable_hmaster1_out { guard x_44 >= 2000; assign x_44:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes1 { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 < 3000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 -> UpdatedLreg_controllable_hmaster1_out { guard x_44 >= 3000; assign x_44:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 >= 3000; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 >= 0; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out_becomes0 { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 < 3000; },
+    UpdatedLsys_fair0done_out_becomes0 -> UpdatedLsys_fair0done_out { guard x_46 >= 3000; assign x_46:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out_becomes1 { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 < 0; },
+    UpdatedLsys_fair0done_out_becomes1 -> UpdatedLsys_fair0done_out { guard x_46 >= 0; assign x_46:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLsys_fair0done_out -> Init { guard T <= 2000; assign T:=0; },
+    UpdatedLsys_fair0done_out -> dead { guard T >2000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_5L_290.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_5L_290.xta
new file mode 100644
index 0000000000..e4d42d7ec3
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_5L_290.xta
@@ -0,0 +1,212 @@
+ clock x_40;
+clock x_42;
+clock x_44;
+clock x_46;
+clock x_48;
+clock T;
+bool Ii_hbusreq0;
+bool Ii_hbusreq1;
+bool Ii_hbusreq2;
+bool Ii_hburst1;
+bool Ii_hburst0;
+bool Ii_hlock0;
+bool Ii_hlock1;
+bool Ii_hlock2;
+bool Ii_hready;
+bool Icontrollable_hmastlock;
+bool Icontrollable_nstart;
+bool Icontrollable_hmaster1;
+bool Icontrollable_locked;
+bool Icontrollable_hmaster0;
+bool Icontrollable_hgrant1;
+bool Icontrollable_busreq;
+bool Icontrollable_hgrant2;
+bool Icontrollable_ndecide;
+bool Icontrollable_nhgrant0;
+bool Ln41;
+bool Lreg_controllable_hgrant2_out;
+bool Lreg_controllable_hmaster1_out;
+bool Lsys_fair0done_out;
+bool Lreg_stateG3_0_out;
+bool Lenv_fair1done_out;
+bool Lreg_controllable_locked_out;
+bool Lsys_fair3done_out;
+bool Lreg_stateG3_1_out;
+bool Lreg_controllable_ndecide_out;
+bool Lreg_stateG3_2_out;
+bool Lreg_i_hbusreq0_out;
+bool Lreg_controllable_busreq_out;
+bool Lreg_controllable_nstart_out;
+bool Lreg_i_hbusreq1_out;
+bool Lsys_fair1done_out;
+bool Lreg_stateG2_out;
+bool Lreg_stateG10_1_out;
+bool Lenv_fair0done_out;
+bool Lreg_controllable_nhgrant0_out;
+bool Lreg_i_hlock2_out;
+bool Lreg_stateG10_2_out;
+bool Lreg_stateA1_out;
+bool Lreg_controllable_hmastlock_out;
+bool Lsys_fair4done_out;
+bool Lreg_i_hbusreq2_out;
+bool Lreg_i_hlock1_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_hlock0_out;
+bool Lreg_i_hready_out;
+bool Lreg_controllable_hgrant1_out;
+bool Lsys_fair2done_out;
+bool Lreg_controllable_hmaster0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn41,
+    UpdatedLn41_becomes0 { x_40 <= 1000 },
+    UpdatedLn41_becomes1 { x_40 <= 1500 },
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hgrant2_out_becomes0 { x_42 <= 500 },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 { x_42 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hmaster1_out_becomes0 { x_44 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 { x_44 <= 3000 },
+    UpdatedLsys_fair0done_out,
+    UpdatedLsys_fair0done_out_becomes0 { x_46 <= 3000 },
+    UpdatedLsys_fair0done_out_becomes1 { x_46 <= 0 },
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLreg_stateG3_0_out_becomes0 { x_48 <= 2500 },
+    UpdatedLreg_stateG3_0_out_becomes1 { x_48 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn41,
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLsys_fair0done_out,
+    UpdatedLreg_stateG3_0_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 0; },
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 1; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 0; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 1; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 0; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 1; },
+    JustSetIi_hbusreq2 -> JustSetIi_hburst1 { assign Ii_hburst1 := 0; },
+    JustSetIi_hbusreq2 -> JustSetIi_hburst1 { assign Ii_hburst1 := 1; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 0; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 1; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 0; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 1; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 0; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 1; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 0; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 1; },
+    JustSetIi_hlock2 -> JustSetIi_hready { assign Ii_hready := 0; },
+    JustSetIi_hlock2 -> JustSetIi_hready { assign Ii_hready := 1; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 0; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 1; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 0; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 1; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 0; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 1; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 0; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 1; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 0; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 1; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 0; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 1; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 0; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 1; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 0; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 1; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 0; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 1; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 0; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 1 && Ln41 != 1 && x_40 >= 1000; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 0 && Ln41 != 1 && x_40 >= 1500; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41_becomes0 { guard Ln41 == 1 && Ln41 != 1 && x_40 < 1000; },
+    UpdatedLn41_becomes0 -> UpdatedLn41 { guard x_40 >= 1000; assign x_40:=0, Ln41 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41_becomes1 { guard Ln41 == 0 && Ln41 != 1 && x_40 < 1500; },
+    UpdatedLn41_becomes1 -> UpdatedLn41 { guard x_40 >= 1500; assign x_40:=0, Ln41 := 1; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == (Icontrollable_hgrant2); },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 >= 500; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 >= 2000; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out_becomes0 { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 < 500; },
+    UpdatedLreg_controllable_hgrant2_out_becomes0 -> UpdatedLreg_controllable_hgrant2_out { guard x_42 >= 500; assign x_42:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out_becomes1 { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 < 2000; },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 -> UpdatedLreg_controllable_hgrant2_out { guard x_42 >= 2000; assign x_42:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 >= 2000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 >= 3000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes0 { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 < 2000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes0 -> UpdatedLreg_controllable_hmaster1_out { guard x_44 >= 2000; assign x_44:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes1 { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 < 3000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 -> UpdatedLreg_controllable_hmaster1_out { guard x_44 >= 3000; assign x_44:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 >= 3000; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 >= 0; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out_becomes0 { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 < 3000; },
+    UpdatedLsys_fair0done_out_becomes0 -> UpdatedLsys_fair0done_out { guard x_46 >= 3000; assign x_46:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out_becomes1 { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 < 0; },
+    UpdatedLsys_fair0done_out_becomes1 -> UpdatedLsys_fair0done_out { guard x_46 >= 0; assign x_46:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 >= 2500; },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 >= 0; },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out_becomes0 { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 < 2500; },
+    UpdatedLreg_stateG3_0_out_becomes0 -> UpdatedLreg_stateG3_0_out { guard x_48 >= 2500; assign x_48:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out_becomes1 { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 < 0; },
+    UpdatedLreg_stateG3_0_out_becomes1 -> UpdatedLreg_stateG3_0_out { guard x_48 >= 0; assign x_48:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLreg_stateG3_0_out -> Init { guard T <= 2900; assign T:=0; },
+    UpdatedLreg_stateG3_0_out -> dead { guard T >2900; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_7L_290.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_7L_290.xta
new file mode 100644
index 0000000000..47e8ce73b0
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba3b5y.aag_7L_290.xta
@@ -0,0 +1,236 @@
+ clock x_40;
+clock x_42;
+clock x_44;
+clock x_46;
+clock x_48;
+clock x_50;
+clock x_52;
+clock T;
+bool Ii_hbusreq0;
+bool Ii_hbusreq1;
+bool Ii_hbusreq2;
+bool Ii_hburst1;
+bool Ii_hburst0;
+bool Ii_hlock0;
+bool Ii_hlock1;
+bool Ii_hlock2;
+bool Ii_hready;
+bool Icontrollable_hmastlock;
+bool Icontrollable_nstart;
+bool Icontrollable_hmaster1;
+bool Icontrollable_locked;
+bool Icontrollable_hmaster0;
+bool Icontrollable_hgrant1;
+bool Icontrollable_busreq;
+bool Icontrollable_hgrant2;
+bool Icontrollable_ndecide;
+bool Icontrollable_nhgrant0;
+bool Ln41;
+bool Lreg_controllable_hgrant2_out;
+bool Lreg_controllable_hmaster1_out;
+bool Lsys_fair0done_out;
+bool Lreg_stateG3_0_out;
+bool Lenv_fair1done_out;
+bool Lreg_controllable_locked_out;
+bool Lsys_fair3done_out;
+bool Lreg_stateG3_1_out;
+bool Lreg_controllable_ndecide_out;
+bool Lreg_stateG3_2_out;
+bool Lreg_i_hbusreq0_out;
+bool Lreg_controllable_busreq_out;
+bool Lreg_controllable_nstart_out;
+bool Lreg_i_hbusreq1_out;
+bool Lsys_fair1done_out;
+bool Lreg_stateG2_out;
+bool Lreg_stateG10_1_out;
+bool Lenv_fair0done_out;
+bool Lreg_controllable_nhgrant0_out;
+bool Lreg_i_hlock2_out;
+bool Lreg_stateG10_2_out;
+bool Lreg_stateA1_out;
+bool Lreg_controllable_hmastlock_out;
+bool Lsys_fair4done_out;
+bool Lreg_i_hbusreq2_out;
+bool Lreg_i_hlock1_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_hlock0_out;
+bool Lreg_i_hready_out;
+bool Lreg_controllable_hgrant1_out;
+bool Lsys_fair2done_out;
+bool Lreg_controllable_hmaster0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn41,
+    UpdatedLn41_becomes0 { x_40 <= 1000 },
+    UpdatedLn41_becomes1 { x_40 <= 1500 },
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hgrant2_out_becomes0 { x_42 <= 500 },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 { x_42 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hmaster1_out_becomes0 { x_44 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 { x_44 <= 3000 },
+    UpdatedLsys_fair0done_out,
+    UpdatedLsys_fair0done_out_becomes0 { x_46 <= 3000 },
+    UpdatedLsys_fair0done_out_becomes1 { x_46 <= 0 },
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLreg_stateG3_0_out_becomes0 { x_48 <= 2500 },
+    UpdatedLreg_stateG3_0_out_becomes1 { x_48 <= 0 },
+    UpdatedLenv_fair1done_out,
+    UpdatedLenv_fair1done_out_becomes0 { x_50 <= 4000 },
+    UpdatedLenv_fair1done_out_becomes1 { x_50 <= 2000 },
+    UpdatedLreg_controllable_locked_out,
+    UpdatedLreg_controllable_locked_out_becomes0 { x_52 <= 1000 },
+    UpdatedLreg_controllable_locked_out_becomes1 { x_52 <= 500 },
+    dead;
+urgent
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn41,
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLsys_fair0done_out,
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLenv_fair1done_out,
+    UpdatedLreg_controllable_locked_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 0; },
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 1; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 0; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 1; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 0; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 1; },
+    JustSetIi_hbusreq2 -> JustSetIi_hburst1 { assign Ii_hburst1 := 0; },
+    JustSetIi_hbusreq2 -> JustSetIi_hburst1 { assign Ii_hburst1 := 1; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 0; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 1; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 0; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 1; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 0; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 1; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 0; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 1; },
+    JustSetIi_hlock2 -> JustSetIi_hready { assign Ii_hready := 0; },
+    JustSetIi_hlock2 -> JustSetIi_hready { assign Ii_hready := 1; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 0; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 1; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 0; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 1; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 0; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 1; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 0; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 1; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 0; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 1; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 0; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 1; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 0; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 1; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 0; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 1; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 0; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 1; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 0; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 1 && Ln41 != 1 && x_40 >= 1000; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41 { guard Ln41 == 0 && Ln41 != 1 && x_40 >= 1500; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41_becomes0 { guard Ln41 == 1 && Ln41 != 1 && x_40 < 1000; },
+    UpdatedLn41_becomes0 -> UpdatedLn41 { guard x_40 >= 1000; assign x_40:=0, Ln41 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn41_becomes1 { guard Ln41 == 0 && Ln41 != 1 && x_40 < 1500; },
+    UpdatedLn41_becomes1 -> UpdatedLn41 { guard x_40 >= 1500; assign x_40:=0, Ln41 := 1; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == (Icontrollable_hgrant2); },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 >= 500; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 >= 2000; },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out_becomes0 { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 < 500; },
+    UpdatedLreg_controllable_hgrant2_out_becomes0 -> UpdatedLreg_controllable_hgrant2_out { guard x_42 >= 500; assign x_42:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLn41 -> UpdatedLreg_controllable_hgrant2_out_becomes1 { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_42 < 2000; },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 -> UpdatedLreg_controllable_hgrant2_out { guard x_42 >= 2000; assign x_42:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 >= 2000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 >= 3000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes0 { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 < 2000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes0 -> UpdatedLreg_controllable_hmaster1_out { guard x_44 >= 2000; assign x_44:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes1 { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_44 < 3000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 -> UpdatedLreg_controllable_hmaster1_out { guard x_44 >= 3000; assign x_44:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 >= 3000; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 >= 0; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out_becomes0 { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 < 3000; },
+    UpdatedLsys_fair0done_out_becomes0 -> UpdatedLsys_fair0done_out { guard x_46 >= 3000; assign x_46:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLsys_fair0done_out_becomes1 { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))) && x_46 < 0; },
+    UpdatedLsys_fair0done_out_becomes1 -> UpdatedLsys_fair0done_out { guard x_46 >= 0; assign x_46:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41))))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))); },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 >= 2500; },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 >= 0; },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out_becomes0 { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 < 2500; },
+    UpdatedLreg_stateG3_0_out_becomes0 -> UpdatedLreg_stateG3_0_out { guard x_48 >= 2500; assign x_48:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLsys_fair0done_out -> UpdatedLreg_stateG3_0_out_becomes1 { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))) && x_48 < 0; },
+    UpdatedLreg_stateG3_0_out_becomes1 -> UpdatedLreg_stateG3_0_out { guard x_48 >= 0; assign x_48:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln41))) && !(!(!((Lreg_stateG3_2_out) && (Ln41)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLenv_fair1done_out { guard Lenv_fair1done_out == ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLenv_fair1done_out { guard Lenv_fair1done_out == 1 && Lenv_fair1done_out != ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))) && x_50 >= 4000; },
+    UpdatedLreg_stateG3_0_out -> UpdatedLenv_fair1done_out { guard Lenv_fair1done_out == 0 && Lenv_fair1done_out != ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))) && x_50 >= 2000; },
+    UpdatedLreg_stateG3_0_out -> UpdatedLenv_fair1done_out_becomes0 { guard Lenv_fair1done_out == 1 && Lenv_fair1done_out != ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))) && x_50 < 4000; },
+    UpdatedLenv_fair1done_out_becomes0 -> UpdatedLenv_fair1done_out { guard x_50 >= 4000; assign x_50:=0, Lenv_fair1done_out := ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLenv_fair1done_out_becomes1 { guard Lenv_fair1done_out == 0 && Lenv_fair1done_out != ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))) && x_50 < 2000; },
+    UpdatedLenv_fair1done_out_becomes1 -> UpdatedLenv_fair1done_out { guard x_50 >= 2000; assign x_50:=0, Lenv_fair1done_out := ((((!(!((Lsys_fair4done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && !(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && !(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && (!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && !((Lreg_stateG2_out) && (Ln41))))))) && !(!(!((Lsys_fair4done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2))) && (!(!((Lsys_fair3done_out) && (Ln41)) && (!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1))) && (!(!((Lsys_fair2done_out) && (Ln41)) && (!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0))) && (!(!((Lsys_fair1done_out) && (Ln41)) && !(!((Lreg_stateG3_2_out) && (Ln41)) && (!((Lreg_stateG3_1_out) && (Ln41)) && !((Lreg_stateG3_0_out) && (Ln41))))) && !(!((Lsys_fair0done_out) && (Ln41)) && ((Lreg_stateG2_out) && (Ln41)))))))) && !(!(!((Lenv_fair0done_out) && (Ln41)) && ((Lreg_stateA1_out) && (Ln41))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready)))) && !(!((Lenv_fair1done_out) && (Ln41)) && !(Ii_hready))); },
+    UpdatedLenv_fair1done_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == (Icontrollable_locked); },
+    UpdatedLenv_fair1done_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == 1 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_52 >= 1000; },
+    UpdatedLenv_fair1done_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == 0 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_52 >= 500; },
+    UpdatedLenv_fair1done_out -> UpdatedLreg_controllable_locked_out_becomes0 { guard Lreg_controllable_locked_out == 1 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_52 < 1000; },
+    UpdatedLreg_controllable_locked_out_becomes0 -> UpdatedLreg_controllable_locked_out { guard x_52 >= 1000; assign x_52:=0, Lreg_controllable_locked_out := (Icontrollable_locked); },
+    UpdatedLenv_fair1done_out -> UpdatedLreg_controllable_locked_out_becomes1 { guard Lreg_controllable_locked_out == 0 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_52 < 500; },
+    UpdatedLreg_controllable_locked_out_becomes1 -> UpdatedLreg_controllable_locked_out { guard x_52 >= 500; assign x_52:=0, Lreg_controllable_locked_out := (Icontrollable_locked); },
+    UpdatedLreg_controllable_locked_out -> Init { guard T <= 2900; assign T:=0; },
+    UpdatedLreg_controllable_locked_out -> dead { guard T >2900; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_5L_200.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_5L_200.xta
new file mode 100644
index 0000000000..ebb8877a8e
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_5L_200.xta
@@ -0,0 +1,229 @@
+ clock x_46;
+clock x_48;
+clock x_50;
+clock x_52;
+clock x_54;
+clock T;
+bool Ii_hbusreq0;
+bool Ii_hbusreq1;
+bool Ii_hbusreq2;
+bool Ii_hbusreq3;
+bool Ii_hburst1;
+bool Ii_hburst0;
+bool Ii_hlock0;
+bool Ii_hlock1;
+bool Ii_hlock2;
+bool Ii_hlock3;
+bool Ii_hready;
+bool Icontrollable_hmastlock;
+bool Icontrollable_nstart;
+bool Icontrollable_hmaster1;
+bool Icontrollable_locked;
+bool Icontrollable_hmaster0;
+bool Icontrollable_hgrant1;
+bool Icontrollable_busreq;
+bool Icontrollable_hgrant2;
+bool Icontrollable_hgrant3;
+bool Icontrollable_ndecide;
+bool Icontrollable_nhgrant0;
+bool Ln47;
+bool Lreg_controllable_hgrant2_out;
+bool Lreg_controllable_hmaster1_out;
+bool Lreg_controllable_hgrant3_out;
+bool Lnext_env_fair_out;
+bool Lreg_stateG3_0_out;
+bool Lreg_controllable_locked_out;
+bool Lreg_stateG3_1_out;
+bool Lreg_controllable_ndecide_out;
+bool Lreg_stateG3_2_out;
+bool Lreg_i_hbusreq0_out;
+bool Lreg_controllable_busreq_out;
+bool Lreg_controllable_nstart_out;
+bool Lreg_i_hbusreq1_out;
+bool Lreg_i_hlock3_out;
+bool Lreg_stateG2_out;
+bool Lreg_stateG10_1_out;
+bool Lreg_controllable_nhgrant0_out;
+bool Lreg_i_hlock2_out;
+bool Lreg_stateG10_2_out;
+bool Lreg_stateA1_out;
+bool Lreg_controllable_hmastlock_out;
+bool Lreg_i_hbusreq2_out;
+bool Lnext_sys_fair0_out;
+bool Lnext_sys_fair1_out;
+bool Lnext_sys_fair2_out;
+bool Lnext_sys_fair3_out;
+bool Lreg_i_hlock1_out;
+bool Lreg_stateG10_3_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lreg_i_hbusreq3_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_hlock0_out;
+bool Lreg_i_hready_out;
+bool Lreg_controllable_hgrant1_out;
+bool Lreg_controllable_hmaster0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hbusreq3,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hlock3,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_hgrant3,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn47,
+    UpdatedLn47_becomes0 { x_46 <= 1000 },
+    UpdatedLn47_becomes1 { x_46 <= 1500 },
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hgrant2_out_becomes0 { x_48 <= 500 },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 { x_48 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hmaster1_out_becomes0 { x_50 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 { x_50 <= 3000 },
+    UpdatedLreg_controllable_hgrant3_out,
+    UpdatedLreg_controllable_hgrant3_out_becomes0 { x_52 <= 3000 },
+    UpdatedLreg_controllable_hgrant3_out_becomes1 { x_52 <= 0 },
+    UpdatedLnext_env_fair_out,
+    UpdatedLnext_env_fair_out_becomes0 { x_54 <= 2500 },
+    UpdatedLnext_env_fair_out_becomes1 { x_54 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hbusreq3,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hlock3,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_hgrant3,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn47,
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hgrant3_out,
+    UpdatedLnext_env_fair_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 0; },
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 1; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 0; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 1; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 0; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 1; },
+    JustSetIi_hbusreq2 -> JustSetIi_hbusreq3 { assign Ii_hbusreq3 := 0; },
+    JustSetIi_hbusreq2 -> JustSetIi_hbusreq3 { assign Ii_hbusreq3 := 1; },
+    JustSetIi_hbusreq3 -> JustSetIi_hburst1 { assign Ii_hburst1 := 0; },
+    JustSetIi_hbusreq3 -> JustSetIi_hburst1 { assign Ii_hburst1 := 1; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 0; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 1; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 0; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 1; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 0; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 1; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 0; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 1; },
+    JustSetIi_hlock2 -> JustSetIi_hlock3 { assign Ii_hlock3 := 0; },
+    JustSetIi_hlock2 -> JustSetIi_hlock3 { assign Ii_hlock3 := 1; },
+    JustSetIi_hlock3 -> JustSetIi_hready { assign Ii_hready := 0; },
+    JustSetIi_hlock3 -> JustSetIi_hready { assign Ii_hready := 1; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 0; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 1; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 0; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 1; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 0; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 1; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 0; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 1; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 0; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 1; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 0; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 1; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 0; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 1; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 0; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 1; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_hgrant3 { assign Icontrollable_hgrant3 := 0; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_hgrant3 { assign Icontrollable_hgrant3 := 1; },
+    JustSetIcontrollable_hgrant3 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 0; },
+    JustSetIcontrollable_hgrant3 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 1; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 0; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 1 && Ln47 != 1 && x_46 >= 1000; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 0 && Ln47 != 1 && x_46 >= 1500; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47_becomes0 { guard Ln47 == 1 && Ln47 != 1 && x_46 < 1000; },
+    UpdatedLn47_becomes0 -> UpdatedLn47 { guard x_46 >= 1000; assign x_46:=0, Ln47 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47_becomes1 { guard Ln47 == 0 && Ln47 != 1 && x_46 < 1500; },
+    UpdatedLn47_becomes1 -> UpdatedLn47 { guard x_46 >= 1500; assign x_46:=0, Ln47 := 1; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == (Icontrollable_hgrant2); },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 >= 500; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 >= 2000; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out_becomes0 { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 < 500; },
+    UpdatedLreg_controllable_hgrant2_out_becomes0 -> UpdatedLreg_controllable_hgrant2_out { guard x_48 >= 500; assign x_48:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out_becomes1 { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 < 2000; },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 -> UpdatedLreg_controllable_hgrant2_out { guard x_48 >= 2000; assign x_48:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 >= 2000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 >= 3000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes0 { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 < 2000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes0 -> UpdatedLreg_controllable_hmaster1_out { guard x_50 >= 2000; assign x_50:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes1 { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 < 3000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 -> UpdatedLreg_controllable_hmaster1_out { guard x_50 >= 3000; assign x_50:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == 1 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 >= 3000; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == 0 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 >= 0; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out_becomes0 { guard Lreg_controllable_hgrant3_out == 1 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 < 3000; },
+    UpdatedLreg_controllable_hgrant3_out_becomes0 -> UpdatedLreg_controllable_hgrant3_out { guard x_52 >= 3000; assign x_52:=0, Lreg_controllable_hgrant3_out := (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out_becomes1 { guard Lreg_controllable_hgrant3_out == 0 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 < 0; },
+    UpdatedLreg_controllable_hgrant3_out_becomes1 -> UpdatedLreg_controllable_hgrant3_out { guard x_52 >= 0; assign x_52:=0, Lreg_controllable_hgrant3_out := (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == 1 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 >= 2500; },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == 0 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 >= 0; },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out_becomes0 { guard Lnext_env_fair_out == 1 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 < 2500; },
+    UpdatedLnext_env_fair_out_becomes0 -> UpdatedLnext_env_fair_out { guard x_54 >= 2500; assign x_54:=0, Lnext_env_fair_out := (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out_becomes1 { guard Lnext_env_fair_out == 0 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 < 0; },
+    UpdatedLnext_env_fair_out_becomes1 -> UpdatedLnext_env_fair_out { guard x_54 >= 0; assign x_54:=0, Lnext_env_fair_out := (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLnext_env_fair_out -> Init { guard T <= 2000; assign T:=0; },
+    UpdatedLnext_env_fair_out -> dead { guard T >2000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_7L_300.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_7L_300.xta
new file mode 100644
index 0000000000..3dcc44463c
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_7L_300.xta
@@ -0,0 +1,253 @@
+ clock x_46;
+clock x_48;
+clock x_50;
+clock x_52;
+clock x_54;
+clock x_56;
+clock x_58;
+clock T;
+bool Ii_hbusreq0;
+bool Ii_hbusreq1;
+bool Ii_hbusreq2;
+bool Ii_hbusreq3;
+bool Ii_hburst1;
+bool Ii_hburst0;
+bool Ii_hlock0;
+bool Ii_hlock1;
+bool Ii_hlock2;
+bool Ii_hlock3;
+bool Ii_hready;
+bool Icontrollable_hmastlock;
+bool Icontrollable_nstart;
+bool Icontrollable_hmaster1;
+bool Icontrollable_locked;
+bool Icontrollable_hmaster0;
+bool Icontrollable_hgrant1;
+bool Icontrollable_busreq;
+bool Icontrollable_hgrant2;
+bool Icontrollable_hgrant3;
+bool Icontrollable_ndecide;
+bool Icontrollable_nhgrant0;
+bool Ln47;
+bool Lreg_controllable_hgrant2_out;
+bool Lreg_controllable_hmaster1_out;
+bool Lreg_controllable_hgrant3_out;
+bool Lnext_env_fair_out;
+bool Lreg_stateG3_0_out;
+bool Lreg_controllable_locked_out;
+bool Lreg_stateG3_1_out;
+bool Lreg_controllable_ndecide_out;
+bool Lreg_stateG3_2_out;
+bool Lreg_i_hbusreq0_out;
+bool Lreg_controllable_busreq_out;
+bool Lreg_controllable_nstart_out;
+bool Lreg_i_hbusreq1_out;
+bool Lreg_i_hlock3_out;
+bool Lreg_stateG2_out;
+bool Lreg_stateG10_1_out;
+bool Lreg_controllable_nhgrant0_out;
+bool Lreg_i_hlock2_out;
+bool Lreg_stateG10_2_out;
+bool Lreg_stateA1_out;
+bool Lreg_controllable_hmastlock_out;
+bool Lreg_i_hbusreq2_out;
+bool Lnext_sys_fair0_out;
+bool Lnext_sys_fair1_out;
+bool Lnext_sys_fair2_out;
+bool Lnext_sys_fair3_out;
+bool Lreg_i_hlock1_out;
+bool Lreg_stateG10_3_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lreg_i_hbusreq3_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_hlock0_out;
+bool Lreg_i_hready_out;
+bool Lreg_controllable_hgrant1_out;
+bool Lreg_controllable_hmaster0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hbusreq3,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hlock3,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_hgrant3,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn47,
+    UpdatedLn47_becomes0 { x_46 <= 1000 },
+    UpdatedLn47_becomes1 { x_46 <= 1500 },
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hgrant2_out_becomes0 { x_48 <= 500 },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 { x_48 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hmaster1_out_becomes0 { x_50 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 { x_50 <= 3000 },
+    UpdatedLreg_controllable_hgrant3_out,
+    UpdatedLreg_controllable_hgrant3_out_becomes0 { x_52 <= 3000 },
+    UpdatedLreg_controllable_hgrant3_out_becomes1 { x_52 <= 0 },
+    UpdatedLnext_env_fair_out,
+    UpdatedLnext_env_fair_out_becomes0 { x_54 <= 2500 },
+    UpdatedLnext_env_fair_out_becomes1 { x_54 <= 0 },
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLreg_stateG3_0_out_becomes0 { x_56 <= 4000 },
+    UpdatedLreg_stateG3_0_out_becomes1 { x_56 <= 2000 },
+    UpdatedLreg_controllable_locked_out,
+    UpdatedLreg_controllable_locked_out_becomes0 { x_58 <= 1000 },
+    UpdatedLreg_controllable_locked_out_becomes1 { x_58 <= 500 },
+    dead;
+urgent
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hbusreq3,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hlock3,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_hgrant3,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn47,
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hgrant3_out,
+    UpdatedLnext_env_fair_out,
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLreg_controllable_locked_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 0; },
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 1; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 0; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 1; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 0; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 1; },
+    JustSetIi_hbusreq2 -> JustSetIi_hbusreq3 { assign Ii_hbusreq3 := 0; },
+    JustSetIi_hbusreq2 -> JustSetIi_hbusreq3 { assign Ii_hbusreq3 := 1; },
+    JustSetIi_hbusreq3 -> JustSetIi_hburst1 { assign Ii_hburst1 := 0; },
+    JustSetIi_hbusreq3 -> JustSetIi_hburst1 { assign Ii_hburst1 := 1; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 0; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 1; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 0; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 1; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 0; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 1; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 0; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 1; },
+    JustSetIi_hlock2 -> JustSetIi_hlock3 { assign Ii_hlock3 := 0; },
+    JustSetIi_hlock2 -> JustSetIi_hlock3 { assign Ii_hlock3 := 1; },
+    JustSetIi_hlock3 -> JustSetIi_hready { assign Ii_hready := 0; },
+    JustSetIi_hlock3 -> JustSetIi_hready { assign Ii_hready := 1; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 0; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 1; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 0; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 1; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 0; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 1; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 0; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 1; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 0; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 1; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 0; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 1; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 0; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 1; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 0; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 1; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_hgrant3 { assign Icontrollable_hgrant3 := 0; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_hgrant3 { assign Icontrollable_hgrant3 := 1; },
+    JustSetIcontrollable_hgrant3 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 0; },
+    JustSetIcontrollable_hgrant3 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 1; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 0; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 1 && Ln47 != 1 && x_46 >= 1000; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 0 && Ln47 != 1 && x_46 >= 1500; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47_becomes0 { guard Ln47 == 1 && Ln47 != 1 && x_46 < 1000; },
+    UpdatedLn47_becomes0 -> UpdatedLn47 { guard x_46 >= 1000; assign x_46:=0, Ln47 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47_becomes1 { guard Ln47 == 0 && Ln47 != 1 && x_46 < 1500; },
+    UpdatedLn47_becomes1 -> UpdatedLn47 { guard x_46 >= 1500; assign x_46:=0, Ln47 := 1; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == (Icontrollable_hgrant2); },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 >= 500; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 >= 2000; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out_becomes0 { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 < 500; },
+    UpdatedLreg_controllable_hgrant2_out_becomes0 -> UpdatedLreg_controllable_hgrant2_out { guard x_48 >= 500; assign x_48:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out_becomes1 { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 < 2000; },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 -> UpdatedLreg_controllable_hgrant2_out { guard x_48 >= 2000; assign x_48:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 >= 2000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 >= 3000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes0 { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 < 2000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes0 -> UpdatedLreg_controllable_hmaster1_out { guard x_50 >= 2000; assign x_50:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes1 { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 < 3000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 -> UpdatedLreg_controllable_hmaster1_out { guard x_50 >= 3000; assign x_50:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == 1 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 >= 3000; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == 0 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 >= 0; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out_becomes0 { guard Lreg_controllable_hgrant3_out == 1 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 < 3000; },
+    UpdatedLreg_controllable_hgrant3_out_becomes0 -> UpdatedLreg_controllable_hgrant3_out { guard x_52 >= 3000; assign x_52:=0, Lreg_controllable_hgrant3_out := (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out_becomes1 { guard Lreg_controllable_hgrant3_out == 0 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 < 0; },
+    UpdatedLreg_controllable_hgrant3_out_becomes1 -> UpdatedLreg_controllable_hgrant3_out { guard x_52 >= 0; assign x_52:=0, Lreg_controllable_hgrant3_out := (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == 1 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 >= 2500; },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == 0 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 >= 0; },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out_becomes0 { guard Lnext_env_fair_out == 1 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 < 2500; },
+    UpdatedLnext_env_fair_out_becomes0 -> UpdatedLnext_env_fair_out { guard x_54 >= 2500; assign x_54:=0, Lnext_env_fair_out := (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out_becomes1 { guard Lnext_env_fair_out == 0 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 < 0; },
+    UpdatedLnext_env_fair_out_becomes1 -> UpdatedLnext_env_fair_out { guard x_54 >= 0; assign x_54:=0, Lnext_env_fair_out := (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 >= 4000; },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 >= 2000; },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out_becomes0 { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 < 4000; },
+    UpdatedLreg_stateG3_0_out_becomes0 -> UpdatedLreg_stateG3_0_out { guard x_56 >= 4000; assign x_56:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out_becomes1 { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 < 2000; },
+    UpdatedLreg_stateG3_0_out_becomes1 -> UpdatedLreg_stateG3_0_out { guard x_56 >= 2000; assign x_56:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == (Icontrollable_locked); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == 1 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 >= 1000; },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == 0 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 >= 500; },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out_becomes0 { guard Lreg_controllable_locked_out == 1 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 < 1000; },
+    UpdatedLreg_controllable_locked_out_becomes0 -> UpdatedLreg_controllable_locked_out { guard x_58 >= 1000; assign x_58:=0, Lreg_controllable_locked_out := (Icontrollable_locked); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out_becomes1 { guard Lreg_controllable_locked_out == 0 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 < 500; },
+    UpdatedLreg_controllable_locked_out_becomes1 -> UpdatedLreg_controllable_locked_out { guard x_58 >= 500; assign x_58:=0, Lreg_controllable_locked_out := (Icontrollable_locked); },
+    UpdatedLreg_controllable_locked_out -> Init { guard T <= 3000; assign T:=0; },
+    UpdatedLreg_controllable_locked_out -> dead { guard T >3000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_9L_300.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_9L_300.xta
new file mode 100644
index 0000000000..c4c521c43f
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/amba4c7y.aag_9L_300.xta
@@ -0,0 +1,277 @@
+ clock x_46;
+clock x_48;
+clock x_50;
+clock x_52;
+clock x_54;
+clock x_56;
+clock x_58;
+clock x_60;
+clock x_62;
+clock T;
+bool Ii_hbusreq0;
+bool Ii_hbusreq1;
+bool Ii_hbusreq2;
+bool Ii_hbusreq3;
+bool Ii_hburst1;
+bool Ii_hburst0;
+bool Ii_hlock0;
+bool Ii_hlock1;
+bool Ii_hlock2;
+bool Ii_hlock3;
+bool Ii_hready;
+bool Icontrollable_hmastlock;
+bool Icontrollable_nstart;
+bool Icontrollable_hmaster1;
+bool Icontrollable_locked;
+bool Icontrollable_hmaster0;
+bool Icontrollable_hgrant1;
+bool Icontrollable_busreq;
+bool Icontrollable_hgrant2;
+bool Icontrollable_hgrant3;
+bool Icontrollable_ndecide;
+bool Icontrollable_nhgrant0;
+bool Ln47;
+bool Lreg_controllable_hgrant2_out;
+bool Lreg_controllable_hmaster1_out;
+bool Lreg_controllable_hgrant3_out;
+bool Lnext_env_fair_out;
+bool Lreg_stateG3_0_out;
+bool Lreg_controllable_locked_out;
+bool Lreg_stateG3_1_out;
+bool Lreg_controllable_ndecide_out;
+bool Lreg_stateG3_2_out;
+bool Lreg_i_hbusreq0_out;
+bool Lreg_controllable_busreq_out;
+bool Lreg_controllable_nstart_out;
+bool Lreg_i_hbusreq1_out;
+bool Lreg_i_hlock3_out;
+bool Lreg_stateG2_out;
+bool Lreg_stateG10_1_out;
+bool Lreg_controllable_nhgrant0_out;
+bool Lreg_i_hlock2_out;
+bool Lreg_stateG10_2_out;
+bool Lreg_stateA1_out;
+bool Lreg_controllable_hmastlock_out;
+bool Lreg_i_hbusreq2_out;
+bool Lnext_sys_fair0_out;
+bool Lnext_sys_fair1_out;
+bool Lnext_sys_fair2_out;
+bool Lnext_sys_fair3_out;
+bool Lreg_i_hlock1_out;
+bool Lreg_stateG10_3_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lreg_i_hbusreq3_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_hlock0_out;
+bool Lreg_i_hready_out;
+bool Lreg_controllable_hgrant1_out;
+bool Lreg_controllable_hmaster0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hbusreq3,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hlock3,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_hgrant3,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn47,
+    UpdatedLn47_becomes0 { x_46 <= 1000 },
+    UpdatedLn47_becomes1 { x_46 <= 1500 },
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hgrant2_out_becomes0 { x_48 <= 500 },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 { x_48 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hmaster1_out_becomes0 { x_50 <= 2000 },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 { x_50 <= 3000 },
+    UpdatedLreg_controllable_hgrant3_out,
+    UpdatedLreg_controllable_hgrant3_out_becomes0 { x_52 <= 3000 },
+    UpdatedLreg_controllable_hgrant3_out_becomes1 { x_52 <= 0 },
+    UpdatedLnext_env_fair_out,
+    UpdatedLnext_env_fair_out_becomes0 { x_54 <= 2500 },
+    UpdatedLnext_env_fair_out_becomes1 { x_54 <= 0 },
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLreg_stateG3_0_out_becomes0 { x_56 <= 4000 },
+    UpdatedLreg_stateG3_0_out_becomes1 { x_56 <= 2000 },
+    UpdatedLreg_controllable_locked_out,
+    UpdatedLreg_controllable_locked_out_becomes0 { x_58 <= 1000 },
+    UpdatedLreg_controllable_locked_out_becomes1 { x_58 <= 500 },
+    UpdatedLreg_stateG3_1_out,
+    UpdatedLreg_stateG3_1_out_becomes0 { x_60 <= 1000 },
+    UpdatedLreg_stateG3_1_out_becomes1 { x_60 <= 500 },
+    UpdatedLreg_controllable_ndecide_out,
+    UpdatedLreg_controllable_ndecide_out_becomes0 { x_62 <= 2000 },
+    UpdatedLreg_controllable_ndecide_out_becomes1 { x_62 <= 1500 },
+    dead;
+urgent
+    Init,
+    JustSetIi_hbusreq0,
+    JustSetIi_hbusreq1,
+    JustSetIi_hbusreq2,
+    JustSetIi_hbusreq3,
+    JustSetIi_hburst1,
+    JustSetIi_hburst0,
+    JustSetIi_hlock0,
+    JustSetIi_hlock1,
+    JustSetIi_hlock2,
+    JustSetIi_hlock3,
+    JustSetIi_hready,
+    JustSetIcontrollable_hmastlock,
+    JustSetIcontrollable_nstart,
+    JustSetIcontrollable_hmaster1,
+    JustSetIcontrollable_locked,
+    JustSetIcontrollable_hmaster0,
+    JustSetIcontrollable_hgrant1,
+    JustSetIcontrollable_busreq,
+    JustSetIcontrollable_hgrant2,
+    JustSetIcontrollable_hgrant3,
+    JustSetIcontrollable_ndecide,
+    JustSetIcontrollable_nhgrant0,
+    UpdatedLn47,
+    UpdatedLreg_controllable_hgrant2_out,
+    UpdatedLreg_controllable_hmaster1_out,
+    UpdatedLreg_controllable_hgrant3_out,
+    UpdatedLnext_env_fair_out,
+    UpdatedLreg_stateG3_0_out,
+    UpdatedLreg_controllable_locked_out,
+    UpdatedLreg_stateG3_1_out,
+    UpdatedLreg_controllable_ndecide_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 0; },
+    Init -> JustSetIi_hbusreq0 { assign Ii_hbusreq0 := 1; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 0; },
+    JustSetIi_hbusreq0 -> JustSetIi_hbusreq1 { assign Ii_hbusreq1 := 1; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 0; },
+    JustSetIi_hbusreq1 -> JustSetIi_hbusreq2 { assign Ii_hbusreq2 := 1; },
+    JustSetIi_hbusreq2 -> JustSetIi_hbusreq3 { assign Ii_hbusreq3 := 0; },
+    JustSetIi_hbusreq2 -> JustSetIi_hbusreq3 { assign Ii_hbusreq3 := 1; },
+    JustSetIi_hbusreq3 -> JustSetIi_hburst1 { assign Ii_hburst1 := 0; },
+    JustSetIi_hbusreq3 -> JustSetIi_hburst1 { assign Ii_hburst1 := 1; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 0; },
+    JustSetIi_hburst1 -> JustSetIi_hburst0 { assign Ii_hburst0 := 1; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 0; },
+    JustSetIi_hburst0 -> JustSetIi_hlock0 { assign Ii_hlock0 := 1; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 0; },
+    JustSetIi_hlock0 -> JustSetIi_hlock1 { assign Ii_hlock1 := 1; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 0; },
+    JustSetIi_hlock1 -> JustSetIi_hlock2 { assign Ii_hlock2 := 1; },
+    JustSetIi_hlock2 -> JustSetIi_hlock3 { assign Ii_hlock3 := 0; },
+    JustSetIi_hlock2 -> JustSetIi_hlock3 { assign Ii_hlock3 := 1; },
+    JustSetIi_hlock3 -> JustSetIi_hready { assign Ii_hready := 0; },
+    JustSetIi_hlock3 -> JustSetIi_hready { assign Ii_hready := 1; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 0; },
+    JustSetIi_hready -> JustSetIcontrollable_hmastlock { assign Icontrollable_hmastlock := 1; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 0; },
+    JustSetIcontrollable_hmastlock -> JustSetIcontrollable_nstart { assign Icontrollable_nstart := 1; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 0; },
+    JustSetIcontrollable_nstart -> JustSetIcontrollable_hmaster1 { assign Icontrollable_hmaster1 := 1; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 0; },
+    JustSetIcontrollable_hmaster1 -> JustSetIcontrollable_locked { assign Icontrollable_locked := 1; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 0; },
+    JustSetIcontrollable_locked -> JustSetIcontrollable_hmaster0 { assign Icontrollable_hmaster0 := 1; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 0; },
+    JustSetIcontrollable_hmaster0 -> JustSetIcontrollable_hgrant1 { assign Icontrollable_hgrant1 := 1; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 0; },
+    JustSetIcontrollable_hgrant1 -> JustSetIcontrollable_busreq { assign Icontrollable_busreq := 1; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 0; },
+    JustSetIcontrollable_busreq -> JustSetIcontrollable_hgrant2 { assign Icontrollable_hgrant2 := 1; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_hgrant3 { assign Icontrollable_hgrant3 := 0; },
+    JustSetIcontrollable_hgrant2 -> JustSetIcontrollable_hgrant3 { assign Icontrollable_hgrant3 := 1; },
+    JustSetIcontrollable_hgrant3 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 0; },
+    JustSetIcontrollable_hgrant3 -> JustSetIcontrollable_ndecide { assign Icontrollable_ndecide := 1; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 0; },
+    JustSetIcontrollable_ndecide -> JustSetIcontrollable_nhgrant0 { assign Icontrollable_nhgrant0 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 1 && Ln47 != 1 && x_46 >= 1000; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47 { guard Ln47 == 0 && Ln47 != 1 && x_46 >= 1500; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47_becomes0 { guard Ln47 == 1 && Ln47 != 1 && x_46 < 1000; },
+    UpdatedLn47_becomes0 -> UpdatedLn47 { guard x_46 >= 1000; assign x_46:=0, Ln47 := 1; },
+    JustSetIcontrollable_nhgrant0 -> UpdatedLn47_becomes1 { guard Ln47 == 0 && Ln47 != 1 && x_46 < 1500; },
+    UpdatedLn47_becomes1 -> UpdatedLn47 { guard x_46 >= 1500; assign x_46:=0, Ln47 := 1; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == (Icontrollable_hgrant2); },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 >= 500; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 >= 2000; },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out_becomes0 { guard Lreg_controllable_hgrant2_out == 1 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 < 500; },
+    UpdatedLreg_controllable_hgrant2_out_becomes0 -> UpdatedLreg_controllable_hgrant2_out { guard x_48 >= 500; assign x_48:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLn47 -> UpdatedLreg_controllable_hgrant2_out_becomes1 { guard Lreg_controllable_hgrant2_out == 0 && Lreg_controllable_hgrant2_out != (Icontrollable_hgrant2) && x_48 < 2000; },
+    UpdatedLreg_controllable_hgrant2_out_becomes1 -> UpdatedLreg_controllable_hgrant2_out { guard x_48 >= 2000; assign x_48:=0, Lreg_controllable_hgrant2_out := (Icontrollable_hgrant2); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 >= 2000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 >= 3000; },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes0 { guard Lreg_controllable_hmaster1_out == 1 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 < 2000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes0 -> UpdatedLreg_controllable_hmaster1_out { guard x_50 >= 2000; assign x_50:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hgrant2_out -> UpdatedLreg_controllable_hmaster1_out_becomes1 { guard Lreg_controllable_hmaster1_out == 0 && Lreg_controllable_hmaster1_out != (Icontrollable_hmaster1) && x_50 < 3000; },
+    UpdatedLreg_controllable_hmaster1_out_becomes1 -> UpdatedLreg_controllable_hmaster1_out { guard x_50 >= 3000; assign x_50:=0, Lreg_controllable_hmaster1_out := (Icontrollable_hmaster1); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == 1 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 >= 3000; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out { guard Lreg_controllable_hgrant3_out == 0 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 >= 0; },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out_becomes0 { guard Lreg_controllable_hgrant3_out == 1 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 < 3000; },
+    UpdatedLreg_controllable_hgrant3_out_becomes0 -> UpdatedLreg_controllable_hgrant3_out { guard x_52 >= 3000; assign x_52:=0, Lreg_controllable_hgrant3_out := (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hmaster1_out -> UpdatedLreg_controllable_hgrant3_out_becomes1 { guard Lreg_controllable_hgrant3_out == 0 && Lreg_controllable_hgrant3_out != (Icontrollable_hgrant3) && x_52 < 0; },
+    UpdatedLreg_controllable_hgrant3_out_becomes1 -> UpdatedLreg_controllable_hgrant3_out { guard x_52 >= 0; assign x_52:=0, Lreg_controllable_hgrant3_out := (Icontrollable_hgrant3); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == 1 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 >= 2500; },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out { guard Lnext_env_fair_out == 0 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 >= 0; },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out_becomes0 { guard Lnext_env_fair_out == 1 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 < 2500; },
+    UpdatedLnext_env_fair_out_becomes0 -> UpdatedLnext_env_fair_out { guard x_54 >= 2500; assign x_54:=0, Lnext_env_fair_out := (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLreg_controllable_hgrant3_out -> UpdatedLnext_env_fair_out_becomes1 { guard Lnext_env_fair_out == 0 && Lnext_env_fair_out != (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))) && x_54 < 0; },
+    UpdatedLnext_env_fair_out_becomes1 -> UpdatedLnext_env_fair_out { guard x_54 >= 0; assign x_54:=0, Lnext_env_fair_out := (!(((Lreg_stateA1_out) && (Ln47)) && !((Lnext_env_fair_out) && (Ln47))) && ((((!((((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && !((Lreg_stateG2_out) && (Ln47))) && !(!(!((Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq1)) && (((((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))))) && (!((((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && !(!(!(!(Icontrollable_hmaster0) && !(Icontrollable_hmaster1)) && (Ii_hbusreq0)) && (((((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && !((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && (!(!(!(!(Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq2)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && !((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))) && !(!(!((Icontrollable_hmaster0) && (Icontrollable_hmaster1)) && (Ii_hbusreq3)) && (((!((Lnext_sys_fair1_out) && (Ln47)) && ((Lnext_sys_fair0_out) && (Ln47))) && ((Lnext_sys_fair2_out) && (Ln47))) && !((Lnext_sys_fair3_out) && (Ln47)))))) && !(((Lnext_env_fair_out) && (Ln47)) && (Ii_hready)))); },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 >= 4000; },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 >= 2000; },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out_becomes0 { guard Lreg_stateG3_0_out == 1 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 < 4000; },
+    UpdatedLreg_stateG3_0_out_becomes0 -> UpdatedLreg_stateG3_0_out { guard x_56 >= 4000; assign x_56:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLnext_env_fair_out -> UpdatedLreg_stateG3_0_out_becomes1 { guard Lreg_stateG3_0_out == 0 && Lreg_stateG3_0_out != !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))) && x_56 < 2000; },
+    UpdatedLreg_stateG3_0_out_becomes1 -> UpdatedLreg_stateG3_0_out { guard x_56 >= 2000; assign x_56:=0, Lreg_stateG3_0_out := !(!((!((!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && ((Lreg_stateG3_0_out) && (Ln47))) && !(!(!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && !(Ii_hready))); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == (Icontrollable_locked); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == 1 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 >= 1000; },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out { guard Lreg_controllable_locked_out == 0 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 >= 500; },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out_becomes0 { guard Lreg_controllable_locked_out == 1 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 < 1000; },
+    UpdatedLreg_controllable_locked_out_becomes0 -> UpdatedLreg_controllable_locked_out { guard x_58 >= 1000; assign x_58:=0, Lreg_controllable_locked_out := (Icontrollable_locked); },
+    UpdatedLreg_stateG3_0_out -> UpdatedLreg_controllable_locked_out_becomes1 { guard Lreg_controllable_locked_out == 0 && Lreg_controllable_locked_out != (Icontrollable_locked) && x_58 < 500; },
+    UpdatedLreg_controllable_locked_out_becomes1 -> UpdatedLreg_controllable_locked_out { guard x_58 >= 500; assign x_58:=0, Lreg_controllable_locked_out := (Icontrollable_locked); },
+    UpdatedLreg_controllable_locked_out -> UpdatedLreg_stateG3_1_out { guard Lreg_stateG3_1_out == !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))); },
+    UpdatedLreg_controllable_locked_out -> UpdatedLreg_stateG3_1_out { guard Lreg_stateG3_1_out == 1 && Lreg_stateG3_1_out != !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))) && x_60 >= 1000; },
+    UpdatedLreg_controllable_locked_out -> UpdatedLreg_stateG3_1_out { guard Lreg_stateG3_1_out == 0 && Lreg_stateG3_1_out != !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))) && x_60 >= 500; },
+    UpdatedLreg_controllable_locked_out -> UpdatedLreg_stateG3_1_out_becomes0 { guard Lreg_stateG3_1_out == 1 && Lreg_stateG3_1_out != !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))) && x_60 < 1000; },
+    UpdatedLreg_stateG3_1_out_becomes0 -> UpdatedLreg_stateG3_1_out { guard x_60 >= 1000; assign x_60:=0, Lreg_stateG3_1_out := !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))); },
+    UpdatedLreg_controllable_locked_out -> UpdatedLreg_stateG3_1_out_becomes1 { guard Lreg_stateG3_1_out == 0 && Lreg_stateG3_1_out != !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))) && x_60 < 500; },
+    UpdatedLreg_stateG3_1_out_becomes1 -> UpdatedLreg_stateG3_1_out { guard x_60 >= 500; assign x_60:=0, Lreg_stateG3_1_out := !((!((!((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && (!((Lreg_stateG3_2_out) && (Ln47)) && (Ii_hready))) && !(!(((((Lreg_stateG3_1_out) && (Ln47)) && ((Lreg_stateG3_0_out) && (Ln47))) && !((Lreg_stateG3_2_out) && (Ln47))) && (Ii_hready)) && ((Lreg_stateG3_1_out) && (Ln47)))) && !(((((!(Icontrollable_nstart) && (Icontrollable_hmastlock)) && !(Ii_hburst0)) && (!((Lreg_stateG3_2_out) && (Ln47)) && (!((Lreg_stateG3_1_out) && (Ln47)) && !((Lreg_stateG3_0_out) && (Ln47))))) && (Ii_hburst1)) && (Ii_hready))); },
+    UpdatedLreg_stateG3_1_out -> UpdatedLreg_controllable_ndecide_out { guard Lreg_controllable_ndecide_out == (Icontrollable_ndecide); },
+    UpdatedLreg_stateG3_1_out -> UpdatedLreg_controllable_ndecide_out { guard Lreg_controllable_ndecide_out == 1 && Lreg_controllable_ndecide_out != (Icontrollable_ndecide) && x_62 >= 2000; },
+    UpdatedLreg_stateG3_1_out -> UpdatedLreg_controllable_ndecide_out { guard Lreg_controllable_ndecide_out == 0 && Lreg_controllable_ndecide_out != (Icontrollable_ndecide) && x_62 >= 1500; },
+    UpdatedLreg_stateG3_1_out -> UpdatedLreg_controllable_ndecide_out_becomes0 { guard Lreg_controllable_ndecide_out == 1 && Lreg_controllable_ndecide_out != (Icontrollable_ndecide) && x_62 < 2000; },
+    UpdatedLreg_controllable_ndecide_out_becomes0 -> UpdatedLreg_controllable_ndecide_out { guard x_62 >= 2000; assign x_62:=0, Lreg_controllable_ndecide_out := (Icontrollable_ndecide); },
+    UpdatedLreg_stateG3_1_out -> UpdatedLreg_controllable_ndecide_out_becomes1 { guard Lreg_controllable_ndecide_out == 0 && Lreg_controllable_ndecide_out != (Icontrollable_ndecide) && x_62 < 1500; },
+    UpdatedLreg_controllable_ndecide_out_becomes1 -> UpdatedLreg_controllable_ndecide_out { guard x_62 >= 1500; assign x_62:=0, Lreg_controllable_ndecide_out := (Icontrollable_ndecide); },
+    UpdatedLreg_controllable_ndecide_out -> Init { guard T <= 3000; assign T:=0; },
+    UpdatedLreg_controllable_ndecide_out -> dead { guard T >3000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_100.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_100.xta
new file mode 100644
index 0000000000..e8a4275018
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_100.xta
@@ -0,0 +1,110 @@
+ clock x_12;
+clock x_14;
+clock x_16;
+clock x_18;
+clock T;
+bool Ish_0_;
+bool Ish_1_;
+bool Ish_2_;
+bool Ish_3_;
+bool Icontrollable_do_shift;
+bool Lbenchn13;
+bool Lbenchr_0__out;
+bool Lbenchr_1__out;
+bool Lbenchr_2__out;
+bool Lbenchr_3__out;
+bool Lbenchr_4__out;
+bool Lbenchr_5__out;
+bool Lbenchr_6__out;
+bool Lbenchr_7__out;
+bool Lbenchr_8__out;
+bool Lbenchr_9__out;
+bool Lbenchr_10__out;
+bool Lbenchr_11__out;
+bool Lbenchr_12__out;
+bool Lbenchr_13__out;
+bool Lbenchr_14__out;
+bool Lbenchr_15__out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIsh_0_,
+    JustSetIsh_1_,
+    JustSetIsh_2_,
+    JustSetIsh_3_,
+    JustSetIcontrollable_do_shift,
+    UpdatedLbenchn13,
+    UpdatedLbenchn13_becomes0 {x_12 <= 1000},
+    UpdatedLbenchn13_becomes1 {x_12 <= 1500},
+    UpdatedLbenchr_0__out,
+    UpdatedLbenchr_0__out_becomes0 {x_14 <= 500},
+    UpdatedLbenchr_0__out_becomes1 {x_14 <= 2000},
+    UpdatedLbenchr_1__out,
+    UpdatedLbenchr_1__out_becomes0 {x_16 <= 2000},
+    UpdatedLbenchr_1__out_becomes1 {x_16 <= 3000},
+    UpdatedLbenchr_2__out,
+    UpdatedLbenchr_2__out_becomes0 {x_18 <= 3000},
+    UpdatedLbenchr_2__out_becomes1 {x_18 <= 0},
+    dead;
+urgent
+    Init,
+    JustSetIsh_0_,
+    JustSetIsh_1_,
+    JustSetIsh_2_,
+    JustSetIsh_3_,
+    JustSetIcontrollable_do_shift,
+    UpdatedLbenchn13,
+    UpdatedLbenchr_0__out,
+    UpdatedLbenchr_1__out,
+    UpdatedLbenchr_2__out;
+init Init;
+trans
+    Init -> JustSetIsh_0_ { assign Ish_0_ := 0;  },
+    Init -> JustSetIsh_0_ { assign Ish_0_ := 1;  },
+    JustSetIsh_0_ -> JustSetIsh_1_ { assign Ish_1_ := 0;  },
+    JustSetIsh_0_ -> JustSetIsh_1_ { assign Ish_1_ := 1;  },
+    JustSetIsh_1_ -> JustSetIsh_2_ { assign Ish_2_ := 0;  },
+    JustSetIsh_1_ -> JustSetIsh_2_ { assign Ish_2_ := 1;  },
+    JustSetIsh_2_ -> JustSetIsh_3_ { assign Ish_3_ := 0;  },
+    JustSetIsh_2_ -> JustSetIsh_3_ { assign Ish_3_ := 1;  },
+    JustSetIsh_3_ -> JustSetIcontrollable_do_shift { assign Icontrollable_do_shift := 0;  },
+    JustSetIsh_3_ -> JustSetIcontrollable_do_shift { assign Icontrollable_do_shift := 1;  },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13 { guard Lbenchn13 == true;  },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13 { guard Lbenchn13 == true && Lbenchn13 != true && x_12 >= 1000;  },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13 { guard Lbenchn13 == 0 && Lbenchn13 != 1 && x_12 >= 1500;  },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13_becomes0 { guard Lbenchn13 == 1 && Lbenchn13 != 1 && x_12 < 1000;  },
+    UpdatedLbenchn13_becomes0 -> UpdatedLbenchn13 { guard x_12 >= 1000; assign x_12:=0, Lbenchn13 := 1;  },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13_becomes1 { guard Lbenchn13 == 0 && Lbenchn13 != 1 && x_12 < 1500;  },
+    UpdatedLbenchn13_becomes1 -> UpdatedLbenchn13 { guard x_12 >= 1500; assign x_12:=0, Lbenchn13 := 1;  },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out { guard Lbenchr_0__out == !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out { guard Lbenchr_0__out == 1 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 >= 500;  },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out { guard Lbenchr_0__out == 0 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 >= 2000;  },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out_becomes0 { guard Lbenchr_0__out == 1 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 < 500;  },
+    UpdatedLbenchr_0__out_becomes0 -> UpdatedLbenchr_0__out { guard x_14 >= 500; assign x_14:=0, Lbenchr_0__out := !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out_becomes1 { guard Lbenchr_0__out == 0 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 < 2000;  },
+    UpdatedLbenchr_0__out_becomes1 -> UpdatedLbenchr_0__out { guard x_14 >= 2000; assign x_14:=0, Lbenchr_0__out := !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out { guard Lbenchr_1__out == !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out { guard Lbenchr_1__out == 1 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 >= 2000;  },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out { guard Lbenchr_1__out == 0 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 >= 3000;  },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out_becomes0 { guard Lbenchr_1__out == 1 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 < 2000;  },
+    UpdatedLbenchr_1__out_becomes0 -> UpdatedLbenchr_1__out { guard x_16 >= 2000; assign x_16:=0, Lbenchr_1__out := !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out_becomes1 { guard Lbenchr_1__out == 0 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 < 3000;  },
+    UpdatedLbenchr_1__out_becomes1 -> UpdatedLbenchr_1__out { guard x_16 >= 3000; assign x_16:=0, Lbenchr_1__out := !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out { guard Lbenchr_2__out == !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out { guard Lbenchr_2__out == 1 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 >= 3000;  },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out { guard Lbenchr_2__out == 0 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 >= 0;  },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out_becomes0 { guard Lbenchr_2__out == 1 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 < 3000;  },
+    UpdatedLbenchr_2__out_becomes0 -> UpdatedLbenchr_2__out { guard x_18 >= 3000; assign x_18:=0, Lbenchr_2__out := !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out_becomes1 { guard Lbenchr_2__out == 0 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 < 0;  },
+    UpdatedLbenchr_2__out_becomes1 -> UpdatedLbenchr_2__out { guard x_18 >= 0; assign x_18:=0, Lbenchr_2__out := !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift)));  },
+    UpdatedLbenchr_2__out -> Init { guard T <= 1000; assign T:=0;  },
+    UpdatedLbenchr_2__out -> dead { guard T >1000;  };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_200.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_200.xta
new file mode 100644
index 0000000000..f16bb223c9
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/bs16y.aag_4L_200.xta
@@ -0,0 +1,111 @@
+ clock x_12;
+clock x_14;
+clock x_16;
+clock x_18;
+clock T;
+bool Ish_0_;
+bool Ish_1_;
+bool Ish_2_;
+bool Ish_3_;
+bool Icontrollable_do_shift;
+bool Lbenchn13;
+bool Lbenchr_0__out;
+bool Lbenchr_1__out;
+bool Lbenchr_2__out;
+bool Lbenchr_3__out;
+bool Lbenchr_4__out;
+bool Lbenchr_5__out;
+bool Lbenchr_6__out;
+bool Lbenchr_7__out;
+bool Lbenchr_8__out;
+bool Lbenchr_9__out;
+bool Lbenchr_10__out;
+bool Lbenchr_11__out;
+bool Lbenchr_12__out;
+bool Lbenchr_13__out;
+bool Lbenchr_14__out;
+bool Lbenchr_15__out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIsh_0_,
+    JustSetIsh_1_,
+    JustSetIsh_2_,
+    JustSetIsh_3_,
+    JustSetIcontrollable_do_shift,
+    UpdatedLbenchn13,
+    UpdatedLbenchn13_becomes0 { x_12 <= 1000 },
+    UpdatedLbenchn13_becomes1 { x_12 <= 1500 },
+    UpdatedLbenchr_0__out,
+    UpdatedLbenchr_0__out_becomes0 { x_14 <= 500 },
+    UpdatedLbenchr_0__out_becomes1 { x_14 <= 2000 },
+    UpdatedLbenchr_1__out,
+    UpdatedLbenchr_1__out_becomes0 { x_16 <= 2000 },
+    UpdatedLbenchr_1__out_becomes1 { x_16 <= 3000 },
+    UpdatedLbenchr_2__out,
+    UpdatedLbenchr_2__out_becomes0 { x_18 <= 3000 },
+    UpdatedLbenchr_2__out_becomes1 { x_18 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIsh_0_,
+    JustSetIsh_1_,
+    JustSetIsh_2_,
+    JustSetIsh_3_,
+    JustSetIcontrollable_do_shift,
+    UpdatedLbenchn13,
+    UpdatedLbenchr_0__out,
+    UpdatedLbenchr_1__out,
+    UpdatedLbenchr_2__out;
+init
+    Init;
+trans
+    Init -> JustSetIsh_0_ { assign Ish_0_ := 0; },
+    Init -> JustSetIsh_0_ { assign Ish_0_ := 1; },
+    JustSetIsh_0_ -> JustSetIsh_1_ { assign Ish_1_ := 0; },
+    JustSetIsh_0_ -> JustSetIsh_1_ { assign Ish_1_ := 1; },
+    JustSetIsh_1_ -> JustSetIsh_2_ { assign Ish_2_ := 0; },
+    JustSetIsh_1_ -> JustSetIsh_2_ { assign Ish_2_ := 1; },
+    JustSetIsh_2_ -> JustSetIsh_3_ { assign Ish_3_ := 0; },
+    JustSetIsh_2_ -> JustSetIsh_3_ { assign Ish_3_ := 1; },
+    JustSetIsh_3_ -> JustSetIcontrollable_do_shift { assign Icontrollable_do_shift := 0; },
+    JustSetIsh_3_ -> JustSetIcontrollable_do_shift { assign Icontrollable_do_shift := 1; },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13 { guard Lbenchn13 == 1; },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13 { guard Lbenchn13 == 1 && Lbenchn13 != 1 && x_12 >= 1000; },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13 { guard Lbenchn13 == 0 && Lbenchn13 != 1 && x_12 >= 1500; },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13_becomes0 { guard Lbenchn13 == 1 && Lbenchn13 != 1 && x_12 < 1000; },
+    UpdatedLbenchn13_becomes0 -> UpdatedLbenchn13 { guard x_12 >= 1000; assign x_12:=0, Lbenchn13 := 1; },
+    JustSetIcontrollable_do_shift -> UpdatedLbenchn13_becomes1 { guard Lbenchn13 == 0 && Lbenchn13 != 1 && x_12 < 1500; },
+    UpdatedLbenchn13_becomes1 -> UpdatedLbenchn13 { guard x_12 >= 1500; assign x_12:=0, Lbenchn13 := 1; },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out { guard Lbenchr_0__out == !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out { guard Lbenchr_0__out == 1 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 >= 500; },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out { guard Lbenchr_0__out == 0 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 >= 2000; },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out_becomes0 { guard Lbenchr_0__out == 1 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 < 500; },
+    UpdatedLbenchr_0__out_becomes0 -> UpdatedLbenchr_0__out { guard x_14 >= 500; assign x_14:=0, Lbenchr_0__out := !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchn13 -> UpdatedLbenchr_0__out_becomes1 { guard Lbenchr_0__out == 0 && Lbenchr_0__out != !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_14 < 2000; },
+    UpdatedLbenchr_0__out_becomes1 -> UpdatedLbenchr_0__out { guard x_14 >= 2000; assign x_14:=0, Lbenchr_0__out := !(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out { guard Lbenchr_1__out == !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out { guard Lbenchr_1__out == 1 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 >= 2000; },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out { guard Lbenchr_1__out == 0 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 >= 3000; },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out_becomes0 { guard Lbenchr_1__out == 1 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 < 2000; },
+    UpdatedLbenchr_1__out_becomes0 -> UpdatedLbenchr_1__out { guard x_16 >= 2000; assign x_16:=0, Lbenchr_1__out := !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_0__out -> UpdatedLbenchr_1__out_becomes1 { guard Lbenchr_1__out == 0 && Lbenchr_1__out != !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_16 < 3000; },
+    UpdatedLbenchr_1__out_becomes1 -> UpdatedLbenchr_1__out { guard x_16 >= 3000; assign x_16:=0, Lbenchr_1__out := !(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_1__out) && (Lbenchn13)) && !(Ish_0_)) && !(!(!(Lbenchr_0__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_15__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_14__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_13__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_12__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_11__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_10__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_9__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_8__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_7__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_6__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_5__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_4__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_3__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_2__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out { guard Lbenchr_2__out == !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out { guard Lbenchr_2__out == 1 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 >= 3000; },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out { guard Lbenchr_2__out == 0 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 >= 0; },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out_becomes0 { guard Lbenchr_2__out == 1 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 < 3000; },
+    UpdatedLbenchr_2__out_becomes0 -> UpdatedLbenchr_2__out { guard x_18 >= 3000; assign x_18:=0, Lbenchr_2__out := !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_1__out -> UpdatedLbenchr_2__out_becomes1 { guard Lbenchr_2__out == 0 && Lbenchr_2__out != !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))) && x_18 < 0; },
+    UpdatedLbenchr_2__out_becomes1 -> UpdatedLbenchr_2__out { guard x_18 >= 0; assign x_18:=0, Lbenchr_2__out := !(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Icontrollable_do_shift)) && !(!(!(!(!(!(!(!(!(((Lbenchr_2__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_1__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(!(!(Lbenchr_0__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_15__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_14__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_13__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_12__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_11__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && !(Ish_3_)) && !(!(!(!(!(!(!(((Lbenchr_10__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_9__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_8__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_7__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && !(Ish_2_)) && !(!(!(!(!(((Lbenchr_6__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_5__out) && (Lbenchn13)) && (Ish_0_))) && !(Ish_1_)) && !(!(!(((Lbenchr_4__out) && (Lbenchn13)) && !(Ish_0_)) && !(((Lbenchr_3__out) && (Lbenchn13)) && (Ish_0_))) && (Ish_1_))) && (Ish_2_))) && (Ish_3_))) && (Icontrollable_do_shift))); },
+    UpdatedLbenchr_2__out -> Init { guard T <= 2000; assign T:=0; },
+    UpdatedLbenchr_2__out -> dead { guard T >2000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_200.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_200.xta
new file mode 100644
index 0000000000..8105693315
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_200.xta
@@ -0,0 +1,85 @@
+ clock x_6;
+clock x_8;
+clock x_10;
+clock x_12;
+clock T;
+bool Istay;
+bool Icontrollable_reset;
+bool Ln7;
+bool Lcounter0_out;
+bool Lcounter1_out;
+bool Lcounter2_out;
+bool Lcounter3_out;
+bool Lcounter4_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLn7_becomes0 { x_6 <= 1000 },
+    UpdatedLn7_becomes1 { x_6 <= 1500 },
+    UpdatedLcounter0_out,
+    UpdatedLcounter0_out_becomes0 { x_8 <= 500 },
+    UpdatedLcounter0_out_becomes1 { x_8 <= 2000 },
+    UpdatedLcounter1_out,
+    UpdatedLcounter1_out_becomes0 { x_10 <= 2000 },
+    UpdatedLcounter1_out_becomes1 { x_10 <= 3000 },
+    UpdatedLcounter2_out,
+    UpdatedLcounter2_out_becomes0 { x_12 <= 3000 },
+    UpdatedLcounter2_out_becomes1 { x_12 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out;
+init
+    Init;
+trans
+    Init -> JustSetIstay { assign Istay := 0; },
+    Init -> JustSetIstay { assign Istay := 1; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 0; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { guard Ln7 == 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { guard Ln7 == 1 && Ln7 != 1 && x_6 >= 1000; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { guard Ln7 == 0 && Ln7 != 1 && x_6 >= 1500; },
+    JustSetIcontrollable_reset -> UpdatedLn7_becomes0 { guard Ln7 == 1 && Ln7 != 1 && x_6 < 1000; },
+    UpdatedLn7_becomes0 -> UpdatedLn7 { guard x_6 >= 1000; assign x_6:=0, Ln7 := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7_becomes1 { guard Ln7 == 0 && Ln7 != 1 && x_6 < 1500; },
+    UpdatedLn7_becomes1 -> UpdatedLn7 { guard x_6 >= 1500; assign x_6:=0, Ln7 := 1; },
+    UpdatedLn7 -> UpdatedLcounter0_out { guard Lcounter0_out == !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLn7 -> UpdatedLcounter0_out { guard Lcounter0_out == 1 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 >= 500; },
+    UpdatedLn7 -> UpdatedLcounter0_out { guard Lcounter0_out == 0 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 >= 2000; },
+    UpdatedLn7 -> UpdatedLcounter0_out_becomes0 { guard Lcounter0_out == 1 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 < 500; },
+    UpdatedLcounter0_out_becomes0 -> UpdatedLcounter0_out { guard x_8 >= 500; assign x_8:=0, Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLn7 -> UpdatedLcounter0_out_becomes1 { guard Lcounter0_out == 0 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 < 2000; },
+    UpdatedLcounter0_out_becomes1 -> UpdatedLcounter0_out { guard x_8 >= 2000; assign x_8:=0, Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { guard Lcounter1_out == !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { guard Lcounter1_out == 1 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 >= 2000; },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { guard Lcounter1_out == 0 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 >= 3000; },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out_becomes0 { guard Lcounter1_out == 1 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 < 2000; },
+    UpdatedLcounter1_out_becomes0 -> UpdatedLcounter1_out { guard x_10 >= 2000; assign x_10:=0, Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out_becomes1 { guard Lcounter1_out == 0 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 < 3000; },
+    UpdatedLcounter1_out_becomes1 -> UpdatedLcounter1_out { guard x_10 >= 3000; assign x_10:=0, Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { guard Lcounter2_out == !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { guard Lcounter2_out == 1 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 >= 3000; },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { guard Lcounter2_out == 0 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 >= 0; },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out_becomes0 { guard Lcounter2_out == 1 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 < 3000; },
+    UpdatedLcounter2_out_becomes0 -> UpdatedLcounter2_out { guard x_12 >= 3000; assign x_12:=0, Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out_becomes1 { guard Lcounter2_out == 0 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 < 0; },
+    UpdatedLcounter2_out_becomes1 -> UpdatedLcounter2_out { guard x_12 >= 0; assign x_12:=0, Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter2_out -> Init { guard T <= 2000; assign T:=0; },
+    UpdatedLcounter2_out -> dead { guard T >2000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_300.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_300.xta
new file mode 100644
index 0000000000..e59ccc9421
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/cnt5y.aag_4L_300.xta
@@ -0,0 +1,85 @@
+ clock x_6;
+clock x_8;
+clock x_10;
+clock x_12;
+clock T;
+bool Istay;
+bool Icontrollable_reset;
+bool Ln7;
+bool Lcounter0_out;
+bool Lcounter1_out;
+bool Lcounter2_out;
+bool Lcounter3_out;
+bool Lcounter4_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLn7_becomes0 { x_6 <= 1000 },
+    UpdatedLn7_becomes1 { x_6 <= 1500 },
+    UpdatedLcounter0_out,
+    UpdatedLcounter0_out_becomes0 { x_8 <= 500 },
+    UpdatedLcounter0_out_becomes1 { x_8 <= 2000 },
+    UpdatedLcounter1_out,
+    UpdatedLcounter1_out_becomes0 { x_10 <= 2000 },
+    UpdatedLcounter1_out_becomes1 { x_10 <= 3000 },
+    UpdatedLcounter2_out,
+    UpdatedLcounter2_out_becomes0 { x_12 <= 3000 },
+    UpdatedLcounter2_out_becomes1 { x_12 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIstay,
+    JustSetIcontrollable_reset,
+    UpdatedLn7,
+    UpdatedLcounter0_out,
+    UpdatedLcounter1_out,
+    UpdatedLcounter2_out;
+init
+    Init;
+trans
+    Init -> JustSetIstay { assign Istay := 0; },
+    Init -> JustSetIstay { assign Istay := 1; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 0; },
+    JustSetIstay -> JustSetIcontrollable_reset { assign Icontrollable_reset := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { guard Ln7 == 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { guard Ln7 == 1 && Ln7 != 1 && x_6 >= 1000; },
+    JustSetIcontrollable_reset -> UpdatedLn7 { guard Ln7 == 0 && Ln7 != 1 && x_6 >= 1500; },
+    JustSetIcontrollable_reset -> UpdatedLn7_becomes0 { guard Ln7 == 1 && Ln7 != 1 && x_6 < 1000; },
+    UpdatedLn7_becomes0 -> UpdatedLn7 { guard x_6 >= 1000; assign x_6:=0, Ln7 := 1; },
+    JustSetIcontrollable_reset -> UpdatedLn7_becomes1 { guard Ln7 == 0 && Ln7 != 1 && x_6 < 1500; },
+    UpdatedLn7_becomes1 -> UpdatedLn7 { guard x_6 >= 1500; assign x_6:=0, Ln7 := 1; },
+    UpdatedLn7 -> UpdatedLcounter0_out { guard Lcounter0_out == !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLn7 -> UpdatedLcounter0_out { guard Lcounter0_out == 1 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 >= 500; },
+    UpdatedLn7 -> UpdatedLcounter0_out { guard Lcounter0_out == 0 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 >= 2000; },
+    UpdatedLn7 -> UpdatedLcounter0_out_becomes0 { guard Lcounter0_out == 1 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 < 500; },
+    UpdatedLcounter0_out_becomes0 -> UpdatedLcounter0_out { guard x_8 >= 500; assign x_8:=0, Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLn7 -> UpdatedLcounter0_out_becomes1 { guard Lcounter0_out == 0 && Lcounter0_out != !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))) && x_8 < 2000; },
+    UpdatedLcounter0_out_becomes1 -> UpdatedLcounter0_out { guard x_8 >= 2000; assign x_8:=0, Lcounter0_out := !(!(!((Lcounter0_out) && (Ln7)) && !(Istay)) && !(((Lcounter0_out) && (Ln7)) && (Istay))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { guard Lcounter1_out == !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { guard Lcounter1_out == 1 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 >= 2000; },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out { guard Lcounter1_out == 0 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 >= 3000; },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out_becomes0 { guard Lcounter1_out == 1 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 < 2000; },
+    UpdatedLcounter1_out_becomes0 -> UpdatedLcounter1_out { guard x_10 >= 2000; assign x_10:=0, Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter0_out -> UpdatedLcounter1_out_becomes1 { guard Lcounter1_out == 0 && Lcounter1_out != !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))) && x_10 < 3000; },
+    UpdatedLcounter1_out_becomes1 -> UpdatedLcounter1_out { guard x_10 >= 3000; assign x_10:=0, Lcounter1_out := !(!((((Lcounter0_out) && (Ln7)) && !(Istay)) && !((Lcounter1_out) && (Ln7))) && !(!(((Lcounter0_out) && (Ln7)) && !(Istay)) && ((Lcounter1_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { guard Lcounter2_out == !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { guard Lcounter2_out == 1 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 >= 3000; },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out { guard Lcounter2_out == 0 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 >= 0; },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out_becomes0 { guard Lcounter2_out == 1 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 < 3000; },
+    UpdatedLcounter2_out_becomes0 -> UpdatedLcounter2_out { guard x_12 >= 3000; assign x_12:=0, Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter1_out -> UpdatedLcounter2_out_becomes1 { guard Lcounter2_out == 0 && Lcounter2_out != !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))) && x_12 < 0; },
+    UpdatedLcounter2_out_becomes1 -> UpdatedLcounter2_out { guard x_12 >= 0; assign x_12:=0, Lcounter2_out := !(!(((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && !((Lcounter2_out) && (Ln7))) && !(!((((Lcounter1_out) && (Ln7)) && ((Lcounter0_out) && (Ln7))) && !(Istay)) && ((Lcounter2_out) && (Ln7)))); },
+    UpdatedLcounter2_out -> Init { guard T <= 3000; assign T:=0; },
+    UpdatedLcounter2_out -> dead { guard T >3000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_4L_200.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_4L_200.xta
new file mode 100644
index 0000000000..c112412bf7
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_4L_200.xta
@@ -0,0 +1,179 @@
+ clock x_38;
+clock x_40;
+clock x_42;
+clock x_44;
+clock T;
+bool Ip0_0;
+bool Ip0_1;
+bool Ip0_2;
+bool Ip1_0;
+bool Ip1_1;
+bool Ip1_2;
+bool Ip2_0;
+bool Ip2_1;
+bool Ip2_2;
+bool IerrorCount_0_0_1;
+bool Icontrollable_arm1_0_0_2;
+bool Icontrollable_arm1_1;
+bool Icontrollable_arm2_0_0_2;
+bool Icontrollable_arm2_1;
+bool Icontrollable_arm1op_0_0_2;
+bool Icontrollable_arm1op_1;
+bool Icontrollable_arm2op_0_0_2;
+bool Icontrollable_arm2op_1;
+bool LIsNotFirstRound;
+bool Lprev_p0_0;
+bool Lprev_p0_1;
+bool Lprev_p0_2;
+bool Lprev_p1_0;
+bool Lprev_p1_1;
+bool Lprev_p1_2;
+bool Lprev_p2_0;
+bool Lprev_p2_1;
+bool Lprev_p2_2;
+bool Lprev_errorCount_0_0_1;
+bool Lprev_arm1_0_0_2;
+bool Lprev_arm1_1;
+bool Lprev_arm2_0_0_2;
+bool Lprev_arm2_1;
+bool Lprev_arm1op_0_0_2;
+bool Lprev_arm1op_1;
+bool Lprev_arm2op_0_0_2;
+bool Lprev_arm2op_1;
+bool LAssumptionsAlreadyViolated;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIp0_0,
+    JustSetIp0_1,
+    JustSetIp0_2,
+    JustSetIp1_0,
+    JustSetIp1_1,
+    JustSetIp1_2,
+    JustSetIp2_0,
+    JustSetIp2_1,
+    JustSetIp2_2,
+    JustSetIerrorCount_0_0_1,
+    JustSetIcontrollable_arm1_0_0_2,
+    JustSetIcontrollable_arm1_1,
+    JustSetIcontrollable_arm2_0_0_2,
+    JustSetIcontrollable_arm2_1,
+    JustSetIcontrollable_arm1op_0_0_2,
+    JustSetIcontrollable_arm1op_1,
+    JustSetIcontrollable_arm2op_0_0_2,
+    JustSetIcontrollable_arm2op_1,
+    UpdatedLIsNotFirstRound,
+    UpdatedLIsNotFirstRound_becomes0 { x_38 <= 1000 },
+    UpdatedLIsNotFirstRound_becomes1 { x_38 <= 1500 },
+    UpdatedLprev_p0_0,
+    UpdatedLprev_p0_0_becomes0 { x_40 <= 500 },
+    UpdatedLprev_p0_0_becomes1 { x_40 <= 2000 },
+    UpdatedLprev_p0_1,
+    UpdatedLprev_p0_1_becomes0 { x_42 <= 2000 },
+    UpdatedLprev_p0_1_becomes1 { x_42 <= 3000 },
+    UpdatedLprev_p0_2,
+    UpdatedLprev_p0_2_becomes0 { x_44 <= 3000 },
+    UpdatedLprev_p0_2_becomes1 { x_44 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIp0_0,
+    JustSetIp0_1,
+    JustSetIp0_2,
+    JustSetIp1_0,
+    JustSetIp1_1,
+    JustSetIp1_2,
+    JustSetIp2_0,
+    JustSetIp2_1,
+    JustSetIp2_2,
+    JustSetIerrorCount_0_0_1,
+    JustSetIcontrollable_arm1_0_0_2,
+    JustSetIcontrollable_arm1_1,
+    JustSetIcontrollable_arm2_0_0_2,
+    JustSetIcontrollable_arm2_1,
+    JustSetIcontrollable_arm1op_0_0_2,
+    JustSetIcontrollable_arm1op_1,
+    JustSetIcontrollable_arm2op_0_0_2,
+    JustSetIcontrollable_arm2op_1,
+    UpdatedLIsNotFirstRound,
+    UpdatedLprev_p0_0,
+    UpdatedLprev_p0_1,
+    UpdatedLprev_p0_2;
+init
+    Init;
+trans
+    Init -> JustSetIp0_0 { assign Ip0_0 := 0; },
+    Init -> JustSetIp0_0 { assign Ip0_0 := 1; },
+    JustSetIp0_0 -> JustSetIp0_1 { assign Ip0_1 := 0; },
+    JustSetIp0_0 -> JustSetIp0_1 { assign Ip0_1 := 1; },
+    JustSetIp0_1 -> JustSetIp0_2 { assign Ip0_2 := 0; },
+    JustSetIp0_1 -> JustSetIp0_2 { assign Ip0_2 := 1; },
+    JustSetIp0_2 -> JustSetIp1_0 { assign Ip1_0 := 0; },
+    JustSetIp0_2 -> JustSetIp1_0 { assign Ip1_0 := 1; },
+    JustSetIp1_0 -> JustSetIp1_1 { assign Ip1_1 := 0; },
+    JustSetIp1_0 -> JustSetIp1_1 { assign Ip1_1 := 1; },
+    JustSetIp1_1 -> JustSetIp1_2 { assign Ip1_2 := 0; },
+    JustSetIp1_1 -> JustSetIp1_2 { assign Ip1_2 := 1; },
+    JustSetIp1_2 -> JustSetIp2_0 { assign Ip2_0 := 0; },
+    JustSetIp1_2 -> JustSetIp2_0 { assign Ip2_0 := 1; },
+    JustSetIp2_0 -> JustSetIp2_1 { assign Ip2_1 := 0; },
+    JustSetIp2_0 -> JustSetIp2_1 { assign Ip2_1 := 1; },
+    JustSetIp2_1 -> JustSetIp2_2 { assign Ip2_2 := 0; },
+    JustSetIp2_1 -> JustSetIp2_2 { assign Ip2_2 := 1; },
+    JustSetIp2_2 -> JustSetIerrorCount_0_0_1 { assign IerrorCount_0_0_1 := 0; },
+    JustSetIp2_2 -> JustSetIerrorCount_0_0_1 { assign IerrorCount_0_0_1 := 1; },
+    JustSetIerrorCount_0_0_1 -> JustSetIcontrollable_arm1_0_0_2 { assign Icontrollable_arm1_0_0_2 := 0; },
+    JustSetIerrorCount_0_0_1 -> JustSetIcontrollable_arm1_0_0_2 { assign Icontrollable_arm1_0_0_2 := 1; },
+    JustSetIcontrollable_arm1_0_0_2 -> JustSetIcontrollable_arm1_1 { assign Icontrollable_arm1_1 := 0; },
+    JustSetIcontrollable_arm1_0_0_2 -> JustSetIcontrollable_arm1_1 { assign Icontrollable_arm1_1 := 1; },
+    JustSetIcontrollable_arm1_1 -> JustSetIcontrollable_arm2_0_0_2 { assign Icontrollable_arm2_0_0_2 := 0; },
+    JustSetIcontrollable_arm1_1 -> JustSetIcontrollable_arm2_0_0_2 { assign Icontrollable_arm2_0_0_2 := 1; },
+    JustSetIcontrollable_arm2_0_0_2 -> JustSetIcontrollable_arm2_1 { assign Icontrollable_arm2_1 := 0; },
+    JustSetIcontrollable_arm2_0_0_2 -> JustSetIcontrollable_arm2_1 { assign Icontrollable_arm2_1 := 1; },
+    JustSetIcontrollable_arm2_1 -> JustSetIcontrollable_arm1op_0_0_2 { assign Icontrollable_arm1op_0_0_2 := 0; },
+    JustSetIcontrollable_arm2_1 -> JustSetIcontrollable_arm1op_0_0_2 { assign Icontrollable_arm1op_0_0_2 := 1; },
+    JustSetIcontrollable_arm1op_0_0_2 -> JustSetIcontrollable_arm1op_1 { assign Icontrollable_arm1op_1 := 0; },
+    JustSetIcontrollable_arm1op_0_0_2 -> JustSetIcontrollable_arm1op_1 { assign Icontrollable_arm1op_1 := 1; },
+    JustSetIcontrollable_arm1op_1 -> JustSetIcontrollable_arm2op_0_0_2 { assign Icontrollable_arm2op_0_0_2 := 0; },
+    JustSetIcontrollable_arm1op_1 -> JustSetIcontrollable_arm2op_0_0_2 { assign Icontrollable_arm2op_0_0_2 := 1; },
+    JustSetIcontrollable_arm2op_0_0_2 -> JustSetIcontrollable_arm2op_1 { assign Icontrollable_arm2op_1 := 0; },
+    JustSetIcontrollable_arm2op_0_0_2 -> JustSetIcontrollable_arm2op_1 { assign Icontrollable_arm2op_1 := 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 >= 1000; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 >= 1500; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound_becomes0 { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 < 1000; },
+    UpdatedLIsNotFirstRound_becomes0 -> UpdatedLIsNotFirstRound { guard x_38 >= 1000; assign x_38:=0, LIsNotFirstRound := 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound_becomes1 { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 < 1500; },
+    UpdatedLIsNotFirstRound_becomes1 -> UpdatedLIsNotFirstRound { guard x_38 >= 1500; assign x_38:=0, LIsNotFirstRound := 1; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == (Ip0_0); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == 1 && Lprev_p0_0 != (Ip0_0) && x_40 >= 500; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == 0 && Lprev_p0_0 != (Ip0_0) && x_40 >= 2000; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0_becomes0 { guard Lprev_p0_0 == 1 && Lprev_p0_0 != (Ip0_0) && x_40 < 500; },
+    UpdatedLprev_p0_0_becomes0 -> UpdatedLprev_p0_0 { guard x_40 >= 500; assign x_40:=0, Lprev_p0_0 := (Ip0_0); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0_becomes1 { guard Lprev_p0_0 == 0 && Lprev_p0_0 != (Ip0_0) && x_40 < 2000; },
+    UpdatedLprev_p0_0_becomes1 -> UpdatedLprev_p0_0 { guard x_40 >= 2000; assign x_40:=0, Lprev_p0_0 := (Ip0_0); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == (Ip0_1); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == 1 && Lprev_p0_1 != (Ip0_1) && x_42 >= 2000; },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == 0 && Lprev_p0_1 != (Ip0_1) && x_42 >= 3000; },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1_becomes0 { guard Lprev_p0_1 == 1 && Lprev_p0_1 != (Ip0_1) && x_42 < 2000; },
+    UpdatedLprev_p0_1_becomes0 -> UpdatedLprev_p0_1 { guard x_42 >= 2000; assign x_42:=0, Lprev_p0_1 := (Ip0_1); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1_becomes1 { guard Lprev_p0_1 == 0 && Lprev_p0_1 != (Ip0_1) && x_42 < 3000; },
+    UpdatedLprev_p0_1_becomes1 -> UpdatedLprev_p0_1 { guard x_42 >= 3000; assign x_42:=0, Lprev_p0_1 := (Ip0_1); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == (Ip0_2); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == 1 && Lprev_p0_2 != (Ip0_2) && x_44 >= 3000; },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == 0 && Lprev_p0_2 != (Ip0_2) && x_44 >= 0; },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2_becomes0 { guard Lprev_p0_2 == 1 && Lprev_p0_2 != (Ip0_2) && x_44 < 3000; },
+    UpdatedLprev_p0_2_becomes0 -> UpdatedLprev_p0_2 { guard x_44 >= 3000; assign x_44:=0, Lprev_p0_2 := (Ip0_2); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2_becomes1 { guard Lprev_p0_2 == 0 && Lprev_p0_2 != (Ip0_2) && x_44 < 0; },
+    UpdatedLprev_p0_2_becomes1 -> UpdatedLprev_p0_2 { guard x_44 >= 0; assign x_44:=0, Lprev_p0_2 := (Ip0_2); },
+    UpdatedLprev_p0_2 -> Init { guard T <= 2000; assign T:=0; },
+    UpdatedLprev_p0_2 -> dead { guard T >2000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_6L_300.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_6L_300.xta
new file mode 100644
index 0000000000..943349b8c9
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_6L_300.xta
@@ -0,0 +1,203 @@
+ clock x_38;
+clock x_40;
+clock x_42;
+clock x_44;
+clock x_46;
+clock x_48;
+clock T;
+bool Ip0_0;
+bool Ip0_1;
+bool Ip0_2;
+bool Ip1_0;
+bool Ip1_1;
+bool Ip1_2;
+bool Ip2_0;
+bool Ip2_1;
+bool Ip2_2;
+bool IerrorCount_0_0_1;
+bool Icontrollable_arm1_0_0_2;
+bool Icontrollable_arm1_1;
+bool Icontrollable_arm2_0_0_2;
+bool Icontrollable_arm2_1;
+bool Icontrollable_arm1op_0_0_2;
+bool Icontrollable_arm1op_1;
+bool Icontrollable_arm2op_0_0_2;
+bool Icontrollable_arm2op_1;
+bool LIsNotFirstRound;
+bool Lprev_p0_0;
+bool Lprev_p0_1;
+bool Lprev_p0_2;
+bool Lprev_p1_0;
+bool Lprev_p1_1;
+bool Lprev_p1_2;
+bool Lprev_p2_0;
+bool Lprev_p2_1;
+bool Lprev_p2_2;
+bool Lprev_errorCount_0_0_1;
+bool Lprev_arm1_0_0_2;
+bool Lprev_arm1_1;
+bool Lprev_arm2_0_0_2;
+bool Lprev_arm2_1;
+bool Lprev_arm1op_0_0_2;
+bool Lprev_arm1op_1;
+bool Lprev_arm2op_0_0_2;
+bool Lprev_arm2op_1;
+bool LAssumptionsAlreadyViolated;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIp0_0,
+    JustSetIp0_1,
+    JustSetIp0_2,
+    JustSetIp1_0,
+    JustSetIp1_1,
+    JustSetIp1_2,
+    JustSetIp2_0,
+    JustSetIp2_1,
+    JustSetIp2_2,
+    JustSetIerrorCount_0_0_1,
+    JustSetIcontrollable_arm1_0_0_2,
+    JustSetIcontrollable_arm1_1,
+    JustSetIcontrollable_arm2_0_0_2,
+    JustSetIcontrollable_arm2_1,
+    JustSetIcontrollable_arm1op_0_0_2,
+    JustSetIcontrollable_arm1op_1,
+    JustSetIcontrollable_arm2op_0_0_2,
+    JustSetIcontrollable_arm2op_1,
+    UpdatedLIsNotFirstRound,
+    UpdatedLIsNotFirstRound_becomes0 { x_38 <= 1000 },
+    UpdatedLIsNotFirstRound_becomes1 { x_38 <= 1500 },
+    UpdatedLprev_p0_0,
+    UpdatedLprev_p0_0_becomes0 { x_40 <= 500 },
+    UpdatedLprev_p0_0_becomes1 { x_40 <= 2000 },
+    UpdatedLprev_p0_1,
+    UpdatedLprev_p0_1_becomes0 { x_42 <= 2000 },
+    UpdatedLprev_p0_1_becomes1 { x_42 <= 3000 },
+    UpdatedLprev_p0_2,
+    UpdatedLprev_p0_2_becomes0 { x_44 <= 3000 },
+    UpdatedLprev_p0_2_becomes1 { x_44 <= 0 },
+    UpdatedLprev_p1_0,
+    UpdatedLprev_p1_0_becomes0 { x_46 <= 2500 },
+    UpdatedLprev_p1_0_becomes1 { x_46 <= 0 },
+    UpdatedLprev_p1_1,
+    UpdatedLprev_p1_1_becomes0 { x_48 <= 4000 },
+    UpdatedLprev_p1_1_becomes1 { x_48 <= 2000 },
+    dead;
+urgent
+    Init,
+    JustSetIp0_0,
+    JustSetIp0_1,
+    JustSetIp0_2,
+    JustSetIp1_0,
+    JustSetIp1_1,
+    JustSetIp1_2,
+    JustSetIp2_0,
+    JustSetIp2_1,
+    JustSetIp2_2,
+    JustSetIerrorCount_0_0_1,
+    JustSetIcontrollable_arm1_0_0_2,
+    JustSetIcontrollable_arm1_1,
+    JustSetIcontrollable_arm2_0_0_2,
+    JustSetIcontrollable_arm2_1,
+    JustSetIcontrollable_arm1op_0_0_2,
+    JustSetIcontrollable_arm1op_1,
+    JustSetIcontrollable_arm2op_0_0_2,
+    JustSetIcontrollable_arm2op_1,
+    UpdatedLIsNotFirstRound,
+    UpdatedLprev_p0_0,
+    UpdatedLprev_p0_1,
+    UpdatedLprev_p0_2,
+    UpdatedLprev_p1_0,
+    UpdatedLprev_p1_1;
+init
+    Init;
+trans
+    Init -> JustSetIp0_0 { assign Ip0_0 := 0; },
+    Init -> JustSetIp0_0 { assign Ip0_0 := 1; },
+    JustSetIp0_0 -> JustSetIp0_1 { assign Ip0_1 := 0; },
+    JustSetIp0_0 -> JustSetIp0_1 { assign Ip0_1 := 1; },
+    JustSetIp0_1 -> JustSetIp0_2 { assign Ip0_2 := 0; },
+    JustSetIp0_1 -> JustSetIp0_2 { assign Ip0_2 := 1; },
+    JustSetIp0_2 -> JustSetIp1_0 { assign Ip1_0 := 0; },
+    JustSetIp0_2 -> JustSetIp1_0 { assign Ip1_0 := 1; },
+    JustSetIp1_0 -> JustSetIp1_1 { assign Ip1_1 := 0; },
+    JustSetIp1_0 -> JustSetIp1_1 { assign Ip1_1 := 1; },
+    JustSetIp1_1 -> JustSetIp1_2 { assign Ip1_2 := 0; },
+    JustSetIp1_1 -> JustSetIp1_2 { assign Ip1_2 := 1; },
+    JustSetIp1_2 -> JustSetIp2_0 { assign Ip2_0 := 0; },
+    JustSetIp1_2 -> JustSetIp2_0 { assign Ip2_0 := 1; },
+    JustSetIp2_0 -> JustSetIp2_1 { assign Ip2_1 := 0; },
+    JustSetIp2_0 -> JustSetIp2_1 { assign Ip2_1 := 1; },
+    JustSetIp2_1 -> JustSetIp2_2 { assign Ip2_2 := 0; },
+    JustSetIp2_1 -> JustSetIp2_2 { assign Ip2_2 := 1; },
+    JustSetIp2_2 -> JustSetIerrorCount_0_0_1 { assign IerrorCount_0_0_1 := 0; },
+    JustSetIp2_2 -> JustSetIerrorCount_0_0_1 { assign IerrorCount_0_0_1 := 1; },
+    JustSetIerrorCount_0_0_1 -> JustSetIcontrollable_arm1_0_0_2 { assign Icontrollable_arm1_0_0_2 := 0; },
+    JustSetIerrorCount_0_0_1 -> JustSetIcontrollable_arm1_0_0_2 { assign Icontrollable_arm1_0_0_2 := 1; },
+    JustSetIcontrollable_arm1_0_0_2 -> JustSetIcontrollable_arm1_1 { assign Icontrollable_arm1_1 := 0; },
+    JustSetIcontrollable_arm1_0_0_2 -> JustSetIcontrollable_arm1_1 { assign Icontrollable_arm1_1 := 1; },
+    JustSetIcontrollable_arm1_1 -> JustSetIcontrollable_arm2_0_0_2 { assign Icontrollable_arm2_0_0_2 := 0; },
+    JustSetIcontrollable_arm1_1 -> JustSetIcontrollable_arm2_0_0_2 { assign Icontrollable_arm2_0_0_2 := 1; },
+    JustSetIcontrollable_arm2_0_0_2 -> JustSetIcontrollable_arm2_1 { assign Icontrollable_arm2_1 := 0; },
+    JustSetIcontrollable_arm2_0_0_2 -> JustSetIcontrollable_arm2_1 { assign Icontrollable_arm2_1 := 1; },
+    JustSetIcontrollable_arm2_1 -> JustSetIcontrollable_arm1op_0_0_2 { assign Icontrollable_arm1op_0_0_2 := 0; },
+    JustSetIcontrollable_arm2_1 -> JustSetIcontrollable_arm1op_0_0_2 { assign Icontrollable_arm1op_0_0_2 := 1; },
+    JustSetIcontrollable_arm1op_0_0_2 -> JustSetIcontrollable_arm1op_1 { assign Icontrollable_arm1op_1 := 0; },
+    JustSetIcontrollable_arm1op_0_0_2 -> JustSetIcontrollable_arm1op_1 { assign Icontrollable_arm1op_1 := 1; },
+    JustSetIcontrollable_arm1op_1 -> JustSetIcontrollable_arm2op_0_0_2 { assign Icontrollable_arm2op_0_0_2 := 0; },
+    JustSetIcontrollable_arm1op_1 -> JustSetIcontrollable_arm2op_0_0_2 { assign Icontrollable_arm2op_0_0_2 := 1; },
+    JustSetIcontrollable_arm2op_0_0_2 -> JustSetIcontrollable_arm2op_1 { assign Icontrollable_arm2op_1 := 0; },
+    JustSetIcontrollable_arm2op_0_0_2 -> JustSetIcontrollable_arm2op_1 { assign Icontrollable_arm2op_1 := 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 >= 1000; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 >= 1500; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound_becomes0 { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 < 1000; },
+    UpdatedLIsNotFirstRound_becomes0 -> UpdatedLIsNotFirstRound { guard x_38 >= 1000; assign x_38:=0, LIsNotFirstRound := 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound_becomes1 { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 < 1500; },
+    UpdatedLIsNotFirstRound_becomes1 -> UpdatedLIsNotFirstRound { guard x_38 >= 1500; assign x_38:=0, LIsNotFirstRound := 1; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == (Ip0_0); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == 1 && Lprev_p0_0 != (Ip0_0) && x_40 >= 500; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == 0 && Lprev_p0_0 != (Ip0_0) && x_40 >= 2000; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0_becomes0 { guard Lprev_p0_0 == 1 && Lprev_p0_0 != (Ip0_0) && x_40 < 500; },
+    UpdatedLprev_p0_0_becomes0 -> UpdatedLprev_p0_0 { guard x_40 >= 500; assign x_40:=0, Lprev_p0_0 := (Ip0_0); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0_becomes1 { guard Lprev_p0_0 == 0 && Lprev_p0_0 != (Ip0_0) && x_40 < 2000; },
+    UpdatedLprev_p0_0_becomes1 -> UpdatedLprev_p0_0 { guard x_40 >= 2000; assign x_40:=0, Lprev_p0_0 := (Ip0_0); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == (Ip0_1); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == 1 && Lprev_p0_1 != (Ip0_1) && x_42 >= 2000; },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == 0 && Lprev_p0_1 != (Ip0_1) && x_42 >= 3000; },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1_becomes0 { guard Lprev_p0_1 == 1 && Lprev_p0_1 != (Ip0_1) && x_42 < 2000; },
+    UpdatedLprev_p0_1_becomes0 -> UpdatedLprev_p0_1 { guard x_42 >= 2000; assign x_42:=0, Lprev_p0_1 := (Ip0_1); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1_becomes1 { guard Lprev_p0_1 == 0 && Lprev_p0_1 != (Ip0_1) && x_42 < 3000; },
+    UpdatedLprev_p0_1_becomes1 -> UpdatedLprev_p0_1 { guard x_42 >= 3000; assign x_42:=0, Lprev_p0_1 := (Ip0_1); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == (Ip0_2); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == 1 && Lprev_p0_2 != (Ip0_2) && x_44 >= 3000; },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == 0 && Lprev_p0_2 != (Ip0_2) && x_44 >= 0; },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2_becomes0 { guard Lprev_p0_2 == 1 && Lprev_p0_2 != (Ip0_2) && x_44 < 3000; },
+    UpdatedLprev_p0_2_becomes0 -> UpdatedLprev_p0_2 { guard x_44 >= 3000; assign x_44:=0, Lprev_p0_2 := (Ip0_2); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2_becomes1 { guard Lprev_p0_2 == 0 && Lprev_p0_2 != (Ip0_2) && x_44 < 0; },
+    UpdatedLprev_p0_2_becomes1 -> UpdatedLprev_p0_2 { guard x_44 >= 0; assign x_44:=0, Lprev_p0_2 := (Ip0_2); },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0 { guard Lprev_p1_0 == (Ip1_0); },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0 { guard Lprev_p1_0 == 1 && Lprev_p1_0 != (Ip1_0) && x_46 >= 2500; },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0 { guard Lprev_p1_0 == 0 && Lprev_p1_0 != (Ip1_0) && x_46 >= 0; },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0_becomes0 { guard Lprev_p1_0 == 1 && Lprev_p1_0 != (Ip1_0) && x_46 < 2500; },
+    UpdatedLprev_p1_0_becomes0 -> UpdatedLprev_p1_0 { guard x_46 >= 2500; assign x_46:=0, Lprev_p1_0 := (Ip1_0); },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0_becomes1 { guard Lprev_p1_0 == 0 && Lprev_p1_0 != (Ip1_0) && x_46 < 0; },
+    UpdatedLprev_p1_0_becomes1 -> UpdatedLprev_p1_0 { guard x_46 >= 0; assign x_46:=0, Lprev_p1_0 := (Ip1_0); },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1 { guard Lprev_p1_1 == (Ip1_1); },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1 { guard Lprev_p1_1 == 1 && Lprev_p1_1 != (Ip1_1) && x_48 >= 4000; },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1 { guard Lprev_p1_1 == 0 && Lprev_p1_1 != (Ip1_1) && x_48 >= 2000; },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1_becomes0 { guard Lprev_p1_1 == 1 && Lprev_p1_1 != (Ip1_1) && x_48 < 4000; },
+    UpdatedLprev_p1_1_becomes0 -> UpdatedLprev_p1_1 { guard x_48 >= 4000; assign x_48:=0, Lprev_p1_1 := (Ip1_1); },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1_becomes1 { guard Lprev_p1_1 == 0 && Lprev_p1_1 != (Ip1_1) && x_48 < 2000; },
+    UpdatedLprev_p1_1_becomes1 -> UpdatedLprev_p1_1 { guard x_48 >= 2000; assign x_48:=0, Lprev_p1_1 := (Ip1_1); },
+    UpdatedLprev_p1_1 -> Init { guard T <= 3000; assign T:=0; },
+    UpdatedLprev_p1_1 -> dead { guard T >3000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_7L_500.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_7L_500.xta
new file mode 100644
index 0000000000..de38f09e4b
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/factory_assembly_3x3_1_1errors.aag_7L_500.xta
@@ -0,0 +1,215 @@
+ clock x_38;
+clock x_40;
+clock x_42;
+clock x_44;
+clock x_46;
+clock x_48;
+clock x_50;
+clock T;
+bool Ip0_0;
+bool Ip0_1;
+bool Ip0_2;
+bool Ip1_0;
+bool Ip1_1;
+bool Ip1_2;
+bool Ip2_0;
+bool Ip2_1;
+bool Ip2_2;
+bool IerrorCount_0_0_1;
+bool Icontrollable_arm1_0_0_2;
+bool Icontrollable_arm1_1;
+bool Icontrollable_arm2_0_0_2;
+bool Icontrollable_arm2_1;
+bool Icontrollable_arm1op_0_0_2;
+bool Icontrollable_arm1op_1;
+bool Icontrollable_arm2op_0_0_2;
+bool Icontrollable_arm2op_1;
+bool LIsNotFirstRound;
+bool Lprev_p0_0;
+bool Lprev_p0_1;
+bool Lprev_p0_2;
+bool Lprev_p1_0;
+bool Lprev_p1_1;
+bool Lprev_p1_2;
+bool Lprev_p2_0;
+bool Lprev_p2_1;
+bool Lprev_p2_2;
+bool Lprev_errorCount_0_0_1;
+bool Lprev_arm1_0_0_2;
+bool Lprev_arm1_1;
+bool Lprev_arm2_0_0_2;
+bool Lprev_arm2_1;
+bool Lprev_arm1op_0_0_2;
+bool Lprev_arm1op_1;
+bool Lprev_arm2op_0_0_2;
+bool Lprev_arm2op_1;
+bool LAssumptionsAlreadyViolated;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIp0_0,
+    JustSetIp0_1,
+    JustSetIp0_2,
+    JustSetIp1_0,
+    JustSetIp1_1,
+    JustSetIp1_2,
+    JustSetIp2_0,
+    JustSetIp2_1,
+    JustSetIp2_2,
+    JustSetIerrorCount_0_0_1,
+    JustSetIcontrollable_arm1_0_0_2,
+    JustSetIcontrollable_arm1_1,
+    JustSetIcontrollable_arm2_0_0_2,
+    JustSetIcontrollable_arm2_1,
+    JustSetIcontrollable_arm1op_0_0_2,
+    JustSetIcontrollable_arm1op_1,
+    JustSetIcontrollable_arm2op_0_0_2,
+    JustSetIcontrollable_arm2op_1,
+    UpdatedLIsNotFirstRound,
+    UpdatedLIsNotFirstRound_becomes0 { x_38 <= 1000 },
+    UpdatedLIsNotFirstRound_becomes1 { x_38 <= 1500 },
+    UpdatedLprev_p0_0,
+    UpdatedLprev_p0_0_becomes0 { x_40 <= 500 },
+    UpdatedLprev_p0_0_becomes1 { x_40 <= 2000 },
+    UpdatedLprev_p0_1,
+    UpdatedLprev_p0_1_becomes0 { x_42 <= 2000 },
+    UpdatedLprev_p0_1_becomes1 { x_42 <= 3000 },
+    UpdatedLprev_p0_2,
+    UpdatedLprev_p0_2_becomes0 { x_44 <= 3000 },
+    UpdatedLprev_p0_2_becomes1 { x_44 <= 0 },
+    UpdatedLprev_p1_0,
+    UpdatedLprev_p1_0_becomes0 { x_46 <= 2500 },
+    UpdatedLprev_p1_0_becomes1 { x_46 <= 0 },
+    UpdatedLprev_p1_1,
+    UpdatedLprev_p1_1_becomes0 { x_48 <= 4000 },
+    UpdatedLprev_p1_1_becomes1 { x_48 <= 2000 },
+    UpdatedLprev_p1_2,
+    UpdatedLprev_p1_2_becomes0 { x_50 <= 1000 },
+    UpdatedLprev_p1_2_becomes1 { x_50 <= 500 },
+    dead;
+urgent
+    Init,
+    JustSetIp0_0,
+    JustSetIp0_1,
+    JustSetIp0_2,
+    JustSetIp1_0,
+    JustSetIp1_1,
+    JustSetIp1_2,
+    JustSetIp2_0,
+    JustSetIp2_1,
+    JustSetIp2_2,
+    JustSetIerrorCount_0_0_1,
+    JustSetIcontrollable_arm1_0_0_2,
+    JustSetIcontrollable_arm1_1,
+    JustSetIcontrollable_arm2_0_0_2,
+    JustSetIcontrollable_arm2_1,
+    JustSetIcontrollable_arm1op_0_0_2,
+    JustSetIcontrollable_arm1op_1,
+    JustSetIcontrollable_arm2op_0_0_2,
+    JustSetIcontrollable_arm2op_1,
+    UpdatedLIsNotFirstRound,
+    UpdatedLprev_p0_0,
+    UpdatedLprev_p0_1,
+    UpdatedLprev_p0_2,
+    UpdatedLprev_p1_0,
+    UpdatedLprev_p1_1,
+    UpdatedLprev_p1_2;
+init
+    Init;
+trans
+    Init -> JustSetIp0_0 { assign Ip0_0 := 0; },
+    Init -> JustSetIp0_0 { assign Ip0_0 := 1; },
+    JustSetIp0_0 -> JustSetIp0_1 { assign Ip0_1 := 0; },
+    JustSetIp0_0 -> JustSetIp0_1 { assign Ip0_1 := 1; },
+    JustSetIp0_1 -> JustSetIp0_2 { assign Ip0_2 := 0; },
+    JustSetIp0_1 -> JustSetIp0_2 { assign Ip0_2 := 1; },
+    JustSetIp0_2 -> JustSetIp1_0 { assign Ip1_0 := 0; },
+    JustSetIp0_2 -> JustSetIp1_0 { assign Ip1_0 := 1; },
+    JustSetIp1_0 -> JustSetIp1_1 { assign Ip1_1 := 0; },
+    JustSetIp1_0 -> JustSetIp1_1 { assign Ip1_1 := 1; },
+    JustSetIp1_1 -> JustSetIp1_2 { assign Ip1_2 := 0; },
+    JustSetIp1_1 -> JustSetIp1_2 { assign Ip1_2 := 1; },
+    JustSetIp1_2 -> JustSetIp2_0 { assign Ip2_0 := 0; },
+    JustSetIp1_2 -> JustSetIp2_0 { assign Ip2_0 := 1; },
+    JustSetIp2_0 -> JustSetIp2_1 { assign Ip2_1 := 0; },
+    JustSetIp2_0 -> JustSetIp2_1 { assign Ip2_1 := 1; },
+    JustSetIp2_1 -> JustSetIp2_2 { assign Ip2_2 := 0; },
+    JustSetIp2_1 -> JustSetIp2_2 { assign Ip2_2 := 1; },
+    JustSetIp2_2 -> JustSetIerrorCount_0_0_1 { assign IerrorCount_0_0_1 := 0; },
+    JustSetIp2_2 -> JustSetIerrorCount_0_0_1 { assign IerrorCount_0_0_1 := 1; },
+    JustSetIerrorCount_0_0_1 -> JustSetIcontrollable_arm1_0_0_2 { assign Icontrollable_arm1_0_0_2 := 0; },
+    JustSetIerrorCount_0_0_1 -> JustSetIcontrollable_arm1_0_0_2 { assign Icontrollable_arm1_0_0_2 := 1; },
+    JustSetIcontrollable_arm1_0_0_2 -> JustSetIcontrollable_arm1_1 { assign Icontrollable_arm1_1 := 0; },
+    JustSetIcontrollable_arm1_0_0_2 -> JustSetIcontrollable_arm1_1 { assign Icontrollable_arm1_1 := 1; },
+    JustSetIcontrollable_arm1_1 -> JustSetIcontrollable_arm2_0_0_2 { assign Icontrollable_arm2_0_0_2 := 0; },
+    JustSetIcontrollable_arm1_1 -> JustSetIcontrollable_arm2_0_0_2 { assign Icontrollable_arm2_0_0_2 := 1; },
+    JustSetIcontrollable_arm2_0_0_2 -> JustSetIcontrollable_arm2_1 { assign Icontrollable_arm2_1 := 0; },
+    JustSetIcontrollable_arm2_0_0_2 -> JustSetIcontrollable_arm2_1 { assign Icontrollable_arm2_1 := 1; },
+    JustSetIcontrollable_arm2_1 -> JustSetIcontrollable_arm1op_0_0_2 { assign Icontrollable_arm1op_0_0_2 := 0; },
+    JustSetIcontrollable_arm2_1 -> JustSetIcontrollable_arm1op_0_0_2 { assign Icontrollable_arm1op_0_0_2 := 1; },
+    JustSetIcontrollable_arm1op_0_0_2 -> JustSetIcontrollable_arm1op_1 { assign Icontrollable_arm1op_1 := 0; },
+    JustSetIcontrollable_arm1op_0_0_2 -> JustSetIcontrollable_arm1op_1 { assign Icontrollable_arm1op_1 := 1; },
+    JustSetIcontrollable_arm1op_1 -> JustSetIcontrollable_arm2op_0_0_2 { assign Icontrollable_arm2op_0_0_2 := 0; },
+    JustSetIcontrollable_arm1op_1 -> JustSetIcontrollable_arm2op_0_0_2 { assign Icontrollable_arm2op_0_0_2 := 1; },
+    JustSetIcontrollable_arm2op_0_0_2 -> JustSetIcontrollable_arm2op_1 { assign Icontrollable_arm2op_1 := 0; },
+    JustSetIcontrollable_arm2op_0_0_2 -> JustSetIcontrollable_arm2op_1 { assign Icontrollable_arm2op_1 := 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 >= 1000; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 >= 1500; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound_becomes0 { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 < 1000; },
+    UpdatedLIsNotFirstRound_becomes0 -> UpdatedLIsNotFirstRound { guard x_38 >= 1000; assign x_38:=0, LIsNotFirstRound := 1; },
+    JustSetIcontrollable_arm2op_1 -> UpdatedLIsNotFirstRound_becomes1 { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 < 1500; },
+    UpdatedLIsNotFirstRound_becomes1 -> UpdatedLIsNotFirstRound { guard x_38 >= 1500; assign x_38:=0, LIsNotFirstRound := 1; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == (Ip0_0); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == 1 && Lprev_p0_0 != (Ip0_0) && x_40 >= 500; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0 { guard Lprev_p0_0 == 0 && Lprev_p0_0 != (Ip0_0) && x_40 >= 2000; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0_becomes0 { guard Lprev_p0_0 == 1 && Lprev_p0_0 != (Ip0_0) && x_40 < 500; },
+    UpdatedLprev_p0_0_becomes0 -> UpdatedLprev_p0_0 { guard x_40 >= 500; assign x_40:=0, Lprev_p0_0 := (Ip0_0); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_p0_0_becomes1 { guard Lprev_p0_0 == 0 && Lprev_p0_0 != (Ip0_0) && x_40 < 2000; },
+    UpdatedLprev_p0_0_becomes1 -> UpdatedLprev_p0_0 { guard x_40 >= 2000; assign x_40:=0, Lprev_p0_0 := (Ip0_0); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == (Ip0_1); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == 1 && Lprev_p0_1 != (Ip0_1) && x_42 >= 2000; },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1 { guard Lprev_p0_1 == 0 && Lprev_p0_1 != (Ip0_1) && x_42 >= 3000; },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1_becomes0 { guard Lprev_p0_1 == 1 && Lprev_p0_1 != (Ip0_1) && x_42 < 2000; },
+    UpdatedLprev_p0_1_becomes0 -> UpdatedLprev_p0_1 { guard x_42 >= 2000; assign x_42:=0, Lprev_p0_1 := (Ip0_1); },
+    UpdatedLprev_p0_0 -> UpdatedLprev_p0_1_becomes1 { guard Lprev_p0_1 == 0 && Lprev_p0_1 != (Ip0_1) && x_42 < 3000; },
+    UpdatedLprev_p0_1_becomes1 -> UpdatedLprev_p0_1 { guard x_42 >= 3000; assign x_42:=0, Lprev_p0_1 := (Ip0_1); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == (Ip0_2); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == 1 && Lprev_p0_2 != (Ip0_2) && x_44 >= 3000; },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2 { guard Lprev_p0_2 == 0 && Lprev_p0_2 != (Ip0_2) && x_44 >= 0; },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2_becomes0 { guard Lprev_p0_2 == 1 && Lprev_p0_2 != (Ip0_2) && x_44 < 3000; },
+    UpdatedLprev_p0_2_becomes0 -> UpdatedLprev_p0_2 { guard x_44 >= 3000; assign x_44:=0, Lprev_p0_2 := (Ip0_2); },
+    UpdatedLprev_p0_1 -> UpdatedLprev_p0_2_becomes1 { guard Lprev_p0_2 == 0 && Lprev_p0_2 != (Ip0_2) && x_44 < 0; },
+    UpdatedLprev_p0_2_becomes1 -> UpdatedLprev_p0_2 { guard x_44 >= 0; assign x_44:=0, Lprev_p0_2 := (Ip0_2); },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0 { guard Lprev_p1_0 == (Ip1_0); },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0 { guard Lprev_p1_0 == 1 && Lprev_p1_0 != (Ip1_0) && x_46 >= 2500; },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0 { guard Lprev_p1_0 == 0 && Lprev_p1_0 != (Ip1_0) && x_46 >= 0; },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0_becomes0 { guard Lprev_p1_0 == 1 && Lprev_p1_0 != (Ip1_0) && x_46 < 2500; },
+    UpdatedLprev_p1_0_becomes0 -> UpdatedLprev_p1_0 { guard x_46 >= 2500; assign x_46:=0, Lprev_p1_0 := (Ip1_0); },
+    UpdatedLprev_p0_2 -> UpdatedLprev_p1_0_becomes1 { guard Lprev_p1_0 == 0 && Lprev_p1_0 != (Ip1_0) && x_46 < 0; },
+    UpdatedLprev_p1_0_becomes1 -> UpdatedLprev_p1_0 { guard x_46 >= 0; assign x_46:=0, Lprev_p1_0 := (Ip1_0); },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1 { guard Lprev_p1_1 == (Ip1_1); },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1 { guard Lprev_p1_1 == 1 && Lprev_p1_1 != (Ip1_1) && x_48 >= 4000; },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1 { guard Lprev_p1_1 == 0 && Lprev_p1_1 != (Ip1_1) && x_48 >= 2000; },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1_becomes0 { guard Lprev_p1_1 == 1 && Lprev_p1_1 != (Ip1_1) && x_48 < 4000; },
+    UpdatedLprev_p1_1_becomes0 -> UpdatedLprev_p1_1 { guard x_48 >= 4000; assign x_48:=0, Lprev_p1_1 := (Ip1_1); },
+    UpdatedLprev_p1_0 -> UpdatedLprev_p1_1_becomes1 { guard Lprev_p1_1 == 0 && Lprev_p1_1 != (Ip1_1) && x_48 < 2000; },
+    UpdatedLprev_p1_1_becomes1 -> UpdatedLprev_p1_1 { guard x_48 >= 2000; assign x_48:=0, Lprev_p1_1 := (Ip1_1); },
+    UpdatedLprev_p1_1 -> UpdatedLprev_p1_2 { guard Lprev_p1_2 == (Ip1_2); },
+    UpdatedLprev_p1_1 -> UpdatedLprev_p1_2 { guard Lprev_p1_2 == 1 && Lprev_p1_2 != (Ip1_2) && x_50 >= 1000; },
+    UpdatedLprev_p1_1 -> UpdatedLprev_p1_2 { guard Lprev_p1_2 == 0 && Lprev_p1_2 != (Ip1_2) && x_50 >= 500; },
+    UpdatedLprev_p1_1 -> UpdatedLprev_p1_2_becomes0 { guard Lprev_p1_2 == 1 && Lprev_p1_2 != (Ip1_2) && x_50 < 1000; },
+    UpdatedLprev_p1_2_becomes0 -> UpdatedLprev_p1_2 { guard x_50 >= 1000; assign x_50:=0, Lprev_p1_2 := (Ip1_2); },
+    UpdatedLprev_p1_1 -> UpdatedLprev_p1_2_becomes1 { guard Lprev_p1_2 == 0 && Lprev_p1_2 != (Ip1_2) && x_50 < 500; },
+    UpdatedLprev_p1_2_becomes1 -> UpdatedLprev_p1_2 { guard x_50 >= 500; assign x_50:=0, Lprev_p1_2 := (Ip1_2); },
+    UpdatedLprev_p1_2 -> Init { guard T <= 5000; assign T:=0; },
+    UpdatedLprev_p1_2 -> dead { guard T >5000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_4L_300.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_4L_300.xta
new file mode 100644
index 0000000000..755cd09ba3
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_4L_300.xta
@@ -0,0 +1,159 @@
+ clock x_28;
+clock x_30;
+clock x_32;
+clock x_34;
+clock T;
+bool Ii_RtoB_ACK1;
+bool Ii_RtoB_ACK0;
+bool Ii_FULL;
+bool Ii_nEMPTY;
+bool Ii_StoB_REQ0;
+bool Ii_StoB_REQ1;
+bool Icontrollable_BtoR_REQ0;
+bool Icontrollable_BtoR_REQ1;
+bool Icontrollable_BtoS_ACK0;
+bool Icontrollable_BtoS_ACK1;
+bool Icontrollable_SLC0;
+bool Icontrollable_ENQ;
+bool Icontrollable_DEQ;
+bool Ln29;
+bool Lreg_stateG7_0_out;
+bool Lreg_controllable_BtoR_REQ1_out;
+bool Lreg_i_RtoB_ACK1_out;
+bool Lsys_fair0done_out;
+bool Lreg_controllable_BtoS_ACK0_out;
+bool Lenv_fair1done_out;
+bool Lreg_i_nEMPTY_out;
+bool Lreg_nstateG7_1_out;
+bool Lreg_controllable_BtoS_ACK1_out;
+bool Lreg_controllable_SLC0_out;
+bool Lsys_fair1done_out;
+bool Lenv_fair0done_out;
+bool Lreg_controllable_ENQ_out;
+bool Lreg_i_FULL_out;
+bool Lreg_stateG12_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lreg_controllable_DEQ_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_StoB_REQ1_out;
+bool Lreg_i_RtoB_ACK0_out;
+bool Lsys_fair2done_out;
+bool Lreg_controllable_BtoR_REQ0_out;
+bool Lreg_i_StoB_REQ0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_RtoB_ACK1,
+    JustSetIi_RtoB_ACK0,
+    JustSetIi_FULL,
+    JustSetIi_nEMPTY,
+    JustSetIi_StoB_REQ0,
+    JustSetIi_StoB_REQ1,
+    JustSetIcontrollable_BtoR_REQ0,
+    JustSetIcontrollable_BtoR_REQ1,
+    JustSetIcontrollable_BtoS_ACK0,
+    JustSetIcontrollable_BtoS_ACK1,
+    JustSetIcontrollable_SLC0,
+    JustSetIcontrollable_ENQ,
+    JustSetIcontrollable_DEQ,
+    UpdatedLn29,
+    UpdatedLn29_becomes0 { x_28 <= 1000 },
+    UpdatedLn29_becomes1 { x_28 <= 1500 },
+    UpdatedLreg_stateG7_0_out,
+    UpdatedLreg_stateG7_0_out_becomes0 { x_30 <= 500 },
+    UpdatedLreg_stateG7_0_out_becomes1 { x_30 <= 2000 },
+    UpdatedLreg_controllable_BtoR_REQ1_out,
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 { x_32 <= 2000 },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 { x_32 <= 3000 },
+    UpdatedLreg_i_RtoB_ACK1_out,
+    UpdatedLreg_i_RtoB_ACK1_out_becomes0 { x_34 <= 3000 },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes1 { x_34 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIi_RtoB_ACK1,
+    JustSetIi_RtoB_ACK0,
+    JustSetIi_FULL,
+    JustSetIi_nEMPTY,
+    JustSetIi_StoB_REQ0,
+    JustSetIi_StoB_REQ1,
+    JustSetIcontrollable_BtoR_REQ0,
+    JustSetIcontrollable_BtoR_REQ1,
+    JustSetIcontrollable_BtoS_ACK0,
+    JustSetIcontrollable_BtoS_ACK1,
+    JustSetIcontrollable_SLC0,
+    JustSetIcontrollable_ENQ,
+    JustSetIcontrollable_DEQ,
+    UpdatedLn29,
+    UpdatedLreg_stateG7_0_out,
+    UpdatedLreg_controllable_BtoR_REQ1_out,
+    UpdatedLreg_i_RtoB_ACK1_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_RtoB_ACK1 { assign Ii_RtoB_ACK1 := 0; },
+    Init -> JustSetIi_RtoB_ACK1 { assign Ii_RtoB_ACK1 := 1; },
+    JustSetIi_RtoB_ACK1 -> JustSetIi_RtoB_ACK0 { assign Ii_RtoB_ACK0 := 0; },
+    JustSetIi_RtoB_ACK1 -> JustSetIi_RtoB_ACK0 { assign Ii_RtoB_ACK0 := 1; },
+    JustSetIi_RtoB_ACK0 -> JustSetIi_FULL { assign Ii_FULL := 0; },
+    JustSetIi_RtoB_ACK0 -> JustSetIi_FULL { assign Ii_FULL := 1; },
+    JustSetIi_FULL -> JustSetIi_nEMPTY { assign Ii_nEMPTY := 0; },
+    JustSetIi_FULL -> JustSetIi_nEMPTY { assign Ii_nEMPTY := 1; },
+    JustSetIi_nEMPTY -> JustSetIi_StoB_REQ0 { assign Ii_StoB_REQ0 := 0; },
+    JustSetIi_nEMPTY -> JustSetIi_StoB_REQ0 { assign Ii_StoB_REQ0 := 1; },
+    JustSetIi_StoB_REQ0 -> JustSetIi_StoB_REQ1 { assign Ii_StoB_REQ1 := 0; },
+    JustSetIi_StoB_REQ0 -> JustSetIi_StoB_REQ1 { assign Ii_StoB_REQ1 := 1; },
+    JustSetIi_StoB_REQ1 -> JustSetIcontrollable_BtoR_REQ0 { assign Icontrollable_BtoR_REQ0 := 0; },
+    JustSetIi_StoB_REQ1 -> JustSetIcontrollable_BtoR_REQ0 { assign Icontrollable_BtoR_REQ0 := 1; },
+    JustSetIcontrollable_BtoR_REQ0 -> JustSetIcontrollable_BtoR_REQ1 { assign Icontrollable_BtoR_REQ1 := 0; },
+    JustSetIcontrollable_BtoR_REQ0 -> JustSetIcontrollable_BtoR_REQ1 { assign Icontrollable_BtoR_REQ1 := 1; },
+    JustSetIcontrollable_BtoR_REQ1 -> JustSetIcontrollable_BtoS_ACK0 { assign Icontrollable_BtoS_ACK0 := 0; },
+    JustSetIcontrollable_BtoR_REQ1 -> JustSetIcontrollable_BtoS_ACK0 { assign Icontrollable_BtoS_ACK0 := 1; },
+    JustSetIcontrollable_BtoS_ACK0 -> JustSetIcontrollable_BtoS_ACK1 { assign Icontrollable_BtoS_ACK1 := 0; },
+    JustSetIcontrollable_BtoS_ACK0 -> JustSetIcontrollable_BtoS_ACK1 { assign Icontrollable_BtoS_ACK1 := 1; },
+    JustSetIcontrollable_BtoS_ACK1 -> JustSetIcontrollable_SLC0 { assign Icontrollable_SLC0 := 0; },
+    JustSetIcontrollable_BtoS_ACK1 -> JustSetIcontrollable_SLC0 { assign Icontrollable_SLC0 := 1; },
+    JustSetIcontrollable_SLC0 -> JustSetIcontrollable_ENQ { assign Icontrollable_ENQ := 0; },
+    JustSetIcontrollable_SLC0 -> JustSetIcontrollable_ENQ { assign Icontrollable_ENQ := 1; },
+    JustSetIcontrollable_ENQ -> JustSetIcontrollable_DEQ { assign Icontrollable_DEQ := 0; },
+    JustSetIcontrollable_ENQ -> JustSetIcontrollable_DEQ { assign Icontrollable_DEQ := 1; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29 { guard Ln29 == 1; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29 { guard Ln29 == 1 && Ln29 != 1 && x_28 >= 1000; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29 { guard Ln29 == 0 && Ln29 != 1 && x_28 >= 1500; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29_becomes0 { guard Ln29 == 1 && Ln29 != 1 && x_28 < 1000; },
+    UpdatedLn29_becomes0 -> UpdatedLn29 { guard x_28 >= 1000; assign x_28:=0, Ln29 := 1; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29_becomes1 { guard Ln29 == 0 && Ln29 != 1 && x_28 < 1500; },
+    UpdatedLn29_becomes1 -> UpdatedLn29 { guard x_28 >= 1500; assign x_28:=0, Ln29 := 1; },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))); },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == 1 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 >= 500; },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == 0 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 >= 2000; },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out_becomes0 { guard Lreg_stateG7_0_out == 1 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 < 500; },
+    UpdatedLreg_stateG7_0_out_becomes0 -> UpdatedLreg_stateG7_0_out { guard x_30 >= 500; assign x_30:=0, Lreg_stateG7_0_out := (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))); },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out_becomes1 { guard Lreg_stateG7_0_out == 0 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 < 2000; },
+    UpdatedLreg_stateG7_0_out_becomes1 -> UpdatedLreg_stateG7_0_out { guard x_30 >= 2000; assign x_30:=0, Lreg_stateG7_0_out := (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == 1 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 >= 2000; },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == 0 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 >= 3000; },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 { guard Lreg_controllable_BtoR_REQ1_out == 1 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 < 2000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 -> UpdatedLreg_controllable_BtoR_REQ1_out { guard x_32 >= 2000; assign x_32:=0, Lreg_controllable_BtoR_REQ1_out := (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 { guard Lreg_controllable_BtoR_REQ1_out == 0 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 < 3000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 -> UpdatedLreg_controllable_BtoR_REQ1_out { guard x_32 >= 3000; assign x_32:=0, Lreg_controllable_BtoR_REQ1_out := (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == (Ii_RtoB_ACK1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == 1 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 >= 3000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == 0 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 >= 0; },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out_becomes0 { guard Lreg_i_RtoB_ACK1_out == 1 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 < 3000; },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes0 -> UpdatedLreg_i_RtoB_ACK1_out { guard x_34 >= 3000; assign x_34:=0, Lreg_i_RtoB_ACK1_out := (Ii_RtoB_ACK1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out_becomes1 { guard Lreg_i_RtoB_ACK1_out == 0 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 < 0; },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes1 -> UpdatedLreg_i_RtoB_ACK1_out { guard x_34 >= 0; assign x_34:=0, Lreg_i_RtoB_ACK1_out := (Ii_RtoB_ACK1); },
+    UpdatedLreg_i_RtoB_ACK1_out -> Init { guard T <= 3000; assign T:=0; },
+    UpdatedLreg_i_RtoB_ACK1_out -> dead { guard T >3000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_5L_300.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_5L_300.xta
new file mode 100644
index 0000000000..de25d5b00f
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf2b3unrealy.aag_5L_300.xta
@@ -0,0 +1,171 @@
+ clock x_28;
+clock x_30;
+clock x_32;
+clock x_34;
+clock x_36;
+clock T;
+bool Ii_RtoB_ACK1;
+bool Ii_RtoB_ACK0;
+bool Ii_FULL;
+bool Ii_nEMPTY;
+bool Ii_StoB_REQ0;
+bool Ii_StoB_REQ1;
+bool Icontrollable_BtoR_REQ0;
+bool Icontrollable_BtoR_REQ1;
+bool Icontrollable_BtoS_ACK0;
+bool Icontrollable_BtoS_ACK1;
+bool Icontrollable_SLC0;
+bool Icontrollable_ENQ;
+bool Icontrollable_DEQ;
+bool Ln29;
+bool Lreg_stateG7_0_out;
+bool Lreg_controllable_BtoR_REQ1_out;
+bool Lreg_i_RtoB_ACK1_out;
+bool Lsys_fair0done_out;
+bool Lreg_controllable_BtoS_ACK0_out;
+bool Lenv_fair1done_out;
+bool Lreg_i_nEMPTY_out;
+bool Lreg_nstateG7_1_out;
+bool Lreg_controllable_BtoS_ACK1_out;
+bool Lreg_controllable_SLC0_out;
+bool Lsys_fair1done_out;
+bool Lenv_fair0done_out;
+bool Lreg_controllable_ENQ_out;
+bool Lreg_i_FULL_out;
+bool Lreg_stateG12_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lreg_controllable_DEQ_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_StoB_REQ1_out;
+bool Lreg_i_RtoB_ACK0_out;
+bool Lsys_fair2done_out;
+bool Lreg_controllable_BtoR_REQ0_out;
+bool Lreg_i_StoB_REQ0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_RtoB_ACK1,
+    JustSetIi_RtoB_ACK0,
+    JustSetIi_FULL,
+    JustSetIi_nEMPTY,
+    JustSetIi_StoB_REQ0,
+    JustSetIi_StoB_REQ1,
+    JustSetIcontrollable_BtoR_REQ0,
+    JustSetIcontrollable_BtoR_REQ1,
+    JustSetIcontrollable_BtoS_ACK0,
+    JustSetIcontrollable_BtoS_ACK1,
+    JustSetIcontrollable_SLC0,
+    JustSetIcontrollable_ENQ,
+    JustSetIcontrollable_DEQ,
+    UpdatedLn29,
+    UpdatedLn29_becomes0 { x_28 <= 1000 },
+    UpdatedLn29_becomes1 { x_28 <= 1500 },
+    UpdatedLreg_stateG7_0_out,
+    UpdatedLreg_stateG7_0_out_becomes0 { x_30 <= 500 },
+    UpdatedLreg_stateG7_0_out_becomes1 { x_30 <= 2000 },
+    UpdatedLreg_controllable_BtoR_REQ1_out,
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 { x_32 <= 2000 },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 { x_32 <= 3000 },
+    UpdatedLreg_i_RtoB_ACK1_out,
+    UpdatedLreg_i_RtoB_ACK1_out_becomes0 { x_34 <= 3000 },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes1 { x_34 <= 0 },
+    UpdatedLsys_fair0done_out,
+    UpdatedLsys_fair0done_out_becomes0 { x_36 <= 2500 },
+    UpdatedLsys_fair0done_out_becomes1 { x_36 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIi_RtoB_ACK1,
+    JustSetIi_RtoB_ACK0,
+    JustSetIi_FULL,
+    JustSetIi_nEMPTY,
+    JustSetIi_StoB_REQ0,
+    JustSetIi_StoB_REQ1,
+    JustSetIcontrollable_BtoR_REQ0,
+    JustSetIcontrollable_BtoR_REQ1,
+    JustSetIcontrollable_BtoS_ACK0,
+    JustSetIcontrollable_BtoS_ACK1,
+    JustSetIcontrollable_SLC0,
+    JustSetIcontrollable_ENQ,
+    JustSetIcontrollable_DEQ,
+    UpdatedLn29,
+    UpdatedLreg_stateG7_0_out,
+    UpdatedLreg_controllable_BtoR_REQ1_out,
+    UpdatedLreg_i_RtoB_ACK1_out,
+    UpdatedLsys_fair0done_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_RtoB_ACK1 { assign Ii_RtoB_ACK1 := 0; },
+    Init -> JustSetIi_RtoB_ACK1 { assign Ii_RtoB_ACK1 := 1; },
+    JustSetIi_RtoB_ACK1 -> JustSetIi_RtoB_ACK0 { assign Ii_RtoB_ACK0 := 0; },
+    JustSetIi_RtoB_ACK1 -> JustSetIi_RtoB_ACK0 { assign Ii_RtoB_ACK0 := 1; },
+    JustSetIi_RtoB_ACK0 -> JustSetIi_FULL { assign Ii_FULL := 0; },
+    JustSetIi_RtoB_ACK0 -> JustSetIi_FULL { assign Ii_FULL := 1; },
+    JustSetIi_FULL -> JustSetIi_nEMPTY { assign Ii_nEMPTY := 0; },
+    JustSetIi_FULL -> JustSetIi_nEMPTY { assign Ii_nEMPTY := 1; },
+    JustSetIi_nEMPTY -> JustSetIi_StoB_REQ0 { assign Ii_StoB_REQ0 := 0; },
+    JustSetIi_nEMPTY -> JustSetIi_StoB_REQ0 { assign Ii_StoB_REQ0 := 1; },
+    JustSetIi_StoB_REQ0 -> JustSetIi_StoB_REQ1 { assign Ii_StoB_REQ1 := 0; },
+    JustSetIi_StoB_REQ0 -> JustSetIi_StoB_REQ1 { assign Ii_StoB_REQ1 := 1; },
+    JustSetIi_StoB_REQ1 -> JustSetIcontrollable_BtoR_REQ0 { assign Icontrollable_BtoR_REQ0 := 0; },
+    JustSetIi_StoB_REQ1 -> JustSetIcontrollable_BtoR_REQ0 { assign Icontrollable_BtoR_REQ0 := 1; },
+    JustSetIcontrollable_BtoR_REQ0 -> JustSetIcontrollable_BtoR_REQ1 { assign Icontrollable_BtoR_REQ1 := 0; },
+    JustSetIcontrollable_BtoR_REQ0 -> JustSetIcontrollable_BtoR_REQ1 { assign Icontrollable_BtoR_REQ1 := 1; },
+    JustSetIcontrollable_BtoR_REQ1 -> JustSetIcontrollable_BtoS_ACK0 { assign Icontrollable_BtoS_ACK0 := 0; },
+    JustSetIcontrollable_BtoR_REQ1 -> JustSetIcontrollable_BtoS_ACK0 { assign Icontrollable_BtoS_ACK0 := 1; },
+    JustSetIcontrollable_BtoS_ACK0 -> JustSetIcontrollable_BtoS_ACK1 { assign Icontrollable_BtoS_ACK1 := 0; },
+    JustSetIcontrollable_BtoS_ACK0 -> JustSetIcontrollable_BtoS_ACK1 { assign Icontrollable_BtoS_ACK1 := 1; },
+    JustSetIcontrollable_BtoS_ACK1 -> JustSetIcontrollable_SLC0 { assign Icontrollable_SLC0 := 0; },
+    JustSetIcontrollable_BtoS_ACK1 -> JustSetIcontrollable_SLC0 { assign Icontrollable_SLC0 := 1; },
+    JustSetIcontrollable_SLC0 -> JustSetIcontrollable_ENQ { assign Icontrollable_ENQ := 0; },
+    JustSetIcontrollable_SLC0 -> JustSetIcontrollable_ENQ { assign Icontrollable_ENQ := 1; },
+    JustSetIcontrollable_ENQ -> JustSetIcontrollable_DEQ { assign Icontrollable_DEQ := 0; },
+    JustSetIcontrollable_ENQ -> JustSetIcontrollable_DEQ { assign Icontrollable_DEQ := 1; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29 { guard Ln29 == 1; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29 { guard Ln29 == 1 && Ln29 != 1 && x_28 >= 1000; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29 { guard Ln29 == 0 && Ln29 != 1 && x_28 >= 1500; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29_becomes0 { guard Ln29 == 1 && Ln29 != 1 && x_28 < 1000; },
+    UpdatedLn29_becomes0 -> UpdatedLn29 { guard x_28 >= 1000; assign x_28:=0, Ln29 := 1; },
+    JustSetIcontrollable_DEQ -> UpdatedLn29_becomes1 { guard Ln29 == 0 && Ln29 != 1 && x_28 < 1500; },
+    UpdatedLn29_becomes1 -> UpdatedLn29 { guard x_28 >= 1500; assign x_28:=0, Ln29 := 1; },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))); },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == 1 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 >= 500; },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == 0 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 >= 2000; },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out_becomes0 { guard Lreg_stateG7_0_out == 1 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 < 500; },
+    UpdatedLreg_stateG7_0_out_becomes0 -> UpdatedLreg_stateG7_0_out { guard x_30 >= 500; assign x_30:=0, Lreg_stateG7_0_out := (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))); },
+    UpdatedLn29 -> UpdatedLreg_stateG7_0_out_becomes1 { guard Lreg_stateG7_0_out == 0 && Lreg_stateG7_0_out != (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))) && x_30 < 2000; },
+    UpdatedLreg_stateG7_0_out_becomes1 -> UpdatedLreg_stateG7_0_out { guard x_30 >= 2000; assign x_30:=0, Lreg_stateG7_0_out := (!(!(!((Lreg_controllable_BtoR_REQ1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_stateG7_0_out) && (Ln29))) && (!((!((Lreg_nstateG7_1_out) && (Ln29)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && !((Lreg_controllable_BtoR_REQ1_out) && (Ln29))) && !((((Lreg_nstateG7_1_out) && (Ln29)) && !((Lreg_controllable_BtoR_REQ0_out) && (Ln29))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln29))))); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == 1 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 >= 2000; },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == 0 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 >= 3000; },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 { guard Lreg_controllable_BtoR_REQ1_out == 1 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 < 2000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 -> UpdatedLreg_controllable_BtoR_REQ1_out { guard x_32 >= 2000; assign x_32:=0, Lreg_controllable_BtoR_REQ1_out := (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 { guard Lreg_controllable_BtoR_REQ1_out == 0 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_32 < 3000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 -> UpdatedLreg_controllable_BtoR_REQ1_out { guard x_32 >= 3000; assign x_32:=0, Lreg_controllable_BtoR_REQ1_out := (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == (Ii_RtoB_ACK1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == 1 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 >= 3000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == 0 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 >= 0; },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out_becomes0 { guard Lreg_i_RtoB_ACK1_out == 1 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 < 3000; },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes0 -> UpdatedLreg_i_RtoB_ACK1_out { guard x_34 >= 3000; assign x_34:=0, Lreg_i_RtoB_ACK1_out := (Ii_RtoB_ACK1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out_becomes1 { guard Lreg_i_RtoB_ACK1_out == 0 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_34 < 0; },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes1 -> UpdatedLreg_i_RtoB_ACK1_out { guard x_34 >= 0; assign x_34:=0, Lreg_i_RtoB_ACK1_out := (Ii_RtoB_ACK1); },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))); },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))) && x_36 >= 2500; },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLsys_fair0done_out { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))) && x_36 >= 0; },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLsys_fair0done_out_becomes0 { guard Lsys_fair0done_out == 1 && Lsys_fair0done_out != (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))) && x_36 < 2500; },
+    UpdatedLsys_fair0done_out_becomes0 -> UpdatedLsys_fair0done_out { guard x_36 >= 2500; assign x_36:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))); },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLsys_fair0done_out_becomes1 { guard Lsys_fair0done_out == 0 && Lsys_fair0done_out != (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))) && x_36 < 0; },
+    UpdatedLsys_fair0done_out_becomes1 -> UpdatedLsys_fair0done_out { guard x_36 >= 0; assign x_36:=0, Lsys_fair0done_out := (!(!(!((Lsys_fair2done_out) && (Ln29)) && ((Lreg_stateG12_out) && (Ln29))) && (!(!((Lsys_fair1done_out) && (Ln29)) && !(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1)))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29))))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !((Lsys_fair0done_out) && (Ln29)))); },
+    UpdatedLsys_fair0done_out -> Init { guard T <= 3000; assign T:=0; },
+    UpdatedLsys_fair0done_out -> dead { guard T >3000; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf5f5n.aag_6L_290.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf5f5n.aag_6L_290.xta
new file mode 100644
index 0000000000..a4ffff10a8
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/genbuf5f5n.aag_6L_290.xta
@@ -0,0 +1,235 @@
+ clock x_44;
+clock x_46;
+clock x_48;
+clock x_50;
+clock x_52;
+clock x_54;
+clock T;
+bool Ii_nEMPTY;
+bool Ii_StoB_REQ0;
+bool Ii_StoB_REQ1;
+bool Ii_StoB_REQ2;
+bool Ii_StoB_REQ3;
+bool Ii_StoB_REQ4;
+bool Ii_FULL;
+bool Ii_RtoB_ACK1;
+bool Ii_RtoB_ACK0;
+bool Icontrollable_DEQ;
+bool Icontrollable_ENQ;
+bool Icontrollable_BtoS_ACK0;
+bool Icontrollable_BtoS_ACK1;
+bool Icontrollable_BtoS_ACK2;
+bool Icontrollable_BtoS_ACK3;
+bool Icontrollable_BtoS_ACK4;
+bool Icontrollable_BtoR_REQ0;
+bool Icontrollable_BtoR_REQ1;
+bool Icontrollable_SLC0;
+bool Icontrollable_SLC1;
+bool Icontrollable_SLC2;
+bool Ln45;
+bool Lsys_fair5done_out;
+bool Lreg_stateG7_0_out;
+bool Lreg_controllable_BtoR_REQ1_out;
+bool Lreg_i_RtoB_ACK1_out;
+bool Lenv_fair1done_out;
+bool Lreg_controllable_BtoS_ACK0_out;
+bool Lsys_fair0done_out;
+bool Lreg_i_nEMPTY_out;
+bool Lsys_fair3done_out;
+bool Lreg_controllable_BtoS_ACK1_out;
+bool Lreg_nstateG7_1_out;
+bool Lreg_controllable_BtoS_ACK2_out;
+bool Lreg_controllable_SLC0_out;
+bool Lreg_controllable_BtoS_ACK3_out;
+bool Lsys_fair1done_out;
+bool Lreg_controllable_SLC1_out;
+bool Lreg_controllable_ENQ_out;
+bool Lreg_controllable_BtoS_ACK4_out;
+bool Lenv_fair0done_out;
+bool Lreg_i_StoB_REQ4_out;
+bool Lreg_i_FULL_out;
+bool Lreg_controllable_SLC2_out;
+bool Lreg_i_StoB_REQ3_out;
+bool Lreg_stateG12_out;
+bool Lsys_fair4done_out;
+bool Lfair_cnt0_out;
+bool Lfair_cnt1_out;
+bool Lfair_cnt2_out;
+bool Lreg_controllable_DEQ_out;
+bool Lreg_i_StoB_REQ2_out;
+bool Lenv_safe_err_happened_out;
+bool Lreg_i_StoB_REQ1_out;
+bool Lsys_fair2done_out;
+bool Lreg_controllable_BtoR_REQ0_out;
+bool Lreg_i_StoB_REQ0_out;
+bool Lreg_i_RtoB_ACK0_out;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIi_nEMPTY,
+    JustSetIi_StoB_REQ0,
+    JustSetIi_StoB_REQ1,
+    JustSetIi_StoB_REQ2,
+    JustSetIi_StoB_REQ3,
+    JustSetIi_StoB_REQ4,
+    JustSetIi_FULL,
+    JustSetIi_RtoB_ACK1,
+    JustSetIi_RtoB_ACK0,
+    JustSetIcontrollable_DEQ,
+    JustSetIcontrollable_ENQ,
+    JustSetIcontrollable_BtoS_ACK0,
+    JustSetIcontrollable_BtoS_ACK1,
+    JustSetIcontrollable_BtoS_ACK2,
+    JustSetIcontrollable_BtoS_ACK3,
+    JustSetIcontrollable_BtoS_ACK4,
+    JustSetIcontrollable_BtoR_REQ0,
+    JustSetIcontrollable_BtoR_REQ1,
+    JustSetIcontrollable_SLC0,
+    JustSetIcontrollable_SLC1,
+    JustSetIcontrollable_SLC2,
+    UpdatedLn45,
+    UpdatedLn45_becomes0 { x_44 <= 1000 },
+    UpdatedLn45_becomes1 { x_44 <= 1500 },
+    UpdatedLsys_fair5done_out,
+    UpdatedLsys_fair5done_out_becomes0 { x_46 <= 500 },
+    UpdatedLsys_fair5done_out_becomes1 { x_46 <= 2000 },
+    UpdatedLreg_stateG7_0_out,
+    UpdatedLreg_stateG7_0_out_becomes0 { x_48 <= 2000 },
+    UpdatedLreg_stateG7_0_out_becomes1 { x_48 <= 3000 },
+    UpdatedLreg_controllable_BtoR_REQ1_out,
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 { x_50 <= 3000 },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 { x_50 <= 0 },
+    UpdatedLreg_i_RtoB_ACK1_out,
+    UpdatedLreg_i_RtoB_ACK1_out_becomes0 { x_52 <= 2500 },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes1 { x_52 <= 0 },
+    UpdatedLenv_fair1done_out,
+    UpdatedLenv_fair1done_out_becomes0 { x_54 <= 4000 },
+    UpdatedLenv_fair1done_out_becomes1 { x_54 <= 2000 },
+    dead;
+urgent
+    Init,
+    JustSetIi_nEMPTY,
+    JustSetIi_StoB_REQ0,
+    JustSetIi_StoB_REQ1,
+    JustSetIi_StoB_REQ2,
+    JustSetIi_StoB_REQ3,
+    JustSetIi_StoB_REQ4,
+    JustSetIi_FULL,
+    JustSetIi_RtoB_ACK1,
+    JustSetIi_RtoB_ACK0,
+    JustSetIcontrollable_DEQ,
+    JustSetIcontrollable_ENQ,
+    JustSetIcontrollable_BtoS_ACK0,
+    JustSetIcontrollable_BtoS_ACK1,
+    JustSetIcontrollable_BtoS_ACK2,
+    JustSetIcontrollable_BtoS_ACK3,
+    JustSetIcontrollable_BtoS_ACK4,
+    JustSetIcontrollable_BtoR_REQ0,
+    JustSetIcontrollable_BtoR_REQ1,
+    JustSetIcontrollable_SLC0,
+    JustSetIcontrollable_SLC1,
+    JustSetIcontrollable_SLC2,
+    UpdatedLn45,
+    UpdatedLsys_fair5done_out,
+    UpdatedLreg_stateG7_0_out,
+    UpdatedLreg_controllable_BtoR_REQ1_out,
+    UpdatedLreg_i_RtoB_ACK1_out,
+    UpdatedLenv_fair1done_out;
+init
+    Init;
+trans
+    Init -> JustSetIi_nEMPTY { assign Ii_nEMPTY := 0; },
+    Init -> JustSetIi_nEMPTY { assign Ii_nEMPTY := 1; },
+    JustSetIi_nEMPTY -> JustSetIi_StoB_REQ0 { assign Ii_StoB_REQ0 := 0; },
+    JustSetIi_nEMPTY -> JustSetIi_StoB_REQ0 { assign Ii_StoB_REQ0 := 1; },
+    JustSetIi_StoB_REQ0 -> JustSetIi_StoB_REQ1 { assign Ii_StoB_REQ1 := 0; },
+    JustSetIi_StoB_REQ0 -> JustSetIi_StoB_REQ1 { assign Ii_StoB_REQ1 := 1; },
+    JustSetIi_StoB_REQ1 -> JustSetIi_StoB_REQ2 { assign Ii_StoB_REQ2 := 0; },
+    JustSetIi_StoB_REQ1 -> JustSetIi_StoB_REQ2 { assign Ii_StoB_REQ2 := 1; },
+    JustSetIi_StoB_REQ2 -> JustSetIi_StoB_REQ3 { assign Ii_StoB_REQ3 := 0; },
+    JustSetIi_StoB_REQ2 -> JustSetIi_StoB_REQ3 { assign Ii_StoB_REQ3 := 1; },
+    JustSetIi_StoB_REQ3 -> JustSetIi_StoB_REQ4 { assign Ii_StoB_REQ4 := 0; },
+    JustSetIi_StoB_REQ3 -> JustSetIi_StoB_REQ4 { assign Ii_StoB_REQ4 := 1; },
+    JustSetIi_StoB_REQ4 -> JustSetIi_FULL { assign Ii_FULL := 0; },
+    JustSetIi_StoB_REQ4 -> JustSetIi_FULL { assign Ii_FULL := 1; },
+    JustSetIi_FULL -> JustSetIi_RtoB_ACK1 { assign Ii_RtoB_ACK1 := 0; },
+    JustSetIi_FULL -> JustSetIi_RtoB_ACK1 { assign Ii_RtoB_ACK1 := 1; },
+    JustSetIi_RtoB_ACK1 -> JustSetIi_RtoB_ACK0 { assign Ii_RtoB_ACK0 := 0; },
+    JustSetIi_RtoB_ACK1 -> JustSetIi_RtoB_ACK0 { assign Ii_RtoB_ACK0 := 1; },
+    JustSetIi_RtoB_ACK0 -> JustSetIcontrollable_DEQ { assign Icontrollable_DEQ := 0; },
+    JustSetIi_RtoB_ACK0 -> JustSetIcontrollable_DEQ { assign Icontrollable_DEQ := 1; },
+    JustSetIcontrollable_DEQ -> JustSetIcontrollable_ENQ { assign Icontrollable_ENQ := 0; },
+    JustSetIcontrollable_DEQ -> JustSetIcontrollable_ENQ { assign Icontrollable_ENQ := 1; },
+    JustSetIcontrollable_ENQ -> JustSetIcontrollable_BtoS_ACK0 { assign Icontrollable_BtoS_ACK0 := 0; },
+    JustSetIcontrollable_ENQ -> JustSetIcontrollable_BtoS_ACK0 { assign Icontrollable_BtoS_ACK0 := 1; },
+    JustSetIcontrollable_BtoS_ACK0 -> JustSetIcontrollable_BtoS_ACK1 { assign Icontrollable_BtoS_ACK1 := 0; },
+    JustSetIcontrollable_BtoS_ACK0 -> JustSetIcontrollable_BtoS_ACK1 { assign Icontrollable_BtoS_ACK1 := 1; },
+    JustSetIcontrollable_BtoS_ACK1 -> JustSetIcontrollable_BtoS_ACK2 { assign Icontrollable_BtoS_ACK2 := 0; },
+    JustSetIcontrollable_BtoS_ACK1 -> JustSetIcontrollable_BtoS_ACK2 { assign Icontrollable_BtoS_ACK2 := 1; },
+    JustSetIcontrollable_BtoS_ACK2 -> JustSetIcontrollable_BtoS_ACK3 { assign Icontrollable_BtoS_ACK3 := 0; },
+    JustSetIcontrollable_BtoS_ACK2 -> JustSetIcontrollable_BtoS_ACK3 { assign Icontrollable_BtoS_ACK3 := 1; },
+    JustSetIcontrollable_BtoS_ACK3 -> JustSetIcontrollable_BtoS_ACK4 { assign Icontrollable_BtoS_ACK4 := 0; },
+    JustSetIcontrollable_BtoS_ACK3 -> JustSetIcontrollable_BtoS_ACK4 { assign Icontrollable_BtoS_ACK4 := 1; },
+    JustSetIcontrollable_BtoS_ACK4 -> JustSetIcontrollable_BtoR_REQ0 { assign Icontrollable_BtoR_REQ0 := 0; },
+    JustSetIcontrollable_BtoS_ACK4 -> JustSetIcontrollable_BtoR_REQ0 { assign Icontrollable_BtoR_REQ0 := 1; },
+    JustSetIcontrollable_BtoR_REQ0 -> JustSetIcontrollable_BtoR_REQ1 { assign Icontrollable_BtoR_REQ1 := 0; },
+    JustSetIcontrollable_BtoR_REQ0 -> JustSetIcontrollable_BtoR_REQ1 { assign Icontrollable_BtoR_REQ1 := 1; },
+    JustSetIcontrollable_BtoR_REQ1 -> JustSetIcontrollable_SLC0 { assign Icontrollable_SLC0 := 0; },
+    JustSetIcontrollable_BtoR_REQ1 -> JustSetIcontrollable_SLC0 { assign Icontrollable_SLC0 := 1; },
+    JustSetIcontrollable_SLC0 -> JustSetIcontrollable_SLC1 { assign Icontrollable_SLC1 := 0; },
+    JustSetIcontrollable_SLC0 -> JustSetIcontrollable_SLC1 { assign Icontrollable_SLC1 := 1; },
+    JustSetIcontrollable_SLC1 -> JustSetIcontrollable_SLC2 { assign Icontrollable_SLC2 := 0; },
+    JustSetIcontrollable_SLC1 -> JustSetIcontrollable_SLC2 { assign Icontrollable_SLC2 := 1; },
+    JustSetIcontrollable_SLC2 -> UpdatedLn45 { guard Ln45 == 1; },
+    JustSetIcontrollable_SLC2 -> UpdatedLn45 { guard Ln45 == 1 && Ln45 != 1 && x_44 >= 1000; },
+    JustSetIcontrollable_SLC2 -> UpdatedLn45 { guard Ln45 == 0 && Ln45 != 1 && x_44 >= 1500; },
+    JustSetIcontrollable_SLC2 -> UpdatedLn45_becomes0 { guard Ln45 == 1 && Ln45 != 1 && x_44 < 1000; },
+    UpdatedLn45_becomes0 -> UpdatedLn45 { guard x_44 >= 1000; assign x_44:=0, Ln45 := 1; },
+    JustSetIcontrollable_SLC2 -> UpdatedLn45_becomes1 { guard Ln45 == 0 && Ln45 != 1 && x_44 < 1500; },
+    UpdatedLn45_becomes1 -> UpdatedLn45 { guard x_44 >= 1500; assign x_44:=0, Ln45 := 1; },
+    UpdatedLn45 -> UpdatedLsys_fair5done_out { guard Lsys_fair5done_out == (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))); },
+    UpdatedLn45 -> UpdatedLsys_fair5done_out { guard Lsys_fair5done_out == 1 && Lsys_fair5done_out != (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))) && x_46 >= 500; },
+    UpdatedLn45 -> UpdatedLsys_fair5done_out { guard Lsys_fair5done_out == 0 && Lsys_fair5done_out != (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))) && x_46 >= 2000; },
+    UpdatedLn45 -> UpdatedLsys_fair5done_out_becomes0 { guard Lsys_fair5done_out == 1 && Lsys_fair5done_out != (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))) && x_46 < 500; },
+    UpdatedLsys_fair5done_out_becomes0 -> UpdatedLsys_fair5done_out { guard x_46 >= 500; assign x_46:=0, Lsys_fair5done_out := (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))); },
+    UpdatedLn45 -> UpdatedLsys_fair5done_out_becomes1 { guard Lsys_fair5done_out == 0 && Lsys_fair5done_out != (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))) && x_46 < 2000; },
+    UpdatedLsys_fair5done_out_becomes1 -> UpdatedLsys_fair5done_out { guard x_46 >= 2000; assign x_46:=0, Lsys_fair5done_out := (!(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))) && !(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45)))); },
+    UpdatedLsys_fair5done_out -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))); },
+    UpdatedLsys_fair5done_out -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == 1 && Lreg_stateG7_0_out != !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))) && x_48 >= 2000; },
+    UpdatedLsys_fair5done_out -> UpdatedLreg_stateG7_0_out { guard Lreg_stateG7_0_out == 0 && Lreg_stateG7_0_out != !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))) && x_48 >= 3000; },
+    UpdatedLsys_fair5done_out -> UpdatedLreg_stateG7_0_out_becomes0 { guard Lreg_stateG7_0_out == 1 && Lreg_stateG7_0_out != !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))) && x_48 < 2000; },
+    UpdatedLreg_stateG7_0_out_becomes0 -> UpdatedLreg_stateG7_0_out { guard x_48 >= 2000; assign x_48:=0, Lreg_stateG7_0_out := !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))); },
+    UpdatedLsys_fair5done_out -> UpdatedLreg_stateG7_0_out_becomes1 { guard Lreg_stateG7_0_out == 0 && Lreg_stateG7_0_out != !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))) && x_48 < 3000; },
+    UpdatedLreg_stateG7_0_out_becomes1 -> UpdatedLreg_stateG7_0_out { guard x_48 >= 3000; assign x_48:=0, Lreg_stateG7_0_out := !(!((!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))) && ((Lreg_stateG7_0_out) && (Ln45))) && !(((!(!(!(!(!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && ((Lreg_stateG7_0_out) && (Ln45))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !(!(((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && ((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!((!((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && ((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45)))) && (!(((!(!(!(Lreg_nstateG7_1_out) && (Ln45)) && (Ln45)) && ((Lreg_controllable_BtoR_REQ0_out) && (Ln45))) && !(!(!(Lreg_controllable_BtoR_REQ1_out) && (Ln45)) && (Ln45))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))) && !((((Lreg_nstateG7_1_out) && (Ln45)) && !(!(!(Lreg_controllable_BtoR_REQ0_out) && (Ln45)) && (Ln45))) && ((Lreg_controllable_BtoR_REQ1_out) && (Ln45)))))))); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == 1 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_50 >= 3000; },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out { guard Lreg_controllable_BtoR_REQ1_out == 0 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_50 >= 0; },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 { guard Lreg_controllable_BtoR_REQ1_out == 1 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_50 < 3000; },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes0 -> UpdatedLreg_controllable_BtoR_REQ1_out { guard x_50 >= 3000; assign x_50:=0, Lreg_controllable_BtoR_REQ1_out := (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_stateG7_0_out -> UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 { guard Lreg_controllable_BtoR_REQ1_out == 0 && Lreg_controllable_BtoR_REQ1_out != (Icontrollable_BtoR_REQ1) && x_50 < 0; },
+    UpdatedLreg_controllable_BtoR_REQ1_out_becomes1 -> UpdatedLreg_controllable_BtoR_REQ1_out { guard x_50 >= 0; assign x_50:=0, Lreg_controllable_BtoR_REQ1_out := (Icontrollable_BtoR_REQ1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == (Ii_RtoB_ACK1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == 1 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_52 >= 2500; },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out { guard Lreg_i_RtoB_ACK1_out == 0 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_52 >= 0; },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out_becomes0 { guard Lreg_i_RtoB_ACK1_out == 1 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_52 < 2500; },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes0 -> UpdatedLreg_i_RtoB_ACK1_out { guard x_52 >= 2500; assign x_52:=0, Lreg_i_RtoB_ACK1_out := (Ii_RtoB_ACK1); },
+    UpdatedLreg_controllable_BtoR_REQ1_out -> UpdatedLreg_i_RtoB_ACK1_out_becomes1 { guard Lreg_i_RtoB_ACK1_out == 0 && Lreg_i_RtoB_ACK1_out != (Ii_RtoB_ACK1) && x_52 < 0; },
+    UpdatedLreg_i_RtoB_ACK1_out_becomes1 -> UpdatedLreg_i_RtoB_ACK1_out { guard x_52 >= 0; assign x_52:=0, Lreg_i_RtoB_ACK1_out := (Ii_RtoB_ACK1); },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLenv_fair1done_out { guard Lenv_fair1done_out == !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))); },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLenv_fair1done_out { guard Lenv_fair1done_out == 1 && Lenv_fair1done_out != !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))) && x_54 >= 4000; },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLenv_fair1done_out { guard Lenv_fair1done_out == 0 && Lenv_fair1done_out != !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))) && x_54 >= 2000; },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLenv_fair1done_out_becomes0 { guard Lenv_fair1done_out == 1 && Lenv_fair1done_out != !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))) && x_54 < 4000; },
+    UpdatedLenv_fair1done_out_becomes0 -> UpdatedLenv_fair1done_out { guard x_54 >= 4000; assign x_54:=0, Lenv_fair1done_out := !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))); },
+    UpdatedLreg_i_RtoB_ACK1_out -> UpdatedLenv_fair1done_out_becomes1 { guard Lenv_fair1done_out == 0 && Lenv_fair1done_out != !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))) && x_54 < 2000; },
+    UpdatedLenv_fair1done_out_becomes1 -> UpdatedLenv_fair1done_out { guard x_54 >= 2000; assign x_54:=0, Lenv_fair1done_out := !(!((!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))) && ((Lenv_fair1done_out) && (Ln45))) && !(((!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(!(!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && (!((!(!(!(!(Ii_RtoB_ACK1) && (Icontrollable_BtoR_REQ1)) && !((Ii_RtoB_ACK1) && !(Icontrollable_BtoR_REQ1))) && !(!(!(Lenv_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!(!(Ii_RtoB_ACK0) && (Icontrollable_BtoR_REQ0)) && !((Ii_RtoB_ACK0) && !(Icontrollable_BtoR_REQ0))) && !(!(!(Lenv_fair0done_out) && (Ln45)) && (Ln45)))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45))))))))) && !(!(((Lreg_stateG12_out) && (Ln45)) && !(!(!(Lsys_fair5done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ4) && !(Icontrollable_BtoS_ACK4)) && !(!(Ii_StoB_REQ4) && (Icontrollable_BtoS_ACK4))) && !(!(!(Lsys_fair4done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ3) && !(Icontrollable_BtoS_ACK3)) && !(!(Ii_StoB_REQ3) && (Icontrollable_BtoS_ACK3))) && !(!(!(Lsys_fair3done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ2) && !(Icontrollable_BtoS_ACK2)) && !(!(Ii_StoB_REQ2) && (Icontrollable_BtoS_ACK2))) && !(!(!(Lsys_fair2done_out) && (Ln45)) && (Ln45))) && (!(!(!((Ii_StoB_REQ1) && !(Icontrollable_BtoS_ACK1)) && !(!(Ii_StoB_REQ1) && (Icontrollable_BtoS_ACK1))) && !(!(!(Lsys_fair1done_out) && (Ln45)) && (Ln45))) && !(!(!((Ii_StoB_REQ0) && !(Icontrollable_BtoS_ACK0)) && !(!(Ii_StoB_REQ0) && (Icontrollable_BtoS_ACK0))) && !(!(!(Lsys_fair0done_out) && (Ln45)) && (Ln45)))))))))))); },
+    UpdatedLenv_fair1done_out -> Init { guard T <= 2900; assign T:=0; },
+    UpdatedLenv_fair1done_out -> dead { guard T >2900; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/moving_obstacle_8x8_1glitches.aag_4L_150.xta b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/moving_obstacle_8x8_1glitches.aag_4L_150.xta
new file mode 100644
index 0000000000..fbdbb8317a
--- /dev/null
+++ b/subprojects/xta/xta-analysis/src/test/resources/model/dipterv/moving_obstacle_8x8_1glitches.aag_4L_150.xta
@@ -0,0 +1,179 @@
+ clock x_38;
+clock x_40;
+clock x_42;
+clock x_44;
+clock T;
+bool Iobsx_0_0_6;
+bool Iobsx_1;
+bool Iobsx_2;
+bool Iobsy_0_0_6;
+bool Iobsy_1;
+bool Iobsy_2;
+bool Irobx_0_0_7;
+bool Irobx_1;
+bool Irobx_2;
+bool Iroby_0_0_7;
+bool Iroby_1;
+bool Iroby_2;
+bool Iglitches_0_0_1;
+bool Icontrollable_movx_0_0_2;
+bool Icontrollable_movx_1;
+bool Icontrollable_movy_0_0_2;
+bool Icontrollable_movy_1;
+bool Icontrollable_obsmove;
+bool LIsNotFirstRound;
+bool Lprev_obsx_0_0_6;
+bool Lprev_obsx_1;
+bool Lprev_obsx_2;
+bool Lprev_obsy_0_0_6;
+bool Lprev_obsy_1;
+bool Lprev_obsy_2;
+bool Lprev_robx_0_0_7;
+bool Lprev_robx_1;
+bool Lprev_robx_2;
+bool Lprev_roby_0_0_7;
+bool Lprev_roby_1;
+bool Lprev_roby_2;
+bool Lprev_glitches_0_0_1;
+bool Lprev_movx_0_0_2;
+bool Lprev_movx_1;
+bool Lprev_movy_0_0_2;
+bool Lprev_movy_1;
+bool Lprev_obsmove;
+bool LAssumptionsAlreadyViolated;
+
+
+process Circuit() {
+
+state
+    Init,
+    JustSetIobsx_0_0_6,
+    JustSetIobsx_1,
+    JustSetIobsx_2,
+    JustSetIobsy_0_0_6,
+    JustSetIobsy_1,
+    JustSetIobsy_2,
+    JustSetIrobx_0_0_7,
+    JustSetIrobx_1,
+    JustSetIrobx_2,
+    JustSetIroby_0_0_7,
+    JustSetIroby_1,
+    JustSetIroby_2,
+    JustSetIglitches_0_0_1,
+    JustSetIcontrollable_movx_0_0_2,
+    JustSetIcontrollable_movx_1,
+    JustSetIcontrollable_movy_0_0_2,
+    JustSetIcontrollable_movy_1,
+    JustSetIcontrollable_obsmove,
+    UpdatedLIsNotFirstRound,
+    UpdatedLIsNotFirstRound_becomes0 { x_38 <= 1000 },
+    UpdatedLIsNotFirstRound_becomes1 { x_38 <= 1500 },
+    UpdatedLprev_obsx_0_0_6,
+    UpdatedLprev_obsx_0_0_6_becomes0 { x_40 <= 500 },
+    UpdatedLprev_obsx_0_0_6_becomes1 { x_40 <= 2000 },
+    UpdatedLprev_obsx_1,
+    UpdatedLprev_obsx_1_becomes0 { x_42 <= 2000 },
+    UpdatedLprev_obsx_1_becomes1 { x_42 <= 3000 },
+    UpdatedLprev_obsx_2,
+    UpdatedLprev_obsx_2_becomes0 { x_44 <= 3000 },
+    UpdatedLprev_obsx_2_becomes1 { x_44 <= 0 },
+    dead;
+urgent
+    Init,
+    JustSetIobsx_0_0_6,
+    JustSetIobsx_1,
+    JustSetIobsx_2,
+    JustSetIobsy_0_0_6,
+    JustSetIobsy_1,
+    JustSetIobsy_2,
+    JustSetIrobx_0_0_7,
+    JustSetIrobx_1,
+    JustSetIrobx_2,
+    JustSetIroby_0_0_7,
+    JustSetIroby_1,
+    JustSetIroby_2,
+    JustSetIglitches_0_0_1,
+    JustSetIcontrollable_movx_0_0_2,
+    JustSetIcontrollable_movx_1,
+    JustSetIcontrollable_movy_0_0_2,
+    JustSetIcontrollable_movy_1,
+    JustSetIcontrollable_obsmove,
+    UpdatedLIsNotFirstRound,
+    UpdatedLprev_obsx_0_0_6,
+    UpdatedLprev_obsx_1,
+    UpdatedLprev_obsx_2;
+init
+    Init;
+trans
+    Init -> JustSetIobsx_0_0_6 { assign Iobsx_0_0_6 := 0; },
+    Init -> JustSetIobsx_0_0_6 { assign Iobsx_0_0_6 := 1; },
+    JustSetIobsx_0_0_6 -> JustSetIobsx_1 { assign Iobsx_1 := 0; },
+    JustSetIobsx_0_0_6 -> JustSetIobsx_1 { assign Iobsx_1 := 1; },
+    JustSetIobsx_1 -> JustSetIobsx_2 { assign Iobsx_2 := 0; },
+    JustSetIobsx_1 -> JustSetIobsx_2 { assign Iobsx_2 := 1; },
+    JustSetIobsx_2 -> JustSetIobsy_0_0_6 { assign Iobsy_0_0_6 := 0; },
+    JustSetIobsx_2 -> JustSetIobsy_0_0_6 { assign Iobsy_0_0_6 := 1; },
+    JustSetIobsy_0_0_6 -> JustSetIobsy_1 { assign Iobsy_1 := 0; },
+    JustSetIobsy_0_0_6 -> JustSetIobsy_1 { assign Iobsy_1 := 1; },
+    JustSetIobsy_1 -> JustSetIobsy_2 { assign Iobsy_2 := 0; },
+    JustSetIobsy_1 -> JustSetIobsy_2 { assign Iobsy_2 := 1; },
+    JustSetIobsy_2 -> JustSetIrobx_0_0_7 { assign Irobx_0_0_7 := 0; },
+    JustSetIobsy_2 -> JustSetIrobx_0_0_7 { assign Irobx_0_0_7 := 1; },
+    JustSetIrobx_0_0_7 -> JustSetIrobx_1 { assign Irobx_1 := 0; },
+    JustSetIrobx_0_0_7 -> JustSetIrobx_1 { assign Irobx_1 := 1; },
+    JustSetIrobx_1 -> JustSetIrobx_2 { assign Irobx_2 := 0; },
+    JustSetIrobx_1 -> JustSetIrobx_2 { assign Irobx_2 := 1; },
+    JustSetIrobx_2 -> JustSetIroby_0_0_7 { assign Iroby_0_0_7 := 0; },
+    JustSetIrobx_2 -> JustSetIroby_0_0_7 { assign Iroby_0_0_7 := 1; },
+    JustSetIroby_0_0_7 -> JustSetIroby_1 { assign Iroby_1 := 0; },
+    JustSetIroby_0_0_7 -> JustSetIroby_1 { assign Iroby_1 := 1; },
+    JustSetIroby_1 -> JustSetIroby_2 { assign Iroby_2 := 0; },
+    JustSetIroby_1 -> JustSetIroby_2 { assign Iroby_2 := 1; },
+    JustSetIroby_2 -> JustSetIglitches_0_0_1 { assign Iglitches_0_0_1 := 0; },
+    JustSetIroby_2 -> JustSetIglitches_0_0_1 { assign Iglitches_0_0_1 := 1; },
+    JustSetIglitches_0_0_1 -> JustSetIcontrollable_movx_0_0_2 { assign Icontrollable_movx_0_0_2 := 0; },
+    JustSetIglitches_0_0_1 -> JustSetIcontrollable_movx_0_0_2 { assign Icontrollable_movx_0_0_2 := 1; },
+    JustSetIcontrollable_movx_0_0_2 -> JustSetIcontrollable_movx_1 { assign Icontrollable_movx_1 := 0; },
+    JustSetIcontrollable_movx_0_0_2 -> JustSetIcontrollable_movx_1 { assign Icontrollable_movx_1 := 1; },
+    JustSetIcontrollable_movx_1 -> JustSetIcontrollable_movy_0_0_2 { assign Icontrollable_movy_0_0_2 := 0; },
+    JustSetIcontrollable_movx_1 -> JustSetIcontrollable_movy_0_0_2 { assign Icontrollable_movy_0_0_2 := 1; },
+    JustSetIcontrollable_movy_0_0_2 -> JustSetIcontrollable_movy_1 { assign Icontrollable_movy_1 := 0; },
+    JustSetIcontrollable_movy_0_0_2 -> JustSetIcontrollable_movy_1 { assign Icontrollable_movy_1 := 1; },
+    JustSetIcontrollable_movy_1 -> JustSetIcontrollable_obsmove { assign Icontrollable_obsmove := 0; },
+    JustSetIcontrollable_movy_1 -> JustSetIcontrollable_obsmove { assign Icontrollable_obsmove := 1; },
+    JustSetIcontrollable_obsmove -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1; },
+    JustSetIcontrollable_obsmove -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 >= 1000; },
+    JustSetIcontrollable_obsmove -> UpdatedLIsNotFirstRound { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 >= 1500; },
+    JustSetIcontrollable_obsmove -> UpdatedLIsNotFirstRound_becomes0 { guard LIsNotFirstRound == 1 && LIsNotFirstRound != 1 && x_38 < 1000; },
+    UpdatedLIsNotFirstRound_becomes0 -> UpdatedLIsNotFirstRound { guard x_38 >= 1000; assign x_38:=0, LIsNotFirstRound := 1; },
+    JustSetIcontrollable_obsmove -> UpdatedLIsNotFirstRound_becomes1 { guard LIsNotFirstRound == 0 && LIsNotFirstRound != 1 && x_38 < 1500; },
+    UpdatedLIsNotFirstRound_becomes1 -> UpdatedLIsNotFirstRound { guard x_38 >= 1500; assign x_38:=0, LIsNotFirstRound := 1; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_obsx_0_0_6 { guard Lprev_obsx_0_0_6 == (Iobsx_0_0_6); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_obsx_0_0_6 { guard Lprev_obsx_0_0_6 == 1 && Lprev_obsx_0_0_6 != (Iobsx_0_0_6) && x_40 >= 500; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_obsx_0_0_6 { guard Lprev_obsx_0_0_6 == 0 && Lprev_obsx_0_0_6 != (Iobsx_0_0_6) && x_40 >= 2000; },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_obsx_0_0_6_becomes0 { guard Lprev_obsx_0_0_6 == 1 && Lprev_obsx_0_0_6 != (Iobsx_0_0_6) && x_40 < 500; },
+    UpdatedLprev_obsx_0_0_6_becomes0 -> UpdatedLprev_obsx_0_0_6 { guard x_40 >= 500; assign x_40:=0, Lprev_obsx_0_0_6 := (Iobsx_0_0_6); },
+    UpdatedLIsNotFirstRound -> UpdatedLprev_obsx_0_0_6_becomes1 { guard Lprev_obsx_0_0_6 == 0 && Lprev_obsx_0_0_6 != (Iobsx_0_0_6) && x_40 < 2000; },
+    UpdatedLprev_obsx_0_0_6_becomes1 -> UpdatedLprev_obsx_0_0_6 { guard x_40 >= 2000; assign x_40:=0, Lprev_obsx_0_0_6 := (Iobsx_0_0_6); },
+    UpdatedLprev_obsx_0_0_6 -> UpdatedLprev_obsx_1 { guard Lprev_obsx_1 == (Iobsx_1); },
+    UpdatedLprev_obsx_0_0_6 -> UpdatedLprev_obsx_1 { guard Lprev_obsx_1 == 1 && Lprev_obsx_1 != (Iobsx_1) && x_42 >= 2000; },
+    UpdatedLprev_obsx_0_0_6 -> UpdatedLprev_obsx_1 { guard Lprev_obsx_1 == 0 && Lprev_obsx_1 != (Iobsx_1) && x_42 >= 3000; },
+    UpdatedLprev_obsx_0_0_6 -> UpdatedLprev_obsx_1_becomes0 { guard Lprev_obsx_1 == 1 && Lprev_obsx_1 != (Iobsx_1) && x_42 < 2000; },
+    UpdatedLprev_obsx_1_becomes0 -> UpdatedLprev_obsx_1 { guard x_42 >= 2000; assign x_42:=0, Lprev_obsx_1 := (Iobsx_1); },
+    UpdatedLprev_obsx_0_0_6 -> UpdatedLprev_obsx_1_becomes1 { guard Lprev_obsx_1 == 0 && Lprev_obsx_1 != (Iobsx_1) && x_42 < 3000; },
+    UpdatedLprev_obsx_1_becomes1 -> UpdatedLprev_obsx_1 { guard x_42 >= 3000; assign x_42:=0, Lprev_obsx_1 := (Iobsx_1); },
+    UpdatedLprev_obsx_1 -> UpdatedLprev_obsx_2 { guard Lprev_obsx_2 == (Iobsx_2); },
+    UpdatedLprev_obsx_1 -> UpdatedLprev_obsx_2 { guard Lprev_obsx_2 == 1 && Lprev_obsx_2 != (Iobsx_2) && x_44 >= 3000; },
+    UpdatedLprev_obsx_1 -> UpdatedLprev_obsx_2 { guard Lprev_obsx_2 == 0 && Lprev_obsx_2 != (Iobsx_2) && x_44 >= 0; },
+    UpdatedLprev_obsx_1 -> UpdatedLprev_obsx_2_becomes0 { guard Lprev_obsx_2 == 1 && Lprev_obsx_2 != (Iobsx_2) && x_44 < 3000; },
+    UpdatedLprev_obsx_2_becomes0 -> UpdatedLprev_obsx_2 { guard x_44 >= 3000; assign x_44:=0, Lprev_obsx_2 := (Iobsx_2); },
+    UpdatedLprev_obsx_1 -> UpdatedLprev_obsx_2_becomes1 { guard Lprev_obsx_2 == 0 && Lprev_obsx_2 != (Iobsx_2) && x_44 < 0; },
+    UpdatedLprev_obsx_2_becomes1 -> UpdatedLprev_obsx_2 { guard x_44 >= 0; assign x_44:=0, Lprev_obsx_2 := (Iobsx_2); },
+    UpdatedLprev_obsx_2 -> Init { guard T <= 1500; assign T:=0; },
+    UpdatedLprev_obsx_2 -> dead { guard T >1500; };
+}
+
+system Circuit;
+prop{
+    E<> Circuit_dead
+}
\ No newline at end of file
diff --git a/subprojects/xta/xta-cli/src/main/java/hu/bme/mit/theta/xta/cli/XtaCli.java b/subprojects/xta/xta-cli/src/main/java/hu/bme/mit/theta/xta/cli/XtaCli.java
index 7cfeacdc78..9b7ff78c1d 100644
--- a/subprojects/xta/xta-cli/src/main/java/hu/bme/mit/theta/xta/cli/XtaCli.java
+++ b/subprojects/xta/xta-cli/src/main/java/hu/bme/mit/theta/xta/cli/XtaCli.java
@@ -44,6 +44,7 @@
 import hu.bme.mit.theta.xta.XtaSystem;
 import hu.bme.mit.theta.xta.XtaVisualizer;
 import hu.bme.mit.theta.xta.analysis.config.XtaConfig;
+import hu.bme.mit.theta.xta.analysis.config.XtaConfigBuilder_ClockPred;
 import hu.bme.mit.theta.xta.analysis.config.XtaConfigBuilder_Zone;
 import hu.bme.mit.theta.xta.analysis.lazy.ClockStrategy;
 import hu.bme.mit.theta.xta.analysis.lazy.LazyXtaStatistics;
@@ -69,6 +70,8 @@ public enum Algorithm {
 	@Parameter(names = {"--model", "-m"}, description = "Path of the input model", required = true)
 	String model;
 
+	@Parameter (names = {"--clockpred"}, description = "Use clock predicate domain")
+	boolean clockpred = false;
 	/*@Parameter(names = {"--discreteconcr", "-dc"}, description = "Concrete domain for discrete variables", required = false)
 	DataStrategy2.ConcrDom concrDataDom = DataStrategy2.ConcrDom.EXPL;
 
@@ -104,16 +107,16 @@ public enum Algorithm {
 
 	//Eager CEGAR
 	@Parameter(names = "--domain", description = "Abstract domain")
-	Domain domain = Domain.PRED_CART;
+	String domain = "PRED_CART";
 
 	@Parameter(names = "--refinement", description = "Refinement strategy")
-	Refinement refinement = Refinement.SEQ_ITP;
+	String refinement = "SEQ_ITP";
 
 	@Parameter(names = "--search", description = "Search strategy")
-	Search search = Search.BFS;
+	String search = "BFS";
 
 	@Parameter(names = "--predsplit", description = "Predicate splitting (for predicate abstraction)")
-	PredSplit predSplit = PredSplit.WHOLE;
+	String predSplit = "WHOLE";
 
 	@Parameter(names = "--solver", description = "Sets the underlying SMT solver to use for both the abstraction and the refinement process. Enter in format <solver_name>:<solver_version>, see theta-smtlib-cli.jar for more details. Enter \"Z3\" to use the legacy z3 solver.")
 	String solver = "Z3";
@@ -126,13 +129,13 @@ public enum Algorithm {
 
 
 	@Parameter(names = "--precgranularity", description = "Precision granularity")
-	PrecGranularity precGranularity = PrecGranularity.GLOBAL;
+	String precGranularity = "GLOBAL";
 
 	@Parameter(names = "--maxenum", description = "Maximal number of explicitly enumerated successors (0: unlimited)")
 	Integer maxEnum = 10;
 
 	@Parameter(names = "--initprec", description = "Initial precision of abstraction")
-	InitPrec initPrec = InitPrec.EMPTY;
+	String initPrec = "EMPTY";
 
 	@Parameter(names = "--prunestrategy", description = "Strategy for pruning the ARG after refinement")
 	PruneStrategy pruneStrategy = PruneStrategy.LAZY;
@@ -337,6 +340,7 @@ private void Eager_Cegar_check(XtaSystem xta){
 			final XtaConfig<?, ?, ?> configuration = buildConfiguration(xta, abstractionSolverFactory, refinementSolverFactory);
 			final SafetyResult<?, ?> status = check(configuration);
 			sw.stop();
+			System.out.println(status.isSafe());
 			resultPrinter(status.isSafe(), status.isUnsafe(), xta);
 			if (status.isUnsafe() && cexfile != null) {
 				writeCex(status.asUnsafe());
@@ -349,7 +353,17 @@ private void Eager_Cegar_check(XtaSystem xta){
 	}
 	private XtaConfig<?, ?, ?> buildConfiguration(final XtaSystem xta, final SolverFactory abstractionSolverFactory, final SolverFactory refinementSolverFactory) throws Exception {
 		try {
-			return new XtaConfigBuilder_Zone(domain, refinement, abstractionSolverFactory, refinementSolverFactory)
+			if (clockpred) {
+				XtaConfigBuilder_ClockPred.Domain domainEnum = XtaConfigBuilder_ClockPred.Domain.valueOf(domain);
+				XtaConfigBuilder_ClockPred.Refinement refinementEnum = XtaConfigBuilder_ClockPred.Refinement.valueOf(refinement);
+				return new XtaConfigBuilder_ClockPred(domainEnum, refinementEnum, abstractionSolverFactory, refinementSolverFactory)
+						.precGranularity(precGranularity).search(search)
+						.predSplit(predSplit).maxEnum(maxEnum).initPrec(initPrec)
+						.pruneStrategy(pruneStrategy).logger(logger).build(xta);
+			}
+			XtaConfigBuilder_Zone.Domain domainEnum = XtaConfigBuilder_Zone.Domain.valueOf(domain);
+			XtaConfigBuilder_Zone.Refinement refinementEnum = XtaConfigBuilder_Zone.Refinement.valueOf(refinement);
+			return new XtaConfigBuilder_Zone(domainEnum, refinementEnum, abstractionSolverFactory, refinementSolverFactory)
 					.precGranularity(precGranularity).search(search)
 					.predSplit(predSplit).maxEnum(maxEnum).initPrec(initPrec)
 					.pruneStrategy(pruneStrategy).logger(logger).build(xta);