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Bit 2 of the STATUS register is documented as reserved, but actually means user/superuser mode, where it being cleared means user mode. This bit only has significance if (the documented as reserved) bit 25 of the CONFIG register is on, which tells the core to use user/superuser mode at all.
When user/superuser mode is in effect, an interrupt sets bit 2 of STATUS, and an RTI instruction unsets it. Among other things, when user/superuser mode is in effect, user mode is not allowed to issue GIE, GID, and RTI, and is not allowed to access system registers.
https://parallella.org/forums/viewtopic.php?f=23&t=818&hilit=interrupt
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