chapter5.adoc

Registers

If an optional register is not implemented, the behavior is implementation-dependent unless otherwise specified. An optional field in an implemented register means being WARL. If it is not programmable, it should be hardwired to value matching its meaning and should not cause any effect when written.

Table 1. Register summary

OFFSET	Register	Description
0x0000	INFO
	VERSION	Indicates the specification and the IP vendor.
	IMPLEMENTATION	Indicates the implementation version.
	HWCFG0~2	Indicate the configurations of current IOPMP instance.
	ENTRYOFFSET	Indicates the internal address offsets of each table.
	Programming Protection
	MDSTALL/MDSTALLH	(Optional) Stall and resume the transaction checks when programming the IOPMP.
	RRIDSCP
	Configuration Protection
	MDLCK/MDLCKH	(Optional) lock register for SRCMD table.
	MDCFGLCK	(Optional) lock register for MDCFG table.
	ENTRYLCK	Lock register for IOPMP entry array.
	Error Reporting
	ERR_CFG	Indicates the reactions for the violations
	ERR_INFO	(Optional) indicates the information regarding captured violations.
	ERR_REQID	(Optional) indicates the RRID and entry index regarding the first captured violation.
	ERR_REQADDR/ERR_REQADDRH	(Optional) indicates request address regarding the first captured violation.
	ERR_MFR	(Optional) To retrieve which RRIDs make subsequent violations.
	ERR_MSIADDR/ERR_MSIADDRH	(Optional) The address to trigger MSI.
	ERR_USER(0:7)	(Optional) User-defined violation information.
0x0800	MDCFG Table, m = 0…​HWCFG0.md_num-1, only available when HWCFG0.mdcfg_fmt = 0.
	MDCFG(m)	MD config register, which is to specify the indices of IOPMP entries belonging to a MD.
0x1000	SRCMD Table, s = 0…​HWCFG1.rrid_num-1, only available when HWCFG0.srcmd_fmt = 0.
	SRCMD_EN(s)/SRCMD_ENH(s)	The bitmapped MD enabling register of the requestor s that SRCMD_EN(s)[m] indicates if the requestor is associated with MD m and SRCMD_ENH(s)[m] indicates if the requestor is associated with MD (m+31).
	SRCMD_R(s)/SRCMD_RH(s)	(Optional) bitmapped MD read eanble register, s corresponding to number of requestors, it indicates requestor s read permission on MDs.
	SRCMD_W(s)/SRCMD_WH(s)	(Optional) bitmapped MD write eanble register, s corresponding to number of requestors, it indicates requestor s write permission on MDs.
	SRCMD Table, m =0…​HWCFG0.md_num-1, only available when HWCFG0.srcmd_fmt = 2.
	SRCMD_PERM(m)/SRCMD_PERMH(m)	The bitmapped permission register of the MD m. Bit 2*s of SRCMD_PERM(m).perm holds the read permission for RRID s, and bit 2*s+1 of perm holds the write permission for RRID s, where s ≤15. Similarly, bit 2*(s-16) of SRCMD_PERMH(m).permh holds the read permission for RRID s, and bit 2*(s-16)+1 of permh holds the write permission for RRID s, where s≥16.
ENTRYOFFSET	Entry Array, i =0…HWCFG1.entry_num-1
	ENTRY_ADDR(i)	Bit 33:2 of address (region) for entry i.
	ENTRY_ADDRH(i)	(Optional) bit 65:34 of the address (region) for entry i.
	ENTRY_CFG(i)	The configuration of entry i.
	ENTRY_USER_CFG(i)	(Optional) extension to support user customized attributes.

INFO registers

INFO registers are use to indicate the IOPMP instance configuration info.

VERSION
0x0000
Field	Bits	R/W	Default	Description
vendor	23:0	R	IMP	The JEDEC manufacturer ID.
specver	31:24	R	IMP	The specification version. (it will be defined in ratified version).

IMPLEMENTATION
0x0004
Field	Bits	R/W	Default	Description
impid	31:0	R	IMP	The user-defined implementation ID.

HWCFG0
0x0008
Field	Bits	R/W	Default	Description
mdcfg_fmt	1:0	R	IMP	Indicate the MDCFG format 0x0: Format 0. MDCFG table is implemented. 0x1: Format 1. No MDCFG table. HWCFG.md_entry_num is fixed. 0x2: Format 2. No MDCFG table. HWCFG.md_entry_num is programmable. 0x3: reserved. Please refer to MDCFG Table Formats for details.
srcmd_fmt	3:2	R	IMP	Indicate the SRCMD format 0x0: Format 0. SRCMD_EN(s) and SRCMD_ENH(s) are available. 0x1: Format 1. No SRCMD table. 0x2: Format 2. SRCMD_PERM(m) and SRCMD_PERMH(m) are available. 0x3: reserved. Please refer to SRCMD Table Formats for details.
tor_en	4:4	R	IMP	Indicate if TOR is supported
sps_en	5:5	R	IMP	Indicate secondary permission settings is supported; which are SRCMD_R/RH(i) and SRCMD_W/WH(i) registers.
user_cfg_en	6:6	R	IMP	Indicate if user customized attributes is supported; which are ENTRY_USER_CFG(i) registers.
prient_prog	7:7	W1CS	IMP	A write-1-clear bit is sticky to 0 and indicates if HWCFG2.prio_entry is programmable. Reset to 1 if the implementation supports programmable prio_entry, otherwise, wired to 0.
rrid_transl_en	8:8	R	IMP	Indicate the if tagging a new RRID on the initiator port is supported
rrid_transl_prog	9:9	W1CS	IMP	A write-1-clear bit is sticky to 0 and indicate if the field rrid_transl is programmable. Support only for rrid_transl_en=1, otherwise, wired to 0.
chk_x	10:10	R	IMP	Indicate if the IOPMP implements the check of an instruction fetch. On chk_x=0, all fields of illegal instruction fetches are ignored, including HWCFG0.no_x, ENTRY_CFG(i).sixe, ENTRY_CFG(i).sexe, and ENTRY_CFG(i).x. It should be wired to zero if there is no indication for an instruction fetch.
no_x	11:11	R	IMP	For chk_x=1, the IOPMP with no_x=1 always fails on an instruction fetch; otherwise, it should depend on x-bit in ENTRY_CFG(i). For chk_x=0, no_x has no effect.
no_w	12:12	R	IMP	Indicate if the IOPMP always fails write accesses considered as as no rule matched.
stall_en	13:13	R	IMP	Indicate if the IOPMP implements stall-related features, which are MDSTALL, MDSTALLH, and RRIDSCP registers.
peis	14:14	R	IMP	Indicate if the IOPMP implements interrupt suppression per entry, including fields sire, siwe, and sixe in ENTRY_CFG(i).
pees	15:15	R	IMP	Indicate if the IOPMP implements the error suppression per entry, including fields sere, sewe, and sexe in ENTRY_CFG(i).
mfr_en	16:16	R	IMP	Indicate if the IOPMP implements Multi Faults Record Extension, that is ERR_MFR and ERR_INFO.svc.
md_entry_num	23:17	WARL	IMP	When HWCFG0.mdcfg_fmt = 0x0: must be zero 0x1 or 0x2: md_entry_num indicates each memory domain exactly has (md_entry_num + 1) entries in a memory domain md_entry_num is locked if HWCFG0.enable is 1.
md_num	29:24	R	IMP	Indicate the supported number of MD in the instance
addrh_en	30	R	IMP	Indicate if ENTRY_ADDRH(i) and ERR_MSIADDRH (if ERR_CFG.msi_en = 1) are available.
enable	31:31	W1SS	0	Indicate if the IOPMP checks transactions by default. If it is implemented, it should be initial to 0 and sticky to 1. If it is not implemented, it should be wired to 1. HWCFG0.md_entry_num is locked if enable is 1.

HWCFG1
0x000C
Field	Bits	R/W	Default	Description
rrid_num	15:0	R	IMP	Indicate the supported number of RRID in the instance
entry_num	31:16	R	IMP	Indicate the supported number of entries in the instance

HWCFG2
0x0010
Field	Bits	R/W	Default	Description
prio_entry	15:0	WARL	IMP	Indicate the number of entries matched with priority. These rules should be placed in the lowest order. Within these rules, the lower order has a higher priority.
rrid_transl	31:16	WARL	IMP	The RRID tagged to outgoing transactions. Support only for HWCFG0.rrid_transl_en=1.

ENTRYOFFSET
0x0014
Field	Bits	R/W	Default	Description
offset	31:0	R	IMP	Indicate the offset address of the IOPMP array from the base of an IOPMP instance, a.k.a. the address of VERSION. Note: the offset is a signed number. That is, the IOPMP array can be placed in front of VERSION.

Programming Protection Registers

MDSTALL(H) and RRIDSCP registers are all optional and used to support atomicity issue while programming the IOPMP, as the IOPMP rule may not be updated in a single transaction.

MDSTALL
0x0030
Field	Bits	R/W	Default	Description
exempt	0:0	W	N/A	Stall transactions with exempt selected MDs, or Stall selected MDs.
is_stalled	0:0	R	0	After the last writing of MDSTALL (included) plus any following writing RRIDSCP, 1 indicates that all requested stalls take effect; otherwise, 0. After the last writing MDSTALLH (if any) and then MDSTALL by zero, 0 indicates that all transactions have been resumed; otherwise, 1.
md	31:1	WARL	0	Writing md[m]=1 selects MD m; reading md[m] = 1 means MD m selected.

MDSTALLH
0x0034
Field	Bits	R/W	Default	Description
mdh	31:0	WARL	0	Writing mdh[m]=1 selects MD (m+31); reading mdh[m] = 1 means MD (m+31) selected.

RRIDSCP
0x0038
Field	Bits	R/W	Default	Description
rrid	15:0	WARL	DC	RRID to select
rsv	29:16	ZERO	0	Must be zero on write, reserved for future
op	31:30	W	N/A	0: query 1: stall transactions associated with selected RRID 2: don’t stall transactions associated with selected RRID 3: reserved
stat	31:30	R	0	0: RRIDSCP is not implemented 1: transactions associated with selected RRID are stalled 2: transactions associated with selected RRID are not stalled 3: unimplemented or unselectable RRID

Configuration Protection Registers

MDLCK and MDLCKH are optional registers with a bitmap field to indicate which MDs are locked in the SRCMD table.

MDLCK
0x0040
Field	Bits	R/W	Default	Description
l	0:0	W1SS	0	Lock bit to MDLCK and MDLCKH register.
md	31:1	WARL	0	md[m] is sticky to 1 and indicates if SRCMD_EN(s).md[m], SRCMD_R(i).md[m] and SRCMD_W(s).md[m] are locked for all RRID s.

MDLCKH
0x0044
Field	Bits	R/W	Default	Description
mdh	31:0	WARL	0	mdh[m] is sticky to 1 and indicates if SRCMD_ENH(s).mdh[m], SRCMD_RH(s).mdh[m] and SRCMD_WH(s).mdh[m] are locked for all RRID s.

MDCFGLCK is the lock register to MDCFG table. Available only when MDCFG is in Format 0.

MDCFGLCK
0x0048
Field	Bits	R/W	Default	Description
l	0:0	W1SS	0	Lock bit to MDCFGLCK register.
f	6:1	WARL	IMP	Indicate the number of locked MDCFG entries - MDCFG(m) is locked for m < f. On write, the field only accepts the value larger than the previous value until the next reset cycle; otherwise, there is no effect.
rsv	31:7	ZERO	0	Must be zero on write, reserved for future

ENTRYLCK is the lock register to entry array.

ENTRYLCK
0x004C
Field	Bits	R/W	Default	Description
l	0:0	W1SS	0	Lock bit to ENTRYLCK register.
f	16:1	WARL	IMP	Indicate the number of locked IOPMP entries - ENTRY_ADDR(i), ENTRY_ADDRH(i), ENTRY_CFG(i), and ENTRY_USER_CFG(i) are locked for i < f. On write, the field only accepts the value larger than the previous value until the next reset cycle; otherwise, there is no effect.
rsv	31:17	ZERO	0	Must be zero on write, reserved for future

Error Capture Registers

ERR_CFG is a read/write WARL register used to configure the global error reporting behavior on an IOPMP violation.

ERR_CFG
0x0060
Field	Bits	R/W	Default	Description
l	0:0	W1SS	0	Lock fields to ERR_CFG register
ie	1:1	RW	0	Enable the interrupt of the IOPMP rule violation.
rs	2:2	WARL	0	To suppress an error response on an IOPMP rule violation. 0x0: respond an implementation-dependent error, such as a bus error 0x1: respond a success with a pre-defined value to the initiator instead of an error
msi_en	3:3	WARL	IMP	Indicates whether the IOPMP triggers interrupt by MSI or wired interrupt: 0x0: the IOPMP triggers interrupt by wired interrupt 0x1: the IOPMP triggers interrupt by MSI
stall_violation_en	4:4	WARL	IMP	Indicates whether the IOPMP faults stalled transactions. When the bit is set, the IOPMP faults the transactions if the corresponding RRID is not exempt from stall.
rsv1	7:5	ZERO	0	Must be zero on write, reserved for future
msidata	18:8	WARL	IMP	The data to trigger MSI
rsv2	31:19	ZERO	0	Must be zero on write, reserved for future

ERR_INFO captures more detailed error information.

ERR_INFO
0x0064
Field	Bits	R/W	Default	Description
v	0:0	R	0	Indicate if the illegal capture recorder (ERR_REQID, ERR_REQADDR, ERR_REQADDRH, ERR_INFO.ttype, and ERR_INFO.etype) has a valid content and will keep the content until the bit is cleared. An interrupt will be triggered if a violation is detected and related interrupt enable/supression configure bits are not disabled, the interrupt will keep asserted until the error valid is cleared.
v	0:0	W1C	N/A	Write 1 clears the bit, the illegal recorder reactivates and the interrupt (if enabled). Write 0 causes no effect on the bit.
ttype	2:1	R	0	Indicated the transaction type of the first captured violation 0x00 = reserved 0x01 = read access 0x02 = write access 0x03 = instruction fetch
msi_werr	3:3	R	0	It’s asserted when the write access to trigger an IOPMP-originated MSI has failed. When it’s not available, it should be ZERO.
msi_werr	3:3	W1C	N/A	Write 1 clears the bit. Write 0 causes no effect on the bit.
etype	7:4	R	0	Indicated the type of violation 0x00 = no error 0x01 = illegal read access 0x02 = illegal write access 0x03 = illegal instruction fetch 0x04 = partial hit on a priority rule 0x05 = not hit any rule 0x06 = unknown RRID 0x07 = error due to a stalled transaction. It should not happen when ERR_CFG.stall_violation_en is 0. 0x08 ~ 0x0D = N/A, reserved for future 0x0E ~ 0x0F = user-defined error
svc	8:8	R	0	Indicate there is a subsequent violation caught in ERR_MFR. Implemented only for HWCFG0.mfr_en=1, otherwise, ZERO.
rsv	31:9	ZERO	0	Must be zero on write, reserved for future

When the bus matrix doesn’t have a signal to indicate an instruction fetch, the ttype and etype can never return "instruction fetch" (0x03) and "instruction fetch error" (0x03), respectively.

ERR_REQADDR and ERR_REQADDRH indicate the errored request address of the first captured violation.

ERR_REQADDR
0x0068
Field	Bits	R/W	Default	Description
addr	31:0	R	DC	Indicate the errored address[33:2]

ERR_REQADDRH
0x006C
Field	Bits	R/W	Default	Description
addrh	31:0	R	DC	Indicate the errored address[65:34]

ERR_REQID indicates the errored RRID and entry index of the first captured violation.

ERR_REQID
0x0070
Field	Bits	R/W	Default	Description
rrid	15:0	R	DC	Indicate the errored RRID.
eid	31:16	R	DC	Indicates the index pointing to the entry that catches the violation. If no entry is hit, i.e., etype=0x05 or 0x06, the value of this field is invalid. If the field is not implemented, it should be wired to 0xffff.

ERR_MFR is an optional register. If Multi-Faults Record Extension is enabled (HWCFG0.mfr_en=1), ERR_MFR can be used to retrieve which RRIDs make subsequent violations.

ERR_MFR
0x0074
Field	Bits	R/W	Default	Description
svw	15:0	R	DC	Subsequent violations in the window indexed by svi. svw[j]=1 for the at lease one subsequent violation issued from RRID= svi*16 + j.
svi	27:16	WARL	0	Window’s index to search subsequent violations. When read, IOPMP sequentially scans all windows from svi until one subsequent violation is found. Once the last available window is scanned, the next window to be scanned is the first record window (index is 0). svi indexes the found subsequent violation or svi has been rounded back to the same value. After read, the window’s content, svw, should be clean.
rsv	30:28	ZERO	0	Must be zero on write, reserved for future
svs	31:31	R	0	The status of this window’s content: 0x0 : no subsequent violation found 0x1 : subsequent violation found

ERR_MSIADDR
0x0078
Field	Bits	R/W	Default	Description
msiaddr	31:0	WARL	IMP	The address to trigger MSI. For HWCFG0.addrh_en=0, it contains bits 33 to 2 of the address; otherwise, it contains bits 31 to 0. Available only if ERR_CFG.msi_en=1

ERR_MSIADDRH
0x007C
Field	Bits	R/W	Default	Description
msiaddrh	31:0	WARL	IMP	The higher 32 bits of the address to trigger MSI. Available only if HWCFG0.addrh_en=1 and ERR_CFG.msi_en=1

ERR_USER(0:7) are optional registers to provide users to define their own error capture information.

ERR_USER(i)
0x0080 + 0x04 * i, i = 0…​7
Field	Bits	R/W	Default	Description
user	31:0	IMP	IMP	(Optional) user-defined registers

MDCFG Table Registers

MDCFG table is a lookup to specify the number of IOPMP entries that is associated with each MD. For different formats:

1. Format 0: MDCFG table is implemented.

2. Format 1 and format 2: No MDCFG table.

MDCFG(m), m = 0…​HWCFG0.md_num-1, support up to 63 MDs
0x0800 + (m)*4
Field	Bits	R/W	Default	Description
t	15:0	WARL	DC/IMP	Indicate the top range of memory domain m. An IOPMP entry with index j belongs to MD m If MDCFG(m-1).t ≤ j < MDCFG(m).t, where m>0. MD0 owns the IOPMP entries with index j < MDCFG(0).t. If MDCFG(m-1).t >= MDCFG(m).t, then MD m is empty.
rsv	31:16	ZERO	0	Must be zero on write, reserved for future

SRCMD Table Registers

Format 1 does not implement the SRCMD table registers.

SRCMD_EN(s) and SRCMD_ENH(s) are available when the SRCMD table format (HWCFG0.srcmd_fmt) is 0.

SRCMD_EN(s), s = 0…​HWCFG1.rrid_num-1
0x1000 + (s)*32
Field	Bits	R/W	Default	Description
l	0:0	W1SS	0	A sticky lock bit. When set, locks SRCMD_EN(s), SRCMD_ENH(s), SRCMD_R(s), SRCMD_RH(s), SRCMD_W(s), and SRCMD_WH(s) if any.
md	31:1	WARL	DC	md[m] = 1 indicates MD m is associated with RRID s.

SRCMD_ENH(s), s = 0…​HWCFG1.rrid_num-1
0x1004 + (s)*32
Field	Bits	R/W	Default	Description
mdh	31:0	WARL	DC	mdh[m] = 1 indicates MD (m+31) is associated with RRID s.

SRCMD_PERM(m) and SRCMD_PERMH(m) are available when HWCFG0.srcmd_fmt = 2. In Format 2, an IOPMP checks both the permission of SRCMD_PERM(H)(m) and the ENTRY_CFG.r/w/x permission. A transaction is legal if any of them allows the transaction.

SRCMD_PERM(m), m = 0…​HWCFG0.md_num-1
0x1000 + (m)*32
Field	Bits	R/W	Default	Description
perm	31:0	WARL	DC	Holds two bits per RRID that give the RRID’s read and write permissions for the entry. Bit 2*s holds the read permission for RRID s, and bit 2*s+1 holds the write permission for RRID s, where s≤15.

SRCMD_PERMH(m), m = 0…​HWCFG0.md_num-1
0x1004 + (m)*32
Field	Bits	R/W	Default	Description
permh	31:0	WARL	DC	Holds two bits per RRID that give the RRID’s read and write permissions for the entry. Bit 2*(s-16) holds the read permission for RRID s, and bit 2*(s-16)+1 holds the write permission for RRID s, where s ≥16. The register is implemented when HWCFG0.rrid_num > 16.

SRCMD_R, SRCMD_RH, SRCMD_W and SRCMD_WH are optional registers for the SRCMD table in Format 0; When SPS extension is enabled, the IOPMP checks both the R/W/X and the ENTRY_CFG.r/w/x permission and follows a fail-first rule.

SRCMD_R(s), s = 0…​HWCFG1.rrid_num-1
0x1008 + (s)*32
Field	Bits	R/W	Default	Description
rsv	0:0	ZERO	0	Must be zero on write, reserved for future
md	31:1	WARL	DC	md[m] = 1 indicates RRID s has read access and instruction fetch permission to the corresponding MD m.

SRCMD_RH(s), s = 0…​HWCFG1.rrid_num-1
0x100C + (s)*32
Field	Bits	R/W	Default	Description
mdh	31:0	WARL	DC	mdh[m] = 1 indicates RRID s has read access and instruction fetch permission to MD (m+31).

SRCMD_W(s), s = 0…​HWCFG1.rrid_num-1
0x1010 + (s)*32
Field	Bits	R/W	Default	Description
rsv	0:0	ZERO	0	Must be zero on write, reserved for future
md	31:1	WARL	DC	md[m] = 1 indicates RRID s has write permission to the corresponding MD m.

SRCMD_WH(s), s = 0…​HWCFG1.rrid_num-1
0x1014 + (s)*32
Field	Bits	R/W	Default	Description
mdh	31:0	WARL	DC	mdh[m] = 1 indicates RRID s has write permission to MD (m+31).

Entry Array Registers

ENTRY_ADDR(i), i = 0…​HWCFG1.entry_num-1
ENTRYOFFSET + (i)*16
Field	Bits	R/W	Default	Description
addr	31:0	WARL	DC	The physical address[33:2] of protected memory region.

ENTRY_ADDRH(i), i = 0…​HWCFG1.entry_num-1
ENTRYOFFSET + 0x4 + (i)*16
Field	Bits	R/W	Default	Description
addrh	31:0	WARL	DC	The physical address[65:34] of protected memory region.

A complete 64-bit address consists of these two registers, ENTRY_ADDR and ENTRY_ADDRH. However, an IOPMP can only manage a segment of space, so an implementation would have a certain number of the most significant bits that are the same among all entries. These bits are allowed to be hardwired.

ENTRY_CFG(i), i = 0…​HWCFG1.entry_num-1
ENTRYOFFSET + 0x8 + (i)*16
Field	Bits	R/W	Default	Description
r	0:0	WARL	DC	The read permission to protected memory region
w	1:1			The write permission to the protected memory region
x	2:2			The instruction fetch permission to the protected memory region. Optional field, if unimplemented, write any read the same value as r field.
a	4:3	WARL	DC	The address mode of the IOPMP entry 0x0: OFF 0x1: TOR 0x2: NA4 0x3: NAPOT
sire	5:5	WARL	IMP	To suppress interrupt for an illegal read access caught by the entry
siwe	6:6	WARL	IMP	Suppress interrupt for write violations caught by the entry
sixe	7:7	WARL	IMP	Suppress interrupt on an illegal instruction fetch caught by the entry
sere	8:8	WARL	IMP	Suppress the (bus) error on an illegal read access caught by the entry 0x0: respond an error if ERR_CFG.rs is 0x0. 0x1: do not respond an error. User to define the behavior, e.g., respond a success with an implementation-dependent value to the initiator.
sewe	9:9	WARL	IMP	Suppress the (bus) error on an illegal write access caught by the entry 0x0: respond an error if ERR_CFG.rs is 0x0. 0x1: do not respond an error. User to define the behavior, e.g., respond a success if response is needed
sexe	10:10	WARL	IMP	Suppress the (bus) error on an illegal instruction fetch caught by the entry 0x0: respond an error if ERR_CFG.rs is 0x0. 0x1: do not respond an error. User to define the behavior, e.g., respond a success with an implementation-dependent value to the initiator.
rsv	31:11	ZERO	0	Must be zero on write, reserved for future

Bits, r, w, and x, grant read, write, or instruction fetch permission, respectively. Not each bit should be programmable. Some or all of them could be wired. Besides, an implementation can optionally impose constraints on their combinations. For example, x and w can’t be 1 simultaneously.

ENTRY_USER_CFG implementation defined registers that allows users to define their own additional IOPMP check rules beside the rules defined in ENTRY_CFG.

ENTRY_USER_CFG(i), i =0…​HWCFG1.entry_num-1
ENTRYOFFSET + 0xC + (i)*16
Field	Bits	R/W	Default	Description
im	31:0	IMP	IMP	User customized field