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Would you like to be the maintainer for this package?
Why should this be included in the repository?
sv2v is a SystemVerilog to old-school verilog converter. This is really useful alongside yosys, as there are a bunch of modern SV features that yosys still doesn't support, but you can get the same functionality by preprocessing with sv2v.
Are we allowed to redistribute it?
BSD-3-Clause
What kind of user will use this package, and how many users do you think will use this package?
FPGA users and anybody interested in open VLSI tools. I use sv2v (along with yosys, icestorm, nextpnr, and verilator) to work with iCE40 FPGAs, one of the most affordable entry-level FPGA families.
Please confirm there isn't an open request for this package
Homepage
https://github.com/zachjs/sv2v
Maintainer
Why should this be included in the repository?
sv2v is a SystemVerilog to old-school verilog converter. This is really useful alongside yosys, as there are a bunch of modern SV features that yosys still doesn't support, but you can get the same functionality by preprocessing with sv2v.
Are we allowed to redistribute it?
BSD-3-Clause
What kind of user will use this package, and how many users do you think will use this package?
FPGA users and anybody interested in open VLSI tools. I use sv2v (along with yosys, icestorm, nextpnr, and verilator) to work with iCE40 FPGAs, one of the most affordable entry-level FPGA families.
Link to source archive file
https://github.com/zachjs/sv2v/archive/refs/tags/v0.0.12.tar.gz
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