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pci.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2020 Realtek Corporation
*/
#include <linux/pci.h>
#include "mac.h"
#include "pci.h"
#include "reg.h"
#include "ser.h"
static bool rtw89_pci_disable_clkreq;
static bool rtw89_pci_disable_aspm_l1;
static bool rtw89_pci_disable_l1ss;
module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644);
module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644);
module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644);
MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support");
MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support");
MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support");
static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev)
{
u32 val;
int ret;
rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1,
rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM);
ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM),
1, RTW89_PCI_POLL_BDRAM_RST_CNT, false,
rtwdev, R_AX_PCIE_INIT_CFG1);
if (ret)
return -EBUSY;
return 0;
}
static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev,
struct rtw89_pci_dma_ring *bd_ring,
u32 cur_idx, bool tx)
{
u32 cnt, cur_rp, wp, rp, len;
rp = bd_ring->rp;
wp = bd_ring->wp;
len = bd_ring->len;
cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx);
if (tx)
cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp);
else
cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp);
bd_ring->rp = cur_rp;
return cnt;
}
static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
u32 addr_idx = bd_ring->addr_idx;
u32 cnt, idx;
idx = rtw89_read32(rtwdev, addr_idx);
cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true);
return cnt;
}
static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci,
u32 cnt, bool release_all)
{
struct rtw89_pci_tx_data *tx_data;
struct sk_buff *skb;
u32 qlen;
while (cnt--) {
skb = skb_dequeue(&rtwpci->h2c_queue);
if (!skb) {
rtw89_err(rtwdev, "failed to pre-release fwcmd\n");
return;
}
skb_queue_tail(&rtwpci->h2c_release_queue, skb);
}
qlen = skb_queue_len(&rtwpci->h2c_release_queue);
if (!release_all)
qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0;
while (qlen--) {
skb = skb_dequeue(&rtwpci->h2c_release_queue);
if (!skb) {
rtw89_err(rtwdev, "failed to release fwcmd\n");
return;
}
tx_data = RTW89_PCI_TX_SKB_CB(skb);
dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
}
}
static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci)
{
struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
u32 cnt;
cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring);
if (!cnt)
return;
rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false);
}
static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
u32 addr_idx = bd_ring->addr_idx;
u32 cnt, idx;
idx = rtw89_read32(rtwdev, addr_idx);
cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false);
return cnt;
}
static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rx_info *rx_info;
dma_addr_t dma;
rx_info = RTW89_PCI_RX_SKB_CB(skb);
dma = rx_info->dma;
dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
DMA_FROM_DEVICE);
}
static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rx_info *rx_info;
dma_addr_t dma;
rx_info = RTW89_PCI_RX_SKB_CB(skb);
dma = rx_info->dma;
dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
DMA_FROM_DEVICE);
}
static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rxbd_info *rxbd_info;
struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb);
rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data;
rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS);
rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS);
rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE);
rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG);
return 0;
}
static bool
rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls,
struct sk_buff *new,
const struct sk_buff *skb, u32 offset,
const struct rtw89_pci_rx_info *rx_info,
const struct rtw89_rx_desc_info *desc_info)
{
u32 copy_len = rx_info->len - offset;
if (unlikely(skb_tailroom(new) < copy_len)) {
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
"invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n",
rx_info->len, desc_info->pkt_size, offset, fs, ls);
rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ",
skb->data, rx_info->len);
/* length of a single segment skb is desc_info->pkt_size */
if (fs && ls) {
copy_len = desc_info->pkt_size;
} else {
rtw89_info(rtwdev, "drop rx data due to invalid length\n");
return false;
}
}
skb_put_data(new, skb->data + offset, copy_len);
return true;
}
static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
struct rtw89_pci_rx_info *rx_info;
struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc;
struct sk_buff *new = rx_ring->diliver_skb;
struct sk_buff *skb;
u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info);
u32 offset;
u32 cnt = 1;
bool fs, ls;
int ret;
skb = rx_ring->buf[bd_ring->wp];
rtw89_pci_sync_skb_for_cpu(rtwdev, skb);
ret = rtw89_pci_rxbd_info_update(rtwdev, skb);
if (ret) {
rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n",
bd_ring->wp, ret);
goto err_sync_device;
}
rx_info = RTW89_PCI_RX_SKB_CB(skb);
fs = rx_info->fs;
ls = rx_info->ls;
if (fs) {
if (new) {
rtw89_err(rtwdev, "skb should not be ready before first segment start\n");
goto err_sync_device;
}
if (desc_info->ready) {
rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n");
goto err_sync_device;
}
rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
new = dev_alloc_skb(desc_info->pkt_size);
if (!new)
goto err_sync_device;
rx_ring->diliver_skb = new;
/* first segment has RX desc */
offset = desc_info->offset;
offset += desc_info->long_rxdesc ? sizeof(struct rtw89_rxdesc_long) :
sizeof(struct rtw89_rxdesc_short);
} else {
offset = sizeof(struct rtw89_pci_rxbd_info);
if (!new) {
rtw89_warn(rtwdev, "no last skb\n");
goto err_sync_device;
}
}
if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info))
goto err_sync_device;
rtw89_pci_sync_skb_for_device(rtwdev, skb);
rtw89_pci_rxbd_increase(rx_ring, 1);
if (!desc_info->ready) {
rtw89_warn(rtwdev, "no rx desc information\n");
goto err_free_resource;
}
if (ls) {
rtw89_core_rx(rtwdev, desc_info, new);
rx_ring->diliver_skb = NULL;
desc_info->ready = false;
}
return cnt;
err_sync_device:
rtw89_pci_sync_skb_for_device(rtwdev, skb);
rtw89_pci_rxbd_increase(rx_ring, 1);
err_free_resource:
if (new)
dev_kfree_skb_any(new);
rx_ring->diliver_skb = NULL;
desc_info->ready = false;
return cnt;
}
static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
u32 cnt)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
u32 rx_cnt;
while (cnt && rtwdev->napi_budget_countdown > 0) {
rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring);
if (!rx_cnt) {
rtw89_err(rtwdev, "failed to deliver RXBD skb\n");
/* skip the rest RXBD bufs */
rtw89_pci_rxbd_increase(rx_ring, cnt);
break;
}
cnt -= rx_cnt;
}
rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp);
}
static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci, int budget)
{
struct rtw89_pci_rx_ring *rx_ring;
int countdown = rtwdev->napi_budget_countdown;
u32 cnt;
rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ];
cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring);
if (!cnt)
return 0;
cnt = min_t(u32, budget, cnt);
rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt);
/* In case of flushing pending SKBs, the countdown may exceed. */
if (rtwdev->napi_budget_countdown <= 0)
return budget;
return budget - countdown;
}
static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring,
struct sk_buff *skb, u8 tx_status)
{
struct ieee80211_tx_info *info;
info = IEEE80211_SKB_CB(skb);
ieee80211_tx_info_clear_status(info);
if (info->flags & IEEE80211_TX_CTL_NO_ACK)
info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
if (tx_status == RTW89_TX_DONE) {
info->flags |= IEEE80211_TX_STAT_ACK;
tx_ring->tx_acked++;
} else {
if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)
rtw89_debug(rtwdev, RTW89_DBG_FW,
"failed to TX of status %x\n", tx_status);
switch (tx_status) {
case RTW89_TX_RETRY_LIMIT:
tx_ring->tx_retry_lmt++;
break;
case RTW89_TX_LIFE_TIME:
tx_ring->tx_life_time++;
break;
case RTW89_TX_MACID_DROP:
tx_ring->tx_mac_id_drop++;
break;
default:
rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status);
break;
}
}
ieee80211_tx_status_ni(rtwdev->hw, skb);
}
static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_tx_wd *txwd;
u32 cnt;
cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring);
while (cnt--) {
txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
if (!txwd) {
rtw89_warn(rtwdev, "No busy txwd pages available\n");
break;
}
list_del_init(&txwd->list);
}
}
static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
struct rtw89_pci_tx_wd *txwd;
int i;
for (i = 0; i < wd_ring->page_num; i++) {
txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
if (!txwd)
break;
list_del_init(&txwd->list);
}
}
static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring,
struct rtw89_pci_tx_wd *txwd, u16 seq,
u8 tx_status)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_data *tx_data;
struct sk_buff *skb, *tmp;
u8 txch = tx_ring->txch;
if (!list_empty(&txwd->list)) {
rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n",
txch, seq);
return;
}
/* currently, support for only one frame */
if (skb_queue_len(&txwd->queue) != 1) {
rtw89_warn(rtwdev, "empty pending queue %d page %d\n",
txch, seq);
return;
}
skb_queue_walk_safe(&txwd->queue, skb, tmp) {
skb_unlink(skb, &txwd->queue);
tx_data = RTW89_PCI_TX_SKB_CB(skb);
dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
DMA_TO_DEVICE);
rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status);
}
rtw89_pci_enqueue_txwd(tx_ring, txwd);
}
static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev,
struct rtw89_pci_rpp_fmt *rpp)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_ring *tx_ring;
struct rtw89_pci_tx_wd_ring *wd_ring;
struct rtw89_pci_tx_wd *txwd;
u16 seq;
u8 qsel, tx_status, txch;
seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ);
qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL);
tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS);
txch = rtw89_core_get_ch_dma(rtwdev, qsel);
if (txch == RTW89_TXCH_CH12) {
rtw89_warn(rtwdev, "should no fwcmd release report\n");
return;
}
tx_ring = &rtwpci->tx_rings[txch];
rtw89_pci_reclaim_txbd(rtwdev, tx_ring);
wd_ring = &tx_ring->wd_ring;
txwd = &wd_ring->pages[seq];
rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status);
}
static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
struct rtw89_pci_tx_wd *txwd;
int i;
for (i = 0; i < wd_ring->page_num; i++) {
txwd = &wd_ring->pages[i];
if (!list_empty(&txwd->list))
continue;
rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP);
}
}
static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
u32 max_cnt)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
struct rtw89_pci_rx_info *rx_info;
struct rtw89_pci_rpp_fmt *rpp;
struct rtw89_rx_desc_info desc_info = {};
struct sk_buff *skb;
u32 cnt = 0;
u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt);
u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info);
u32 offset;
int ret;
skb = rx_ring->buf[bd_ring->wp];
rtw89_pci_sync_skb_for_cpu(rtwdev, skb);
ret = rtw89_pci_rxbd_info_update(rtwdev, skb);
if (ret) {
rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n",
bd_ring->wp, ret);
goto err_sync_device;
}
rx_info = RTW89_PCI_RX_SKB_CB(skb);
if (!rx_info->fs || !rx_info->ls) {
rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n");
return cnt;
}
rtw89_core_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size);
/* first segment has RX desc */
offset = desc_info.offset;
offset += desc_info.long_rxdesc ? sizeof(struct rtw89_rxdesc_long) :
sizeof(struct rtw89_rxdesc_short);
for (; offset + rpp_size <= rx_info->len; offset += rpp_size) {
rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset);
rtw89_pci_release_rpp(rtwdev, rpp);
}
rtw89_pci_sync_skb_for_device(rtwdev, skb);
rtw89_pci_rxbd_increase(rx_ring, 1);
cnt++;
return cnt;
err_sync_device:
rtw89_pci_sync_skb_for_device(rtwdev, skb);
return 0;
}
static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
u32 cnt)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
u32 release_cnt;
while (cnt) {
release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt);
if (!release_cnt) {
rtw89_err(rtwdev, "failed to release TX skbs\n");
/* skip the rest RXBD bufs */
rtw89_pci_rxbd_increase(rx_ring, cnt);
break;
}
cnt -= release_cnt;
}
rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp);
}
static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci, int budget)
{
struct rtw89_pci_rx_ring *rx_ring;
u32 cnt;
int work_done;
rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
spin_lock_bh(&rtwpci->trx_lock);
cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring);
if (cnt == 0)
goto out_unlock;
rtw89_pci_release_tx(rtwdev, rx_ring, cnt);
out_unlock:
spin_unlock_bh(&rtwpci->trx_lock);
/* always release all RPQ */
work_done = min_t(int, cnt, budget);
rtwdev->napi_budget_countdown -= work_done;
return work_done;
}
static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci)
{
struct rtw89_pci_rx_ring *rx_ring;
struct rtw89_pci_dma_ring *bd_ring;
u32 reg_idx;
u16 hw_idx, hw_idx_next, host_idx;
int i;
for (i = 0; i < RTW89_RXCH_NUM; i++) {
rx_ring = &rtwpci->rx_rings[i];
bd_ring = &rx_ring->bd_ring;
reg_idx = rtw89_read32(rtwdev, bd_ring->addr_idx);
hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx);
host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx);
hw_idx_next = (hw_idx + 1) % bd_ring->len;
if (hw_idx_next == host_idx)
rtw89_warn(rtwdev, "%d RXD unavailable\n", i);
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
"%d RXD unavailable, idx=0x%08x, len=%d\n",
i, reg_idx, bd_ring->len);
}
}
static void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci,
struct rtw89_pci_isrs *isrs)
{
isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs;
isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0];
isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1];
rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]);
rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]);
}
static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00)
{
/* write 1 clear */
rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00);
}
static void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]);
}
static void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_AX_HIMR0, 0);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0);
}
static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev)
{
struct rtw89_dev *rtwdev = dev;
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_isrs isrs;
unsigned long flags;
spin_lock_irqsave(&rtwpci->irq_lock, flags);
rtw89_pci_recognize_intrs(rtwdev, rtwpci, &isrs);
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
if (unlikely(isrs.isrs[0] & B_AX_RDU_INT))
rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci);
if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN))
rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev));
if (likely(rtwpci->running)) {
local_bh_disable();
napi_schedule(&rtwdev->napi);
local_bh_enable();
}
return IRQ_HANDLED;
}
static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev)
{
struct rtw89_dev *rtwdev = dev;
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
unsigned long flags;
irqreturn_t irqret = IRQ_WAKE_THREAD;
spin_lock_irqsave(&rtwpci->irq_lock, flags);
/* If interrupt event is on the road, it is still trigger interrupt
* even we have done pci_stop() to turn off IMR.
*/
if (unlikely(!rtwpci->running)) {
irqret = IRQ_HANDLED;
goto exit;
}
rtw89_pci_disable_intr(rtwdev, rtwpci);
exit:
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
return irqret;
}
#define case_TXCHADDRS(txch) \
case RTW89_TXCH_##txch: \
*addr_num = R_AX_##txch##_TXBD_NUM; \
*addr_idx = R_AX_##txch##_TXBD_IDX; \
*addr_bdram = R_AX_##txch##_BDRAM_CTRL; \
*addr_desa_l = R_AX_##txch##_TXBD_DESA_L; \
*addr_desa_h = R_AX_##txch##_TXBD_DESA_H; \
break
static int rtw89_pci_get_txch_addrs(enum rtw89_tx_channel txch,
u32 *addr_num,
u32 *addr_idx,
u32 *addr_bdram,
u32 *addr_desa_l,
u32 *addr_desa_h)
{
switch (txch) {
case_TXCHADDRS(ACH0);
case_TXCHADDRS(ACH1);
case_TXCHADDRS(ACH2);
case_TXCHADDRS(ACH3);
case_TXCHADDRS(ACH4);
case_TXCHADDRS(ACH5);
case_TXCHADDRS(ACH6);
case_TXCHADDRS(ACH7);
case_TXCHADDRS(CH8);
case_TXCHADDRS(CH9);
case_TXCHADDRS(CH10);
case_TXCHADDRS(CH11);
case_TXCHADDRS(CH12);
default:
return -EINVAL;
}
return 0;
}
#undef case_TXCHADDRS
#define case_RXCHADDRS(rxch) \
case RTW89_RXCH_##rxch: \
*addr_num = R_AX_##rxch##_RXBD_NUM; \
*addr_idx = R_AX_##rxch##_RXBD_IDX; \
*addr_desa_l = R_AX_##rxch##_RXBD_DESA_L; \
*addr_desa_h = R_AX_##rxch##_RXBD_DESA_H; \
break
static int rtw89_pci_get_rxch_addrs(enum rtw89_rx_channel rxch,
u32 *addr_num,
u32 *addr_idx,
u32 *addr_desa_l,
u32 *addr_desa_h)
{
switch (rxch) {
case_RXCHADDRS(RXQ);
case_RXCHADDRS(RPQ);
default:
return -EINVAL;
}
return 0;
}
#undef case_RXCHADDRS
static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring)
{
struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring;
/* reserved 1 desc check ring is full or not */
if (bd_ring->rp > bd_ring->wp)
return bd_ring->rp - bd_ring->wp - 1;
return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1;
}
static
u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
u32 cnt;
spin_lock_bh(&rtwpci->trx_lock);
rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci);
cnt = rtw89_pci_get_avail_txbd_num(tx_ring);
spin_unlock_bh(&rtwpci->trx_lock);
return cnt;
}
static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,
u8 txch)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
u32 bd_cnt, wd_cnt, min_cnt = 0;
struct rtw89_pci_rx_ring *rx_ring;
u32 cnt;
rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
spin_lock_bh(&rtwpci->trx_lock);
bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring);
wd_cnt = wd_ring->curr_num;
if (wd_cnt == 0 || bd_cnt == 0) {
cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring);
if (!cnt)
goto out_unlock;
rtw89_pci_release_tx(rtwdev, rx_ring, cnt);
}
bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring);
wd_cnt = wd_ring->curr_num;
min_cnt = min(bd_cnt, wd_cnt);
if (min_cnt == 0)
rtw89_warn(rtwdev, "still no tx resource after reclaim\n");
out_unlock:
spin_unlock_bh(&rtwpci->trx_lock);
return min_cnt;
}
static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,
u8 txch)
{
if (txch == RTW89_TXCH_CH12)
return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev);
return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch);
}
static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
u32 host_idx, addr;
addr = bd_ring->addr_idx;
host_idx = bd_ring->wp;
rtw89_write16(rtwdev, addr, host_idx);
}
static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring,
int n_txbd)
{
struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
u32 host_idx, len;
len = bd_ring->len;
host_idx = bd_ring->wp + n_txbd;
host_idx = host_idx < len ? host_idx : host_idx - len;
bd_ring->wp = host_idx;
}
static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
spin_lock_bh(&rtwpci->trx_lock);
__rtw89_pci_tx_kick_off(rtwdev, tx_ring);
spin_unlock_bh(&rtwpci->trx_lock);
}
static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch];
struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
u32 cur_idx, cur_rp;
u8 i;
/* Because the time taked by the I/O is a bit dynamic, it's hard to
* define a reasonable fixed total timeout to use read_poll_timeout*
* helper. Instead, we can ensure a reasonable polling times, so we
* just use for loop with udelay here.
*/
for (i = 0; i < 60; i++) {
cur_idx = rtw89_read32(rtwdev, bd_ring->addr_idx);
cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx);
if (cur_rp == bd_ring->wp)
return;
udelay(1);
}
if (!drop)
rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch);
}
static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs,
bool drop)
{
u8 i;
for (i = 0; i < RTW89_TXCH_NUM; i++) {
/* It may be unnecessary to flush FWCMD queue. */
if (i == RTW89_TXCH_CH12)
continue;
if (txchs & BIT(i))
__pci_flush_txch(rtwdev, i, drop);
}
}
static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
bool drop)
{
__rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop);
}
static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring,
struct rtw89_pci_tx_wd *txwd,
struct rtw89_core_tx_request *tx_req)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
struct rtw89_txwd_body *txwd_body;
struct rtw89_txwd_info *txwd_info;
struct rtw89_pci_tx_wp_info *txwp_info;
struct rtw89_pci_tx_addr_info_32 *txaddr_info;
struct pci_dev *pdev = rtwpci->pdev;
struct sk_buff *skb = tx_req->skb;
struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb);
bool en_wd_info = desc_info->en_wd_info;
u32 txwd_len;
u32 txwp_len;
u32 txaddr_info_len;
dma_addr_t dma;
int ret;
rtw89_core_fill_txdesc(rtwdev, desc_info, txwd->vaddr);
dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
if (dma_mapping_error(&pdev->dev, dma)) {
rtw89_err(rtwdev, "failed to map skb dma data\n");
ret = -EBUSY;
goto err;
}
tx_data->dma = dma;
txaddr_info_len = sizeof(*txaddr_info);
txwp_len = sizeof(*txwp_info);
txwd_len = sizeof(*txwd_body);
txwd_len += en_wd_info ? sizeof(*txwd_info) : 0;
txwp_info = txwd->vaddr + txwd_len;
txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID);
txwp_info->seq1 = 0;
txwp_info->seq2 = 0;
txwp_info->seq3 = 0;
tx_ring->tx_cnt++;
txaddr_info = txwd->vaddr + txwd_len + txwp_len;
txaddr_info->length = cpu_to_le16(skb->len);
txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS |
RTW89_PCI_ADDR_NUM(1));
txaddr_info->dma = cpu_to_le32(dma);
txwd->len = txwd_len + txwp_len + txaddr_info_len;
skb_queue_tail(&txwd->queue, skb);
return 0;
err:
return ret;
}
static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring,
struct rtw89_pci_tx_bd_32 *txbd,
struct rtw89_core_tx_request *tx_req)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
struct rtw89_txwd_body *txwd_body;
struct pci_dev *pdev = rtwpci->pdev;
struct sk_buff *skb = tx_req->skb;
struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb);
dma_addr_t dma;
txwd_body = (struct rtw89_txwd_body *)skb_push(skb, sizeof(*txwd_body));
memset(txwd_body, 0, sizeof(*txwd_body));
rtw89_core_fill_txdesc(rtwdev, desc_info, txwd_body);
dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
if (dma_mapping_error(&pdev->dev, dma)) {
rtw89_err(rtwdev, "failed to map fwcmd dma data\n");
return -EBUSY;
}
tx_data->dma = dma;
txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS);
txbd->length = cpu_to_le16(skb->len);