Variable Length Instructions vs Fixed length Instructions for Stoffel VM

[Mikerah]

Currently, a mixture of design decisions from both MP-SPDZ and SCALE-MAMBA are being used to design the StoffelMPC VM implementation. However, it is clear that this results in a bit of a clunky design due to the use of variable length instructions. The issues that can be resolved with using fixed length instructions as opposed to variable length instructions are the following:

• More readable bytecode. If an instruction takes a lot of parameters, then in the readable assembly format, it would result in this instruction taking up lot of space
• Easier to implement. The instruction struct no longer needs an equivalent start (see here and here) variable to keep track of all of these variable length parameters
• Constant time lookups and corresponding constant time answers for finding the ith instruction. This would be linear with variable length instructions
  The main con that comes from fixed length instructions is that now we may need to increase the instruction set a bit to better handle certain needs (e.g. handling triples). However, I suspect that this could easily be rectified with vectorization

[Mikerah]

After some more thought, another advantage of variable length instructions is that we can minimize the number of rounds needed for communication (see https://eprint.iacr.org/2013/143.pdf). Perhaps, a better design strategy would be to have fixed length instructions for all the instructions that can be performed locally and then have variable length instructions for those that require communication.