From 1bcc8330356ce4c9c90081dc6e93c43983d7ea20 Mon Sep 17 00:00:00 2001 From: MITSUNARI Shigeo Date: Thu, 9 Nov 2023 13:54:32 +0900 Subject: [PATCH] 3-op add supports T_nf --- gen/gen_code.cpp | 2 +- xbyak/xbyak_mnemonic.h | 28 ++++++++++++++-------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/gen/gen_code.cpp b/gen/gen_code.cpp index fd60773e..d7700cb8 100644 --- a/gen/gen_code.cpp +++ b/gen/gen_code.cpp @@ -811,7 +811,7 @@ void put() printf("void %s(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x%02X); }\n", p->name, p->code); printf("void %s(const Operand& op, uint32_t imm) { opOI(op, imm, 0x%02X, %d); }\n", p->name, p->code, p->ext); if (!p->support3op) continue; - std::string s = type2String(0);//p->type); + std::string s = type2String(p->type | T_CODE1_IF1); printf("void %s(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, %s, 0x%02X); }\n", p->name, s.c_str(), p->code); printf("void %s(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, %s, %d); }\n", p->name, s.c_str(), p->ext); } diff --git a/xbyak/xbyak_mnemonic.h b/xbyak/xbyak_mnemonic.h index bbce56ea..877e46de 100644 --- a/xbyak/xbyak_mnemonic.h +++ b/xbyak/xbyak_mnemonic.h @@ -3,14 +3,14 @@ void aadd(const Address& addr, const Reg32e ®) { opMR(addr, reg, T_0F38, 0x0F void aand(const Address& addr, const Reg32e ®) { opMR(addr, reg, T_0F38 | T_66, 0x0FC); } void adc(const Operand& op, uint32_t imm) { opOI(op, imm, 0x10, 2); } void adc(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x10); } -void adc(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 2); } -void adc(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x10); } +void adc(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_CODE1_IF1, 2); } +void adc(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_CODE1_IF1, 0x10); } void adcx(const Reg32e& d, const Reg32e& reg, const Operand& op) { opROO(d, op, reg, T_66, 0x66); } void adcx(const Reg32e& reg, const Operand& op) { if (!reg.isREG(16|i32e) && reg.getBit() == op.getBit()) XBYAK_THROW(ERR_BAD_SIZE_OF_REGISTER) if (opROO(Reg(), op, reg, T_66, 0x66)) return; opRO(reg, op, T_66 | T_0F38, 0xF6); } void add(const Operand& op, uint32_t imm) { opOI(op, imm, 0x00, 0); } void add(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x00); } -void add(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 0); } -void add(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x00); } +void add(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NF|T_CODE1_IF1, 0); } +void add(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NF|T_CODE1_IF1, 0x00); } void addpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x58, isXMM_XMMorMEM); } void addps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F, 0x58, isXMM_XMMorMEM); } void addsd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_F2, 0x58, isXMM_XMMorMEM); } @@ -27,8 +27,8 @@ void aesimc(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_66|T_0F38|T_W0 void aeskeygenassist(const Xmm& xmm, const Operand& op, uint8_t imm) { opSSE(xmm, op, T_66|T_0F3A, 0xDF, isXMM_XMMorMEM, imm); } void and_(const Operand& op, uint32_t imm) { opOI(op, imm, 0x20, 4); } void and_(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x20); } -void and_(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 4); } -void and_(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x20); } +void and_(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NF|T_CODE1_IF1, 4); } +void and_(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NF|T_CODE1_IF1, 0x20); } void andnpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x55, isXMM_XMMorMEM); } void andnps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F, 0x55, isXMM_XMMorMEM); } void andpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x54, isXMM_XMMorMEM); } @@ -566,8 +566,8 @@ void neg(const Operand& op) { opRext(op, 0, 3, 0, 0xF6); } void not_(const Operand& op) { opRext(op, 0, 2, 0, 0xF6); } void or_(const Operand& op, uint32_t imm) { opOI(op, imm, 0x08, 1); } void or_(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x08); } -void or_(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 1); } -void or_(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x08); } +void or_(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NF|T_CODE1_IF1, 1); } +void or_(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NF|T_CODE1_IF1, 0x08); } void orpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x56, isXMM_XMMorMEM); } void orps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F, 0x56, isXMM_XMMorMEM); } void out_(const Reg& d, const Reg& a) { opInOut(a, d, 0xEE); } @@ -759,8 +759,8 @@ void sar(const Operand& op, int imm) { opShift(op, imm, 7); } void sarx(const Reg32e& r1, const Operand& op, const Reg32e& r2) { opRRO(r1, r2, op, T_F3|T_0F38, 0xf7); } void sbb(const Operand& op, uint32_t imm) { opOI(op, imm, 0x18, 3); } void sbb(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x18); } -void sbb(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 3); } -void sbb(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x18); } +void sbb(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_CODE1_IF1, 3); } +void sbb(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_CODE1_IF1, 0x18); } void scasb() { db(0xAE); } void scasd() { db(0xAF); } void scasw() { db(0x66); db(0xAF); } @@ -829,8 +829,8 @@ void stosd() { db(0xAB); } void stosw() { db(0x66); db(0xAB); } void sub(const Operand& op, uint32_t imm) { opOI(op, imm, 0x28, 5); } void sub(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x28); } -void sub(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 5); } -void sub(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x28); } +void sub(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NF|T_CODE1_IF1, 5); } +void sub(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NF|T_CODE1_IF1, 0x28); } void subpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x5C, isXMM_XMMorMEM); } void subps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F, 0x5C, isXMM_XMMorMEM); } void subsd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_F2, 0x5C, isXMM_XMMorMEM); } @@ -1409,8 +1409,8 @@ void xgetbv() { db(0x0F); db(0x01); db(0xD0); } void xlatb() { db(0xD7); } void xor_(const Operand& op, uint32_t imm) { opOI(op, imm, 0x30, 6); } void xor_(const Operand& op1, const Operand& op2) { opRO_MR(op1, op2, 0x30); } -void xor_(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NONE, 6); } -void xor_(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NONE, 0x30); } +void xor_(const Reg& d, const Operand& op, uint32_t imm) { opROI(d, op, imm, T_NF|T_CODE1_IF1, 6); } +void xor_(const Reg& d, const Operand& op1, const Operand& op2) { opROO(d, op1, op2, T_NF|T_CODE1_IF1, 0x30); } void xorpd(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F | T_66, 0x57, isXMM_XMMorMEM); } void xorps(const Xmm& xmm, const Operand& op) { opSSE(xmm, op, T_0F, 0x57, isXMM_XMMorMEM); } #ifdef XBYAK_ENABLE_OMITTED_OPERAND