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signalgenerate.map.rpt
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signalgenerate.map.rpt
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Analysis & Synthesis report for signalgenerate
Mon Mar 04 22:43:34 2019
Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. Registers Protected by Synthesis
11. Registers Removed During Synthesis
12. Removed Registers Triggering Further Register Optimizations
13. General Register Statistics
14. Inverted Register Statistics
15. Multiplexer Restructuring Statistics (Restructuring Performed)
16. Source assignments for Top-level Entity: |PCI
17. Source assignments for scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|dpram_rms:FIFOram|altsyncram_c6k1:altsyncram1
18. Source assignments for scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|dpram_tms:FIFOram|altsyncram_a6k1:altsyncram1
19. Source assignments for scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|dpram_tms:FIFOram|altsyncram_a6k1:altsyncram1
20. Source assignments for sld_signaltap:auto_signaltap_0
21. Parameter Settings for User Entity Instance: scfifo:UUT_DmaDesc_FIFO
22. Parameter Settings for User Entity Instance: scfifo:UUT_DmaRd_FIFO1
23. Parameter Settings for User Entity Instance: scfifo:UUT_DmaRd_FIFO2
24. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
25. scfifo Parameter Settings by Entity Instance
26. Port Connectivity Checks: "SpiMaster:UUT_AD9642_SPI2"
27. Port Connectivity Checks: "SpiMaster:UUT_AD9642_SPI1"
28. SignalTap II Logic Analyzer Settings
29. Post-Synthesis Netlist Statistics for Top Partition
30. Post-Synthesis Netlist Statistics for Partition sld_signaltap:auto_signaltap_0
31. Post-Synthesis Netlist Statistics for Partition sld_hub:auto_hub
32. Elapsed Time Per Partition
33. Connections to In-System Debugging Instance "auto_signaltap_0"
34. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 04 22:43:34 2019 ;
; Quartus II 64-Bit Version ; 14.1.0 Build 186 12/03/2014 SJ Full Version ;
; Revision Name ; signalgenerate ;
; Top-level Entity Name ; PCI ;
; Family ; Cyclone IV E ;
; Total logic elements ; 3,943 ;
; Total combinational functions ; 1,788 ;
; Dedicated logic registers ; 3,072 ;
; Total registers ; 3072 ;
; Total pins ; 87 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 356,416 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE30F23I7 ; ;
; Top-level entity name ; PCI ; signalgenerate ;
; Family name ; Cyclone IV E ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; < 0.1% ;
; Processors 5-8 ; 0.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------+-----------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+--------------------------------------------------------+-----------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------+
; SpiMaster.vhd ; yes ; User VHDL File ; F:/altera_pci/SelfTest/SpiMaster.vhd ; ;
; signalgenerate.vhd ; yes ; User VHDL File ; F:/altera_pci/SelfTest/signalgenerate.vhd ; ;
; define.vhd ; yes ; User VHDL File ; F:/altera_pci/SelfTest/define.vhd ; ;
; scfifo.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/scfifo.tdf ; ;
; a_regfifo.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_regfifo.inc ; ;
; a_dpfifo.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_dpfifo.inc ; ;
; a_i2fifo.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_i2fifo.inc ; ;
; a_fffifo.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_fffifo.inc ; ;
; a_f2fifo.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_f2fifo.inc ; ;
; aglobal141.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/aglobal141.inc ; ;
; db/scfifo_h5m.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/scfifo_h5m.tdf ; ;
; db/a_dpfifo_ujt.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/a_dpfifo_ujt.tdf ; ;
; db/a_fefifo_jaf.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/a_fefifo_jaf.tdf ; ;
; db/cntr_op7.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_op7.tdf ; ;
; db/dpram_rms.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/dpram_rms.tdf ; ;
; db/altsyncram_c6k1.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/altsyncram_c6k1.tdf ; ;
; db/cntr_cpb.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_cpb.tdf ; ;
; db/scfifo_bjl.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/scfifo_bjl.tdf ; ;
; db/a_dpfifo_o1t.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/a_dpfifo_o1t.tdf ; ;
; db/a_fefifo_raf.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/a_fefifo_raf.tdf ; ;
; db/cntr_pp7.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_pp7.tdf ; ;
; db/dpram_tms.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/dpram_tms.tdf ; ;
; db/altsyncram_a6k1.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/altsyncram_a6k1.tdf ; ;
; db/cntr_dpb.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_dpb.tdf ; ;
; db/scfifo_hsk.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/scfifo_hsk.tdf ; ;
; db/a_dpfifo_ffs.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/a_dpfifo_ffs.tdf ; ;
; db/a_fefifo_sae.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/a_fefifo_sae.tdf ; ;
; sld_signaltap.vhd ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_signaltap.vhd ; ;
; sld_signaltap_impl.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd ; ;
; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_ela_control.vhd ; ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; ;
; lpm_constant.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
; dffeea.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/dffeea.inc ; ;
; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_mbpmg.vhd ; ;
; sld_ela_trigger_flow_mgr.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd ; ;
; sld_buffer_manager.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd ; ;
; altsyncram.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_4424.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/altsyncram_4424.tdf ; ;
; altdpram.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altdpram.tdf ; ;
; memmodes.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/others/maxplus2/memmodes.inc ; ;
; a_hdffe.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/a_hdffe.inc ; ;
; alt_le_rden_reg.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/alt_le_rden_reg.inc ; ;
; altsyncram.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altsyncram.inc ; ;
; lpm_mux.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_mux.tdf ; ;
; muxlut.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/muxlut.inc ; ;
; bypassff.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/bypassff.inc ; ;
; altshift.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/altshift.inc ; ;
; db/mux_rsc.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/mux_rsc.tdf ; ;
; lpm_decode.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_decode.tdf ; ;
; declut.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/declut.inc ; ;
; lpm_compare.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
; db/decode_dvf.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/decode_dvf.tdf ; ;
; lpm_counter.tdf ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; cmpconst.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/cmpconst.inc ; ;
; lpm_counter.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
; alt_counter_stratix.inc ; yes ; Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
; db/cntr_3ii.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_3ii.tdf ; ;
; db/cmpr_ugc.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cmpr_ugc.tdf ; ;
; db/cntr_g9j.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_g9j.tdf ; ;
; db/cntr_egi.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_egi.tdf ; ;
; db/cmpr_rgc.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cmpr_rgc.tdf ; ;
; db/cntr_23j.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cntr_23j.tdf ; ;
; db/cmpr_ngc.tdf ; yes ; Auto-Generated Megafunction ; F:/altera_pci/SelfTest/db/cmpr_ngc.tdf ; ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_hub.vhd ; work ;
; db/ip/sld1a6223b6/alt_sld_fab.v ; yes ; Encrypted Auto-Found Verilog HDL File ; F:/altera_pci/SelfTest/db/ip/sld1a6223b6/alt_sld_fab.v ; alt_sld_fab ;
; db/ip/sld1a6223b6/submodules/alt_sld_fab_ident.sv ; yes ; Auto-Found SystemVerilog HDL File ; F:/altera_pci/SelfTest/db/ip/sld1a6223b6/submodules/alt_sld_fab_ident.sv ; alt_sld_fab ;
; db/ip/sld1a6223b6/submodules/alt_sld_fab_presplit.sv ; yes ; Encrypted Auto-Found SystemVerilog HDL File ; F:/altera_pci/SelfTest/db/ip/sld1a6223b6/submodules/alt_sld_fab_presplit.sv ; alt_sld_fab ;
; db/ip/sld1a6223b6/submodules/alt_sld_fab_sldfabric.vhd ; yes ; Encrypted Auto-Found VHDL File ; F:/altera_pci/SelfTest/db/ip/sld1a6223b6/submodules/alt_sld_fab_sldfabric.vhd ; alt_sld_fab ;
; db/ip/sld1a6223b6/submodules/alt_sld_fab_splitter.sv ; yes ; Encrypted Auto-Found SystemVerilog HDL File ; F:/altera_pci/SelfTest/db/ip/sld1a6223b6/submodules/alt_sld_fab_splitter.sv ; alt_sld_fab ;
; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; e:/altera/14.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ;
+--------------------------------------------------------+-----------------+----------------------------------------------+-------------------------------------------------------------------------------+-------------+
+---------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-----------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------+
; Estimated Total logic elements ; 3,943 ;
; ; ;
; Total combinational functions ; 1788 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 997 ;
; -- 3 input functions ; 471 ;
; -- <=2 input functions ; 320 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1609 ;
; -- arithmetic mode ; 179 ;
; ; ;
; Total registers ; 3072 ;
; -- Dedicated logic registers ; 3072 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 87 ;
; Total memory bits ; 356416 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; Clk_Board~input ;
; Maximum fan-out ; 1584 ;
; Total fan-out ; 19994 ;
; Average fan-out ; 3.78 ;
+---------------------------------------------+-----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+---------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |PCI ; 1788 (547) ; 3072 (515) ; 356416 ; 0 ; 0 ; 0 ; 87 ; 0 ; |PCI ; work ;
; |SpiMaster:UUT_AD9642_SPI1| ; 82 (82) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|SpiMaster:UUT_AD9642_SPI1 ; work ;
; |SpiMaster:UUT_AD9642_SPI2| ; 82 (82) ; 75 (75) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|SpiMaster:UUT_AD9642_SPI2 ; work ;
; |scfifo:UUT_DmaDesc_FIFO| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaDesc_FIFO ; work ;
; |scfifo_h5m:auto_generated| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated ; work ;
; |a_dpfifo_ujt:dpfifo| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo ; work ;
; |dpram_rms:FIFOram| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|dpram_rms:FIFOram ; work ;
; |altsyncram_c6k1:altsyncram1| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|dpram_rms:FIFOram|altsyncram_c6k1:altsyncram1 ; work ;
; |scfifo:UUT_DmaRd_FIFO1| ; 46 (0) ; 35 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1 ; work ;
; |scfifo_bjl:auto_generated| ; 46 (0) ; 35 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated ; work ;
; |a_dpfifo_o1t:dpfifo| ; 46 (2) ; 35 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo ; work ;
; |a_fefifo_raf:fifo_state| ; 22 (11) ; 13 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|a_fefifo_raf:fifo_state ; work ;
; |cntr_pp7:count_usedw| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|a_fefifo_raf:fifo_state|cntr_pp7:count_usedw ; work ;
; |cntr_dpb:rd_ptr_count| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|cntr_dpb:rd_ptr_count ; work ;
; |cntr_dpb:wr_ptr| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|cntr_dpb:wr_ptr ; work ;
; |dpram_tms:FIFOram| ; 0 (0) ; 0 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|dpram_tms:FIFOram ; work ;
; |altsyncram_a6k1:altsyncram1| ; 0 (0) ; 0 (0) ; 28672 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|dpram_tms:FIFOram|altsyncram_a6k1:altsyncram1 ; work ;
; |sld_hub:auto_hub| ; 145 (1) ; 100 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_hub:auto_hub ; work ;
; |alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric| ; 144 (1) ; 100 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric ; alt_sld_fab ;
; |alt_sld_fab_sldfabric:sldfabric| ; 143 (0) ; 95 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric ; alt_sld_fab ;
; |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub| ; 143 (104) ; 95 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ; work ;
; |sld_rom_sr:hub_info_reg| ; 21 (21) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg ; work ;
; |sld_shadow_jsm:shadow_jsm| ; 18 (18) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; work ;
; |sld_signaltap:auto_signaltap_0| ; 886 (2) ; 2272 (320) ; 327680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0 ; work ;
; |sld_signaltap_impl:sld_signaltap_body| ; 884 (0) ; 1952 (0) ; 327680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; work ;
; |sld_signaltap_implb:sld_signaltap_body| ; 884 (88) ; 1952 (722) ; 327680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body ; work ;
; |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem| ; 25 (0) ; 70 (70) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem ; work ;
; |lpm_decode:wdecoder| ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder ; work ;
; |decode_dvf:auto_generated| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_dvf:auto_generated ; work ;
; |lpm_mux:mux| ; 23 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux ; work ;
; |mux_rsc:auto_generated| ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_rsc:auto_generated ; work ;
; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 (0) ; 327680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; work ;
; |altsyncram_4424:auto_generated| ; 0 (0) ; 0 (0) ; 327680 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_4424:auto_generated ; work ;
; |lpm_shiftreg:segment_offset_config_deserialize| ; 0 (0) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize ; work ;
; |lpm_shiftreg:status_register| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register ; work ;
; |serial_crc_16:\tdo_crc_gen:tdo_crc_calc| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc ; work ;
; |sld_buffer_manager:sld_buffer_manager_inst| ; 87 (87) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ; work ;
; |sld_ela_control:ela_control| ; 376 (1) ; 816 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control ; work ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; work ;
; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 320 (0) ; 800 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; work ;
; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 480 (480) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; work ;
; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 320 (0) ; 320 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:100:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:100:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:101:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:101:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:102:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:102:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:103:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:103:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:104:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:104:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:105:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:105:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:106:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:106:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:107:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:107:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:108:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:108:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:109:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:109:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:110:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:110:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:111:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:111:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:112:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:112:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:113:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:113:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:114:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:114:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:115:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:115:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:116:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:116:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:117:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:117:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:118:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:118:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:119:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:119:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:120:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:120:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:121:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:121:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:122:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:122:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:123:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:123:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:124:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:124:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:125:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:125:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:126:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:126:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:127:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:127:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:128:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:128:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:129:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:129:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:130:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:130:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:131:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:131:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:132:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:132:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:133:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:133:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:134:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:134:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:135:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:135:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:136:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:136:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:137:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:137:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:138:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:138:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:139:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:139:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:140:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:140:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:141:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:141:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:142:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:142:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:143:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:143:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:144:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:144:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:145:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:145:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:146:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:146:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:147:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:147:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:148:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:148:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:149:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:149:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:150:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:150:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:151:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:151:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:152:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:152:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:153:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:153:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:154:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:154:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:155:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:155:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:156:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:156:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:157:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:157:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:158:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:158:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:159:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:159:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:54:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:55:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:56:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:57:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:58:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:59:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:60:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:61:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:62:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:63:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:64:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:65:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:66:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:67:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:68:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:69:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:70:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:71:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:72:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:74:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:75:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:76:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:77:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:78:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:79:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:80:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:81:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:82:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:83:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:84:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:85:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:86:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:87:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:88:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:89:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:89:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:90:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:90:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:91:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:91:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:92:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:92:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:93:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:93:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:94:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:94:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:95:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:95:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:96:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:96:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:97:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:97:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:98:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:98:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1 ; work ;
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1 ; work ;
; |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity| ; 55 (55) ; 11 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ; work ;
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize ; work ;
; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 247 (10) ; 231 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; work ;
; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 10 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; work ;
; |cntr_3ii:auto_generated| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_3ii:auto_generated ; work ;
; |lpm_counter:read_pointer_counter| ; 11 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; work ;
; |cntr_g9j:auto_generated| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_g9j:auto_generated ; work ;
; |lpm_counter:status_advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ; work ;
; |cntr_egi:auto_generated| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_egi:auto_generated ; work ;
; |lpm_counter:status_read_pointer_counter| ; 3 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ; work ;
; |cntr_23j:auto_generated| ; 3 (3) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_23j:auto_generated ; work ;
; |lpm_shiftreg:info_data_shift_out| ; 23 (23) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; work ;
; |lpm_shiftreg:ram_data_shift_out| ; 160 (160) ; 160 (160) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; work ;
; |lpm_shiftreg:status_data_shift_out| ; 23 (23) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out ; work ;
; |sld_rom_sr:crc_rom_sr| ; 30 (30) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; work ;
+---------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|dpram_rms:FIFOram|altsyncram_c6k1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; None ;
; scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|dpram_tms:FIFOram|altsyncram_a6k1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 14 ; 2048 ; 14 ; 28672 ; None ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_4424:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 160 ; 2048 ; 160 ; 327680 ; None ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric ; ;
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_presplit:presplit ; ;
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric ; ;
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_splitter:splitter ; ;
+--------+--------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
+---------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis ;
+-----------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-----------------------+------------------------------------------------------------------+--------------------------------------------+
; ADDRESS[2] ; yes ; yes ;
; ADDRESS[3] ; yes ; yes ;
; ADDRESS[4] ; yes ; yes ;
; ADDRESS[5] ; yes ; yes ;
; ADDRESS[6] ; yes ; yes ;
; ADDRESS[7] ; yes ; yes ;
; PCI_Config_WrData[0] ; yes ; yes ;
; PCI_Config_WrData[10] ; yes ; yes ;
; PCI_Config_WrData[11] ; yes ; yes ;
; PCI_Config_WrData[12] ; yes ; yes ;
; PCI_Config_WrData[13] ; yes ; yes ;
; PCI_Config_WrData[14] ; yes ; yes ;
; PCI_Config_WrData[15] ; yes ; yes ;
; PCI_Config_WrData[16] ; yes ; yes ;
; PCI_Config_WrData[17] ; yes ; yes ;
; PCI_Config_WrData[18] ; yes ; yes ;
; PCI_Config_WrData[19] ; yes ; yes ;
; PCI_Config_WrData[1] ; yes ; yes ;
; PCI_Config_WrData[20] ; yes ; yes ;
; PCI_Config_WrData[21] ; yes ; yes ;
; PCI_Config_WrData[22] ; yes ; yes ;
; PCI_Config_WrData[23] ; yes ; yes ;
; PCI_Config_WrData[24] ; yes ; yes ;
; PCI_Config_WrData[25] ; yes ; yes ;
; PCI_Config_WrData[26] ; yes ; yes ;
; PCI_Config_WrData[27] ; yes ; yes ;
; PCI_Config_WrData[28] ; yes ; yes ;
; PCI_Config_WrData[29] ; yes ; yes ;
; PCI_Config_WrData[2] ; yes ; yes ;
; PCI_Config_WrData[30] ; yes ; yes ;
; PCI_Config_WrData[31] ; yes ; yes ;
; PCI_Config_WrData[3] ; yes ; yes ;
; PCI_Config_WrData[4] ; yes ; yes ;
; PCI_Config_WrData[5] ; yes ; yes ;
; PCI_Config_WrData[6] ; yes ; yes ;
; PCI_Config_WrData[7] ; yes ; yes ;
; PCI_Config_WrData[8] ; yes ; yes ;
; PCI_Config_WrData[9] ; yes ; yes ;
; STATUS[1] ; yes ; yes ;
; STATUS[0] ; yes ; yes ;
; ConfCS ; yes ; yes ;
; Curr_State_Dma[2] ; yes ; yes ;
; Curr_State_Dma[1] ; yes ; yes ;
; Curr_State_Dma[0] ; yes ; yes ;
+-----------------------+------------------------------------------------------------------+--------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; STOP~reg0 ; Stuck at VCC due to stuck port data_in ;
; CBE[3]~reg0 ; Stuck at GND due to stuck port data_in ;
; DEVSEL~reg0 ; Stuck at GND due to stuck port data_in ;
; DMA_PCIAddress[0,1] ; Stuck at GND due to stuck port data_in ;
; IntReg[0,1] ; Stuck at GND due to stuck port data_in ;
; INTA~reg0 ; Stuck at GND due to stuck port data_in ;
; UUT_DmaRd_FIFO2_Rd ; Lost fanout ;
; scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|cntr_dpb:wr_ptr|counter_reg_bit[0..10] ; Lost fanout ;
; scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|cntr_dpb:rd_ptr_count|counter_reg_bit[0..10] ; Lost fanout ;
; scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|a_fefifo_sae:fifo_state|b_full ; Lost fanout ;
; scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|a_fefifo_sae:fifo_state|b_non_empty ; Lost fanout ;
; scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|a_fefifo_sae:fifo_state|cntr_pp7:count_usedw|counter_reg_bit[0..10] ; Lost fanout ;
; DMA_DonePCIAddress[0,1] ; Stuck at GND due to stuck port data_in ;
; ConfReg[5][17] ; Merged with ConfReg[5][16] ;
; ConfReg[5][18] ; Merged with ConfReg[5][16] ;
; ConfReg[5][19] ; Merged with ConfReg[5][16] ;
; ConfReg[5][1] ; Merged with ConfReg[5][16] ;
; ConfReg[5][20] ; Merged with ConfReg[5][16] ;
; ConfReg[5][21] ; Merged with ConfReg[5][16] ;
; ConfReg[5][22] ; Merged with ConfReg[5][16] ;
; ConfReg[5][23] ; Merged with ConfReg[5][16] ;
; ConfReg[5][24] ; Merged with ConfReg[5][16] ;
; ConfReg[5][25] ; Merged with ConfReg[5][16] ;
; ConfReg[5][26] ; Merged with ConfReg[5][16] ;
; ConfReg[5][27] ; Merged with ConfReg[5][16] ;
; ConfReg[5][28] ; Merged with ConfReg[5][16] ;
; ConfReg[5][29] ; Merged with ConfReg[5][16] ;
; ConfReg[5][2] ; Merged with ConfReg[5][16] ;
; ConfReg[5][30] ; Merged with ConfReg[5][16] ;
; ConfReg[5][31] ; Merged with ConfReg[5][16] ;
; ConfReg[5][3] ; Merged with ConfReg[5][16] ;
; ConfReg[5][4] ; Merged with ConfReg[5][16] ;
; ConfReg[5][5] ; Merged with ConfReg[5][16] ;
; ConfReg[4][1] ; Merged with ConfReg[4][0] ;
; ConfReg[4][2] ; Merged with ConfReg[4][0] ;
; ConfReg[4][3] ; Merged with ConfReg[4][0] ;
; ConfReg[4][4] ; Merged with ConfReg[4][0] ;
; ConfReg[4][5] ; Merged with ConfReg[4][0] ;
; ConfReg[4][6] ; Merged with ConfReg[4][0] ;
; ConfReg[4][7] ; Merged with ConfReg[4][0] ;
; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:wr_ptr|counter_reg_bit[0..9] ; Stuck at GND due to stuck port clock_enable ;
; UUT_DmaDesc_FIFO_Rst ; Stuck at GND due to stuck port data_in ;
; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|b_full ; Stuck at GND due to stuck port data_in ;
; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|b_non_empty ; Stuck at GND due to stuck port data_in ;
; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[0..9] ; Stuck at GND due to stuck port clock_enable ;
; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[0..9] ; Stuck at GND due to stuck port clock_enable ;
; ConfReg[5][16] ; Stuck at GND due to stuck port data_in ;
; ConfReg[5][0] ; Stuck at VCC due to stuck port data_in ;
; ConfReg[4][0] ; Stuck at GND due to stuck port data_in ;
; SpiMaster:UUT_AD9642_SPI1|nCS ; Stuck at VCC due to stuck port data_in ;
; SpiMaster:UUT_AD9642_SPI2|nCS ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 111 ; ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|segment_shift_clk_ena ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[0] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[0] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[1] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[1] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[2] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[2] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[3] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[3] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[4] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[4] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[5] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[5] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[6] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[6] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[7] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[7] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[8] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[8] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[9] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[9] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:offset_count[10] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:next_address[10] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[0] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[0] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[1] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[1] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[2] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[2] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[3] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[3] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[4] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[4] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[5] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[5] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[6] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[6] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[7] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[7] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[8] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[8] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[9] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[9] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|current_offset_delayed[10] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_address_delayed[10] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[13..15] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 26 ; ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; UUT_DmaDesc_FIFO_Rst ; Stuck at GND ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|b_full, ;
; ; due to stuck port data_in ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|b_non_empty, ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[9], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[8], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[7], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[6], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[5], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[4], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[3], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[2], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[1], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|cntr_cpb:rd_ptr_count|counter_reg_bit[0], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[9], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[8], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[7], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[6], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[5], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[4], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[3], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[2], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[1], ;
; ; ; scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|a_fefifo_jaf:fifo_state|cntr_op7:count_usedw|counter_reg_bit[0] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[15] ; Stuck at GND ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[14], ;
; ; due to stuck port data_in ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[13] ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 3072 ;
; Number of registers using Synchronous Clear ; 52 ;
; Number of registers using Synchronous Load ; 119 ;
; Number of registers using Asynchronous Clear ; 1211 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 1374 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; TRDY_Delay ; 2 ;
; ConfReg[1][0] ; 1 ;
; ConfReg[1][1] ; 1 ;
; ConfReg[1][2] ; 1 ;
; ConfReg[15][8] ; 2 ;
; sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|tdo ; 1 ;
; sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[2] ; 2 ;
; sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[1] ; 3 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11] ; 1 ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0] ; 1 ;
; Total number of inverted registers = 20 ; ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 36 bits ; 72 LEs ; 0 LEs ; 72 LEs ; Yes ; |PCI|ParGenData[21] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |PCI|IntReg_Clr[3] ;
; 3:1 ; 7 bits ; 14 LEs ; 0 LEs ; 14 LEs ; Yes ; |PCI|ConfReg[15][14] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[3][9] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[1][13] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[15][17] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[3][18] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[1][18] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[15][25] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[3][29] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[1][29] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[15][0] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |PCI|ConfReg[3][3] ;
; 3:1 ; 5 bits ; 10 LEs ; 0 LEs ; 10 LEs ; Yes ; |PCI|ConfReg[1][3] ;
; 4:1 ; 23 bits ; 46 LEs ; 23 LEs ; 23 LEs ; Yes ; |PCI|SpiMaster:UUT_AD9642_SPI1|CounterReg[17] ;
; 4:1 ; 23 bits ; 46 LEs ; 23 LEs ; 23 LEs ; Yes ; |PCI|SpiMaster:UUT_AD9642_SPI2|CounterReg[15] ;
; 4:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |PCI|DMA_Count[8] ;
; 4:1 ; 30 bits ; 60 LEs ; 30 LEs ; 30 LEs ; Yes ; |PCI|DMA_PCIAddress[30] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |PCI|Devsel_Counter[3] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |PCI|SpiMaster:UUT_AD9642_SPI1|SendData_Reg[22] ;
; 5:1 ; 21 bits ; 63 LEs ; 21 LEs ; 42 LEs ; Yes ; |PCI|SpiMaster:UUT_AD9642_SPI1|SendData_Reg[6] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |PCI|SpiMaster:UUT_AD9642_SPI2|SendData_Reg[21] ;
; 5:1 ; 21 bits ; 63 LEs ; 21 LEs ; 42 LEs ; Yes ; |PCI|SpiMaster:UUT_AD9642_SPI2|SendData_Reg[15] ;
; 12:1 ; 2 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |PCI|Curr_State_Dma[1] ;
; 9:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |PCI|STATUS[1] ;
; 3:1 ; 3 bits ; 6 LEs ; 0 LEs ; 6 LEs ; Yes ; |PCI|ConfReg[1][1] ;
; 22:1 ; 16 bits ; 224 LEs ; 128 LEs ; 96 LEs ; Yes ; |PCI|AD[25]~reg0 ;
; 22:1 ; 2 bits ; 28 LEs ; 16 LEs ; 12 LEs ; Yes ; |PCI|AD[15]~reg0 ;
; 22:1 ; 3 bits ; 42 LEs ; 24 LEs ; 18 LEs ; Yes ; |PCI|AD[13]~reg0 ;
; 82:1 ; 2 bits ; 108 LEs ; 20 LEs ; 88 LEs ; Yes ; |PCI|AD[8]~reg0 ;
; 82:1 ; 2 bits ; 108 LEs ; 18 LEs ; 90 LEs ; Yes ; |PCI|AD[4]~reg0 ;
; 82:1 ; 2 bits ; 108 LEs ; 20 LEs ; 88 LEs ; Yes ; |PCI|AD[7]~reg0 ;
; 82:1 ; 2 bits ; 108 LEs ; 20 LEs ; 88 LEs ; Yes ; |PCI|AD[2]~reg0 ;
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[13] ;
; 3:1 ; 13 bits ; 26 LEs ; 13 LEs ; 13 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[3] ;
; 3:1 ; 13 bits ; 26 LEs ; 13 LEs ; 13 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[1] ;
; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[28] ;
; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[1] ;
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[0] ;
; 12:1 ; 4 bits ; 32 LEs ; 24 LEs ; 8 LEs ; Yes ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1] ;
; 3:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |PCI|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_minor_ver_reg[1] ;
; 5:1 ; 10 bits ; 30 LEs ; 10 LEs ; 20 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][4] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[3] ;
; 6:1 ; 9 bits ; 36 LEs ; 9 LEs ; 27 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[6] ;
; 6:1 ; 10 bits ; 40 LEs ; 10 LEs ; 30 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|shadow_irf_reg[1][4] ;
; 34:1 ; 4 bits ; 88 LEs ; 56 LEs ; 32 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_reg[0] ;
; 20:1 ; 4 bits ; 52 LEs ; 32 LEs ; 20 LEs ; Yes ; |PCI|sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:instrumentation_fabric|alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|WORD_SR[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------+
; Source assignments for Top-level Entity: |PCI ;
+-------------------+-------+------+-----------------------+
; Assignment ; Value ; From ; To ;
+-------------------+-------+------+-----------------------+
; PRESERVE_REGISTER ; on ; - ; STATUS[1] ;
; PRESERVE_REGISTER ; on ; - ; STATUS[0] ;
; PRESERVE_REGISTER ; on ; - ; ADDRESS[7] ;
; PRESERVE_REGISTER ; on ; - ; ADDRESS[6] ;
; PRESERVE_REGISTER ; on ; - ; ADDRESS[5] ;
; PRESERVE_REGISTER ; on ; - ; ADDRESS[4] ;
; PRESERVE_REGISTER ; on ; - ; ADDRESS[3] ;
; PRESERVE_REGISTER ; on ; - ; ADDRESS[2] ;
; PRESERVE_REGISTER ; on ; - ; ConfCS ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[31] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[30] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[29] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[28] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[27] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[26] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[25] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[24] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[23] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[22] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[21] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[20] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[19] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[18] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[17] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[16] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[15] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[14] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[13] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[12] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[11] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[10] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[9] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[8] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[7] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[6] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[5] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[4] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[3] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[2] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[1] ;
; PRESERVE_REGISTER ; on ; - ; PCI_Config_WrData[0] ;
; PRESERVE_REGISTER ; on ; - ; Curr_State_Dma[2] ;
; PRESERVE_REGISTER ; on ; - ; Curr_State_Dma[1] ;
; PRESERVE_REGISTER ; on ; - ; Curr_State_Dma[0] ;
+-------------------+-------+------+-----------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for scfifo:UUT_DmaDesc_FIFO|scfifo_h5m:auto_generated|a_dpfifo_ujt:dpfifo|dpram_rms:FIFOram|altsyncram_c6k1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for scfifo:UUT_DmaRd_FIFO1|scfifo_bjl:auto_generated|a_dpfifo_o1t:dpfifo|dpram_tms:FIFOram|altsyncram_a6k1:altsyncram1 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for scfifo:UUT_DmaRd_FIFO2|scfifo_hsk:auto_generated|a_dpfifo_ffs:dpfifo|dpram_tms:FIFOram|altsyncram_a6k1:altsyncram1 ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------------------+
+-------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0 ;
+-----------------+-------+------+----------------------+
; Assignment ; Value ; From ; To ;
+-----------------+-------+------+----------------------+
; MESSAGE_DISABLE ; 13410 ; - ; - ;
+-----------------+-------+------+----------------------+
+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: scfifo:UUT_DmaDesc_FIFO ;
+-------------------------+--------------+-----------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+--------------+-----------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; lpm_width ; 32 ; Signed Integer ;
; LPM_NUMWORDS ; 1024 ; Signed Integer ;
; LPM_WIDTHU ; 10 ; Signed Integer ;
; LPM_SHOWAHEAD ; OFF ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; ALMOST_FULL_VALUE ; 0 ; Untyped ;
; ALMOST_EMPTY_VALUE ; 0 ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; scfifo_h5m ; Untyped ;
+-------------------------+--------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: scfifo:UUT_DmaRd_FIFO1 ;
+-------------------------+--------------+----------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+--------------+----------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; lpm_width ; 14 ; Signed Integer ;
; LPM_NUMWORDS ; 2048 ; Signed Integer ;
; LPM_WIDTHU ; 11 ; Signed Integer ;
; LPM_SHOWAHEAD ; OFF ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; ALMOST_FULL_VALUE ; 0 ; Untyped ;
; ALMOST_EMPTY_VALUE ; 0 ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; scfifo_bjl ; Untyped ;
+-------------------------+--------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: scfifo:UUT_DmaRd_FIFO2 ;
+-------------------------+--------------+----------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+--------------+----------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; lpm_width ; 14 ; Signed Integer ;
; LPM_NUMWORDS ; 2048 ; Signed Integer ;
; LPM_WIDTHU ; 11 ; Signed Integer ;
; LPM_SHOWAHEAD ; OFF ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; ALMOST_FULL_VALUE ; 0 ; Untyped ;
; ALMOST_EMPTY_VALUE ; 0 ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; CBXI_PARAMETER ; scfifo_hsk ; Untyped ;
+-------------------------+--------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".