GitHub - jpy794/very-simple-cpu: A synthesizable 5-stage pipeline RISC-V CPU for COD course of USTC.

Name	Name	Last commit message	Last commit date
Latest commit jpy794 upload src Apr 28, 2022 492d9b9 · Apr 28, 2022 History 1 Commit
itf	itf	upload src	Apr 28, 2022
perip	perip	upload src	Apr 28, 2022
pkg	pkg	upload src	Apr 28, 2022
tb	tb	upload src	Apr 28, 2022
util	util	upload src	Apr 28, 2022
Alu.sv	Alu.sv	upload src	Apr 28, 2022
Branch.sv	Branch.sv	upload src	Apr 28, 2022
BusCtrl.sv	BusCtrl.sv	upload src	Apr 28, 2022
Cpu.sv	Cpu.sv	upload src	Apr 28, 2022
DataCache.sv	DataCache.sv	upload src	Apr 28, 2022
Decoder.sv	Decoder.sv	upload src	Apr 28, 2022
InsCache.sv	InsCache.sv	upload src	Apr 28, 2022
Register.sv	Register.sv	upload src	Apr 28, 2022
Top.sv	Top.sv	upload src	Apr 28, 2022
tb_Top.sv	tb_Top.sv	upload src	Apr 28, 2022